2 * Copyright © 2010 Daniel Vetter
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <drm/i915_drm.h>
28 #include "i915_trace.h"
29 #include "intel_drv.h"
31 typedef uint32_t gtt_pte_t
;
34 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
36 #define GEN6_PDE_VALID (1 << 0)
37 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
38 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
40 #define GEN6_PTE_VALID (1 << 0)
41 #define GEN6_PTE_UNCACHED (1 << 1)
42 #define HSW_PTE_UNCACHED (0)
43 #define GEN6_PTE_CACHE_LLC (2 << 1)
44 #define GEN6_PTE_CACHE_LLC_MLC (3 << 1)
45 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
47 static inline gtt_pte_t
gen6_pte_encode(struct drm_device
*dev
,
49 enum i915_cache_level level
)
51 gtt_pte_t pte
= GEN6_PTE_VALID
;
52 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
55 case I915_CACHE_LLC_MLC
:
56 /* Haswell doesn't set L3 this way */
58 pte
|= GEN6_PTE_CACHE_LLC
;
60 pte
|= GEN6_PTE_CACHE_LLC_MLC
;
63 pte
|= GEN6_PTE_CACHE_LLC
;
67 pte
|= HSW_PTE_UNCACHED
;
69 pte
|= GEN6_PTE_UNCACHED
;
79 /* PPGTT support for Sandybdrige/Gen6 and later */
80 static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt
*ppgtt
,
85 gtt_pte_t scratch_pte
;
86 unsigned act_pd
= first_entry
/ I915_PPGTT_PT_ENTRIES
;
87 unsigned first_pte
= first_entry
% I915_PPGTT_PT_ENTRIES
;
90 scratch_pte
= gen6_pte_encode(ppgtt
->dev
,
91 ppgtt
->scratch_page_dma_addr
,
95 last_pte
= first_pte
+ num_entries
;
96 if (last_pte
> I915_PPGTT_PT_ENTRIES
)
97 last_pte
= I915_PPGTT_PT_ENTRIES
;
99 pt_vaddr
= kmap_atomic(ppgtt
->pt_pages
[act_pd
]);
101 for (i
= first_pte
; i
< last_pte
; i
++)
102 pt_vaddr
[i
] = scratch_pte
;
104 kunmap_atomic(pt_vaddr
);
106 num_entries
-= last_pte
- first_pte
;
112 static void gen6_ppgtt_insert_entries(struct i915_hw_ppgtt
*ppgtt
,
113 struct sg_table
*pages
,
114 unsigned first_entry
,
115 enum i915_cache_level cache_level
)
118 unsigned act_pd
= first_entry
/ I915_PPGTT_PT_ENTRIES
;
119 unsigned first_pte
= first_entry
% I915_PPGTT_PT_ENTRIES
;
120 unsigned i
, j
, m
, segment_len
;
121 dma_addr_t page_addr
;
122 struct scatterlist
*sg
;
124 /* init sg walking */
127 segment_len
= sg_dma_len(sg
) >> PAGE_SHIFT
;
130 while (i
< pages
->nents
) {
131 pt_vaddr
= kmap_atomic(ppgtt
->pt_pages
[act_pd
]);
133 for (j
= first_pte
; j
< I915_PPGTT_PT_ENTRIES
; j
++) {
134 page_addr
= sg_dma_address(sg
) + (m
<< PAGE_SHIFT
);
135 pt_vaddr
[j
] = gen6_pte_encode(ppgtt
->dev
, page_addr
,
138 /* grab the next page */
139 if (++m
== segment_len
) {
140 if (++i
== pages
->nents
)
144 segment_len
= sg_dma_len(sg
) >> PAGE_SHIFT
;
149 kunmap_atomic(pt_vaddr
);
156 static void gen6_ppgtt_cleanup(struct i915_hw_ppgtt
*ppgtt
)
160 if (ppgtt
->pt_dma_addr
) {
161 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++)
162 pci_unmap_page(ppgtt
->dev
->pdev
,
163 ppgtt
->pt_dma_addr
[i
],
164 4096, PCI_DMA_BIDIRECTIONAL
);
167 kfree(ppgtt
->pt_dma_addr
);
168 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++)
169 __free_page(ppgtt
->pt_pages
[i
]);
170 kfree(ppgtt
->pt_pages
);
174 static int gen6_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
176 struct drm_device
*dev
= ppgtt
->dev
;
177 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
178 unsigned first_pd_entry_in_global_pt
;
182 /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
183 * entries. For aliasing ppgtt support we just steal them at the end for
185 first_pd_entry_in_global_pt
= dev_priv
->mm
.gtt
->gtt_total_entries
- I915_PPGTT_PD_ENTRIES
;
187 ppgtt
->num_pd_entries
= I915_PPGTT_PD_ENTRIES
;
188 ppgtt
->clear_range
= gen6_ppgtt_clear_range
;
189 ppgtt
->insert_entries
= gen6_ppgtt_insert_entries
;
190 ppgtt
->cleanup
= gen6_ppgtt_cleanup
;
191 ppgtt
->pt_pages
= kzalloc(sizeof(struct page
*)*ppgtt
->num_pd_entries
,
193 if (!ppgtt
->pt_pages
)
196 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
197 ppgtt
->pt_pages
[i
] = alloc_page(GFP_KERNEL
);
198 if (!ppgtt
->pt_pages
[i
])
202 ppgtt
->pt_dma_addr
= kzalloc(sizeof(dma_addr_t
) *ppgtt
->num_pd_entries
,
204 if (!ppgtt
->pt_dma_addr
)
207 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
210 pt_addr
= pci_map_page(dev
->pdev
, ppgtt
->pt_pages
[i
], 0, 4096,
211 PCI_DMA_BIDIRECTIONAL
);
213 if (pci_dma_mapping_error(dev
->pdev
, pt_addr
)) {
218 ppgtt
->pt_dma_addr
[i
] = pt_addr
;
221 ppgtt
->scratch_page_dma_addr
= dev_priv
->gtt
.scratch_page_dma
;
223 ppgtt
->clear_range(ppgtt
, 0,
224 ppgtt
->num_pd_entries
*I915_PPGTT_PT_ENTRIES
);
226 ppgtt
->pd_offset
= (first_pd_entry_in_global_pt
)*sizeof(gtt_pte_t
);
231 if (ppgtt
->pt_dma_addr
) {
232 for (i
--; i
>= 0; i
--)
233 pci_unmap_page(dev
->pdev
, ppgtt
->pt_dma_addr
[i
],
234 4096, PCI_DMA_BIDIRECTIONAL
);
237 kfree(ppgtt
->pt_dma_addr
);
238 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
239 if (ppgtt
->pt_pages
[i
])
240 __free_page(ppgtt
->pt_pages
[i
]);
242 kfree(ppgtt
->pt_pages
);
247 static int i915_gem_init_aliasing_ppgtt(struct drm_device
*dev
)
249 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
250 struct i915_hw_ppgtt
*ppgtt
;
253 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
259 ret
= gen6_ppgtt_init(ppgtt
);
263 dev_priv
->mm
.aliasing_ppgtt
= ppgtt
;
268 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device
*dev
)
270 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
271 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
276 ppgtt
->cleanup(ppgtt
);
279 void i915_ppgtt_bind_object(struct i915_hw_ppgtt
*ppgtt
,
280 struct drm_i915_gem_object
*obj
,
281 enum i915_cache_level cache_level
)
283 ppgtt
->insert_entries(ppgtt
, obj
->pages
,
284 obj
->gtt_space
->start
>> PAGE_SHIFT
,
288 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt
*ppgtt
,
289 struct drm_i915_gem_object
*obj
)
291 ppgtt
->clear_range(ppgtt
,
292 obj
->gtt_space
->start
>> PAGE_SHIFT
,
293 obj
->base
.size
>> PAGE_SHIFT
);
296 void i915_gem_init_ppgtt(struct drm_device
*dev
)
298 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
300 struct intel_ring_buffer
*ring
;
301 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
302 gtt_pte_t __iomem
*pd_addr
;
306 if (!dev_priv
->mm
.aliasing_ppgtt
)
310 pd_addr
= (gtt_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ ppgtt
->pd_offset
/sizeof(gtt_pte_t
);
311 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
314 pt_addr
= ppgtt
->pt_dma_addr
[i
];
315 pd_entry
= GEN6_PDE_ADDR_ENCODE(pt_addr
);
316 pd_entry
|= GEN6_PDE_VALID
;
318 writel(pd_entry
, pd_addr
+ i
);
322 pd_offset
= ppgtt
->pd_offset
;
323 pd_offset
/= 64; /* in cachelines, */
326 if (INTEL_INFO(dev
)->gen
== 6) {
327 uint32_t ecochk
, gab_ctl
, ecobits
;
329 ecobits
= I915_READ(GAC_ECO_BITS
);
330 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_PPGTT_CACHE64B
);
332 gab_ctl
= I915_READ(GAB_CTL
);
333 I915_WRITE(GAB_CTL
, gab_ctl
| GAB_CTL_CONT_AFTER_PAGEFAULT
);
335 ecochk
= I915_READ(GAM_ECOCHK
);
336 I915_WRITE(GAM_ECOCHK
, ecochk
| ECOCHK_SNB_BIT
|
337 ECOCHK_PPGTT_CACHE64B
);
338 I915_WRITE(GFX_MODE
, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
339 } else if (INTEL_INFO(dev
)->gen
>= 7) {
340 I915_WRITE(GAM_ECOCHK
, ECOCHK_PPGTT_CACHE64B
);
341 /* GFX_MODE is per-ring on gen7+ */
344 for_each_ring(ring
, dev_priv
, i
) {
345 if (INTEL_INFO(dev
)->gen
>= 7)
346 I915_WRITE(RING_MODE_GEN7(ring
),
347 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
349 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
350 I915_WRITE(RING_PP_DIR_BASE(ring
), pd_offset
);
354 extern int intel_iommu_gfx_mapped
;
355 /* Certain Gen5 chipsets require require idling the GPU before
356 * unmapping anything from the GTT when VT-d is enabled.
358 static inline bool needs_idle_maps(struct drm_device
*dev
)
360 #ifdef CONFIG_INTEL_IOMMU
361 /* Query intel_iommu to see if we need the workaround. Presumably that
364 if (IS_GEN5(dev
) && IS_MOBILE(dev
) && intel_iommu_gfx_mapped
)
370 static bool do_idling(struct drm_i915_private
*dev_priv
)
372 bool ret
= dev_priv
->mm
.interruptible
;
374 if (unlikely(dev_priv
->gtt
.do_idle_maps
)) {
375 dev_priv
->mm
.interruptible
= false;
376 if (i915_gpu_idle(dev_priv
->dev
)) {
377 DRM_ERROR("Couldn't idle GPU\n");
378 /* Wait a bit, in hopes it avoids the hang */
386 static void undo_idling(struct drm_i915_private
*dev_priv
, bool interruptible
)
388 if (unlikely(dev_priv
->gtt
.do_idle_maps
))
389 dev_priv
->mm
.interruptible
= interruptible
;
392 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
)
394 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
395 struct drm_i915_gem_object
*obj
;
397 /* First fill our portion of the GTT with scratch pages */
398 dev_priv
->gtt
.gtt_clear_range(dev
, dev_priv
->gtt
.start
/ PAGE_SIZE
,
399 dev_priv
->gtt
.total
/ PAGE_SIZE
);
401 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, gtt_list
) {
402 i915_gem_clflush_object(obj
);
403 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
406 i915_gem_chipset_flush(dev
);
409 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
)
411 if (obj
->has_dma_mapping
)
414 if (!dma_map_sg(&obj
->base
.dev
->pdev
->dev
,
415 obj
->pages
->sgl
, obj
->pages
->nents
,
416 PCI_DMA_BIDIRECTIONAL
))
423 * Binds an object into the global gtt with the specified cache level. The object
424 * will be accessible to the GPU via commands whose operands reference offsets
425 * within the global GTT as well as accessible by the GPU through the GMADR
426 * mapped BAR (dev_priv->mm.gtt->gtt).
428 static void gen6_ggtt_insert_entries(struct drm_device
*dev
,
430 unsigned int first_entry
,
431 enum i915_cache_level level
)
433 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
434 struct scatterlist
*sg
= st
->sgl
;
435 gtt_pte_t __iomem
*gtt_entries
=
436 (gtt_pte_t __iomem
*)dev_priv
->gtt
.gsm
+ first_entry
;
438 unsigned int len
, m
= 0;
441 for_each_sg(st
->sgl
, sg
, st
->nents
, unused
) {
442 len
= sg_dma_len(sg
) >> PAGE_SHIFT
;
443 for (m
= 0; m
< len
; m
++) {
444 addr
= sg_dma_address(sg
) + (m
<< PAGE_SHIFT
);
445 iowrite32(gen6_pte_encode(dev
, addr
, level
),
451 /* XXX: This serves as a posting read to make sure that the PTE has
452 * actually been updated. There is some concern that even though
453 * registers and PTEs are within the same BAR that they are potentially
454 * of NUMA access patterns. Therefore, even with the way we assume
455 * hardware should work, we must keep this posting read for paranoia.
458 WARN_ON(readl(>t_entries
[i
-1])
459 != gen6_pte_encode(dev
, addr
, level
));
461 /* This next bit makes the above posting read even more important. We
462 * want to flush the TLBs only after we're certain all the PTE updates
465 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
466 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
469 static void gen6_ggtt_clear_range(struct drm_device
*dev
,
470 unsigned int first_entry
,
471 unsigned int num_entries
)
473 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
474 gtt_pte_t scratch_pte
;
475 gtt_pte_t __iomem
*gtt_base
= (gtt_pte_t __iomem
*) dev_priv
->gtt
.gsm
+ first_entry
;
476 const int max_entries
= dev_priv
->mm
.gtt
->gtt_total_entries
- first_entry
;
479 if (WARN(num_entries
> max_entries
,
480 "First entry = %d; Num entries = %d (max=%d)\n",
481 first_entry
, num_entries
, max_entries
))
482 num_entries
= max_entries
;
484 scratch_pte
= gen6_pte_encode(dev
, dev_priv
->gtt
.scratch_page_dma
,
486 for (i
= 0; i
< num_entries
; i
++)
487 iowrite32(scratch_pte
, >t_base
[i
]);
492 static void i915_ggtt_insert_entries(struct drm_device
*dev
,
494 unsigned int pg_start
,
495 enum i915_cache_level cache_level
)
497 unsigned int flags
= (cache_level
== I915_CACHE_NONE
) ?
498 AGP_USER_MEMORY
: AGP_USER_CACHED_MEMORY
;
500 intel_gtt_insert_sg_entries(st
, pg_start
, flags
);
504 static void i915_ggtt_clear_range(struct drm_device
*dev
,
505 unsigned int first_entry
,
506 unsigned int num_entries
)
508 intel_gtt_clear_range(first_entry
, num_entries
);
512 void i915_gem_gtt_bind_object(struct drm_i915_gem_object
*obj
,
513 enum i915_cache_level cache_level
)
515 struct drm_device
*dev
= obj
->base
.dev
;
516 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
518 dev_priv
->gtt
.gtt_insert_entries(dev
, obj
->pages
,
519 obj
->gtt_space
->start
>> PAGE_SHIFT
,
522 obj
->has_global_gtt_mapping
= 1;
525 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object
*obj
)
527 struct drm_device
*dev
= obj
->base
.dev
;
528 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
530 dev_priv
->gtt
.gtt_clear_range(obj
->base
.dev
,
531 obj
->gtt_space
->start
>> PAGE_SHIFT
,
532 obj
->base
.size
>> PAGE_SHIFT
);
534 obj
->has_global_gtt_mapping
= 0;
537 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
)
539 struct drm_device
*dev
= obj
->base
.dev
;
540 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
543 interruptible
= do_idling(dev_priv
);
545 if (!obj
->has_dma_mapping
)
546 dma_unmap_sg(&dev
->pdev
->dev
,
547 obj
->pages
->sgl
, obj
->pages
->nents
,
548 PCI_DMA_BIDIRECTIONAL
);
550 undo_idling(dev_priv
, interruptible
);
553 static void i915_gtt_color_adjust(struct drm_mm_node
*node
,
555 unsigned long *start
,
558 if (node
->color
!= color
)
561 if (!list_empty(&node
->node_list
)) {
562 node
= list_entry(node
->node_list
.next
,
565 if (node
->allocated
&& node
->color
!= color
)
570 void i915_gem_setup_global_gtt(struct drm_device
*dev
,
572 unsigned long mappable_end
,
575 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
576 struct drm_mm_node
*entry
;
577 struct drm_i915_gem_object
*obj
;
578 unsigned long hole_start
, hole_end
;
580 BUG_ON(mappable_end
> end
);
582 /* Subtract the guard page ... */
583 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
, end
- start
- PAGE_SIZE
);
585 dev_priv
->mm
.gtt_space
.color_adjust
= i915_gtt_color_adjust
;
587 /* Mark any preallocated objects as occupied */
588 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, gtt_list
) {
589 DRM_DEBUG_KMS("reserving preallocated space: %x + %zx\n",
590 obj
->gtt_offset
, obj
->base
.size
);
592 BUG_ON(obj
->gtt_space
!= I915_GTT_RESERVED
);
593 obj
->gtt_space
= drm_mm_create_block(&dev_priv
->mm
.gtt_space
,
597 obj
->has_global_gtt_mapping
= 1;
600 dev_priv
->gtt
.start
= start
;
601 dev_priv
->gtt
.total
= end
- start
;
603 /* Clear any non-preallocated blocks */
604 drm_mm_for_each_hole(entry
, &dev_priv
->mm
.gtt_space
,
605 hole_start
, hole_end
) {
606 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
607 hole_start
, hole_end
);
608 dev_priv
->gtt
.gtt_clear_range(dev
, hole_start
/ PAGE_SIZE
,
609 (hole_end
-hole_start
) / PAGE_SIZE
);
612 /* And finally clear the reserved guard page */
613 dev_priv
->gtt
.gtt_clear_range(dev
, end
/ PAGE_SIZE
- 1, 1);
617 intel_enable_ppgtt(struct drm_device
*dev
)
619 if (i915_enable_ppgtt
>= 0)
620 return i915_enable_ppgtt
;
622 #ifdef CONFIG_INTEL_IOMMU
623 /* Disable ppgtt on SNB if VT-d is on. */
624 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
)
631 void i915_gem_init_global_gtt(struct drm_device
*dev
)
633 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
634 unsigned long gtt_size
, mappable_size
;
637 gtt_size
= dev_priv
->mm
.gtt
->gtt_total_entries
<< PAGE_SHIFT
;
638 mappable_size
= dev_priv
->gtt
.mappable_end
;
640 if (intel_enable_ppgtt(dev
) && HAS_ALIASING_PPGTT(dev
)) {
641 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
642 * aperture accordingly when using aliasing ppgtt. */
643 gtt_size
-= I915_PPGTT_PD_ENTRIES
*PAGE_SIZE
;
645 i915_gem_setup_global_gtt(dev
, 0, mappable_size
, gtt_size
);
647 ret
= i915_gem_init_aliasing_ppgtt(dev
);
649 mutex_unlock(&dev
->struct_mutex
);
653 /* Let GEM Manage all of the aperture.
655 * However, leave one page at the end still bound to the scratch
656 * page. There are a number of places where the hardware
657 * apparently prefetches past the end of the object, and we've
658 * seen multiple hangs with the GPU head pointer stuck in a
659 * batchbuffer bound at the last page of the aperture. One page
660 * should be enough to keep any prefetching inside of the
663 i915_gem_setup_global_gtt(dev
, 0, mappable_size
, gtt_size
);
667 static int setup_scratch_page(struct drm_device
*dev
)
669 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
673 page
= alloc_page(GFP_KERNEL
| GFP_DMA32
| __GFP_ZERO
);
677 set_pages_uc(page
, 1);
679 #ifdef CONFIG_INTEL_IOMMU
680 dma_addr
= pci_map_page(dev
->pdev
, page
, 0, PAGE_SIZE
,
681 PCI_DMA_BIDIRECTIONAL
);
682 if (pci_dma_mapping_error(dev
->pdev
, dma_addr
))
685 dma_addr
= page_to_phys(page
);
687 dev_priv
->gtt
.scratch_page
= page
;
688 dev_priv
->gtt
.scratch_page_dma
= dma_addr
;
693 static void teardown_scratch_page(struct drm_device
*dev
)
695 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
696 set_pages_wb(dev_priv
->gtt
.scratch_page
, 1);
697 pci_unmap_page(dev
->pdev
, dev_priv
->gtt
.scratch_page_dma
,
698 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
699 put_page(dev_priv
->gtt
.scratch_page
);
700 __free_page(dev_priv
->gtt
.scratch_page
);
703 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl
)
705 snb_gmch_ctl
>>= SNB_GMCH_GGMS_SHIFT
;
706 snb_gmch_ctl
&= SNB_GMCH_GGMS_MASK
;
707 return snb_gmch_ctl
<< 20;
710 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl
)
712 snb_gmch_ctl
>>= SNB_GMCH_GMS_SHIFT
;
713 snb_gmch_ctl
&= SNB_GMCH_GMS_MASK
;
714 return snb_gmch_ctl
<< 25; /* 32 MB units */
717 static inline size_t gen7_get_stolen_size(u16 snb_gmch_ctl
)
719 static const int stolen_decoder
[] = {
720 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352};
721 snb_gmch_ctl
>>= IVB_GMCH_GMS_SHIFT
;
722 snb_gmch_ctl
&= IVB_GMCH_GMS_MASK
;
723 return stolen_decoder
[snb_gmch_ctl
] << 20;
726 static int gen6_gmch_probe(struct drm_device
*dev
,
730 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
731 phys_addr_t gtt_bus_addr
;
732 unsigned int gtt_size
;
736 /* 64/512MB is the current min/max we actually know of, but this is just
737 * a coarse sanity check.
739 if ((dev_priv
->gtt
.mappable_end
< (64<<20) ||
740 (dev_priv
->gtt
.mappable_end
> (512<<20)))) {
741 DRM_ERROR("Unknown GMADR size (%lx)\n",
742 dev_priv
->gtt
.mappable_end
);
746 if (!pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(40)))
747 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(40));
748 pci_read_config_word(dev
->pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
749 gtt_size
= gen6_get_total_gtt_size(snb_gmch_ctl
);
752 *stolen
= gen7_get_stolen_size(snb_gmch_ctl
);
754 *stolen
= gen6_get_stolen_size(snb_gmch_ctl
);
756 *gtt_total
= (gtt_size
/ sizeof(gtt_pte_t
)) << PAGE_SHIFT
;
758 /* For GEN6+ the PTEs for the ggtt live at 2MB + BAR0 */
759 gtt_bus_addr
= pci_resource_start(dev
->pdev
, 0) + (2<<20);
760 dev_priv
->gtt
.gsm
= ioremap_wc(gtt_bus_addr
, gtt_size
);
761 if (!dev_priv
->gtt
.gsm
) {
762 DRM_ERROR("Failed to map the gtt page table\n");
766 ret
= setup_scratch_page(dev
);
768 DRM_ERROR("Scratch setup failed\n");
770 dev_priv
->gtt
.gtt_clear_range
= gen6_ggtt_clear_range
;
771 dev_priv
->gtt
.gtt_insert_entries
= gen6_ggtt_insert_entries
;
776 void gen6_gmch_remove(struct drm_device
*dev
)
778 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
779 iounmap(dev_priv
->gtt
.gsm
);
780 teardown_scratch_page(dev_priv
->dev
);
781 kfree(dev_priv
->mm
.gtt
);
784 static int i915_gmch_probe(struct drm_device
*dev
,
788 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
791 /* This is a temporary hack to make the code cleaner in
792 * i915_gem_gtt_init. I promise it will go away very shortly. */
793 kfree(dev_priv
->mm
.gtt
);
795 ret
= intel_gmch_probe(dev_priv
->bridge_dev
, dev_priv
->dev
->pdev
, NULL
);
797 DRM_ERROR("failed to set up gmch\n");
801 dev_priv
->mm
.gtt
= intel_gtt_get();
802 if (!dev_priv
->mm
.gtt
) {
803 DRM_ERROR("Failed to initialize GTT\n");
808 dev_priv
->gtt
.do_idle_maps
= needs_idle_maps(dev_priv
->dev
);
809 dev_priv
->gtt
.gtt_clear_range
= i915_ggtt_clear_range
;
810 dev_priv
->gtt
.gtt_insert_entries
= i915_ggtt_insert_entries
;
815 static void i915_gmch_remove(struct drm_device
*dev
)
820 int i915_gem_gtt_init(struct drm_device
*dev
)
822 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
823 struct i915_gtt
*gtt
= &dev_priv
->gtt
;
824 unsigned long gtt_size
;
827 dev_priv
->mm
.gtt
= kzalloc(sizeof(*dev_priv
->mm
.gtt
), GFP_KERNEL
);
828 if (!dev_priv
->mm
.gtt
)
831 gtt
->mappable_base
= pci_resource_start(dev
->pdev
, 2);
832 gtt
->mappable_end
= pci_resource_len(dev
->pdev
, 2);
834 if (INTEL_INFO(dev
)->gen
<= 5) {
835 dev_priv
->gtt
.gtt_probe
= i915_gmch_probe
;
836 dev_priv
->gtt
.gtt_remove
= i915_gmch_remove
;
838 dev_priv
->gtt
.gtt_probe
= gen6_gmch_probe
;
839 dev_priv
->gtt
.gtt_remove
= gen6_gmch_remove
;
842 ret
= dev_priv
->gtt
.gtt_probe(dev
, &dev_priv
->gtt
.total
,
843 &dev_priv
->gtt
.stolen_size
);
845 kfree(dev_priv
->mm
.gtt
);
849 dev_priv
->mm
.gtt
->gtt_total_entries
= dev_priv
->gtt
.total
>> PAGE_SHIFT
;
850 dev_priv
->mm
.gtt
->stolen_size
= dev_priv
->gtt
.stolen_size
;
852 gtt_size
= (dev_priv
->gtt
.total
>> PAGE_SHIFT
) * sizeof(gtt_pte_t
);
854 /* GMADR is the PCI mmio aperture into the global GTT. */
855 DRM_INFO("Memory usable by graphics device = %zdM\n",
856 dev_priv
->gtt
.total
>> 20);
857 DRM_DEBUG_DRIVER("GMADR size = %ldM\n",
858 dev_priv
->gtt
.mappable_end
>> 20);
859 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n",
860 dev_priv
->gtt
.stolen_size
>> 20);