projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
drm/i915: Fix BDW PPGTT error path
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem_gtt.c
1 /*
2 * Copyright © 2010 Daniel Vetter
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25 #include <drm/drmP.h>
26 #include <drm/i915_drm.h>
27 #include "i915_drv.h"
28 #include "i915_trace.h"
29 #include "intel_drv.h"
30
31 #define GEN6_PPGTT_PD_ENTRIES 512
32 #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t))
33 typedef uint64_t gen8_gtt_pte_t;
34 typedef gen8_gtt_pte_t gen8_ppgtt_pde_t;
35
36 /* PPGTT stuff */
37 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
38 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0))
39
40 #define GEN6_PDE_VALID (1 << 0)
41 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
42 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
43
44 #define GEN6_PTE_VALID (1 << 0)
45 #define GEN6_PTE_UNCACHED (1 << 1)
46 #define HSW_PTE_UNCACHED (0)
47 #define GEN6_PTE_CACHE_LLC (2 << 1)
48 #define GEN7_PTE_CACHE_L3_LLC (3 << 1)
49 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
50 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr)
51
52 /* Cacheability Control is a 4-bit value. The low three bits are stored in *
53 * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
54 */
55 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \
56 (((bits) & 0x8) << (11 - 3)))
57 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2)
58 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3)
59 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb)
60 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6)
61
62 #define GEN8_PTES_PER_PAGE (PAGE_SIZE / sizeof(gen8_gtt_pte_t))
63 #define GEN8_PDES_PER_PAGE (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t))
64 #define GEN8_LEGACY_PDPS 4
65
66 #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD)
67 #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */
68 #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */
69 #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */
70
71 static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
72 enum i915_cache_level level,
73 bool valid)
74 {
75 gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
76 pte |= addr;
77 if (level != I915_CACHE_NONE)
78 pte |= PPAT_CACHED_INDEX;
79 else
80 pte |= PPAT_UNCACHED_INDEX;
81 return pte;
82 }
83
84 static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev,
85 dma_addr_t addr,
86 enum i915_cache_level level)
87 {
88 gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
89 pde |= addr;
90 if (level != I915_CACHE_NONE)
91 pde |= PPAT_CACHED_PDE_INDEX;
92 else
93 pde |= PPAT_UNCACHED_INDEX;
94 return pde;
95 }
96
97 static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
98 enum i915_cache_level level,
99 bool valid)
100 {
101 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
102 pte |= GEN6_PTE_ADDR_ENCODE(addr);
103
104 switch (level) {
105 case I915_CACHE_L3_LLC:
106 case I915_CACHE_LLC:
107 pte |= GEN6_PTE_CACHE_LLC;
108 break;
109 case I915_CACHE_NONE:
110 pte |= GEN6_PTE_UNCACHED;
111 break;
112 default:
113 WARN_ON(1);
114 }
115
116 return pte;
117 }
118
119 static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr,
120 enum i915_cache_level level,
121 bool valid)
122 {
123 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
124 pte |= GEN6_PTE_ADDR_ENCODE(addr);
125
126 switch (level) {
127 case I915_CACHE_L3_LLC:
128 pte |= GEN7_PTE_CACHE_L3_LLC;
129 break;
130 case I915_CACHE_LLC:
131 pte |= GEN6_PTE_CACHE_LLC;
132 break;
133 case I915_CACHE_NONE:
134 pte |= GEN6_PTE_UNCACHED;
135 break;
136 default:
137 WARN_ON(1);
138 }
139
140 return pte;
141 }
142
143 #define BYT_PTE_WRITEABLE (1 << 1)
144 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2)
145
146 static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
147 enum i915_cache_level level,
148 bool valid)
149 {
150 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
151 pte |= GEN6_PTE_ADDR_ENCODE(addr);
152
153 /* Mark the page as writeable. Other platforms don't have a
154 * setting for read-only/writable, so this matches that behavior.
155 */
156 pte |= BYT_PTE_WRITEABLE;
157
158 if (level != I915_CACHE_NONE)
159 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
160
161 return pte;
162 }
163
164 static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
165 enum i915_cache_level level,
166 bool valid)
167 {
168 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
169 pte |= HSW_PTE_ADDR_ENCODE(addr);
170
171 if (level != I915_CACHE_NONE)
172 pte |= HSW_WB_LLC_AGE3;
173
174 return pte;
175 }
176
177 static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
178 enum i915_cache_level level,
179 bool valid)
180 {
181 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
182 pte |= HSW_PTE_ADDR_ENCODE(addr);
183
184 switch (level) {
185 case I915_CACHE_NONE:
186 break;
187 case I915_CACHE_WT:
188 pte |= HSW_WT_ELLC_LLC_AGE0;
189 break;
190 default:
191 pte |= HSW_WB_ELLC_LLC_AGE0;
192 break;
193 }
194
195 return pte;
196 }
197
198 /* Broadwell Page Directory Pointer Descriptors */
199 static int gen8_write_pdp(struct intel_ring_buffer *ring, unsigned entry,
200 uint64_t val)
201 {
202 int ret;
203
204 BUG_ON(entry >= 4);
205
206 ret = intel_ring_begin(ring, 6);
207 if (ret)
208 return ret;
209
210 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
211 intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
212 intel_ring_emit(ring, (u32)(val >> 32));
213 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
214 intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
215 intel_ring_emit(ring, (u32)(val));
216 intel_ring_advance(ring);
217
218 return 0;
219 }
220
221 static int gen8_ppgtt_enable(struct drm_device *dev)
222 {
223 struct drm_i915_private *dev_priv = dev->dev_private;
224 struct intel_ring_buffer *ring;
225 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
226 int i, j, ret;
227
228 /* bit of a hack to find the actual last used pd */
229 int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE;
230
231 for_each_ring(ring, dev_priv, j) {
232 I915_WRITE(RING_MODE_GEN7(ring),
233 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
234 }
235
236 for (i = used_pd - 1; i >= 0; i--) {
237 dma_addr_t addr = ppgtt->pd_dma_addr[i];
238 for_each_ring(ring, dev_priv, j) {
239 ret = gen8_write_pdp(ring, i, addr);
240 if (ret)
241 goto err_out;
242 }
243 }
244 return 0;
245
246 err_out:
247 for_each_ring(ring, dev_priv, j)
248 I915_WRITE(RING_MODE_GEN7(ring),
249 _MASKED_BIT_DISABLE(GFX_PPGTT_ENABLE));
250 return ret;
251 }
252
253 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
254 unsigned first_entry,
255 unsigned num_entries,
256 bool use_scratch)
257 {
258 struct i915_hw_ppgtt *ppgtt =
259 container_of(vm, struct i915_hw_ppgtt, base);
260 gen8_gtt_pte_t *pt_vaddr, scratch_pte;
261 unsigned act_pt = first_entry / GEN8_PTES_PER_PAGE;
262 unsigned first_pte = first_entry % GEN8_PTES_PER_PAGE;
263 unsigned last_pte, i;
264
265 scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
266 I915_CACHE_LLC, use_scratch);
267
268 while (num_entries) {
269 struct page *page_table = &ppgtt->gen8_pt_pages[act_pt];
270
271 last_pte = first_pte + num_entries;
272 if (last_pte > GEN8_PTES_PER_PAGE)
273 last_pte = GEN8_PTES_PER_PAGE;
274
275 pt_vaddr = kmap_atomic(page_table);
276
277 for (i = first_pte; i < last_pte; i++)
278 pt_vaddr[i] = scratch_pte;
279
280 kunmap_atomic(pt_vaddr);
281
282 num_entries -= last_pte - first_pte;
283 first_pte = 0;
284 act_pt++;
285 }
286 }
287
288 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
289 struct sg_table *pages,
290 unsigned first_entry,
291 enum i915_cache_level cache_level)
292 {
293 struct i915_hw_ppgtt *ppgtt =
294 container_of(vm, struct i915_hw_ppgtt, base);
295 gen8_gtt_pte_t *pt_vaddr;
296 unsigned act_pt = first_entry / GEN8_PTES_PER_PAGE;
297 unsigned act_pte = first_entry % GEN8_PTES_PER_PAGE;
298 struct sg_page_iter sg_iter;
299
300 pt_vaddr = kmap_atomic(&ppgtt->gen8_pt_pages[act_pt]);
301 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
302 dma_addr_t page_addr;
303
304 page_addr = sg_dma_address(sg_iter.sg) +
305 (sg_iter.sg_pgoffset << PAGE_SHIFT);
306 pt_vaddr[act_pte] = gen8_pte_encode(page_addr, cache_level,
307 true);
308 if (++act_pte == GEN8_PTES_PER_PAGE) {
309 kunmap_atomic(pt_vaddr);
310 act_pt++;
311 pt_vaddr = kmap_atomic(&ppgtt->gen8_pt_pages[act_pt]);
312 act_pte = 0;
313
314 }
315 }
316 kunmap_atomic(pt_vaddr);
317 }
318
319 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
320 {
321 struct i915_hw_ppgtt *ppgtt =
322 container_of(vm, struct i915_hw_ppgtt, base);
323 int i, j;
324
325 for (i = 0; i < ppgtt->num_pd_pages ; i++) {
326 if (ppgtt->pd_dma_addr[i]) {
327 pci_unmap_page(ppgtt->base.dev->pdev,
328 ppgtt->pd_dma_addr[i],
329 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
330
331 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
332 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
333 if (addr)
334 pci_unmap_page(ppgtt->base.dev->pdev,
335 addr,
336 PAGE_SIZE,
337 PCI_DMA_BIDIRECTIONAL);
338
339 }
340 }
341 kfree(ppgtt->gen8_pt_dma_addr[i]);
342 }
343
344 __free_pages(ppgtt->gen8_pt_pages, get_order(ppgtt->num_pt_pages << PAGE_SHIFT));
345 __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT));
346 }
347
348 /**
349 * GEN8 legacy ppgtt programming is accomplished through 4 PDP registers with a
350 * net effect resembling a 2-level page table in normal x86 terms. Each PDP
351 * represents 1GB of memory
352 * 4 * 512 * 512 * 4096 = 4GB legacy 32b address space.
353 *
354 * TODO: Do something with the size parameter
355 **/
356 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
357 {
358 struct page *pt_pages;
359 int i, j, ret = -ENOMEM;
360 const int max_pdp = DIV_ROUND_UP(size, 1 << 30);
361 const int num_pt_pages = GEN8_PDES_PER_PAGE * max_pdp;
362
363 if (size % (1<<30))
364 DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size);
365
366 /* FIXME: split allocation into smaller pieces. For now we only ever do
367 * this once, but with full PPGTT, the multiple contiguous allocations
368 * will be bad.
369 */
370 ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT));
371 if (!ppgtt->pd_pages)
372 return -ENOMEM;
373
374 pt_pages = alloc_pages(GFP_KERNEL, get_order(num_pt_pages << PAGE_SHIFT));
375 if (!pt_pages) {
376 __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT));
377 return -ENOMEM;
378 }
379
380 ppgtt->gen8_pt_pages = pt_pages;
381 ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT);
382 ppgtt->num_pt_pages = 1 << get_order(num_pt_pages << PAGE_SHIFT);
383 ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
384 ppgtt->enable = gen8_ppgtt_enable;
385 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
386 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
387 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
388
389 BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS);
390
391 /*
392 * - Create a mapping for the page directories.
393 * - For each page directory:
394 * allocate space for page table mappings.
395 * map each page table
396 */
397 for (i = 0; i < max_pdp; i++) {
398 dma_addr_t temp;
399 temp = pci_map_page(ppgtt->base.dev->pdev,
400 &ppgtt->pd_pages[i], 0,
401 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
402 if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp))
403 goto err_out;
404
405 ppgtt->pd_dma_addr[i] = temp;
406
407 ppgtt->gen8_pt_dma_addr[i] = kmalloc(sizeof(dma_addr_t) * GEN8_PDES_PER_PAGE, GFP_KERNEL);
408 if (!ppgtt->gen8_pt_dma_addr[i])
409 goto err_out;
410
411 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
412 struct page *p = &pt_pages[i * GEN8_PDES_PER_PAGE + j];
413 temp = pci_map_page(ppgtt->base.dev->pdev,
414 p, 0, PAGE_SIZE,
415 PCI_DMA_BIDIRECTIONAL);
416
417 if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp))
418 goto err_out;
419
420 ppgtt->gen8_pt_dma_addr[i][j] = temp;
421 }
422 }
423
424 /* For now, the PPGTT helper functions all require that the PDEs are
425 * plugged in correctly. So we do that now/here. For aliasing PPGTT, we
426 * will never need to touch the PDEs again */
427 for (i = 0; i < max_pdp; i++) {
428 gen8_ppgtt_pde_t *pd_vaddr;
429 pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]);
430 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
431 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
432 pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr,
433 I915_CACHE_LLC);
434 }
435 kunmap_atomic(pd_vaddr);
436 }
437
438 ppgtt->base.clear_range(&ppgtt->base, 0,
439 ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE,
440 true);
441
442 DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
443 ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp);
444 DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n",
445 ppgtt->num_pt_pages,
446 (ppgtt->num_pt_pages - num_pt_pages) +
447 size % (1<<30));
448 return 0;
449
450 err_out:
451 ppgtt->base.cleanup(&ppgtt->base);
452 return ret;
453 }
454
455 static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
456 {
457 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
458 gen6_gtt_pte_t __iomem *pd_addr;
459 uint32_t pd_entry;
460 int i;
461
462 WARN_ON(ppgtt->pd_offset & 0x3f);
463 pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
464 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
465 for (i = 0; i < ppgtt->num_pd_entries; i++) {
466 dma_addr_t pt_addr;
467
468 pt_addr = ppgtt->pt_dma_addr[i];
469 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
470 pd_entry |= GEN6_PDE_VALID;
471
472 writel(pd_entry, pd_addr + i);
473 }
474 readl(pd_addr);
475 }
476
477 static int gen6_ppgtt_enable(struct drm_device *dev)
478 {
479 drm_i915_private_t *dev_priv = dev->dev_private;
480 uint32_t pd_offset;
481 struct intel_ring_buffer *ring;
482 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
483 int i;
484
485 BUG_ON(ppgtt->pd_offset & 0x3f);
486
487 gen6_write_pdes(ppgtt);
488
489 pd_offset = ppgtt->pd_offset;
490 pd_offset /= 64; /* in cachelines, */
491 pd_offset <<= 16;
492
493 if (INTEL_INFO(dev)->gen == 6) {
494 uint32_t ecochk, gab_ctl, ecobits;
495
496 ecobits = I915_READ(GAC_ECO_BITS);
497 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
498 ECOBITS_PPGTT_CACHE64B);
499
500 gab_ctl = I915_READ(GAB_CTL);
501 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
502
503 ecochk = I915_READ(GAM_ECOCHK);
504 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
505 ECOCHK_PPGTT_CACHE64B);
506 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
507 } else if (INTEL_INFO(dev)->gen >= 7) {
508 uint32_t ecochk, ecobits;
509
510 ecobits = I915_READ(GAC_ECO_BITS);
511 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
512
513 ecochk = I915_READ(GAM_ECOCHK);
514 if (IS_HASWELL(dev)) {
515 ecochk |= ECOCHK_PPGTT_WB_HSW;
516 } else {
517 ecochk |= ECOCHK_PPGTT_LLC_IVB;
518 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
519 }
520 I915_WRITE(GAM_ECOCHK, ecochk);
521 /* GFX_MODE is per-ring on gen7+ */
522 }
523
524 for_each_ring(ring, dev_priv, i) {
525 if (INTEL_INFO(dev)->gen >= 7)
526 I915_WRITE(RING_MODE_GEN7(ring),
527 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
528
529 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
530 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
531 }
532 return 0;
533 }
534
535 /* PPGTT support for Sandybdrige/Gen6 and later */
536 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
537 unsigned first_entry,
538 unsigned num_entries,
539 bool use_scratch)
540 {
541 struct i915_hw_ppgtt *ppgtt =
542 container_of(vm, struct i915_hw_ppgtt, base);
543 gen6_gtt_pte_t *pt_vaddr, scratch_pte;
544 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
545 unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
546 unsigned last_pte, i;
547
548 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true);
549
550 while (num_entries) {
551 last_pte = first_pte + num_entries;
552 if (last_pte > I915_PPGTT_PT_ENTRIES)
553 last_pte = I915_PPGTT_PT_ENTRIES;
554
555 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
556
557 for (i = first_pte; i < last_pte; i++)
558 pt_vaddr[i] = scratch_pte;
559
560 kunmap_atomic(pt_vaddr);
561
562 num_entries -= last_pte - first_pte;
563 first_pte = 0;
564 act_pt++;
565 }
566 }
567
568 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
569 struct sg_table *pages,
570 unsigned first_entry,
571 enum i915_cache_level cache_level)
572 {
573 struct i915_hw_ppgtt *ppgtt =
574 container_of(vm, struct i915_hw_ppgtt, base);
575 gen6_gtt_pte_t *pt_vaddr;
576 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
577 unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
578 struct sg_page_iter sg_iter;
579
580 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
581 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
582 dma_addr_t page_addr;
583
584 page_addr = sg_page_iter_dma_address(&sg_iter);
585 pt_vaddr[act_pte] = vm->pte_encode(page_addr, cache_level, true);
586 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
587 kunmap_atomic(pt_vaddr);
588 act_pt++;
589 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
590 act_pte = 0;
591
592 }
593 }
594 kunmap_atomic(pt_vaddr);
595 }
596
597 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
598 {
599 struct i915_hw_ppgtt *ppgtt =
600 container_of(vm, struct i915_hw_ppgtt, base);
601 int i;
602
603 drm_mm_takedown(&ppgtt->base.mm);
604
605 if (ppgtt->pt_dma_addr) {
606 for (i = 0; i < ppgtt->num_pd_entries; i++)
607 pci_unmap_page(ppgtt->base.dev->pdev,
608 ppgtt->pt_dma_addr[i],
609 4096, PCI_DMA_BIDIRECTIONAL);
610 }
611
612 kfree(ppgtt->pt_dma_addr);
613 for (i = 0; i < ppgtt->num_pd_entries; i++)
614 __free_page(ppgtt->pt_pages[i]);
615 kfree(ppgtt->pt_pages);
616 kfree(ppgtt);
617 }
618
619 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
620 {
621 struct drm_device *dev = ppgtt->base.dev;
622 struct drm_i915_private *dev_priv = dev->dev_private;
623 unsigned first_pd_entry_in_global_pt;
624 int i;
625 int ret = -ENOMEM;
626
627 /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
628 * entries. For aliasing ppgtt support we just steal them at the end for
629 * now. */
630 first_pd_entry_in_global_pt = gtt_total_entries(dev_priv->gtt);
631
632 ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
633 ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES;
634 ppgtt->enable = gen6_ppgtt_enable;
635 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
636 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
637 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
638 ppgtt->base.scratch = dev_priv->gtt.base.scratch;
639 ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *),
640 GFP_KERNEL);
641 if (!ppgtt->pt_pages)
642 return -ENOMEM;
643
644 for (i = 0; i < ppgtt->num_pd_entries; i++) {
645 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
646 if (!ppgtt->pt_pages[i])
647 goto err_pt_alloc;
648 }
649
650 ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t),
651 GFP_KERNEL);
652 if (!ppgtt->pt_dma_addr)
653 goto err_pt_alloc;
654
655 for (i = 0; i < ppgtt->num_pd_entries; i++) {
656 dma_addr_t pt_addr;
657
658 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
659 PCI_DMA_BIDIRECTIONAL);
660
661 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
662 ret = -EIO;
663 goto err_pd_pin;
664
665 }
666 ppgtt->pt_dma_addr[i] = pt_addr;
667 }
668
669 ppgtt->base.clear_range(&ppgtt->base, 0,
670 ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES, true);
671
672 ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t);
673
674 return 0;
675
676 err_pd_pin:
677 if (ppgtt->pt_dma_addr) {
678 for (i--; i >= 0; i--)
679 pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
680 4096, PCI_DMA_BIDIRECTIONAL);
681 }
682 err_pt_alloc:
683 kfree(ppgtt->pt_dma_addr);
684 for (i = 0; i < ppgtt->num_pd_entries; i++) {
685 if (ppgtt->pt_pages[i])
686 __free_page(ppgtt->pt_pages[i]);
687 }
688 kfree(ppgtt->pt_pages);
689
690 return ret;
691 }
692
693 static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
694 {
695 struct drm_i915_private *dev_priv = dev->dev_private;
696 struct i915_hw_ppgtt *ppgtt;
697 int ret;
698
699 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
700 if (!ppgtt)
701 return -ENOMEM;
702
703 ppgtt->base.dev = dev;
704
705 if (INTEL_INFO(dev)->gen < 8)
706 ret = gen6_ppgtt_init(ppgtt);
707 else if (IS_GEN8(dev))
708 ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
709 else
710 BUG();
711
712 if (ret)
713 kfree(ppgtt);
714 else {
715 dev_priv->mm.aliasing_ppgtt = ppgtt;
716 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
717 ppgtt->base.total);
718 }
719
720 return ret;
721 }
722
723 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev)
724 {
725 struct drm_i915_private *dev_priv = dev->dev_private;
726 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
727
728 if (!ppgtt)
729 return;
730
731 ppgtt->base.cleanup(&ppgtt->base);
732 dev_priv->mm.aliasing_ppgtt = NULL;
733 }
734
735 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
736 struct drm_i915_gem_object *obj,
737 enum i915_cache_level cache_level)
738 {
739 ppgtt->base.insert_entries(&ppgtt->base, obj->pages,
740 i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT,
741 cache_level);
742 }
743
744 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
745 struct drm_i915_gem_object *obj)
746 {
747 ppgtt->base.clear_range(&ppgtt->base,
748 i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT,
749 obj->base.size >> PAGE_SHIFT,
750 true);
751 }
752
753 extern int intel_iommu_gfx_mapped;
754 /* Certain Gen5 chipsets require require idling the GPU before
755 * unmapping anything from the GTT when VT-d is enabled.
756 */
757 static inline bool needs_idle_maps(struct drm_device *dev)
758 {
759 #ifdef CONFIG_INTEL_IOMMU
760 /* Query intel_iommu to see if we need the workaround. Presumably that
761 * was loaded first.
762 */
763 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
764 return true;
765 #endif
766 return false;
767 }
768
769 static bool do_idling(struct drm_i915_private *dev_priv)
770 {
771 bool ret = dev_priv->mm.interruptible;
772
773 if (unlikely(dev_priv->gtt.do_idle_maps)) {
774 dev_priv->mm.interruptible = false;
775 if (i915_gpu_idle(dev_priv->dev)) {
776 DRM_ERROR("Couldn't idle GPU\n");
777 /* Wait a bit, in hopes it avoids the hang */
778 udelay(10);
779 }
780 }
781
782 return ret;
783 }
784
785 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
786 {
787 if (unlikely(dev_priv->gtt.do_idle_maps))
788 dev_priv->mm.interruptible = interruptible;
789 }
790
791 void i915_check_and_clear_faults(struct drm_device *dev)
792 {
793 struct drm_i915_private *dev_priv = dev->dev_private;
794 struct intel_ring_buffer *ring;
795 int i;
796
797 if (INTEL_INFO(dev)->gen < 6)
798 return;
799
800 for_each_ring(ring, dev_priv, i) {
801 u32 fault_reg;
802 fault_reg = I915_READ(RING_FAULT_REG(ring));
803 if (fault_reg & RING_FAULT_VALID) {
804 DRM_DEBUG_DRIVER("Unexpected fault\n"
805 "\tAddr: 0x%08lx\\n"
806 "\tAddress space: %s\n"
807 "\tSource ID: %d\n"
808 "\tType: %d\n",
809 fault_reg & PAGE_MASK,
810 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
811 RING_FAULT_SRCID(fault_reg),
812 RING_FAULT_FAULT_TYPE(fault_reg));
813 I915_WRITE(RING_FAULT_REG(ring),
814 fault_reg & ~RING_FAULT_VALID);
815 }
816 }
817 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
818 }
819
820 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
821 {
822 struct drm_i915_private *dev_priv = dev->dev_private;
823
824 /* Don't bother messing with faults pre GEN6 as we have little
825 * documentation supporting that it's a good idea.
826 */
827 if (INTEL_INFO(dev)->gen < 6)
828 return;
829
830 i915_check_and_clear_faults(dev);
831
832 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
833 dev_priv->gtt.base.start / PAGE_SIZE,
834 dev_priv->gtt.base.total / PAGE_SIZE,
835 false);
836 }
837
838 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
839 {
840 struct drm_i915_private *dev_priv = dev->dev_private;
841 struct drm_i915_gem_object *obj;
842
843 i915_check_and_clear_faults(dev);
844
845 /* First fill our portion of the GTT with scratch pages */
846 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
847 dev_priv->gtt.base.start / PAGE_SIZE,
848 dev_priv->gtt.base.total / PAGE_SIZE,
849 true);
850
851 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
852 i915_gem_clflush_object(obj, obj->pin_display);
853 i915_gem_gtt_bind_object(obj, obj->cache_level);
854 }
855
856 i915_gem_chipset_flush(dev);
857 }
858
859 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
860 {
861 if (obj->has_dma_mapping)
862 return 0;
863
864 if (!dma_map_sg(&obj->base.dev->pdev->dev,
865 obj->pages->sgl, obj->pages->nents,
866 PCI_DMA_BIDIRECTIONAL))
867 return -ENOSPC;
868
869 return 0;
870 }
871
872 static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte)
873 {
874 #ifdef writeq
875 writeq(pte, addr);
876 #else
877 iowrite32((u32)pte, addr);
878 iowrite32(pte >> 32, addr + 4);
879 #endif
880 }
881
882 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
883 struct sg_table *st,
884 unsigned int first_entry,
885 enum i915_cache_level level)
886 {
887 struct drm_i915_private *dev_priv = vm->dev->dev_private;
888 gen8_gtt_pte_t __iomem *gtt_entries =
889 (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
890 int i = 0;
891 struct sg_page_iter sg_iter;
892 dma_addr_t addr;
893
894 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
895 addr = sg_dma_address(sg_iter.sg) +
896 (sg_iter.sg_pgoffset << PAGE_SHIFT);
897 gen8_set_pte(&gtt_entries[i],
898 gen8_pte_encode(addr, level, true));
899 i++;
900 }
901
902 /*
903 * XXX: This serves as a posting read to make sure that the PTE has
904 * actually been updated. There is some concern that even though
905 * registers and PTEs are within the same BAR that they are potentially
906 * of NUMA access patterns. Therefore, even with the way we assume
907 * hardware should work, we must keep this posting read for paranoia.
908 */
909 if (i != 0)
910 WARN_ON(readq(&gtt_entries[i-1])
911 != gen8_pte_encode(addr, level, true));
912
913 #if 0 /* TODO: Still needed on GEN8? */
914 /* This next bit makes the above posting read even more important. We
915 * want to flush the TLBs only after we're certain all the PTE updates
916 * have finished.
917 */
918 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
919 POSTING_READ(GFX_FLSH_CNTL_GEN6);
920 #endif
921 }
922
923 /*
924 * Binds an object into the global gtt with the specified cache level. The object
925 * will be accessible to the GPU via commands whose operands reference offsets
926 * within the global GTT as well as accessible by the GPU through the GMADR
927 * mapped BAR (dev_priv->mm.gtt->gtt).
928 */
929 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
930 struct sg_table *st,
931 unsigned int first_entry,
932 enum i915_cache_level level)
933 {
934 struct drm_i915_private *dev_priv = vm->dev->dev_private;
935 gen6_gtt_pte_t __iomem *gtt_entries =
936 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
937 int i = 0;
938 struct sg_page_iter sg_iter;
939 dma_addr_t addr;
940
941 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
942 addr = sg_page_iter_dma_address(&sg_iter);
943 iowrite32(vm->pte_encode(addr, level, true), &gtt_entries[i]);
944 i++;
945 }
946
947 /* XXX: This serves as a posting read to make sure that the PTE has
948 * actually been updated. There is some concern that even though
949 * registers and PTEs are within the same BAR that they are potentially
950 * of NUMA access patterns. Therefore, even with the way we assume
951 * hardware should work, we must keep this posting read for paranoia.
952 */
953 if (i != 0)
954 WARN_ON(readl(&gtt_entries[i-1]) !=
955 vm->pte_encode(addr, level, true));
956
957 /* This next bit makes the above posting read even more important. We
958 * want to flush the TLBs only after we're certain all the PTE updates
959 * have finished.
960 */
961 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
962 POSTING_READ(GFX_FLSH_CNTL_GEN6);
963 }
964
965 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
966 unsigned int first_entry,
967 unsigned int num_entries,
968 bool use_scratch)
969 {
970 struct drm_i915_private *dev_priv = vm->dev->dev_private;
971 gen8_gtt_pte_t scratch_pte, __iomem *gtt_base =
972 (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
973 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
974 int i;
975
976 if (WARN(num_entries > max_entries,
977 "First entry = %d; Num entries = %d (max=%d)\n",
978 first_entry, num_entries, max_entries))
979 num_entries = max_entries;
980
981 scratch_pte = gen8_pte_encode(vm->scratch.addr,
982 I915_CACHE_LLC,
983 use_scratch);
984 for (i = 0; i < num_entries; i++)
985 gen8_set_pte(&gtt_base[i], scratch_pte);
986 readl(gtt_base);
987 }
988
989 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
990 unsigned int first_entry,
991 unsigned int num_entries,
992 bool use_scratch)
993 {
994 struct drm_i915_private *dev_priv = vm->dev->dev_private;
995 gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
996 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
997 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
998 int i;
999
1000 if (WARN(num_entries > max_entries,
1001 "First entry = %d; Num entries = %d (max=%d)\n",
1002 first_entry, num_entries, max_entries))
1003 num_entries = max_entries;
1004
1005 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch);
1006
1007 for (i = 0; i < num_entries; i++)
1008 iowrite32(scratch_pte, &gtt_base[i]);
1009 readl(gtt_base);
1010 }
1011
1012 static void i915_ggtt_insert_entries(struct i915_address_space *vm,
1013 struct sg_table *st,
1014 unsigned int pg_start,
1015 enum i915_cache_level cache_level)
1016 {
1017 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1018 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1019
1020 intel_gtt_insert_sg_entries(st, pg_start, flags);
1021
1022 }
1023
1024 static void i915_ggtt_clear_range(struct i915_address_space *vm,
1025 unsigned int first_entry,
1026 unsigned int num_entries,
1027 bool unused)
1028 {
1029 intel_gtt_clear_range(first_entry, num_entries);
1030 }
1031
1032
1033 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
1034 enum i915_cache_level cache_level)
1035 {
1036 struct drm_device *dev = obj->base.dev;
1037 struct drm_i915_private *dev_priv = dev->dev_private;
1038 const unsigned long entry = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT;
1039
1040 dev_priv->gtt.base.insert_entries(&dev_priv->gtt.base, obj->pages,
1041 entry,
1042 cache_level);
1043
1044 obj->has_global_gtt_mapping = 1;
1045 }
1046
1047 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
1048 {
1049 struct drm_device *dev = obj->base.dev;
1050 struct drm_i915_private *dev_priv = dev->dev_private;
1051 const unsigned long entry = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT;
1052
1053 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1054 entry,
1055 obj->base.size >> PAGE_SHIFT,
1056 true);
1057
1058 obj->has_global_gtt_mapping = 0;
1059 }
1060
1061 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
1062 {
1063 struct drm_device *dev = obj->base.dev;
1064 struct drm_i915_private *dev_priv = dev->dev_private;
1065 bool interruptible;
1066
1067 interruptible = do_idling(dev_priv);
1068
1069 if (!obj->has_dma_mapping)
1070 dma_unmap_sg(&dev->pdev->dev,
1071 obj->pages->sgl, obj->pages->nents,
1072 PCI_DMA_BIDIRECTIONAL);
1073
1074 undo_idling(dev_priv, interruptible);
1075 }
1076
1077 static void i915_gtt_color_adjust(struct drm_mm_node *node,
1078 unsigned long color,
1079 unsigned long *start,
1080 unsigned long *end)
1081 {
1082 if (node->color != color)
1083 *start += 4096;
1084
1085 if (!list_empty(&node->node_list)) {
1086 node = list_entry(node->node_list.next,
1087 struct drm_mm_node,
1088 node_list);
1089 if (node->allocated && node->color != color)
1090 *end -= 4096;
1091 }
1092 }
1093
1094 void i915_gem_setup_global_gtt(struct drm_device *dev,
1095 unsigned long start,
1096 unsigned long mappable_end,
1097 unsigned long end)
1098 {
1099 /* Let GEM Manage all of the aperture.
1100 *
1101 * However, leave one page at the end still bound to the scratch page.
1102 * There are a number of places where the hardware apparently prefetches
1103 * past the end of the object, and we've seen multiple hangs with the
1104 * GPU head pointer stuck in a batchbuffer bound at the last page of the
1105 * aperture. One page should be enough to keep any prefetching inside
1106 * of the aperture.
1107 */
1108 struct drm_i915_private *dev_priv = dev->dev_private;
1109 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
1110 struct drm_mm_node *entry;
1111 struct drm_i915_gem_object *obj;
1112 unsigned long hole_start, hole_end;
1113
1114 BUG_ON(mappable_end > end);
1115
1116 /* Subtract the guard page ... */
1117 drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
1118 if (!HAS_LLC(dev))
1119 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
1120
1121 /* Mark any preallocated objects as occupied */
1122 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1123 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
1124 int ret;
1125 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
1126 i915_gem_obj_ggtt_offset(obj), obj->base.size);
1127
1128 WARN_ON(i915_gem_obj_ggtt_bound(obj));
1129 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
1130 if (ret)
1131 DRM_DEBUG_KMS("Reservation failed\n");
1132 obj->has_global_gtt_mapping = 1;
1133 }
1134
1135 dev_priv->gtt.base.start = start;
1136 dev_priv->gtt.base.total = end - start;
1137
1138 /* Clear any non-preallocated blocks */
1139 drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
1140 const unsigned long count = (hole_end - hole_start) / PAGE_SIZE;
1141 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
1142 hole_start, hole_end);
1143 ggtt_vm->clear_range(ggtt_vm, hole_start / PAGE_SIZE, count, true);
1144 }
1145
1146 /* And finally clear the reserved guard page */
1147 ggtt_vm->clear_range(ggtt_vm, end / PAGE_SIZE - 1, 1, true);
1148 }
1149
1150 static bool
1151 intel_enable_ppgtt(struct drm_device *dev)
1152 {
1153 if (i915_enable_ppgtt >= 0)
1154 return i915_enable_ppgtt;
1155
1156 #ifdef CONFIG_INTEL_IOMMU
1157 /* Disable ppgtt on SNB if VT-d is on. */
1158 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
1159 return false;
1160 #endif
1161
1162 return true;
1163 }
1164
1165 void i915_gem_init_global_gtt(struct drm_device *dev)
1166 {
1167 struct drm_i915_private *dev_priv = dev->dev_private;
1168 unsigned long gtt_size, mappable_size;
1169
1170 gtt_size = dev_priv->gtt.base.total;
1171 mappable_size = dev_priv->gtt.mappable_end;
1172
1173 if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
1174 int ret;
1175
1176 if (INTEL_INFO(dev)->gen <= 7) {
1177 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
1178 * aperture accordingly when using aliasing ppgtt. */
1179 gtt_size -= GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE;
1180 }
1181
1182 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
1183
1184 ret = i915_gem_init_aliasing_ppgtt(dev);
1185 if (!ret)
1186 return;
1187
1188 DRM_ERROR("Aliased PPGTT setup failed %d\n", ret);
1189 drm_mm_takedown(&dev_priv->gtt.base.mm);
1190 if (INTEL_INFO(dev)->gen < 8)
1191 gtt_size += GEN6_PPGTT_PD_ENTRIES*PAGE_SIZE;
1192 }
1193 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
1194 }
1195
1196 static int setup_scratch_page(struct drm_device *dev)
1197 {
1198 struct drm_i915_private *dev_priv = dev->dev_private;
1199 struct page *page;
1200 dma_addr_t dma_addr;
1201
1202 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
1203 if (page == NULL)
1204 return -ENOMEM;
1205 get_page(page);
1206 set_pages_uc(page, 1);
1207
1208 #ifdef CONFIG_INTEL_IOMMU
1209 dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
1210 PCI_DMA_BIDIRECTIONAL);
1211 if (pci_dma_mapping_error(dev->pdev, dma_addr))
1212 return -EINVAL;
1213 #else
1214 dma_addr = page_to_phys(page);
1215 #endif
1216 dev_priv->gtt.base.scratch.page = page;
1217 dev_priv->gtt.base.scratch.addr = dma_addr;
1218
1219 return 0;
1220 }
1221
1222 static void teardown_scratch_page(struct drm_device *dev)
1223 {
1224 struct drm_i915_private *dev_priv = dev->dev_private;
1225 struct page *page = dev_priv->gtt.base.scratch.page;
1226
1227 set_pages_wb(page, 1);
1228 pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
1229 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1230 put_page(page);
1231 __free_page(page);
1232 }
1233
1234 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
1235 {
1236 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
1237 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
1238 return snb_gmch_ctl << 20;
1239 }
1240
1241 static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
1242 {
1243 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
1244 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
1245 if (bdw_gmch_ctl)
1246 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
1247 if (bdw_gmch_ctl > 4) {
1248 WARN_ON(!i915_preliminary_hw_support);
1249 return 4<<20;
1250 }
1251
1252 return bdw_gmch_ctl << 20;
1253 }
1254
1255 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
1256 {
1257 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
1258 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
1259 return snb_gmch_ctl << 25; /* 32 MB units */
1260 }
1261
1262 static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
1263 {
1264 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
1265 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
1266 return bdw_gmch_ctl << 25; /* 32 MB units */
1267 }
1268
1269 static int ggtt_probe_common(struct drm_device *dev,
1270 size_t gtt_size)
1271 {
1272 struct drm_i915_private *dev_priv = dev->dev_private;
1273 phys_addr_t gtt_bus_addr;
1274 int ret;
1275
1276 /* For Modern GENs the PTEs and register space are split in the BAR */
1277 gtt_bus_addr = pci_resource_start(dev->pdev, 0) +
1278 (pci_resource_len(dev->pdev, 0) / 2);
1279
1280 dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size);
1281 if (!dev_priv->gtt.gsm) {
1282 DRM_ERROR("Failed to map the gtt page table\n");
1283 return -ENOMEM;
1284 }
1285
1286 ret = setup_scratch_page(dev);
1287 if (ret) {
1288 DRM_ERROR("Scratch setup failed\n");
1289 /* iounmap will also get called at remove, but meh */
1290 iounmap(dev_priv->gtt.gsm);
1291 }
1292
1293 return ret;
1294 }
1295
1296 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
1297 * bits. When using advanced contexts each context stores its own PAT, but
1298 * writing this data shouldn't be harmful even in those cases. */
1299 static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv)
1300 {
1301 #define GEN8_PPAT_UC (0<<0)
1302 #define GEN8_PPAT_WC (1<<0)
1303 #define GEN8_PPAT_WT (2<<0)
1304 #define GEN8_PPAT_WB (3<<0)
1305 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
1306 /* FIXME(BDW): Bspec is completely confused about cache control bits. */
1307 #define GEN8_PPAT_LLC (1<<2)
1308 #define GEN8_PPAT_LLCELLC (2<<2)
1309 #define GEN8_PPAT_LLCeLLC (3<<2)
1310 #define GEN8_PPAT_AGE(x) (x<<4)
1311 #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8))
1312 uint64_t pat;
1313
1314 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
1315 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
1316 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
1317 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
1318 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
1319 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
1320 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
1321 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
1322
1323 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
1324 * write would work. */
1325 I915_WRITE(GEN8_PRIVATE_PAT, pat);
1326 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
1327 }
1328
1329 static int gen8_gmch_probe(struct drm_device *dev,
1330 size_t *gtt_total,
1331 size_t *stolen,
1332 phys_addr_t *mappable_base,
1333 unsigned long *mappable_end)
1334 {
1335 struct drm_i915_private *dev_priv = dev->dev_private;
1336 unsigned int gtt_size;
1337 u16 snb_gmch_ctl;
1338 int ret;
1339
1340 /* TODO: We're not aware of mappable constraints on gen8 yet */
1341 *mappable_base = pci_resource_start(dev->pdev, 2);
1342 *mappable_end = pci_resource_len(dev->pdev, 2);
1343
1344 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
1345 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
1346
1347 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1348
1349 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
1350
1351 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
1352 *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
1353
1354 gen8_setup_private_ppat(dev_priv);
1355
1356 ret = ggtt_probe_common(dev, gtt_size);
1357
1358 dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
1359 dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
1360
1361 return ret;
1362 }
1363
1364 static int gen6_gmch_probe(struct drm_device *dev,
1365 size_t *gtt_total,
1366 size_t *stolen,
1367 phys_addr_t *mappable_base,
1368 unsigned long *mappable_end)
1369 {
1370 struct drm_i915_private *dev_priv = dev->dev_private;
1371 unsigned int gtt_size;
1372 u16 snb_gmch_ctl;
1373 int ret;
1374
1375 *mappable_base = pci_resource_start(dev->pdev, 2);
1376 *mappable_end = pci_resource_len(dev->pdev, 2);
1377
1378 /* 64/512MB is the current min/max we actually know of, but this is just
1379 * a coarse sanity check.
1380 */
1381 if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
1382 DRM_ERROR("Unknown GMADR size (%lx)\n",
1383 dev_priv->gtt.mappable_end);
1384 return -ENXIO;
1385 }
1386
1387 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
1388 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
1389 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1390
1391 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
1392
1393 gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
1394 *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
1395
1396 ret = ggtt_probe_common(dev, gtt_size);
1397
1398 dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
1399 dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
1400
1401 return ret;
1402 }
1403
1404 static void gen6_gmch_remove(struct i915_address_space *vm)
1405 {
1406
1407 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
1408 iounmap(gtt->gsm);
1409 teardown_scratch_page(vm->dev);
1410 }
1411
1412 static int i915_gmch_probe(struct drm_device *dev,
1413 size_t *gtt_total,
1414 size_t *stolen,
1415 phys_addr_t *mappable_base,
1416 unsigned long *mappable_end)
1417 {
1418 struct drm_i915_private *dev_priv = dev->dev_private;
1419 int ret;
1420
1421 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
1422 if (!ret) {
1423 DRM_ERROR("failed to set up gmch\n");
1424 return -EIO;
1425 }
1426
1427 intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
1428
1429 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
1430 dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
1431 dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries;
1432
1433 return 0;
1434 }
1435
1436 static void i915_gmch_remove(struct i915_address_space *vm)
1437 {
1438 intel_gmch_remove();
1439 }
1440
1441 int i915_gem_gtt_init(struct drm_device *dev)
1442 {
1443 struct drm_i915_private *dev_priv = dev->dev_private;
1444 struct i915_gtt *gtt = &dev_priv->gtt;
1445 int ret;
1446
1447 if (INTEL_INFO(dev)->gen <= 5) {
1448 gtt->gtt_probe = i915_gmch_probe;
1449 gtt->base.cleanup = i915_gmch_remove;
1450 } else if (INTEL_INFO(dev)->gen < 8) {
1451 gtt->gtt_probe = gen6_gmch_probe;
1452 gtt->base.cleanup = gen6_gmch_remove;
1453 if (IS_HASWELL(dev) && dev_priv->ellc_size)
1454 gtt->base.pte_encode = iris_pte_encode;
1455 else if (IS_HASWELL(dev))
1456 gtt->base.pte_encode = hsw_pte_encode;
1457 else if (IS_VALLEYVIEW(dev))
1458 gtt->base.pte_encode = byt_pte_encode;
1459 else if (INTEL_INFO(dev)->gen >= 7)
1460 gtt->base.pte_encode = ivb_pte_encode;
1461 else
1462 gtt->base.pte_encode = snb_pte_encode;
1463 } else {
1464 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
1465 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
1466 }
1467
1468 ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
1469 &gtt->mappable_base, &gtt->mappable_end);
1470 if (ret)
1471 return ret;
1472
1473 gtt->base.dev = dev;
1474
1475 /* GMADR is the PCI mmio aperture into the global GTT. */
1476 DRM_INFO("Memory usable by graphics device = %zdM\n",
1477 gtt->base.total >> 20);
1478 DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
1479 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
1480
1481 return 0;
1482 }
Linux kernel - Deliverables
This page took 0.063231 seconds and 6 git commands to generate.