2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * Please try to maintain the following order within this file unless it makes
24 * sense to do otherwise. From top to bottom:
26 * 2. #defines, and macros
27 * 3. structure definitions
28 * 4. function prototypes
30 * Within each section, please try to order by generation in ascending order,
31 * from top to bottom (ie. gen6 on the top, gen8 on the bottom).
34 #ifndef __I915_GEM_GTT_H__
35 #define __I915_GEM_GTT_H__
37 #include <linux/io-mapping.h>
39 #include "i915_gem_request.h"
41 struct drm_i915_file_private
;
43 typedef uint32_t gen6_pte_t
;
44 typedef uint64_t gen8_pte_t
;
45 typedef uint64_t gen8_pde_t
;
46 typedef uint64_t gen8_ppgtt_pdpe_t
;
47 typedef uint64_t gen8_ppgtt_pml4e_t
;
49 #define ggtt_total_entries(ggtt) ((ggtt)->base.total >> PAGE_SHIFT)
51 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */
52 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
53 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
54 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
55 #define GEN6_PTE_CACHE_LLC (2 << 1)
56 #define GEN6_PTE_UNCACHED (1 << 1)
57 #define GEN6_PTE_VALID (1 << 0)
59 #define I915_PTES(pte_len) (PAGE_SIZE / (pte_len))
60 #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1)
62 #define I915_PDE_MASK (I915_PDES - 1)
63 #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT))
65 #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t))
66 #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE)
67 #define GEN6_PD_ALIGN (PAGE_SIZE * 16)
68 #define GEN6_PDE_SHIFT 22
69 #define GEN6_PDE_VALID (1 << 0)
71 #define GEN7_PTE_CACHE_L3_LLC (3 << 1)
73 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2)
74 #define BYT_PTE_WRITEABLE (1 << 1)
76 /* Cacheability Control is a 4-bit value. The low three bits are stored in bits
77 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
79 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \
80 (((bits) & 0x8) << (11 - 3)))
81 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2)
82 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3)
83 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8)
84 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb)
85 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7)
86 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6)
87 #define HSW_PTE_UNCACHED (0)
88 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0))
89 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr)
91 /* GEN8 legacy style address is defined as a 3 level page table:
92 * 31:30 | 29:21 | 20:12 | 11:0
93 * PDPE | PDE | PTE | offset
94 * The difference as compared to normal x86 3 level page table is the PDPEs are
95 * programmed via register.
97 * GEN8 48b legacy style address is defined as a 4 level page table:
98 * 47:39 | 38:30 | 29:21 | 20:12 | 11:0
99 * PML4E | PDPE | PDE | PTE | offset
101 #define GEN8_PML4ES_PER_PML4 512
102 #define GEN8_PML4E_SHIFT 39
103 #define GEN8_PML4E_MASK (GEN8_PML4ES_PER_PML4 - 1)
104 #define GEN8_PDPE_SHIFT 30
105 /* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page
107 #define GEN8_PDPE_MASK 0x1ff
108 #define GEN8_PDE_SHIFT 21
109 #define GEN8_PDE_MASK 0x1ff
110 #define GEN8_PTE_SHIFT 12
111 #define GEN8_PTE_MASK 0x1ff
112 #define GEN8_LEGACY_PDPES 4
113 #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t))
115 #define I915_PDPES_PER_PDP(dev) (USES_FULL_48BIT_PPGTT(dev) ?\
116 GEN8_PML4ES_PER_PML4 : GEN8_LEGACY_PDPES)
118 #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD)
119 #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */
120 #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */
121 #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */
123 #define CHV_PPAT_SNOOP (1<<6)
124 #define GEN8_PPAT_AGE(x) (x<<4)
125 #define GEN8_PPAT_LLCeLLC (3<<2)
126 #define GEN8_PPAT_LLCELLC (2<<2)
127 #define GEN8_PPAT_LLC (1<<2)
128 #define GEN8_PPAT_WB (3<<0)
129 #define GEN8_PPAT_WT (2<<0)
130 #define GEN8_PPAT_WC (1<<0)
131 #define GEN8_PPAT_UC (0<<0)
132 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
133 #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8))
135 enum i915_ggtt_view_type
{
136 I915_GGTT_VIEW_NORMAL
= 0,
137 I915_GGTT_VIEW_ROTATED
,
138 I915_GGTT_VIEW_PARTIAL
,
141 struct intel_rotation_info
{
144 unsigned int width
, height
, stride
, offset
;
148 struct i915_ggtt_view
{
149 enum i915_ggtt_view_type type
;
156 struct intel_rotation_info rotated
;
160 extern const struct i915_ggtt_view i915_ggtt_view_normal
;
161 extern const struct i915_ggtt_view i915_ggtt_view_rotated
;
163 enum i915_cache_level
;
166 * A VMA represents a GEM BO that is bound into an address space. Therefore, a
167 * VMA's presence cannot be guaranteed before binding, or after unbinding the
168 * object into/from the address space.
170 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime
171 * will always be <= an objects lifetime. So object refcounting should cover us.
174 struct drm_mm_node node
;
175 struct drm_i915_gem_object
*obj
;
176 struct i915_address_space
*vm
;
177 struct sg_table
*pages
;
183 * How many users have pinned this object in GTT space. The following
184 * users can each hold at most one reference: pwrite/pread, execbuffer
185 * (objects are not allowed multiple times for the same batchbuffer),
186 * and the framebuffer code. When switching/pageflipping, the
187 * framebuffer code has at most two buffers pinned per crtc.
189 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
190 * bits with absolutely no headroom. So use 4 bits.
192 #define I915_VMA_PIN_MASK 0xf
193 #define I915_VMA_PIN_OVERFLOW BIT(5)
195 /** Flags and address space this VMA is bound to */
196 #define I915_VMA_GLOBAL_BIND BIT(6)
197 #define I915_VMA_LOCAL_BIND BIT(7)
198 #define I915_VMA_BIND_MASK (I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND | I915_VMA_PIN_OVERFLOW)
200 #define I915_VMA_GGTT BIT(8)
201 #define I915_VMA_CLOSED BIT(9)
204 struct i915_gem_active last_read
[I915_NUM_ENGINES
];
207 * Support different GGTT views into the same object.
208 * This means there can be multiple VMA mappings per object and per VM.
209 * i915_ggtt_view_type is used to distinguish between those entries.
210 * The default one of zero (I915_GGTT_VIEW_NORMAL) is default and also
211 * assumed in GEM functions which take no ggtt view parameter.
213 struct i915_ggtt_view ggtt_view
;
215 /** This object's place on the active/inactive lists */
216 struct list_head vm_link
;
218 struct list_head obj_link
; /* Link in the object's VMA list */
220 /** This vma's place in the batchbuffer or on the eviction list */
221 struct list_head exec_list
;
224 * Used for performing relocations during execbuffer insertion.
226 struct hlist_node exec_node
;
227 unsigned long exec_handle
;
228 struct drm_i915_gem_exec_object2
*exec_entry
;
232 i915_vma_create(struct drm_i915_gem_object
*obj
,
233 struct i915_address_space
*vm
,
234 const struct i915_ggtt_view
*view
);
236 static inline bool i915_vma_is_ggtt(const struct i915_vma
*vma
)
238 return vma
->flags
& I915_VMA_GGTT
;
241 static inline bool i915_vma_is_closed(const struct i915_vma
*vma
)
243 return vma
->flags
& I915_VMA_CLOSED
;
246 static inline unsigned int i915_vma_get_active(const struct i915_vma
*vma
)
251 static inline bool i915_vma_is_active(const struct i915_vma
*vma
)
253 return i915_vma_get_active(vma
);
256 static inline void i915_vma_set_active(struct i915_vma
*vma
,
259 vma
->active
|= BIT(engine
);
262 static inline void i915_vma_clear_active(struct i915_vma
*vma
,
265 vma
->active
&= ~BIT(engine
);
268 static inline bool i915_vma_has_active_engine(const struct i915_vma
*vma
,
271 return vma
->active
& BIT(engine
);
274 struct i915_page_dma
{
279 /* For gen6/gen7 only. This is the offset in the GGTT
280 * where the page directory entries for PPGTT begin
282 uint32_t ggtt_offset
;
286 #define px_base(px) (&(px)->base)
287 #define px_page(px) (px_base(px)->page)
288 #define px_dma(px) (px_base(px)->daddr)
290 struct i915_page_scratch
{
291 struct i915_page_dma base
;
294 struct i915_page_table
{
295 struct i915_page_dma base
;
297 unsigned long *used_ptes
;
300 struct i915_page_directory
{
301 struct i915_page_dma base
;
303 unsigned long *used_pdes
;
304 struct i915_page_table
*page_table
[I915_PDES
]; /* PDEs */
307 struct i915_page_directory_pointer
{
308 struct i915_page_dma base
;
310 unsigned long *used_pdpes
;
311 struct i915_page_directory
**page_directory
;
315 struct i915_page_dma base
;
317 DECLARE_BITMAP(used_pml4es
, GEN8_PML4ES_PER_PML4
);
318 struct i915_page_directory_pointer
*pdps
[GEN8_PML4ES_PER_PML4
];
321 struct i915_address_space
{
323 struct drm_device
*dev
;
324 /* Every address space belongs to a struct file - except for the global
325 * GTT that is owned by the driver (and so @file is set to NULL). In
326 * principle, no information should leak from one context to another
327 * (or between files/processes etc) unless explicitly shared by the
328 * owner. Tracking the owner is important in order to free up per-file
329 * objects along with the file, to aide resource tracking, and to
332 struct drm_i915_file_private
*file
;
333 struct list_head global_link
;
334 u64 start
; /* Start offset always 0 for dri2 */
335 u64 total
; /* size addr space maps (ex. 2GB for ggtt) */
339 struct i915_page_scratch
*scratch_page
;
340 struct i915_page_table
*scratch_pt
;
341 struct i915_page_directory
*scratch_pd
;
342 struct i915_page_directory_pointer
*scratch_pdp
; /* GEN8+ & 48b PPGTT */
345 * List of objects currently involved in rendering.
347 * Includes buffers having the contents of their GPU caches
348 * flushed, not necessarily primitives. last_read_req
349 * represents when the rendering involved will be completed.
351 * A reference is held on the buffer while on this list.
353 struct list_head active_list
;
356 * LRU list of objects which are not in the ringbuffer and
357 * are ready to unbind, but are still in the GTT.
359 * last_read_req is NULL while an object is in this list.
361 * A reference is not held on the buffer while on this list,
362 * as merely being GTT-bound shouldn't prevent its being
363 * freed, and we'll pull it off the list in the free path.
365 struct list_head inactive_list
;
368 * List of vma that have been unbound.
370 * A reference is not held on the buffer while on this list.
372 struct list_head unbound_list
;
374 /* FIXME: Need a more generic return type */
375 gen6_pte_t (*pte_encode
)(dma_addr_t addr
,
376 enum i915_cache_level level
,
377 bool valid
, u32 flags
); /* Create a valid PTE */
378 /* flags for pte_encode */
379 #define PTE_READ_ONLY (1<<0)
380 int (*allocate_va_range
)(struct i915_address_space
*vm
,
383 void (*clear_range
)(struct i915_address_space
*vm
,
387 void (*insert_page
)(struct i915_address_space
*vm
,
390 enum i915_cache_level cache_level
,
392 void (*insert_entries
)(struct i915_address_space
*vm
,
395 enum i915_cache_level cache_level
, u32 flags
);
396 void (*cleanup
)(struct i915_address_space
*vm
);
397 /** Unmap an object from an address space. This usually consists of
398 * setting the valid PTE entries to a reserved scratch page. */
399 void (*unbind_vma
)(struct i915_vma
*vma
);
400 /* Map an object into an address space with the given cache flags. */
401 int (*bind_vma
)(struct i915_vma
*vma
,
402 enum i915_cache_level cache_level
,
406 #define i915_is_ggtt(V) (!(V)->file)
408 /* The Graphics Translation Table is the way in which GEN hardware translates a
409 * Graphics Virtual Address into a Physical Address. In addition to the normal
410 * collateral associated with any va->pa translations GEN hardware also has a
411 * portion of the GTT which can be mapped by the CPU and remain both coherent
412 * and correct (in cases like swizzling). That region is referred to as GMADR in
416 struct i915_address_space base
;
418 size_t stolen_size
; /* Total size of stolen memory */
419 size_t stolen_usable_size
; /* Total size minus BIOS reserved */
420 size_t stolen_reserved_base
;
421 size_t stolen_reserved_size
;
422 u64 mappable_end
; /* End offset that we can CPU map */
423 struct io_mapping
*mappable
; /* Mapping to our CPU mappable region */
424 phys_addr_t mappable_base
; /* PA of our GMADR */
426 /** "Graphics Stolen Memory" holds the global PTEs */
434 struct i915_hw_ppgtt
{
435 struct i915_address_space base
;
437 struct drm_mm_node node
;
438 unsigned long pd_dirty_rings
;
440 struct i915_pml4 pml4
; /* GEN8+ & 48b PPGTT */
441 struct i915_page_directory_pointer pdp
; /* GEN8+ */
442 struct i915_page_directory pd
; /* GEN6-7 */
445 gen6_pte_t __iomem
*pd_addr
;
447 int (*enable
)(struct i915_hw_ppgtt
*ppgtt
);
448 int (*switch_mm
)(struct i915_hw_ppgtt
*ppgtt
,
449 struct drm_i915_gem_request
*req
);
450 void (*debug_dump
)(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
);
454 * gen6_for_each_pde() iterates over every pde from start until start+length.
455 * If start and start+length are not perfectly divisible, the macro will round
456 * down and up as needed. Start=0 and length=2G effectively iterates over
457 * every PDE in the system. The macro modifies ALL its parameters except 'pd',
458 * so each of the other parameters should preferably be a simple variable, or
459 * at most an lvalue with no side-effects!
461 #define gen6_for_each_pde(pt, pd, start, length, iter) \
462 for (iter = gen6_pde_index(start); \
463 length > 0 && iter < I915_PDES && \
464 (pt = (pd)->page_table[iter], true); \
465 ({ u32 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT); \
466 temp = min(temp - start, length); \
467 start += temp, length -= temp; }), ++iter)
469 #define gen6_for_all_pdes(pt, pd, iter) \
471 iter < I915_PDES && \
472 (pt = (pd)->page_table[iter], true); \
475 static inline uint32_t i915_pte_index(uint64_t address
, uint32_t pde_shift
)
477 const uint32_t mask
= NUM_PTE(pde_shift
) - 1;
479 return (address
>> PAGE_SHIFT
) & mask
;
482 /* Helper to counts the number of PTEs within the given length. This count
483 * does not cross a page table boundary, so the max value would be
484 * GEN6_PTES for GEN6, and GEN8_PTES for GEN8.
486 static inline uint32_t i915_pte_count(uint64_t addr
, size_t length
,
489 const uint64_t mask
= ~((1ULL << pde_shift
) - 1);
492 WARN_ON(length
== 0);
493 WARN_ON(offset_in_page(addr
|length
));
497 if ((addr
& mask
) != (end
& mask
))
498 return NUM_PTE(pde_shift
) - i915_pte_index(addr
, pde_shift
);
500 return i915_pte_index(end
, pde_shift
) - i915_pte_index(addr
, pde_shift
);
503 static inline uint32_t i915_pde_index(uint64_t addr
, uint32_t shift
)
505 return (addr
>> shift
) & I915_PDE_MASK
;
508 static inline uint32_t gen6_pte_index(uint32_t addr
)
510 return i915_pte_index(addr
, GEN6_PDE_SHIFT
);
513 static inline size_t gen6_pte_count(uint32_t addr
, uint32_t length
)
515 return i915_pte_count(addr
, length
, GEN6_PDE_SHIFT
);
518 static inline uint32_t gen6_pde_index(uint32_t addr
)
520 return i915_pde_index(addr
, GEN6_PDE_SHIFT
);
523 /* Equivalent to the gen6 version, For each pde iterates over every pde
524 * between from start until start + length. On gen8+ it simply iterates
525 * over every page directory entry in a page directory.
527 #define gen8_for_each_pde(pt, pd, start, length, iter) \
528 for (iter = gen8_pde_index(start); \
529 length > 0 && iter < I915_PDES && \
530 (pt = (pd)->page_table[iter], true); \
531 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT); \
532 temp = min(temp - start, length); \
533 start += temp, length -= temp; }), ++iter)
535 #define gen8_for_each_pdpe(pd, pdp, start, length, iter) \
536 for (iter = gen8_pdpe_index(start); \
537 length > 0 && iter < I915_PDPES_PER_PDP(dev) && \
538 (pd = (pdp)->page_directory[iter], true); \
539 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT); \
540 temp = min(temp - start, length); \
541 start += temp, length -= temp; }), ++iter)
543 #define gen8_for_each_pml4e(pdp, pml4, start, length, iter) \
544 for (iter = gen8_pml4e_index(start); \
545 length > 0 && iter < GEN8_PML4ES_PER_PML4 && \
546 (pdp = (pml4)->pdps[iter], true); \
547 ({ u64 temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT); \
548 temp = min(temp - start, length); \
549 start += temp, length -= temp; }), ++iter)
551 static inline uint32_t gen8_pte_index(uint64_t address
)
553 return i915_pte_index(address
, GEN8_PDE_SHIFT
);
556 static inline uint32_t gen8_pde_index(uint64_t address
)
558 return i915_pde_index(address
, GEN8_PDE_SHIFT
);
561 static inline uint32_t gen8_pdpe_index(uint64_t address
)
563 return (address
>> GEN8_PDPE_SHIFT
) & GEN8_PDPE_MASK
;
566 static inline uint32_t gen8_pml4e_index(uint64_t address
)
568 return (address
>> GEN8_PML4E_SHIFT
) & GEN8_PML4E_MASK
;
571 static inline size_t gen8_pte_count(uint64_t address
, uint64_t length
)
573 return i915_pte_count(address
, length
, GEN8_PDE_SHIFT
);
576 static inline dma_addr_t
577 i915_page_dir_dma_addr(const struct i915_hw_ppgtt
*ppgtt
, const unsigned n
)
579 return test_bit(n
, ppgtt
->pdp
.used_pdpes
) ?
580 px_dma(ppgtt
->pdp
.page_directory
[n
]) :
581 px_dma(ppgtt
->base
.scratch_pd
);
584 int i915_ggtt_probe_hw(struct drm_i915_private
*dev_priv
);
585 int i915_ggtt_init_hw(struct drm_i915_private
*dev_priv
);
586 int i915_ggtt_enable_hw(struct drm_i915_private
*dev_priv
);
587 int i915_gem_init_ggtt(struct drm_i915_private
*dev_priv
);
588 void i915_ggtt_cleanup_hw(struct drm_i915_private
*dev_priv
);
590 int i915_ppgtt_init_hw(struct drm_device
*dev
);
591 void i915_ppgtt_release(struct kref
*kref
);
592 struct i915_hw_ppgtt
*i915_ppgtt_create(struct drm_i915_private
*dev_priv
,
593 struct drm_i915_file_private
*fpriv
);
594 static inline void i915_ppgtt_get(struct i915_hw_ppgtt
*ppgtt
)
597 kref_get(&ppgtt
->ref
);
599 static inline void i915_ppgtt_put(struct i915_hw_ppgtt
*ppgtt
)
602 kref_put(&ppgtt
->ref
, i915_ppgtt_release
);
605 void i915_check_and_clear_faults(struct drm_i915_private
*dev_priv
);
606 void i915_gem_suspend_gtt_mappings(struct drm_device
*dev
);
607 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
);
609 int __must_check
i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
);
610 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
);
613 i915_ggtt_view_equal(const struct i915_ggtt_view
*a
,
614 const struct i915_ggtt_view
*b
)
616 if (WARN_ON(!a
|| !b
))
619 if (a
->type
!= b
->type
)
621 if (a
->type
!= I915_GGTT_VIEW_NORMAL
)
622 return !memcmp(&a
->params
, &b
->params
, sizeof(a
->params
));
626 /* Flags used by pin/bind&friends. */
627 #define PIN_NONBLOCK BIT(0)
628 #define PIN_MAPPABLE BIT(1)
629 #define PIN_ZONE_4G BIT(2)
631 #define PIN_MBZ BIT(5) /* I915_VMA_PIN_OVERFLOW */
632 #define PIN_GLOBAL BIT(6) /* I915_VMA_GLOBAL_BIND */
633 #define PIN_USER BIT(7) /* I915_VMA_LOCAL_BIND */
634 #define PIN_UPDATE BIT(8)
636 #define PIN_HIGH BIT(9)
637 #define PIN_OFFSET_BIAS BIT(10)
638 #define PIN_OFFSET_FIXED BIT(11)
639 #define PIN_OFFSET_MASK (~4095)
641 int __i915_vma_do_pin(struct i915_vma
*vma
,
642 u64 size
, u64 alignment
, u64 flags
);
643 static inline int __must_check
644 i915_vma_pin(struct i915_vma
*vma
, u64 size
, u64 alignment
, u64 flags
)
646 BUILD_BUG_ON(PIN_MBZ
!= I915_VMA_PIN_OVERFLOW
);
647 BUILD_BUG_ON(PIN_GLOBAL
!= I915_VMA_GLOBAL_BIND
);
648 BUILD_BUG_ON(PIN_USER
!= I915_VMA_LOCAL_BIND
);
650 /* Pin early to prevent the shrinker/eviction logic from destroying
651 * our vma as we insert and bind.
653 if (likely(((++vma
->flags
^ flags
) & I915_VMA_BIND_MASK
) == 0))
656 return __i915_vma_do_pin(vma
, size
, alignment
, flags
);
659 static inline int i915_vma_pin_count(const struct i915_vma
*vma
)
661 return vma
->flags
& I915_VMA_PIN_MASK
;
664 static inline bool i915_vma_is_pinned(const struct i915_vma
*vma
)
666 return i915_vma_pin_count(vma
);
669 static inline void __i915_vma_pin(struct i915_vma
*vma
)
672 GEM_BUG_ON(vma
->flags
& I915_VMA_PIN_OVERFLOW
);
675 static inline void __i915_vma_unpin(struct i915_vma
*vma
)
677 GEM_BUG_ON(!i915_vma_is_pinned(vma
));
681 static inline void i915_vma_unpin(struct i915_vma
*vma
)
683 GEM_BUG_ON(!drm_mm_node_allocated(&vma
->node
));
684 __i915_vma_unpin(vma
);
688 * i915_vma_pin_iomap - calls ioremap_wc to map the GGTT VMA via the aperture
691 * The passed in VMA has to be pinned in the global GTT mappable region.
692 * An extra pinning of the VMA is acquired for the return iomapping,
693 * the caller must call i915_vma_unpin_iomap to relinquish the pinning
694 * after the iomapping is no longer required.
696 * Callers must hold the struct_mutex.
698 * Returns a valid iomapped pointer or ERR_PTR.
700 void __iomem
*i915_vma_pin_iomap(struct i915_vma
*vma
);
701 #define IO_ERR_PTR(x) ((void __iomem *)ERR_PTR(x))
704 * i915_vma_unpin_iomap - unpins the mapping returned from i915_vma_iomap
707 * Unpins the previously iomapped VMA from i915_vma_pin_iomap().
709 * Callers must hold the struct_mutex. This function is only valid to be
710 * called on a VMA previously iomapped by the caller with i915_vma_pin_iomap().
712 static inline void i915_vma_unpin_iomap(struct i915_vma
*vma
)
714 lockdep_assert_held(&vma
->vm
->dev
->struct_mutex
);
715 GEM_BUG_ON(vma
->iomap
== NULL
);
719 static inline struct page
*i915_vma_first_page(struct i915_vma
*vma
)
721 GEM_BUG_ON(!vma
->pages
);
722 return sg_page(vma
->pages
->sgl
);