2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * Please try to maintain the following order within this file unless it makes
24 * sense to do otherwise. From top to bottom:
26 * 2. #defines, and macros
27 * 3. structure definitions
28 * 4. function prototypes
30 * Within each section, please try to order by generation in ascending order,
31 * from top to bottom (ie. gen6 on the top, gen8 on the bottom).
34 #ifndef __I915_GEM_GTT_H__
35 #define __I915_GEM_GTT_H__
37 struct drm_i915_file_private
;
39 typedef uint32_t gen6_pte_t
;
40 typedef uint64_t gen8_pte_t
;
41 typedef uint64_t gen8_pde_t
;
42 typedef uint64_t gen8_ppgtt_pdpe_t
;
43 typedef uint64_t gen8_ppgtt_pml4e_t
;
45 #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT)
47 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */
48 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
49 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
50 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
51 #define GEN6_PTE_CACHE_LLC (2 << 1)
52 #define GEN6_PTE_UNCACHED (1 << 1)
53 #define GEN6_PTE_VALID (1 << 0)
55 #define I915_PTES(pte_len) (PAGE_SIZE / (pte_len))
56 #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1)
58 #define I915_PDE_MASK (I915_PDES - 1)
59 #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT))
61 #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t))
62 #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE)
63 #define GEN6_PD_ALIGN (PAGE_SIZE * 16)
64 #define GEN6_PDE_SHIFT 22
65 #define GEN6_PDE_VALID (1 << 0)
67 #define GEN7_PTE_CACHE_L3_LLC (3 << 1)
69 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2)
70 #define BYT_PTE_WRITEABLE (1 << 1)
72 /* Cacheability Control is a 4-bit value. The low three bits are stored in bits
73 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
75 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \
76 (((bits) & 0x8) << (11 - 3)))
77 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2)
78 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3)
79 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8)
80 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb)
81 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7)
82 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6)
83 #define HSW_PTE_UNCACHED (0)
84 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0))
85 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr)
87 /* GEN8 legacy style address is defined as a 3 level page table:
88 * 31:30 | 29:21 | 20:12 | 11:0
89 * PDPE | PDE | PTE | offset
90 * The difference as compared to normal x86 3 level page table is the PDPEs are
91 * programmed via register.
93 * GEN8 48b legacy style address is defined as a 4 level page table:
94 * 47:39 | 38:30 | 29:21 | 20:12 | 11:0
95 * PML4E | PDPE | PDE | PTE | offset
97 #define GEN8_PML4ES_PER_PML4 512
98 #define GEN8_PML4E_SHIFT 39
99 #define GEN8_PML4E_MASK (GEN8_PML4ES_PER_PML4 - 1)
100 #define GEN8_PDPE_SHIFT 30
101 /* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page
103 #define GEN8_PDPE_MASK 0x1ff
104 #define GEN8_PDE_SHIFT 21
105 #define GEN8_PDE_MASK 0x1ff
106 #define GEN8_PTE_SHIFT 12
107 #define GEN8_PTE_MASK 0x1ff
108 #define GEN8_LEGACY_PDPES 4
109 #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t))
111 #define I915_PDPES_PER_PDP(dev) (USES_FULL_48BIT_PPGTT(dev) ?\
112 GEN8_PML4ES_PER_PML4 : GEN8_LEGACY_PDPES)
114 #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD)
115 #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */
116 #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */
117 #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */
119 #define CHV_PPAT_SNOOP (1<<6)
120 #define GEN8_PPAT_AGE(x) (x<<4)
121 #define GEN8_PPAT_LLCeLLC (3<<2)
122 #define GEN8_PPAT_LLCELLC (2<<2)
123 #define GEN8_PPAT_LLC (1<<2)
124 #define GEN8_PPAT_WB (3<<0)
125 #define GEN8_PPAT_WT (2<<0)
126 #define GEN8_PPAT_WC (1<<0)
127 #define GEN8_PPAT_UC (0<<0)
128 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
129 #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8))
131 enum i915_ggtt_view_type
{
132 I915_GGTT_VIEW_NORMAL
= 0,
133 I915_GGTT_VIEW_ROTATED
,
134 I915_GGTT_VIEW_PARTIAL
,
137 struct intel_rotation_info
{
140 unsigned int uv_offset
;
141 uint32_t pixel_format
;
142 uint64_t fb_modifier
;
143 unsigned int width_pages
, height_pages
;
145 unsigned int width_pages_uv
, height_pages_uv
;
147 unsigned int uv_start_page
;
150 struct i915_ggtt_view
{
151 enum i915_ggtt_view_type type
;
158 struct intel_rotation_info rotation_info
;
161 struct sg_table
*pages
;
164 extern const struct i915_ggtt_view i915_ggtt_view_normal
;
165 extern const struct i915_ggtt_view i915_ggtt_view_rotated
;
167 enum i915_cache_level
;
170 * A VMA represents a GEM BO that is bound into an address space. Therefore, a
171 * VMA's presence cannot be guaranteed before binding, or after unbinding the
172 * object into/from the address space.
174 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime
175 * will always be <= an objects lifetime. So object refcounting should cover us.
178 struct drm_mm_node node
;
179 struct drm_i915_gem_object
*obj
;
180 struct i915_address_space
*vm
;
182 /** Flags and address space this VMA is bound to */
183 #define GLOBAL_BIND (1<<0)
184 #define LOCAL_BIND (1<<1)
185 unsigned int bound
: 4;
188 * Support different GGTT views into the same object.
189 * This means there can be multiple VMA mappings per object and per VM.
190 * i915_ggtt_view_type is used to distinguish between those entries.
191 * The default one of zero (I915_GGTT_VIEW_NORMAL) is default and also
192 * assumed in GEM functions which take no ggtt view parameter.
194 struct i915_ggtt_view ggtt_view
;
196 /** This object's place on the active/inactive lists */
197 struct list_head mm_list
;
199 struct list_head vma_link
; /* Link in the object's VMA list */
201 /** This vma's place in the batchbuffer or on the eviction list */
202 struct list_head exec_list
;
205 * Used for performing relocations during execbuffer insertion.
207 struct hlist_node exec_node
;
208 unsigned long exec_handle
;
209 struct drm_i915_gem_exec_object2
*exec_entry
;
212 * How many users have pinned this object in GTT space. The following
213 * users can each hold at most one reference: pwrite/pread, execbuffer
214 * (objects are not allowed multiple times for the same batchbuffer),
215 * and the framebuffer code. When switching/pageflipping, the
216 * framebuffer code has at most two buffers pinned per crtc.
218 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
219 * bits with absolutely no headroom. So use 4 bits. */
220 unsigned int pin_count
:4;
221 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
224 struct i915_page_dma
{
229 /* For gen6/gen7 only. This is the offset in the GGTT
230 * where the page directory entries for PPGTT begin
232 uint32_t ggtt_offset
;
236 #define px_base(px) (&(px)->base)
237 #define px_page(px) (px_base(px)->page)
238 #define px_dma(px) (px_base(px)->daddr)
240 struct i915_page_scratch
{
241 struct i915_page_dma base
;
244 struct i915_page_table
{
245 struct i915_page_dma base
;
247 unsigned long *used_ptes
;
250 struct i915_page_directory
{
251 struct i915_page_dma base
;
253 unsigned long *used_pdes
;
254 struct i915_page_table
*page_table
[I915_PDES
]; /* PDEs */
257 struct i915_page_directory_pointer
{
258 struct i915_page_dma base
;
260 unsigned long *used_pdpes
;
261 struct i915_page_directory
**page_directory
;
265 struct i915_page_dma base
;
267 DECLARE_BITMAP(used_pml4es
, GEN8_PML4ES_PER_PML4
);
268 struct i915_page_directory_pointer
*pdps
[GEN8_PML4ES_PER_PML4
];
271 struct i915_address_space
{
273 struct drm_device
*dev
;
274 struct list_head global_link
;
275 u64 start
; /* Start offset always 0 for dri2 */
276 u64 total
; /* size addr space maps (ex. 2GB for ggtt) */
278 struct i915_page_scratch
*scratch_page
;
279 struct i915_page_table
*scratch_pt
;
280 struct i915_page_directory
*scratch_pd
;
281 struct i915_page_directory_pointer
*scratch_pdp
; /* GEN8+ & 48b PPGTT */
284 * List of objects currently involved in rendering.
286 * Includes buffers having the contents of their GPU caches
287 * flushed, not necessarily primitives. last_read_req
288 * represents when the rendering involved will be completed.
290 * A reference is held on the buffer while on this list.
292 struct list_head active_list
;
295 * LRU list of objects which are not in the ringbuffer and
296 * are ready to unbind, but are still in the GTT.
298 * last_read_req is NULL while an object is in this list.
300 * A reference is not held on the buffer while on this list,
301 * as merely being GTT-bound shouldn't prevent its being
302 * freed, and we'll pull it off the list in the free path.
304 struct list_head inactive_list
;
306 /* FIXME: Need a more generic return type */
307 gen6_pte_t (*pte_encode
)(dma_addr_t addr
,
308 enum i915_cache_level level
,
309 bool valid
, u32 flags
); /* Create a valid PTE */
310 /* flags for pte_encode */
311 #define PTE_READ_ONLY (1<<0)
312 int (*allocate_va_range
)(struct i915_address_space
*vm
,
315 void (*clear_range
)(struct i915_address_space
*vm
,
319 void (*insert_entries
)(struct i915_address_space
*vm
,
322 enum i915_cache_level cache_level
, u32 flags
);
323 void (*cleanup
)(struct i915_address_space
*vm
);
324 /** Unmap an object from an address space. This usually consists of
325 * setting the valid PTE entries to a reserved scratch page. */
326 void (*unbind_vma
)(struct i915_vma
*vma
);
327 /* Map an object into an address space with the given cache flags. */
328 int (*bind_vma
)(struct i915_vma
*vma
,
329 enum i915_cache_level cache_level
,
333 /* The Graphics Translation Table is the way in which GEN hardware translates a
334 * Graphics Virtual Address into a Physical Address. In addition to the normal
335 * collateral associated with any va->pa translations GEN hardware also has a
336 * portion of the GTT which can be mapped by the CPU and remain both coherent
337 * and correct (in cases like swizzling). That region is referred to as GMADR in
341 struct i915_address_space base
;
343 size_t stolen_size
; /* Total size of stolen memory */
344 size_t stolen_usable_size
; /* Total size minus BIOS reserved */
345 u64 mappable_end
; /* End offset that we can CPU map */
346 struct io_mapping
*mappable
; /* Mapping to our CPU mappable region */
347 phys_addr_t mappable_base
; /* PA of our GMADR */
349 /** "Graphics Stolen Memory" holds the global PTEs */
357 int (*gtt_probe
)(struct drm_device
*dev
, u64
*gtt_total
,
358 size_t *stolen
, phys_addr_t
*mappable_base
,
362 struct i915_hw_ppgtt
{
363 struct i915_address_space base
;
365 struct drm_mm_node node
;
366 unsigned long pd_dirty_rings
;
368 struct i915_pml4 pml4
; /* GEN8+ & 48b PPGTT */
369 struct i915_page_directory_pointer pdp
; /* GEN8+ */
370 struct i915_page_directory pd
; /* GEN6-7 */
373 struct drm_i915_file_private
*file_priv
;
375 gen6_pte_t __iomem
*pd_addr
;
377 int (*enable
)(struct i915_hw_ppgtt
*ppgtt
);
378 int (*switch_mm
)(struct i915_hw_ppgtt
*ppgtt
,
379 struct drm_i915_gem_request
*req
);
380 void (*debug_dump
)(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
);
383 /* For each pde iterates over every pde between from start until start + length.
384 * If start, and start+length are not perfectly divisible, the macro will round
385 * down, and up as needed. The macro modifies pde, start, and length. Dev is
386 * only used to differentiate shift values. Temp is temp. On gen6/7, start = 0,
387 * and length = 2G effectively iterates over every PDE in the system.
389 * XXX: temp is not actually needed, but it saves doing the ALIGN operation.
391 #define gen6_for_each_pde(pt, pd, start, length, temp, iter) \
392 for (iter = gen6_pde_index(start); \
393 length > 0 && iter < I915_PDES ? \
394 (pt = (pd)->page_table[iter]), 1 : 0; \
396 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT) - start, \
397 temp = min_t(unsigned, temp, length), \
398 start += temp, length -= temp)
400 #define gen6_for_all_pdes(pt, ppgtt, iter) \
402 pt = ppgtt->pd.page_table[iter], iter < I915_PDES; \
405 static inline uint32_t i915_pte_index(uint64_t address
, uint32_t pde_shift
)
407 const uint32_t mask
= NUM_PTE(pde_shift
) - 1;
409 return (address
>> PAGE_SHIFT
) & mask
;
412 /* Helper to counts the number of PTEs within the given length. This count
413 * does not cross a page table boundary, so the max value would be
414 * GEN6_PTES for GEN6, and GEN8_PTES for GEN8.
416 static inline uint32_t i915_pte_count(uint64_t addr
, size_t length
,
419 const uint64_t mask
= ~((1 << pde_shift
) - 1);
422 WARN_ON(length
== 0);
423 WARN_ON(offset_in_page(addr
|length
));
427 if ((addr
& mask
) != (end
& mask
))
428 return NUM_PTE(pde_shift
) - i915_pte_index(addr
, pde_shift
);
430 return i915_pte_index(end
, pde_shift
) - i915_pte_index(addr
, pde_shift
);
433 static inline uint32_t i915_pde_index(uint64_t addr
, uint32_t shift
)
435 return (addr
>> shift
) & I915_PDE_MASK
;
438 static inline uint32_t gen6_pte_index(uint32_t addr
)
440 return i915_pte_index(addr
, GEN6_PDE_SHIFT
);
443 static inline size_t gen6_pte_count(uint32_t addr
, uint32_t length
)
445 return i915_pte_count(addr
, length
, GEN6_PDE_SHIFT
);
448 static inline uint32_t gen6_pde_index(uint32_t addr
)
450 return i915_pde_index(addr
, GEN6_PDE_SHIFT
);
453 /* Equivalent to the gen6 version, For each pde iterates over every pde
454 * between from start until start + length. On gen8+ it simply iterates
455 * over every page directory entry in a page directory.
457 #define gen8_for_each_pde(pt, pd, start, length, iter) \
458 for (iter = gen8_pde_index(start); \
459 length > 0 && iter < I915_PDES && \
460 (pt = (pd)->page_table[iter], true); \
461 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT); \
462 temp = min(temp - start, length); \
463 start += temp, length -= temp; }), ++iter)
465 #define gen8_for_each_pdpe(pd, pdp, start, length, iter) \
466 for (iter = gen8_pdpe_index(start); \
467 length > 0 && iter < I915_PDPES_PER_PDP(dev) && \
468 (pd = (pdp)->page_directory[iter], true); \
469 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT); \
470 temp = min(temp - start, length); \
471 start += temp, length -= temp; }), ++iter)
473 #define gen8_for_each_pml4e(pdp, pml4, start, length, iter) \
474 for (iter = gen8_pml4e_index(start); \
475 length > 0 && iter < GEN8_PML4ES_PER_PML4 && \
476 (pdp = (pml4)->pdps[iter], true); \
477 ({ u64 temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT); \
478 temp = min(temp - start, length); \
479 start += temp, length -= temp; }), ++iter)
481 static inline uint32_t gen8_pte_index(uint64_t address
)
483 return i915_pte_index(address
, GEN8_PDE_SHIFT
);
486 static inline uint32_t gen8_pde_index(uint64_t address
)
488 return i915_pde_index(address
, GEN8_PDE_SHIFT
);
491 static inline uint32_t gen8_pdpe_index(uint64_t address
)
493 return (address
>> GEN8_PDPE_SHIFT
) & GEN8_PDPE_MASK
;
496 static inline uint32_t gen8_pml4e_index(uint64_t address
)
498 return (address
>> GEN8_PML4E_SHIFT
) & GEN8_PML4E_MASK
;
501 static inline size_t gen8_pte_count(uint64_t address
, uint64_t length
)
503 return i915_pte_count(address
, length
, GEN8_PDE_SHIFT
);
506 static inline dma_addr_t
507 i915_page_dir_dma_addr(const struct i915_hw_ppgtt
*ppgtt
, const unsigned n
)
509 return test_bit(n
, ppgtt
->pdp
.used_pdpes
) ?
510 px_dma(ppgtt
->pdp
.page_directory
[n
]) :
511 px_dma(ppgtt
->base
.scratch_pd
);
514 int i915_gem_gtt_init(struct drm_device
*dev
);
515 void i915_gem_init_global_gtt(struct drm_device
*dev
);
516 void i915_global_gtt_cleanup(struct drm_device
*dev
);
519 int i915_ppgtt_init(struct drm_device
*dev
, struct i915_hw_ppgtt
*ppgtt
);
520 int i915_ppgtt_init_hw(struct drm_device
*dev
);
521 int i915_ppgtt_init_ring(struct drm_i915_gem_request
*req
);
522 void i915_ppgtt_release(struct kref
*kref
);
523 struct i915_hw_ppgtt
*i915_ppgtt_create(struct drm_device
*dev
,
524 struct drm_i915_file_private
*fpriv
);
525 static inline void i915_ppgtt_get(struct i915_hw_ppgtt
*ppgtt
)
528 kref_get(&ppgtt
->ref
);
530 static inline void i915_ppgtt_put(struct i915_hw_ppgtt
*ppgtt
)
533 kref_put(&ppgtt
->ref
, i915_ppgtt_release
);
536 void i915_check_and_clear_faults(struct drm_device
*dev
);
537 void i915_gem_suspend_gtt_mappings(struct drm_device
*dev
);
538 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
);
540 int __must_check
i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
);
541 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
);
544 i915_ggtt_view_equal(const struct i915_ggtt_view
*a
,
545 const struct i915_ggtt_view
*b
)
547 if (WARN_ON(!a
|| !b
))
550 if (a
->type
!= b
->type
)
552 if (a
->type
!= I915_GGTT_VIEW_NORMAL
)
553 return !memcmp(&a
->params
, &b
->params
, sizeof(a
->params
));
558 i915_ggtt_view_size(struct drm_i915_gem_object
*obj
,
559 const struct i915_ggtt_view
*view
);