2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Mika Kuoppala <mika.kuoppala@intel.com>
29 #include "intel_renderstate.h"
31 struct i915_render_state
{
32 struct drm_i915_gem_object
*obj
;
33 unsigned long ggtt_offset
;
39 static struct i915_render_state
*render_state_alloc(struct drm_device
*dev
)
41 struct i915_render_state
*so
;
45 so
= kzalloc(sizeof(*so
), GFP_KERNEL
);
47 return ERR_PTR(-ENOMEM
);
49 so
->obj
= i915_gem_alloc_object(dev
, 4096);
50 if (so
->obj
== NULL
) {
56 ret
= i915_gem_obj_ggtt_pin(so
->obj
, 4096, 0);
60 BUG_ON(so
->obj
->pages
->nents
!= 1);
61 page
= sg_page(so
->obj
->pages
->sgl
);
63 so
->batch
= kmap(page
);
69 so
->ggtt_offset
= i915_gem_obj_ggtt_offset(so
->obj
);
73 i915_gem_object_ggtt_unpin(so
->obj
);
75 drm_gem_object_unreference(&so
->obj
->base
);
81 static void render_state_free(struct i915_render_state
*so
)
84 i915_gem_object_ggtt_unpin(so
->obj
);
85 drm_gem_object_unreference(&so
->obj
->base
);
89 static const struct intel_renderstate_rodata
*
90 render_state_get_rodata(struct drm_device
*dev
, const int gen
)
94 return &gen6_null_state
;
96 return &gen7_null_state
;
98 return &gen8_null_state
;
104 static int render_state_setup(const int gen
,
105 const struct intel_renderstate_rodata
*rodata
,
106 struct i915_render_state
*so
)
108 const u64 goffset
= i915_gem_obj_ggtt_offset(so
->obj
);
110 u32
* const d
= so
->batch
;
114 if (!rodata
|| rodata
->batch_items
* 4 > so
->size
)
117 ret
= i915_gem_object_set_to_cpu_domain(so
->obj
, true);
121 while (i
< rodata
->batch_items
) {
122 u32 s
= rodata
->batch
[i
];
124 if (reloc_index
< rodata
->reloc_items
&&
125 i
* 4 == rodata
->reloc
[reloc_index
]) {
127 s
+= goffset
& 0xffffffff;
129 /* We keep batch offsets max 32bit */
131 if (i
+ 1 >= rodata
->batch_items
||
132 rodata
->batch
[i
+ 1] != 0)
137 s
= (goffset
& 0xffffffff00000000ull
) >> 32;
147 ret
= i915_gem_object_set_to_gtt_domain(so
->obj
, false);
151 if (rodata
->reloc_items
!= reloc_index
) {
152 DRM_ERROR("not all relocs resolved, %d out of %d\n",
153 reloc_index
, rodata
->reloc_items
);
157 so
->len
= rodata
->batch_items
* 4;
162 int i915_gem_render_state_init(struct intel_engine_cs
*ring
)
164 const int gen
= INTEL_INFO(ring
->dev
)->gen
;
165 struct i915_render_state
*so
;
166 const struct intel_renderstate_rodata
*rodata
;
169 if (WARN_ON(ring
->id
!= RCS
))
172 rodata
= render_state_get_rodata(ring
->dev
, gen
);
176 so
= render_state_alloc(ring
->dev
);
180 ret
= render_state_setup(gen
, rodata
, so
);
184 ret
= ring
->dispatch_execbuffer(ring
,
185 i915_gem_obj_ggtt_offset(so
->obj
),
187 I915_DISPATCH_SECURE
);
191 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so
->obj
), ring
);
193 ret
= __i915_add_request(ring
, NULL
, so
->obj
, NULL
);
194 /* __i915_add_request moves object to inactive if it fails */
196 render_state_free(so
);
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