2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Mika Kuoppala <mika.kuoppala@intel.com>
29 #include "intel_renderstate.h"
31 static const struct intel_renderstate_rodata
*
32 render_state_get_rodata(const int gen
)
36 return &gen6_null_state
;
38 return &gen7_null_state
;
40 return &gen8_null_state
;
42 return &gen9_null_state
;
48 static int render_state_init(struct render_state
*so
,
49 struct drm_i915_private
*dev_priv
)
53 so
->gen
= INTEL_GEN(dev_priv
);
54 so
->rodata
= render_state_get_rodata(so
->gen
);
55 if (so
->rodata
== NULL
)
58 if (so
->rodata
->batch_items
* 4 > 4096)
61 so
->obj
= i915_gem_object_create(&dev_priv
->drm
, 4096);
63 return PTR_ERR(so
->obj
);
65 ret
= i915_gem_obj_ggtt_pin(so
->obj
, 4096, 0);
69 so
->ggtt_offset
= i915_gem_obj_ggtt_offset(so
->obj
);
73 i915_gem_object_put(so
->obj
);
78 * Macro to add commands to auxiliary batch.
79 * This macro only checks for page overflow before inserting the commands,
80 * this is sufficient as the null state generator makes the final batch
81 * with two passes to build command and state separately. At this point
82 * the size of both are known and it compacts them by relocating the state
83 * right after the commands taking care of aligment so we should sufficient
84 * space below them for adding new commands.
86 #define OUT_BATCH(batch, i, val) \
88 if (WARN_ON((i) >= PAGE_SIZE / sizeof(u32))) { \
92 (batch)[(i)++] = (val); \
95 static int render_state_setup(struct render_state
*so
)
97 struct drm_device
*dev
= so
->obj
->base
.dev
;
98 const struct intel_renderstate_rodata
*rodata
= so
->rodata
;
99 unsigned int i
= 0, reloc_index
= 0;
104 ret
= i915_gem_object_set_to_cpu_domain(so
->obj
, true);
108 page
= i915_gem_object_get_dirty_page(so
->obj
, 0);
111 while (i
< rodata
->batch_items
) {
112 u32 s
= rodata
->batch
[i
];
114 if (i
* 4 == rodata
->reloc
[reloc_index
]) {
115 u64 r
= s
+ so
->ggtt_offset
;
116 s
= lower_32_bits(r
);
118 if (i
+ 1 >= rodata
->batch_items
||
119 rodata
->batch
[i
+ 1] != 0) {
125 s
= upper_32_bits(r
);
134 while (i
% CACHELINE_DWORDS
)
135 OUT_BATCH(d
, i
, MI_NOOP
);
137 so
->aux_batch_offset
= i
* sizeof(u32
);
139 if (HAS_POOLED_EU(dev
)) {
141 * We always program 3x6 pool config but depending upon which
142 * subslice is disabled HW drops down to appropriate config
145 * In the below table 2x6 config always refers to
146 * fused-down version, native 2x6 is not available and can
149 * SNo subslices config eu pool configuration
150 * -----------------------------------------------------------
151 * 1 3 subslices enabled (3x6) - 0x00777000 (9+9)
152 * 2 ss0 disabled (2x6) - 0x00777000 (3+9)
153 * 3 ss1 disabled (2x6) - 0x00770000 (6+6)
154 * 4 ss2 disabled (2x6) - 0x00007000 (9+3)
156 u32 eu_pool_config
= 0x00777000;
158 OUT_BATCH(d
, i
, GEN9_MEDIA_POOL_STATE
);
159 OUT_BATCH(d
, i
, GEN9_MEDIA_POOL_ENABLE
);
160 OUT_BATCH(d
, i
, eu_pool_config
);
166 OUT_BATCH(d
, i
, MI_BATCH_BUFFER_END
);
167 so
->aux_batch_size
= (i
* sizeof(u32
)) - so
->aux_batch_offset
;
170 * Since we are sending length, we need to strictly conform to
171 * all requirements. For Gen2 this must be a multiple of 8.
173 so
->aux_batch_size
= ALIGN(so
->aux_batch_size
, 8);
177 ret
= i915_gem_object_set_to_gtt_domain(so
->obj
, false);
181 if (rodata
->reloc
[reloc_index
] != -1) {
182 DRM_ERROR("only %d relocs resolved\n", reloc_index
);
195 void i915_gem_render_state_fini(struct render_state
*so
)
197 i915_gem_object_ggtt_unpin(so
->obj
);
198 i915_gem_object_put(so
->obj
);
201 int i915_gem_render_state_prepare(struct intel_engine_cs
*engine
,
202 struct render_state
*so
)
206 if (WARN_ON(engine
->id
!= RCS
))
209 ret
= render_state_init(so
, engine
->i915
);
213 if (so
->rodata
== NULL
)
216 ret
= render_state_setup(so
);
218 i915_gem_render_state_fini(so
);
225 int i915_gem_render_state_init(struct drm_i915_gem_request
*req
)
227 struct render_state so
;
230 ret
= i915_gem_render_state_prepare(req
->engine
, &so
);
234 if (so
.rodata
== NULL
)
237 ret
= req
->engine
->dispatch_execbuffer(req
, so
.ggtt_offset
,
238 so
.rodata
->batch_items
* 4,
239 I915_DISPATCH_SECURE
);
243 if (so
.aux_batch_size
> 8) {
244 ret
= req
->engine
->dispatch_execbuffer(req
,
246 so
.aux_batch_offset
),
248 I915_DISPATCH_SECURE
);
253 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so
.obj
), req
);
256 i915_gem_render_state_fini(&so
);
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