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7c478e6cedaec2195519f9fe6cf4c708a663ea1c
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gpu_error.c
1 /*
2 * Copyright (c) 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 * Mika Kuoppala <mika.kuoppala@intel.com>
27 *
28 */
29
30 #include <generated/utsrelease.h>
31 #include "i915_drv.h"
32
33 static const char *yesno(int v)
34 {
35 return v ? "yes" : "no";
36 }
37
38 static const char *ring_str(int ring)
39 {
40 switch (ring) {
41 case RCS: return "render";
42 case VCS: return "bsd";
43 case BCS: return "blt";
44 case VECS: return "vebox";
45 case VCS2: return "bsd2";
46 default: return "";
47 }
48 }
49
50 static const char *pin_flag(int pinned)
51 {
52 if (pinned > 0)
53 return " P";
54 else if (pinned < 0)
55 return " p";
56 else
57 return "";
58 }
59
60 static const char *tiling_flag(int tiling)
61 {
62 switch (tiling) {
63 default:
64 case I915_TILING_NONE: return "";
65 case I915_TILING_X: return " X";
66 case I915_TILING_Y: return " Y";
67 }
68 }
69
70 static const char *dirty_flag(int dirty)
71 {
72 return dirty ? " dirty" : "";
73 }
74
75 static const char *purgeable_flag(int purgeable)
76 {
77 return purgeable ? " purgeable" : "";
78 }
79
80 static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
81 {
82
83 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
84 e->err = -ENOSPC;
85 return false;
86 }
87
88 if (e->bytes == e->size - 1 || e->err)
89 return false;
90
91 return true;
92 }
93
94 static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
95 unsigned len)
96 {
97 if (e->pos + len <= e->start) {
98 e->pos += len;
99 return false;
100 }
101
102 /* First vsnprintf needs to fit in its entirety for memmove */
103 if (len >= e->size) {
104 e->err = -EIO;
105 return false;
106 }
107
108 return true;
109 }
110
111 static void __i915_error_advance(struct drm_i915_error_state_buf *e,
112 unsigned len)
113 {
114 /* If this is first printf in this window, adjust it so that
115 * start position matches start of the buffer
116 */
117
118 if (e->pos < e->start) {
119 const size_t off = e->start - e->pos;
120
121 /* Should not happen but be paranoid */
122 if (off > len || e->bytes) {
123 e->err = -EIO;
124 return;
125 }
126
127 memmove(e->buf, e->buf + off, len - off);
128 e->bytes = len - off;
129 e->pos = e->start;
130 return;
131 }
132
133 e->bytes += len;
134 e->pos += len;
135 }
136
137 static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
138 const char *f, va_list args)
139 {
140 unsigned len;
141
142 if (!__i915_error_ok(e))
143 return;
144
145 /* Seek the first printf which is hits start position */
146 if (e->pos < e->start) {
147 va_list tmp;
148
149 va_copy(tmp, args);
150 len = vsnprintf(NULL, 0, f, tmp);
151 va_end(tmp);
152
153 if (!__i915_error_seek(e, len))
154 return;
155 }
156
157 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
158 if (len >= e->size - e->bytes)
159 len = e->size - e->bytes - 1;
160
161 __i915_error_advance(e, len);
162 }
163
164 static void i915_error_puts(struct drm_i915_error_state_buf *e,
165 const char *str)
166 {
167 unsigned len;
168
169 if (!__i915_error_ok(e))
170 return;
171
172 len = strlen(str);
173
174 /* Seek the first printf which is hits start position */
175 if (e->pos < e->start) {
176 if (!__i915_error_seek(e, len))
177 return;
178 }
179
180 if (len >= e->size - e->bytes)
181 len = e->size - e->bytes - 1;
182 memcpy(e->buf + e->bytes, str, len);
183
184 __i915_error_advance(e, len);
185 }
186
187 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
188 #define err_puts(e, s) i915_error_puts(e, s)
189
190 static void print_error_buffers(struct drm_i915_error_state_buf *m,
191 const char *name,
192 struct drm_i915_error_buffer *err,
193 int count)
194 {
195 err_printf(m, "%s [%d]:\n", name, count);
196
197 while (count--) {
198 err_printf(m, " %08x %8u %02x %02x %x %x",
199 err->gtt_offset,
200 err->size,
201 err->read_domains,
202 err->write_domain,
203 err->rseqno, err->wseqno);
204 err_puts(m, pin_flag(err->pinned));
205 err_puts(m, tiling_flag(err->tiling));
206 err_puts(m, dirty_flag(err->dirty));
207 err_puts(m, purgeable_flag(err->purgeable));
208 err_puts(m, err->userptr ? " userptr" : "");
209 err_puts(m, err->ring != -1 ? " " : "");
210 err_puts(m, ring_str(err->ring));
211 err_puts(m, i915_cache_level_str(err->cache_level));
212
213 if (err->name)
214 err_printf(m, " (name: %d)", err->name);
215 if (err->fence_reg != I915_FENCE_REG_NONE)
216 err_printf(m, " (fence: %d)", err->fence_reg);
217
218 err_puts(m, "\n");
219 err++;
220 }
221 }
222
223 static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
224 {
225 switch (a) {
226 case HANGCHECK_IDLE:
227 return "idle";
228 case HANGCHECK_WAIT:
229 return "wait";
230 case HANGCHECK_ACTIVE:
231 return "active";
232 case HANGCHECK_ACTIVE_LOOP:
233 return "active (loop)";
234 case HANGCHECK_KICK:
235 return "kick";
236 case HANGCHECK_HUNG:
237 return "hung";
238 }
239
240 return "unknown";
241 }
242
243 static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
244 struct drm_device *dev,
245 struct drm_i915_error_ring *ring)
246 {
247 if (!ring->valid)
248 return;
249
250 err_printf(m, " HEAD: 0x%08x\n", ring->head);
251 err_printf(m, " TAIL: 0x%08x\n", ring->tail);
252 err_printf(m, " CTL: 0x%08x\n", ring->ctl);
253 err_printf(m, " HWS: 0x%08x\n", ring->hws);
254 err_printf(m, " ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd);
255 err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir);
256 err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr);
257 err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone);
258 if (INTEL_INFO(dev)->gen >= 4) {
259 err_printf(m, " BBADDR: 0x%08x %08x\n", (u32)(ring->bbaddr>>32), (u32)ring->bbaddr);
260 err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate);
261 err_printf(m, " INSTPS: 0x%08x\n", ring->instps);
262 }
263 err_printf(m, " INSTPM: 0x%08x\n", ring->instpm);
264 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ring->faddr),
265 lower_32_bits(ring->faddr));
266 if (INTEL_INFO(dev)->gen >= 6) {
267 err_printf(m, " RC PSMI: 0x%08x\n", ring->rc_psmi);
268 err_printf(m, " FAULT_REG: 0x%08x\n", ring->fault_reg);
269 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
270 ring->semaphore_mboxes[0],
271 ring->semaphore_seqno[0]);
272 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
273 ring->semaphore_mboxes[1],
274 ring->semaphore_seqno[1]);
275 if (HAS_VEBOX(dev)) {
276 err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n",
277 ring->semaphore_mboxes[2],
278 ring->semaphore_seqno[2]);
279 }
280 }
281 if (USES_PPGTT(dev)) {
282 err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode);
283
284 if (INTEL_INFO(dev)->gen >= 8) {
285 int i;
286 for (i = 0; i < 4; i++)
287 err_printf(m, " PDP%d: 0x%016llx\n",
288 i, ring->vm_info.pdp[i]);
289 } else {
290 err_printf(m, " PP_DIR_BASE: 0x%08x\n",
291 ring->vm_info.pp_dir_base);
292 }
293 }
294 err_printf(m, " seqno: 0x%08x\n", ring->seqno);
295 err_printf(m, " waiting: %s\n", yesno(ring->waiting));
296 err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head);
297 err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail);
298 err_printf(m, " hangcheck: %s [%d]\n",
299 hangcheck_action_to_str(ring->hangcheck_action),
300 ring->hangcheck_score);
301 }
302
303 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
304 {
305 va_list args;
306
307 va_start(args, f);
308 i915_error_vprintf(e, f, args);
309 va_end(args);
310 }
311
312 static void print_error_obj(struct drm_i915_error_state_buf *m,
313 struct drm_i915_error_object *obj)
314 {
315 int page, offset, elt;
316
317 for (page = offset = 0; page < obj->page_count; page++) {
318 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
319 err_printf(m, "%08x : %08x\n", offset,
320 obj->pages[page][elt]);
321 offset += 4;
322 }
323 }
324 }
325
326 int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
327 const struct i915_error_state_file_priv *error_priv)
328 {
329 struct drm_device *dev = error_priv->dev;
330 struct drm_i915_private *dev_priv = dev->dev_private;
331 struct drm_i915_error_state *error = error_priv->error;
332 struct drm_i915_error_object *obj;
333 int i, j, offset, elt;
334 int max_hangcheck_score;
335
336 if (!error) {
337 err_printf(m, "no error state collected\n");
338 goto out;
339 }
340
341 err_printf(m, "%s\n", error->error_msg);
342 err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
343 error->time.tv_usec);
344 err_printf(m, "Kernel: " UTS_RELEASE "\n");
345 max_hangcheck_score = 0;
346 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
347 if (error->ring[i].hangcheck_score > max_hangcheck_score)
348 max_hangcheck_score = error->ring[i].hangcheck_score;
349 }
350 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
351 if (error->ring[i].hangcheck_score == max_hangcheck_score &&
352 error->ring[i].pid != -1) {
353 err_printf(m, "Active process (on ring %s): %s [%d]\n",
354 ring_str(i),
355 error->ring[i].comm,
356 error->ring[i].pid);
357 }
358 }
359 err_printf(m, "Reset count: %u\n", error->reset_count);
360 err_printf(m, "Suspend count: %u\n", error->suspend_count);
361 err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
362 err_printf(m, "EIR: 0x%08x\n", error->eir);
363 err_printf(m, "IER: 0x%08x\n", error->ier);
364 if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
365 err_printf(m, "GTIER: 0x%08x\n", error->gtier);
366 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
367 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
368 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
369 err_printf(m, "CCID: 0x%08x\n", error->ccid);
370 err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
371
372 for (i = 0; i < dev_priv->num_fence_regs; i++)
373 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
374
375 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
376 err_printf(m, " INSTDONE_%d: 0x%08x\n", i,
377 error->extra_instdone[i]);
378
379 if (INTEL_INFO(dev)->gen >= 6) {
380 err_printf(m, "ERROR: 0x%08x\n", error->error);
381 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
382 }
383
384 if (INTEL_INFO(dev)->gen == 7)
385 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
386
387 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
388 err_printf(m, "%s command stream:\n", ring_str(i));
389 i915_ring_error_state(m, dev, &error->ring[i]);
390 }
391
392 if (error->active_bo)
393 print_error_buffers(m, "Active",
394 error->active_bo[0],
395 error->active_bo_count[0]);
396
397 if (error->pinned_bo)
398 print_error_buffers(m, "Pinned",
399 error->pinned_bo[0],
400 error->pinned_bo_count[0]);
401
402 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
403 obj = error->ring[i].batchbuffer;
404 if (obj) {
405 err_puts(m, dev_priv->ring[i].name);
406 if (error->ring[i].pid != -1)
407 err_printf(m, " (submitted by %s [%d])",
408 error->ring[i].comm,
409 error->ring[i].pid);
410 err_printf(m, " --- gtt_offset = 0x%08x\n",
411 obj->gtt_offset);
412 print_error_obj(m, obj);
413 }
414
415 obj = error->ring[i].wa_batchbuffer;
416 if (obj) {
417 err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n",
418 dev_priv->ring[i].name, obj->gtt_offset);
419 print_error_obj(m, obj);
420 }
421
422 if (error->ring[i].num_requests) {
423 err_printf(m, "%s --- %d requests\n",
424 dev_priv->ring[i].name,
425 error->ring[i].num_requests);
426 for (j = 0; j < error->ring[i].num_requests; j++) {
427 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
428 error->ring[i].requests[j].seqno,
429 error->ring[i].requests[j].jiffies,
430 error->ring[i].requests[j].tail);
431 }
432 }
433
434 if ((obj = error->ring[i].ringbuffer)) {
435 err_printf(m, "%s --- ringbuffer = 0x%08x\n",
436 dev_priv->ring[i].name,
437 obj->gtt_offset);
438 print_error_obj(m, obj);
439 }
440
441 if ((obj = error->ring[i].hws_page)) {
442 err_printf(m, "%s --- HW Status = 0x%08x\n",
443 dev_priv->ring[i].name,
444 obj->gtt_offset);
445 offset = 0;
446 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
447 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
448 offset,
449 obj->pages[0][elt],
450 obj->pages[0][elt+1],
451 obj->pages[0][elt+2],
452 obj->pages[0][elt+3]);
453 offset += 16;
454 }
455 }
456
457 if ((obj = error->ring[i].ctx)) {
458 err_printf(m, "%s --- HW Context = 0x%08x\n",
459 dev_priv->ring[i].name,
460 obj->gtt_offset);
461 print_error_obj(m, obj);
462 }
463 }
464
465 if ((obj = error->semaphore_obj)) {
466 err_printf(m, "Semaphore page = 0x%08x\n", obj->gtt_offset);
467 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
468 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
469 elt * 4,
470 obj->pages[0][elt],
471 obj->pages[0][elt+1],
472 obj->pages[0][elt+2],
473 obj->pages[0][elt+3]);
474 }
475 }
476
477 if (error->overlay)
478 intel_overlay_print_error_state(m, error->overlay);
479
480 if (error->display)
481 intel_display_print_error_state(m, dev, error->display);
482
483 out:
484 if (m->bytes == 0 && m->err)
485 return m->err;
486
487 return 0;
488 }
489
490 int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
491 size_t count, loff_t pos)
492 {
493 memset(ebuf, 0, sizeof(*ebuf));
494
495 /* We need to have enough room to store any i915_error_state printf
496 * so that we can move it to start position.
497 */
498 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
499 ebuf->buf = kmalloc(ebuf->size,
500 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);
501
502 if (ebuf->buf == NULL) {
503 ebuf->size = PAGE_SIZE;
504 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
505 }
506
507 if (ebuf->buf == NULL) {
508 ebuf->size = 128;
509 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
510 }
511
512 if (ebuf->buf == NULL)
513 return -ENOMEM;
514
515 ebuf->start = pos;
516
517 return 0;
518 }
519
520 static void i915_error_object_free(struct drm_i915_error_object *obj)
521 {
522 int page;
523
524 if (obj == NULL)
525 return;
526
527 for (page = 0; page < obj->page_count; page++)
528 kfree(obj->pages[page]);
529
530 kfree(obj);
531 }
532
533 static void i915_error_state_free(struct kref *error_ref)
534 {
535 struct drm_i915_error_state *error = container_of(error_ref,
536 typeof(*error), ref);
537 int i;
538
539 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
540 i915_error_object_free(error->ring[i].batchbuffer);
541 i915_error_object_free(error->ring[i].ringbuffer);
542 i915_error_object_free(error->ring[i].hws_page);
543 i915_error_object_free(error->ring[i].ctx);
544 kfree(error->ring[i].requests);
545 }
546
547 i915_error_object_free(error->semaphore_obj);
548 kfree(error->active_bo);
549 kfree(error->overlay);
550 kfree(error->display);
551 kfree(error);
552 }
553
554 static struct drm_i915_error_object *
555 i915_error_object_create_sized(struct drm_i915_private *dev_priv,
556 struct drm_i915_gem_object *src,
557 struct i915_address_space *vm,
558 const int num_pages)
559 {
560 struct drm_i915_error_object *dst;
561 int i;
562 u32 reloc_offset;
563
564 if (src == NULL || src->pages == NULL)
565 return NULL;
566
567 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
568 if (dst == NULL)
569 return NULL;
570
571 reloc_offset = dst->gtt_offset = i915_gem_obj_offset(src, vm);
572 for (i = 0; i < num_pages; i++) {
573 unsigned long flags;
574 void *d;
575
576 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
577 if (d == NULL)
578 goto unwind;
579
580 local_irq_save(flags);
581 if (src->cache_level == I915_CACHE_NONE &&
582 reloc_offset < dev_priv->gtt.mappable_end &&
583 src->has_global_gtt_mapping &&
584 i915_is_ggtt(vm)) {
585 void __iomem *s;
586
587 /* Simply ignore tiling or any overlapping fence.
588 * It's part of the error state, and this hopefully
589 * captures what the GPU read.
590 */
591
592 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
593 reloc_offset);
594 memcpy_fromio(d, s, PAGE_SIZE);
595 io_mapping_unmap_atomic(s);
596 } else if (src->stolen) {
597 unsigned long offset;
598
599 offset = dev_priv->mm.stolen_base;
600 offset += src->stolen->start;
601 offset += i << PAGE_SHIFT;
602
603 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
604 } else {
605 struct page *page;
606 void *s;
607
608 page = i915_gem_object_get_page(src, i);
609
610 drm_clflush_pages(&page, 1);
611
612 s = kmap_atomic(page);
613 memcpy(d, s, PAGE_SIZE);
614 kunmap_atomic(s);
615
616 drm_clflush_pages(&page, 1);
617 }
618 local_irq_restore(flags);
619
620 dst->pages[i] = d;
621
622 reloc_offset += PAGE_SIZE;
623 }
624 dst->page_count = num_pages;
625
626 return dst;
627
628 unwind:
629 while (i--)
630 kfree(dst->pages[i]);
631 kfree(dst);
632 return NULL;
633 }
634 #define i915_error_object_create(dev_priv, src, vm) \
635 i915_error_object_create_sized((dev_priv), (src), (vm), \
636 (src)->base.size>>PAGE_SHIFT)
637
638 #define i915_error_ggtt_object_create(dev_priv, src) \
639 i915_error_object_create_sized((dev_priv), (src), &(dev_priv)->gtt.base, \
640 (src)->base.size>>PAGE_SHIFT)
641
642 static void capture_bo(struct drm_i915_error_buffer *err,
643 struct drm_i915_gem_object *obj)
644 {
645 err->size = obj->base.size;
646 err->name = obj->base.name;
647 err->rseqno = obj->last_read_seqno;
648 err->wseqno = obj->last_write_seqno;
649 err->gtt_offset = i915_gem_obj_ggtt_offset(obj);
650 err->read_domains = obj->base.read_domains;
651 err->write_domain = obj->base.write_domain;
652 err->fence_reg = obj->fence_reg;
653 err->pinned = 0;
654 if (i915_gem_obj_is_pinned(obj))
655 err->pinned = 1;
656 if (obj->user_pin_count > 0)
657 err->pinned = -1;
658 err->tiling = obj->tiling_mode;
659 err->dirty = obj->dirty;
660 err->purgeable = obj->madv != I915_MADV_WILLNEED;
661 err->userptr = obj->userptr.mm != NULL;
662 err->ring = obj->ring ? obj->ring->id : -1;
663 err->cache_level = obj->cache_level;
664 }
665
666 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
667 int count, struct list_head *head)
668 {
669 struct i915_vma *vma;
670 int i = 0;
671
672 list_for_each_entry(vma, head, mm_list) {
673 capture_bo(err++, vma->obj);
674 if (++i == count)
675 break;
676 }
677
678 return i;
679 }
680
681 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
682 int count, struct list_head *head)
683 {
684 struct drm_i915_gem_object *obj;
685 int i = 0;
686
687 list_for_each_entry(obj, head, global_list) {
688 if (!i915_gem_obj_is_pinned(obj))
689 continue;
690
691 capture_bo(err++, obj);
692 if (++i == count)
693 break;
694 }
695
696 return i;
697 }
698
699 /* Generate a semi-unique error code. The code is not meant to have meaning, The
700 * code's only purpose is to try to prevent false duplicated bug reports by
701 * grossly estimating a GPU error state.
702 *
703 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
704 * the hang if we could strip the GTT offset information from it.
705 *
706 * It's only a small step better than a random number in its current form.
707 */
708 static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
709 struct drm_i915_error_state *error,
710 int *ring_id)
711 {
712 uint32_t error_code = 0;
713 int i;
714
715 /* IPEHR would be an ideal way to detect errors, as it's the gross
716 * measure of "the command that hung." However, has some very common
717 * synchronization commands which almost always appear in the case
718 * strictly a client bug. Use instdone to differentiate those some.
719 */
720 for (i = 0; i < I915_NUM_RINGS; i++) {
721 if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) {
722 if (ring_id)
723 *ring_id = i;
724
725 return error->ring[i].ipehr ^ error->ring[i].instdone;
726 }
727 }
728
729 return error_code;
730 }
731
732 static void i915_gem_record_fences(struct drm_device *dev,
733 struct drm_i915_error_state *error)
734 {
735 struct drm_i915_private *dev_priv = dev->dev_private;
736 int i;
737
738 /* Fences */
739 switch (INTEL_INFO(dev)->gen) {
740 case 8:
741 case 7:
742 case 6:
743 for (i = 0; i < dev_priv->num_fence_regs; i++)
744 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
745 break;
746 case 5:
747 case 4:
748 for (i = 0; i < 16; i++)
749 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
750 break;
751 case 3:
752 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
753 for (i = 0; i < 8; i++)
754 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
755 case 2:
756 for (i = 0; i < 8; i++)
757 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
758 break;
759
760 default:
761 BUG();
762 }
763 }
764
765
766 static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv,
767 struct drm_i915_error_state *error,
768 struct intel_engine_cs *ring,
769 struct drm_i915_error_ring *ering)
770 {
771 struct intel_engine_cs *to;
772 int i;
773
774 if (!i915_semaphore_is_enabled(dev_priv->dev))
775 return;
776
777 if (!error->semaphore_obj)
778 error->semaphore_obj =
779 i915_error_object_create(dev_priv,
780 dev_priv->semaphore_obj,
781 &dev_priv->gtt.base);
782
783 for_each_ring(to, dev_priv, i) {
784 int idx;
785 u16 signal_offset;
786 u32 *tmp;
787
788 if (ring == to)
789 continue;
790
791 signal_offset = (GEN8_SIGNAL_OFFSET(ring, i) & (PAGE_SIZE - 1))
792 / 4;
793 tmp = error->semaphore_obj->pages[0];
794 idx = intel_ring_sync_index(ring, to);
795
796 ering->semaphore_mboxes[idx] = tmp[signal_offset];
797 ering->semaphore_seqno[idx] = ring->semaphore.sync_seqno[idx];
798 }
799 }
800
801 static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv,
802 struct intel_engine_cs *ring,
803 struct drm_i915_error_ring *ering)
804 {
805 ering->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(ring->mmio_base));
806 ering->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(ring->mmio_base));
807 ering->semaphore_seqno[0] = ring->semaphore.sync_seqno[0];
808 ering->semaphore_seqno[1] = ring->semaphore.sync_seqno[1];
809
810 if (HAS_VEBOX(dev_priv->dev)) {
811 ering->semaphore_mboxes[2] =
812 I915_READ(RING_SYNC_2(ring->mmio_base));
813 ering->semaphore_seqno[2] = ring->semaphore.sync_seqno[2];
814 }
815 }
816
817 static void i915_record_ring_state(struct drm_device *dev,
818 struct drm_i915_error_state *error,
819 struct intel_engine_cs *ring,
820 struct drm_i915_error_ring *ering)
821 {
822 struct drm_i915_private *dev_priv = dev->dev_private;
823
824 if (INTEL_INFO(dev)->gen >= 6) {
825 ering->rc_psmi = I915_READ(ring->mmio_base + 0x50);
826 ering->fault_reg = I915_READ(RING_FAULT_REG(ring));
827 if (INTEL_INFO(dev)->gen >= 8)
828 gen8_record_semaphore_state(dev_priv, error, ring, ering);
829 else
830 gen6_record_semaphore_state(dev_priv, ring, ering);
831 }
832
833 if (INTEL_INFO(dev)->gen >= 4) {
834 ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base));
835 ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base));
836 ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
837 ering->instdone = I915_READ(RING_INSTDONE(ring->mmio_base));
838 ering->instps = I915_READ(RING_INSTPS(ring->mmio_base));
839 ering->bbaddr = I915_READ(RING_BBADDR(ring->mmio_base));
840 if (INTEL_INFO(dev)->gen >= 8) {
841 ering->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(ring->mmio_base)) << 32;
842 ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32;
843 }
844 ering->bbstate = I915_READ(RING_BBSTATE(ring->mmio_base));
845 } else {
846 ering->faddr = I915_READ(DMA_FADD_I8XX);
847 ering->ipeir = I915_READ(IPEIR);
848 ering->ipehr = I915_READ(IPEHR);
849 ering->instdone = I915_READ(INSTDONE);
850 }
851
852 ering->waiting = waitqueue_active(&ring->irq_queue);
853 ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base));
854 ering->seqno = ring->get_seqno(ring, false);
855 ering->acthd = intel_ring_get_active_head(ring);
856 ering->head = I915_READ_HEAD(ring);
857 ering->tail = I915_READ_TAIL(ring);
858 ering->ctl = I915_READ_CTL(ring);
859
860 if (I915_NEED_GFX_HWS(dev)) {
861 int mmio;
862
863 if (IS_GEN7(dev)) {
864 switch (ring->id) {
865 default:
866 case RCS:
867 mmio = RENDER_HWS_PGA_GEN7;
868 break;
869 case BCS:
870 mmio = BLT_HWS_PGA_GEN7;
871 break;
872 case VCS:
873 mmio = BSD_HWS_PGA_GEN7;
874 break;
875 case VECS:
876 mmio = VEBOX_HWS_PGA_GEN7;
877 break;
878 }
879 } else if (IS_GEN6(ring->dev)) {
880 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
881 } else {
882 /* XXX: gen8 returns to sanity */
883 mmio = RING_HWS_PGA(ring->mmio_base);
884 }
885
886 ering->hws = I915_READ(mmio);
887 }
888
889 ering->cpu_ring_head = ring->buffer->head;
890 ering->cpu_ring_tail = ring->buffer->tail;
891
892 ering->hangcheck_score = ring->hangcheck.score;
893 ering->hangcheck_action = ring->hangcheck.action;
894
895 if (USES_PPGTT(dev)) {
896 int i;
897
898 ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(ring));
899
900 switch (INTEL_INFO(dev)->gen) {
901 case 8:
902 for (i = 0; i < 4; i++) {
903 ering->vm_info.pdp[i] =
904 I915_READ(GEN8_RING_PDP_UDW(ring, i));
905 ering->vm_info.pdp[i] <<= 32;
906 ering->vm_info.pdp[i] |=
907 I915_READ(GEN8_RING_PDP_LDW(ring, i));
908 }
909 break;
910 case 7:
911 ering->vm_info.pp_dir_base =
912 I915_READ(RING_PP_DIR_BASE(ring));
913 break;
914 case 6:
915 ering->vm_info.pp_dir_base =
916 I915_READ(RING_PP_DIR_BASE_READ(ring));
917 break;
918 }
919 }
920 }
921
922
923 static void i915_gem_record_active_context(struct intel_engine_cs *ring,
924 struct drm_i915_error_state *error,
925 struct drm_i915_error_ring *ering)
926 {
927 struct drm_i915_private *dev_priv = ring->dev->dev_private;
928 struct drm_i915_gem_object *obj;
929
930 /* Currently render ring is the only HW context user */
931 if (ring->id != RCS || !error->ccid)
932 return;
933
934 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
935 if (!i915_gem_obj_ggtt_bound(obj))
936 continue;
937
938 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
939 ering->ctx = i915_error_ggtt_object_create(dev_priv, obj);
940 break;
941 }
942 }
943 }
944
945 static void i915_gem_record_rings(struct drm_device *dev,
946 struct drm_i915_error_state *error)
947 {
948 struct drm_i915_private *dev_priv = dev->dev_private;
949 struct drm_i915_gem_request *request;
950 int i, count;
951
952 for (i = 0; i < I915_NUM_RINGS; i++) {
953 struct intel_engine_cs *ring = &dev_priv->ring[i];
954
955 error->ring[i].pid = -1;
956
957 if (ring->dev == NULL)
958 continue;
959
960 error->ring[i].valid = true;
961
962 i915_record_ring_state(dev, error, ring, &error->ring[i]);
963
964 request = i915_gem_find_active_request(ring);
965 if (request) {
966 /* We need to copy these to an anonymous buffer
967 * as the simplest method to avoid being overwritten
968 * by userspace.
969 */
970 error->ring[i].batchbuffer =
971 i915_error_object_create(dev_priv,
972 request->batch_obj,
973 request->ctx ?
974 request->ctx->vm :
975 &dev_priv->gtt.base);
976
977 if (HAS_BROKEN_CS_TLB(dev_priv->dev) &&
978 ring->scratch.obj)
979 error->ring[i].wa_batchbuffer =
980 i915_error_ggtt_object_create(dev_priv,
981 ring->scratch.obj);
982
983 if (request->file_priv) {
984 struct task_struct *task;
985
986 rcu_read_lock();
987 task = pid_task(request->file_priv->file->pid,
988 PIDTYPE_PID);
989 if (task) {
990 strcpy(error->ring[i].comm, task->comm);
991 error->ring[i].pid = task->pid;
992 }
993 rcu_read_unlock();
994 }
995 }
996
997 error->ring[i].ringbuffer =
998 i915_error_ggtt_object_create(dev_priv, ring->buffer->obj);
999
1000 if (ring->status_page.obj)
1001 error->ring[i].hws_page =
1002 i915_error_ggtt_object_create(dev_priv, ring->status_page.obj);
1003
1004 i915_gem_record_active_context(ring, error, &error->ring[i]);
1005
1006 count = 0;
1007 list_for_each_entry(request, &ring->request_list, list)
1008 count++;
1009
1010 error->ring[i].num_requests = count;
1011 error->ring[i].requests =
1012 kcalloc(count, sizeof(*error->ring[i].requests),
1013 GFP_ATOMIC);
1014 if (error->ring[i].requests == NULL) {
1015 error->ring[i].num_requests = 0;
1016 continue;
1017 }
1018
1019 count = 0;
1020 list_for_each_entry(request, &ring->request_list, list) {
1021 struct drm_i915_error_request *erq;
1022
1023 erq = &error->ring[i].requests[count++];
1024 erq->seqno = request->seqno;
1025 erq->jiffies = request->emitted_jiffies;
1026 erq->tail = request->tail;
1027 }
1028 }
1029 }
1030
1031 /* FIXME: Since pin count/bound list is global, we duplicate what we capture per
1032 * VM.
1033 */
1034 static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
1035 struct drm_i915_error_state *error,
1036 struct i915_address_space *vm,
1037 const int ndx)
1038 {
1039 struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL;
1040 struct drm_i915_gem_object *obj;
1041 struct i915_vma *vma;
1042 int i;
1043
1044 i = 0;
1045 list_for_each_entry(vma, &vm->active_list, mm_list)
1046 i++;
1047 error->active_bo_count[ndx] = i;
1048 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1049 if (i915_gem_obj_is_pinned(obj))
1050 i++;
1051 error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx];
1052
1053 if (i) {
1054 active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC);
1055 if (active_bo)
1056 pinned_bo = active_bo + error->active_bo_count[ndx];
1057 }
1058
1059 if (active_bo)
1060 error->active_bo_count[ndx] =
1061 capture_active_bo(active_bo,
1062 error->active_bo_count[ndx],
1063 &vm->active_list);
1064
1065 if (pinned_bo)
1066 error->pinned_bo_count[ndx] =
1067 capture_pinned_bo(pinned_bo,
1068 error->pinned_bo_count[ndx],
1069 &dev_priv->mm.bound_list);
1070 error->active_bo[ndx] = active_bo;
1071 error->pinned_bo[ndx] = pinned_bo;
1072 }
1073
1074 static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
1075 struct drm_i915_error_state *error)
1076 {
1077 struct i915_address_space *vm;
1078 int cnt = 0, i = 0;
1079
1080 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
1081 cnt++;
1082
1083 error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC);
1084 error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC);
1085 error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count),
1086 GFP_ATOMIC);
1087 error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count),
1088 GFP_ATOMIC);
1089
1090 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
1091 i915_gem_capture_vm(dev_priv, error, vm, i++);
1092 }
1093
1094 /* Capture all registers which don't fit into another category. */
1095 static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
1096 struct drm_i915_error_state *error)
1097 {
1098 struct drm_device *dev = dev_priv->dev;
1099
1100 /* General organization
1101 * 1. Registers specific to a single generation
1102 * 2. Registers which belong to multiple generations
1103 * 3. Feature specific registers.
1104 * 4. Everything else
1105 * Please try to follow the order.
1106 */
1107
1108 /* 1: Registers specific to a single generation */
1109 if (IS_VALLEYVIEW(dev)) {
1110 error->gtier = I915_READ(GTIER);
1111 error->ier = I915_READ(VLV_IER);
1112 error->forcewake = I915_READ(FORCEWAKE_VLV);
1113 }
1114
1115 if (IS_GEN7(dev))
1116 error->err_int = I915_READ(GEN7_ERR_INT);
1117
1118 if (IS_GEN6(dev)) {
1119 error->forcewake = I915_READ(FORCEWAKE);
1120 error->gab_ctl = I915_READ(GAB_CTL);
1121 error->gfx_mode = I915_READ(GFX_MODE);
1122 }
1123
1124 /* 2: Registers which belong to multiple generations */
1125 if (INTEL_INFO(dev)->gen >= 7)
1126 error->forcewake = I915_READ(FORCEWAKE_MT);
1127
1128 if (INTEL_INFO(dev)->gen >= 6) {
1129 error->derrmr = I915_READ(DERRMR);
1130 error->error = I915_READ(ERROR_GEN6);
1131 error->done_reg = I915_READ(DONE_REG);
1132 }
1133
1134 /* 3: Feature specific registers */
1135 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1136 error->gam_ecochk = I915_READ(GAM_ECOCHK);
1137 error->gac_eco = I915_READ(GAC_ECO_BITS);
1138 }
1139
1140 /* 4: Everything else */
1141 if (HAS_HW_CONTEXTS(dev))
1142 error->ccid = I915_READ(CCID);
1143
1144 if (HAS_PCH_SPLIT(dev)) {
1145 error->ier = I915_READ(DEIER);
1146 error->gtier = I915_READ(GTIER);
1147 } else if (IS_GEN2(dev)) {
1148 error->ier = I915_READ16(IER);
1149 } else if (!IS_VALLEYVIEW(dev)) {
1150 error->ier = I915_READ(IER);
1151 }
1152 error->eir = I915_READ(EIR);
1153 error->pgtbl_er = I915_READ(PGTBL_ER);
1154
1155 i915_get_extra_instdone(dev, error->extra_instdone);
1156 }
1157
1158 static void i915_error_capture_msg(struct drm_device *dev,
1159 struct drm_i915_error_state *error,
1160 bool wedged,
1161 const char *error_msg)
1162 {
1163 struct drm_i915_private *dev_priv = dev->dev_private;
1164 u32 ecode;
1165 int ring_id = -1, len;
1166
1167 ecode = i915_error_generate_code(dev_priv, error, &ring_id);
1168
1169 len = scnprintf(error->error_msg, sizeof(error->error_msg),
1170 "GPU HANG: ecode %d:0x%08x", ring_id, ecode);
1171
1172 if (ring_id != -1 && error->ring[ring_id].pid != -1)
1173 len += scnprintf(error->error_msg + len,
1174 sizeof(error->error_msg) - len,
1175 ", in %s [%d]",
1176 error->ring[ring_id].comm,
1177 error->ring[ring_id].pid);
1178
1179 scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
1180 ", reason: %s, action: %s",
1181 error_msg,
1182 wedged ? "reset" : "continue");
1183 }
1184
1185 static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
1186 struct drm_i915_error_state *error)
1187 {
1188 error->reset_count = i915_reset_count(&dev_priv->gpu_error);
1189 error->suspend_count = dev_priv->suspend_count;
1190 }
1191
1192 /**
1193 * i915_capture_error_state - capture an error record for later analysis
1194 * @dev: drm device
1195 *
1196 * Should be called when an error is detected (either a hang or an error
1197 * interrupt) to capture error state from the time of the error. Fills
1198 * out a structure which becomes available in debugfs for user level tools
1199 * to pick up.
1200 */
1201 void i915_capture_error_state(struct drm_device *dev, bool wedged,
1202 const char *error_msg)
1203 {
1204 static bool warned;
1205 struct drm_i915_private *dev_priv = dev->dev_private;
1206 struct drm_i915_error_state *error;
1207 unsigned long flags;
1208
1209 /* Account for pipe specific data like PIPE*STAT */
1210 error = kzalloc(sizeof(*error), GFP_ATOMIC);
1211 if (!error) {
1212 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1213 return;
1214 }
1215
1216 kref_init(&error->ref);
1217
1218 i915_capture_gen_state(dev_priv, error);
1219 i915_capture_reg_state(dev_priv, error);
1220 i915_gem_capture_buffers(dev_priv, error);
1221 i915_gem_record_fences(dev, error);
1222 i915_gem_record_rings(dev, error);
1223
1224 do_gettimeofday(&error->time);
1225
1226 error->overlay = intel_overlay_capture_error_state(dev);
1227 error->display = intel_display_capture_error_state(dev);
1228
1229 i915_error_capture_msg(dev, error, wedged, error_msg);
1230 DRM_INFO("%s\n", error->error_msg);
1231
1232 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1233 if (dev_priv->gpu_error.first_error == NULL) {
1234 dev_priv->gpu_error.first_error = error;
1235 error = NULL;
1236 }
1237 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1238
1239 if (error) {
1240 i915_error_state_free(&error->ref);
1241 return;
1242 }
1243
1244 if (!warned) {
1245 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1246 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
1247 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1248 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
1249 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev->primary->index);
1250 warned = true;
1251 }
1252 }
1253
1254 void i915_error_state_get(struct drm_device *dev,
1255 struct i915_error_state_file_priv *error_priv)
1256 {
1257 struct drm_i915_private *dev_priv = dev->dev_private;
1258 unsigned long flags;
1259
1260 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1261 error_priv->error = dev_priv->gpu_error.first_error;
1262 if (error_priv->error)
1263 kref_get(&error_priv->error->ref);
1264 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1265
1266 }
1267
1268 void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
1269 {
1270 if (error_priv->error)
1271 kref_put(&error_priv->error->ref, i915_error_state_free);
1272 }
1273
1274 void i915_destroy_error_state(struct drm_device *dev)
1275 {
1276 struct drm_i915_private *dev_priv = dev->dev_private;
1277 struct drm_i915_error_state *error;
1278 unsigned long flags;
1279
1280 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1281 error = dev_priv->gpu_error.first_error;
1282 dev_priv->gpu_error.first_error = NULL;
1283 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1284
1285 if (error)
1286 kref_put(&error->ref, i915_error_state_free);
1287 }
1288
1289 const char *i915_cache_level_str(int type)
1290 {
1291 switch (type) {
1292 case I915_CACHE_NONE: return " uncached";
1293 case I915_CACHE_LLC: return " snooped or LLC";
1294 case I915_CACHE_L3_LLC: return " L3+LLC";
1295 case I915_CACHE_WT: return " WT";
1296 default: return "";
1297 }
1298 }
1299
1300 /* NB: please notice the memset */
1301 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone)
1302 {
1303 struct drm_i915_private *dev_priv = dev->dev_private;
1304 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1305
1306 switch (INTEL_INFO(dev)->gen) {
1307 case 2:
1308 case 3:
1309 instdone[0] = I915_READ(INSTDONE);
1310 break;
1311 case 4:
1312 case 5:
1313 case 6:
1314 instdone[0] = I915_READ(INSTDONE_I965);
1315 instdone[1] = I915_READ(INSTDONE1);
1316 break;
1317 default:
1318 WARN_ONCE(1, "Unsupported platform\n");
1319 case 7:
1320 case 8:
1321 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1322 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1323 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1324 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1325 break;
1326 }
1327 }
Linux kernel - Deliverables
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