projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
drm/i915: Replace last_[rwf]_seqno with last_[rwf]_req
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gpu_error.c
1 /*
2 * Copyright (c) 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 * Mika Kuoppala <mika.kuoppala@intel.com>
27 *
28 */
29
30 #include <generated/utsrelease.h>
31 #include "i915_drv.h"
32
33 static const char *yesno(int v)
34 {
35 return v ? "yes" : "no";
36 }
37
38 static const char *ring_str(int ring)
39 {
40 switch (ring) {
41 case RCS: return "render";
42 case VCS: return "bsd";
43 case BCS: return "blt";
44 case VECS: return "vebox";
45 case VCS2: return "bsd2";
46 default: return "";
47 }
48 }
49
50 static const char *pin_flag(int pinned)
51 {
52 if (pinned > 0)
53 return " P";
54 else if (pinned < 0)
55 return " p";
56 else
57 return "";
58 }
59
60 static const char *tiling_flag(int tiling)
61 {
62 switch (tiling) {
63 default:
64 case I915_TILING_NONE: return "";
65 case I915_TILING_X: return " X";
66 case I915_TILING_Y: return " Y";
67 }
68 }
69
70 static const char *dirty_flag(int dirty)
71 {
72 return dirty ? " dirty" : "";
73 }
74
75 static const char *purgeable_flag(int purgeable)
76 {
77 return purgeable ? " purgeable" : "";
78 }
79
80 static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
81 {
82
83 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
84 e->err = -ENOSPC;
85 return false;
86 }
87
88 if (e->bytes == e->size - 1 || e->err)
89 return false;
90
91 return true;
92 }
93
94 static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
95 unsigned len)
96 {
97 if (e->pos + len <= e->start) {
98 e->pos += len;
99 return false;
100 }
101
102 /* First vsnprintf needs to fit in its entirety for memmove */
103 if (len >= e->size) {
104 e->err = -EIO;
105 return false;
106 }
107
108 return true;
109 }
110
111 static void __i915_error_advance(struct drm_i915_error_state_buf *e,
112 unsigned len)
113 {
114 /* If this is first printf in this window, adjust it so that
115 * start position matches start of the buffer
116 */
117
118 if (e->pos < e->start) {
119 const size_t off = e->start - e->pos;
120
121 /* Should not happen but be paranoid */
122 if (off > len || e->bytes) {
123 e->err = -EIO;
124 return;
125 }
126
127 memmove(e->buf, e->buf + off, len - off);
128 e->bytes = len - off;
129 e->pos = e->start;
130 return;
131 }
132
133 e->bytes += len;
134 e->pos += len;
135 }
136
137 static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
138 const char *f, va_list args)
139 {
140 unsigned len;
141
142 if (!__i915_error_ok(e))
143 return;
144
145 /* Seek the first printf which is hits start position */
146 if (e->pos < e->start) {
147 va_list tmp;
148
149 va_copy(tmp, args);
150 len = vsnprintf(NULL, 0, f, tmp);
151 va_end(tmp);
152
153 if (!__i915_error_seek(e, len))
154 return;
155 }
156
157 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
158 if (len >= e->size - e->bytes)
159 len = e->size - e->bytes - 1;
160
161 __i915_error_advance(e, len);
162 }
163
164 static void i915_error_puts(struct drm_i915_error_state_buf *e,
165 const char *str)
166 {
167 unsigned len;
168
169 if (!__i915_error_ok(e))
170 return;
171
172 len = strlen(str);
173
174 /* Seek the first printf which is hits start position */
175 if (e->pos < e->start) {
176 if (!__i915_error_seek(e, len))
177 return;
178 }
179
180 if (len >= e->size - e->bytes)
181 len = e->size - e->bytes - 1;
182 memcpy(e->buf + e->bytes, str, len);
183
184 __i915_error_advance(e, len);
185 }
186
187 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
188 #define err_puts(e, s) i915_error_puts(e, s)
189
190 static void print_error_buffers(struct drm_i915_error_state_buf *m,
191 const char *name,
192 struct drm_i915_error_buffer *err,
193 int count)
194 {
195 err_printf(m, " %s [%d]:\n", name, count);
196
197 while (count--) {
198 err_printf(m, " %08x %8u %02x %02x %x %x",
199 err->gtt_offset,
200 err->size,
201 err->read_domains,
202 err->write_domain,
203 err->rseqno, err->wseqno);
204 err_puts(m, pin_flag(err->pinned));
205 err_puts(m, tiling_flag(err->tiling));
206 err_puts(m, dirty_flag(err->dirty));
207 err_puts(m, purgeable_flag(err->purgeable));
208 err_puts(m, err->userptr ? " userptr" : "");
209 err_puts(m, err->ring != -1 ? " " : "");
210 err_puts(m, ring_str(err->ring));
211 err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
212
213 if (err->name)
214 err_printf(m, " (name: %d)", err->name);
215 if (err->fence_reg != I915_FENCE_REG_NONE)
216 err_printf(m, " (fence: %d)", err->fence_reg);
217
218 err_puts(m, "\n");
219 err++;
220 }
221 }
222
223 static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
224 {
225 switch (a) {
226 case HANGCHECK_IDLE:
227 return "idle";
228 case HANGCHECK_WAIT:
229 return "wait";
230 case HANGCHECK_ACTIVE:
231 return "active";
232 case HANGCHECK_ACTIVE_LOOP:
233 return "active (loop)";
234 case HANGCHECK_KICK:
235 return "kick";
236 case HANGCHECK_HUNG:
237 return "hung";
238 }
239
240 return "unknown";
241 }
242
243 static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
244 struct drm_device *dev,
245 struct drm_i915_error_state *error,
246 int ring_idx)
247 {
248 struct drm_i915_error_ring *ring = &error->ring[ring_idx];
249
250 if (!ring->valid)
251 return;
252
253 err_printf(m, "%s command stream:\n", ring_str(ring_idx));
254 err_printf(m, " HEAD: 0x%08x\n", ring->head);
255 err_printf(m, " TAIL: 0x%08x\n", ring->tail);
256 err_printf(m, " CTL: 0x%08x\n", ring->ctl);
257 err_printf(m, " HWS: 0x%08x\n", ring->hws);
258 err_printf(m, " ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd);
259 err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir);
260 err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr);
261 err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone);
262 if (INTEL_INFO(dev)->gen >= 4) {
263 err_printf(m, " BBADDR: 0x%08x %08x\n", (u32)(ring->bbaddr>>32), (u32)ring->bbaddr);
264 err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate);
265 err_printf(m, " INSTPS: 0x%08x\n", ring->instps);
266 }
267 err_printf(m, " INSTPM: 0x%08x\n", ring->instpm);
268 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ring->faddr),
269 lower_32_bits(ring->faddr));
270 if (INTEL_INFO(dev)->gen >= 6) {
271 err_printf(m, " RC PSMI: 0x%08x\n", ring->rc_psmi);
272 err_printf(m, " FAULT_REG: 0x%08x\n", ring->fault_reg);
273 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
274 ring->semaphore_mboxes[0],
275 ring->semaphore_seqno[0]);
276 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
277 ring->semaphore_mboxes[1],
278 ring->semaphore_seqno[1]);
279 if (HAS_VEBOX(dev)) {
280 err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n",
281 ring->semaphore_mboxes[2],
282 ring->semaphore_seqno[2]);
283 }
284 }
285 if (USES_PPGTT(dev)) {
286 err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode);
287
288 if (INTEL_INFO(dev)->gen >= 8) {
289 int i;
290 for (i = 0; i < 4; i++)
291 err_printf(m, " PDP%d: 0x%016llx\n",
292 i, ring->vm_info.pdp[i]);
293 } else {
294 err_printf(m, " PP_DIR_BASE: 0x%08x\n",
295 ring->vm_info.pp_dir_base);
296 }
297 }
298 err_printf(m, " seqno: 0x%08x\n", ring->seqno);
299 err_printf(m, " waiting: %s\n", yesno(ring->waiting));
300 err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head);
301 err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail);
302 err_printf(m, " hangcheck: %s [%d]\n",
303 hangcheck_action_to_str(ring->hangcheck_action),
304 ring->hangcheck_score);
305 }
306
307 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
308 {
309 va_list args;
310
311 va_start(args, f);
312 i915_error_vprintf(e, f, args);
313 va_end(args);
314 }
315
316 static void print_error_obj(struct drm_i915_error_state_buf *m,
317 struct drm_i915_error_object *obj)
318 {
319 int page, offset, elt;
320
321 for (page = offset = 0; page < obj->page_count; page++) {
322 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
323 err_printf(m, "%08x : %08x\n", offset,
324 obj->pages[page][elt]);
325 offset += 4;
326 }
327 }
328 }
329
330 int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
331 const struct i915_error_state_file_priv *error_priv)
332 {
333 struct drm_device *dev = error_priv->dev;
334 struct drm_i915_private *dev_priv = dev->dev_private;
335 struct drm_i915_error_state *error = error_priv->error;
336 struct drm_i915_error_object *obj;
337 int i, j, offset, elt;
338 int max_hangcheck_score;
339
340 if (!error) {
341 err_printf(m, "no error state collected\n");
342 goto out;
343 }
344
345 err_printf(m, "%s\n", error->error_msg);
346 err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
347 error->time.tv_usec);
348 err_printf(m, "Kernel: " UTS_RELEASE "\n");
349 max_hangcheck_score = 0;
350 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
351 if (error->ring[i].hangcheck_score > max_hangcheck_score)
352 max_hangcheck_score = error->ring[i].hangcheck_score;
353 }
354 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
355 if (error->ring[i].hangcheck_score == max_hangcheck_score &&
356 error->ring[i].pid != -1) {
357 err_printf(m, "Active process (on ring %s): %s [%d]\n",
358 ring_str(i),
359 error->ring[i].comm,
360 error->ring[i].pid);
361 }
362 }
363 err_printf(m, "Reset count: %u\n", error->reset_count);
364 err_printf(m, "Suspend count: %u\n", error->suspend_count);
365 err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
366 err_printf(m, "EIR: 0x%08x\n", error->eir);
367 err_printf(m, "IER: 0x%08x\n", error->ier);
368 if (INTEL_INFO(dev)->gen >= 8) {
369 for (i = 0; i < 4; i++)
370 err_printf(m, "GTIER gt %d: 0x%08x\n", i,
371 error->gtier[i]);
372 } else if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
373 err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]);
374 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
375 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
376 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
377 err_printf(m, "CCID: 0x%08x\n", error->ccid);
378 err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
379
380 for (i = 0; i < dev_priv->num_fence_regs; i++)
381 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
382
383 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
384 err_printf(m, " INSTDONE_%d: 0x%08x\n", i,
385 error->extra_instdone[i]);
386
387 if (INTEL_INFO(dev)->gen >= 6) {
388 err_printf(m, "ERROR: 0x%08x\n", error->error);
389 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
390 }
391
392 if (INTEL_INFO(dev)->gen == 7)
393 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
394
395 for (i = 0; i < ARRAY_SIZE(error->ring); i++)
396 i915_ring_error_state(m, dev, error, i);
397
398 for (i = 0; i < error->vm_count; i++) {
399 err_printf(m, "vm[%d]\n", i);
400
401 print_error_buffers(m, "Active",
402 error->active_bo[i],
403 error->active_bo_count[i]);
404
405 print_error_buffers(m, "Pinned",
406 error->pinned_bo[i],
407 error->pinned_bo_count[i]);
408 }
409
410 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
411 obj = error->ring[i].batchbuffer;
412 if (obj) {
413 err_puts(m, dev_priv->ring[i].name);
414 if (error->ring[i].pid != -1)
415 err_printf(m, " (submitted by %s [%d])",
416 error->ring[i].comm,
417 error->ring[i].pid);
418 err_printf(m, " --- gtt_offset = 0x%08x\n",
419 obj->gtt_offset);
420 print_error_obj(m, obj);
421 }
422
423 obj = error->ring[i].wa_batchbuffer;
424 if (obj) {
425 err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n",
426 dev_priv->ring[i].name, obj->gtt_offset);
427 print_error_obj(m, obj);
428 }
429
430 if (error->ring[i].num_requests) {
431 err_printf(m, "%s --- %d requests\n",
432 dev_priv->ring[i].name,
433 error->ring[i].num_requests);
434 for (j = 0; j < error->ring[i].num_requests; j++) {
435 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
436 error->ring[i].requests[j].seqno,
437 error->ring[i].requests[j].jiffies,
438 error->ring[i].requests[j].tail);
439 }
440 }
441
442 if ((obj = error->ring[i].ringbuffer)) {
443 err_printf(m, "%s --- ringbuffer = 0x%08x\n",
444 dev_priv->ring[i].name,
445 obj->gtt_offset);
446 print_error_obj(m, obj);
447 }
448
449 if ((obj = error->ring[i].hws_page)) {
450 err_printf(m, "%s --- HW Status = 0x%08x\n",
451 dev_priv->ring[i].name,
452 obj->gtt_offset);
453 offset = 0;
454 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
455 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
456 offset,
457 obj->pages[0][elt],
458 obj->pages[0][elt+1],
459 obj->pages[0][elt+2],
460 obj->pages[0][elt+3]);
461 offset += 16;
462 }
463 }
464
465 if ((obj = error->ring[i].ctx)) {
466 err_printf(m, "%s --- HW Context = 0x%08x\n",
467 dev_priv->ring[i].name,
468 obj->gtt_offset);
469 print_error_obj(m, obj);
470 }
471 }
472
473 if ((obj = error->semaphore_obj)) {
474 err_printf(m, "Semaphore page = 0x%08x\n", obj->gtt_offset);
475 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
476 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
477 elt * 4,
478 obj->pages[0][elt],
479 obj->pages[0][elt+1],
480 obj->pages[0][elt+2],
481 obj->pages[0][elt+3]);
482 }
483 }
484
485 if (error->overlay)
486 intel_overlay_print_error_state(m, error->overlay);
487
488 if (error->display)
489 intel_display_print_error_state(m, dev, error->display);
490
491 out:
492 if (m->bytes == 0 && m->err)
493 return m->err;
494
495 return 0;
496 }
497
498 int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
499 struct drm_i915_private *i915,
500 size_t count, loff_t pos)
501 {
502 memset(ebuf, 0, sizeof(*ebuf));
503 ebuf->i915 = i915;
504
505 /* We need to have enough room to store any i915_error_state printf
506 * so that we can move it to start position.
507 */
508 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
509 ebuf->buf = kmalloc(ebuf->size,
510 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);
511
512 if (ebuf->buf == NULL) {
513 ebuf->size = PAGE_SIZE;
514 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
515 }
516
517 if (ebuf->buf == NULL) {
518 ebuf->size = 128;
519 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
520 }
521
522 if (ebuf->buf == NULL)
523 return -ENOMEM;
524
525 ebuf->start = pos;
526
527 return 0;
528 }
529
530 static void i915_error_object_free(struct drm_i915_error_object *obj)
531 {
532 int page;
533
534 if (obj == NULL)
535 return;
536
537 for (page = 0; page < obj->page_count; page++)
538 kfree(obj->pages[page]);
539
540 kfree(obj);
541 }
542
543 static void i915_error_state_free(struct kref *error_ref)
544 {
545 struct drm_i915_error_state *error = container_of(error_ref,
546 typeof(*error), ref);
547 int i;
548
549 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
550 i915_error_object_free(error->ring[i].batchbuffer);
551 i915_error_object_free(error->ring[i].ringbuffer);
552 i915_error_object_free(error->ring[i].hws_page);
553 i915_error_object_free(error->ring[i].ctx);
554 kfree(error->ring[i].requests);
555 }
556
557 i915_error_object_free(error->semaphore_obj);
558 kfree(error->active_bo);
559 kfree(error->overlay);
560 kfree(error->display);
561 kfree(error);
562 }
563
564 static struct drm_i915_error_object *
565 i915_error_object_create(struct drm_i915_private *dev_priv,
566 struct drm_i915_gem_object *src,
567 struct i915_address_space *vm)
568 {
569 struct drm_i915_error_object *dst;
570 struct i915_vma *vma = NULL;
571 int num_pages;
572 bool use_ggtt;
573 int i = 0;
574 u32 reloc_offset;
575
576 if (src == NULL || src->pages == NULL)
577 return NULL;
578
579 num_pages = src->base.size >> PAGE_SHIFT;
580
581 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
582 if (dst == NULL)
583 return NULL;
584
585 if (i915_gem_obj_bound(src, vm))
586 dst->gtt_offset = i915_gem_obj_offset(src, vm);
587 else
588 dst->gtt_offset = -1;
589
590 reloc_offset = dst->gtt_offset;
591 if (i915_is_ggtt(vm))
592 vma = i915_gem_obj_to_ggtt(src);
593 use_ggtt = (src->cache_level == I915_CACHE_NONE &&
594 vma && (vma->bound & GLOBAL_BIND) &&
595 reloc_offset + num_pages * PAGE_SIZE <= dev_priv->gtt.mappable_end);
596
597 /* Cannot access stolen address directly, try to use the aperture */
598 if (src->stolen) {
599 use_ggtt = true;
600
601 if (!(vma && vma->bound & GLOBAL_BIND))
602 goto unwind;
603
604 reloc_offset = i915_gem_obj_ggtt_offset(src);
605 if (reloc_offset + num_pages * PAGE_SIZE > dev_priv->gtt.mappable_end)
606 goto unwind;
607 }
608
609 /* Cannot access snooped pages through the aperture */
610 if (use_ggtt && src->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv->dev))
611 goto unwind;
612
613 dst->page_count = num_pages;
614 while (num_pages--) {
615 unsigned long flags;
616 void *d;
617
618 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
619 if (d == NULL)
620 goto unwind;
621
622 local_irq_save(flags);
623 if (use_ggtt) {
624 void __iomem *s;
625
626 /* Simply ignore tiling or any overlapping fence.
627 * It's part of the error state, and this hopefully
628 * captures what the GPU read.
629 */
630
631 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
632 reloc_offset);
633 memcpy_fromio(d, s, PAGE_SIZE);
634 io_mapping_unmap_atomic(s);
635 } else {
636 struct page *page;
637 void *s;
638
639 page = i915_gem_object_get_page(src, i);
640
641 drm_clflush_pages(&page, 1);
642
643 s = kmap_atomic(page);
644 memcpy(d, s, PAGE_SIZE);
645 kunmap_atomic(s);
646
647 drm_clflush_pages(&page, 1);
648 }
649 local_irq_restore(flags);
650
651 dst->pages[i++] = d;
652 reloc_offset += PAGE_SIZE;
653 }
654
655 return dst;
656
657 unwind:
658 while (i--)
659 kfree(dst->pages[i]);
660 kfree(dst);
661 return NULL;
662 }
663 #define i915_error_ggtt_object_create(dev_priv, src) \
664 i915_error_object_create((dev_priv), (src), &(dev_priv)->gtt.base)
665
666 static void capture_bo(struct drm_i915_error_buffer *err,
667 struct i915_vma *vma)
668 {
669 struct drm_i915_gem_object *obj = vma->obj;
670
671 err->size = obj->base.size;
672 err->name = obj->base.name;
673 err->rseqno = i915_gem_request_get_seqno(obj->last_read_req);
674 err->wseqno = i915_gem_request_get_seqno(obj->last_write_req);
675 err->gtt_offset = vma->node.start;
676 err->read_domains = obj->base.read_domains;
677 err->write_domain = obj->base.write_domain;
678 err->fence_reg = obj->fence_reg;
679 err->pinned = 0;
680 if (i915_gem_obj_is_pinned(obj))
681 err->pinned = 1;
682 err->tiling = obj->tiling_mode;
683 err->dirty = obj->dirty;
684 err->purgeable = obj->madv != I915_MADV_WILLNEED;
685 err->userptr = obj->userptr.mm != NULL;
686 err->ring = obj->ring ? obj->ring->id : -1;
687 err->cache_level = obj->cache_level;
688 }
689
690 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
691 int count, struct list_head *head)
692 {
693 struct i915_vma *vma;
694 int i = 0;
695
696 list_for_each_entry(vma, head, mm_list) {
697 capture_bo(err++, vma);
698 if (++i == count)
699 break;
700 }
701
702 return i;
703 }
704
705 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
706 int count, struct list_head *head,
707 struct i915_address_space *vm)
708 {
709 struct drm_i915_gem_object *obj;
710 struct drm_i915_error_buffer * const first = err;
711 struct drm_i915_error_buffer * const last = err + count;
712
713 list_for_each_entry(obj, head, global_list) {
714 struct i915_vma *vma;
715
716 if (err == last)
717 break;
718
719 list_for_each_entry(vma, &obj->vma_list, vma_link)
720 if (vma->vm == vm && vma->pin_count > 0) {
721 capture_bo(err++, vma);
722 break;
723 }
724 }
725
726 return err - first;
727 }
728
729 /* Generate a semi-unique error code. The code is not meant to have meaning, The
730 * code's only purpose is to try to prevent false duplicated bug reports by
731 * grossly estimating a GPU error state.
732 *
733 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
734 * the hang if we could strip the GTT offset information from it.
735 *
736 * It's only a small step better than a random number in its current form.
737 */
738 static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
739 struct drm_i915_error_state *error,
740 int *ring_id)
741 {
742 uint32_t error_code = 0;
743 int i;
744
745 /* IPEHR would be an ideal way to detect errors, as it's the gross
746 * measure of "the command that hung." However, has some very common
747 * synchronization commands which almost always appear in the case
748 * strictly a client bug. Use instdone to differentiate those some.
749 */
750 for (i = 0; i < I915_NUM_RINGS; i++) {
751 if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) {
752 if (ring_id)
753 *ring_id = i;
754
755 return error->ring[i].ipehr ^ error->ring[i].instdone;
756 }
757 }
758
759 return error_code;
760 }
761
762 static void i915_gem_record_fences(struct drm_device *dev,
763 struct drm_i915_error_state *error)
764 {
765 struct drm_i915_private *dev_priv = dev->dev_private;
766 int i;
767
768 /* Fences */
769 switch (INTEL_INFO(dev)->gen) {
770 case 9:
771 case 8:
772 case 7:
773 case 6:
774 for (i = 0; i < dev_priv->num_fence_regs; i++)
775 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
776 break;
777 case 5:
778 case 4:
779 for (i = 0; i < 16; i++)
780 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
781 break;
782 case 3:
783 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
784 for (i = 0; i < 8; i++)
785 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
786 case 2:
787 for (i = 0; i < 8; i++)
788 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
789 break;
790
791 default:
792 BUG();
793 }
794 }
795
796
797 static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv,
798 struct drm_i915_error_state *error,
799 struct intel_engine_cs *ring,
800 struct drm_i915_error_ring *ering)
801 {
802 struct intel_engine_cs *to;
803 int i;
804
805 if (!i915_semaphore_is_enabled(dev_priv->dev))
806 return;
807
808 if (!error->semaphore_obj)
809 error->semaphore_obj =
810 i915_error_ggtt_object_create(dev_priv,
811 dev_priv->semaphore_obj);
812
813 for_each_ring(to, dev_priv, i) {
814 int idx;
815 u16 signal_offset;
816 u32 *tmp;
817
818 if (ring == to)
819 continue;
820
821 signal_offset = (GEN8_SIGNAL_OFFSET(ring, i) & (PAGE_SIZE - 1))
822 / 4;
823 tmp = error->semaphore_obj->pages[0];
824 idx = intel_ring_sync_index(ring, to);
825
826 ering->semaphore_mboxes[idx] = tmp[signal_offset];
827 ering->semaphore_seqno[idx] = ring->semaphore.sync_seqno[idx];
828 }
829 }
830
831 static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv,
832 struct intel_engine_cs *ring,
833 struct drm_i915_error_ring *ering)
834 {
835 ering->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(ring->mmio_base));
836 ering->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(ring->mmio_base));
837 ering->semaphore_seqno[0] = ring->semaphore.sync_seqno[0];
838 ering->semaphore_seqno[1] = ring->semaphore.sync_seqno[1];
839
840 if (HAS_VEBOX(dev_priv->dev)) {
841 ering->semaphore_mboxes[2] =
842 I915_READ(RING_SYNC_2(ring->mmio_base));
843 ering->semaphore_seqno[2] = ring->semaphore.sync_seqno[2];
844 }
845 }
846
847 static void i915_record_ring_state(struct drm_device *dev,
848 struct drm_i915_error_state *error,
849 struct intel_engine_cs *ring,
850 struct drm_i915_error_ring *ering)
851 {
852 struct drm_i915_private *dev_priv = dev->dev_private;
853
854 if (INTEL_INFO(dev)->gen >= 6) {
855 ering->rc_psmi = I915_READ(ring->mmio_base + 0x50);
856 ering->fault_reg = I915_READ(RING_FAULT_REG(ring));
857 if (INTEL_INFO(dev)->gen >= 8)
858 gen8_record_semaphore_state(dev_priv, error, ring, ering);
859 else
860 gen6_record_semaphore_state(dev_priv, ring, ering);
861 }
862
863 if (INTEL_INFO(dev)->gen >= 4) {
864 ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base));
865 ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base));
866 ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
867 ering->instdone = I915_READ(RING_INSTDONE(ring->mmio_base));
868 ering->instps = I915_READ(RING_INSTPS(ring->mmio_base));
869 ering->bbaddr = I915_READ(RING_BBADDR(ring->mmio_base));
870 if (INTEL_INFO(dev)->gen >= 8) {
871 ering->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(ring->mmio_base)) << 32;
872 ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32;
873 }
874 ering->bbstate = I915_READ(RING_BBSTATE(ring->mmio_base));
875 } else {
876 ering->faddr = I915_READ(DMA_FADD_I8XX);
877 ering->ipeir = I915_READ(IPEIR);
878 ering->ipehr = I915_READ(IPEHR);
879 ering->instdone = I915_READ(INSTDONE);
880 }
881
882 ering->waiting = waitqueue_active(&ring->irq_queue);
883 ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base));
884 ering->seqno = ring->get_seqno(ring, false);
885 ering->acthd = intel_ring_get_active_head(ring);
886 ering->head = I915_READ_HEAD(ring);
887 ering->tail = I915_READ_TAIL(ring);
888 ering->ctl = I915_READ_CTL(ring);
889
890 if (I915_NEED_GFX_HWS(dev)) {
891 int mmio;
892
893 if (IS_GEN7(dev)) {
894 switch (ring->id) {
895 default:
896 case RCS:
897 mmio = RENDER_HWS_PGA_GEN7;
898 break;
899 case BCS:
900 mmio = BLT_HWS_PGA_GEN7;
901 break;
902 case VCS:
903 mmio = BSD_HWS_PGA_GEN7;
904 break;
905 case VECS:
906 mmio = VEBOX_HWS_PGA_GEN7;
907 break;
908 }
909 } else if (IS_GEN6(ring->dev)) {
910 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
911 } else {
912 /* XXX: gen8 returns to sanity */
913 mmio = RING_HWS_PGA(ring->mmio_base);
914 }
915
916 ering->hws = I915_READ(mmio);
917 }
918
919 ering->hangcheck_score = ring->hangcheck.score;
920 ering->hangcheck_action = ring->hangcheck.action;
921
922 if (USES_PPGTT(dev)) {
923 int i;
924
925 ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(ring));
926
927 switch (INTEL_INFO(dev)->gen) {
928 case 9:
929 case 8:
930 for (i = 0; i < 4; i++) {
931 ering->vm_info.pdp[i] =
932 I915_READ(GEN8_RING_PDP_UDW(ring, i));
933 ering->vm_info.pdp[i] <<= 32;
934 ering->vm_info.pdp[i] |=
935 I915_READ(GEN8_RING_PDP_LDW(ring, i));
936 }
937 break;
938 case 7:
939 ering->vm_info.pp_dir_base =
940 I915_READ(RING_PP_DIR_BASE(ring));
941 break;
942 case 6:
943 ering->vm_info.pp_dir_base =
944 I915_READ(RING_PP_DIR_BASE_READ(ring));
945 break;
946 }
947 }
948 }
949
950
951 static void i915_gem_record_active_context(struct intel_engine_cs *ring,
952 struct drm_i915_error_state *error,
953 struct drm_i915_error_ring *ering)
954 {
955 struct drm_i915_private *dev_priv = ring->dev->dev_private;
956 struct drm_i915_gem_object *obj;
957
958 /* Currently render ring is the only HW context user */
959 if (ring->id != RCS || !error->ccid)
960 return;
961
962 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
963 if (!i915_gem_obj_ggtt_bound(obj))
964 continue;
965
966 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
967 ering->ctx = i915_error_ggtt_object_create(dev_priv, obj);
968 break;
969 }
970 }
971 }
972
973 static void i915_gem_record_rings(struct drm_device *dev,
974 struct drm_i915_error_state *error)
975 {
976 struct drm_i915_private *dev_priv = dev->dev_private;
977 struct drm_i915_gem_request *request;
978 int i, count;
979
980 for (i = 0; i < I915_NUM_RINGS; i++) {
981 struct intel_engine_cs *ring = &dev_priv->ring[i];
982 struct intel_ringbuffer *rbuf;
983
984 error->ring[i].pid = -1;
985
986 if (ring->dev == NULL)
987 continue;
988
989 error->ring[i].valid = true;
990
991 i915_record_ring_state(dev, error, ring, &error->ring[i]);
992
993 request = i915_gem_find_active_request(ring);
994 if (request) {
995 struct i915_address_space *vm;
996
997 vm = request->ctx && request->ctx->ppgtt ?
998 &request->ctx->ppgtt->base :
999 &dev_priv->gtt.base;
1000
1001 /* We need to copy these to an anonymous buffer
1002 * as the simplest method to avoid being overwritten
1003 * by userspace.
1004 */
1005 error->ring[i].batchbuffer =
1006 i915_error_object_create(dev_priv,
1007 request->batch_obj,
1008 vm);
1009
1010 if (HAS_BROKEN_CS_TLB(dev_priv->dev))
1011 error->ring[i].wa_batchbuffer =
1012 i915_error_ggtt_object_create(dev_priv,
1013 ring->scratch.obj);
1014
1015 if (request->file_priv) {
1016 struct task_struct *task;
1017
1018 rcu_read_lock();
1019 task = pid_task(request->file_priv->file->pid,
1020 PIDTYPE_PID);
1021 if (task) {
1022 strcpy(error->ring[i].comm, task->comm);
1023 error->ring[i].pid = task->pid;
1024 }
1025 rcu_read_unlock();
1026 }
1027 }
1028
1029 if (i915.enable_execlists) {
1030 /* TODO: This is only a small fix to keep basic error
1031 * capture working, but we need to add more information
1032 * for it to be useful (e.g. dump the context being
1033 * executed).
1034 */
1035 if (request)
1036 rbuf = request->ctx->engine[ring->id].ringbuf;
1037 else
1038 rbuf = ring->default_context->engine[ring->id].ringbuf;
1039 } else
1040 rbuf = ring->buffer;
1041
1042 error->ring[i].cpu_ring_head = rbuf->head;
1043 error->ring[i].cpu_ring_tail = rbuf->tail;
1044
1045 error->ring[i].ringbuffer =
1046 i915_error_ggtt_object_create(dev_priv, rbuf->obj);
1047
1048 error->ring[i].hws_page =
1049 i915_error_ggtt_object_create(dev_priv, ring->status_page.obj);
1050
1051 i915_gem_record_active_context(ring, error, &error->ring[i]);
1052
1053 count = 0;
1054 list_for_each_entry(request, &ring->request_list, list)
1055 count++;
1056
1057 error->ring[i].num_requests = count;
1058 error->ring[i].requests =
1059 kcalloc(count, sizeof(*error->ring[i].requests),
1060 GFP_ATOMIC);
1061 if (error->ring[i].requests == NULL) {
1062 error->ring[i].num_requests = 0;
1063 continue;
1064 }
1065
1066 count = 0;
1067 list_for_each_entry(request, &ring->request_list, list) {
1068 struct drm_i915_error_request *erq;
1069
1070 erq = &error->ring[i].requests[count++];
1071 erq->seqno = request->seqno;
1072 erq->jiffies = request->emitted_jiffies;
1073 erq->tail = request->tail;
1074 }
1075 }
1076 }
1077
1078 /* FIXME: Since pin count/bound list is global, we duplicate what we capture per
1079 * VM.
1080 */
1081 static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
1082 struct drm_i915_error_state *error,
1083 struct i915_address_space *vm,
1084 const int ndx)
1085 {
1086 struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL;
1087 struct drm_i915_gem_object *obj;
1088 struct i915_vma *vma;
1089 int i;
1090
1091 i = 0;
1092 list_for_each_entry(vma, &vm->active_list, mm_list)
1093 i++;
1094 error->active_bo_count[ndx] = i;
1095
1096 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1097 list_for_each_entry(vma, &obj->vma_list, vma_link)
1098 if (vma->vm == vm && vma->pin_count > 0) {
1099 i++;
1100 break;
1101 }
1102 }
1103 error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx];
1104
1105 if (i) {
1106 active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC);
1107 if (active_bo)
1108 pinned_bo = active_bo + error->active_bo_count[ndx];
1109 }
1110
1111 if (active_bo)
1112 error->active_bo_count[ndx] =
1113 capture_active_bo(active_bo,
1114 error->active_bo_count[ndx],
1115 &vm->active_list);
1116
1117 if (pinned_bo)
1118 error->pinned_bo_count[ndx] =
1119 capture_pinned_bo(pinned_bo,
1120 error->pinned_bo_count[ndx],
1121 &dev_priv->mm.bound_list, vm);
1122 error->active_bo[ndx] = active_bo;
1123 error->pinned_bo[ndx] = pinned_bo;
1124 }
1125
1126 static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
1127 struct drm_i915_error_state *error)
1128 {
1129 struct i915_address_space *vm;
1130 int cnt = 0, i = 0;
1131
1132 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
1133 cnt++;
1134
1135 error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC);
1136 error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC);
1137 error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count),
1138 GFP_ATOMIC);
1139 error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count),
1140 GFP_ATOMIC);
1141
1142 if (error->active_bo == NULL ||
1143 error->pinned_bo == NULL ||
1144 error->active_bo_count == NULL ||
1145 error->pinned_bo_count == NULL) {
1146 kfree(error->active_bo);
1147 kfree(error->active_bo_count);
1148 kfree(error->pinned_bo);
1149 kfree(error->pinned_bo_count);
1150
1151 error->active_bo = NULL;
1152 error->active_bo_count = NULL;
1153 error->pinned_bo = NULL;
1154 error->pinned_bo_count = NULL;
1155 } else {
1156 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
1157 i915_gem_capture_vm(dev_priv, error, vm, i++);
1158
1159 error->vm_count = cnt;
1160 }
1161 }
1162
1163 /* Capture all registers which don't fit into another category. */
1164 static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
1165 struct drm_i915_error_state *error)
1166 {
1167 struct drm_device *dev = dev_priv->dev;
1168 int i;
1169
1170 /* General organization
1171 * 1. Registers specific to a single generation
1172 * 2. Registers which belong to multiple generations
1173 * 3. Feature specific registers.
1174 * 4. Everything else
1175 * Please try to follow the order.
1176 */
1177
1178 /* 1: Registers specific to a single generation */
1179 if (IS_VALLEYVIEW(dev)) {
1180 error->gtier[0] = I915_READ(GTIER);
1181 error->ier = I915_READ(VLV_IER);
1182 error->forcewake = I915_READ(FORCEWAKE_VLV);
1183 }
1184
1185 if (IS_GEN7(dev))
1186 error->err_int = I915_READ(GEN7_ERR_INT);
1187
1188 if (IS_GEN6(dev)) {
1189 error->forcewake = I915_READ(FORCEWAKE);
1190 error->gab_ctl = I915_READ(GAB_CTL);
1191 error->gfx_mode = I915_READ(GFX_MODE);
1192 }
1193
1194 /* 2: Registers which belong to multiple generations */
1195 if (INTEL_INFO(dev)->gen >= 7)
1196 error->forcewake = I915_READ(FORCEWAKE_MT);
1197
1198 if (INTEL_INFO(dev)->gen >= 6) {
1199 error->derrmr = I915_READ(DERRMR);
1200 error->error = I915_READ(ERROR_GEN6);
1201 error->done_reg = I915_READ(DONE_REG);
1202 }
1203
1204 /* 3: Feature specific registers */
1205 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1206 error->gam_ecochk = I915_READ(GAM_ECOCHK);
1207 error->gac_eco = I915_READ(GAC_ECO_BITS);
1208 }
1209
1210 /* 4: Everything else */
1211 if (HAS_HW_CONTEXTS(dev))
1212 error->ccid = I915_READ(CCID);
1213
1214 if (INTEL_INFO(dev)->gen >= 8) {
1215 error->ier = I915_READ(GEN8_DE_MISC_IER);
1216 for (i = 0; i < 4; i++)
1217 error->gtier[i] = I915_READ(GEN8_GT_IER(i));
1218 } else if (HAS_PCH_SPLIT(dev)) {
1219 error->ier = I915_READ(DEIER);
1220 error->gtier[0] = I915_READ(GTIER);
1221 } else if (IS_GEN2(dev)) {
1222 error->ier = I915_READ16(IER);
1223 } else if (!IS_VALLEYVIEW(dev)) {
1224 error->ier = I915_READ(IER);
1225 }
1226 error->eir = I915_READ(EIR);
1227 error->pgtbl_er = I915_READ(PGTBL_ER);
1228
1229 i915_get_extra_instdone(dev, error->extra_instdone);
1230 }
1231
1232 static void i915_error_capture_msg(struct drm_device *dev,
1233 struct drm_i915_error_state *error,
1234 bool wedged,
1235 const char *error_msg)
1236 {
1237 struct drm_i915_private *dev_priv = dev->dev_private;
1238 u32 ecode;
1239 int ring_id = -1, len;
1240
1241 ecode = i915_error_generate_code(dev_priv, error, &ring_id);
1242
1243 len = scnprintf(error->error_msg, sizeof(error->error_msg),
1244 "GPU HANG: ecode %d:%d:0x%08x",
1245 INTEL_INFO(dev)->gen, ring_id, ecode);
1246
1247 if (ring_id != -1 && error->ring[ring_id].pid != -1)
1248 len += scnprintf(error->error_msg + len,
1249 sizeof(error->error_msg) - len,
1250 ", in %s [%d]",
1251 error->ring[ring_id].comm,
1252 error->ring[ring_id].pid);
1253
1254 scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
1255 ", reason: %s, action: %s",
1256 error_msg,
1257 wedged ? "reset" : "continue");
1258 }
1259
1260 static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
1261 struct drm_i915_error_state *error)
1262 {
1263 error->reset_count = i915_reset_count(&dev_priv->gpu_error);
1264 error->suspend_count = dev_priv->suspend_count;
1265 }
1266
1267 /**
1268 * i915_capture_error_state - capture an error record for later analysis
1269 * @dev: drm device
1270 *
1271 * Should be called when an error is detected (either a hang or an error
1272 * interrupt) to capture error state from the time of the error. Fills
1273 * out a structure which becomes available in debugfs for user level tools
1274 * to pick up.
1275 */
1276 void i915_capture_error_state(struct drm_device *dev, bool wedged,
1277 const char *error_msg)
1278 {
1279 static bool warned;
1280 struct drm_i915_private *dev_priv = dev->dev_private;
1281 struct drm_i915_error_state *error;
1282 unsigned long flags;
1283
1284 /* Account for pipe specific data like PIPE*STAT */
1285 error = kzalloc(sizeof(*error), GFP_ATOMIC);
1286 if (!error) {
1287 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1288 return;
1289 }
1290
1291 kref_init(&error->ref);
1292
1293 i915_capture_gen_state(dev_priv, error);
1294 i915_capture_reg_state(dev_priv, error);
1295 i915_gem_capture_buffers(dev_priv, error);
1296 i915_gem_record_fences(dev, error);
1297 i915_gem_record_rings(dev, error);
1298
1299 do_gettimeofday(&error->time);
1300
1301 error->overlay = intel_overlay_capture_error_state(dev);
1302 error->display = intel_display_capture_error_state(dev);
1303
1304 i915_error_capture_msg(dev, error, wedged, error_msg);
1305 DRM_INFO("%s\n", error->error_msg);
1306
1307 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1308 if (dev_priv->gpu_error.first_error == NULL) {
1309 dev_priv->gpu_error.first_error = error;
1310 error = NULL;
1311 }
1312 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1313
1314 if (error) {
1315 i915_error_state_free(&error->ref);
1316 return;
1317 }
1318
1319 if (!warned) {
1320 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1321 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
1322 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1323 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
1324 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev->primary->index);
1325 warned = true;
1326 }
1327 }
1328
1329 void i915_error_state_get(struct drm_device *dev,
1330 struct i915_error_state_file_priv *error_priv)
1331 {
1332 struct drm_i915_private *dev_priv = dev->dev_private;
1333
1334 spin_lock_irq(&dev_priv->gpu_error.lock);
1335 error_priv->error = dev_priv->gpu_error.first_error;
1336 if (error_priv->error)
1337 kref_get(&error_priv->error->ref);
1338 spin_unlock_irq(&dev_priv->gpu_error.lock);
1339
1340 }
1341
1342 void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
1343 {
1344 if (error_priv->error)
1345 kref_put(&error_priv->error->ref, i915_error_state_free);
1346 }
1347
1348 void i915_destroy_error_state(struct drm_device *dev)
1349 {
1350 struct drm_i915_private *dev_priv = dev->dev_private;
1351 struct drm_i915_error_state *error;
1352
1353 spin_lock_irq(&dev_priv->gpu_error.lock);
1354 error = dev_priv->gpu_error.first_error;
1355 dev_priv->gpu_error.first_error = NULL;
1356 spin_unlock_irq(&dev_priv->gpu_error.lock);
1357
1358 if (error)
1359 kref_put(&error->ref, i915_error_state_free);
1360 }
1361
1362 const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
1363 {
1364 switch (type) {
1365 case I915_CACHE_NONE: return " uncached";
1366 case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
1367 case I915_CACHE_L3_LLC: return " L3+LLC";
1368 case I915_CACHE_WT: return " WT";
1369 default: return "";
1370 }
1371 }
1372
1373 /* NB: please notice the memset */
1374 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone)
1375 {
1376 struct drm_i915_private *dev_priv = dev->dev_private;
1377 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1378
1379 switch (INTEL_INFO(dev)->gen) {
1380 case 2:
1381 case 3:
1382 instdone[0] = I915_READ(INSTDONE);
1383 break;
1384 case 4:
1385 case 5:
1386 case 6:
1387 instdone[0] = I915_READ(INSTDONE_I965);
1388 instdone[1] = I915_READ(INSTDONE1);
1389 break;
1390 default:
1391 WARN_ONCE(1, "Unsupported platform\n");
1392 case 7:
1393 case 8:
1394 case 9:
1395 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1396 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1397 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1398 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1399 break;
1400 }
1401 }
Linux kernel - Deliverables
This page took 0.092678 seconds and 5 git commands to generate.