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drm/i915: move dev_priv->suspend around
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gpu_error.c
1 /*
2 * Copyright (c) 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 * Mika Kuoppala <mika.kuoppala@intel.com>
27 *
28 */
29
30 #include <generated/utsrelease.h>
31 #include "i915_drv.h"
32
33 static const char *yesno(int v)
34 {
35 return v ? "yes" : "no";
36 }
37
38 static const char *ring_str(int ring)
39 {
40 switch (ring) {
41 case RCS: return "render";
42 case VCS: return "bsd";
43 case BCS: return "blt";
44 case VECS: return "vebox";
45 default: return "";
46 }
47 }
48
49 static const char *pin_flag(int pinned)
50 {
51 if (pinned > 0)
52 return " P";
53 else if (pinned < 0)
54 return " p";
55 else
56 return "";
57 }
58
59 static const char *tiling_flag(int tiling)
60 {
61 switch (tiling) {
62 default:
63 case I915_TILING_NONE: return "";
64 case I915_TILING_X: return " X";
65 case I915_TILING_Y: return " Y";
66 }
67 }
68
69 static const char *dirty_flag(int dirty)
70 {
71 return dirty ? " dirty" : "";
72 }
73
74 static const char *purgeable_flag(int purgeable)
75 {
76 return purgeable ? " purgeable" : "";
77 }
78
79 static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
80 {
81
82 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
83 e->err = -ENOSPC;
84 return false;
85 }
86
87 if (e->bytes == e->size - 1 || e->err)
88 return false;
89
90 return true;
91 }
92
93 static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
94 unsigned len)
95 {
96 if (e->pos + len <= e->start) {
97 e->pos += len;
98 return false;
99 }
100
101 /* First vsnprintf needs to fit in its entirety for memmove */
102 if (len >= e->size) {
103 e->err = -EIO;
104 return false;
105 }
106
107 return true;
108 }
109
110 static void __i915_error_advance(struct drm_i915_error_state_buf *e,
111 unsigned len)
112 {
113 /* If this is first printf in this window, adjust it so that
114 * start position matches start of the buffer
115 */
116
117 if (e->pos < e->start) {
118 const size_t off = e->start - e->pos;
119
120 /* Should not happen but be paranoid */
121 if (off > len || e->bytes) {
122 e->err = -EIO;
123 return;
124 }
125
126 memmove(e->buf, e->buf + off, len - off);
127 e->bytes = len - off;
128 e->pos = e->start;
129 return;
130 }
131
132 e->bytes += len;
133 e->pos += len;
134 }
135
136 static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
137 const char *f, va_list args)
138 {
139 unsigned len;
140
141 if (!__i915_error_ok(e))
142 return;
143
144 /* Seek the first printf which is hits start position */
145 if (e->pos < e->start) {
146 va_list tmp;
147
148 va_copy(tmp, args);
149 if (!__i915_error_seek(e, vsnprintf(NULL, 0, f, tmp)))
150 return;
151 }
152
153 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
154 if (len >= e->size - e->bytes)
155 len = e->size - e->bytes - 1;
156
157 __i915_error_advance(e, len);
158 }
159
160 static void i915_error_puts(struct drm_i915_error_state_buf *e,
161 const char *str)
162 {
163 unsigned len;
164
165 if (!__i915_error_ok(e))
166 return;
167
168 len = strlen(str);
169
170 /* Seek the first printf which is hits start position */
171 if (e->pos < e->start) {
172 if (!__i915_error_seek(e, len))
173 return;
174 }
175
176 if (len >= e->size - e->bytes)
177 len = e->size - e->bytes - 1;
178 memcpy(e->buf + e->bytes, str, len);
179
180 __i915_error_advance(e, len);
181 }
182
183 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
184 #define err_puts(e, s) i915_error_puts(e, s)
185
186 static void print_error_buffers(struct drm_i915_error_state_buf *m,
187 const char *name,
188 struct drm_i915_error_buffer *err,
189 int count)
190 {
191 err_printf(m, "%s [%d]:\n", name, count);
192
193 while (count--) {
194 err_printf(m, " %08x %8u %02x %02x %x %x",
195 err->gtt_offset,
196 err->size,
197 err->read_domains,
198 err->write_domain,
199 err->rseqno, err->wseqno);
200 err_puts(m, pin_flag(err->pinned));
201 err_puts(m, tiling_flag(err->tiling));
202 err_puts(m, dirty_flag(err->dirty));
203 err_puts(m, purgeable_flag(err->purgeable));
204 err_puts(m, err->ring != -1 ? " " : "");
205 err_puts(m, ring_str(err->ring));
206 err_puts(m, i915_cache_level_str(err->cache_level));
207
208 if (err->name)
209 err_printf(m, " (name: %d)", err->name);
210 if (err->fence_reg != I915_FENCE_REG_NONE)
211 err_printf(m, " (fence: %d)", err->fence_reg);
212
213 err_puts(m, "\n");
214 err++;
215 }
216 }
217
218 static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
219 {
220 switch (a) {
221 case HANGCHECK_IDLE:
222 return "idle";
223 case HANGCHECK_WAIT:
224 return "wait";
225 case HANGCHECK_ACTIVE:
226 return "active";
227 case HANGCHECK_KICK:
228 return "kick";
229 case HANGCHECK_HUNG:
230 return "hung";
231 }
232
233 return "unknown";
234 }
235
236 static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
237 struct drm_device *dev,
238 struct drm_i915_error_ring *ring)
239 {
240 if (!ring->valid)
241 return;
242
243 err_printf(m, " HEAD: 0x%08x\n", ring->head);
244 err_printf(m, " TAIL: 0x%08x\n", ring->tail);
245 err_printf(m, " CTL: 0x%08x\n", ring->ctl);
246 err_printf(m, " HWS: 0x%08x\n", ring->hws);
247 err_printf(m, " ACTHD: 0x%08x\n", ring->acthd);
248 err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir);
249 err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr);
250 err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone);
251 if (INTEL_INFO(dev)->gen >= 4) {
252 err_printf(m, " BBADDR: 0x%08llx\n", ring->bbaddr);
253 err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate);
254 err_printf(m, " INSTPS: 0x%08x\n", ring->instps);
255 }
256 err_printf(m, " INSTPM: 0x%08x\n", ring->instpm);
257 err_printf(m, " FADDR: 0x%08x\n", ring->faddr);
258 if (INTEL_INFO(dev)->gen >= 6) {
259 err_printf(m, " RC PSMI: 0x%08x\n", ring->rc_psmi);
260 err_printf(m, " FAULT_REG: 0x%08x\n", ring->fault_reg);
261 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
262 ring->semaphore_mboxes[0],
263 ring->semaphore_seqno[0]);
264 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
265 ring->semaphore_mboxes[1],
266 ring->semaphore_seqno[1]);
267 if (HAS_VEBOX(dev)) {
268 err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n",
269 ring->semaphore_mboxes[2],
270 ring->semaphore_seqno[2]);
271 }
272 }
273 if (USES_PPGTT(dev)) {
274 err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode);
275
276 if (INTEL_INFO(dev)->gen >= 8) {
277 int i;
278 for (i = 0; i < 4; i++)
279 err_printf(m, " PDP%d: 0x%016llx\n",
280 i, ring->vm_info.pdp[i]);
281 } else {
282 err_printf(m, " PP_DIR_BASE: 0x%08x\n",
283 ring->vm_info.pp_dir_base);
284 }
285 }
286 err_printf(m, " seqno: 0x%08x\n", ring->seqno);
287 err_printf(m, " waiting: %s\n", yesno(ring->waiting));
288 err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head);
289 err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail);
290 err_printf(m, " hangcheck: %s [%d]\n",
291 hangcheck_action_to_str(ring->hangcheck_action),
292 ring->hangcheck_score);
293 }
294
295 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
296 {
297 va_list args;
298
299 va_start(args, f);
300 i915_error_vprintf(e, f, args);
301 va_end(args);
302 }
303
304 static void print_error_obj(struct drm_i915_error_state_buf *m,
305 struct drm_i915_error_object *obj)
306 {
307 int page, offset, elt;
308
309 for (page = offset = 0; page < obj->page_count; page++) {
310 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
311 err_printf(m, "%08x : %08x\n", offset,
312 obj->pages[page][elt]);
313 offset += 4;
314 }
315 }
316 }
317
318 int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
319 const struct i915_error_state_file_priv *error_priv)
320 {
321 struct drm_device *dev = error_priv->dev;
322 drm_i915_private_t *dev_priv = dev->dev_private;
323 struct drm_i915_error_state *error = error_priv->error;
324 int i, j, offset, elt;
325 int max_hangcheck_score;
326
327 if (!error) {
328 err_printf(m, "no error state collected\n");
329 goto out;
330 }
331
332 err_printf(m, "%s\n", error->error_msg);
333 err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
334 error->time.tv_usec);
335 err_printf(m, "Kernel: " UTS_RELEASE "\n");
336 max_hangcheck_score = 0;
337 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
338 if (error->ring[i].hangcheck_score > max_hangcheck_score)
339 max_hangcheck_score = error->ring[i].hangcheck_score;
340 }
341 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
342 if (error->ring[i].hangcheck_score == max_hangcheck_score &&
343 error->ring[i].pid != -1) {
344 err_printf(m, "Active process (on ring %s): %s [%d]\n",
345 ring_str(i),
346 error->ring[i].comm,
347 error->ring[i].pid);
348 }
349 }
350 err_printf(m, "Reset count: %u\n", error->reset_count);
351 err_printf(m, "Suspend count: %u\n", error->suspend_count);
352 err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
353 err_printf(m, "EIR: 0x%08x\n", error->eir);
354 err_printf(m, "IER: 0x%08x\n", error->ier);
355 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
356 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
357 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
358 err_printf(m, "CCID: 0x%08x\n", error->ccid);
359 err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
360
361 for (i = 0; i < dev_priv->num_fence_regs; i++)
362 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
363
364 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
365 err_printf(m, " INSTDONE_%d: 0x%08x\n", i,
366 error->extra_instdone[i]);
367
368 if (INTEL_INFO(dev)->gen >= 6) {
369 err_printf(m, "ERROR: 0x%08x\n", error->error);
370 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
371 }
372
373 if (INTEL_INFO(dev)->gen == 7)
374 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
375
376 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
377 err_printf(m, "%s command stream:\n", ring_str(i));
378 i915_ring_error_state(m, dev, &error->ring[i]);
379 }
380
381 if (error->active_bo)
382 print_error_buffers(m, "Active",
383 error->active_bo[0],
384 error->active_bo_count[0]);
385
386 if (error->pinned_bo)
387 print_error_buffers(m, "Pinned",
388 error->pinned_bo[0],
389 error->pinned_bo_count[0]);
390
391 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
392 struct drm_i915_error_object *obj;
393
394 obj = error->ring[i].batchbuffer;
395 if (obj) {
396 err_puts(m, dev_priv->ring[i].name);
397 if (error->ring[i].pid != -1)
398 err_printf(m, " (submitted by %s [%d])",
399 error->ring[i].comm,
400 error->ring[i].pid);
401 err_printf(m, " --- gtt_offset = 0x%08x\n",
402 obj->gtt_offset);
403 print_error_obj(m, obj);
404 }
405
406 obj = error->ring[i].wa_batchbuffer;
407 if (obj) {
408 err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n",
409 dev_priv->ring[i].name, obj->gtt_offset);
410 print_error_obj(m, obj);
411 }
412
413 if (error->ring[i].num_requests) {
414 err_printf(m, "%s --- %d requests\n",
415 dev_priv->ring[i].name,
416 error->ring[i].num_requests);
417 for (j = 0; j < error->ring[i].num_requests; j++) {
418 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
419 error->ring[i].requests[j].seqno,
420 error->ring[i].requests[j].jiffies,
421 error->ring[i].requests[j].tail);
422 }
423 }
424
425 if ((obj = error->ring[i].ringbuffer)) {
426 err_printf(m, "%s --- ringbuffer = 0x%08x\n",
427 dev_priv->ring[i].name,
428 obj->gtt_offset);
429 print_error_obj(m, obj);
430 }
431
432 if ((obj = error->ring[i].hws_page)) {
433 err_printf(m, "%s --- HW Status = 0x%08x\n",
434 dev_priv->ring[i].name,
435 obj->gtt_offset);
436 offset = 0;
437 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
438 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
439 offset,
440 obj->pages[0][elt],
441 obj->pages[0][elt+1],
442 obj->pages[0][elt+2],
443 obj->pages[0][elt+3]);
444 offset += 16;
445 }
446 }
447
448 if ((obj = error->ring[i].ctx)) {
449 err_printf(m, "%s --- HW Context = 0x%08x\n",
450 dev_priv->ring[i].name,
451 obj->gtt_offset);
452 offset = 0;
453 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
454 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
455 offset,
456 obj->pages[0][elt],
457 obj->pages[0][elt+1],
458 obj->pages[0][elt+2],
459 obj->pages[0][elt+3]);
460 offset += 16;
461 }
462 }
463 }
464
465 if (error->overlay)
466 intel_overlay_print_error_state(m, error->overlay);
467
468 if (error->display)
469 intel_display_print_error_state(m, dev, error->display);
470
471 out:
472 if (m->bytes == 0 && m->err)
473 return m->err;
474
475 return 0;
476 }
477
478 int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
479 size_t count, loff_t pos)
480 {
481 memset(ebuf, 0, sizeof(*ebuf));
482
483 /* We need to have enough room to store any i915_error_state printf
484 * so that we can move it to start position.
485 */
486 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
487 ebuf->buf = kmalloc(ebuf->size,
488 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);
489
490 if (ebuf->buf == NULL) {
491 ebuf->size = PAGE_SIZE;
492 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
493 }
494
495 if (ebuf->buf == NULL) {
496 ebuf->size = 128;
497 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
498 }
499
500 if (ebuf->buf == NULL)
501 return -ENOMEM;
502
503 ebuf->start = pos;
504
505 return 0;
506 }
507
508 static void i915_error_object_free(struct drm_i915_error_object *obj)
509 {
510 int page;
511
512 if (obj == NULL)
513 return;
514
515 for (page = 0; page < obj->page_count; page++)
516 kfree(obj->pages[page]);
517
518 kfree(obj);
519 }
520
521 static void i915_error_state_free(struct kref *error_ref)
522 {
523 struct drm_i915_error_state *error = container_of(error_ref,
524 typeof(*error), ref);
525 int i;
526
527 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
528 i915_error_object_free(error->ring[i].batchbuffer);
529 i915_error_object_free(error->ring[i].ringbuffer);
530 i915_error_object_free(error->ring[i].hws_page);
531 i915_error_object_free(error->ring[i].ctx);
532 kfree(error->ring[i].requests);
533 }
534
535 kfree(error->active_bo);
536 kfree(error->overlay);
537 kfree(error->display);
538 kfree(error);
539 }
540
541 static struct drm_i915_error_object *
542 i915_error_object_create_sized(struct drm_i915_private *dev_priv,
543 struct drm_i915_gem_object *src,
544 struct i915_address_space *vm,
545 const int num_pages)
546 {
547 struct drm_i915_error_object *dst;
548 int i;
549 u32 reloc_offset;
550
551 if (src == NULL || src->pages == NULL)
552 return NULL;
553
554 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
555 if (dst == NULL)
556 return NULL;
557
558 reloc_offset = dst->gtt_offset = i915_gem_obj_offset(src, vm);
559 for (i = 0; i < num_pages; i++) {
560 unsigned long flags;
561 void *d;
562
563 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
564 if (d == NULL)
565 goto unwind;
566
567 local_irq_save(flags);
568 if (src->cache_level == I915_CACHE_NONE &&
569 reloc_offset < dev_priv->gtt.mappable_end &&
570 src->has_global_gtt_mapping &&
571 i915_is_ggtt(vm)) {
572 void __iomem *s;
573
574 /* Simply ignore tiling or any overlapping fence.
575 * It's part of the error state, and this hopefully
576 * captures what the GPU read.
577 */
578
579 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
580 reloc_offset);
581 memcpy_fromio(d, s, PAGE_SIZE);
582 io_mapping_unmap_atomic(s);
583 } else if (src->stolen) {
584 unsigned long offset;
585
586 offset = dev_priv->mm.stolen_base;
587 offset += src->stolen->start;
588 offset += i << PAGE_SHIFT;
589
590 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
591 } else {
592 struct page *page;
593 void *s;
594
595 page = i915_gem_object_get_page(src, i);
596
597 drm_clflush_pages(&page, 1);
598
599 s = kmap_atomic(page);
600 memcpy(d, s, PAGE_SIZE);
601 kunmap_atomic(s);
602
603 drm_clflush_pages(&page, 1);
604 }
605 local_irq_restore(flags);
606
607 dst->pages[i] = d;
608
609 reloc_offset += PAGE_SIZE;
610 }
611 dst->page_count = num_pages;
612
613 return dst;
614
615 unwind:
616 while (i--)
617 kfree(dst->pages[i]);
618 kfree(dst);
619 return NULL;
620 }
621 #define i915_error_object_create(dev_priv, src, vm) \
622 i915_error_object_create_sized((dev_priv), (src), (vm), \
623 (src)->base.size>>PAGE_SHIFT)
624
625 #define i915_error_ggtt_object_create(dev_priv, src) \
626 i915_error_object_create_sized((dev_priv), (src), &(dev_priv)->gtt.base, \
627 (src)->base.size>>PAGE_SHIFT)
628
629 static void capture_bo(struct drm_i915_error_buffer *err,
630 struct drm_i915_gem_object *obj)
631 {
632 err->size = obj->base.size;
633 err->name = obj->base.name;
634 err->rseqno = obj->last_read_seqno;
635 err->wseqno = obj->last_write_seqno;
636 err->gtt_offset = i915_gem_obj_ggtt_offset(obj);
637 err->read_domains = obj->base.read_domains;
638 err->write_domain = obj->base.write_domain;
639 err->fence_reg = obj->fence_reg;
640 err->pinned = 0;
641 if (i915_gem_obj_is_pinned(obj))
642 err->pinned = 1;
643 if (obj->user_pin_count > 0)
644 err->pinned = -1;
645 err->tiling = obj->tiling_mode;
646 err->dirty = obj->dirty;
647 err->purgeable = obj->madv != I915_MADV_WILLNEED;
648 err->ring = obj->ring ? obj->ring->id : -1;
649 err->cache_level = obj->cache_level;
650 }
651
652 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
653 int count, struct list_head *head)
654 {
655 struct i915_vma *vma;
656 int i = 0;
657
658 list_for_each_entry(vma, head, mm_list) {
659 capture_bo(err++, vma->obj);
660 if (++i == count)
661 break;
662 }
663
664 return i;
665 }
666
667 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
668 int count, struct list_head *head)
669 {
670 struct drm_i915_gem_object *obj;
671 int i = 0;
672
673 list_for_each_entry(obj, head, global_list) {
674 if (!i915_gem_obj_is_pinned(obj))
675 continue;
676
677 capture_bo(err++, obj);
678 if (++i == count)
679 break;
680 }
681
682 return i;
683 }
684
685 /* Generate a semi-unique error code. The code is not meant to have meaning, The
686 * code's only purpose is to try to prevent false duplicated bug reports by
687 * grossly estimating a GPU error state.
688 *
689 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
690 * the hang if we could strip the GTT offset information from it.
691 *
692 * It's only a small step better than a random number in its current form.
693 */
694 static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
695 struct drm_i915_error_state *error,
696 int *ring_id)
697 {
698 uint32_t error_code = 0;
699 int i;
700
701 /* IPEHR would be an ideal way to detect errors, as it's the gross
702 * measure of "the command that hung." However, has some very common
703 * synchronization commands which almost always appear in the case
704 * strictly a client bug. Use instdone to differentiate those some.
705 */
706 for (i = 0; i < I915_NUM_RINGS; i++) {
707 if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) {
708 if (ring_id)
709 *ring_id = i;
710
711 return error->ring[i].ipehr ^ error->ring[i].instdone;
712 }
713 }
714
715 return error_code;
716 }
717
718 static void i915_gem_record_fences(struct drm_device *dev,
719 struct drm_i915_error_state *error)
720 {
721 struct drm_i915_private *dev_priv = dev->dev_private;
722 int i;
723
724 /* Fences */
725 switch (INTEL_INFO(dev)->gen) {
726 case 8:
727 case 7:
728 case 6:
729 for (i = 0; i < dev_priv->num_fence_regs; i++)
730 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
731 break;
732 case 5:
733 case 4:
734 for (i = 0; i < 16; i++)
735 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
736 break;
737 case 3:
738 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
739 for (i = 0; i < 8; i++)
740 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
741 case 2:
742 for (i = 0; i < 8; i++)
743 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
744 break;
745
746 default:
747 BUG();
748 }
749 }
750
751 static void i915_record_ring_state(struct drm_device *dev,
752 struct intel_ring_buffer *ring,
753 struct drm_i915_error_ring *ering)
754 {
755 struct drm_i915_private *dev_priv = dev->dev_private;
756
757 if (INTEL_INFO(dev)->gen >= 6) {
758 ering->rc_psmi = I915_READ(ring->mmio_base + 0x50);
759 ering->fault_reg = I915_READ(RING_FAULT_REG(ring));
760 ering->semaphore_mboxes[0]
761 = I915_READ(RING_SYNC_0(ring->mmio_base));
762 ering->semaphore_mboxes[1]
763 = I915_READ(RING_SYNC_1(ring->mmio_base));
764 ering->semaphore_seqno[0] = ring->sync_seqno[0];
765 ering->semaphore_seqno[1] = ring->sync_seqno[1];
766 }
767
768 if (HAS_VEBOX(dev)) {
769 ering->semaphore_mboxes[2] =
770 I915_READ(RING_SYNC_2(ring->mmio_base));
771 ering->semaphore_seqno[2] = ring->sync_seqno[2];
772 }
773
774 if (INTEL_INFO(dev)->gen >= 4) {
775 ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base));
776 ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base));
777 ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
778 ering->instdone = I915_READ(RING_INSTDONE(ring->mmio_base));
779 ering->instps = I915_READ(RING_INSTPS(ring->mmio_base));
780 ering->bbaddr = I915_READ(RING_BBADDR(ring->mmio_base));
781 if (INTEL_INFO(dev)->gen >= 8)
782 ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32;
783 ering->bbstate = I915_READ(RING_BBSTATE(ring->mmio_base));
784 } else {
785 ering->faddr = I915_READ(DMA_FADD_I8XX);
786 ering->ipeir = I915_READ(IPEIR);
787 ering->ipehr = I915_READ(IPEHR);
788 ering->instdone = I915_READ(INSTDONE);
789 }
790
791 ering->waiting = waitqueue_active(&ring->irq_queue);
792 ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base));
793 ering->seqno = ring->get_seqno(ring, false);
794 ering->acthd = intel_ring_get_active_head(ring);
795 ering->head = I915_READ_HEAD(ring);
796 ering->tail = I915_READ_TAIL(ring);
797 ering->ctl = I915_READ_CTL(ring);
798
799 if (I915_NEED_GFX_HWS(dev)) {
800 int mmio;
801
802 if (IS_GEN7(dev)) {
803 switch (ring->id) {
804 default:
805 case RCS:
806 mmio = RENDER_HWS_PGA_GEN7;
807 break;
808 case BCS:
809 mmio = BLT_HWS_PGA_GEN7;
810 break;
811 case VCS:
812 mmio = BSD_HWS_PGA_GEN7;
813 break;
814 case VECS:
815 mmio = VEBOX_HWS_PGA_GEN7;
816 break;
817 }
818 } else if (IS_GEN6(ring->dev)) {
819 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
820 } else {
821 /* XXX: gen8 returns to sanity */
822 mmio = RING_HWS_PGA(ring->mmio_base);
823 }
824
825 ering->hws = I915_READ(mmio);
826 }
827
828 ering->cpu_ring_head = ring->head;
829 ering->cpu_ring_tail = ring->tail;
830
831 ering->hangcheck_score = ring->hangcheck.score;
832 ering->hangcheck_action = ring->hangcheck.action;
833
834 if (USES_PPGTT(dev)) {
835 int i;
836
837 ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(ring));
838
839 switch (INTEL_INFO(dev)->gen) {
840 case 8:
841 for (i = 0; i < 4; i++) {
842 ering->vm_info.pdp[i] =
843 I915_READ(GEN8_RING_PDP_UDW(ring, i));
844 ering->vm_info.pdp[i] <<= 32;
845 ering->vm_info.pdp[i] |=
846 I915_READ(GEN8_RING_PDP_LDW(ring, i));
847 }
848 break;
849 case 7:
850 ering->vm_info.pp_dir_base = RING_PP_DIR_BASE(ring);
851 break;
852 case 6:
853 ering->vm_info.pp_dir_base = RING_PP_DIR_BASE_READ(ring);
854 break;
855 }
856 }
857 }
858
859
860 static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
861 struct drm_i915_error_state *error,
862 struct drm_i915_error_ring *ering)
863 {
864 struct drm_i915_private *dev_priv = ring->dev->dev_private;
865 struct drm_i915_gem_object *obj;
866
867 /* Currently render ring is the only HW context user */
868 if (ring->id != RCS || !error->ccid)
869 return;
870
871 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
872 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
873 ering->ctx = i915_error_object_create_sized(dev_priv,
874 obj,
875 &dev_priv->gtt.base,
876 1);
877 break;
878 }
879 }
880 }
881
882 static void i915_gem_record_rings(struct drm_device *dev,
883 struct drm_i915_error_state *error)
884 {
885 struct drm_i915_private *dev_priv = dev->dev_private;
886 struct drm_i915_gem_request *request;
887 int i, count;
888
889 for (i = 0; i < I915_NUM_RINGS; i++) {
890 struct intel_ring_buffer *ring = &dev_priv->ring[i];
891
892 if (ring->dev == NULL)
893 continue;
894
895 error->ring[i].valid = true;
896
897 i915_record_ring_state(dev, ring, &error->ring[i]);
898
899 error->ring[i].pid = -1;
900 request = i915_gem_find_active_request(ring);
901 if (request) {
902 /* We need to copy these to an anonymous buffer
903 * as the simplest method to avoid being overwritten
904 * by userspace.
905 */
906 error->ring[i].batchbuffer =
907 i915_error_object_create(dev_priv,
908 request->batch_obj,
909 request->ctx ?
910 request->ctx->vm :
911 &dev_priv->gtt.base);
912
913 if (HAS_BROKEN_CS_TLB(dev_priv->dev) &&
914 ring->scratch.obj)
915 error->ring[i].wa_batchbuffer =
916 i915_error_ggtt_object_create(dev_priv,
917 ring->scratch.obj);
918
919 if (request->file_priv) {
920 struct task_struct *task;
921
922 rcu_read_lock();
923 task = pid_task(request->file_priv->file->pid,
924 PIDTYPE_PID);
925 if (task) {
926 strcpy(error->ring[i].comm, task->comm);
927 error->ring[i].pid = task->pid;
928 }
929 rcu_read_unlock();
930 }
931 }
932
933 error->ring[i].ringbuffer =
934 i915_error_ggtt_object_create(dev_priv, ring->obj);
935
936 if (ring->status_page.obj)
937 error->ring[i].hws_page =
938 i915_error_ggtt_object_create(dev_priv, ring->status_page.obj);
939
940 i915_gem_record_active_context(ring, error, &error->ring[i]);
941
942 count = 0;
943 list_for_each_entry(request, &ring->request_list, list)
944 count++;
945
946 error->ring[i].num_requests = count;
947 error->ring[i].requests =
948 kcalloc(count, sizeof(*error->ring[i].requests),
949 GFP_ATOMIC);
950 if (error->ring[i].requests == NULL) {
951 error->ring[i].num_requests = 0;
952 continue;
953 }
954
955 count = 0;
956 list_for_each_entry(request, &ring->request_list, list) {
957 struct drm_i915_error_request *erq;
958
959 erq = &error->ring[i].requests[count++];
960 erq->seqno = request->seqno;
961 erq->jiffies = request->emitted_jiffies;
962 erq->tail = request->tail;
963 }
964 }
965 }
966
967 /* FIXME: Since pin count/bound list is global, we duplicate what we capture per
968 * VM.
969 */
970 static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
971 struct drm_i915_error_state *error,
972 struct i915_address_space *vm,
973 const int ndx)
974 {
975 struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL;
976 struct drm_i915_gem_object *obj;
977 struct i915_vma *vma;
978 int i;
979
980 i = 0;
981 list_for_each_entry(vma, &vm->active_list, mm_list)
982 i++;
983 error->active_bo_count[ndx] = i;
984 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
985 if (i915_gem_obj_is_pinned(obj))
986 i++;
987 error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx];
988
989 if (i) {
990 active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC);
991 if (active_bo)
992 pinned_bo = active_bo + error->active_bo_count[ndx];
993 }
994
995 if (active_bo)
996 error->active_bo_count[ndx] =
997 capture_active_bo(active_bo,
998 error->active_bo_count[ndx],
999 &vm->active_list);
1000
1001 if (pinned_bo)
1002 error->pinned_bo_count[ndx] =
1003 capture_pinned_bo(pinned_bo,
1004 error->pinned_bo_count[ndx],
1005 &dev_priv->mm.bound_list);
1006 error->active_bo[ndx] = active_bo;
1007 error->pinned_bo[ndx] = pinned_bo;
1008 }
1009
1010 static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
1011 struct drm_i915_error_state *error)
1012 {
1013 struct i915_address_space *vm;
1014 int cnt = 0, i = 0;
1015
1016 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
1017 cnt++;
1018
1019 error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC);
1020 error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC);
1021 error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count),
1022 GFP_ATOMIC);
1023 error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count),
1024 GFP_ATOMIC);
1025
1026 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
1027 i915_gem_capture_vm(dev_priv, error, vm, i++);
1028 }
1029
1030 /* Capture all registers which don't fit into another category. */
1031 static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
1032 struct drm_i915_error_state *error)
1033 {
1034 struct drm_device *dev = dev_priv->dev;
1035 int pipe;
1036
1037 /* General organization
1038 * 1. Registers specific to a single generation
1039 * 2. Registers which belong to multiple generations
1040 * 3. Feature specific registers.
1041 * 4. Everything else
1042 * Please try to follow the order.
1043 */
1044
1045 /* 1: Registers specific to a single generation */
1046 if (IS_VALLEYVIEW(dev)) {
1047 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1048 error->forcewake = I915_READ(FORCEWAKE_VLV);
1049 }
1050
1051 if (IS_GEN7(dev))
1052 error->err_int = I915_READ(GEN7_ERR_INT);
1053
1054 if (IS_GEN6(dev)) {
1055 error->forcewake = I915_READ(FORCEWAKE);
1056 error->gab_ctl = I915_READ(GAB_CTL);
1057 error->gfx_mode = I915_READ(GFX_MODE);
1058 }
1059
1060 if (IS_GEN2(dev))
1061 error->ier = I915_READ16(IER);
1062
1063 /* 2: Registers which belong to multiple generations */
1064 if (INTEL_INFO(dev)->gen >= 7)
1065 error->forcewake = I915_READ(FORCEWAKE_MT);
1066
1067 if (INTEL_INFO(dev)->gen >= 6) {
1068 error->derrmr = I915_READ(DERRMR);
1069 error->error = I915_READ(ERROR_GEN6);
1070 error->done_reg = I915_READ(DONE_REG);
1071 }
1072
1073 /* 3: Feature specific registers */
1074 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1075 error->gam_ecochk = I915_READ(GAM_ECOCHK);
1076 error->gac_eco = I915_READ(GAC_ECO_BITS);
1077 }
1078
1079 /* 4: Everything else */
1080 if (HAS_HW_CONTEXTS(dev))
1081 error->ccid = I915_READ(CCID);
1082
1083 if (HAS_PCH_SPLIT(dev))
1084 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1085 else {
1086 error->ier = I915_READ(IER);
1087 for_each_pipe(pipe)
1088 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1089 }
1090
1091 /* 4: Everything else */
1092 error->eir = I915_READ(EIR);
1093 error->pgtbl_er = I915_READ(PGTBL_ER);
1094
1095 i915_get_extra_instdone(dev, error->extra_instdone);
1096 }
1097
1098 static void i915_error_capture_msg(struct drm_device *dev,
1099 struct drm_i915_error_state *error,
1100 bool wedged,
1101 const char *error_msg)
1102 {
1103 struct drm_i915_private *dev_priv = dev->dev_private;
1104 u32 ecode;
1105 int ring_id = -1, len;
1106
1107 ecode = i915_error_generate_code(dev_priv, error, &ring_id);
1108
1109 len = scnprintf(error->error_msg, sizeof(error->error_msg),
1110 "GPU HANG: ecode %d:0x%08x", ring_id, ecode);
1111
1112 if (ring_id != -1 && error->ring[ring_id].pid != -1)
1113 len += scnprintf(error->error_msg + len,
1114 sizeof(error->error_msg) - len,
1115 ", in %s [%d]",
1116 error->ring[ring_id].comm,
1117 error->ring[ring_id].pid);
1118
1119 scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
1120 ", reason: %s, action: %s",
1121 error_msg,
1122 wedged ? "reset" : "continue");
1123 }
1124
1125 static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
1126 struct drm_i915_error_state *error)
1127 {
1128 error->reset_count = i915_reset_count(&dev_priv->gpu_error);
1129 error->suspend_count = dev_priv->suspend_count;
1130 }
1131
1132 /**
1133 * i915_capture_error_state - capture an error record for later analysis
1134 * @dev: drm device
1135 *
1136 * Should be called when an error is detected (either a hang or an error
1137 * interrupt) to capture error state from the time of the error. Fills
1138 * out a structure which becomes available in debugfs for user level tools
1139 * to pick up.
1140 */
1141 void i915_capture_error_state(struct drm_device *dev, bool wedged,
1142 const char *error_msg)
1143 {
1144 static bool warned;
1145 struct drm_i915_private *dev_priv = dev->dev_private;
1146 struct drm_i915_error_state *error;
1147 unsigned long flags;
1148
1149 /* Account for pipe specific data like PIPE*STAT */
1150 error = kzalloc(sizeof(*error), GFP_ATOMIC);
1151 if (!error) {
1152 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1153 return;
1154 }
1155
1156 kref_init(&error->ref);
1157
1158 i915_capture_gen_state(dev_priv, error);
1159 i915_capture_reg_state(dev_priv, error);
1160 i915_gem_capture_buffers(dev_priv, error);
1161 i915_gem_record_fences(dev, error);
1162 i915_gem_record_rings(dev, error);
1163
1164 do_gettimeofday(&error->time);
1165
1166 error->overlay = intel_overlay_capture_error_state(dev);
1167 error->display = intel_display_capture_error_state(dev);
1168
1169 i915_error_capture_msg(dev, error, wedged, error_msg);
1170 DRM_INFO("%s\n", error->error_msg);
1171
1172 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1173 if (dev_priv->gpu_error.first_error == NULL) {
1174 dev_priv->gpu_error.first_error = error;
1175 error = NULL;
1176 }
1177 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1178
1179 if (error) {
1180 i915_error_state_free(&error->ref);
1181 return;
1182 }
1183
1184 if (!warned) {
1185 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1186 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
1187 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1188 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
1189 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev->primary->index);
1190 warned = true;
1191 }
1192 }
1193
1194 void i915_error_state_get(struct drm_device *dev,
1195 struct i915_error_state_file_priv *error_priv)
1196 {
1197 struct drm_i915_private *dev_priv = dev->dev_private;
1198 unsigned long flags;
1199
1200 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1201 error_priv->error = dev_priv->gpu_error.first_error;
1202 if (error_priv->error)
1203 kref_get(&error_priv->error->ref);
1204 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1205
1206 }
1207
1208 void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
1209 {
1210 if (error_priv->error)
1211 kref_put(&error_priv->error->ref, i915_error_state_free);
1212 }
1213
1214 void i915_destroy_error_state(struct drm_device *dev)
1215 {
1216 struct drm_i915_private *dev_priv = dev->dev_private;
1217 struct drm_i915_error_state *error;
1218 unsigned long flags;
1219
1220 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1221 error = dev_priv->gpu_error.first_error;
1222 dev_priv->gpu_error.first_error = NULL;
1223 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1224
1225 if (error)
1226 kref_put(&error->ref, i915_error_state_free);
1227 }
1228
1229 const char *i915_cache_level_str(int type)
1230 {
1231 switch (type) {
1232 case I915_CACHE_NONE: return " uncached";
1233 case I915_CACHE_LLC: return " snooped or LLC";
1234 case I915_CACHE_L3_LLC: return " L3+LLC";
1235 case I915_CACHE_WT: return " WT";
1236 default: return "";
1237 }
1238 }
1239
1240 /* NB: please notice the memset */
1241 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone)
1242 {
1243 struct drm_i915_private *dev_priv = dev->dev_private;
1244 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1245
1246 switch (INTEL_INFO(dev)->gen) {
1247 case 2:
1248 case 3:
1249 instdone[0] = I915_READ(INSTDONE);
1250 break;
1251 case 4:
1252 case 5:
1253 case 6:
1254 instdone[0] = I915_READ(INSTDONE_I965);
1255 instdone[1] = I915_READ(INSTDONE1);
1256 break;
1257 default:
1258 WARN_ONCE(1, "Unsupported platform\n");
1259 case 7:
1260 case 8:
1261 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1262 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1263 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1264 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1265 break;
1266 }
1267 }
Linux kernel - Deliverables
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