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Merge remote-tracking branch 'airlied/drm-next' into drm-intel-next
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gpu_error.c
1 /*
2 * Copyright (c) 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 * Mika Kuoppala <mika.kuoppala@intel.com>
27 *
28 */
29
30 #include <generated/utsrelease.h>
31 #include "i915_drv.h"
32
33 static const char *yesno(int v)
34 {
35 return v ? "yes" : "no";
36 }
37
38 static const char *ring_str(int ring)
39 {
40 switch (ring) {
41 case RCS: return "render";
42 case VCS: return "bsd";
43 case BCS: return "blt";
44 case VECS: return "vebox";
45 default: return "";
46 }
47 }
48
49 static const char *pin_flag(int pinned)
50 {
51 if (pinned > 0)
52 return " P";
53 else if (pinned < 0)
54 return " p";
55 else
56 return "";
57 }
58
59 static const char *tiling_flag(int tiling)
60 {
61 switch (tiling) {
62 default:
63 case I915_TILING_NONE: return "";
64 case I915_TILING_X: return " X";
65 case I915_TILING_Y: return " Y";
66 }
67 }
68
69 static const char *dirty_flag(int dirty)
70 {
71 return dirty ? " dirty" : "";
72 }
73
74 static const char *purgeable_flag(int purgeable)
75 {
76 return purgeable ? " purgeable" : "";
77 }
78
79 static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
80 {
81
82 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
83 e->err = -ENOSPC;
84 return false;
85 }
86
87 if (e->bytes == e->size - 1 || e->err)
88 return false;
89
90 return true;
91 }
92
93 static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
94 unsigned len)
95 {
96 if (e->pos + len <= e->start) {
97 e->pos += len;
98 return false;
99 }
100
101 /* First vsnprintf needs to fit in its entirety for memmove */
102 if (len >= e->size) {
103 e->err = -EIO;
104 return false;
105 }
106
107 return true;
108 }
109
110 static void __i915_error_advance(struct drm_i915_error_state_buf *e,
111 unsigned len)
112 {
113 /* If this is first printf in this window, adjust it so that
114 * start position matches start of the buffer
115 */
116
117 if (e->pos < e->start) {
118 const size_t off = e->start - e->pos;
119
120 /* Should not happen but be paranoid */
121 if (off > len || e->bytes) {
122 e->err = -EIO;
123 return;
124 }
125
126 memmove(e->buf, e->buf + off, len - off);
127 e->bytes = len - off;
128 e->pos = e->start;
129 return;
130 }
131
132 e->bytes += len;
133 e->pos += len;
134 }
135
136 static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
137 const char *f, va_list args)
138 {
139 unsigned len;
140
141 if (!__i915_error_ok(e))
142 return;
143
144 /* Seek the first printf which is hits start position */
145 if (e->pos < e->start) {
146 va_list tmp;
147
148 va_copy(tmp, args);
149 if (!__i915_error_seek(e, vsnprintf(NULL, 0, f, tmp)))
150 return;
151 }
152
153 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
154 if (len >= e->size - e->bytes)
155 len = e->size - e->bytes - 1;
156
157 __i915_error_advance(e, len);
158 }
159
160 static void i915_error_puts(struct drm_i915_error_state_buf *e,
161 const char *str)
162 {
163 unsigned len;
164
165 if (!__i915_error_ok(e))
166 return;
167
168 len = strlen(str);
169
170 /* Seek the first printf which is hits start position */
171 if (e->pos < e->start) {
172 if (!__i915_error_seek(e, len))
173 return;
174 }
175
176 if (len >= e->size - e->bytes)
177 len = e->size - e->bytes - 1;
178 memcpy(e->buf + e->bytes, str, len);
179
180 __i915_error_advance(e, len);
181 }
182
183 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
184 #define err_puts(e, s) i915_error_puts(e, s)
185
186 static void print_error_buffers(struct drm_i915_error_state_buf *m,
187 const char *name,
188 struct drm_i915_error_buffer *err,
189 int count)
190 {
191 err_printf(m, "%s [%d]:\n", name, count);
192
193 while (count--) {
194 err_printf(m, " %08x %8u %02x %02x %x %x",
195 err->gtt_offset,
196 err->size,
197 err->read_domains,
198 err->write_domain,
199 err->rseqno, err->wseqno);
200 err_puts(m, pin_flag(err->pinned));
201 err_puts(m, tiling_flag(err->tiling));
202 err_puts(m, dirty_flag(err->dirty));
203 err_puts(m, purgeable_flag(err->purgeable));
204 err_puts(m, err->ring != -1 ? " " : "");
205 err_puts(m, ring_str(err->ring));
206 err_puts(m, i915_cache_level_str(err->cache_level));
207
208 if (err->name)
209 err_printf(m, " (name: %d)", err->name);
210 if (err->fence_reg != I915_FENCE_REG_NONE)
211 err_printf(m, " (fence: %d)", err->fence_reg);
212
213 err_puts(m, "\n");
214 err++;
215 }
216 }
217
218 static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
219 {
220 switch (a) {
221 case HANGCHECK_IDLE:
222 return "idle";
223 case HANGCHECK_WAIT:
224 return "wait";
225 case HANGCHECK_ACTIVE:
226 return "active";
227 case HANGCHECK_KICK:
228 return "kick";
229 case HANGCHECK_HUNG:
230 return "hung";
231 }
232
233 return "unknown";
234 }
235
236 static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
237 struct drm_device *dev,
238 struct drm_i915_error_state *error,
239 unsigned ring)
240 {
241 BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */
242 err_printf(m, "%s command stream:\n", ring_str(ring));
243 err_printf(m, " HEAD: 0x%08x\n", error->head[ring]);
244 err_printf(m, " TAIL: 0x%08x\n", error->tail[ring]);
245 err_printf(m, " CTL: 0x%08x\n", error->ctl[ring]);
246 err_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]);
247 err_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]);
248 err_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]);
249 err_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]);
250 if (ring == RCS && INTEL_INFO(dev)->gen >= 4)
251 err_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr);
252
253 if (INTEL_INFO(dev)->gen >= 4)
254 err_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]);
255 err_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]);
256 err_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]);
257 if (INTEL_INFO(dev)->gen >= 6) {
258 err_printf(m, " RC PSMI: 0x%08x\n", error->rc_psmi[ring]);
259 err_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]);
260 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
261 error->semaphore_mboxes[ring][0],
262 error->semaphore_seqno[ring][0]);
263 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
264 error->semaphore_mboxes[ring][1],
265 error->semaphore_seqno[ring][1]);
266 if (HAS_VEBOX(dev)) {
267 err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n",
268 error->semaphore_mboxes[ring][2],
269 error->semaphore_seqno[ring][2]);
270 }
271 }
272 err_printf(m, " seqno: 0x%08x\n", error->seqno[ring]);
273 err_printf(m, " waiting: %s\n", yesno(error->waiting[ring]));
274 err_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]);
275 err_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]);
276 err_printf(m, " hangcheck: %s [%d]\n",
277 hangcheck_action_to_str(error->hangcheck_action[ring]),
278 error->hangcheck_score[ring]);
279 }
280
281 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
282 {
283 va_list args;
284
285 va_start(args, f);
286 i915_error_vprintf(e, f, args);
287 va_end(args);
288 }
289
290 int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
291 const struct i915_error_state_file_priv *error_priv)
292 {
293 struct drm_device *dev = error_priv->dev;
294 drm_i915_private_t *dev_priv = dev->dev_private;
295 struct drm_i915_error_state *error = error_priv->error;
296 struct intel_ring_buffer *ring;
297 int i, j, page, offset, elt;
298
299 if (!error) {
300 err_printf(m, "no error state collected\n");
301 goto out;
302 }
303
304 err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
305 error->time.tv_usec);
306 err_printf(m, "Kernel: " UTS_RELEASE "\n");
307 err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
308 err_printf(m, "EIR: 0x%08x\n", error->eir);
309 err_printf(m, "IER: 0x%08x\n", error->ier);
310 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
311 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
312 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
313 err_printf(m, "CCID: 0x%08x\n", error->ccid);
314 err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
315
316 for (i = 0; i < dev_priv->num_fence_regs; i++)
317 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
318
319 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
320 err_printf(m, " INSTDONE_%d: 0x%08x\n", i,
321 error->extra_instdone[i]);
322
323 if (INTEL_INFO(dev)->gen >= 6) {
324 err_printf(m, "ERROR: 0x%08x\n", error->error);
325 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
326 }
327
328 if (INTEL_INFO(dev)->gen == 7)
329 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
330
331 for_each_ring(ring, dev_priv, i)
332 i915_ring_error_state(m, dev, error, i);
333
334 if (error->active_bo)
335 print_error_buffers(m, "Active",
336 error->active_bo[0],
337 error->active_bo_count[0]);
338
339 if (error->pinned_bo)
340 print_error_buffers(m, "Pinned",
341 error->pinned_bo[0],
342 error->pinned_bo_count[0]);
343
344 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
345 struct drm_i915_error_object *obj;
346
347 if ((obj = error->ring[i].batchbuffer)) {
348 err_printf(m, "%s --- gtt_offset = 0x%08x\n",
349 dev_priv->ring[i].name,
350 obj->gtt_offset);
351 offset = 0;
352 for (page = 0; page < obj->page_count; page++) {
353 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
354 err_printf(m, "%08x : %08x\n", offset,
355 obj->pages[page][elt]);
356 offset += 4;
357 }
358 }
359 }
360
361 if (error->ring[i].num_requests) {
362 err_printf(m, "%s --- %d requests\n",
363 dev_priv->ring[i].name,
364 error->ring[i].num_requests);
365 for (j = 0; j < error->ring[i].num_requests; j++) {
366 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
367 error->ring[i].requests[j].seqno,
368 error->ring[i].requests[j].jiffies,
369 error->ring[i].requests[j].tail);
370 }
371 }
372
373 if ((obj = error->ring[i].ringbuffer)) {
374 err_printf(m, "%s --- ringbuffer = 0x%08x\n",
375 dev_priv->ring[i].name,
376 obj->gtt_offset);
377 offset = 0;
378 for (page = 0; page < obj->page_count; page++) {
379 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
380 err_printf(m, "%08x : %08x\n",
381 offset,
382 obj->pages[page][elt]);
383 offset += 4;
384 }
385 }
386 }
387
388 obj = error->ring[i].ctx;
389 if (obj) {
390 err_printf(m, "%s --- HW Context = 0x%08x\n",
391 dev_priv->ring[i].name,
392 obj->gtt_offset);
393 offset = 0;
394 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
395 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
396 offset,
397 obj->pages[0][elt],
398 obj->pages[0][elt+1],
399 obj->pages[0][elt+2],
400 obj->pages[0][elt+3]);
401 offset += 16;
402 }
403 }
404 }
405
406 if (error->overlay)
407 intel_overlay_print_error_state(m, error->overlay);
408
409 if (error->display)
410 intel_display_print_error_state(m, dev, error->display);
411
412 out:
413 if (m->bytes == 0 && m->err)
414 return m->err;
415
416 return 0;
417 }
418
419 int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
420 size_t count, loff_t pos)
421 {
422 memset(ebuf, 0, sizeof(*ebuf));
423
424 /* We need to have enough room to store any i915_error_state printf
425 * so that we can move it to start position.
426 */
427 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
428 ebuf->buf = kmalloc(ebuf->size,
429 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);
430
431 if (ebuf->buf == NULL) {
432 ebuf->size = PAGE_SIZE;
433 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
434 }
435
436 if (ebuf->buf == NULL) {
437 ebuf->size = 128;
438 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
439 }
440
441 if (ebuf->buf == NULL)
442 return -ENOMEM;
443
444 ebuf->start = pos;
445
446 return 0;
447 }
448
449 static void i915_error_object_free(struct drm_i915_error_object *obj)
450 {
451 int page;
452
453 if (obj == NULL)
454 return;
455
456 for (page = 0; page < obj->page_count; page++)
457 kfree(obj->pages[page]);
458
459 kfree(obj);
460 }
461
462 static void i915_error_state_free(struct kref *error_ref)
463 {
464 struct drm_i915_error_state *error = container_of(error_ref,
465 typeof(*error), ref);
466 int i;
467
468 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
469 i915_error_object_free(error->ring[i].batchbuffer);
470 i915_error_object_free(error->ring[i].ringbuffer);
471 i915_error_object_free(error->ring[i].ctx);
472 kfree(error->ring[i].requests);
473 }
474
475 kfree(error->active_bo);
476 kfree(error->overlay);
477 kfree(error->display);
478 kfree(error);
479 }
480
481 static struct drm_i915_error_object *
482 i915_error_object_create_sized(struct drm_i915_private *dev_priv,
483 struct drm_i915_gem_object *src,
484 const int num_pages)
485 {
486 struct drm_i915_error_object *dst;
487 int i;
488 u32 reloc_offset;
489
490 if (src == NULL || src->pages == NULL)
491 return NULL;
492
493 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
494 if (dst == NULL)
495 return NULL;
496
497 reloc_offset = dst->gtt_offset = i915_gem_obj_ggtt_offset(src);
498 for (i = 0; i < num_pages; i++) {
499 unsigned long flags;
500 void *d;
501
502 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
503 if (d == NULL)
504 goto unwind;
505
506 local_irq_save(flags);
507 if (reloc_offset < dev_priv->gtt.mappable_end &&
508 src->has_global_gtt_mapping) {
509 void __iomem *s;
510
511 /* Simply ignore tiling or any overlapping fence.
512 * It's part of the error state, and this hopefully
513 * captures what the GPU read.
514 */
515
516 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
517 reloc_offset);
518 memcpy_fromio(d, s, PAGE_SIZE);
519 io_mapping_unmap_atomic(s);
520 } else if (src->stolen) {
521 unsigned long offset;
522
523 offset = dev_priv->mm.stolen_base;
524 offset += src->stolen->start;
525 offset += i << PAGE_SHIFT;
526
527 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
528 } else {
529 struct page *page;
530 void *s;
531
532 page = i915_gem_object_get_page(src, i);
533
534 drm_clflush_pages(&page, 1);
535
536 s = kmap_atomic(page);
537 memcpy(d, s, PAGE_SIZE);
538 kunmap_atomic(s);
539
540 drm_clflush_pages(&page, 1);
541 }
542 local_irq_restore(flags);
543
544 dst->pages[i] = d;
545
546 reloc_offset += PAGE_SIZE;
547 }
548 dst->page_count = num_pages;
549
550 return dst;
551
552 unwind:
553 while (i--)
554 kfree(dst->pages[i]);
555 kfree(dst);
556 return NULL;
557 }
558 #define i915_error_object_create(dev_priv, src) \
559 i915_error_object_create_sized((dev_priv), (src), \
560 (src)->base.size>>PAGE_SHIFT)
561
562 static void capture_bo(struct drm_i915_error_buffer *err,
563 struct drm_i915_gem_object *obj)
564 {
565 err->size = obj->base.size;
566 err->name = obj->base.name;
567 err->rseqno = obj->last_read_seqno;
568 err->wseqno = obj->last_write_seqno;
569 err->gtt_offset = i915_gem_obj_ggtt_offset(obj);
570 err->read_domains = obj->base.read_domains;
571 err->write_domain = obj->base.write_domain;
572 err->fence_reg = obj->fence_reg;
573 err->pinned = 0;
574 if (obj->pin_count > 0)
575 err->pinned = 1;
576 if (obj->user_pin_count > 0)
577 err->pinned = -1;
578 err->tiling = obj->tiling_mode;
579 err->dirty = obj->dirty;
580 err->purgeable = obj->madv != I915_MADV_WILLNEED;
581 err->ring = obj->ring ? obj->ring->id : -1;
582 err->cache_level = obj->cache_level;
583 }
584
585 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
586 int count, struct list_head *head)
587 {
588 struct i915_vma *vma;
589 int i = 0;
590
591 list_for_each_entry(vma, head, mm_list) {
592 capture_bo(err++, vma->obj);
593 if (++i == count)
594 break;
595 }
596
597 return i;
598 }
599
600 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
601 int count, struct list_head *head)
602 {
603 struct drm_i915_gem_object *obj;
604 int i = 0;
605
606 list_for_each_entry(obj, head, global_list) {
607 if (obj->pin_count == 0)
608 continue;
609
610 capture_bo(err++, obj);
611 if (++i == count)
612 break;
613 }
614
615 return i;
616 }
617
618 static void i915_gem_record_fences(struct drm_device *dev,
619 struct drm_i915_error_state *error)
620 {
621 struct drm_i915_private *dev_priv = dev->dev_private;
622 int i;
623
624 /* Fences */
625 switch (INTEL_INFO(dev)->gen) {
626 case 7:
627 case 6:
628 for (i = 0; i < dev_priv->num_fence_regs; i++)
629 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
630 break;
631 case 5:
632 case 4:
633 for (i = 0; i < 16; i++)
634 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
635 break;
636 case 3:
637 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
638 for (i = 0; i < 8; i++)
639 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
640 case 2:
641 for (i = 0; i < 8; i++)
642 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
643 break;
644
645 default:
646 BUG();
647 }
648 }
649
650 static struct drm_i915_error_object *
651 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
652 struct intel_ring_buffer *ring)
653 {
654 struct i915_address_space *vm;
655 struct i915_vma *vma;
656 struct drm_i915_gem_object *obj;
657 u32 seqno;
658
659 if (!ring->get_seqno)
660 return NULL;
661
662 if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
663 u32 acthd = I915_READ(ACTHD);
664
665 if (WARN_ON(ring->id != RCS))
666 return NULL;
667
668 obj = ring->scratch.obj;
669 if (acthd >= i915_gem_obj_ggtt_offset(obj) &&
670 acthd < i915_gem_obj_ggtt_offset(obj) + obj->base.size)
671 return i915_error_object_create(dev_priv, obj);
672 }
673
674 seqno = ring->get_seqno(ring, false);
675 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
676 list_for_each_entry(vma, &vm->active_list, mm_list) {
677 obj = vma->obj;
678 if (obj->ring != ring)
679 continue;
680
681 if (i915_seqno_passed(seqno, obj->last_read_seqno))
682 continue;
683
684 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
685 continue;
686
687 /* We need to copy these to an anonymous buffer as the simplest
688 * method to avoid being overwritten by userspace.
689 */
690 return i915_error_object_create(dev_priv, obj);
691 }
692 }
693
694 return NULL;
695 }
696
697 static void i915_record_ring_state(struct drm_device *dev,
698 struct drm_i915_error_state *error,
699 struct intel_ring_buffer *ring)
700 {
701 struct drm_i915_private *dev_priv = dev->dev_private;
702
703 if (INTEL_INFO(dev)->gen >= 6) {
704 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
705 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
706 error->semaphore_mboxes[ring->id][0]
707 = I915_READ(RING_SYNC_0(ring->mmio_base));
708 error->semaphore_mboxes[ring->id][1]
709 = I915_READ(RING_SYNC_1(ring->mmio_base));
710 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
711 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
712 }
713
714 if (HAS_VEBOX(dev)) {
715 error->semaphore_mboxes[ring->id][2] =
716 I915_READ(RING_SYNC_2(ring->mmio_base));
717 error->semaphore_seqno[ring->id][2] = ring->sync_seqno[2];
718 }
719
720 if (INTEL_INFO(dev)->gen >= 4) {
721 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
722 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
723 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
724 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
725 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
726 if (ring->id == RCS)
727 error->bbaddr = I915_READ64(BB_ADDR);
728 } else {
729 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
730 error->ipeir[ring->id] = I915_READ(IPEIR);
731 error->ipehr[ring->id] = I915_READ(IPEHR);
732 error->instdone[ring->id] = I915_READ(INSTDONE);
733 }
734
735 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
736 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
737 error->seqno[ring->id] = ring->get_seqno(ring, false);
738 error->acthd[ring->id] = intel_ring_get_active_head(ring);
739 error->head[ring->id] = I915_READ_HEAD(ring);
740 error->tail[ring->id] = I915_READ_TAIL(ring);
741 error->ctl[ring->id] = I915_READ_CTL(ring);
742
743 error->cpu_ring_head[ring->id] = ring->head;
744 error->cpu_ring_tail[ring->id] = ring->tail;
745
746 error->hangcheck_score[ring->id] = ring->hangcheck.score;
747 error->hangcheck_action[ring->id] = ring->hangcheck.action;
748 }
749
750
751 static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
752 struct drm_i915_error_state *error,
753 struct drm_i915_error_ring *ering)
754 {
755 struct drm_i915_private *dev_priv = ring->dev->dev_private;
756 struct drm_i915_gem_object *obj;
757
758 /* Currently render ring is the only HW context user */
759 if (ring->id != RCS || !error->ccid)
760 return;
761
762 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
763 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
764 ering->ctx = i915_error_object_create_sized(dev_priv,
765 obj, 1);
766 break;
767 }
768 }
769 }
770
771 static void i915_gem_record_rings(struct drm_device *dev,
772 struct drm_i915_error_state *error)
773 {
774 struct drm_i915_private *dev_priv = dev->dev_private;
775 struct intel_ring_buffer *ring;
776 struct drm_i915_gem_request *request;
777 int i, count;
778
779 for_each_ring(ring, dev_priv, i) {
780 i915_record_ring_state(dev, error, ring);
781
782 error->ring[i].batchbuffer =
783 i915_error_first_batchbuffer(dev_priv, ring);
784
785 error->ring[i].ringbuffer =
786 i915_error_object_create(dev_priv, ring->obj);
787
788
789 i915_gem_record_active_context(ring, error, &error->ring[i]);
790
791 count = 0;
792 list_for_each_entry(request, &ring->request_list, list)
793 count++;
794
795 error->ring[i].num_requests = count;
796 error->ring[i].requests =
797 kcalloc(count, sizeof(*error->ring[i].requests),
798 GFP_ATOMIC);
799 if (error->ring[i].requests == NULL) {
800 error->ring[i].num_requests = 0;
801 continue;
802 }
803
804 count = 0;
805 list_for_each_entry(request, &ring->request_list, list) {
806 struct drm_i915_error_request *erq;
807
808 erq = &error->ring[i].requests[count++];
809 erq->seqno = request->seqno;
810 erq->jiffies = request->emitted_jiffies;
811 erq->tail = request->tail;
812 }
813 }
814 }
815
816 /* FIXME: Since pin count/bound list is global, we duplicate what we capture per
817 * VM.
818 */
819 static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
820 struct drm_i915_error_state *error,
821 struct i915_address_space *vm,
822 const int ndx)
823 {
824 struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL;
825 struct drm_i915_gem_object *obj;
826 struct i915_vma *vma;
827 int i;
828
829 i = 0;
830 list_for_each_entry(vma, &vm->active_list, mm_list)
831 i++;
832 error->active_bo_count[ndx] = i;
833 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
834 if (obj->pin_count)
835 i++;
836 error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx];
837
838 if (i) {
839 active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC);
840 if (active_bo)
841 pinned_bo = active_bo + error->active_bo_count[ndx];
842 }
843
844 if (active_bo)
845 error->active_bo_count[ndx] =
846 capture_active_bo(active_bo,
847 error->active_bo_count[ndx],
848 &vm->active_list);
849
850 if (pinned_bo)
851 error->pinned_bo_count[ndx] =
852 capture_pinned_bo(pinned_bo,
853 error->pinned_bo_count[ndx],
854 &dev_priv->mm.bound_list);
855 error->active_bo[ndx] = active_bo;
856 error->pinned_bo[ndx] = pinned_bo;
857 }
858
859 static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
860 struct drm_i915_error_state *error)
861 {
862 struct i915_address_space *vm;
863 int cnt = 0, i = 0;
864
865 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
866 cnt++;
867
868 if (WARN(cnt > 1, "Multiple VMs not yet supported\n"))
869 cnt = 1;
870
871 vm = &dev_priv->gtt.base;
872
873 error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC);
874 error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC);
875 error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count),
876 GFP_ATOMIC);
877 error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count),
878 GFP_ATOMIC);
879
880 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
881 i915_gem_capture_vm(dev_priv, error, vm, i++);
882 }
883
884 /**
885 * i915_capture_error_state - capture an error record for later analysis
886 * @dev: drm device
887 *
888 * Should be called when an error is detected (either a hang or an error
889 * interrupt) to capture error state from the time of the error. Fills
890 * out a structure which becomes available in debugfs for user level tools
891 * to pick up.
892 */
893 void i915_capture_error_state(struct drm_device *dev)
894 {
895 struct drm_i915_private *dev_priv = dev->dev_private;
896 struct drm_i915_error_state *error;
897 unsigned long flags;
898 int pipe;
899
900 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
901 error = dev_priv->gpu_error.first_error;
902 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
903 if (error)
904 return;
905
906 /* Account for pipe specific data like PIPE*STAT */
907 error = kzalloc(sizeof(*error), GFP_ATOMIC);
908 if (!error) {
909 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
910 return;
911 }
912
913 DRM_INFO("capturing error event; look for more information in "
914 "/sys/class/drm/card%d/error\n", dev->primary->index);
915
916 kref_init(&error->ref);
917 error->eir = I915_READ(EIR);
918 error->pgtbl_er = I915_READ(PGTBL_ER);
919 if (HAS_HW_CONTEXTS(dev))
920 error->ccid = I915_READ(CCID);
921
922 if (HAS_PCH_SPLIT(dev))
923 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
924 else if (IS_VALLEYVIEW(dev))
925 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
926 else if (IS_GEN2(dev))
927 error->ier = I915_READ16(IER);
928 else
929 error->ier = I915_READ(IER);
930
931 if (INTEL_INFO(dev)->gen >= 6)
932 error->derrmr = I915_READ(DERRMR);
933
934 if (IS_VALLEYVIEW(dev))
935 error->forcewake = I915_READ(FORCEWAKE_VLV);
936 else if (INTEL_INFO(dev)->gen >= 7)
937 error->forcewake = I915_READ(FORCEWAKE_MT);
938 else if (INTEL_INFO(dev)->gen == 6)
939 error->forcewake = I915_READ(FORCEWAKE);
940
941 if (!HAS_PCH_SPLIT(dev))
942 for_each_pipe(pipe)
943 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
944
945 if (INTEL_INFO(dev)->gen >= 6) {
946 error->error = I915_READ(ERROR_GEN6);
947 error->done_reg = I915_READ(DONE_REG);
948 }
949
950 if (INTEL_INFO(dev)->gen == 7)
951 error->err_int = I915_READ(GEN7_ERR_INT);
952
953 i915_get_extra_instdone(dev, error->extra_instdone);
954
955 i915_gem_capture_buffers(dev_priv, error);
956 i915_gem_record_fences(dev, error);
957 i915_gem_record_rings(dev, error);
958
959 do_gettimeofday(&error->time);
960
961 error->overlay = intel_overlay_capture_error_state(dev);
962 error->display = intel_display_capture_error_state(dev);
963
964 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
965 if (dev_priv->gpu_error.first_error == NULL) {
966 dev_priv->gpu_error.first_error = error;
967 error = NULL;
968 }
969 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
970
971 if (error)
972 i915_error_state_free(&error->ref);
973 }
974
975 void i915_error_state_get(struct drm_device *dev,
976 struct i915_error_state_file_priv *error_priv)
977 {
978 struct drm_i915_private *dev_priv = dev->dev_private;
979 unsigned long flags;
980
981 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
982 error_priv->error = dev_priv->gpu_error.first_error;
983 if (error_priv->error)
984 kref_get(&error_priv->error->ref);
985 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
986
987 }
988
989 void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
990 {
991 if (error_priv->error)
992 kref_put(&error_priv->error->ref, i915_error_state_free);
993 }
994
995 void i915_destroy_error_state(struct drm_device *dev)
996 {
997 struct drm_i915_private *dev_priv = dev->dev_private;
998 struct drm_i915_error_state *error;
999 unsigned long flags;
1000
1001 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1002 error = dev_priv->gpu_error.first_error;
1003 dev_priv->gpu_error.first_error = NULL;
1004 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1005
1006 if (error)
1007 kref_put(&error->ref, i915_error_state_free);
1008 }
1009
1010 const char *i915_cache_level_str(int type)
1011 {
1012 switch (type) {
1013 case I915_CACHE_NONE: return " uncached";
1014 case I915_CACHE_LLC: return " snooped or LLC";
1015 case I915_CACHE_L3_LLC: return " L3+LLC";
1016 case I915_CACHE_WT: return " WT";
1017 default: return "";
1018 }
1019 }
1020
1021 /* NB: please notice the memset */
1022 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone)
1023 {
1024 struct drm_i915_private *dev_priv = dev->dev_private;
1025 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1026
1027 switch (INTEL_INFO(dev)->gen) {
1028 case 2:
1029 case 3:
1030 instdone[0] = I915_READ(INSTDONE);
1031 break;
1032 case 4:
1033 case 5:
1034 case 6:
1035 instdone[0] = I915_READ(INSTDONE_I965);
1036 instdone[1] = I915_READ(INSTDONE1);
1037 break;
1038 default:
1039 WARN_ONCE(1, "Unsupported platform\n");
1040 case 7:
1041 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1042 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1043 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1044 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1045 break;
1046 }
1047 }
Linux kernel - Deliverables
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