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drm/i915: Use kcalloc more
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gpu_error.c
1 /*
2 * Copyright (c) 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 * Mika Kuoppala <mika.kuoppala@intel.com>
27 *
28 */
29
30 #include <generated/utsrelease.h>
31 #include "i915_drv.h"
32
33 static const char *yesno(int v)
34 {
35 return v ? "yes" : "no";
36 }
37
38 static const char *ring_str(int ring)
39 {
40 switch (ring) {
41 case RCS: return "render";
42 case VCS: return "bsd";
43 case BCS: return "blt";
44 case VECS: return "vebox";
45 default: return "";
46 }
47 }
48
49 static const char *pin_flag(int pinned)
50 {
51 if (pinned > 0)
52 return " P";
53 else if (pinned < 0)
54 return " p";
55 else
56 return "";
57 }
58
59 static const char *tiling_flag(int tiling)
60 {
61 switch (tiling) {
62 default:
63 case I915_TILING_NONE: return "";
64 case I915_TILING_X: return " X";
65 case I915_TILING_Y: return " Y";
66 }
67 }
68
69 static const char *dirty_flag(int dirty)
70 {
71 return dirty ? " dirty" : "";
72 }
73
74 static const char *purgeable_flag(int purgeable)
75 {
76 return purgeable ? " purgeable" : "";
77 }
78
79 static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
80 {
81
82 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
83 e->err = -ENOSPC;
84 return false;
85 }
86
87 if (e->bytes == e->size - 1 || e->err)
88 return false;
89
90 return true;
91 }
92
93 static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
94 unsigned len)
95 {
96 if (e->pos + len <= e->start) {
97 e->pos += len;
98 return false;
99 }
100
101 /* First vsnprintf needs to fit in its entirety for memmove */
102 if (len >= e->size) {
103 e->err = -EIO;
104 return false;
105 }
106
107 return true;
108 }
109
110 static void __i915_error_advance(struct drm_i915_error_state_buf *e,
111 unsigned len)
112 {
113 /* If this is first printf in this window, adjust it so that
114 * start position matches start of the buffer
115 */
116
117 if (e->pos < e->start) {
118 const size_t off = e->start - e->pos;
119
120 /* Should not happen but be paranoid */
121 if (off > len || e->bytes) {
122 e->err = -EIO;
123 return;
124 }
125
126 memmove(e->buf, e->buf + off, len - off);
127 e->bytes = len - off;
128 e->pos = e->start;
129 return;
130 }
131
132 e->bytes += len;
133 e->pos += len;
134 }
135
136 static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
137 const char *f, va_list args)
138 {
139 unsigned len;
140
141 if (!__i915_error_ok(e))
142 return;
143
144 /* Seek the first printf which is hits start position */
145 if (e->pos < e->start) {
146 va_list tmp;
147
148 va_copy(tmp, args);
149 if (!__i915_error_seek(e, vsnprintf(NULL, 0, f, tmp)))
150 return;
151 }
152
153 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
154 if (len >= e->size - e->bytes)
155 len = e->size - e->bytes - 1;
156
157 __i915_error_advance(e, len);
158 }
159
160 static void i915_error_puts(struct drm_i915_error_state_buf *e,
161 const char *str)
162 {
163 unsigned len;
164
165 if (!__i915_error_ok(e))
166 return;
167
168 len = strlen(str);
169
170 /* Seek the first printf which is hits start position */
171 if (e->pos < e->start) {
172 if (!__i915_error_seek(e, len))
173 return;
174 }
175
176 if (len >= e->size - e->bytes)
177 len = e->size - e->bytes - 1;
178 memcpy(e->buf + e->bytes, str, len);
179
180 __i915_error_advance(e, len);
181 }
182
183 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
184 #define err_puts(e, s) i915_error_puts(e, s)
185
186 static void print_error_buffers(struct drm_i915_error_state_buf *m,
187 const char *name,
188 struct drm_i915_error_buffer *err,
189 int count)
190 {
191 err_printf(m, "%s [%d]:\n", name, count);
192
193 while (count--) {
194 err_printf(m, " %08x %8u %02x %02x %x %x",
195 err->gtt_offset,
196 err->size,
197 err->read_domains,
198 err->write_domain,
199 err->rseqno, err->wseqno);
200 err_puts(m, pin_flag(err->pinned));
201 err_puts(m, tiling_flag(err->tiling));
202 err_puts(m, dirty_flag(err->dirty));
203 err_puts(m, purgeable_flag(err->purgeable));
204 err_puts(m, err->ring != -1 ? " " : "");
205 err_puts(m, ring_str(err->ring));
206 err_puts(m, i915_cache_level_str(err->cache_level));
207
208 if (err->name)
209 err_printf(m, " (name: %d)", err->name);
210 if (err->fence_reg != I915_FENCE_REG_NONE)
211 err_printf(m, " (fence: %d)", err->fence_reg);
212
213 err_puts(m, "\n");
214 err++;
215 }
216 }
217
218 static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
219 {
220 switch (a) {
221 case HANGCHECK_IDLE:
222 return "idle";
223 case HANGCHECK_WAIT:
224 return "wait";
225 case HANGCHECK_ACTIVE:
226 return "active";
227 case HANGCHECK_KICK:
228 return "kick";
229 case HANGCHECK_HUNG:
230 return "hung";
231 }
232
233 return "unknown";
234 }
235
236 static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
237 struct drm_device *dev,
238 struct drm_i915_error_state *error,
239 unsigned ring)
240 {
241 BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */
242 err_printf(m, "%s command stream:\n", ring_str(ring));
243 err_printf(m, " HEAD: 0x%08x\n", error->head[ring]);
244 err_printf(m, " TAIL: 0x%08x\n", error->tail[ring]);
245 err_printf(m, " CTL: 0x%08x\n", error->ctl[ring]);
246 err_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]);
247 err_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]);
248 err_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]);
249 err_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]);
250 if (ring == RCS && INTEL_INFO(dev)->gen >= 4)
251 err_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr);
252
253 if (INTEL_INFO(dev)->gen >= 4)
254 err_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]);
255 err_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]);
256 err_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]);
257 if (INTEL_INFO(dev)->gen >= 6) {
258 err_printf(m, " RC PSMI: 0x%08x\n", error->rc_psmi[ring]);
259 err_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]);
260 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
261 error->semaphore_mboxes[ring][0],
262 error->semaphore_seqno[ring][0]);
263 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
264 error->semaphore_mboxes[ring][1],
265 error->semaphore_seqno[ring][1]);
266 if (HAS_VEBOX(dev)) {
267 err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n",
268 error->semaphore_mboxes[ring][2],
269 error->semaphore_seqno[ring][2]);
270 }
271 }
272 err_printf(m, " seqno: 0x%08x\n", error->seqno[ring]);
273 err_printf(m, " waiting: %s\n", yesno(error->waiting[ring]));
274 err_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]);
275 err_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]);
276 err_printf(m, " hangcheck: %s [%d]\n",
277 hangcheck_action_to_str(error->hangcheck_action[ring]),
278 error->hangcheck_score[ring]);
279 }
280
281 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
282 {
283 va_list args;
284
285 va_start(args, f);
286 i915_error_vprintf(e, f, args);
287 va_end(args);
288 }
289
290 int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
291 const struct i915_error_state_file_priv *error_priv)
292 {
293 struct drm_device *dev = error_priv->dev;
294 drm_i915_private_t *dev_priv = dev->dev_private;
295 struct drm_i915_error_state *error = error_priv->error;
296 struct intel_ring_buffer *ring;
297 int i, j, page, offset, elt;
298
299 if (!error) {
300 err_printf(m, "no error state collected\n");
301 goto out;
302 }
303
304 err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
305 error->time.tv_usec);
306 err_printf(m, "Kernel: " UTS_RELEASE "\n");
307 err_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
308 err_printf(m, "EIR: 0x%08x\n", error->eir);
309 err_printf(m, "IER: 0x%08x\n", error->ier);
310 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
311 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
312 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
313 err_printf(m, "CCID: 0x%08x\n", error->ccid);
314
315 for (i = 0; i < dev_priv->num_fence_regs; i++)
316 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
317
318 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
319 err_printf(m, " INSTDONE_%d: 0x%08x\n", i,
320 error->extra_instdone[i]);
321
322 if (INTEL_INFO(dev)->gen >= 6) {
323 err_printf(m, "ERROR: 0x%08x\n", error->error);
324 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
325 }
326
327 if (INTEL_INFO(dev)->gen == 7)
328 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
329
330 for_each_ring(ring, dev_priv, i)
331 i915_ring_error_state(m, dev, error, i);
332
333 if (error->active_bo)
334 print_error_buffers(m, "Active",
335 error->active_bo[0],
336 error->active_bo_count[0]);
337
338 if (error->pinned_bo)
339 print_error_buffers(m, "Pinned",
340 error->pinned_bo[0],
341 error->pinned_bo_count[0]);
342
343 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
344 struct drm_i915_error_object *obj;
345
346 if ((obj = error->ring[i].batchbuffer)) {
347 err_printf(m, "%s --- gtt_offset = 0x%08x\n",
348 dev_priv->ring[i].name,
349 obj->gtt_offset);
350 offset = 0;
351 for (page = 0; page < obj->page_count; page++) {
352 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
353 err_printf(m, "%08x : %08x\n", offset,
354 obj->pages[page][elt]);
355 offset += 4;
356 }
357 }
358 }
359
360 if (error->ring[i].num_requests) {
361 err_printf(m, "%s --- %d requests\n",
362 dev_priv->ring[i].name,
363 error->ring[i].num_requests);
364 for (j = 0; j < error->ring[i].num_requests; j++) {
365 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
366 error->ring[i].requests[j].seqno,
367 error->ring[i].requests[j].jiffies,
368 error->ring[i].requests[j].tail);
369 }
370 }
371
372 if ((obj = error->ring[i].ringbuffer)) {
373 err_printf(m, "%s --- ringbuffer = 0x%08x\n",
374 dev_priv->ring[i].name,
375 obj->gtt_offset);
376 offset = 0;
377 for (page = 0; page < obj->page_count; page++) {
378 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
379 err_printf(m, "%08x : %08x\n",
380 offset,
381 obj->pages[page][elt]);
382 offset += 4;
383 }
384 }
385 }
386
387 obj = error->ring[i].ctx;
388 if (obj) {
389 err_printf(m, "%s --- HW Context = 0x%08x\n",
390 dev_priv->ring[i].name,
391 obj->gtt_offset);
392 offset = 0;
393 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
394 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
395 offset,
396 obj->pages[0][elt],
397 obj->pages[0][elt+1],
398 obj->pages[0][elt+2],
399 obj->pages[0][elt+3]);
400 offset += 16;
401 }
402 }
403 }
404
405 if (error->overlay)
406 intel_overlay_print_error_state(m, error->overlay);
407
408 if (error->display)
409 intel_display_print_error_state(m, dev, error->display);
410
411 out:
412 if (m->bytes == 0 && m->err)
413 return m->err;
414
415 return 0;
416 }
417
418 int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
419 size_t count, loff_t pos)
420 {
421 memset(ebuf, 0, sizeof(*ebuf));
422
423 /* We need to have enough room to store any i915_error_state printf
424 * so that we can move it to start position.
425 */
426 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
427 ebuf->buf = kmalloc(ebuf->size,
428 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);
429
430 if (ebuf->buf == NULL) {
431 ebuf->size = PAGE_SIZE;
432 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
433 }
434
435 if (ebuf->buf == NULL) {
436 ebuf->size = 128;
437 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
438 }
439
440 if (ebuf->buf == NULL)
441 return -ENOMEM;
442
443 ebuf->start = pos;
444
445 return 0;
446 }
447
448 static void i915_error_object_free(struct drm_i915_error_object *obj)
449 {
450 int page;
451
452 if (obj == NULL)
453 return;
454
455 for (page = 0; page < obj->page_count; page++)
456 kfree(obj->pages[page]);
457
458 kfree(obj);
459 }
460
461 static void i915_error_state_free(struct kref *error_ref)
462 {
463 struct drm_i915_error_state *error = container_of(error_ref,
464 typeof(*error), ref);
465 int i;
466
467 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
468 i915_error_object_free(error->ring[i].batchbuffer);
469 i915_error_object_free(error->ring[i].ringbuffer);
470 i915_error_object_free(error->ring[i].ctx);
471 kfree(error->ring[i].requests);
472 }
473
474 kfree(error->active_bo);
475 kfree(error->overlay);
476 kfree(error->display);
477 kfree(error);
478 }
479
480 static struct drm_i915_error_object *
481 i915_error_object_create_sized(struct drm_i915_private *dev_priv,
482 struct drm_i915_gem_object *src,
483 const int num_pages)
484 {
485 struct drm_i915_error_object *dst;
486 int i;
487 u32 reloc_offset;
488
489 if (src == NULL || src->pages == NULL)
490 return NULL;
491
492 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
493 if (dst == NULL)
494 return NULL;
495
496 reloc_offset = dst->gtt_offset = i915_gem_obj_ggtt_offset(src);
497 for (i = 0; i < num_pages; i++) {
498 unsigned long flags;
499 void *d;
500
501 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
502 if (d == NULL)
503 goto unwind;
504
505 local_irq_save(flags);
506 if (reloc_offset < dev_priv->gtt.mappable_end &&
507 src->has_global_gtt_mapping) {
508 void __iomem *s;
509
510 /* Simply ignore tiling or any overlapping fence.
511 * It's part of the error state, and this hopefully
512 * captures what the GPU read.
513 */
514
515 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
516 reloc_offset);
517 memcpy_fromio(d, s, PAGE_SIZE);
518 io_mapping_unmap_atomic(s);
519 } else if (src->stolen) {
520 unsigned long offset;
521
522 offset = dev_priv->mm.stolen_base;
523 offset += src->stolen->start;
524 offset += i << PAGE_SHIFT;
525
526 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
527 } else {
528 struct page *page;
529 void *s;
530
531 page = i915_gem_object_get_page(src, i);
532
533 drm_clflush_pages(&page, 1);
534
535 s = kmap_atomic(page);
536 memcpy(d, s, PAGE_SIZE);
537 kunmap_atomic(s);
538
539 drm_clflush_pages(&page, 1);
540 }
541 local_irq_restore(flags);
542
543 dst->pages[i] = d;
544
545 reloc_offset += PAGE_SIZE;
546 }
547 dst->page_count = num_pages;
548
549 return dst;
550
551 unwind:
552 while (i--)
553 kfree(dst->pages[i]);
554 kfree(dst);
555 return NULL;
556 }
557 #define i915_error_object_create(dev_priv, src) \
558 i915_error_object_create_sized((dev_priv), (src), \
559 (src)->base.size>>PAGE_SHIFT)
560
561 static void capture_bo(struct drm_i915_error_buffer *err,
562 struct drm_i915_gem_object *obj)
563 {
564 err->size = obj->base.size;
565 err->name = obj->base.name;
566 err->rseqno = obj->last_read_seqno;
567 err->wseqno = obj->last_write_seqno;
568 err->gtt_offset = i915_gem_obj_ggtt_offset(obj);
569 err->read_domains = obj->base.read_domains;
570 err->write_domain = obj->base.write_domain;
571 err->fence_reg = obj->fence_reg;
572 err->pinned = 0;
573 if (obj->pin_count > 0)
574 err->pinned = 1;
575 if (obj->user_pin_count > 0)
576 err->pinned = -1;
577 err->tiling = obj->tiling_mode;
578 err->dirty = obj->dirty;
579 err->purgeable = obj->madv != I915_MADV_WILLNEED;
580 err->ring = obj->ring ? obj->ring->id : -1;
581 err->cache_level = obj->cache_level;
582 }
583
584 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
585 int count, struct list_head *head)
586 {
587 struct i915_vma *vma;
588 int i = 0;
589
590 list_for_each_entry(vma, head, mm_list) {
591 capture_bo(err++, vma->obj);
592 if (++i == count)
593 break;
594 }
595
596 return i;
597 }
598
599 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
600 int count, struct list_head *head)
601 {
602 struct drm_i915_gem_object *obj;
603 int i = 0;
604
605 list_for_each_entry(obj, head, global_list) {
606 if (obj->pin_count == 0)
607 continue;
608
609 capture_bo(err++, obj);
610 if (++i == count)
611 break;
612 }
613
614 return i;
615 }
616
617 static void i915_gem_record_fences(struct drm_device *dev,
618 struct drm_i915_error_state *error)
619 {
620 struct drm_i915_private *dev_priv = dev->dev_private;
621 int i;
622
623 /* Fences */
624 switch (INTEL_INFO(dev)->gen) {
625 case 7:
626 case 6:
627 for (i = 0; i < dev_priv->num_fence_regs; i++)
628 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
629 break;
630 case 5:
631 case 4:
632 for (i = 0; i < 16; i++)
633 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
634 break;
635 case 3:
636 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
637 for (i = 0; i < 8; i++)
638 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
639 case 2:
640 for (i = 0; i < 8; i++)
641 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
642 break;
643
644 default:
645 BUG();
646 }
647 }
648
649 static struct drm_i915_error_object *
650 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
651 struct intel_ring_buffer *ring)
652 {
653 struct i915_address_space *vm;
654 struct i915_vma *vma;
655 struct drm_i915_gem_object *obj;
656 u32 seqno;
657
658 if (!ring->get_seqno)
659 return NULL;
660
661 if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
662 u32 acthd = I915_READ(ACTHD);
663
664 if (WARN_ON(ring->id != RCS))
665 return NULL;
666
667 obj = ring->scratch.obj;
668 if (acthd >= i915_gem_obj_ggtt_offset(obj) &&
669 acthd < i915_gem_obj_ggtt_offset(obj) + obj->base.size)
670 return i915_error_object_create(dev_priv, obj);
671 }
672
673 seqno = ring->get_seqno(ring, false);
674 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
675 list_for_each_entry(vma, &vm->active_list, mm_list) {
676 obj = vma->obj;
677 if (obj->ring != ring)
678 continue;
679
680 if (i915_seqno_passed(seqno, obj->last_read_seqno))
681 continue;
682
683 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
684 continue;
685
686 /* We need to copy these to an anonymous buffer as the simplest
687 * method to avoid being overwritten by userspace.
688 */
689 return i915_error_object_create(dev_priv, obj);
690 }
691 }
692
693 return NULL;
694 }
695
696 static void i915_record_ring_state(struct drm_device *dev,
697 struct drm_i915_error_state *error,
698 struct intel_ring_buffer *ring)
699 {
700 struct drm_i915_private *dev_priv = dev->dev_private;
701
702 if (INTEL_INFO(dev)->gen >= 6) {
703 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
704 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
705 error->semaphore_mboxes[ring->id][0]
706 = I915_READ(RING_SYNC_0(ring->mmio_base));
707 error->semaphore_mboxes[ring->id][1]
708 = I915_READ(RING_SYNC_1(ring->mmio_base));
709 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
710 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
711 }
712
713 if (HAS_VEBOX(dev)) {
714 error->semaphore_mboxes[ring->id][2] =
715 I915_READ(RING_SYNC_2(ring->mmio_base));
716 error->semaphore_seqno[ring->id][2] = ring->sync_seqno[2];
717 }
718
719 if (INTEL_INFO(dev)->gen >= 4) {
720 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
721 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
722 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
723 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
724 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
725 if (ring->id == RCS)
726 error->bbaddr = I915_READ64(BB_ADDR);
727 } else {
728 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
729 error->ipeir[ring->id] = I915_READ(IPEIR);
730 error->ipehr[ring->id] = I915_READ(IPEHR);
731 error->instdone[ring->id] = I915_READ(INSTDONE);
732 }
733
734 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
735 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
736 error->seqno[ring->id] = ring->get_seqno(ring, false);
737 error->acthd[ring->id] = intel_ring_get_active_head(ring);
738 error->head[ring->id] = I915_READ_HEAD(ring);
739 error->tail[ring->id] = I915_READ_TAIL(ring);
740 error->ctl[ring->id] = I915_READ_CTL(ring);
741
742 error->cpu_ring_head[ring->id] = ring->head;
743 error->cpu_ring_tail[ring->id] = ring->tail;
744
745 error->hangcheck_score[ring->id] = ring->hangcheck.score;
746 error->hangcheck_action[ring->id] = ring->hangcheck.action;
747 }
748
749
750 static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
751 struct drm_i915_error_state *error,
752 struct drm_i915_error_ring *ering)
753 {
754 struct drm_i915_private *dev_priv = ring->dev->dev_private;
755 struct drm_i915_gem_object *obj;
756
757 /* Currently render ring is the only HW context user */
758 if (ring->id != RCS || !error->ccid)
759 return;
760
761 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
762 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
763 ering->ctx = i915_error_object_create_sized(dev_priv,
764 obj, 1);
765 break;
766 }
767 }
768 }
769
770 static void i915_gem_record_rings(struct drm_device *dev,
771 struct drm_i915_error_state *error)
772 {
773 struct drm_i915_private *dev_priv = dev->dev_private;
774 struct intel_ring_buffer *ring;
775 struct drm_i915_gem_request *request;
776 int i, count;
777
778 for_each_ring(ring, dev_priv, i) {
779 i915_record_ring_state(dev, error, ring);
780
781 error->ring[i].batchbuffer =
782 i915_error_first_batchbuffer(dev_priv, ring);
783
784 error->ring[i].ringbuffer =
785 i915_error_object_create(dev_priv, ring->obj);
786
787
788 i915_gem_record_active_context(ring, error, &error->ring[i]);
789
790 count = 0;
791 list_for_each_entry(request, &ring->request_list, list)
792 count++;
793
794 error->ring[i].num_requests = count;
795 error->ring[i].requests =
796 kcalloc(count, sizeof(*error->ring[i].requests),
797 GFP_ATOMIC);
798 if (error->ring[i].requests == NULL) {
799 error->ring[i].num_requests = 0;
800 continue;
801 }
802
803 count = 0;
804 list_for_each_entry(request, &ring->request_list, list) {
805 struct drm_i915_error_request *erq;
806
807 erq = &error->ring[i].requests[count++];
808 erq->seqno = request->seqno;
809 erq->jiffies = request->emitted_jiffies;
810 erq->tail = request->tail;
811 }
812 }
813 }
814
815 /* FIXME: Since pin count/bound list is global, we duplicate what we capture per
816 * VM.
817 */
818 static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
819 struct drm_i915_error_state *error,
820 struct i915_address_space *vm,
821 const int ndx)
822 {
823 struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL;
824 struct drm_i915_gem_object *obj;
825 struct i915_vma *vma;
826 int i;
827
828 i = 0;
829 list_for_each_entry(vma, &vm->active_list, mm_list)
830 i++;
831 error->active_bo_count[ndx] = i;
832 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
833 if (obj->pin_count)
834 i++;
835 error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx];
836
837 if (i) {
838 active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC);
839 if (active_bo)
840 pinned_bo = active_bo + error->active_bo_count[ndx];
841 }
842
843 if (active_bo)
844 error->active_bo_count[ndx] =
845 capture_active_bo(active_bo,
846 error->active_bo_count[ndx],
847 &vm->active_list);
848
849 if (pinned_bo)
850 error->pinned_bo_count[ndx] =
851 capture_pinned_bo(pinned_bo,
852 error->pinned_bo_count[ndx],
853 &dev_priv->mm.bound_list);
854 error->active_bo[ndx] = active_bo;
855 error->pinned_bo[ndx] = pinned_bo;
856 }
857
858 static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
859 struct drm_i915_error_state *error)
860 {
861 struct i915_address_space *vm;
862 int cnt = 0, i = 0;
863
864 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
865 cnt++;
866
867 if (WARN(cnt > 1, "Multiple VMs not yet supported\n"))
868 cnt = 1;
869
870 vm = &dev_priv->gtt.base;
871
872 error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC);
873 error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC);
874 error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count),
875 GFP_ATOMIC);
876 error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count),
877 GFP_ATOMIC);
878
879 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
880 i915_gem_capture_vm(dev_priv, error, vm, i++);
881 }
882
883 /**
884 * i915_capture_error_state - capture an error record for later analysis
885 * @dev: drm device
886 *
887 * Should be called when an error is detected (either a hang or an error
888 * interrupt) to capture error state from the time of the error. Fills
889 * out a structure which becomes available in debugfs for user level tools
890 * to pick up.
891 */
892 void i915_capture_error_state(struct drm_device *dev)
893 {
894 struct drm_i915_private *dev_priv = dev->dev_private;
895 struct drm_i915_error_state *error;
896 unsigned long flags;
897 int pipe;
898
899 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
900 error = dev_priv->gpu_error.first_error;
901 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
902 if (error)
903 return;
904
905 /* Account for pipe specific data like PIPE*STAT */
906 error = kzalloc(sizeof(*error), GFP_ATOMIC);
907 if (!error) {
908 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
909 return;
910 }
911
912 DRM_INFO("capturing error event; look for more information in "
913 "/sys/class/drm/card%d/error\n", dev->primary->index);
914
915 kref_init(&error->ref);
916 error->eir = I915_READ(EIR);
917 error->pgtbl_er = I915_READ(PGTBL_ER);
918 if (HAS_HW_CONTEXTS(dev))
919 error->ccid = I915_READ(CCID);
920
921 if (HAS_PCH_SPLIT(dev))
922 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
923 else if (IS_VALLEYVIEW(dev))
924 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
925 else if (IS_GEN2(dev))
926 error->ier = I915_READ16(IER);
927 else
928 error->ier = I915_READ(IER);
929
930 if (INTEL_INFO(dev)->gen >= 6)
931 error->derrmr = I915_READ(DERRMR);
932
933 if (IS_VALLEYVIEW(dev))
934 error->forcewake = I915_READ(FORCEWAKE_VLV);
935 else if (INTEL_INFO(dev)->gen >= 7)
936 error->forcewake = I915_READ(FORCEWAKE_MT);
937 else if (INTEL_INFO(dev)->gen == 6)
938 error->forcewake = I915_READ(FORCEWAKE);
939
940 if (!HAS_PCH_SPLIT(dev))
941 for_each_pipe(pipe)
942 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
943
944 if (INTEL_INFO(dev)->gen >= 6) {
945 error->error = I915_READ(ERROR_GEN6);
946 error->done_reg = I915_READ(DONE_REG);
947 }
948
949 if (INTEL_INFO(dev)->gen == 7)
950 error->err_int = I915_READ(GEN7_ERR_INT);
951
952 i915_get_extra_instdone(dev, error->extra_instdone);
953
954 i915_gem_capture_buffers(dev_priv, error);
955 i915_gem_record_fences(dev, error);
956 i915_gem_record_rings(dev, error);
957
958 do_gettimeofday(&error->time);
959
960 error->overlay = intel_overlay_capture_error_state(dev);
961 error->display = intel_display_capture_error_state(dev);
962
963 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
964 if (dev_priv->gpu_error.first_error == NULL) {
965 dev_priv->gpu_error.first_error = error;
966 error = NULL;
967 }
968 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
969
970 if (error)
971 i915_error_state_free(&error->ref);
972 }
973
974 void i915_error_state_get(struct drm_device *dev,
975 struct i915_error_state_file_priv *error_priv)
976 {
977 struct drm_i915_private *dev_priv = dev->dev_private;
978 unsigned long flags;
979
980 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
981 error_priv->error = dev_priv->gpu_error.first_error;
982 if (error_priv->error)
983 kref_get(&error_priv->error->ref);
984 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
985
986 }
987
988 void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
989 {
990 if (error_priv->error)
991 kref_put(&error_priv->error->ref, i915_error_state_free);
992 }
993
994 void i915_destroy_error_state(struct drm_device *dev)
995 {
996 struct drm_i915_private *dev_priv = dev->dev_private;
997 struct drm_i915_error_state *error;
998 unsigned long flags;
999
1000 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1001 error = dev_priv->gpu_error.first_error;
1002 dev_priv->gpu_error.first_error = NULL;
1003 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1004
1005 if (error)
1006 kref_put(&error->ref, i915_error_state_free);
1007 }
1008
1009 const char *i915_cache_level_str(int type)
1010 {
1011 switch (type) {
1012 case I915_CACHE_NONE: return " uncached";
1013 case I915_CACHE_LLC: return " snooped or LLC";
1014 case I915_CACHE_L3_LLC: return " L3+LLC";
1015 default: return "";
1016 }
1017 }
1018
1019 /* NB: please notice the memset */
1020 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone)
1021 {
1022 struct drm_i915_private *dev_priv = dev->dev_private;
1023 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1024
1025 switch (INTEL_INFO(dev)->gen) {
1026 case 2:
1027 case 3:
1028 instdone[0] = I915_READ(INSTDONE);
1029 break;
1030 case 4:
1031 case 5:
1032 case 6:
1033 instdone[0] = I915_READ(INSTDONE_I965);
1034 instdone[1] = I915_READ(INSTDONE1);
1035 break;
1036 default:
1037 WARN_ONCE(1, "Unsupported platform\n");
1038 case 7:
1039 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1040 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1041 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1042 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1043 break;
1044 }
1045 }
Linux kernel - Deliverables
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