2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include <linux/firmware.h>
25 #include <linux/circ_buf.h>
27 #include "intel_guc.h"
30 * DOC: GuC-based command submission
33 * We use the term client to avoid confusion with contexts. A i915_guc_client is
34 * equivalent to GuC object guc_context_desc. This context descriptor is
35 * allocated from a pool of 1024 entries. Kernel driver will allocate doorbell
36 * and workqueue for it. Also the process descriptor (guc_process_desc), which
37 * is mapped to client space. So the client can write Work Item then ring the
40 * To simplify the implementation, we allocate one gem object that contains all
41 * pages for doorbell, process descriptor and workqueue.
43 * The Scratch registers:
44 * There are 16 MMIO-based registers start from 0xC180. The kernel driver writes
45 * a value to the action register (SOFT_SCRATCH_0) along with any data. It then
46 * triggers an interrupt on the GuC via another register write (0xC4C8).
47 * Firmware writes a success/fail code back to the action register after
48 * processes the request. The kernel driver polls waiting for this update and
50 * See host2guc_action()
53 * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
54 * mapped into process space.
57 * There are several types of work items that the host may place into a
58 * workqueue, each with its own requirements and limitations. Currently only
59 * WQ_TYPE_INORDER is needed to support legacy submission via GuC, which
60 * represents in-order queue. The kernel driver packs ring tail pointer and an
61 * ELSP context descriptor dword into Work Item.
62 * See guc_add_workqueue_item()
67 * Read GuC command/status register (SOFT_SCRATCH_0)
68 * Return true if it contains a response rather than a command
70 static inline bool host2guc_action_response(struct drm_i915_private
*dev_priv
,
73 u32 val
= I915_READ(SOFT_SCRATCH(0));
75 return GUC2HOST_IS_RESPONSE(val
);
78 static int host2guc_action(struct intel_guc
*guc
, u32
*data
, u32 len
)
80 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
85 if (WARN_ON(len
< 1 || len
> 15))
88 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
90 dev_priv
->guc
.action_count
+= 1;
91 dev_priv
->guc
.action_cmd
= data
[0];
93 for (i
= 0; i
< len
; i
++)
94 I915_WRITE(SOFT_SCRATCH(i
), data
[i
]);
96 POSTING_READ(SOFT_SCRATCH(i
- 1));
98 I915_WRITE(HOST2GUC_INTERRUPT
, HOST2GUC_TRIGGER
);
100 /* No HOST2GUC command should take longer than 10ms */
101 ret
= wait_for_atomic(host2guc_action_response(dev_priv
, &status
), 10);
102 if (status
!= GUC2HOST_STATUS_SUCCESS
) {
104 * Either the GuC explicitly returned an error (which
105 * we convert to -EIO here) or no response at all was
106 * received within the timeout limit (-ETIMEDOUT)
108 if (ret
!= -ETIMEDOUT
)
111 DRM_ERROR("GUC: host2guc action 0x%X failed. ret=%d "
112 "status=0x%08X response=0x%08X\n",
113 data
[0], ret
, status
,
114 I915_READ(SOFT_SCRATCH(15)));
116 dev_priv
->guc
.action_fail
+= 1;
117 dev_priv
->guc
.action_err
= ret
;
119 dev_priv
->guc
.action_status
= status
;
121 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
127 * Tell the GuC to allocate or deallocate a specific doorbell
130 static int host2guc_allocate_doorbell(struct intel_guc
*guc
,
131 struct i915_guc_client
*client
)
135 data
[0] = HOST2GUC_ACTION_ALLOCATE_DOORBELL
;
136 data
[1] = client
->ctx_index
;
138 return host2guc_action(guc
, data
, 2);
141 static int host2guc_release_doorbell(struct intel_guc
*guc
,
142 struct i915_guc_client
*client
)
146 data
[0] = HOST2GUC_ACTION_DEALLOCATE_DOORBELL
;
147 data
[1] = client
->ctx_index
;
149 return host2guc_action(guc
, data
, 2);
152 static int host2guc_sample_forcewake(struct intel_guc
*guc
,
153 struct i915_guc_client
*client
)
155 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
156 struct drm_device
*dev
= dev_priv
->dev
;
159 data
[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE
;
160 /* WaRsDisableCoarsePowerGating:skl,bxt */
161 if (!intel_enable_rc6() || NEEDS_WaRsDisableCoarsePowerGating(dev
))
164 /* bit 0 and 1 are for Render and Media domain separately */
165 data
[1] = GUC_FORCEWAKE_RENDER
| GUC_FORCEWAKE_MEDIA
;
167 return host2guc_action(guc
, data
, ARRAY_SIZE(data
));
171 * Initialise, update, or clear doorbell data shared with the GuC
173 * These functions modify shared data and so need access to the mapped
174 * client object which contains the page being used for the doorbell
177 static void guc_init_doorbell(struct intel_guc
*guc
,
178 struct i915_guc_client
*client
)
180 struct guc_doorbell_info
*doorbell
;
182 doorbell
= client
->client_base
+ client
->doorbell_offset
;
184 doorbell
->db_status
= GUC_DOORBELL_ENABLED
;
185 doorbell
->cookie
= 0;
188 static int guc_ring_doorbell(struct i915_guc_client
*gc
)
190 struct guc_process_desc
*desc
;
191 union guc_doorbell_qw db_cmp
, db_exc
, db_ret
;
192 union guc_doorbell_qw
*db
;
193 int attempt
= 2, ret
= -EAGAIN
;
195 desc
= gc
->client_base
+ gc
->proc_desc_offset
;
197 /* Update the tail so it is visible to GuC */
198 desc
->tail
= gc
->wq_tail
;
201 db_cmp
.db_status
= GUC_DOORBELL_ENABLED
;
202 db_cmp
.cookie
= gc
->cookie
;
204 /* cookie to be updated */
205 db_exc
.db_status
= GUC_DOORBELL_ENABLED
;
206 db_exc
.cookie
= gc
->cookie
+ 1;
207 if (db_exc
.cookie
== 0)
210 /* pointer of current doorbell cacheline */
211 db
= gc
->client_base
+ gc
->doorbell_offset
;
214 /* lets ring the doorbell */
215 db_ret
.value_qw
= atomic64_cmpxchg((atomic64_t
*)db
,
216 db_cmp
.value_qw
, db_exc
.value_qw
);
218 /* if the exchange was successfully executed */
219 if (db_ret
.value_qw
== db_cmp
.value_qw
) {
220 /* db was successfully rung */
221 gc
->cookie
= db_exc
.cookie
;
226 /* XXX: doorbell was lost and need to acquire it again */
227 if (db_ret
.db_status
== GUC_DOORBELL_DISABLED
)
230 DRM_ERROR("Cookie mismatch. Expected %d, returned %d\n",
231 db_cmp
.cookie
, db_ret
.cookie
);
233 /* update the cookie to newly read cookie from GuC */
234 db_cmp
.cookie
= db_ret
.cookie
;
235 db_exc
.cookie
= db_ret
.cookie
+ 1;
236 if (db_exc
.cookie
== 0)
243 static void guc_disable_doorbell(struct intel_guc
*guc
,
244 struct i915_guc_client
*client
)
246 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
247 struct guc_doorbell_info
*doorbell
;
248 i915_reg_t drbreg
= GEN8_DRBREGL(client
->doorbell_id
);
251 doorbell
= client
->client_base
+ client
->doorbell_offset
;
253 doorbell
->db_status
= GUC_DOORBELL_DISABLED
;
255 I915_WRITE(drbreg
, I915_READ(drbreg
) & ~GEN8_DRB_VALID
);
257 value
= I915_READ(drbreg
);
258 WARN_ON((value
& GEN8_DRB_VALID
) != 0);
260 I915_WRITE(GEN8_DRBREGU(client
->doorbell_id
), 0);
261 I915_WRITE(drbreg
, 0);
263 /* XXX: wait for any interrupts */
264 /* XXX: wait for workqueue to drain */
268 * Select, assign and relase doorbell cachelines
270 * These functions track which doorbell cachelines are in use.
271 * The data they manipulate is protected by the host2guc lock.
274 static uint32_t select_doorbell_cacheline(struct intel_guc
*guc
)
276 const uint32_t cacheline_size
= cache_line_size();
279 /* Doorbell uses a single cache line within a page */
280 offset
= offset_in_page(guc
->db_cacheline
);
282 /* Moving to next cache line to reduce contention */
283 guc
->db_cacheline
+= cacheline_size
;
285 DRM_DEBUG_DRIVER("selected doorbell cacheline 0x%x, next 0x%x, linesize %u\n",
286 offset
, guc
->db_cacheline
, cacheline_size
);
291 static uint16_t assign_doorbell(struct intel_guc
*guc
, uint32_t priority
)
294 * The bitmap is split into two halves; the first half is used for
295 * normal priority contexts, the second half for high-priority ones.
296 * Note that logically higher priorities are numerically less than
297 * normal ones, so the test below means "is it high-priority?"
299 const bool hi_pri
= (priority
<= GUC_CTX_PRIORITY_HIGH
);
300 const uint16_t half
= GUC_MAX_DOORBELLS
/ 2;
301 const uint16_t start
= hi_pri
? half
: 0;
302 const uint16_t end
= start
+ half
;
305 id
= find_next_zero_bit(guc
->doorbell_bitmap
, end
, start
);
307 id
= GUC_INVALID_DOORBELL_ID
;
309 bitmap_set(guc
->doorbell_bitmap
, id
, 1);
311 DRM_DEBUG_DRIVER("assigned %s priority doorbell id 0x%x\n",
312 hi_pri
? "high" : "normal", id
);
317 static void release_doorbell(struct intel_guc
*guc
, uint16_t id
)
319 bitmap_clear(guc
->doorbell_bitmap
, id
, 1);
323 * Initialise the process descriptor shared with the GuC firmware.
325 static void guc_init_proc_desc(struct intel_guc
*guc
,
326 struct i915_guc_client
*client
)
328 struct guc_process_desc
*desc
;
330 desc
= client
->client_base
+ client
->proc_desc_offset
;
332 memset(desc
, 0, sizeof(*desc
));
335 * XXX: pDoorbell and WQVBaseAddress are pointers in process address
336 * space for ring3 clients (set them as in mmap_ioctl) or kernel
337 * space for kernel clients (map on demand instead? May make debug
338 * easier to have it mapped).
340 desc
->wq_base_addr
= 0;
341 desc
->db_base_addr
= 0;
343 desc
->context_id
= client
->ctx_index
;
344 desc
->wq_size_bytes
= client
->wq_size
;
345 desc
->wq_status
= WQ_STATUS_ACTIVE
;
346 desc
->priority
= client
->priority
;
350 * Initialise/clear the context descriptor shared with the GuC firmware.
352 * This descriptor tells the GuC where (in GGTT space) to find the important
353 * data structures relating to this client (doorbell, process descriptor,
357 static void guc_init_ctx_desc(struct intel_guc
*guc
,
358 struct i915_guc_client
*client
)
360 struct drm_i915_gem_object
*client_obj
= client
->client_obj
;
361 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
362 struct intel_engine_cs
*engine
;
363 struct intel_context
*ctx
= client
->owner
;
364 struct guc_context_desc desc
;
366 enum intel_engine_id id
;
369 memset(&desc
, 0, sizeof(desc
));
371 desc
.attribute
= GUC_CTX_DESC_ATTR_ACTIVE
| GUC_CTX_DESC_ATTR_KERNEL
;
372 desc
.context_id
= client
->ctx_index
;
373 desc
.priority
= client
->priority
;
374 desc
.db_id
= client
->doorbell_id
;
376 for_each_engine_id(engine
, dev_priv
, id
) {
377 struct guc_execlist_context
*lrc
= &desc
.lrc
[engine
->guc_id
];
378 struct drm_i915_gem_object
*obj
;
381 /* TODO: We have a design issue to be solved here. Only when we
382 * receive the first batch, we know which engine is used by the
383 * user. But here GuC expects the lrc and ring to be pinned. It
384 * is not an issue for default context, which is the only one
385 * for now who owns a GuC client. But for future owner of GuC
386 * client, need to make sure lrc is pinned prior to enter here.
388 obj
= ctx
->engine
[id
].state
;
390 break; /* XXX: continue? */
392 ctx_desc
= intel_lr_context_descriptor(ctx
, engine
);
393 lrc
->context_desc
= (u32
)ctx_desc
;
395 /* The state page is after PPHWSP */
396 gfx_addr
= i915_gem_obj_ggtt_offset(obj
);
397 lrc
->ring_lcra
= gfx_addr
+ LRC_STATE_PN
* PAGE_SIZE
;
398 lrc
->context_id
= (client
->ctx_index
<< GUC_ELC_CTXID_OFFSET
) |
399 (engine
->guc_id
<< GUC_ELC_ENGINE_OFFSET
);
401 obj
= ctx
->engine
[id
].ringbuf
->obj
;
402 gfx_addr
= i915_gem_obj_ggtt_offset(obj
);
404 lrc
->ring_begin
= gfx_addr
;
405 lrc
->ring_end
= gfx_addr
+ obj
->base
.size
- 1;
406 lrc
->ring_next_free_location
= gfx_addr
;
407 lrc
->ring_current_tail_pointer_value
= 0;
409 desc
.engines_used
|= (1 << engine
->guc_id
);
412 WARN_ON(desc
.engines_used
== 0);
415 * The doorbell, process descriptor, and workqueue are all parts
416 * of the client object, which the GuC will reference via the GGTT
418 gfx_addr
= i915_gem_obj_ggtt_offset(client_obj
);
419 desc
.db_trigger_phy
= sg_dma_address(client_obj
->pages
->sgl
) +
420 client
->doorbell_offset
;
421 desc
.db_trigger_cpu
= (uintptr_t)client
->client_base
+
422 client
->doorbell_offset
;
423 desc
.db_trigger_uk
= gfx_addr
+ client
->doorbell_offset
;
424 desc
.process_desc
= gfx_addr
+ client
->proc_desc_offset
;
425 desc
.wq_addr
= gfx_addr
+ client
->wq_offset
;
426 desc
.wq_size
= client
->wq_size
;
429 * XXX: Take LRCs from an existing intel_context if this is not an
430 * IsKMDCreatedContext client
432 desc
.desc_private
= (uintptr_t)client
;
434 /* Pool context is pinned already */
435 sg
= guc
->ctx_pool_obj
->pages
;
436 sg_pcopy_from_buffer(sg
->sgl
, sg
->nents
, &desc
, sizeof(desc
),
437 sizeof(desc
) * client
->ctx_index
);
440 static void guc_fini_ctx_desc(struct intel_guc
*guc
,
441 struct i915_guc_client
*client
)
443 struct guc_context_desc desc
;
446 memset(&desc
, 0, sizeof(desc
));
448 sg
= guc
->ctx_pool_obj
->pages
;
449 sg_pcopy_from_buffer(sg
->sgl
, sg
->nents
, &desc
, sizeof(desc
),
450 sizeof(desc
) * client
->ctx_index
);
453 int i915_guc_wq_check_space(struct i915_guc_client
*gc
)
455 struct guc_process_desc
*desc
;
456 u32 size
= sizeof(struct guc_wq_item
);
457 int ret
= -ETIMEDOUT
, timeout_counter
= 200;
462 desc
= gc
->client_base
+ gc
->proc_desc_offset
;
464 while (timeout_counter
-- > 0) {
465 if (CIRC_SPACE(gc
->wq_tail
, desc
->head
, gc
->wq_size
) >= size
) {
471 usleep_range(1000, 2000);
477 static int guc_add_workqueue_item(struct i915_guc_client
*gc
,
478 struct drm_i915_gem_request
*rq
)
480 struct guc_process_desc
*desc
;
481 struct guc_wq_item
*wqi
;
483 u32 tail
, wq_len
, wq_off
, space
;
485 desc
= gc
->client_base
+ gc
->proc_desc_offset
;
486 space
= CIRC_SPACE(gc
->wq_tail
, desc
->head
, gc
->wq_size
);
487 if (WARN_ON(space
< sizeof(struct guc_wq_item
)))
488 return -ENOSPC
; /* shouldn't happen */
490 /* postincrement WQ tail for next time */
491 wq_off
= gc
->wq_tail
;
492 gc
->wq_tail
+= sizeof(struct guc_wq_item
);
493 gc
->wq_tail
&= gc
->wq_size
- 1;
495 /* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we
496 * should not have the case where structure wqi is across page, neither
497 * wrapped to the beginning. This simplifies the implementation below.
499 * XXX: if not the case, we need save data to a temp wqi and copy it to
500 * workqueue buffer dw by dw.
502 WARN_ON(sizeof(struct guc_wq_item
) != 16);
505 /* wq starts from the page after doorbell / process_desc */
506 base
= kmap_atomic(i915_gem_object_get_page(gc
->client_obj
,
507 (wq_off
+ GUC_DB_SIZE
) >> PAGE_SHIFT
));
508 wq_off
&= PAGE_SIZE
- 1;
509 wqi
= (struct guc_wq_item
*)((char *)base
+ wq_off
);
511 /* len does not include the header */
512 wq_len
= sizeof(struct guc_wq_item
) / sizeof(u32
) - 1;
513 wqi
->header
= WQ_TYPE_INORDER
|
514 (wq_len
<< WQ_LEN_SHIFT
) |
515 (rq
->engine
->guc_id
<< WQ_TARGET_SHIFT
) |
518 /* The GuC wants only the low-order word of the context descriptor */
519 wqi
->context_desc
= (u32
)intel_lr_context_descriptor(rq
->ctx
,
522 /* The GuC firmware wants the tail index in QWords, not bytes */
523 tail
= rq
->ringbuf
->tail
>> 3;
524 wqi
->ring_tail
= tail
<< WQ_RING_TAIL_SHIFT
;
525 wqi
->fence_id
= 0; /*XXX: what fence to be here */
533 * i915_guc_submit() - Submit commands through GuC
534 * @client: the guc client where commands will go through
535 * @rq: request associated with the commands
537 * Return: 0 if succeed
539 int i915_guc_submit(struct i915_guc_client
*client
,
540 struct drm_i915_gem_request
*rq
)
542 struct intel_guc
*guc
= client
->guc
;
543 unsigned int engine_id
= rq
->engine
->guc_id
;
546 q_ret
= guc_add_workqueue_item(client
, rq
);
548 b_ret
= guc_ring_doorbell(client
);
550 client
->submissions
[engine_id
] += 1;
553 client
->retcode
= q_ret
;
556 client
->retcode
= q_ret
= b_ret
;
560 guc
->submissions
[engine_id
] += 1;
561 guc
->last_seqno
[engine_id
] = rq
->seqno
;
567 * Everything below here is concerned with setup & teardown, and is
568 * therefore not part of the somewhat time-critical batch-submission
569 * path of i915_guc_submit() above.
573 * gem_allocate_guc_obj() - Allocate gem object for GuC usage
575 * @size: size of object
577 * This is a wrapper to create a gem obj. In order to use it inside GuC, the
578 * object needs to be pinned lifetime. Also we must pin it to gtt space other
579 * than [0, GUC_WOPCM_TOP) because this range is reserved inside GuC.
581 * Return: A drm_i915_gem_object if successful, otherwise NULL.
583 static struct drm_i915_gem_object
*gem_allocate_guc_obj(struct drm_device
*dev
,
586 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
587 struct drm_i915_gem_object
*obj
;
589 obj
= i915_gem_object_create(dev
, size
);
593 if (i915_gem_object_get_pages(obj
)) {
594 drm_gem_object_unreference(&obj
->base
);
598 if (i915_gem_obj_ggtt_pin(obj
, PAGE_SIZE
,
599 PIN_OFFSET_BIAS
| GUC_WOPCM_TOP
)) {
600 drm_gem_object_unreference(&obj
->base
);
604 /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
605 I915_WRITE(GEN8_GTCR
, GEN8_GTCR_INVALIDATE
);
611 * gem_release_guc_obj() - Release gem object allocated for GuC usage
612 * @obj: gem obj to be released
614 static void gem_release_guc_obj(struct drm_i915_gem_object
*obj
)
619 if (i915_gem_obj_is_pinned(obj
))
620 i915_gem_object_ggtt_unpin(obj
);
622 drm_gem_object_unreference(&obj
->base
);
625 static void guc_client_free(struct drm_device
*dev
,
626 struct i915_guc_client
*client
)
628 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
629 struct intel_guc
*guc
= &dev_priv
->guc
;
635 * XXX: wait for any outstanding submissions before freeing memory.
636 * Be sure to drop any locks
639 if (client
->client_base
) {
641 * If we got as far as setting up a doorbell, make sure
642 * we shut it down before unmapping & deallocating the
643 * memory. So first disable the doorbell, then tell the
644 * GuC that we've finished with it, finally deallocate
647 if (client
->doorbell_id
!= GUC_INVALID_DOORBELL_ID
) {
648 guc_disable_doorbell(guc
, client
);
649 host2guc_release_doorbell(guc
, client
);
650 release_doorbell(guc
, client
->doorbell_id
);
653 kunmap(kmap_to_page(client
->client_base
));
656 gem_release_guc_obj(client
->client_obj
);
658 if (client
->ctx_index
!= GUC_INVALID_CTX_ID
) {
659 guc_fini_ctx_desc(guc
, client
);
660 ida_simple_remove(&guc
->ctx_ids
, client
->ctx_index
);
667 * guc_client_alloc() - Allocate an i915_guc_client
669 * @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW
670 * The kernel client to replace ExecList submission is created with
671 * NORMAL priority. Priority of a client for scheduler can be HIGH,
672 * while a preemption context can use CRITICAL.
673 * @ctx: the context that owns the client (we use the default render
676 * Return: An i915_guc_client object if success, else NULL.
678 static struct i915_guc_client
*guc_client_alloc(struct drm_device
*dev
,
680 struct intel_context
*ctx
)
682 struct i915_guc_client
*client
;
683 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
684 struct intel_guc
*guc
= &dev_priv
->guc
;
685 struct drm_i915_gem_object
*obj
;
687 client
= kzalloc(sizeof(*client
), GFP_KERNEL
);
691 client
->doorbell_id
= GUC_INVALID_DOORBELL_ID
;
692 client
->priority
= priority
;
696 client
->ctx_index
= (uint32_t)ida_simple_get(&guc
->ctx_ids
, 0,
697 GUC_MAX_GPU_CONTEXTS
, GFP_KERNEL
);
698 if (client
->ctx_index
>= GUC_MAX_GPU_CONTEXTS
) {
699 client
->ctx_index
= GUC_INVALID_CTX_ID
;
703 /* The first page is doorbell/proc_desc. Two followed pages are wq. */
704 obj
= gem_allocate_guc_obj(dev
, GUC_DB_SIZE
+ GUC_WQ_SIZE
);
708 /* We'll keep just the first (doorbell/proc) page permanently kmap'd. */
709 client
->client_obj
= obj
;
710 client
->client_base
= kmap(i915_gem_object_get_page(obj
, 0));
711 client
->wq_offset
= GUC_DB_SIZE
;
712 client
->wq_size
= GUC_WQ_SIZE
;
714 client
->doorbell_offset
= select_doorbell_cacheline(guc
);
717 * Since the doorbell only requires a single cacheline, we can save
718 * space by putting the application process descriptor in the same
719 * page. Use the half of the page that doesn't include the doorbell.
721 if (client
->doorbell_offset
>= (GUC_DB_SIZE
/ 2))
722 client
->proc_desc_offset
= 0;
724 client
->proc_desc_offset
= (GUC_DB_SIZE
/ 2);
726 client
->doorbell_id
= assign_doorbell(guc
, client
->priority
);
727 if (client
->doorbell_id
== GUC_INVALID_DOORBELL_ID
)
728 /* XXX: evict a doorbell instead */
731 guc_init_proc_desc(guc
, client
);
732 guc_init_ctx_desc(guc
, client
);
733 guc_init_doorbell(guc
, client
);
735 /* XXX: Any cache flushes needed? General domain mgmt calls? */
737 if (host2guc_allocate_doorbell(guc
, client
))
740 DRM_DEBUG_DRIVER("new priority %u client %p: ctx_index %u db_id %u\n",
741 priority
, client
, client
->ctx_index
, client
->doorbell_id
);
746 DRM_ERROR("FAILED to create priority %u GuC client!\n", priority
);
748 guc_client_free(dev
, client
);
752 static void guc_create_log(struct intel_guc
*guc
)
754 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
755 struct drm_i915_gem_object
*obj
;
756 unsigned long offset
;
757 uint32_t size
, flags
;
759 if (i915
.guc_log_level
< GUC_LOG_VERBOSITY_MIN
)
762 if (i915
.guc_log_level
> GUC_LOG_VERBOSITY_MAX
)
763 i915
.guc_log_level
= GUC_LOG_VERBOSITY_MAX
;
765 /* The first page is to save log buffer state. Allocate one
766 * extra page for others in case for overlap */
767 size
= (1 + GUC_LOG_DPC_PAGES
+ 1 +
768 GUC_LOG_ISR_PAGES
+ 1 +
769 GUC_LOG_CRASH_PAGES
+ 1) << PAGE_SHIFT
;
773 obj
= gem_allocate_guc_obj(dev_priv
->dev
, size
);
775 /* logging will be off */
776 i915
.guc_log_level
= -1;
783 /* each allocated unit is a page */
784 flags
= GUC_LOG_VALID
| GUC_LOG_NOTIFY_ON_HALF_FULL
|
785 (GUC_LOG_DPC_PAGES
<< GUC_LOG_DPC_SHIFT
) |
786 (GUC_LOG_ISR_PAGES
<< GUC_LOG_ISR_SHIFT
) |
787 (GUC_LOG_CRASH_PAGES
<< GUC_LOG_CRASH_SHIFT
);
789 offset
= i915_gem_obj_ggtt_offset(obj
) >> PAGE_SHIFT
; /* in pages */
790 guc
->log_flags
= (offset
<< GUC_LOG_BUF_ADDR_SHIFT
) | flags
;
793 static void init_guc_policies(struct guc_policies
*policies
)
795 struct guc_policy
*policy
;
798 policies
->dpc_promote_time
= 500000;
799 policies
->max_num_work_items
= POLICY_MAX_NUM_WI
;
801 for (p
= 0; p
< GUC_CTX_PRIORITY_NUM
; p
++) {
802 for (i
= GUC_RENDER_ENGINE
; i
< GUC_MAX_ENGINES_NUM
; i
++) {
803 policy
= &policies
->policy
[p
][i
];
805 policy
->execution_quantum
= 1000000;
806 policy
->preemption_time
= 500000;
807 policy
->fault_time
= 250000;
808 policy
->policy_flags
= 0;
812 policies
->is_valid
= 1;
815 static void guc_create_ads(struct intel_guc
*guc
)
817 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
818 struct drm_i915_gem_object
*obj
;
820 struct guc_policies
*policies
;
821 struct guc_mmio_reg_state
*reg_state
;
822 struct intel_engine_cs
*engine
;
826 /* The ads obj includes the struct itself and buffers passed to GuC */
827 size
= sizeof(struct guc_ads
) + sizeof(struct guc_policies
) +
828 sizeof(struct guc_mmio_reg_state
) +
829 GUC_S3_SAVE_SPACE_PAGES
* PAGE_SIZE
;
833 obj
= gem_allocate_guc_obj(dev_priv
->dev
, PAGE_ALIGN(size
));
840 page
= i915_gem_object_get_page(obj
, 0);
844 * The GuC requires a "Golden Context" when it reinitialises
845 * engines after a reset. Here we use the Render ring default
846 * context, which must already exist and be pinned in the GGTT,
847 * so its address won't change after we've told the GuC where
850 engine
= &dev_priv
->engine
[RCS
];
851 ads
->golden_context_lrca
= engine
->status_page
.gfx_addr
;
853 for_each_engine(engine
, dev_priv
)
854 ads
->eng_state_size
[engine
->guc_id
] = intel_lr_context_size(engine
);
856 /* GuC scheduling policies */
857 policies
= (void *)ads
+ sizeof(struct guc_ads
);
858 init_guc_policies(policies
);
860 ads
->scheduler_policies
= i915_gem_obj_ggtt_offset(obj
) +
861 sizeof(struct guc_ads
);
864 reg_state
= (void *)policies
+ sizeof(struct guc_policies
);
866 for_each_engine(engine
, dev_priv
) {
867 reg_state
->mmio_white_list
[engine
->guc_id
].mmio_start
=
868 engine
->mmio_base
+ GUC_MMIO_WHITE_LIST_START
;
870 /* Nothing to be saved or restored for now. */
871 reg_state
->mmio_white_list
[engine
->guc_id
].count
= 0;
874 ads
->reg_state_addr
= ads
->scheduler_policies
+
875 sizeof(struct guc_policies
);
877 ads
->reg_state_buffer
= ads
->reg_state_addr
+
878 sizeof(struct guc_mmio_reg_state
);
884 * Set up the memory resources to be shared with the GuC. At this point,
885 * we require just one object that can be mapped through the GGTT.
887 int i915_guc_submission_init(struct drm_device
*dev
)
889 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
890 const size_t ctxsize
= sizeof(struct guc_context_desc
);
891 const size_t poolsize
= GUC_MAX_GPU_CONTEXTS
* ctxsize
;
892 const size_t gemsize
= round_up(poolsize
, PAGE_SIZE
);
893 struct intel_guc
*guc
= &dev_priv
->guc
;
895 if (!i915
.enable_guc_submission
)
896 return 0; /* not enabled */
898 if (guc
->ctx_pool_obj
)
899 return 0; /* already allocated */
901 guc
->ctx_pool_obj
= gem_allocate_guc_obj(dev_priv
->dev
, gemsize
);
902 if (!guc
->ctx_pool_obj
)
905 ida_init(&guc
->ctx_ids
);
914 int i915_guc_submission_enable(struct drm_device
*dev
)
916 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
917 struct intel_guc
*guc
= &dev_priv
->guc
;
918 struct intel_context
*ctx
= dev_priv
->kernel_context
;
919 struct i915_guc_client
*client
;
921 /* client for execbuf submission */
922 client
= guc_client_alloc(dev
, GUC_CTX_PRIORITY_KMD_NORMAL
, ctx
);
924 DRM_ERROR("Failed to create execbuf guc_client\n");
928 guc
->execbuf_client
= client
;
930 host2guc_sample_forcewake(guc
, client
);
935 void i915_guc_submission_disable(struct drm_device
*dev
)
937 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
938 struct intel_guc
*guc
= &dev_priv
->guc
;
940 guc_client_free(dev
, guc
->execbuf_client
);
941 guc
->execbuf_client
= NULL
;
944 void i915_guc_submission_fini(struct drm_device
*dev
)
946 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
947 struct intel_guc
*guc
= &dev_priv
->guc
;
949 gem_release_guc_obj(dev_priv
->guc
.ads_obj
);
952 gem_release_guc_obj(dev_priv
->guc
.log_obj
);
955 if (guc
->ctx_pool_obj
)
956 ida_destroy(&guc
->ctx_ids
);
957 gem_release_guc_obj(guc
->ctx_pool_obj
);
958 guc
->ctx_pool_obj
= NULL
;
962 * intel_guc_suspend() - notify GuC entering suspend state
965 int intel_guc_suspend(struct drm_device
*dev
)
967 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
968 struct intel_guc
*guc
= &dev_priv
->guc
;
969 struct intel_context
*ctx
;
972 if (!i915
.enable_guc_submission
)
975 ctx
= dev_priv
->kernel_context
;
977 data
[0] = HOST2GUC_ACTION_ENTER_S_STATE
;
978 /* any value greater than GUC_POWER_D0 */
979 data
[1] = GUC_POWER_D1
;
980 /* first page is shared data with GuC */
981 data
[2] = i915_gem_obj_ggtt_offset(ctx
->engine
[RCS
].state
);
983 return host2guc_action(guc
, data
, ARRAY_SIZE(data
));
988 * intel_guc_resume() - notify GuC resuming from suspend state
991 int intel_guc_resume(struct drm_device
*dev
)
993 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
994 struct intel_guc
*guc
= &dev_priv
->guc
;
995 struct intel_context
*ctx
;
998 if (!i915
.enable_guc_submission
)
1001 ctx
= dev_priv
->kernel_context
;
1003 data
[0] = HOST2GUC_ACTION_EXIT_S_STATE
;
1004 data
[1] = GUC_POWER_D0
;
1005 /* first page is shared data with GuC */
1006 data
[2] = i915_gem_obj_ggtt_offset(ctx
->engine
[RCS
].state
);
1008 return host2guc_action(guc
, data
, ARRAY_SIZE(data
));