2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include <linux/firmware.h>
25 #include <linux/circ_buf.h>
27 #include "intel_guc.h"
30 * DOC: GuC-based command submission
33 * We use the term client to avoid confusion with contexts. A i915_guc_client is
34 * equivalent to GuC object guc_context_desc. This context descriptor is
35 * allocated from a pool of 1024 entries. Kernel driver will allocate doorbell
36 * and workqueue for it. Also the process descriptor (guc_process_desc), which
37 * is mapped to client space. So the client can write Work Item then ring the
40 * To simplify the implementation, we allocate one gem object that contains all
41 * pages for doorbell, process descriptor and workqueue.
43 * The Scratch registers:
44 * There are 16 MMIO-based registers start from 0xC180. The kernel driver writes
45 * a value to the action register (SOFT_SCRATCH_0) along with any data. It then
46 * triggers an interrupt on the GuC via another register write (0xC4C8).
47 * Firmware writes a success/fail code back to the action register after
48 * processes the request. The kernel driver polls waiting for this update and
50 * See host2guc_action()
53 * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
54 * mapped into process space.
57 * There are several types of work items that the host may place into a
58 * workqueue, each with its own requirements and limitations. Currently only
59 * WQ_TYPE_INORDER is needed to support legacy submission via GuC, which
60 * represents in-order queue. The kernel driver packs ring tail pointer and an
61 * ELSP context descriptor dword into Work Item.
62 * See guc_add_workqueue_item()
67 * Read GuC command/status register (SOFT_SCRATCH_0)
68 * Return true if it contains a response rather than a command
70 static inline bool host2guc_action_response(struct drm_i915_private
*dev_priv
,
73 u32 val
= I915_READ(SOFT_SCRATCH(0));
75 return GUC2HOST_IS_RESPONSE(val
);
78 static int host2guc_action(struct intel_guc
*guc
, u32
*data
, u32 len
)
80 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
85 if (WARN_ON(len
< 1 || len
> 15))
88 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
90 dev_priv
->guc
.action_count
+= 1;
91 dev_priv
->guc
.action_cmd
= data
[0];
93 for (i
= 0; i
< len
; i
++)
94 I915_WRITE(SOFT_SCRATCH(i
), data
[i
]);
96 POSTING_READ(SOFT_SCRATCH(i
- 1));
98 I915_WRITE(HOST2GUC_INTERRUPT
, HOST2GUC_TRIGGER
);
101 * Fast commands should complete in less than 10us, so sample quickly
102 * up to that length of time, then switch to a slower sleep-wait loop.
103 * No HOST2GUC command should ever take longer than 10ms.
105 ret
= wait_for_us(host2guc_action_response(dev_priv
, &status
), 10);
107 ret
= wait_for(host2guc_action_response(dev_priv
, &status
), 10);
108 if (status
!= GUC2HOST_STATUS_SUCCESS
) {
110 * Either the GuC explicitly returned an error (which
111 * we convert to -EIO here) or no response at all was
112 * received within the timeout limit (-ETIMEDOUT)
114 if (ret
!= -ETIMEDOUT
)
117 DRM_ERROR("GUC: host2guc action 0x%X failed. ret=%d "
118 "status=0x%08X response=0x%08X\n",
119 data
[0], ret
, status
,
120 I915_READ(SOFT_SCRATCH(15)));
122 dev_priv
->guc
.action_fail
+= 1;
123 dev_priv
->guc
.action_err
= ret
;
125 dev_priv
->guc
.action_status
= status
;
127 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
133 * Tell the GuC to allocate or deallocate a specific doorbell
136 static int host2guc_allocate_doorbell(struct intel_guc
*guc
,
137 struct i915_guc_client
*client
)
141 data
[0] = HOST2GUC_ACTION_ALLOCATE_DOORBELL
;
142 data
[1] = client
->ctx_index
;
144 return host2guc_action(guc
, data
, 2);
147 static int host2guc_release_doorbell(struct intel_guc
*guc
,
148 struct i915_guc_client
*client
)
152 data
[0] = HOST2GUC_ACTION_DEALLOCATE_DOORBELL
;
153 data
[1] = client
->ctx_index
;
155 return host2guc_action(guc
, data
, 2);
158 static int host2guc_sample_forcewake(struct intel_guc
*guc
,
159 struct i915_guc_client
*client
)
161 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
164 data
[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE
;
165 /* WaRsDisableCoarsePowerGating:skl,bxt */
166 if (!intel_enable_rc6() || NEEDS_WaRsDisableCoarsePowerGating(dev_priv
))
169 /* bit 0 and 1 are for Render and Media domain separately */
170 data
[1] = GUC_FORCEWAKE_RENDER
| GUC_FORCEWAKE_MEDIA
;
172 return host2guc_action(guc
, data
, ARRAY_SIZE(data
));
176 * Initialise, update, or clear doorbell data shared with the GuC
178 * These functions modify shared data and so need access to the mapped
179 * client object which contains the page being used for the doorbell
182 static int guc_update_doorbell_id(struct intel_guc
*guc
,
183 struct i915_guc_client
*client
,
186 struct sg_table
*sg
= guc
->ctx_pool_vma
->pages
;
187 void *doorbell_bitmap
= guc
->doorbell_bitmap
;
188 struct guc_doorbell_info
*doorbell
;
189 struct guc_context_desc desc
;
192 doorbell
= client
->client_base
+ client
->doorbell_offset
;
194 if (client
->doorbell_id
!= GUC_INVALID_DOORBELL_ID
&&
195 test_bit(client
->doorbell_id
, doorbell_bitmap
)) {
196 /* Deactivate the old doorbell */
197 doorbell
->db_status
= GUC_DOORBELL_DISABLED
;
198 (void)host2guc_release_doorbell(guc
, client
);
199 __clear_bit(client
->doorbell_id
, doorbell_bitmap
);
202 /* Update the GuC's idea of the doorbell ID */
203 len
= sg_pcopy_to_buffer(sg
->sgl
, sg
->nents
, &desc
, sizeof(desc
),
204 sizeof(desc
) * client
->ctx_index
);
205 if (len
!= sizeof(desc
))
208 len
= sg_pcopy_from_buffer(sg
->sgl
, sg
->nents
, &desc
, sizeof(desc
),
209 sizeof(desc
) * client
->ctx_index
);
210 if (len
!= sizeof(desc
))
213 client
->doorbell_id
= new_id
;
214 if (new_id
== GUC_INVALID_DOORBELL_ID
)
217 /* Activate the new doorbell */
218 __set_bit(new_id
, doorbell_bitmap
);
219 doorbell
->cookie
= 0;
220 doorbell
->db_status
= GUC_DOORBELL_ENABLED
;
221 return host2guc_allocate_doorbell(guc
, client
);
224 static int guc_init_doorbell(struct intel_guc
*guc
,
225 struct i915_guc_client
*client
,
228 return guc_update_doorbell_id(guc
, client
, db_id
);
231 static void guc_disable_doorbell(struct intel_guc
*guc
,
232 struct i915_guc_client
*client
)
234 (void)guc_update_doorbell_id(guc
, client
, GUC_INVALID_DOORBELL_ID
);
236 /* XXX: wait for any interrupts */
237 /* XXX: wait for workqueue to drain */
241 select_doorbell_register(struct intel_guc
*guc
, uint32_t priority
)
244 * The bitmap tracks which doorbell registers are currently in use.
245 * It is split into two halves; the first half is used for normal
246 * priority contexts, the second half for high-priority ones.
247 * Note that logically higher priorities are numerically less than
248 * normal ones, so the test below means "is it high-priority?"
250 const bool hi_pri
= (priority
<= GUC_CTX_PRIORITY_HIGH
);
251 const uint16_t half
= GUC_MAX_DOORBELLS
/ 2;
252 const uint16_t start
= hi_pri
? half
: 0;
253 const uint16_t end
= start
+ half
;
256 id
= find_next_zero_bit(guc
->doorbell_bitmap
, end
, start
);
258 id
= GUC_INVALID_DOORBELL_ID
;
260 DRM_DEBUG_DRIVER("assigned %s priority doorbell id 0x%x\n",
261 hi_pri
? "high" : "normal", id
);
267 * Select, assign and relase doorbell cachelines
269 * These functions track which doorbell cachelines are in use.
270 * The data they manipulate is protected by the host2guc lock.
273 static uint32_t select_doorbell_cacheline(struct intel_guc
*guc
)
275 const uint32_t cacheline_size
= cache_line_size();
278 /* Doorbell uses a single cache line within a page */
279 offset
= offset_in_page(guc
->db_cacheline
);
281 /* Moving to next cache line to reduce contention */
282 guc
->db_cacheline
+= cacheline_size
;
284 DRM_DEBUG_DRIVER("selected doorbell cacheline 0x%x, next 0x%x, linesize %u\n",
285 offset
, guc
->db_cacheline
, cacheline_size
);
291 * Initialise the process descriptor shared with the GuC firmware.
293 static void guc_init_proc_desc(struct intel_guc
*guc
,
294 struct i915_guc_client
*client
)
296 struct guc_process_desc
*desc
;
298 desc
= client
->client_base
+ client
->proc_desc_offset
;
300 memset(desc
, 0, sizeof(*desc
));
303 * XXX: pDoorbell and WQVBaseAddress are pointers in process address
304 * space for ring3 clients (set them as in mmap_ioctl) or kernel
305 * space for kernel clients (map on demand instead? May make debug
306 * easier to have it mapped).
308 desc
->wq_base_addr
= 0;
309 desc
->db_base_addr
= 0;
311 desc
->context_id
= client
->ctx_index
;
312 desc
->wq_size_bytes
= client
->wq_size
;
313 desc
->wq_status
= WQ_STATUS_ACTIVE
;
314 desc
->priority
= client
->priority
;
318 * Initialise/clear the context descriptor shared with the GuC firmware.
320 * This descriptor tells the GuC where (in GGTT space) to find the important
321 * data structures relating to this client (doorbell, process descriptor,
325 static void guc_init_ctx_desc(struct intel_guc
*guc
,
326 struct i915_guc_client
*client
)
328 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
329 struct intel_engine_cs
*engine
;
330 struct i915_gem_context
*ctx
= client
->owner
;
331 struct guc_context_desc desc
;
335 memset(&desc
, 0, sizeof(desc
));
337 desc
.attribute
= GUC_CTX_DESC_ATTR_ACTIVE
| GUC_CTX_DESC_ATTR_KERNEL
;
338 desc
.context_id
= client
->ctx_index
;
339 desc
.priority
= client
->priority
;
340 desc
.db_id
= client
->doorbell_id
;
342 for_each_engine_masked(engine
, dev_priv
, client
->engines
) {
343 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
344 uint32_t guc_engine_id
= engine
->guc_id
;
345 struct guc_execlist_context
*lrc
= &desc
.lrc
[guc_engine_id
];
346 struct drm_i915_gem_object
*obj
;
348 /* TODO: We have a design issue to be solved here. Only when we
349 * receive the first batch, we know which engine is used by the
350 * user. But here GuC expects the lrc and ring to be pinned. It
351 * is not an issue for default context, which is the only one
352 * for now who owns a GuC client. But for future owner of GuC
353 * client, need to make sure lrc is pinned prior to enter here.
356 break; /* XXX: continue? */
358 lrc
->context_desc
= lower_32_bits(ce
->lrc_desc
);
360 /* The state page is after PPHWSP */
361 gfx_addr
= i915_gem_obj_ggtt_offset(ce
->state
);
362 lrc
->ring_lcra
= gfx_addr
+ LRC_STATE_PN
* PAGE_SIZE
;
363 lrc
->context_id
= (client
->ctx_index
<< GUC_ELC_CTXID_OFFSET
) |
364 (guc_engine_id
<< GUC_ELC_ENGINE_OFFSET
);
367 gfx_addr
= i915_gem_obj_ggtt_offset(obj
);
369 lrc
->ring_begin
= gfx_addr
;
370 lrc
->ring_end
= gfx_addr
+ obj
->base
.size
- 1;
371 lrc
->ring_next_free_location
= gfx_addr
;
372 lrc
->ring_current_tail_pointer_value
= 0;
374 desc
.engines_used
|= (1 << guc_engine_id
);
377 DRM_DEBUG_DRIVER("Host engines 0x%x => GuC engines used 0x%x\n",
378 client
->engines
, desc
.engines_used
);
379 WARN_ON(desc
.engines_used
== 0);
382 * The doorbell, process descriptor, and workqueue are all parts
383 * of the client object, which the GuC will reference via the GGTT
385 gfx_addr
= client
->vma
->node
.start
;
386 desc
.db_trigger_phy
= sg_dma_address(client
->vma
->pages
->sgl
) +
387 client
->doorbell_offset
;
388 desc
.db_trigger_cpu
= (uintptr_t)client
->client_base
+
389 client
->doorbell_offset
;
390 desc
.db_trigger_uk
= gfx_addr
+ client
->doorbell_offset
;
391 desc
.process_desc
= gfx_addr
+ client
->proc_desc_offset
;
392 desc
.wq_addr
= gfx_addr
+ client
->wq_offset
;
393 desc
.wq_size
= client
->wq_size
;
396 * XXX: Take LRCs from an existing context if this is not an
397 * IsKMDCreatedContext client
399 desc
.desc_private
= (uintptr_t)client
;
401 /* Pool context is pinned already */
402 sg
= guc
->ctx_pool_vma
->pages
;
403 sg_pcopy_from_buffer(sg
->sgl
, sg
->nents
, &desc
, sizeof(desc
),
404 sizeof(desc
) * client
->ctx_index
);
407 static void guc_fini_ctx_desc(struct intel_guc
*guc
,
408 struct i915_guc_client
*client
)
410 struct guc_context_desc desc
;
413 memset(&desc
, 0, sizeof(desc
));
415 sg
= guc
->ctx_pool_vma
->pages
;
416 sg_pcopy_from_buffer(sg
->sgl
, sg
->nents
, &desc
, sizeof(desc
),
417 sizeof(desc
) * client
->ctx_index
);
421 * i915_guc_wq_check_space() - check that the GuC can accept a request
422 * @request: request associated with the commands
424 * Return: 0 if space is available
425 * -EAGAIN if space is not currently available
427 * This function must be called (and must return 0) before a request
428 * is submitted to the GuC via i915_guc_submit() below. Once a result
429 * of 0 has been returned, it remains valid until (but only until)
430 * the next call to submit().
432 * This precheck allows the caller to determine in advance that space
433 * will be available for the next submission before committing resources
434 * to it, and helps avoid late failures with complicated recovery paths.
436 int i915_guc_wq_check_space(struct drm_i915_gem_request
*request
)
438 const size_t wqi_size
= sizeof(struct guc_wq_item
);
439 struct i915_guc_client
*gc
= request
->i915
->guc
.execbuf_client
;
440 struct guc_process_desc
*desc
;
443 GEM_BUG_ON(gc
== NULL
);
445 desc
= gc
->client_base
+ gc
->proc_desc_offset
;
447 freespace
= CIRC_SPACE(gc
->wq_tail
, desc
->head
, gc
->wq_size
);
448 if (likely(freespace
>= wqi_size
))
451 gc
->no_wq_space
+= 1;
456 static void guc_add_workqueue_item(struct i915_guc_client
*gc
,
457 struct drm_i915_gem_request
*rq
)
459 /* wqi_len is in DWords, and does not include the one-word header */
460 const size_t wqi_size
= sizeof(struct guc_wq_item
);
461 const u32 wqi_len
= wqi_size
/sizeof(u32
) - 1;
462 struct intel_engine_cs
*engine
= rq
->engine
;
463 struct guc_process_desc
*desc
;
464 struct guc_wq_item
*wqi
;
466 u32 freespace
, tail
, wq_off
, wq_page
;
468 desc
= gc
->client_base
+ gc
->proc_desc_offset
;
470 /* Free space is guaranteed, see i915_guc_wq_check_space() above */
471 freespace
= CIRC_SPACE(gc
->wq_tail
, desc
->head
, gc
->wq_size
);
472 GEM_BUG_ON(freespace
< wqi_size
);
474 /* The GuC firmware wants the tail index in QWords, not bytes */
476 GEM_BUG_ON(tail
& 7);
478 GEM_BUG_ON(tail
> WQ_RING_TAIL_MAX
);
480 /* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we
481 * should not have the case where structure wqi is across page, neither
482 * wrapped to the beginning. This simplifies the implementation below.
484 * XXX: if not the case, we need save data to a temp wqi and copy it to
485 * workqueue buffer dw by dw.
487 BUILD_BUG_ON(wqi_size
!= 16);
489 /* postincrement WQ tail for next time */
490 wq_off
= gc
->wq_tail
;
491 gc
->wq_tail
+= wqi_size
;
492 gc
->wq_tail
&= gc
->wq_size
- 1;
493 GEM_BUG_ON(wq_off
& (wqi_size
- 1));
495 /* WQ starts from the page after doorbell / process_desc */
496 wq_page
= (wq_off
+ GUC_DB_SIZE
) >> PAGE_SHIFT
;
497 wq_off
&= PAGE_SIZE
- 1;
498 base
= kmap_atomic(i915_gem_object_get_page(gc
->vma
->obj
, wq_page
));
499 wqi
= (struct guc_wq_item
*)((char *)base
+ wq_off
);
501 /* Now fill in the 4-word work queue item */
502 wqi
->header
= WQ_TYPE_INORDER
|
503 (wqi_len
<< WQ_LEN_SHIFT
) |
504 (engine
->guc_id
<< WQ_TARGET_SHIFT
) |
507 /* The GuC wants only the low-order word of the context descriptor */
508 wqi
->context_desc
= (u32
)intel_lr_context_descriptor(rq
->ctx
, engine
);
510 wqi
->ring_tail
= tail
<< WQ_RING_TAIL_SHIFT
;
511 wqi
->fence_id
= rq
->fence
.seqno
;
516 static int guc_ring_doorbell(struct i915_guc_client
*gc
)
518 struct guc_process_desc
*desc
;
519 union guc_doorbell_qw db_cmp
, db_exc
, db_ret
;
520 union guc_doorbell_qw
*db
;
521 int attempt
= 2, ret
= -EAGAIN
;
523 desc
= gc
->client_base
+ gc
->proc_desc_offset
;
525 /* Update the tail so it is visible to GuC */
526 desc
->tail
= gc
->wq_tail
;
529 db_cmp
.db_status
= GUC_DOORBELL_ENABLED
;
530 db_cmp
.cookie
= gc
->cookie
;
532 /* cookie to be updated */
533 db_exc
.db_status
= GUC_DOORBELL_ENABLED
;
534 db_exc
.cookie
= gc
->cookie
+ 1;
535 if (db_exc
.cookie
== 0)
538 /* pointer of current doorbell cacheline */
539 db
= gc
->client_base
+ gc
->doorbell_offset
;
542 /* lets ring the doorbell */
543 db_ret
.value_qw
= atomic64_cmpxchg((atomic64_t
*)db
,
544 db_cmp
.value_qw
, db_exc
.value_qw
);
546 /* if the exchange was successfully executed */
547 if (db_ret
.value_qw
== db_cmp
.value_qw
) {
548 /* db was successfully rung */
549 gc
->cookie
= db_exc
.cookie
;
554 /* XXX: doorbell was lost and need to acquire it again */
555 if (db_ret
.db_status
== GUC_DOORBELL_DISABLED
)
558 DRM_ERROR("Cookie mismatch. Expected %d, returned %d\n",
559 db_cmp
.cookie
, db_ret
.cookie
);
561 /* update the cookie to newly read cookie from GuC */
562 db_cmp
.cookie
= db_ret
.cookie
;
563 db_exc
.cookie
= db_ret
.cookie
+ 1;
564 if (db_exc
.cookie
== 0)
572 * i915_guc_submit() - Submit commands through GuC
573 * @rq: request associated with the commands
575 * Return: 0 on success, otherwise an errno.
576 * (Note: nonzero really shouldn't happen!)
578 * The caller must have already called i915_guc_wq_check_space() above
579 * with a result of 0 (success) since the last request submission. This
580 * guarantees that there is space in the work queue for the new request,
581 * so enqueuing the item cannot fail.
583 * Bad Things Will Happen if the caller violates this protocol e.g. calls
584 * submit() when check() says there's no space, or calls submit() multiple
585 * times with no intervening check().
587 * The only error here arises if the doorbell hardware isn't functioning
588 * as expected, which really shouln't happen.
590 static void i915_guc_submit(struct drm_i915_gem_request
*rq
)
592 unsigned int engine_id
= rq
->engine
->id
;
593 struct intel_guc
*guc
= &rq
->i915
->guc
;
594 struct i915_guc_client
*client
= guc
->execbuf_client
;
597 guc_add_workqueue_item(client
, rq
);
598 b_ret
= guc_ring_doorbell(client
);
600 client
->submissions
[engine_id
] += 1;
601 client
->retcode
= b_ret
;
605 guc
->submissions
[engine_id
] += 1;
606 guc
->last_seqno
[engine_id
] = rq
->fence
.seqno
;
610 * Everything below here is concerned with setup & teardown, and is
611 * therefore not part of the somewhat time-critical batch-submission
612 * path of i915_guc_submit() above.
616 * guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
618 * @size: size of area to allocate (both virtual space and memory)
620 * This is a wrapper to create an object for use with the GuC. In order to
621 * use it inside the GuC, an object needs to be pinned lifetime, so we allocate
622 * both some backing storage and a range inside the Global GTT. We must pin
623 * it in the GGTT somewhere other than than [0, GUC_WOPCM_TOP) because that
624 * range is reserved inside GuC.
626 * Return: A i915_vma if successful, otherwise an ERR_PTR.
628 static struct i915_vma
*guc_allocate_vma(struct intel_guc
*guc
, u32 size
)
630 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
631 struct drm_i915_gem_object
*obj
;
632 struct i915_vma
*vma
;
635 obj
= i915_gem_object_create(&dev_priv
->drm
, size
);
637 return ERR_CAST(obj
);
639 vma
= i915_vma_create(obj
, &dev_priv
->ggtt
.base
, NULL
);
643 ret
= i915_vma_pin(vma
, 0, PAGE_SIZE
,
644 PIN_GLOBAL
| PIN_OFFSET_BIAS
| GUC_WOPCM_TOP
);
650 /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
651 I915_WRITE(GEN8_GTCR
, GEN8_GTCR_INVALIDATE
);
656 i915_gem_object_put(obj
);
661 * guc_release_vma() - Release gem object allocated for GuC usage
662 * @vma: gem obj to be released
664 static void guc_release_vma(struct i915_vma
*vma
)
674 guc_client_free(struct drm_i915_private
*dev_priv
,
675 struct i915_guc_client
*client
)
677 struct intel_guc
*guc
= &dev_priv
->guc
;
683 * XXX: wait for any outstanding submissions before freeing memory.
684 * Be sure to drop any locks
687 if (client
->client_base
) {
689 * If we got as far as setting up a doorbell, make sure we
690 * shut it down before unmapping & deallocating the memory.
692 guc_disable_doorbell(guc
, client
);
694 kunmap(kmap_to_page(client
->client_base
));
697 guc_release_vma(client
->vma
);
699 if (client
->ctx_index
!= GUC_INVALID_CTX_ID
) {
700 guc_fini_ctx_desc(guc
, client
);
701 ida_simple_remove(&guc
->ctx_ids
, client
->ctx_index
);
707 /* Check that a doorbell register is in the expected state */
708 static bool guc_doorbell_check(struct intel_guc
*guc
, uint16_t db_id
)
710 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
711 i915_reg_t drbreg
= GEN8_DRBREGL(db_id
);
712 uint32_t value
= I915_READ(drbreg
);
713 bool enabled
= (value
& GUC_DOORBELL_ENABLED
) != 0;
714 bool expected
= test_bit(db_id
, guc
->doorbell_bitmap
);
716 if (enabled
== expected
)
719 DRM_DEBUG_DRIVER("Doorbell %d (reg 0x%x) 0x%x, should be %s\n",
720 db_id
, drbreg
.reg
, value
,
721 expected
? "active" : "inactive");
727 * Borrow the first client to set up & tear down each unused doorbell
728 * in turn, to ensure that all doorbell h/w is (re)initialised.
730 static void guc_init_doorbell_hw(struct intel_guc
*guc
)
732 struct i915_guc_client
*client
= guc
->execbuf_client
;
736 /* Save client's original doorbell selection */
737 db_id
= client
->doorbell_id
;
739 for (i
= 0; i
< GUC_MAX_DOORBELLS
; ++i
) {
740 /* Skip if doorbell is OK */
741 if (guc_doorbell_check(guc
, i
))
744 err
= guc_update_doorbell_id(guc
, client
, i
);
746 DRM_DEBUG_DRIVER("Doorbell %d update failed, err %d\n",
750 /* Restore to original value */
751 err
= guc_update_doorbell_id(guc
, client
, db_id
);
753 DRM_ERROR("Failed to restore doorbell to %d, err %d\n",
756 /* Read back & verify all doorbell registers */
757 for (i
= 0; i
< GUC_MAX_DOORBELLS
; ++i
)
758 (void)guc_doorbell_check(guc
, i
);
762 * guc_client_alloc() - Allocate an i915_guc_client
763 * @dev_priv: driver private data structure
764 * @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW
765 * The kernel client to replace ExecList submission is created with
766 * NORMAL priority. Priority of a client for scheduler can be HIGH,
767 * while a preemption context can use CRITICAL.
768 * @ctx: the context that owns the client (we use the default render
771 * Return: An i915_guc_client object if success, else NULL.
773 static struct i915_guc_client
*
774 guc_client_alloc(struct drm_i915_private
*dev_priv
,
777 struct i915_gem_context
*ctx
)
779 struct i915_guc_client
*client
;
780 struct intel_guc
*guc
= &dev_priv
->guc
;
781 struct i915_vma
*vma
;
784 client
= kzalloc(sizeof(*client
), GFP_KERNEL
);
790 client
->engines
= engines
;
791 client
->priority
= priority
;
792 client
->doorbell_id
= GUC_INVALID_DOORBELL_ID
;
794 client
->ctx_index
= (uint32_t)ida_simple_get(&guc
->ctx_ids
, 0,
795 GUC_MAX_GPU_CONTEXTS
, GFP_KERNEL
);
796 if (client
->ctx_index
>= GUC_MAX_GPU_CONTEXTS
) {
797 client
->ctx_index
= GUC_INVALID_CTX_ID
;
801 /* The first page is doorbell/proc_desc. Two followed pages are wq. */
802 vma
= guc_allocate_vma(guc
, GUC_DB_SIZE
+ GUC_WQ_SIZE
);
806 /* We'll keep just the first (doorbell/proc) page permanently kmap'd. */
808 client
->client_base
= kmap(i915_vma_first_page(vma
));
809 client
->wq_offset
= GUC_DB_SIZE
;
810 client
->wq_size
= GUC_WQ_SIZE
;
812 db_id
= select_doorbell_register(guc
, client
->priority
);
813 if (db_id
== GUC_INVALID_DOORBELL_ID
)
814 /* XXX: evict a doorbell instead? */
817 client
->doorbell_offset
= select_doorbell_cacheline(guc
);
820 * Since the doorbell only requires a single cacheline, we can save
821 * space by putting the application process descriptor in the same
822 * page. Use the half of the page that doesn't include the doorbell.
824 if (client
->doorbell_offset
>= (GUC_DB_SIZE
/ 2))
825 client
->proc_desc_offset
= 0;
827 client
->proc_desc_offset
= (GUC_DB_SIZE
/ 2);
829 guc_init_proc_desc(guc
, client
);
830 guc_init_ctx_desc(guc
, client
);
831 if (guc_init_doorbell(guc
, client
, db_id
))
834 DRM_DEBUG_DRIVER("new priority %u client %p for engine(s) 0x%x: ctx_index %u\n",
835 priority
, client
, client
->engines
, client
->ctx_index
);
836 DRM_DEBUG_DRIVER("doorbell id %u, cacheline offset 0x%x\n",
837 client
->doorbell_id
, client
->doorbell_offset
);
842 DRM_ERROR("FAILED to create priority %u GuC client!\n", priority
);
844 guc_client_free(dev_priv
, client
);
848 static void guc_create_log(struct intel_guc
*guc
)
850 struct i915_vma
*vma
;
851 unsigned long offset
;
852 uint32_t size
, flags
;
854 if (i915
.guc_log_level
< GUC_LOG_VERBOSITY_MIN
)
857 if (i915
.guc_log_level
> GUC_LOG_VERBOSITY_MAX
)
858 i915
.guc_log_level
= GUC_LOG_VERBOSITY_MAX
;
860 /* The first page is to save log buffer state. Allocate one
861 * extra page for others in case for overlap */
862 size
= (1 + GUC_LOG_DPC_PAGES
+ 1 +
863 GUC_LOG_ISR_PAGES
+ 1 +
864 GUC_LOG_CRASH_PAGES
+ 1) << PAGE_SHIFT
;
868 vma
= guc_allocate_vma(guc
, size
);
870 /* logging will be off */
871 i915
.guc_log_level
= -1;
878 /* each allocated unit is a page */
879 flags
= GUC_LOG_VALID
| GUC_LOG_NOTIFY_ON_HALF_FULL
|
880 (GUC_LOG_DPC_PAGES
<< GUC_LOG_DPC_SHIFT
) |
881 (GUC_LOG_ISR_PAGES
<< GUC_LOG_ISR_SHIFT
) |
882 (GUC_LOG_CRASH_PAGES
<< GUC_LOG_CRASH_SHIFT
);
884 offset
= vma
->node
.start
>> PAGE_SHIFT
; /* in pages */
885 guc
->log_flags
= (offset
<< GUC_LOG_BUF_ADDR_SHIFT
) | flags
;
888 static void init_guc_policies(struct guc_policies
*policies
)
890 struct guc_policy
*policy
;
893 policies
->dpc_promote_time
= 500000;
894 policies
->max_num_work_items
= POLICY_MAX_NUM_WI
;
896 for (p
= 0; p
< GUC_CTX_PRIORITY_NUM
; p
++) {
897 for (i
= GUC_RENDER_ENGINE
; i
< GUC_MAX_ENGINES_NUM
; i
++) {
898 policy
= &policies
->policy
[p
][i
];
900 policy
->execution_quantum
= 1000000;
901 policy
->preemption_time
= 500000;
902 policy
->fault_time
= 250000;
903 policy
->policy_flags
= 0;
907 policies
->is_valid
= 1;
910 static void guc_create_ads(struct intel_guc
*guc
)
912 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
913 struct i915_vma
*vma
;
915 struct guc_policies
*policies
;
916 struct guc_mmio_reg_state
*reg_state
;
917 struct intel_engine_cs
*engine
;
921 /* The ads obj includes the struct itself and buffers passed to GuC */
922 size
= sizeof(struct guc_ads
) + sizeof(struct guc_policies
) +
923 sizeof(struct guc_mmio_reg_state
) +
924 GUC_S3_SAVE_SPACE_PAGES
* PAGE_SIZE
;
928 vma
= guc_allocate_vma(guc
, PAGE_ALIGN(size
));
935 page
= i915_vma_first_page(vma
);
939 * The GuC requires a "Golden Context" when it reinitialises
940 * engines after a reset. Here we use the Render ring default
941 * context, which must already exist and be pinned in the GGTT,
942 * so its address won't change after we've told the GuC where
945 engine
= &dev_priv
->engine
[RCS
];
946 ads
->golden_context_lrca
= engine
->status_page
.gfx_addr
;
948 for_each_engine(engine
, dev_priv
)
949 ads
->eng_state_size
[engine
->guc_id
] = intel_lr_context_size(engine
);
951 /* GuC scheduling policies */
952 policies
= (void *)ads
+ sizeof(struct guc_ads
);
953 init_guc_policies(policies
);
955 ads
->scheduler_policies
= vma
->node
.start
+ sizeof(struct guc_ads
);
958 reg_state
= (void *)policies
+ sizeof(struct guc_policies
);
960 for_each_engine(engine
, dev_priv
) {
961 reg_state
->mmio_white_list
[engine
->guc_id
].mmio_start
=
962 engine
->mmio_base
+ GUC_MMIO_WHITE_LIST_START
;
964 /* Nothing to be saved or restored for now. */
965 reg_state
->mmio_white_list
[engine
->guc_id
].count
= 0;
968 ads
->reg_state_addr
= ads
->scheduler_policies
+
969 sizeof(struct guc_policies
);
971 ads
->reg_state_buffer
= ads
->reg_state_addr
+
972 sizeof(struct guc_mmio_reg_state
);
978 * Set up the memory resources to be shared with the GuC. At this point,
979 * we require just one object that can be mapped through the GGTT.
981 int i915_guc_submission_init(struct drm_i915_private
*dev_priv
)
983 struct intel_guc
*guc
= &dev_priv
->guc
;
984 struct i915_vma
*vma
;
987 /* Wipe bitmap & delete client in case of reinitialisation */
988 bitmap_clear(guc
->doorbell_bitmap
, 0, GUC_MAX_DOORBELLS
);
989 i915_guc_submission_disable(dev_priv
);
991 if (!i915
.enable_guc_submission
)
992 return 0; /* not enabled */
994 if (guc
->ctx_pool_vma
)
995 return 0; /* already allocated */
997 size
= PAGE_ALIGN(GUC_MAX_GPU_CONTEXTS
*sizeof(struct guc_context_desc
));
998 vma
= guc_allocate_vma(guc
, size
);
1000 return PTR_ERR(vma
);
1002 guc
->ctx_pool_vma
= vma
;
1003 ida_init(&guc
->ctx_ids
);
1004 guc_create_log(guc
);
1005 guc_create_ads(guc
);
1010 int i915_guc_submission_enable(struct drm_i915_private
*dev_priv
)
1012 struct intel_guc
*guc
= &dev_priv
->guc
;
1013 struct i915_guc_client
*client
;
1014 struct intel_engine_cs
*engine
;
1016 /* client for execbuf submission */
1017 client
= guc_client_alloc(dev_priv
,
1018 INTEL_INFO(dev_priv
)->ring_mask
,
1019 GUC_CTX_PRIORITY_KMD_NORMAL
,
1020 dev_priv
->kernel_context
);
1022 DRM_ERROR("Failed to create execbuf guc_client\n");
1026 guc
->execbuf_client
= client
;
1027 host2guc_sample_forcewake(guc
, client
);
1028 guc_init_doorbell_hw(guc
);
1030 /* Take over from manual control of ELSP (execlists) */
1031 for_each_engine(engine
, dev_priv
)
1032 engine
->submit_request
= i915_guc_submit
;
1037 void i915_guc_submission_disable(struct drm_i915_private
*dev_priv
)
1039 struct intel_guc
*guc
= &dev_priv
->guc
;
1041 if (!guc
->execbuf_client
)
1044 /* Revert back to manual ELSP submission */
1045 intel_execlists_enable_submission(dev_priv
);
1047 guc_client_free(dev_priv
, guc
->execbuf_client
);
1048 guc
->execbuf_client
= NULL
;
1051 void i915_guc_submission_fini(struct drm_i915_private
*dev_priv
)
1053 struct intel_guc
*guc
= &dev_priv
->guc
;
1055 guc_release_vma(fetch_and_zero(&guc
->ads_vma
));
1056 guc_release_vma(fetch_and_zero(&guc
->log_vma
));
1058 if (guc
->ctx_pool_vma
)
1059 ida_destroy(&guc
->ctx_ids
);
1060 guc_release_vma(fetch_and_zero(&guc
->ctx_pool_vma
));
1064 * intel_guc_suspend() - notify GuC entering suspend state
1067 int intel_guc_suspend(struct drm_device
*dev
)
1069 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1070 struct intel_guc
*guc
= &dev_priv
->guc
;
1071 struct i915_gem_context
*ctx
;
1074 if (guc
->guc_fw
.guc_fw_load_status
!= GUC_FIRMWARE_SUCCESS
)
1077 ctx
= dev_priv
->kernel_context
;
1079 data
[0] = HOST2GUC_ACTION_ENTER_S_STATE
;
1080 /* any value greater than GUC_POWER_D0 */
1081 data
[1] = GUC_POWER_D1
;
1082 /* first page is shared data with GuC */
1083 data
[2] = i915_gem_obj_ggtt_offset(ctx
->engine
[RCS
].state
);
1085 return host2guc_action(guc
, data
, ARRAY_SIZE(data
));
1090 * intel_guc_resume() - notify GuC resuming from suspend state
1093 int intel_guc_resume(struct drm_device
*dev
)
1095 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1096 struct intel_guc
*guc
= &dev_priv
->guc
;
1097 struct i915_gem_context
*ctx
;
1100 if (guc
->guc_fw
.guc_fw_load_status
!= GUC_FIRMWARE_SUCCESS
)
1103 ctx
= dev_priv
->kernel_context
;
1105 data
[0] = HOST2GUC_ACTION_EXIT_S_STATE
;
1106 data
[1] = GUC_POWER_D0
;
1107 /* first page is shared data with GuC */
1108 data
[2] = i915_gem_obj_ggtt_offset(ctx
->engine
[RCS
].state
);
1110 return host2guc_action(guc
, data
, ARRAY_SIZE(data
));