2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include <linux/firmware.h>
25 #include <linux/circ_buf.h>
27 #include "intel_guc.h"
30 * DOC: GuC-based command submission
33 * We use the term client to avoid confusion with contexts. A i915_guc_client is
34 * equivalent to GuC object guc_context_desc. This context descriptor is
35 * allocated from a pool of 1024 entries. Kernel driver will allocate doorbell
36 * and workqueue for it. Also the process descriptor (guc_process_desc), which
37 * is mapped to client space. So the client can write Work Item then ring the
40 * To simplify the implementation, we allocate one gem object that contains all
41 * pages for doorbell, process descriptor and workqueue.
43 * The Scratch registers:
44 * There are 16 MMIO-based registers start from 0xC180. The kernel driver writes
45 * a value to the action register (SOFT_SCRATCH_0) along with any data. It then
46 * triggers an interrupt on the GuC via another register write (0xC4C8).
47 * Firmware writes a success/fail code back to the action register after
48 * processes the request. The kernel driver polls waiting for this update and
50 * See host2guc_action()
53 * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
54 * mapped into process space.
57 * There are several types of work items that the host may place into a
58 * workqueue, each with its own requirements and limitations. Currently only
59 * WQ_TYPE_INORDER is needed to support legacy submission via GuC, which
60 * represents in-order queue. The kernel driver packs ring tail pointer and an
61 * ELSP context descriptor dword into Work Item.
62 * See guc_add_workqueue_item()
67 * Read GuC command/status register (SOFT_SCRATCH_0)
68 * Return true if it contains a response rather than a command
70 static inline bool host2guc_action_response(struct drm_i915_private
*dev_priv
,
73 u32 val
= I915_READ(SOFT_SCRATCH(0));
75 return GUC2HOST_IS_RESPONSE(val
);
78 static int host2guc_action(struct intel_guc
*guc
, u32
*data
, u32 len
)
80 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
85 if (WARN_ON(len
< 1 || len
> 15))
88 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
90 dev_priv
->guc
.action_count
+= 1;
91 dev_priv
->guc
.action_cmd
= data
[0];
93 for (i
= 0; i
< len
; i
++)
94 I915_WRITE(SOFT_SCRATCH(i
), data
[i
]);
96 POSTING_READ(SOFT_SCRATCH(i
- 1));
98 I915_WRITE(HOST2GUC_INTERRUPT
, HOST2GUC_TRIGGER
);
100 /* No HOST2GUC command should take longer than 10ms */
101 ret
= wait_for_atomic(host2guc_action_response(dev_priv
, &status
), 10);
102 if (status
!= GUC2HOST_STATUS_SUCCESS
) {
104 * Either the GuC explicitly returned an error (which
105 * we convert to -EIO here) or no response at all was
106 * received within the timeout limit (-ETIMEDOUT)
108 if (ret
!= -ETIMEDOUT
)
111 DRM_ERROR("GUC: host2guc action 0x%X failed. ret=%d "
112 "status=0x%08X response=0x%08X\n",
113 data
[0], ret
, status
,
114 I915_READ(SOFT_SCRATCH(15)));
116 dev_priv
->guc
.action_fail
+= 1;
117 dev_priv
->guc
.action_err
= ret
;
119 dev_priv
->guc
.action_status
= status
;
121 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
127 * Tell the GuC to allocate or deallocate a specific doorbell
130 static int host2guc_allocate_doorbell(struct intel_guc
*guc
,
131 struct i915_guc_client
*client
)
135 data
[0] = HOST2GUC_ACTION_ALLOCATE_DOORBELL
;
136 data
[1] = client
->ctx_index
;
138 return host2guc_action(guc
, data
, 2);
141 static int host2guc_release_doorbell(struct intel_guc
*guc
,
142 struct i915_guc_client
*client
)
146 data
[0] = HOST2GUC_ACTION_DEALLOCATE_DOORBELL
;
147 data
[1] = client
->ctx_index
;
149 return host2guc_action(guc
, data
, 2);
152 static int host2guc_sample_forcewake(struct intel_guc
*guc
,
153 struct i915_guc_client
*client
)
155 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
156 struct drm_device
*dev
= dev_priv
->dev
;
159 data
[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE
;
160 /* WaRsDisableCoarsePowerGating:skl,bxt */
161 if (!intel_enable_rc6(dev
) ||
162 NEEDS_WaRsDisableCoarsePowerGating(dev
))
165 /* bit 0 and 1 are for Render and Media domain separately */
166 data
[1] = GUC_FORCEWAKE_RENDER
| GUC_FORCEWAKE_MEDIA
;
168 return host2guc_action(guc
, data
, ARRAY_SIZE(data
));
172 * Initialise, update, or clear doorbell data shared with the GuC
174 * These functions modify shared data and so need access to the mapped
175 * client object which contains the page being used for the doorbell
178 static void guc_init_doorbell(struct intel_guc
*guc
,
179 struct i915_guc_client
*client
)
181 struct guc_doorbell_info
*doorbell
;
184 base
= kmap_atomic(i915_gem_object_get_page(client
->client_obj
, 0));
185 doorbell
= base
+ client
->doorbell_offset
;
187 doorbell
->db_status
= 1;
188 doorbell
->cookie
= 0;
193 static int guc_ring_doorbell(struct i915_guc_client
*gc
)
195 struct guc_process_desc
*desc
;
196 union guc_doorbell_qw db_cmp
, db_exc
, db_ret
;
197 union guc_doorbell_qw
*db
;
199 int attempt
= 2, ret
= -EAGAIN
;
201 base
= kmap_atomic(i915_gem_object_get_page(gc
->client_obj
, 0));
202 desc
= base
+ gc
->proc_desc_offset
;
204 /* Update the tail so it is visible to GuC */
205 desc
->tail
= gc
->wq_tail
;
208 db_cmp
.db_status
= GUC_DOORBELL_ENABLED
;
209 db_cmp
.cookie
= gc
->cookie
;
211 /* cookie to be updated */
212 db_exc
.db_status
= GUC_DOORBELL_ENABLED
;
213 db_exc
.cookie
= gc
->cookie
+ 1;
214 if (db_exc
.cookie
== 0)
217 /* pointer of current doorbell cacheline */
218 db
= base
+ gc
->doorbell_offset
;
221 /* lets ring the doorbell */
222 db_ret
.value_qw
= atomic64_cmpxchg((atomic64_t
*)db
,
223 db_cmp
.value_qw
, db_exc
.value_qw
);
225 /* if the exchange was successfully executed */
226 if (db_ret
.value_qw
== db_cmp
.value_qw
) {
227 /* db was successfully rung */
228 gc
->cookie
= db_exc
.cookie
;
233 /* XXX: doorbell was lost and need to acquire it again */
234 if (db_ret
.db_status
== GUC_DOORBELL_DISABLED
)
237 DRM_ERROR("Cookie mismatch. Expected %d, returned %d\n",
238 db_cmp
.cookie
, db_ret
.cookie
);
240 /* update the cookie to newly read cookie from GuC */
241 db_cmp
.cookie
= db_ret
.cookie
;
242 db_exc
.cookie
= db_ret
.cookie
+ 1;
243 if (db_exc
.cookie
== 0)
251 static void guc_disable_doorbell(struct intel_guc
*guc
,
252 struct i915_guc_client
*client
)
254 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
255 struct guc_doorbell_info
*doorbell
;
257 i915_reg_t drbreg
= GEN8_DRBREGL(client
->doorbell_id
);
260 base
= kmap_atomic(i915_gem_object_get_page(client
->client_obj
, 0));
261 doorbell
= base
+ client
->doorbell_offset
;
263 doorbell
->db_status
= 0;
267 I915_WRITE(drbreg
, I915_READ(drbreg
) & ~GEN8_DRB_VALID
);
269 value
= I915_READ(drbreg
);
270 WARN_ON((value
& GEN8_DRB_VALID
) != 0);
272 I915_WRITE(GEN8_DRBREGU(client
->doorbell_id
), 0);
273 I915_WRITE(drbreg
, 0);
275 /* XXX: wait for any interrupts */
276 /* XXX: wait for workqueue to drain */
280 * Select, assign and relase doorbell cachelines
282 * These functions track which doorbell cachelines are in use.
283 * The data they manipulate is protected by the host2guc lock.
286 static uint32_t select_doorbell_cacheline(struct intel_guc
*guc
)
288 const uint32_t cacheline_size
= cache_line_size();
291 /* Doorbell uses a single cache line within a page */
292 offset
= offset_in_page(guc
->db_cacheline
);
294 /* Moving to next cache line to reduce contention */
295 guc
->db_cacheline
+= cacheline_size
;
297 DRM_DEBUG_DRIVER("selected doorbell cacheline 0x%x, next 0x%x, linesize %u\n",
298 offset
, guc
->db_cacheline
, cacheline_size
);
303 static uint16_t assign_doorbell(struct intel_guc
*guc
, uint32_t priority
)
306 * The bitmap is split into two halves; the first half is used for
307 * normal priority contexts, the second half for high-priority ones.
308 * Note that logically higher priorities are numerically less than
309 * normal ones, so the test below means "is it high-priority?"
311 const bool hi_pri
= (priority
<= GUC_CTX_PRIORITY_HIGH
);
312 const uint16_t half
= GUC_MAX_DOORBELLS
/ 2;
313 const uint16_t start
= hi_pri
? half
: 0;
314 const uint16_t end
= start
+ half
;
317 id
= find_next_zero_bit(guc
->doorbell_bitmap
, end
, start
);
319 id
= GUC_INVALID_DOORBELL_ID
;
321 bitmap_set(guc
->doorbell_bitmap
, id
, 1);
323 DRM_DEBUG_DRIVER("assigned %s priority doorbell id 0x%x\n",
324 hi_pri
? "high" : "normal", id
);
329 static void release_doorbell(struct intel_guc
*guc
, uint16_t id
)
331 bitmap_clear(guc
->doorbell_bitmap
, id
, 1);
335 * Initialise the process descriptor shared with the GuC firmware.
337 static void guc_init_proc_desc(struct intel_guc
*guc
,
338 struct i915_guc_client
*client
)
340 struct guc_process_desc
*desc
;
343 base
= kmap_atomic(i915_gem_object_get_page(client
->client_obj
, 0));
344 desc
= base
+ client
->proc_desc_offset
;
346 memset(desc
, 0, sizeof(*desc
));
349 * XXX: pDoorbell and WQVBaseAddress are pointers in process address
350 * space for ring3 clients (set them as in mmap_ioctl) or kernel
351 * space for kernel clients (map on demand instead? May make debug
352 * easier to have it mapped).
354 desc
->wq_base_addr
= 0;
355 desc
->db_base_addr
= 0;
357 desc
->context_id
= client
->ctx_index
;
358 desc
->wq_size_bytes
= client
->wq_size
;
359 desc
->wq_status
= WQ_STATUS_ACTIVE
;
360 desc
->priority
= client
->priority
;
366 * Initialise/clear the context descriptor shared with the GuC firmware.
368 * This descriptor tells the GuC where (in GGTT space) to find the important
369 * data structures relating to this client (doorbell, process descriptor,
373 static void guc_init_ctx_desc(struct intel_guc
*guc
,
374 struct i915_guc_client
*client
)
376 struct intel_context
*ctx
= client
->owner
;
377 struct guc_context_desc desc
;
381 memset(&desc
, 0, sizeof(desc
));
383 desc
.attribute
= GUC_CTX_DESC_ATTR_ACTIVE
| GUC_CTX_DESC_ATTR_KERNEL
;
384 desc
.context_id
= client
->ctx_index
;
385 desc
.priority
= client
->priority
;
386 desc
.db_id
= client
->doorbell_id
;
388 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
389 struct guc_execlist_context
*lrc
= &desc
.lrc
[i
];
390 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[i
].ringbuf
;
391 struct intel_engine_cs
*ring
;
392 struct drm_i915_gem_object
*obj
;
395 /* TODO: We have a design issue to be solved here. Only when we
396 * receive the first batch, we know which engine is used by the
397 * user. But here GuC expects the lrc and ring to be pinned. It
398 * is not an issue for default context, which is the only one
399 * for now who owns a GuC client. But for future owner of GuC
400 * client, need to make sure lrc is pinned prior to enter here.
402 obj
= ctx
->engine
[i
].state
;
404 break; /* XXX: continue? */
406 ring
= ringbuf
->ring
;
407 ctx_desc
= intel_lr_context_descriptor(ctx
, ring
);
408 lrc
->context_desc
= (u32
)ctx_desc
;
410 /* The state page is after PPHWSP */
411 lrc
->ring_lcra
= i915_gem_obj_ggtt_offset(obj
) +
412 LRC_STATE_PN
* PAGE_SIZE
;
413 lrc
->context_id
= (client
->ctx_index
<< GUC_ELC_CTXID_OFFSET
) |
414 (ring
->id
<< GUC_ELC_ENGINE_OFFSET
);
418 lrc
->ring_begin
= i915_gem_obj_ggtt_offset(obj
);
419 lrc
->ring_end
= lrc
->ring_begin
+ obj
->base
.size
- 1;
420 lrc
->ring_next_free_location
= lrc
->ring_begin
;
421 lrc
->ring_current_tail_pointer_value
= 0;
423 desc
.engines_used
|= (1 << ring
->id
);
426 WARN_ON(desc
.engines_used
== 0);
429 * The CPU address is only needed at certain points, so kmap_atomic on
430 * demand instead of storing it in the ctx descriptor.
431 * XXX: May make debug easier to have it mapped
433 desc
.db_trigger_cpu
= 0;
434 desc
.db_trigger_uk
= client
->doorbell_offset
+
435 i915_gem_obj_ggtt_offset(client
->client_obj
);
436 desc
.db_trigger_phy
= client
->doorbell_offset
+
437 sg_dma_address(client
->client_obj
->pages
->sgl
);
439 desc
.process_desc
= client
->proc_desc_offset
+
440 i915_gem_obj_ggtt_offset(client
->client_obj
);
442 desc
.wq_addr
= client
->wq_offset
+
443 i915_gem_obj_ggtt_offset(client
->client_obj
);
445 desc
.wq_size
= client
->wq_size
;
448 * XXX: Take LRCs from an existing intel_context if this is not an
449 * IsKMDCreatedContext client
451 desc
.desc_private
= (uintptr_t)client
;
453 /* Pool context is pinned already */
454 sg
= guc
->ctx_pool_obj
->pages
;
455 sg_pcopy_from_buffer(sg
->sgl
, sg
->nents
, &desc
, sizeof(desc
),
456 sizeof(desc
) * client
->ctx_index
);
459 static void guc_fini_ctx_desc(struct intel_guc
*guc
,
460 struct i915_guc_client
*client
)
462 struct guc_context_desc desc
;
465 memset(&desc
, 0, sizeof(desc
));
467 sg
= guc
->ctx_pool_obj
->pages
;
468 sg_pcopy_from_buffer(sg
->sgl
, sg
->nents
, &desc
, sizeof(desc
),
469 sizeof(desc
) * client
->ctx_index
);
472 /* Get valid workqueue item and return it back to offset */
473 static int guc_get_workqueue_space(struct i915_guc_client
*gc
, u32
*offset
)
475 struct guc_process_desc
*desc
;
477 u32 size
= sizeof(struct guc_wq_item
);
478 int ret
= -ETIMEDOUT
, timeout_counter
= 200;
480 base
= kmap_atomic(i915_gem_object_get_page(gc
->client_obj
, 0));
481 desc
= base
+ gc
->proc_desc_offset
;
483 while (timeout_counter
-- > 0) {
484 if (CIRC_SPACE(gc
->wq_tail
, desc
->head
, gc
->wq_size
) >= size
) {
485 *offset
= gc
->wq_tail
;
487 /* advance the tail for next workqueue item */
489 gc
->wq_tail
&= gc
->wq_size
- 1;
491 /* this will break the loop */
497 usleep_range(1000, 2000);
505 static int guc_add_workqueue_item(struct i915_guc_client
*gc
,
506 struct drm_i915_gem_request
*rq
)
508 enum intel_ring_id ring_id
= rq
->ring
->id
;
509 struct guc_wq_item
*wqi
;
511 u32 tail
, wq_len
, wq_off
= 0;
514 ret
= guc_get_workqueue_space(gc
, &wq_off
);
518 /* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we
519 * should not have the case where structure wqi is across page, neither
520 * wrapped to the beginning. This simplifies the implementation below.
522 * XXX: if not the case, we need save data to a temp wqi and copy it to
523 * workqueue buffer dw by dw.
525 WARN_ON(sizeof(struct guc_wq_item
) != 16);
528 /* wq starts from the page after doorbell / process_desc */
529 base
= kmap_atomic(i915_gem_object_get_page(gc
->client_obj
,
530 (wq_off
+ GUC_DB_SIZE
) >> PAGE_SHIFT
));
531 wq_off
&= PAGE_SIZE
- 1;
532 wqi
= (struct guc_wq_item
*)((char *)base
+ wq_off
);
534 /* len does not include the header */
535 wq_len
= sizeof(struct guc_wq_item
) / sizeof(u32
) - 1;
536 wqi
->header
= WQ_TYPE_INORDER
|
537 (wq_len
<< WQ_LEN_SHIFT
) |
538 (ring_id
<< WQ_TARGET_SHIFT
) |
541 /* The GuC wants only the low-order word of the context descriptor */
542 wqi
->context_desc
= (u32
)intel_lr_context_descriptor(rq
->ctx
, rq
->ring
);
544 /* The GuC firmware wants the tail index in QWords, not bytes */
545 tail
= rq
->ringbuf
->tail
>> 3;
546 wqi
->ring_tail
= tail
<< WQ_RING_TAIL_SHIFT
;
547 wqi
->fence_id
= 0; /*XXX: what fence to be here */
554 #define CTX_RING_BUFFER_START 0x08
556 /* Update the ringbuffer pointer in a saved context image */
557 static void lr_context_update(struct drm_i915_gem_request
*rq
)
559 enum intel_ring_id ring_id
= rq
->ring
->id
;
560 struct drm_i915_gem_object
*ctx_obj
= rq
->ctx
->engine
[ring_id
].state
;
561 struct drm_i915_gem_object
*rb_obj
= rq
->ringbuf
->obj
;
566 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj
));
567 WARN_ON(!i915_gem_obj_is_pinned(rb_obj
));
569 page
= i915_gem_object_get_dirty_page(ctx_obj
, LRC_STATE_PN
);
570 reg_state
= kmap_atomic(page
);
572 reg_state
[CTX_RING_BUFFER_START
+1] = i915_gem_obj_ggtt_offset(rb_obj
);
574 kunmap_atomic(reg_state
);
578 * i915_guc_submit() - Submit commands through GuC
579 * @client: the guc client where commands will go through
580 * @rq: request associated with the commands
582 * Return: 0 if succeed
584 int i915_guc_submit(struct i915_guc_client
*client
,
585 struct drm_i915_gem_request
*rq
)
587 struct intel_guc
*guc
= client
->guc
;
588 enum intel_ring_id ring_id
= rq
->ring
->id
;
591 /* Need this because of the deferred pin ctx and ring */
592 /* Shall we move this right after ring is pinned? */
593 lr_context_update(rq
);
595 q_ret
= guc_add_workqueue_item(client
, rq
);
597 b_ret
= guc_ring_doorbell(client
);
599 client
->submissions
[ring_id
] += 1;
602 client
->retcode
= q_ret
;
605 client
->retcode
= q_ret
= b_ret
;
609 guc
->submissions
[ring_id
] += 1;
610 guc
->last_seqno
[ring_id
] = rq
->seqno
;
616 * Everything below here is concerned with setup & teardown, and is
617 * therefore not part of the somewhat time-critical batch-submission
618 * path of i915_guc_submit() above.
622 * gem_allocate_guc_obj() - Allocate gem object for GuC usage
624 * @size: size of object
626 * This is a wrapper to create a gem obj. In order to use it inside GuC, the
627 * object needs to be pinned lifetime. Also we must pin it to gtt space other
628 * than [0, GUC_WOPCM_TOP) because this range is reserved inside GuC.
630 * Return: A drm_i915_gem_object if successful, otherwise NULL.
632 static struct drm_i915_gem_object
*gem_allocate_guc_obj(struct drm_device
*dev
,
635 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
636 struct drm_i915_gem_object
*obj
;
638 obj
= i915_gem_alloc_object(dev
, size
);
642 if (i915_gem_object_get_pages(obj
)) {
643 drm_gem_object_unreference(&obj
->base
);
647 if (i915_gem_obj_ggtt_pin(obj
, PAGE_SIZE
,
648 PIN_OFFSET_BIAS
| GUC_WOPCM_TOP
)) {
649 drm_gem_object_unreference(&obj
->base
);
653 /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
654 I915_WRITE(GEN8_GTCR
, GEN8_GTCR_INVALIDATE
);
660 * gem_release_guc_obj() - Release gem object allocated for GuC usage
661 * @obj: gem obj to be released
663 static void gem_release_guc_obj(struct drm_i915_gem_object
*obj
)
668 if (i915_gem_obj_is_pinned(obj
))
669 i915_gem_object_ggtt_unpin(obj
);
671 drm_gem_object_unreference(&obj
->base
);
674 static void guc_client_free(struct drm_device
*dev
,
675 struct i915_guc_client
*client
)
677 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
678 struct intel_guc
*guc
= &dev_priv
->guc
;
683 if (client
->doorbell_id
!= GUC_INVALID_DOORBELL_ID
) {
685 * First disable the doorbell, then tell the GuC we've
686 * finished with it, finally deallocate it in our bitmap
688 guc_disable_doorbell(guc
, client
);
689 host2guc_release_doorbell(guc
, client
);
690 release_doorbell(guc
, client
->doorbell_id
);
694 * XXX: wait for any outstanding submissions before freeing memory.
695 * Be sure to drop any locks
698 gem_release_guc_obj(client
->client_obj
);
700 if (client
->ctx_index
!= GUC_INVALID_CTX_ID
) {
701 guc_fini_ctx_desc(guc
, client
);
702 ida_simple_remove(&guc
->ctx_ids
, client
->ctx_index
);
709 * guc_client_alloc() - Allocate an i915_guc_client
711 * @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW
712 * The kernel client to replace ExecList submission is created with
713 * NORMAL priority. Priority of a client for scheduler can be HIGH,
714 * while a preemption context can use CRITICAL.
715 * @ctx: the context that owns the client (we use the default render
718 * Return: An i915_guc_client object if success.
720 static struct i915_guc_client
*guc_client_alloc(struct drm_device
*dev
,
722 struct intel_context
*ctx
)
724 struct i915_guc_client
*client
;
725 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
726 struct intel_guc
*guc
= &dev_priv
->guc
;
727 struct drm_i915_gem_object
*obj
;
729 client
= kzalloc(sizeof(*client
), GFP_KERNEL
);
733 client
->doorbell_id
= GUC_INVALID_DOORBELL_ID
;
734 client
->priority
= priority
;
738 client
->ctx_index
= (uint32_t)ida_simple_get(&guc
->ctx_ids
, 0,
739 GUC_MAX_GPU_CONTEXTS
, GFP_KERNEL
);
740 if (client
->ctx_index
>= GUC_MAX_GPU_CONTEXTS
) {
741 client
->ctx_index
= GUC_INVALID_CTX_ID
;
745 /* The first page is doorbell/proc_desc. Two followed pages are wq. */
746 obj
= gem_allocate_guc_obj(dev
, GUC_DB_SIZE
+ GUC_WQ_SIZE
);
750 client
->client_obj
= obj
;
751 client
->wq_offset
= GUC_DB_SIZE
;
752 client
->wq_size
= GUC_WQ_SIZE
;
754 client
->doorbell_offset
= select_doorbell_cacheline(guc
);
757 * Since the doorbell only requires a single cacheline, we can save
758 * space by putting the application process descriptor in the same
759 * page. Use the half of the page that doesn't include the doorbell.
761 if (client
->doorbell_offset
>= (GUC_DB_SIZE
/ 2))
762 client
->proc_desc_offset
= 0;
764 client
->proc_desc_offset
= (GUC_DB_SIZE
/ 2);
766 client
->doorbell_id
= assign_doorbell(guc
, client
->priority
);
767 if (client
->doorbell_id
== GUC_INVALID_DOORBELL_ID
)
768 /* XXX: evict a doorbell instead */
771 guc_init_proc_desc(guc
, client
);
772 guc_init_ctx_desc(guc
, client
);
773 guc_init_doorbell(guc
, client
);
775 /* XXX: Any cache flushes needed? General domain mgmt calls? */
777 if (host2guc_allocate_doorbell(guc
, client
))
780 DRM_DEBUG_DRIVER("new priority %u client %p: ctx_index %u db_id %u\n",
781 priority
, client
, client
->ctx_index
, client
->doorbell_id
);
786 DRM_ERROR("FAILED to create priority %u GuC client!\n", priority
);
788 guc_client_free(dev
, client
);
792 static void guc_create_log(struct intel_guc
*guc
)
794 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
795 struct drm_i915_gem_object
*obj
;
796 unsigned long offset
;
797 uint32_t size
, flags
;
799 if (i915
.guc_log_level
< GUC_LOG_VERBOSITY_MIN
)
802 if (i915
.guc_log_level
> GUC_LOG_VERBOSITY_MAX
)
803 i915
.guc_log_level
= GUC_LOG_VERBOSITY_MAX
;
805 /* The first page is to save log buffer state. Allocate one
806 * extra page for others in case for overlap */
807 size
= (1 + GUC_LOG_DPC_PAGES
+ 1 +
808 GUC_LOG_ISR_PAGES
+ 1 +
809 GUC_LOG_CRASH_PAGES
+ 1) << PAGE_SHIFT
;
813 obj
= gem_allocate_guc_obj(dev_priv
->dev
, size
);
815 /* logging will be off */
816 i915
.guc_log_level
= -1;
823 /* each allocated unit is a page */
824 flags
= GUC_LOG_VALID
| GUC_LOG_NOTIFY_ON_HALF_FULL
|
825 (GUC_LOG_DPC_PAGES
<< GUC_LOG_DPC_SHIFT
) |
826 (GUC_LOG_ISR_PAGES
<< GUC_LOG_ISR_SHIFT
) |
827 (GUC_LOG_CRASH_PAGES
<< GUC_LOG_CRASH_SHIFT
);
829 offset
= i915_gem_obj_ggtt_offset(obj
) >> PAGE_SHIFT
; /* in pages */
830 guc
->log_flags
= (offset
<< GUC_LOG_BUF_ADDR_SHIFT
) | flags
;
834 * Set up the memory resources to be shared with the GuC. At this point,
835 * we require just one object that can be mapped through the GGTT.
837 int i915_guc_submission_init(struct drm_device
*dev
)
839 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
840 const size_t ctxsize
= sizeof(struct guc_context_desc
);
841 const size_t poolsize
= GUC_MAX_GPU_CONTEXTS
* ctxsize
;
842 const size_t gemsize
= round_up(poolsize
, PAGE_SIZE
);
843 struct intel_guc
*guc
= &dev_priv
->guc
;
845 if (!i915
.enable_guc_submission
)
846 return 0; /* not enabled */
848 if (guc
->ctx_pool_obj
)
849 return 0; /* already allocated */
851 guc
->ctx_pool_obj
= gem_allocate_guc_obj(dev_priv
->dev
, gemsize
);
852 if (!guc
->ctx_pool_obj
)
855 ida_init(&guc
->ctx_ids
);
862 int i915_guc_submission_enable(struct drm_device
*dev
)
864 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
865 struct intel_guc
*guc
= &dev_priv
->guc
;
866 struct intel_context
*ctx
= dev_priv
->ring
[RCS
].default_context
;
867 struct i915_guc_client
*client
;
869 /* client for execbuf submission */
870 client
= guc_client_alloc(dev
, GUC_CTX_PRIORITY_KMD_NORMAL
, ctx
);
872 DRM_ERROR("Failed to create execbuf guc_client\n");
876 guc
->execbuf_client
= client
;
878 host2guc_sample_forcewake(guc
, client
);
883 void i915_guc_submission_disable(struct drm_device
*dev
)
885 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
886 struct intel_guc
*guc
= &dev_priv
->guc
;
888 guc_client_free(dev
, guc
->execbuf_client
);
889 guc
->execbuf_client
= NULL
;
892 void i915_guc_submission_fini(struct drm_device
*dev
)
894 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
895 struct intel_guc
*guc
= &dev_priv
->guc
;
897 gem_release_guc_obj(dev_priv
->guc
.log_obj
);
900 if (guc
->ctx_pool_obj
)
901 ida_destroy(&guc
->ctx_ids
);
902 gem_release_guc_obj(guc
->ctx_pool_obj
);
903 guc
->ctx_pool_obj
= NULL
;
907 * intel_guc_suspend() - notify GuC entering suspend state
910 int intel_guc_suspend(struct drm_device
*dev
)
912 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
913 struct intel_guc
*guc
= &dev_priv
->guc
;
914 struct intel_context
*ctx
;
917 if (!i915
.enable_guc_submission
)
920 ctx
= dev_priv
->ring
[RCS
].default_context
;
922 data
[0] = HOST2GUC_ACTION_ENTER_S_STATE
;
923 /* any value greater than GUC_POWER_D0 */
924 data
[1] = GUC_POWER_D1
;
925 /* first page is shared data with GuC */
926 data
[2] = i915_gem_obj_ggtt_offset(ctx
->engine
[RCS
].state
);
928 return host2guc_action(guc
, data
, ARRAY_SIZE(data
));
933 * intel_guc_resume() - notify GuC resuming from suspend state
936 int intel_guc_resume(struct drm_device
*dev
)
938 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
939 struct intel_guc
*guc
= &dev_priv
->guc
;
940 struct intel_context
*ctx
;
943 if (!i915
.enable_guc_submission
)
946 ctx
= dev_priv
->ring
[RCS
].default_context
;
948 data
[0] = HOST2GUC_ACTION_EXIT_S_STATE
;
949 data
[1] = GUC_POWER_D0
;
950 /* first page is shared data with GuC */
951 data
[2] = i915_gem_obj_ggtt_offset(ctx
->engine
[RCS
].state
);
953 return host2guc_action(guc
, data
, ARRAY_SIZE(data
));