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drm/i915: track ring progression using seqnos
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <drm/drmP.h>
34 #include <drm/i915_drm.h>
35 #include "i915_drv.h"
36 #include "i915_trace.h"
37 #include "intel_drv.h"
38
39 static const u32 hpd_ibx[] = {
40 [HPD_CRT] = SDE_CRT_HOTPLUG,
41 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
42 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
43 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
44 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
45 };
46
47 static const u32 hpd_cpt[] = {
48 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
49 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
50 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
51 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
52 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
53 };
54
55 static const u32 hpd_mask_i915[] = {
56 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
57 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
58 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
59 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
60 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
61 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
62 };
63
64 static const u32 hpd_status_gen4[] = {
65 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
66 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
67 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
68 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
69 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
70 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
71 };
72
73 static const u32 hpd_status_i965[] = {
74 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
75 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I965,
76 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I965,
77 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
78 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
79 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
80 };
81
82 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
83 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
84 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
85 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
86 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
87 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
88 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
89 };
90
91 static void ibx_hpd_irq_setup(struct drm_device *dev);
92 static void i915_hpd_irq_setup(struct drm_device *dev);
93
94 /* For display hotplug interrupt */
95 static void
96 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
97 {
98 if ((dev_priv->irq_mask & mask) != 0) {
99 dev_priv->irq_mask &= ~mask;
100 I915_WRITE(DEIMR, dev_priv->irq_mask);
101 POSTING_READ(DEIMR);
102 }
103 }
104
105 static void
106 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
107 {
108 if ((dev_priv->irq_mask & mask) != mask) {
109 dev_priv->irq_mask |= mask;
110 I915_WRITE(DEIMR, dev_priv->irq_mask);
111 POSTING_READ(DEIMR);
112 }
113 }
114
115 static bool ivb_can_enable_err_int(struct drm_device *dev)
116 {
117 struct drm_i915_private *dev_priv = dev->dev_private;
118 struct intel_crtc *crtc;
119 enum pipe pipe;
120
121 for_each_pipe(pipe) {
122 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
123
124 if (crtc->cpu_fifo_underrun_disabled)
125 return false;
126 }
127
128 return true;
129 }
130
131 static bool cpt_can_enable_serr_int(struct drm_device *dev)
132 {
133 struct drm_i915_private *dev_priv = dev->dev_private;
134 enum pipe pipe;
135 struct intel_crtc *crtc;
136
137 for_each_pipe(pipe) {
138 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
139
140 if (crtc->pch_fifo_underrun_disabled)
141 return false;
142 }
143
144 return true;
145 }
146
147 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
148 enum pipe pipe, bool enable)
149 {
150 struct drm_i915_private *dev_priv = dev->dev_private;
151 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
152 DE_PIPEB_FIFO_UNDERRUN;
153
154 if (enable)
155 ironlake_enable_display_irq(dev_priv, bit);
156 else
157 ironlake_disable_display_irq(dev_priv, bit);
158 }
159
160 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
161 bool enable)
162 {
163 struct drm_i915_private *dev_priv = dev->dev_private;
164
165 if (enable) {
166 if (!ivb_can_enable_err_int(dev))
167 return;
168
169 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN_A |
170 ERR_INT_FIFO_UNDERRUN_B |
171 ERR_INT_FIFO_UNDERRUN_C);
172
173 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
174 } else {
175 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
176 }
177 }
178
179 static void ibx_set_fifo_underrun_reporting(struct intel_crtc *crtc,
180 bool enable)
181 {
182 struct drm_device *dev = crtc->base.dev;
183 struct drm_i915_private *dev_priv = dev->dev_private;
184 uint32_t bit = (crtc->pipe == PIPE_A) ? SDE_TRANSA_FIFO_UNDER :
185 SDE_TRANSB_FIFO_UNDER;
186
187 if (enable)
188 I915_WRITE(SDEIMR, I915_READ(SDEIMR) & ~bit);
189 else
190 I915_WRITE(SDEIMR, I915_READ(SDEIMR) | bit);
191
192 POSTING_READ(SDEIMR);
193 }
194
195 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
196 enum transcoder pch_transcoder,
197 bool enable)
198 {
199 struct drm_i915_private *dev_priv = dev->dev_private;
200
201 if (enable) {
202 if (!cpt_can_enable_serr_int(dev))
203 return;
204
205 I915_WRITE(SERR_INT, SERR_INT_TRANS_A_FIFO_UNDERRUN |
206 SERR_INT_TRANS_B_FIFO_UNDERRUN |
207 SERR_INT_TRANS_C_FIFO_UNDERRUN);
208
209 I915_WRITE(SDEIMR, I915_READ(SDEIMR) & ~SDE_ERROR_CPT);
210 } else {
211 I915_WRITE(SDEIMR, I915_READ(SDEIMR) | SDE_ERROR_CPT);
212 }
213
214 POSTING_READ(SDEIMR);
215 }
216
217 /**
218 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
219 * @dev: drm device
220 * @pipe: pipe
221 * @enable: true if we want to report FIFO underrun errors, false otherwise
222 *
223 * This function makes us disable or enable CPU fifo underruns for a specific
224 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
225 * reporting for one pipe may also disable all the other CPU error interruts for
226 * the other pipes, due to the fact that there's just one interrupt mask/enable
227 * bit for all the pipes.
228 *
229 * Returns the previous state of underrun reporting.
230 */
231 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
232 enum pipe pipe, bool enable)
233 {
234 struct drm_i915_private *dev_priv = dev->dev_private;
235 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
236 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
237 unsigned long flags;
238 bool ret;
239
240 spin_lock_irqsave(&dev_priv->irq_lock, flags);
241
242 ret = !intel_crtc->cpu_fifo_underrun_disabled;
243
244 if (enable == ret)
245 goto done;
246
247 intel_crtc->cpu_fifo_underrun_disabled = !enable;
248
249 if (IS_GEN5(dev) || IS_GEN6(dev))
250 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
251 else if (IS_GEN7(dev))
252 ivybridge_set_fifo_underrun_reporting(dev, enable);
253
254 done:
255 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
256 return ret;
257 }
258
259 /**
260 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
261 * @dev: drm device
262 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
263 * @enable: true if we want to report FIFO underrun errors, false otherwise
264 *
265 * This function makes us disable or enable PCH fifo underruns for a specific
266 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
267 * underrun reporting for one transcoder may also disable all the other PCH
268 * error interruts for the other transcoders, due to the fact that there's just
269 * one interrupt mask/enable bit for all the transcoders.
270 *
271 * Returns the previous state of underrun reporting.
272 */
273 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
274 enum transcoder pch_transcoder,
275 bool enable)
276 {
277 struct drm_i915_private *dev_priv = dev->dev_private;
278 enum pipe p;
279 struct drm_crtc *crtc;
280 struct intel_crtc *intel_crtc;
281 unsigned long flags;
282 bool ret;
283
284 if (HAS_PCH_LPT(dev)) {
285 crtc = NULL;
286 for_each_pipe(p) {
287 struct drm_crtc *c = dev_priv->pipe_to_crtc_mapping[p];
288 if (intel_pipe_has_type(c, INTEL_OUTPUT_ANALOG)) {
289 crtc = c;
290 break;
291 }
292 }
293 if (!crtc) {
294 DRM_ERROR("PCH FIFO underrun, but no CRTC using the PCH found\n");
295 return false;
296 }
297 } else {
298 crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
299 }
300 intel_crtc = to_intel_crtc(crtc);
301
302 spin_lock_irqsave(&dev_priv->irq_lock, flags);
303
304 ret = !intel_crtc->pch_fifo_underrun_disabled;
305
306 if (enable == ret)
307 goto done;
308
309 intel_crtc->pch_fifo_underrun_disabled = !enable;
310
311 if (HAS_PCH_IBX(dev))
312 ibx_set_fifo_underrun_reporting(intel_crtc, enable);
313 else
314 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
315
316 done:
317 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
318 return ret;
319 }
320
321
322 void
323 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
324 {
325 u32 reg = PIPESTAT(pipe);
326 u32 pipestat = I915_READ(reg) & 0x7fff0000;
327
328 if ((pipestat & mask) == mask)
329 return;
330
331 /* Enable the interrupt, clear any pending status */
332 pipestat |= mask | (mask >> 16);
333 I915_WRITE(reg, pipestat);
334 POSTING_READ(reg);
335 }
336
337 void
338 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
339 {
340 u32 reg = PIPESTAT(pipe);
341 u32 pipestat = I915_READ(reg) & 0x7fff0000;
342
343 if ((pipestat & mask) == 0)
344 return;
345
346 pipestat &= ~mask;
347 I915_WRITE(reg, pipestat);
348 POSTING_READ(reg);
349 }
350
351 /**
352 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
353 */
354 static void i915_enable_asle_pipestat(struct drm_device *dev)
355 {
356 drm_i915_private_t *dev_priv = dev->dev_private;
357 unsigned long irqflags;
358
359 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
360 return;
361
362 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
363
364 i915_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE);
365 if (INTEL_INFO(dev)->gen >= 4)
366 i915_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE);
367
368 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
369 }
370
371 /**
372 * i915_pipe_enabled - check if a pipe is enabled
373 * @dev: DRM device
374 * @pipe: pipe to check
375 *
376 * Reading certain registers when the pipe is disabled can hang the chip.
377 * Use this routine to make sure the PLL is running and the pipe is active
378 * before reading such registers if unsure.
379 */
380 static int
381 i915_pipe_enabled(struct drm_device *dev, int pipe)
382 {
383 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
384 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
385 pipe);
386
387 if (!intel_display_power_enabled(dev,
388 POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
389 return false;
390
391 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
392 }
393
394 /* Called from drm generic code, passed a 'crtc', which
395 * we use as a pipe index
396 */
397 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
398 {
399 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
400 unsigned long high_frame;
401 unsigned long low_frame;
402 u32 high1, high2, low;
403
404 if (!i915_pipe_enabled(dev, pipe)) {
405 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
406 "pipe %c\n", pipe_name(pipe));
407 return 0;
408 }
409
410 high_frame = PIPEFRAME(pipe);
411 low_frame = PIPEFRAMEPIXEL(pipe);
412
413 /*
414 * High & low register fields aren't synchronized, so make sure
415 * we get a low value that's stable across two reads of the high
416 * register.
417 */
418 do {
419 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
420 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
421 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
422 } while (high1 != high2);
423
424 high1 >>= PIPE_FRAME_HIGH_SHIFT;
425 low >>= PIPE_FRAME_LOW_SHIFT;
426 return (high1 << 8) | low;
427 }
428
429 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
430 {
431 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
432 int reg = PIPE_FRMCOUNT_GM45(pipe);
433
434 if (!i915_pipe_enabled(dev, pipe)) {
435 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
436 "pipe %c\n", pipe_name(pipe));
437 return 0;
438 }
439
440 return I915_READ(reg);
441 }
442
443 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
444 int *vpos, int *hpos)
445 {
446 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
447 u32 vbl = 0, position = 0;
448 int vbl_start, vbl_end, htotal, vtotal;
449 bool in_vbl = true;
450 int ret = 0;
451 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
452 pipe);
453
454 if (!i915_pipe_enabled(dev, pipe)) {
455 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
456 "pipe %c\n", pipe_name(pipe));
457 return 0;
458 }
459
460 /* Get vtotal. */
461 vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
462
463 if (INTEL_INFO(dev)->gen >= 4) {
464 /* No obvious pixelcount register. Only query vertical
465 * scanout position from Display scan line register.
466 */
467 position = I915_READ(PIPEDSL(pipe));
468
469 /* Decode into vertical scanout position. Don't have
470 * horizontal scanout position.
471 */
472 *vpos = position & 0x1fff;
473 *hpos = 0;
474 } else {
475 /* Have access to pixelcount since start of frame.
476 * We can split this into vertical and horizontal
477 * scanout position.
478 */
479 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
480
481 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
482 *vpos = position / htotal;
483 *hpos = position - (*vpos * htotal);
484 }
485
486 /* Query vblank area. */
487 vbl = I915_READ(VBLANK(cpu_transcoder));
488
489 /* Test position against vblank region. */
490 vbl_start = vbl & 0x1fff;
491 vbl_end = (vbl >> 16) & 0x1fff;
492
493 if ((*vpos < vbl_start) || (*vpos > vbl_end))
494 in_vbl = false;
495
496 /* Inside "upper part" of vblank area? Apply corrective offset: */
497 if (in_vbl && (*vpos >= vbl_start))
498 *vpos = *vpos - vtotal;
499
500 /* Readouts valid? */
501 if (vbl > 0)
502 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
503
504 /* In vblank? */
505 if (in_vbl)
506 ret |= DRM_SCANOUTPOS_INVBL;
507
508 return ret;
509 }
510
511 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
512 int *max_error,
513 struct timeval *vblank_time,
514 unsigned flags)
515 {
516 struct drm_crtc *crtc;
517
518 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
519 DRM_ERROR("Invalid crtc %d\n", pipe);
520 return -EINVAL;
521 }
522
523 /* Get drm_crtc to timestamp: */
524 crtc = intel_get_crtc_for_pipe(dev, pipe);
525 if (crtc == NULL) {
526 DRM_ERROR("Invalid crtc %d\n", pipe);
527 return -EINVAL;
528 }
529
530 if (!crtc->enabled) {
531 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
532 return -EBUSY;
533 }
534
535 /* Helper routine in DRM core does all the work: */
536 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
537 vblank_time, flags,
538 crtc);
539 }
540
541 static int intel_hpd_irq_event(struct drm_device *dev, struct drm_connector *connector)
542 {
543 enum drm_connector_status old_status;
544
545 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
546 old_status = connector->status;
547
548 connector->status = connector->funcs->detect(connector, false);
549 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
550 connector->base.id,
551 drm_get_connector_name(connector),
552 old_status, connector->status);
553 return (old_status != connector->status);
554 }
555
556 /*
557 * Handle hotplug events outside the interrupt handler proper.
558 */
559 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
560
561 static void i915_hotplug_work_func(struct work_struct *work)
562 {
563 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
564 hotplug_work);
565 struct drm_device *dev = dev_priv->dev;
566 struct drm_mode_config *mode_config = &dev->mode_config;
567 struct intel_connector *intel_connector;
568 struct intel_encoder *intel_encoder;
569 struct drm_connector *connector;
570 unsigned long irqflags;
571 bool hpd_disabled = false;
572 bool changed = false;
573 u32 hpd_event_bits;
574
575 /* HPD irq before everything is fully set up. */
576 if (!dev_priv->enable_hotplug_processing)
577 return;
578
579 mutex_lock(&mode_config->mutex);
580 DRM_DEBUG_KMS("running encoder hotplug functions\n");
581
582 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
583
584 hpd_event_bits = dev_priv->hpd_event_bits;
585 dev_priv->hpd_event_bits = 0;
586 list_for_each_entry(connector, &mode_config->connector_list, head) {
587 intel_connector = to_intel_connector(connector);
588 intel_encoder = intel_connector->encoder;
589 if (intel_encoder->hpd_pin > HPD_NONE &&
590 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
591 connector->polled == DRM_CONNECTOR_POLL_HPD) {
592 DRM_INFO("HPD interrupt storm detected on connector %s: "
593 "switching from hotplug detection to polling\n",
594 drm_get_connector_name(connector));
595 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
596 connector->polled = DRM_CONNECTOR_POLL_CONNECT
597 | DRM_CONNECTOR_POLL_DISCONNECT;
598 hpd_disabled = true;
599 }
600 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
601 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
602 drm_get_connector_name(connector), intel_encoder->hpd_pin);
603 }
604 }
605 /* if there were no outputs to poll, poll was disabled,
606 * therefore make sure it's enabled when disabling HPD on
607 * some connectors */
608 if (hpd_disabled) {
609 drm_kms_helper_poll_enable(dev);
610 mod_timer(&dev_priv->hotplug_reenable_timer,
611 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
612 }
613
614 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
615
616 list_for_each_entry(connector, &mode_config->connector_list, head) {
617 intel_connector = to_intel_connector(connector);
618 intel_encoder = intel_connector->encoder;
619 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
620 if (intel_encoder->hot_plug)
621 intel_encoder->hot_plug(intel_encoder);
622 if (intel_hpd_irq_event(dev, connector))
623 changed = true;
624 }
625 }
626 mutex_unlock(&mode_config->mutex);
627
628 if (changed)
629 drm_kms_helper_hotplug_event(dev);
630 }
631
632 static void ironlake_handle_rps_change(struct drm_device *dev)
633 {
634 drm_i915_private_t *dev_priv = dev->dev_private;
635 u32 busy_up, busy_down, max_avg, min_avg;
636 u8 new_delay;
637 unsigned long flags;
638
639 spin_lock_irqsave(&mchdev_lock, flags);
640
641 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
642
643 new_delay = dev_priv->ips.cur_delay;
644
645 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
646 busy_up = I915_READ(RCPREVBSYTUPAVG);
647 busy_down = I915_READ(RCPREVBSYTDNAVG);
648 max_avg = I915_READ(RCBMAXAVG);
649 min_avg = I915_READ(RCBMINAVG);
650
651 /* Handle RCS change request from hw */
652 if (busy_up > max_avg) {
653 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
654 new_delay = dev_priv->ips.cur_delay - 1;
655 if (new_delay < dev_priv->ips.max_delay)
656 new_delay = dev_priv->ips.max_delay;
657 } else if (busy_down < min_avg) {
658 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
659 new_delay = dev_priv->ips.cur_delay + 1;
660 if (new_delay > dev_priv->ips.min_delay)
661 new_delay = dev_priv->ips.min_delay;
662 }
663
664 if (ironlake_set_drps(dev, new_delay))
665 dev_priv->ips.cur_delay = new_delay;
666
667 spin_unlock_irqrestore(&mchdev_lock, flags);
668
669 return;
670 }
671
672 static void notify_ring(struct drm_device *dev,
673 struct intel_ring_buffer *ring)
674 {
675 struct drm_i915_private *dev_priv = dev->dev_private;
676
677 if (ring->obj == NULL)
678 return;
679
680 trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
681
682 wake_up_all(&ring->irq_queue);
683 if (i915_enable_hangcheck) {
684 dev_priv->gpu_error.hangcheck_count = 0;
685 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
686 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
687 }
688 }
689
690 static void gen6_pm_rps_work(struct work_struct *work)
691 {
692 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
693 rps.work);
694 u32 pm_iir, pm_imr;
695 u8 new_delay;
696
697 spin_lock_irq(&dev_priv->rps.lock);
698 pm_iir = dev_priv->rps.pm_iir;
699 dev_priv->rps.pm_iir = 0;
700 pm_imr = I915_READ(GEN6_PMIMR);
701 I915_WRITE(GEN6_PMIMR, 0);
702 spin_unlock_irq(&dev_priv->rps.lock);
703
704 if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
705 return;
706
707 mutex_lock(&dev_priv->rps.hw_lock);
708
709 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
710 new_delay = dev_priv->rps.cur_delay + 1;
711 else
712 new_delay = dev_priv->rps.cur_delay - 1;
713
714 /* sysfs frequency interfaces may have snuck in while servicing the
715 * interrupt
716 */
717 if (!(new_delay > dev_priv->rps.max_delay ||
718 new_delay < dev_priv->rps.min_delay)) {
719 if (IS_VALLEYVIEW(dev_priv->dev))
720 valleyview_set_rps(dev_priv->dev, new_delay);
721 else
722 gen6_set_rps(dev_priv->dev, new_delay);
723 }
724
725 if (IS_VALLEYVIEW(dev_priv->dev)) {
726 /*
727 * On VLV, when we enter RC6 we may not be at the minimum
728 * voltage level, so arm a timer to check. It should only
729 * fire when there's activity or once after we've entered
730 * RC6, and then won't be re-armed until the next RPS interrupt.
731 */
732 mod_delayed_work(dev_priv->wq, &dev_priv->rps.vlv_work,
733 msecs_to_jiffies(100));
734 }
735
736 mutex_unlock(&dev_priv->rps.hw_lock);
737 }
738
739
740 /**
741 * ivybridge_parity_work - Workqueue called when a parity error interrupt
742 * occurred.
743 * @work: workqueue struct
744 *
745 * Doesn't actually do anything except notify userspace. As a consequence of
746 * this event, userspace should try to remap the bad rows since statistically
747 * it is likely the same row is more likely to go bad again.
748 */
749 static void ivybridge_parity_work(struct work_struct *work)
750 {
751 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
752 l3_parity.error_work);
753 u32 error_status, row, bank, subbank;
754 char *parity_event[5];
755 uint32_t misccpctl;
756 unsigned long flags;
757
758 /* We must turn off DOP level clock gating to access the L3 registers.
759 * In order to prevent a get/put style interface, acquire struct mutex
760 * any time we access those registers.
761 */
762 mutex_lock(&dev_priv->dev->struct_mutex);
763
764 misccpctl = I915_READ(GEN7_MISCCPCTL);
765 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
766 POSTING_READ(GEN7_MISCCPCTL);
767
768 error_status = I915_READ(GEN7_L3CDERRST1);
769 row = GEN7_PARITY_ERROR_ROW(error_status);
770 bank = GEN7_PARITY_ERROR_BANK(error_status);
771 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
772
773 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
774 GEN7_L3CDERRST1_ENABLE);
775 POSTING_READ(GEN7_L3CDERRST1);
776
777 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
778
779 spin_lock_irqsave(&dev_priv->irq_lock, flags);
780 dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
781 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
782 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
783
784 mutex_unlock(&dev_priv->dev->struct_mutex);
785
786 parity_event[0] = "L3_PARITY_ERROR=1";
787 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
788 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
789 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
790 parity_event[4] = NULL;
791
792 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
793 KOBJ_CHANGE, parity_event);
794
795 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
796 row, bank, subbank);
797
798 kfree(parity_event[3]);
799 kfree(parity_event[2]);
800 kfree(parity_event[1]);
801 }
802
803 static void ivybridge_handle_parity_error(struct drm_device *dev)
804 {
805 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
806 unsigned long flags;
807
808 if (!HAS_L3_GPU_CACHE(dev))
809 return;
810
811 spin_lock_irqsave(&dev_priv->irq_lock, flags);
812 dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
813 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
814 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
815
816 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
817 }
818
819 static void snb_gt_irq_handler(struct drm_device *dev,
820 struct drm_i915_private *dev_priv,
821 u32 gt_iir)
822 {
823
824 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
825 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
826 notify_ring(dev, &dev_priv->ring[RCS]);
827 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
828 notify_ring(dev, &dev_priv->ring[VCS]);
829 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
830 notify_ring(dev, &dev_priv->ring[BCS]);
831
832 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
833 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
834 GT_RENDER_CS_ERROR_INTERRUPT)) {
835 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
836 i915_handle_error(dev, false);
837 }
838
839 if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
840 ivybridge_handle_parity_error(dev);
841 }
842
843 static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
844 u32 pm_iir)
845 {
846 unsigned long flags;
847
848 /*
849 * IIR bits should never already be set because IMR should
850 * prevent an interrupt from being shown in IIR. The warning
851 * displays a case where we've unsafely cleared
852 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
853 * type is not a problem, it displays a problem in the logic.
854 *
855 * The mask bit in IMR is cleared by dev_priv->rps.work.
856 */
857
858 spin_lock_irqsave(&dev_priv->rps.lock, flags);
859 dev_priv->rps.pm_iir |= pm_iir;
860 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
861 POSTING_READ(GEN6_PMIMR);
862 spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
863
864 queue_work(dev_priv->wq, &dev_priv->rps.work);
865 }
866
867 #define HPD_STORM_DETECT_PERIOD 1000
868 #define HPD_STORM_THRESHOLD 5
869
870 static inline bool hotplug_irq_storm_detect(struct drm_device *dev,
871 u32 hotplug_trigger,
872 const u32 *hpd)
873 {
874 drm_i915_private_t *dev_priv = dev->dev_private;
875 unsigned long irqflags;
876 int i;
877 bool ret = false;
878
879 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
880
881 for (i = 1; i < HPD_NUM_PINS; i++) {
882
883 if (!(hpd[i] & hotplug_trigger) ||
884 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
885 continue;
886
887 dev_priv->hpd_event_bits |= (1 << i);
888 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
889 dev_priv->hpd_stats[i].hpd_last_jiffies
890 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
891 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
892 dev_priv->hpd_stats[i].hpd_cnt = 0;
893 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
894 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
895 dev_priv->hpd_event_bits &= ~(1 << i);
896 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
897 ret = true;
898 } else {
899 dev_priv->hpd_stats[i].hpd_cnt++;
900 }
901 }
902
903 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
904
905 return ret;
906 }
907
908 static void gmbus_irq_handler(struct drm_device *dev)
909 {
910 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
911
912 wake_up_all(&dev_priv->gmbus_wait_queue);
913 }
914
915 static void dp_aux_irq_handler(struct drm_device *dev)
916 {
917 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
918
919 wake_up_all(&dev_priv->gmbus_wait_queue);
920 }
921
922 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
923 {
924 struct drm_device *dev = (struct drm_device *) arg;
925 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
926 u32 iir, gt_iir, pm_iir;
927 irqreturn_t ret = IRQ_NONE;
928 unsigned long irqflags;
929 int pipe;
930 u32 pipe_stats[I915_MAX_PIPES];
931
932 atomic_inc(&dev_priv->irq_received);
933
934 while (true) {
935 iir = I915_READ(VLV_IIR);
936 gt_iir = I915_READ(GTIIR);
937 pm_iir = I915_READ(GEN6_PMIIR);
938
939 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
940 goto out;
941
942 ret = IRQ_HANDLED;
943
944 snb_gt_irq_handler(dev, dev_priv, gt_iir);
945
946 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
947 for_each_pipe(pipe) {
948 int reg = PIPESTAT(pipe);
949 pipe_stats[pipe] = I915_READ(reg);
950
951 /*
952 * Clear the PIPE*STAT regs before the IIR
953 */
954 if (pipe_stats[pipe] & 0x8000ffff) {
955 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
956 DRM_DEBUG_DRIVER("pipe %c underrun\n",
957 pipe_name(pipe));
958 I915_WRITE(reg, pipe_stats[pipe]);
959 }
960 }
961 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
962
963 for_each_pipe(pipe) {
964 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
965 drm_handle_vblank(dev, pipe);
966
967 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
968 intel_prepare_page_flip(dev, pipe);
969 intel_finish_page_flip(dev, pipe);
970 }
971 }
972
973 /* Consume port. Then clear IIR or we'll miss events */
974 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
975 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
976 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
977
978 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
979 hotplug_status);
980 if (hotplug_trigger) {
981 if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_status_i915))
982 i915_hpd_irq_setup(dev);
983 queue_work(dev_priv->wq,
984 &dev_priv->hotplug_work);
985 }
986 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
987 I915_READ(PORT_HOTPLUG_STAT);
988 }
989
990 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
991 gmbus_irq_handler(dev);
992
993 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
994 gen6_queue_rps_work(dev_priv, pm_iir);
995
996 I915_WRITE(GTIIR, gt_iir);
997 I915_WRITE(GEN6_PMIIR, pm_iir);
998 I915_WRITE(VLV_IIR, iir);
999 }
1000
1001 out:
1002 return ret;
1003 }
1004
1005 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1006 {
1007 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1008 int pipe;
1009 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1010
1011 if (hotplug_trigger) {
1012 if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_ibx))
1013 ibx_hpd_irq_setup(dev);
1014 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
1015 }
1016 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1017 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1018 SDE_AUDIO_POWER_SHIFT);
1019 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1020 port_name(port));
1021 }
1022
1023 if (pch_iir & SDE_AUX_MASK)
1024 dp_aux_irq_handler(dev);
1025
1026 if (pch_iir & SDE_GMBUS)
1027 gmbus_irq_handler(dev);
1028
1029 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1030 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1031
1032 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1033 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1034
1035 if (pch_iir & SDE_POISON)
1036 DRM_ERROR("PCH poison interrupt\n");
1037
1038 if (pch_iir & SDE_FDI_MASK)
1039 for_each_pipe(pipe)
1040 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1041 pipe_name(pipe),
1042 I915_READ(FDI_RX_IIR(pipe)));
1043
1044 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1045 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1046
1047 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1048 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1049
1050 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1051 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1052 false))
1053 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1054
1055 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1056 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1057 false))
1058 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1059 }
1060
1061 static void ivb_err_int_handler(struct drm_device *dev)
1062 {
1063 struct drm_i915_private *dev_priv = dev->dev_private;
1064 u32 err_int = I915_READ(GEN7_ERR_INT);
1065
1066 if (err_int & ERR_INT_POISON)
1067 DRM_ERROR("Poison interrupt\n");
1068
1069 if (err_int & ERR_INT_FIFO_UNDERRUN_A)
1070 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1071 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1072
1073 if (err_int & ERR_INT_FIFO_UNDERRUN_B)
1074 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1075 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1076
1077 if (err_int & ERR_INT_FIFO_UNDERRUN_C)
1078 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false))
1079 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1080
1081 I915_WRITE(GEN7_ERR_INT, err_int);
1082 }
1083
1084 static void cpt_serr_int_handler(struct drm_device *dev)
1085 {
1086 struct drm_i915_private *dev_priv = dev->dev_private;
1087 u32 serr_int = I915_READ(SERR_INT);
1088
1089 if (serr_int & SERR_INT_POISON)
1090 DRM_ERROR("PCH poison interrupt\n");
1091
1092 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1093 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1094 false))
1095 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1096
1097 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1098 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1099 false))
1100 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1101
1102 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1103 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1104 false))
1105 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1106
1107 I915_WRITE(SERR_INT, serr_int);
1108 }
1109
1110 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1111 {
1112 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1113 int pipe;
1114 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1115
1116 if (hotplug_trigger) {
1117 if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_cpt))
1118 ibx_hpd_irq_setup(dev);
1119 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
1120 }
1121 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1122 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1123 SDE_AUDIO_POWER_SHIFT_CPT);
1124 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1125 port_name(port));
1126 }
1127
1128 if (pch_iir & SDE_AUX_MASK_CPT)
1129 dp_aux_irq_handler(dev);
1130
1131 if (pch_iir & SDE_GMBUS_CPT)
1132 gmbus_irq_handler(dev);
1133
1134 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1135 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1136
1137 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1138 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1139
1140 if (pch_iir & SDE_FDI_MASK_CPT)
1141 for_each_pipe(pipe)
1142 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1143 pipe_name(pipe),
1144 I915_READ(FDI_RX_IIR(pipe)));
1145
1146 if (pch_iir & SDE_ERROR_CPT)
1147 cpt_serr_int_handler(dev);
1148 }
1149
1150 static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
1151 {
1152 struct drm_device *dev = (struct drm_device *) arg;
1153 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1154 u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier = 0;
1155 irqreturn_t ret = IRQ_NONE;
1156 int i;
1157
1158 atomic_inc(&dev_priv->irq_received);
1159
1160 /* We get interrupts on unclaimed registers, so check for this before we
1161 * do any I915_{READ,WRITE}. */
1162 if (IS_HASWELL(dev) &&
1163 (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1164 DRM_ERROR("Unclaimed register before interrupt\n");
1165 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1166 }
1167
1168 /* disable master interrupt before clearing iir */
1169 de_ier = I915_READ(DEIER);
1170 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
1171
1172 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1173 * interrupts will will be stored on its back queue, and then we'll be
1174 * able to process them after we restore SDEIER (as soon as we restore
1175 * it, we'll get an interrupt if SDEIIR still has something to process
1176 * due to its back queue). */
1177 if (!HAS_PCH_NOP(dev)) {
1178 sde_ier = I915_READ(SDEIER);
1179 I915_WRITE(SDEIER, 0);
1180 POSTING_READ(SDEIER);
1181 }
1182
1183 /* On Haswell, also mask ERR_INT because we don't want to risk
1184 * generating "unclaimed register" interrupts from inside the interrupt
1185 * handler. */
1186 if (IS_HASWELL(dev))
1187 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
1188
1189 gt_iir = I915_READ(GTIIR);
1190 if (gt_iir) {
1191 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1192 I915_WRITE(GTIIR, gt_iir);
1193 ret = IRQ_HANDLED;
1194 }
1195
1196 de_iir = I915_READ(DEIIR);
1197 if (de_iir) {
1198 if (de_iir & DE_ERR_INT_IVB)
1199 ivb_err_int_handler(dev);
1200
1201 if (de_iir & DE_AUX_CHANNEL_A_IVB)
1202 dp_aux_irq_handler(dev);
1203
1204 if (de_iir & DE_GSE_IVB)
1205 intel_opregion_asle_intr(dev);
1206
1207 for (i = 0; i < 3; i++) {
1208 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
1209 drm_handle_vblank(dev, i);
1210 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
1211 intel_prepare_page_flip(dev, i);
1212 intel_finish_page_flip_plane(dev, i);
1213 }
1214 }
1215
1216 /* check event from PCH */
1217 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1218 u32 pch_iir = I915_READ(SDEIIR);
1219
1220 cpt_irq_handler(dev, pch_iir);
1221
1222 /* clear PCH hotplug event before clear CPU irq */
1223 I915_WRITE(SDEIIR, pch_iir);
1224 }
1225
1226 I915_WRITE(DEIIR, de_iir);
1227 ret = IRQ_HANDLED;
1228 }
1229
1230 pm_iir = I915_READ(GEN6_PMIIR);
1231 if (pm_iir) {
1232 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
1233 gen6_queue_rps_work(dev_priv, pm_iir);
1234 I915_WRITE(GEN6_PMIIR, pm_iir);
1235 ret = IRQ_HANDLED;
1236 }
1237
1238 if (IS_HASWELL(dev) && ivb_can_enable_err_int(dev))
1239 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
1240
1241 I915_WRITE(DEIER, de_ier);
1242 POSTING_READ(DEIER);
1243 if (!HAS_PCH_NOP(dev)) {
1244 I915_WRITE(SDEIER, sde_ier);
1245 POSTING_READ(SDEIER);
1246 }
1247
1248 return ret;
1249 }
1250
1251 static void ilk_gt_irq_handler(struct drm_device *dev,
1252 struct drm_i915_private *dev_priv,
1253 u32 gt_iir)
1254 {
1255 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
1256 notify_ring(dev, &dev_priv->ring[RCS]);
1257 if (gt_iir & GT_BSD_USER_INTERRUPT)
1258 notify_ring(dev, &dev_priv->ring[VCS]);
1259 }
1260
1261 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
1262 {
1263 struct drm_device *dev = (struct drm_device *) arg;
1264 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1265 int ret = IRQ_NONE;
1266 u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
1267
1268 atomic_inc(&dev_priv->irq_received);
1269
1270 /* disable master interrupt before clearing iir */
1271 de_ier = I915_READ(DEIER);
1272 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
1273 POSTING_READ(DEIER);
1274
1275 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1276 * interrupts will will be stored on its back queue, and then we'll be
1277 * able to process them after we restore SDEIER (as soon as we restore
1278 * it, we'll get an interrupt if SDEIIR still has something to process
1279 * due to its back queue). */
1280 sde_ier = I915_READ(SDEIER);
1281 I915_WRITE(SDEIER, 0);
1282 POSTING_READ(SDEIER);
1283
1284 de_iir = I915_READ(DEIIR);
1285 gt_iir = I915_READ(GTIIR);
1286 pm_iir = I915_READ(GEN6_PMIIR);
1287
1288 if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
1289 goto done;
1290
1291 ret = IRQ_HANDLED;
1292
1293 if (IS_GEN5(dev))
1294 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1295 else
1296 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1297
1298 if (de_iir & DE_AUX_CHANNEL_A)
1299 dp_aux_irq_handler(dev);
1300
1301 if (de_iir & DE_GSE)
1302 intel_opregion_asle_intr(dev);
1303
1304 if (de_iir & DE_PIPEA_VBLANK)
1305 drm_handle_vblank(dev, 0);
1306
1307 if (de_iir & DE_PIPEB_VBLANK)
1308 drm_handle_vblank(dev, 1);
1309
1310 if (de_iir & DE_POISON)
1311 DRM_ERROR("Poison interrupt\n");
1312
1313 if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
1314 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1315 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1316
1317 if (de_iir & DE_PIPEB_FIFO_UNDERRUN)
1318 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1319 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1320
1321 if (de_iir & DE_PLANEA_FLIP_DONE) {
1322 intel_prepare_page_flip(dev, 0);
1323 intel_finish_page_flip_plane(dev, 0);
1324 }
1325
1326 if (de_iir & DE_PLANEB_FLIP_DONE) {
1327 intel_prepare_page_flip(dev, 1);
1328 intel_finish_page_flip_plane(dev, 1);
1329 }
1330
1331 /* check event from PCH */
1332 if (de_iir & DE_PCH_EVENT) {
1333 u32 pch_iir = I915_READ(SDEIIR);
1334
1335 if (HAS_PCH_CPT(dev))
1336 cpt_irq_handler(dev, pch_iir);
1337 else
1338 ibx_irq_handler(dev, pch_iir);
1339
1340 /* should clear PCH hotplug event before clear CPU irq */
1341 I915_WRITE(SDEIIR, pch_iir);
1342 }
1343
1344 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1345 ironlake_handle_rps_change(dev);
1346
1347 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
1348 gen6_queue_rps_work(dev_priv, pm_iir);
1349
1350 I915_WRITE(GTIIR, gt_iir);
1351 I915_WRITE(DEIIR, de_iir);
1352 I915_WRITE(GEN6_PMIIR, pm_iir);
1353
1354 done:
1355 I915_WRITE(DEIER, de_ier);
1356 POSTING_READ(DEIER);
1357 I915_WRITE(SDEIER, sde_ier);
1358 POSTING_READ(SDEIER);
1359
1360 return ret;
1361 }
1362
1363 /**
1364 * i915_error_work_func - do process context error handling work
1365 * @work: work struct
1366 *
1367 * Fire an error uevent so userspace can see that a hang or error
1368 * was detected.
1369 */
1370 static void i915_error_work_func(struct work_struct *work)
1371 {
1372 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
1373 work);
1374 drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
1375 gpu_error);
1376 struct drm_device *dev = dev_priv->dev;
1377 struct intel_ring_buffer *ring;
1378 char *error_event[] = { "ERROR=1", NULL };
1379 char *reset_event[] = { "RESET=1", NULL };
1380 char *reset_done_event[] = { "ERROR=0", NULL };
1381 int i, ret;
1382
1383 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
1384
1385 /*
1386 * Note that there's only one work item which does gpu resets, so we
1387 * need not worry about concurrent gpu resets potentially incrementing
1388 * error->reset_counter twice. We only need to take care of another
1389 * racing irq/hangcheck declaring the gpu dead for a second time. A
1390 * quick check for that is good enough: schedule_work ensures the
1391 * correct ordering between hang detection and this work item, and since
1392 * the reset in-progress bit is only ever set by code outside of this
1393 * work we don't need to worry about any other races.
1394 */
1395 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
1396 DRM_DEBUG_DRIVER("resetting chip\n");
1397 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
1398 reset_event);
1399
1400 ret = i915_reset(dev);
1401
1402 if (ret == 0) {
1403 /*
1404 * After all the gem state is reset, increment the reset
1405 * counter and wake up everyone waiting for the reset to
1406 * complete.
1407 *
1408 * Since unlock operations are a one-sided barrier only,
1409 * we need to insert a barrier here to order any seqno
1410 * updates before
1411 * the counter increment.
1412 */
1413 smp_mb__before_atomic_inc();
1414 atomic_inc(&dev_priv->gpu_error.reset_counter);
1415
1416 kobject_uevent_env(&dev->primary->kdev.kobj,
1417 KOBJ_CHANGE, reset_done_event);
1418 } else {
1419 atomic_set(&error->reset_counter, I915_WEDGED);
1420 }
1421
1422 for_each_ring(ring, dev_priv, i)
1423 wake_up_all(&ring->irq_queue);
1424
1425 intel_display_handle_reset(dev);
1426
1427 wake_up_all(&dev_priv->gpu_error.reset_queue);
1428 }
1429 }
1430
1431 /* NB: please notice the memset */
1432 static void i915_get_extra_instdone(struct drm_device *dev,
1433 uint32_t *instdone)
1434 {
1435 struct drm_i915_private *dev_priv = dev->dev_private;
1436 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1437
1438 switch(INTEL_INFO(dev)->gen) {
1439 case 2:
1440 case 3:
1441 instdone[0] = I915_READ(INSTDONE);
1442 break;
1443 case 4:
1444 case 5:
1445 case 6:
1446 instdone[0] = I915_READ(INSTDONE_I965);
1447 instdone[1] = I915_READ(INSTDONE1);
1448 break;
1449 default:
1450 WARN_ONCE(1, "Unsupported platform\n");
1451 case 7:
1452 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1453 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1454 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1455 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1456 break;
1457 }
1458 }
1459
1460 #ifdef CONFIG_DEBUG_FS
1461 static struct drm_i915_error_object *
1462 i915_error_object_create_sized(struct drm_i915_private *dev_priv,
1463 struct drm_i915_gem_object *src,
1464 const int num_pages)
1465 {
1466 struct drm_i915_error_object *dst;
1467 int i;
1468 u32 reloc_offset;
1469
1470 if (src == NULL || src->pages == NULL)
1471 return NULL;
1472
1473 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
1474 if (dst == NULL)
1475 return NULL;
1476
1477 reloc_offset = src->gtt_offset;
1478 for (i = 0; i < num_pages; i++) {
1479 unsigned long flags;
1480 void *d;
1481
1482 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
1483 if (d == NULL)
1484 goto unwind;
1485
1486 local_irq_save(flags);
1487 if (reloc_offset < dev_priv->gtt.mappable_end &&
1488 src->has_global_gtt_mapping) {
1489 void __iomem *s;
1490
1491 /* Simply ignore tiling or any overlapping fence.
1492 * It's part of the error state, and this hopefully
1493 * captures what the GPU read.
1494 */
1495
1496 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
1497 reloc_offset);
1498 memcpy_fromio(d, s, PAGE_SIZE);
1499 io_mapping_unmap_atomic(s);
1500 } else if (src->stolen) {
1501 unsigned long offset;
1502
1503 offset = dev_priv->mm.stolen_base;
1504 offset += src->stolen->start;
1505 offset += i << PAGE_SHIFT;
1506
1507 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
1508 } else {
1509 struct page *page;
1510 void *s;
1511
1512 page = i915_gem_object_get_page(src, i);
1513
1514 drm_clflush_pages(&page, 1);
1515
1516 s = kmap_atomic(page);
1517 memcpy(d, s, PAGE_SIZE);
1518 kunmap_atomic(s);
1519
1520 drm_clflush_pages(&page, 1);
1521 }
1522 local_irq_restore(flags);
1523
1524 dst->pages[i] = d;
1525
1526 reloc_offset += PAGE_SIZE;
1527 }
1528 dst->page_count = num_pages;
1529 dst->gtt_offset = src->gtt_offset;
1530
1531 return dst;
1532
1533 unwind:
1534 while (i--)
1535 kfree(dst->pages[i]);
1536 kfree(dst);
1537 return NULL;
1538 }
1539 #define i915_error_object_create(dev_priv, src) \
1540 i915_error_object_create_sized((dev_priv), (src), \
1541 (src)->base.size>>PAGE_SHIFT)
1542
1543 static void
1544 i915_error_object_free(struct drm_i915_error_object *obj)
1545 {
1546 int page;
1547
1548 if (obj == NULL)
1549 return;
1550
1551 for (page = 0; page < obj->page_count; page++)
1552 kfree(obj->pages[page]);
1553
1554 kfree(obj);
1555 }
1556
1557 void
1558 i915_error_state_free(struct kref *error_ref)
1559 {
1560 struct drm_i915_error_state *error = container_of(error_ref,
1561 typeof(*error), ref);
1562 int i;
1563
1564 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
1565 i915_error_object_free(error->ring[i].batchbuffer);
1566 i915_error_object_free(error->ring[i].ringbuffer);
1567 kfree(error->ring[i].requests);
1568 }
1569
1570 kfree(error->active_bo);
1571 kfree(error->overlay);
1572 kfree(error);
1573 }
1574 static void capture_bo(struct drm_i915_error_buffer *err,
1575 struct drm_i915_gem_object *obj)
1576 {
1577 err->size = obj->base.size;
1578 err->name = obj->base.name;
1579 err->rseqno = obj->last_read_seqno;
1580 err->wseqno = obj->last_write_seqno;
1581 err->gtt_offset = obj->gtt_offset;
1582 err->read_domains = obj->base.read_domains;
1583 err->write_domain = obj->base.write_domain;
1584 err->fence_reg = obj->fence_reg;
1585 err->pinned = 0;
1586 if (obj->pin_count > 0)
1587 err->pinned = 1;
1588 if (obj->user_pin_count > 0)
1589 err->pinned = -1;
1590 err->tiling = obj->tiling_mode;
1591 err->dirty = obj->dirty;
1592 err->purgeable = obj->madv != I915_MADV_WILLNEED;
1593 err->ring = obj->ring ? obj->ring->id : -1;
1594 err->cache_level = obj->cache_level;
1595 }
1596
1597 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1598 int count, struct list_head *head)
1599 {
1600 struct drm_i915_gem_object *obj;
1601 int i = 0;
1602
1603 list_for_each_entry(obj, head, mm_list) {
1604 capture_bo(err++, obj);
1605 if (++i == count)
1606 break;
1607 }
1608
1609 return i;
1610 }
1611
1612 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1613 int count, struct list_head *head)
1614 {
1615 struct drm_i915_gem_object *obj;
1616 int i = 0;
1617
1618 list_for_each_entry(obj, head, gtt_list) {
1619 if (obj->pin_count == 0)
1620 continue;
1621
1622 capture_bo(err++, obj);
1623 if (++i == count)
1624 break;
1625 }
1626
1627 return i;
1628 }
1629
1630 static void i915_gem_record_fences(struct drm_device *dev,
1631 struct drm_i915_error_state *error)
1632 {
1633 struct drm_i915_private *dev_priv = dev->dev_private;
1634 int i;
1635
1636 /* Fences */
1637 switch (INTEL_INFO(dev)->gen) {
1638 case 7:
1639 case 6:
1640 for (i = 0; i < dev_priv->num_fence_regs; i++)
1641 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1642 break;
1643 case 5:
1644 case 4:
1645 for (i = 0; i < 16; i++)
1646 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1647 break;
1648 case 3:
1649 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1650 for (i = 0; i < 8; i++)
1651 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1652 case 2:
1653 for (i = 0; i < 8; i++)
1654 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1655 break;
1656
1657 default:
1658 BUG();
1659 }
1660 }
1661
1662 static struct drm_i915_error_object *
1663 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1664 struct intel_ring_buffer *ring)
1665 {
1666 struct drm_i915_gem_object *obj;
1667 u32 seqno;
1668
1669 if (!ring->get_seqno)
1670 return NULL;
1671
1672 if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
1673 u32 acthd = I915_READ(ACTHD);
1674
1675 if (WARN_ON(ring->id != RCS))
1676 return NULL;
1677
1678 obj = ring->private;
1679 if (acthd >= obj->gtt_offset &&
1680 acthd < obj->gtt_offset + obj->base.size)
1681 return i915_error_object_create(dev_priv, obj);
1682 }
1683
1684 seqno = ring->get_seqno(ring, false);
1685 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1686 if (obj->ring != ring)
1687 continue;
1688
1689 if (i915_seqno_passed(seqno, obj->last_read_seqno))
1690 continue;
1691
1692 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1693 continue;
1694
1695 /* We need to copy these to an anonymous buffer as the simplest
1696 * method to avoid being overwritten by userspace.
1697 */
1698 return i915_error_object_create(dev_priv, obj);
1699 }
1700
1701 return NULL;
1702 }
1703
1704 static void i915_record_ring_state(struct drm_device *dev,
1705 struct drm_i915_error_state *error,
1706 struct intel_ring_buffer *ring)
1707 {
1708 struct drm_i915_private *dev_priv = dev->dev_private;
1709
1710 if (INTEL_INFO(dev)->gen >= 6) {
1711 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
1712 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
1713 error->semaphore_mboxes[ring->id][0]
1714 = I915_READ(RING_SYNC_0(ring->mmio_base));
1715 error->semaphore_mboxes[ring->id][1]
1716 = I915_READ(RING_SYNC_1(ring->mmio_base));
1717 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
1718 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
1719 }
1720
1721 if (INTEL_INFO(dev)->gen >= 4) {
1722 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
1723 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1724 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1725 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
1726 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
1727 if (ring->id == RCS)
1728 error->bbaddr = I915_READ64(BB_ADDR);
1729 } else {
1730 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
1731 error->ipeir[ring->id] = I915_READ(IPEIR);
1732 error->ipehr[ring->id] = I915_READ(IPEHR);
1733 error->instdone[ring->id] = I915_READ(INSTDONE);
1734 }
1735
1736 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
1737 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
1738 error->seqno[ring->id] = ring->get_seqno(ring, false);
1739 error->acthd[ring->id] = intel_ring_get_active_head(ring);
1740 error->head[ring->id] = I915_READ_HEAD(ring);
1741 error->tail[ring->id] = I915_READ_TAIL(ring);
1742 error->ctl[ring->id] = I915_READ_CTL(ring);
1743
1744 error->cpu_ring_head[ring->id] = ring->head;
1745 error->cpu_ring_tail[ring->id] = ring->tail;
1746 }
1747
1748
1749 static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
1750 struct drm_i915_error_state *error,
1751 struct drm_i915_error_ring *ering)
1752 {
1753 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1754 struct drm_i915_gem_object *obj;
1755
1756 /* Currently render ring is the only HW context user */
1757 if (ring->id != RCS || !error->ccid)
1758 return;
1759
1760 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
1761 if ((error->ccid & PAGE_MASK) == obj->gtt_offset) {
1762 ering->ctx = i915_error_object_create_sized(dev_priv,
1763 obj, 1);
1764 }
1765 }
1766 }
1767
1768 static void i915_gem_record_rings(struct drm_device *dev,
1769 struct drm_i915_error_state *error)
1770 {
1771 struct drm_i915_private *dev_priv = dev->dev_private;
1772 struct intel_ring_buffer *ring;
1773 struct drm_i915_gem_request *request;
1774 int i, count;
1775
1776 for_each_ring(ring, dev_priv, i) {
1777 i915_record_ring_state(dev, error, ring);
1778
1779 error->ring[i].batchbuffer =
1780 i915_error_first_batchbuffer(dev_priv, ring);
1781
1782 error->ring[i].ringbuffer =
1783 i915_error_object_create(dev_priv, ring->obj);
1784
1785
1786 i915_gem_record_active_context(ring, error, &error->ring[i]);
1787
1788 count = 0;
1789 list_for_each_entry(request, &ring->request_list, list)
1790 count++;
1791
1792 error->ring[i].num_requests = count;
1793 error->ring[i].requests =
1794 kmalloc(count*sizeof(struct drm_i915_error_request),
1795 GFP_ATOMIC);
1796 if (error->ring[i].requests == NULL) {
1797 error->ring[i].num_requests = 0;
1798 continue;
1799 }
1800
1801 count = 0;
1802 list_for_each_entry(request, &ring->request_list, list) {
1803 struct drm_i915_error_request *erq;
1804
1805 erq = &error->ring[i].requests[count++];
1806 erq->seqno = request->seqno;
1807 erq->jiffies = request->emitted_jiffies;
1808 erq->tail = request->tail;
1809 }
1810 }
1811 }
1812
1813 /**
1814 * i915_capture_error_state - capture an error record for later analysis
1815 * @dev: drm device
1816 *
1817 * Should be called when an error is detected (either a hang or an error
1818 * interrupt) to capture error state from the time of the error. Fills
1819 * out a structure which becomes available in debugfs for user level tools
1820 * to pick up.
1821 */
1822 static void i915_capture_error_state(struct drm_device *dev)
1823 {
1824 struct drm_i915_private *dev_priv = dev->dev_private;
1825 struct drm_i915_gem_object *obj;
1826 struct drm_i915_error_state *error;
1827 unsigned long flags;
1828 int i, pipe;
1829
1830 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1831 error = dev_priv->gpu_error.first_error;
1832 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1833 if (error)
1834 return;
1835
1836 /* Account for pipe specific data like PIPE*STAT */
1837 error = kzalloc(sizeof(*error), GFP_ATOMIC);
1838 if (!error) {
1839 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1840 return;
1841 }
1842
1843 DRM_INFO("capturing error event; look for more information in "
1844 "/sys/kernel/debug/dri/%d/i915_error_state\n",
1845 dev->primary->index);
1846
1847 kref_init(&error->ref);
1848 error->eir = I915_READ(EIR);
1849 error->pgtbl_er = I915_READ(PGTBL_ER);
1850 if (HAS_HW_CONTEXTS(dev))
1851 error->ccid = I915_READ(CCID);
1852
1853 if (HAS_PCH_SPLIT(dev))
1854 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1855 else if (IS_VALLEYVIEW(dev))
1856 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1857 else if (IS_GEN2(dev))
1858 error->ier = I915_READ16(IER);
1859 else
1860 error->ier = I915_READ(IER);
1861
1862 if (INTEL_INFO(dev)->gen >= 6)
1863 error->derrmr = I915_READ(DERRMR);
1864
1865 if (IS_VALLEYVIEW(dev))
1866 error->forcewake = I915_READ(FORCEWAKE_VLV);
1867 else if (INTEL_INFO(dev)->gen >= 7)
1868 error->forcewake = I915_READ(FORCEWAKE_MT);
1869 else if (INTEL_INFO(dev)->gen == 6)
1870 error->forcewake = I915_READ(FORCEWAKE);
1871
1872 if (!HAS_PCH_SPLIT(dev))
1873 for_each_pipe(pipe)
1874 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1875
1876 if (INTEL_INFO(dev)->gen >= 6) {
1877 error->error = I915_READ(ERROR_GEN6);
1878 error->done_reg = I915_READ(DONE_REG);
1879 }
1880
1881 if (INTEL_INFO(dev)->gen == 7)
1882 error->err_int = I915_READ(GEN7_ERR_INT);
1883
1884 i915_get_extra_instdone(dev, error->extra_instdone);
1885
1886 i915_gem_record_fences(dev, error);
1887 i915_gem_record_rings(dev, error);
1888
1889 /* Record buffers on the active and pinned lists. */
1890 error->active_bo = NULL;
1891 error->pinned_bo = NULL;
1892
1893 i = 0;
1894 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1895 i++;
1896 error->active_bo_count = i;
1897 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
1898 if (obj->pin_count)
1899 i++;
1900 error->pinned_bo_count = i - error->active_bo_count;
1901
1902 error->active_bo = NULL;
1903 error->pinned_bo = NULL;
1904 if (i) {
1905 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
1906 GFP_ATOMIC);
1907 if (error->active_bo)
1908 error->pinned_bo =
1909 error->active_bo + error->active_bo_count;
1910 }
1911
1912 if (error->active_bo)
1913 error->active_bo_count =
1914 capture_active_bo(error->active_bo,
1915 error->active_bo_count,
1916 &dev_priv->mm.active_list);
1917
1918 if (error->pinned_bo)
1919 error->pinned_bo_count =
1920 capture_pinned_bo(error->pinned_bo,
1921 error->pinned_bo_count,
1922 &dev_priv->mm.bound_list);
1923
1924 do_gettimeofday(&error->time);
1925
1926 error->overlay = intel_overlay_capture_error_state(dev);
1927 error->display = intel_display_capture_error_state(dev);
1928
1929 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1930 if (dev_priv->gpu_error.first_error == NULL) {
1931 dev_priv->gpu_error.first_error = error;
1932 error = NULL;
1933 }
1934 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1935
1936 if (error)
1937 i915_error_state_free(&error->ref);
1938 }
1939
1940 void i915_destroy_error_state(struct drm_device *dev)
1941 {
1942 struct drm_i915_private *dev_priv = dev->dev_private;
1943 struct drm_i915_error_state *error;
1944 unsigned long flags;
1945
1946 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1947 error = dev_priv->gpu_error.first_error;
1948 dev_priv->gpu_error.first_error = NULL;
1949 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1950
1951 if (error)
1952 kref_put(&error->ref, i915_error_state_free);
1953 }
1954 #else
1955 #define i915_capture_error_state(x)
1956 #endif
1957
1958 static void i915_report_and_clear_eir(struct drm_device *dev)
1959 {
1960 struct drm_i915_private *dev_priv = dev->dev_private;
1961 uint32_t instdone[I915_NUM_INSTDONE_REG];
1962 u32 eir = I915_READ(EIR);
1963 int pipe, i;
1964
1965 if (!eir)
1966 return;
1967
1968 pr_err("render error detected, EIR: 0x%08x\n", eir);
1969
1970 i915_get_extra_instdone(dev, instdone);
1971
1972 if (IS_G4X(dev)) {
1973 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1974 u32 ipeir = I915_READ(IPEIR_I965);
1975
1976 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1977 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1978 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1979 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1980 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1981 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1982 I915_WRITE(IPEIR_I965, ipeir);
1983 POSTING_READ(IPEIR_I965);
1984 }
1985 if (eir & GM45_ERROR_PAGE_TABLE) {
1986 u32 pgtbl_err = I915_READ(PGTBL_ER);
1987 pr_err("page table error\n");
1988 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
1989 I915_WRITE(PGTBL_ER, pgtbl_err);
1990 POSTING_READ(PGTBL_ER);
1991 }
1992 }
1993
1994 if (!IS_GEN2(dev)) {
1995 if (eir & I915_ERROR_PAGE_TABLE) {
1996 u32 pgtbl_err = I915_READ(PGTBL_ER);
1997 pr_err("page table error\n");
1998 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
1999 I915_WRITE(PGTBL_ER, pgtbl_err);
2000 POSTING_READ(PGTBL_ER);
2001 }
2002 }
2003
2004 if (eir & I915_ERROR_MEMORY_REFRESH) {
2005 pr_err("memory refresh error:\n");
2006 for_each_pipe(pipe)
2007 pr_err("pipe %c stat: 0x%08x\n",
2008 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2009 /* pipestat has already been acked */
2010 }
2011 if (eir & I915_ERROR_INSTRUCTION) {
2012 pr_err("instruction error\n");
2013 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
2014 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2015 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2016 if (INTEL_INFO(dev)->gen < 4) {
2017 u32 ipeir = I915_READ(IPEIR);
2018
2019 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2020 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
2021 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
2022 I915_WRITE(IPEIR, ipeir);
2023 POSTING_READ(IPEIR);
2024 } else {
2025 u32 ipeir = I915_READ(IPEIR_I965);
2026
2027 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2028 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2029 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2030 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2031 I915_WRITE(IPEIR_I965, ipeir);
2032 POSTING_READ(IPEIR_I965);
2033 }
2034 }
2035
2036 I915_WRITE(EIR, eir);
2037 POSTING_READ(EIR);
2038 eir = I915_READ(EIR);
2039 if (eir) {
2040 /*
2041 * some errors might have become stuck,
2042 * mask them.
2043 */
2044 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2045 I915_WRITE(EMR, I915_READ(EMR) | eir);
2046 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2047 }
2048 }
2049
2050 /**
2051 * i915_handle_error - handle an error interrupt
2052 * @dev: drm device
2053 *
2054 * Do some basic checking of regsiter state at error interrupt time and
2055 * dump it to the syslog. Also call i915_capture_error_state() to make
2056 * sure we get a record and make it available in debugfs. Fire a uevent
2057 * so userspace knows something bad happened (should trigger collection
2058 * of a ring dump etc.).
2059 */
2060 void i915_handle_error(struct drm_device *dev, bool wedged)
2061 {
2062 struct drm_i915_private *dev_priv = dev->dev_private;
2063 struct intel_ring_buffer *ring;
2064 int i;
2065
2066 i915_capture_error_state(dev);
2067 i915_report_and_clear_eir(dev);
2068
2069 if (wedged) {
2070 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2071 &dev_priv->gpu_error.reset_counter);
2072
2073 /*
2074 * Wakeup waiting processes so that the reset work item
2075 * doesn't deadlock trying to grab various locks.
2076 */
2077 for_each_ring(ring, dev_priv, i)
2078 wake_up_all(&ring->irq_queue);
2079 }
2080
2081 queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
2082 }
2083
2084 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
2085 {
2086 drm_i915_private_t *dev_priv = dev->dev_private;
2087 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2088 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2089 struct drm_i915_gem_object *obj;
2090 struct intel_unpin_work *work;
2091 unsigned long flags;
2092 bool stall_detected;
2093
2094 /* Ignore early vblank irqs */
2095 if (intel_crtc == NULL)
2096 return;
2097
2098 spin_lock_irqsave(&dev->event_lock, flags);
2099 work = intel_crtc->unpin_work;
2100
2101 if (work == NULL ||
2102 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2103 !work->enable_stall_check) {
2104 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2105 spin_unlock_irqrestore(&dev->event_lock, flags);
2106 return;
2107 }
2108
2109 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2110 obj = work->pending_flip_obj;
2111 if (INTEL_INFO(dev)->gen >= 4) {
2112 int dspsurf = DSPSURF(intel_crtc->plane);
2113 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
2114 obj->gtt_offset;
2115 } else {
2116 int dspaddr = DSPADDR(intel_crtc->plane);
2117 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
2118 crtc->y * crtc->fb->pitches[0] +
2119 crtc->x * crtc->fb->bits_per_pixel/8);
2120 }
2121
2122 spin_unlock_irqrestore(&dev->event_lock, flags);
2123
2124 if (stall_detected) {
2125 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2126 intel_prepare_page_flip(dev, intel_crtc->plane);
2127 }
2128 }
2129
2130 /* Called from drm generic code, passed 'crtc' which
2131 * we use as a pipe index
2132 */
2133 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2134 {
2135 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2136 unsigned long irqflags;
2137
2138 if (!i915_pipe_enabled(dev, pipe))
2139 return -EINVAL;
2140
2141 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2142 if (INTEL_INFO(dev)->gen >= 4)
2143 i915_enable_pipestat(dev_priv, pipe,
2144 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2145 else
2146 i915_enable_pipestat(dev_priv, pipe,
2147 PIPE_VBLANK_INTERRUPT_ENABLE);
2148
2149 /* maintain vblank delivery even in deep C-states */
2150 if (dev_priv->info->gen == 3)
2151 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
2152 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2153
2154 return 0;
2155 }
2156
2157 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2158 {
2159 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2160 unsigned long irqflags;
2161
2162 if (!i915_pipe_enabled(dev, pipe))
2163 return -EINVAL;
2164
2165 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2166 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
2167 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
2168 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2169
2170 return 0;
2171 }
2172
2173 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
2174 {
2175 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2176 unsigned long irqflags;
2177
2178 if (!i915_pipe_enabled(dev, pipe))
2179 return -EINVAL;
2180
2181 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2182 ironlake_enable_display_irq(dev_priv,
2183 DE_PIPEA_VBLANK_IVB << (5 * pipe));
2184 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2185
2186 return 0;
2187 }
2188
2189 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2190 {
2191 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2192 unsigned long irqflags;
2193 u32 imr;
2194
2195 if (!i915_pipe_enabled(dev, pipe))
2196 return -EINVAL;
2197
2198 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2199 imr = I915_READ(VLV_IMR);
2200 if (pipe == 0)
2201 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
2202 else
2203 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2204 I915_WRITE(VLV_IMR, imr);
2205 i915_enable_pipestat(dev_priv, pipe,
2206 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2207 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2208
2209 return 0;
2210 }
2211
2212 /* Called from drm generic code, passed 'crtc' which
2213 * we use as a pipe index
2214 */
2215 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2216 {
2217 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2218 unsigned long irqflags;
2219
2220 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2221 if (dev_priv->info->gen == 3)
2222 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
2223
2224 i915_disable_pipestat(dev_priv, pipe,
2225 PIPE_VBLANK_INTERRUPT_ENABLE |
2226 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2227 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2228 }
2229
2230 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2231 {
2232 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2233 unsigned long irqflags;
2234
2235 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2236 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
2237 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
2238 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2239 }
2240
2241 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
2242 {
2243 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2244 unsigned long irqflags;
2245
2246 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2247 ironlake_disable_display_irq(dev_priv,
2248 DE_PIPEA_VBLANK_IVB << (pipe * 5));
2249 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2250 }
2251
2252 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2253 {
2254 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2255 unsigned long irqflags;
2256 u32 imr;
2257
2258 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2259 i915_disable_pipestat(dev_priv, pipe,
2260 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2261 imr = I915_READ(VLV_IMR);
2262 if (pipe == 0)
2263 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
2264 else
2265 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2266 I915_WRITE(VLV_IMR, imr);
2267 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2268 }
2269
2270 static u32
2271 ring_last_seqno(struct intel_ring_buffer *ring)
2272 {
2273 return list_entry(ring->request_list.prev,
2274 struct drm_i915_gem_request, list)->seqno;
2275 }
2276
2277 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring,
2278 u32 ring_seqno, bool *err)
2279 {
2280 if (list_empty(&ring->request_list) ||
2281 i915_seqno_passed(ring_seqno, ring_last_seqno(ring))) {
2282 /* Issue a wake-up to catch stuck h/w. */
2283 if (waitqueue_active(&ring->irq_queue)) {
2284 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2285 ring->name);
2286 wake_up_all(&ring->irq_queue);
2287 *err = true;
2288 }
2289 return true;
2290 }
2291 return false;
2292 }
2293
2294 static bool semaphore_passed(struct intel_ring_buffer *ring)
2295 {
2296 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2297 u32 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
2298 struct intel_ring_buffer *signaller;
2299 u32 cmd, ipehr, acthd_min;
2300
2301 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2302 if ((ipehr & ~(0x3 << 16)) !=
2303 (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
2304 return false;
2305
2306 /* ACTHD is likely pointing to the dword after the actual command,
2307 * so scan backwards until we find the MBOX.
2308 */
2309 acthd_min = max((int)acthd - 3 * 4, 0);
2310 do {
2311 cmd = ioread32(ring->virtual_start + acthd);
2312 if (cmd == ipehr)
2313 break;
2314
2315 acthd -= 4;
2316 if (acthd < acthd_min)
2317 return false;
2318 } while (1);
2319
2320 signaller = &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
2321 return i915_seqno_passed(signaller->get_seqno(signaller, false),
2322 ioread32(ring->virtual_start+acthd+4)+1);
2323 }
2324
2325 static bool kick_ring(struct intel_ring_buffer *ring)
2326 {
2327 struct drm_device *dev = ring->dev;
2328 struct drm_i915_private *dev_priv = dev->dev_private;
2329 u32 tmp = I915_READ_CTL(ring);
2330 if (tmp & RING_WAIT) {
2331 DRM_ERROR("Kicking stuck wait on %s\n",
2332 ring->name);
2333 I915_WRITE_CTL(ring, tmp);
2334 return true;
2335 }
2336
2337 if (INTEL_INFO(dev)->gen >= 6 &&
2338 tmp & RING_WAIT_SEMAPHORE &&
2339 semaphore_passed(ring)) {
2340 DRM_ERROR("Kicking stuck semaphore on %s\n",
2341 ring->name);
2342 I915_WRITE_CTL(ring, tmp);
2343 return true;
2344 }
2345 return false;
2346 }
2347
2348 static bool i915_hangcheck_hung(struct drm_device *dev)
2349 {
2350 drm_i915_private_t *dev_priv = dev->dev_private;
2351
2352 if (dev_priv->gpu_error.hangcheck_count++ > 1) {
2353 bool hung = true;
2354
2355 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
2356 i915_handle_error(dev, true);
2357
2358 if (!IS_GEN2(dev)) {
2359 struct intel_ring_buffer *ring;
2360 int i;
2361
2362 /* Is the chip hanging on a WAIT_FOR_EVENT?
2363 * If so we can simply poke the RB_WAIT bit
2364 * and break the hang. This should work on
2365 * all but the second generation chipsets.
2366 */
2367 for_each_ring(ring, dev_priv, i)
2368 hung &= !kick_ring(ring);
2369 }
2370
2371 return hung;
2372 }
2373
2374 return false;
2375 }
2376
2377 /**
2378 * This is called when the chip hasn't reported back with completed
2379 * batchbuffers in a long time. The first time this is called we simply record
2380 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
2381 * again, we assume the chip is wedged and try to fix it.
2382 */
2383 void i915_hangcheck_elapsed(unsigned long data)
2384 {
2385 struct drm_device *dev = (struct drm_device *)data;
2386 drm_i915_private_t *dev_priv = dev->dev_private;
2387 struct intel_ring_buffer *ring;
2388 bool err = false, idle;
2389 int i;
2390 u32 seqno[I915_NUM_RINGS];
2391 bool work_done;
2392
2393 if (!i915_enable_hangcheck)
2394 return;
2395
2396 idle = true;
2397 for_each_ring(ring, dev_priv, i) {
2398 seqno[i] = ring->get_seqno(ring, false);
2399 idle &= i915_hangcheck_ring_idle(ring, seqno[i], &err);
2400 }
2401
2402 /* If all work is done then ACTHD clearly hasn't advanced. */
2403 if (idle) {
2404 if (err) {
2405 if (i915_hangcheck_hung(dev))
2406 return;
2407
2408 goto repeat;
2409 }
2410
2411 dev_priv->gpu_error.hangcheck_count = 0;
2412 return;
2413 }
2414
2415 work_done = false;
2416 for_each_ring(ring, dev_priv, i) {
2417 if (ring->hangcheck.seqno != seqno[i]) {
2418 work_done = true;
2419 ring->hangcheck.seqno = seqno[i];
2420 }
2421 }
2422
2423 if (!work_done) {
2424 if (i915_hangcheck_hung(dev))
2425 return;
2426 } else {
2427 dev_priv->gpu_error.hangcheck_count = 0;
2428 }
2429
2430 repeat:
2431 /* Reset timer case chip hangs without another request being added */
2432 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2433 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2434 }
2435
2436 /* drm_dma.h hooks
2437 */
2438 static void ironlake_irq_preinstall(struct drm_device *dev)
2439 {
2440 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2441
2442 atomic_set(&dev_priv->irq_received, 0);
2443
2444 I915_WRITE(HWSTAM, 0xeffe);
2445
2446 /* XXX hotplug from PCH */
2447
2448 I915_WRITE(DEIMR, 0xffffffff);
2449 I915_WRITE(DEIER, 0x0);
2450 POSTING_READ(DEIER);
2451
2452 /* and GT */
2453 I915_WRITE(GTIMR, 0xffffffff);
2454 I915_WRITE(GTIER, 0x0);
2455 POSTING_READ(GTIER);
2456
2457 if (HAS_PCH_NOP(dev))
2458 return;
2459
2460 /* south display irq */
2461 I915_WRITE(SDEIMR, 0xffffffff);
2462 /*
2463 * SDEIER is also touched by the interrupt handler to work around missed
2464 * PCH interrupts. Hence we can't update it after the interrupt handler
2465 * is enabled - instead we unconditionally enable all PCH interrupt
2466 * sources here, but then only unmask them as needed with SDEIMR.
2467 */
2468 I915_WRITE(SDEIER, 0xffffffff);
2469 POSTING_READ(SDEIER);
2470 }
2471
2472 static void valleyview_irq_preinstall(struct drm_device *dev)
2473 {
2474 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2475 int pipe;
2476
2477 atomic_set(&dev_priv->irq_received, 0);
2478
2479 /* VLV magic */
2480 I915_WRITE(VLV_IMR, 0);
2481 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2482 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2483 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2484
2485 /* and GT */
2486 I915_WRITE(GTIIR, I915_READ(GTIIR));
2487 I915_WRITE(GTIIR, I915_READ(GTIIR));
2488 I915_WRITE(GTIMR, 0xffffffff);
2489 I915_WRITE(GTIER, 0x0);
2490 POSTING_READ(GTIER);
2491
2492 I915_WRITE(DPINVGTT, 0xff);
2493
2494 I915_WRITE(PORT_HOTPLUG_EN, 0);
2495 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2496 for_each_pipe(pipe)
2497 I915_WRITE(PIPESTAT(pipe), 0xffff);
2498 I915_WRITE(VLV_IIR, 0xffffffff);
2499 I915_WRITE(VLV_IMR, 0xffffffff);
2500 I915_WRITE(VLV_IER, 0x0);
2501 POSTING_READ(VLV_IER);
2502 }
2503
2504 static void ibx_hpd_irq_setup(struct drm_device *dev)
2505 {
2506 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2507 struct drm_mode_config *mode_config = &dev->mode_config;
2508 struct intel_encoder *intel_encoder;
2509 u32 mask = ~I915_READ(SDEIMR);
2510 u32 hotplug;
2511
2512 if (HAS_PCH_IBX(dev)) {
2513 mask &= ~SDE_HOTPLUG_MASK;
2514 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2515 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2516 mask |= hpd_ibx[intel_encoder->hpd_pin];
2517 } else {
2518 mask &= ~SDE_HOTPLUG_MASK_CPT;
2519 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2520 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2521 mask |= hpd_cpt[intel_encoder->hpd_pin];
2522 }
2523
2524 I915_WRITE(SDEIMR, ~mask);
2525
2526 /*
2527 * Enable digital hotplug on the PCH, and configure the DP short pulse
2528 * duration to 2ms (which is the minimum in the Display Port spec)
2529 *
2530 * This register is the same on all known PCH chips.
2531 */
2532 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2533 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2534 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2535 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2536 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2537 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2538 }
2539
2540 static void ibx_irq_postinstall(struct drm_device *dev)
2541 {
2542 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2543 u32 mask;
2544
2545 if (HAS_PCH_IBX(dev)) {
2546 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
2547 SDE_TRANSA_FIFO_UNDER | SDE_POISON;
2548 } else {
2549 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2550
2551 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2552 }
2553
2554 if (HAS_PCH_NOP(dev))
2555 return;
2556
2557 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2558 I915_WRITE(SDEIMR, ~mask);
2559 }
2560
2561 static int ironlake_irq_postinstall(struct drm_device *dev)
2562 {
2563 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2564 /* enable kind of interrupts always enabled */
2565 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2566 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
2567 DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
2568 DE_PIPEA_FIFO_UNDERRUN | DE_POISON;
2569 u32 render_irqs;
2570
2571 dev_priv->irq_mask = ~display_mask;
2572
2573 /* should always can generate irq */
2574 I915_WRITE(DEIIR, I915_READ(DEIIR));
2575 I915_WRITE(DEIMR, dev_priv->irq_mask);
2576 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
2577 POSTING_READ(DEIER);
2578
2579 dev_priv->gt_irq_mask = ~0;
2580
2581 I915_WRITE(GTIIR, I915_READ(GTIIR));
2582 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2583
2584 if (IS_GEN6(dev))
2585 render_irqs =
2586 GT_USER_INTERRUPT |
2587 GEN6_BSD_USER_INTERRUPT |
2588 GEN6_BLITTER_USER_INTERRUPT;
2589 else
2590 render_irqs =
2591 GT_USER_INTERRUPT |
2592 GT_PIPE_NOTIFY |
2593 GT_BSD_USER_INTERRUPT;
2594 I915_WRITE(GTIER, render_irqs);
2595 POSTING_READ(GTIER);
2596
2597 ibx_irq_postinstall(dev);
2598
2599 if (IS_IRONLAKE_M(dev)) {
2600 /* Clear & enable PCU event interrupts */
2601 I915_WRITE(DEIIR, DE_PCU_EVENT);
2602 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
2603 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2604 }
2605
2606 return 0;
2607 }
2608
2609 static int ivybridge_irq_postinstall(struct drm_device *dev)
2610 {
2611 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2612 /* enable kind of interrupts always enabled */
2613 u32 display_mask =
2614 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
2615 DE_PLANEC_FLIP_DONE_IVB |
2616 DE_PLANEB_FLIP_DONE_IVB |
2617 DE_PLANEA_FLIP_DONE_IVB |
2618 DE_AUX_CHANNEL_A_IVB |
2619 DE_ERR_INT_IVB;
2620 u32 render_irqs;
2621
2622 dev_priv->irq_mask = ~display_mask;
2623
2624 /* should always can generate irq */
2625 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2626 I915_WRITE(DEIIR, I915_READ(DEIIR));
2627 I915_WRITE(DEIMR, dev_priv->irq_mask);
2628 I915_WRITE(DEIER,
2629 display_mask |
2630 DE_PIPEC_VBLANK_IVB |
2631 DE_PIPEB_VBLANK_IVB |
2632 DE_PIPEA_VBLANK_IVB);
2633 POSTING_READ(DEIER);
2634
2635 dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
2636
2637 I915_WRITE(GTIIR, I915_READ(GTIIR));
2638 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2639
2640 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2641 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
2642 I915_WRITE(GTIER, render_irqs);
2643 POSTING_READ(GTIER);
2644
2645 ibx_irq_postinstall(dev);
2646
2647 return 0;
2648 }
2649
2650 static int valleyview_irq_postinstall(struct drm_device *dev)
2651 {
2652 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2653 u32 enable_mask;
2654 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
2655 u32 render_irqs;
2656
2657 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
2658 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2659 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2660 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2661 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2662
2663 /*
2664 *Leave vblank interrupts masked initially. enable/disable will
2665 * toggle them based on usage.
2666 */
2667 dev_priv->irq_mask = (~enable_mask) |
2668 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2669 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2670
2671 I915_WRITE(PORT_HOTPLUG_EN, 0);
2672 POSTING_READ(PORT_HOTPLUG_EN);
2673
2674 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2675 I915_WRITE(VLV_IER, enable_mask);
2676 I915_WRITE(VLV_IIR, 0xffffffff);
2677 I915_WRITE(PIPESTAT(0), 0xffff);
2678 I915_WRITE(PIPESTAT(1), 0xffff);
2679 POSTING_READ(VLV_IER);
2680
2681 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
2682 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
2683 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
2684
2685 I915_WRITE(VLV_IIR, 0xffffffff);
2686 I915_WRITE(VLV_IIR, 0xffffffff);
2687
2688 I915_WRITE(GTIIR, I915_READ(GTIIR));
2689 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2690
2691 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2692 GEN6_BLITTER_USER_INTERRUPT;
2693 I915_WRITE(GTIER, render_irqs);
2694 POSTING_READ(GTIER);
2695
2696 /* ack & enable invalid PTE error interrupts */
2697 #if 0 /* FIXME: add support to irq handler for checking these bits */
2698 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2699 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2700 #endif
2701
2702 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2703
2704 return 0;
2705 }
2706
2707 static void valleyview_irq_uninstall(struct drm_device *dev)
2708 {
2709 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2710 int pipe;
2711
2712 if (!dev_priv)
2713 return;
2714
2715 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2716
2717 for_each_pipe(pipe)
2718 I915_WRITE(PIPESTAT(pipe), 0xffff);
2719
2720 I915_WRITE(HWSTAM, 0xffffffff);
2721 I915_WRITE(PORT_HOTPLUG_EN, 0);
2722 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2723 for_each_pipe(pipe)
2724 I915_WRITE(PIPESTAT(pipe), 0xffff);
2725 I915_WRITE(VLV_IIR, 0xffffffff);
2726 I915_WRITE(VLV_IMR, 0xffffffff);
2727 I915_WRITE(VLV_IER, 0x0);
2728 POSTING_READ(VLV_IER);
2729 }
2730
2731 static void ironlake_irq_uninstall(struct drm_device *dev)
2732 {
2733 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2734
2735 if (!dev_priv)
2736 return;
2737
2738 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2739
2740 I915_WRITE(HWSTAM, 0xffffffff);
2741
2742 I915_WRITE(DEIMR, 0xffffffff);
2743 I915_WRITE(DEIER, 0x0);
2744 I915_WRITE(DEIIR, I915_READ(DEIIR));
2745 if (IS_GEN7(dev))
2746 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2747
2748 I915_WRITE(GTIMR, 0xffffffff);
2749 I915_WRITE(GTIER, 0x0);
2750 I915_WRITE(GTIIR, I915_READ(GTIIR));
2751
2752 if (HAS_PCH_NOP(dev))
2753 return;
2754
2755 I915_WRITE(SDEIMR, 0xffffffff);
2756 I915_WRITE(SDEIER, 0x0);
2757 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2758 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
2759 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2760 }
2761
2762 static void i8xx_irq_preinstall(struct drm_device * dev)
2763 {
2764 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2765 int pipe;
2766
2767 atomic_set(&dev_priv->irq_received, 0);
2768
2769 for_each_pipe(pipe)
2770 I915_WRITE(PIPESTAT(pipe), 0);
2771 I915_WRITE16(IMR, 0xffff);
2772 I915_WRITE16(IER, 0x0);
2773 POSTING_READ16(IER);
2774 }
2775
2776 static int i8xx_irq_postinstall(struct drm_device *dev)
2777 {
2778 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2779
2780 I915_WRITE16(EMR,
2781 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2782
2783 /* Unmask the interrupts that we always want on. */
2784 dev_priv->irq_mask =
2785 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2786 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2787 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2788 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2789 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2790 I915_WRITE16(IMR, dev_priv->irq_mask);
2791
2792 I915_WRITE16(IER,
2793 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2794 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2795 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2796 I915_USER_INTERRUPT);
2797 POSTING_READ16(IER);
2798
2799 return 0;
2800 }
2801
2802 /*
2803 * Returns true when a page flip has completed.
2804 */
2805 static bool i8xx_handle_vblank(struct drm_device *dev,
2806 int pipe, u16 iir)
2807 {
2808 drm_i915_private_t *dev_priv = dev->dev_private;
2809 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
2810
2811 if (!drm_handle_vblank(dev, pipe))
2812 return false;
2813
2814 if ((iir & flip_pending) == 0)
2815 return false;
2816
2817 intel_prepare_page_flip(dev, pipe);
2818
2819 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2820 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2821 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2822 * the flip is completed (no longer pending). Since this doesn't raise
2823 * an interrupt per se, we watch for the change at vblank.
2824 */
2825 if (I915_READ16(ISR) & flip_pending)
2826 return false;
2827
2828 intel_finish_page_flip(dev, pipe);
2829
2830 return true;
2831 }
2832
2833 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
2834 {
2835 struct drm_device *dev = (struct drm_device *) arg;
2836 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2837 u16 iir, new_iir;
2838 u32 pipe_stats[2];
2839 unsigned long irqflags;
2840 int irq_received;
2841 int pipe;
2842 u16 flip_mask =
2843 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2844 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2845
2846 atomic_inc(&dev_priv->irq_received);
2847
2848 iir = I915_READ16(IIR);
2849 if (iir == 0)
2850 return IRQ_NONE;
2851
2852 while (iir & ~flip_mask) {
2853 /* Can't rely on pipestat interrupt bit in iir as it might
2854 * have been cleared after the pipestat interrupt was received.
2855 * It doesn't set the bit in iir again, but it still produces
2856 * interrupts (for non-MSI).
2857 */
2858 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2859 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2860 i915_handle_error(dev, false);
2861
2862 for_each_pipe(pipe) {
2863 int reg = PIPESTAT(pipe);
2864 pipe_stats[pipe] = I915_READ(reg);
2865
2866 /*
2867 * Clear the PIPE*STAT regs before the IIR
2868 */
2869 if (pipe_stats[pipe] & 0x8000ffff) {
2870 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2871 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2872 pipe_name(pipe));
2873 I915_WRITE(reg, pipe_stats[pipe]);
2874 irq_received = 1;
2875 }
2876 }
2877 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2878
2879 I915_WRITE16(IIR, iir & ~flip_mask);
2880 new_iir = I915_READ16(IIR); /* Flush posted writes */
2881
2882 i915_update_dri1_breadcrumb(dev);
2883
2884 if (iir & I915_USER_INTERRUPT)
2885 notify_ring(dev, &dev_priv->ring[RCS]);
2886
2887 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2888 i8xx_handle_vblank(dev, 0, iir))
2889 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
2890
2891 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2892 i8xx_handle_vblank(dev, 1, iir))
2893 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
2894
2895 iir = new_iir;
2896 }
2897
2898 return IRQ_HANDLED;
2899 }
2900
2901 static void i8xx_irq_uninstall(struct drm_device * dev)
2902 {
2903 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2904 int pipe;
2905
2906 for_each_pipe(pipe) {
2907 /* Clear enable bits; then clear status bits */
2908 I915_WRITE(PIPESTAT(pipe), 0);
2909 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2910 }
2911 I915_WRITE16(IMR, 0xffff);
2912 I915_WRITE16(IER, 0x0);
2913 I915_WRITE16(IIR, I915_READ16(IIR));
2914 }
2915
2916 static void i915_irq_preinstall(struct drm_device * dev)
2917 {
2918 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2919 int pipe;
2920
2921 atomic_set(&dev_priv->irq_received, 0);
2922
2923 if (I915_HAS_HOTPLUG(dev)) {
2924 I915_WRITE(PORT_HOTPLUG_EN, 0);
2925 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2926 }
2927
2928 I915_WRITE16(HWSTAM, 0xeffe);
2929 for_each_pipe(pipe)
2930 I915_WRITE(PIPESTAT(pipe), 0);
2931 I915_WRITE(IMR, 0xffffffff);
2932 I915_WRITE(IER, 0x0);
2933 POSTING_READ(IER);
2934 }
2935
2936 static int i915_irq_postinstall(struct drm_device *dev)
2937 {
2938 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2939 u32 enable_mask;
2940
2941 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2942
2943 /* Unmask the interrupts that we always want on. */
2944 dev_priv->irq_mask =
2945 ~(I915_ASLE_INTERRUPT |
2946 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2947 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2948 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2949 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2950 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2951
2952 enable_mask =
2953 I915_ASLE_INTERRUPT |
2954 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2955 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2956 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2957 I915_USER_INTERRUPT;
2958
2959 if (I915_HAS_HOTPLUG(dev)) {
2960 I915_WRITE(PORT_HOTPLUG_EN, 0);
2961 POSTING_READ(PORT_HOTPLUG_EN);
2962
2963 /* Enable in IER... */
2964 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2965 /* and unmask in IMR */
2966 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2967 }
2968
2969 I915_WRITE(IMR, dev_priv->irq_mask);
2970 I915_WRITE(IER, enable_mask);
2971 POSTING_READ(IER);
2972
2973 i915_enable_asle_pipestat(dev);
2974
2975 return 0;
2976 }
2977
2978 /*
2979 * Returns true when a page flip has completed.
2980 */
2981 static bool i915_handle_vblank(struct drm_device *dev,
2982 int plane, int pipe, u32 iir)
2983 {
2984 drm_i915_private_t *dev_priv = dev->dev_private;
2985 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
2986
2987 if (!drm_handle_vblank(dev, pipe))
2988 return false;
2989
2990 if ((iir & flip_pending) == 0)
2991 return false;
2992
2993 intel_prepare_page_flip(dev, plane);
2994
2995 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2996 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2997 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2998 * the flip is completed (no longer pending). Since this doesn't raise
2999 * an interrupt per se, we watch for the change at vblank.
3000 */
3001 if (I915_READ(ISR) & flip_pending)
3002 return false;
3003
3004 intel_finish_page_flip(dev, pipe);
3005
3006 return true;
3007 }
3008
3009 static irqreturn_t i915_irq_handler(int irq, void *arg)
3010 {
3011 struct drm_device *dev = (struct drm_device *) arg;
3012 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3013 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3014 unsigned long irqflags;
3015 u32 flip_mask =
3016 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3017 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3018 int pipe, ret = IRQ_NONE;
3019
3020 atomic_inc(&dev_priv->irq_received);
3021
3022 iir = I915_READ(IIR);
3023 do {
3024 bool irq_received = (iir & ~flip_mask) != 0;
3025 bool blc_event = false;
3026
3027 /* Can't rely on pipestat interrupt bit in iir as it might
3028 * have been cleared after the pipestat interrupt was received.
3029 * It doesn't set the bit in iir again, but it still produces
3030 * interrupts (for non-MSI).
3031 */
3032 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3033 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3034 i915_handle_error(dev, false);
3035
3036 for_each_pipe(pipe) {
3037 int reg = PIPESTAT(pipe);
3038 pipe_stats[pipe] = I915_READ(reg);
3039
3040 /* Clear the PIPE*STAT regs before the IIR */
3041 if (pipe_stats[pipe] & 0x8000ffff) {
3042 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3043 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3044 pipe_name(pipe));
3045 I915_WRITE(reg, pipe_stats[pipe]);
3046 irq_received = true;
3047 }
3048 }
3049 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3050
3051 if (!irq_received)
3052 break;
3053
3054 /* Consume port. Then clear IIR or we'll miss events */
3055 if ((I915_HAS_HOTPLUG(dev)) &&
3056 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
3057 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3058 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
3059
3060 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3061 hotplug_status);
3062 if (hotplug_trigger) {
3063 if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_status_i915))
3064 i915_hpd_irq_setup(dev);
3065 queue_work(dev_priv->wq,
3066 &dev_priv->hotplug_work);
3067 }
3068 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3069 POSTING_READ(PORT_HOTPLUG_STAT);
3070 }
3071
3072 I915_WRITE(IIR, iir & ~flip_mask);
3073 new_iir = I915_READ(IIR); /* Flush posted writes */
3074
3075 if (iir & I915_USER_INTERRUPT)
3076 notify_ring(dev, &dev_priv->ring[RCS]);
3077
3078 for_each_pipe(pipe) {
3079 int plane = pipe;
3080 if (IS_MOBILE(dev))
3081 plane = !plane;
3082
3083 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3084 i915_handle_vblank(dev, plane, pipe, iir))
3085 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3086
3087 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3088 blc_event = true;
3089 }
3090
3091 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3092 intel_opregion_asle_intr(dev);
3093
3094 /* With MSI, interrupts are only generated when iir
3095 * transitions from zero to nonzero. If another bit got
3096 * set while we were handling the existing iir bits, then
3097 * we would never get another interrupt.
3098 *
3099 * This is fine on non-MSI as well, as if we hit this path
3100 * we avoid exiting the interrupt handler only to generate
3101 * another one.
3102 *
3103 * Note that for MSI this could cause a stray interrupt report
3104 * if an interrupt landed in the time between writing IIR and
3105 * the posting read. This should be rare enough to never
3106 * trigger the 99% of 100,000 interrupts test for disabling
3107 * stray interrupts.
3108 */
3109 ret = IRQ_HANDLED;
3110 iir = new_iir;
3111 } while (iir & ~flip_mask);
3112
3113 i915_update_dri1_breadcrumb(dev);
3114
3115 return ret;
3116 }
3117
3118 static void i915_irq_uninstall(struct drm_device * dev)
3119 {
3120 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3121 int pipe;
3122
3123 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3124
3125 if (I915_HAS_HOTPLUG(dev)) {
3126 I915_WRITE(PORT_HOTPLUG_EN, 0);
3127 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3128 }
3129
3130 I915_WRITE16(HWSTAM, 0xffff);
3131 for_each_pipe(pipe) {
3132 /* Clear enable bits; then clear status bits */
3133 I915_WRITE(PIPESTAT(pipe), 0);
3134 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3135 }
3136 I915_WRITE(IMR, 0xffffffff);
3137 I915_WRITE(IER, 0x0);
3138
3139 I915_WRITE(IIR, I915_READ(IIR));
3140 }
3141
3142 static void i965_irq_preinstall(struct drm_device * dev)
3143 {
3144 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3145 int pipe;
3146
3147 atomic_set(&dev_priv->irq_received, 0);
3148
3149 I915_WRITE(PORT_HOTPLUG_EN, 0);
3150 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3151
3152 I915_WRITE(HWSTAM, 0xeffe);
3153 for_each_pipe(pipe)
3154 I915_WRITE(PIPESTAT(pipe), 0);
3155 I915_WRITE(IMR, 0xffffffff);
3156 I915_WRITE(IER, 0x0);
3157 POSTING_READ(IER);
3158 }
3159
3160 static int i965_irq_postinstall(struct drm_device *dev)
3161 {
3162 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3163 u32 enable_mask;
3164 u32 error_mask;
3165
3166 /* Unmask the interrupts that we always want on. */
3167 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
3168 I915_DISPLAY_PORT_INTERRUPT |
3169 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3170 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3171 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3172 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3173 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3174
3175 enable_mask = ~dev_priv->irq_mask;
3176 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3177 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3178 enable_mask |= I915_USER_INTERRUPT;
3179
3180 if (IS_G4X(dev))
3181 enable_mask |= I915_BSD_USER_INTERRUPT;
3182
3183 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
3184
3185 /*
3186 * Enable some error detection, note the instruction error mask
3187 * bit is reserved, so we leave it masked.
3188 */
3189 if (IS_G4X(dev)) {
3190 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3191 GM45_ERROR_MEM_PRIV |
3192 GM45_ERROR_CP_PRIV |
3193 I915_ERROR_MEMORY_REFRESH);
3194 } else {
3195 error_mask = ~(I915_ERROR_PAGE_TABLE |
3196 I915_ERROR_MEMORY_REFRESH);
3197 }
3198 I915_WRITE(EMR, error_mask);
3199
3200 I915_WRITE(IMR, dev_priv->irq_mask);
3201 I915_WRITE(IER, enable_mask);
3202 POSTING_READ(IER);
3203
3204 I915_WRITE(PORT_HOTPLUG_EN, 0);
3205 POSTING_READ(PORT_HOTPLUG_EN);
3206
3207 i915_enable_asle_pipestat(dev);
3208
3209 return 0;
3210 }
3211
3212 static void i915_hpd_irq_setup(struct drm_device *dev)
3213 {
3214 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3215 struct drm_mode_config *mode_config = &dev->mode_config;
3216 struct intel_encoder *intel_encoder;
3217 u32 hotplug_en;
3218
3219 if (I915_HAS_HOTPLUG(dev)) {
3220 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3221 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3222 /* Note HDMI and DP share hotplug bits */
3223 /* enable bits are the same for all generations */
3224 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3225 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3226 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
3227 /* Programming the CRT detection parameters tends
3228 to generate a spurious hotplug event about three
3229 seconds later. So just do it once.
3230 */
3231 if (IS_G4X(dev))
3232 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
3233 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
3234 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
3235
3236 /* Ignore TV since it's buggy */
3237 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3238 }
3239 }
3240
3241 static irqreturn_t i965_irq_handler(int irq, void *arg)
3242 {
3243 struct drm_device *dev = (struct drm_device *) arg;
3244 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3245 u32 iir, new_iir;
3246 u32 pipe_stats[I915_MAX_PIPES];
3247 unsigned long irqflags;
3248 int irq_received;
3249 int ret = IRQ_NONE, pipe;
3250 u32 flip_mask =
3251 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3252 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3253
3254 atomic_inc(&dev_priv->irq_received);
3255
3256 iir = I915_READ(IIR);
3257
3258 for (;;) {
3259 bool blc_event = false;
3260
3261 irq_received = (iir & ~flip_mask) != 0;
3262
3263 /* Can't rely on pipestat interrupt bit in iir as it might
3264 * have been cleared after the pipestat interrupt was received.
3265 * It doesn't set the bit in iir again, but it still produces
3266 * interrupts (for non-MSI).
3267 */
3268 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3269 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3270 i915_handle_error(dev, false);
3271
3272 for_each_pipe(pipe) {
3273 int reg = PIPESTAT(pipe);
3274 pipe_stats[pipe] = I915_READ(reg);
3275
3276 /*
3277 * Clear the PIPE*STAT regs before the IIR
3278 */
3279 if (pipe_stats[pipe] & 0x8000ffff) {
3280 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3281 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3282 pipe_name(pipe));
3283 I915_WRITE(reg, pipe_stats[pipe]);
3284 irq_received = 1;
3285 }
3286 }
3287 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3288
3289 if (!irq_received)
3290 break;
3291
3292 ret = IRQ_HANDLED;
3293
3294 /* Consume port. Then clear IIR or we'll miss events */
3295 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
3296 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3297 u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
3298 HOTPLUG_INT_STATUS_G4X :
3299 HOTPLUG_INT_STATUS_I965);
3300
3301 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3302 hotplug_status);
3303 if (hotplug_trigger) {
3304 if (hotplug_irq_storm_detect(dev, hotplug_trigger,
3305 IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i965))
3306 i915_hpd_irq_setup(dev);
3307 queue_work(dev_priv->wq,
3308 &dev_priv->hotplug_work);
3309 }
3310 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3311 I915_READ(PORT_HOTPLUG_STAT);
3312 }
3313
3314 I915_WRITE(IIR, iir & ~flip_mask);
3315 new_iir = I915_READ(IIR); /* Flush posted writes */
3316
3317 if (iir & I915_USER_INTERRUPT)
3318 notify_ring(dev, &dev_priv->ring[RCS]);
3319 if (iir & I915_BSD_USER_INTERRUPT)
3320 notify_ring(dev, &dev_priv->ring[VCS]);
3321
3322 for_each_pipe(pipe) {
3323 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
3324 i915_handle_vblank(dev, pipe, pipe, iir))
3325 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
3326
3327 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3328 blc_event = true;
3329 }
3330
3331
3332 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3333 intel_opregion_asle_intr(dev);
3334
3335 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3336 gmbus_irq_handler(dev);
3337
3338 /* With MSI, interrupts are only generated when iir
3339 * transitions from zero to nonzero. If another bit got
3340 * set while we were handling the existing iir bits, then
3341 * we would never get another interrupt.
3342 *
3343 * This is fine on non-MSI as well, as if we hit this path
3344 * we avoid exiting the interrupt handler only to generate
3345 * another one.
3346 *
3347 * Note that for MSI this could cause a stray interrupt report
3348 * if an interrupt landed in the time between writing IIR and
3349 * the posting read. This should be rare enough to never
3350 * trigger the 99% of 100,000 interrupts test for disabling
3351 * stray interrupts.
3352 */
3353 iir = new_iir;
3354 }
3355
3356 i915_update_dri1_breadcrumb(dev);
3357
3358 return ret;
3359 }
3360
3361 static void i965_irq_uninstall(struct drm_device * dev)
3362 {
3363 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3364 int pipe;
3365
3366 if (!dev_priv)
3367 return;
3368
3369 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3370
3371 I915_WRITE(PORT_HOTPLUG_EN, 0);
3372 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3373
3374 I915_WRITE(HWSTAM, 0xffffffff);
3375 for_each_pipe(pipe)
3376 I915_WRITE(PIPESTAT(pipe), 0);
3377 I915_WRITE(IMR, 0xffffffff);
3378 I915_WRITE(IER, 0x0);
3379
3380 for_each_pipe(pipe)
3381 I915_WRITE(PIPESTAT(pipe),
3382 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3383 I915_WRITE(IIR, I915_READ(IIR));
3384 }
3385
3386 static void i915_reenable_hotplug_timer_func(unsigned long data)
3387 {
3388 drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
3389 struct drm_device *dev = dev_priv->dev;
3390 struct drm_mode_config *mode_config = &dev->mode_config;
3391 unsigned long irqflags;
3392 int i;
3393
3394 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3395 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3396 struct drm_connector *connector;
3397
3398 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3399 continue;
3400
3401 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3402
3403 list_for_each_entry(connector, &mode_config->connector_list, head) {
3404 struct intel_connector *intel_connector = to_intel_connector(connector);
3405
3406 if (intel_connector->encoder->hpd_pin == i) {
3407 if (connector->polled != intel_connector->polled)
3408 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3409 drm_get_connector_name(connector));
3410 connector->polled = intel_connector->polled;
3411 if (!connector->polled)
3412 connector->polled = DRM_CONNECTOR_POLL_HPD;
3413 }
3414 }
3415 }
3416 if (dev_priv->display.hpd_irq_setup)
3417 dev_priv->display.hpd_irq_setup(dev);
3418 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3419 }
3420
3421 void intel_irq_init(struct drm_device *dev)
3422 {
3423 struct drm_i915_private *dev_priv = dev->dev_private;
3424
3425 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
3426 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
3427 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
3428 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
3429
3430 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3431 i915_hangcheck_elapsed,
3432 (unsigned long) dev);
3433 setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
3434 (unsigned long) dev_priv);
3435
3436 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
3437
3438 dev->driver->get_vblank_counter = i915_get_vblank_counter;
3439 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
3440 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
3441 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3442 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
3443 }
3444
3445 if (drm_core_check_feature(dev, DRIVER_MODESET))
3446 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
3447 else
3448 dev->driver->get_vblank_timestamp = NULL;
3449 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3450
3451 if (IS_VALLEYVIEW(dev)) {
3452 dev->driver->irq_handler = valleyview_irq_handler;
3453 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3454 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3455 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3456 dev->driver->enable_vblank = valleyview_enable_vblank;
3457 dev->driver->disable_vblank = valleyview_disable_vblank;
3458 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3459 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
3460 /* Share pre & uninstall handlers with ILK/SNB */
3461 dev->driver->irq_handler = ivybridge_irq_handler;
3462 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3463 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
3464 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3465 dev->driver->enable_vblank = ivybridge_enable_vblank;
3466 dev->driver->disable_vblank = ivybridge_disable_vblank;
3467 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3468 } else if (HAS_PCH_SPLIT(dev)) {
3469 dev->driver->irq_handler = ironlake_irq_handler;
3470 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3471 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3472 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3473 dev->driver->enable_vblank = ironlake_enable_vblank;
3474 dev->driver->disable_vblank = ironlake_disable_vblank;
3475 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3476 } else {
3477 if (INTEL_INFO(dev)->gen == 2) {
3478 dev->driver->irq_preinstall = i8xx_irq_preinstall;
3479 dev->driver->irq_postinstall = i8xx_irq_postinstall;
3480 dev->driver->irq_handler = i8xx_irq_handler;
3481 dev->driver->irq_uninstall = i8xx_irq_uninstall;
3482 } else if (INTEL_INFO(dev)->gen == 3) {
3483 dev->driver->irq_preinstall = i915_irq_preinstall;
3484 dev->driver->irq_postinstall = i915_irq_postinstall;
3485 dev->driver->irq_uninstall = i915_irq_uninstall;
3486 dev->driver->irq_handler = i915_irq_handler;
3487 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3488 } else {
3489 dev->driver->irq_preinstall = i965_irq_preinstall;
3490 dev->driver->irq_postinstall = i965_irq_postinstall;
3491 dev->driver->irq_uninstall = i965_irq_uninstall;
3492 dev->driver->irq_handler = i965_irq_handler;
3493 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3494 }
3495 dev->driver->enable_vblank = i915_enable_vblank;
3496 dev->driver->disable_vblank = i915_disable_vblank;
3497 }
3498 }
3499
3500 void intel_hpd_init(struct drm_device *dev)
3501 {
3502 struct drm_i915_private *dev_priv = dev->dev_private;
3503 struct drm_mode_config *mode_config = &dev->mode_config;
3504 struct drm_connector *connector;
3505 int i;
3506
3507 for (i = 1; i < HPD_NUM_PINS; i++) {
3508 dev_priv->hpd_stats[i].hpd_cnt = 0;
3509 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3510 }
3511 list_for_each_entry(connector, &mode_config->connector_list, head) {
3512 struct intel_connector *intel_connector = to_intel_connector(connector);
3513 connector->polled = intel_connector->polled;
3514 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3515 connector->polled = DRM_CONNECTOR_POLL_HPD;
3516 }
3517 if (dev_priv->display.hpd_irq_setup)
3518 dev_priv->display.hpd_irq_setup(dev);
3519 }
Linux kernel - Deliverables
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