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0acadc5e02d26b47995328628a4cdb89998aa142
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include "drmP.h"
34 #include "drm.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "intel_drv.h"
39
40 /* For display hotplug interrupt */
41 static void
42 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
43 {
44 if ((dev_priv->irq_mask & mask) != 0) {
45 dev_priv->irq_mask &= ~mask;
46 I915_WRITE(DEIMR, dev_priv->irq_mask);
47 POSTING_READ(DEIMR);
48 }
49 }
50
51 static inline void
52 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
53 {
54 if ((dev_priv->irq_mask & mask) != mask) {
55 dev_priv->irq_mask |= mask;
56 I915_WRITE(DEIMR, dev_priv->irq_mask);
57 POSTING_READ(DEIMR);
58 }
59 }
60
61 void
62 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
63 {
64 if ((dev_priv->pipestat[pipe] & mask) != mask) {
65 u32 reg = PIPESTAT(pipe);
66
67 dev_priv->pipestat[pipe] |= mask;
68 /* Enable the interrupt, clear any pending status */
69 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
70 POSTING_READ(reg);
71 }
72 }
73
74 void
75 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
76 {
77 if ((dev_priv->pipestat[pipe] & mask) != 0) {
78 u32 reg = PIPESTAT(pipe);
79
80 dev_priv->pipestat[pipe] &= ~mask;
81 I915_WRITE(reg, dev_priv->pipestat[pipe]);
82 POSTING_READ(reg);
83 }
84 }
85
86 /**
87 * intel_enable_asle - enable ASLE interrupt for OpRegion
88 */
89 void intel_enable_asle(struct drm_device *dev)
90 {
91 drm_i915_private_t *dev_priv = dev->dev_private;
92 unsigned long irqflags;
93
94 /* FIXME: opregion/asle for VLV */
95 if (IS_VALLEYVIEW(dev))
96 return;
97
98 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
99
100 if (HAS_PCH_SPLIT(dev))
101 ironlake_enable_display_irq(dev_priv, DE_GSE);
102 else {
103 i915_enable_pipestat(dev_priv, 1,
104 PIPE_LEGACY_BLC_EVENT_ENABLE);
105 if (INTEL_INFO(dev)->gen >= 4)
106 i915_enable_pipestat(dev_priv, 0,
107 PIPE_LEGACY_BLC_EVENT_ENABLE);
108 }
109
110 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
111 }
112
113 /**
114 * i915_pipe_enabled - check if a pipe is enabled
115 * @dev: DRM device
116 * @pipe: pipe to check
117 *
118 * Reading certain registers when the pipe is disabled can hang the chip.
119 * Use this routine to make sure the PLL is running and the pipe is active
120 * before reading such registers if unsure.
121 */
122 static int
123 i915_pipe_enabled(struct drm_device *dev, int pipe)
124 {
125 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
126 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
127 }
128
129 /* Called from drm generic code, passed a 'crtc', which
130 * we use as a pipe index
131 */
132 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
133 {
134 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
135 unsigned long high_frame;
136 unsigned long low_frame;
137 u32 high1, high2, low;
138
139 if (!i915_pipe_enabled(dev, pipe)) {
140 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
141 "pipe %c\n", pipe_name(pipe));
142 return 0;
143 }
144
145 high_frame = PIPEFRAME(pipe);
146 low_frame = PIPEFRAMEPIXEL(pipe);
147
148 /*
149 * High & low register fields aren't synchronized, so make sure
150 * we get a low value that's stable across two reads of the high
151 * register.
152 */
153 do {
154 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
155 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
156 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
157 } while (high1 != high2);
158
159 high1 >>= PIPE_FRAME_HIGH_SHIFT;
160 low >>= PIPE_FRAME_LOW_SHIFT;
161 return (high1 << 8) | low;
162 }
163
164 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
165 {
166 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
167 int reg = PIPE_FRMCOUNT_GM45(pipe);
168
169 if (!i915_pipe_enabled(dev, pipe)) {
170 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
171 "pipe %c\n", pipe_name(pipe));
172 return 0;
173 }
174
175 return I915_READ(reg);
176 }
177
178 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
179 int *vpos, int *hpos)
180 {
181 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
182 u32 vbl = 0, position = 0;
183 int vbl_start, vbl_end, htotal, vtotal;
184 bool in_vbl = true;
185 int ret = 0;
186
187 if (!i915_pipe_enabled(dev, pipe)) {
188 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
189 "pipe %c\n", pipe_name(pipe));
190 return 0;
191 }
192
193 /* Get vtotal. */
194 vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
195
196 if (INTEL_INFO(dev)->gen >= 4) {
197 /* No obvious pixelcount register. Only query vertical
198 * scanout position from Display scan line register.
199 */
200 position = I915_READ(PIPEDSL(pipe));
201
202 /* Decode into vertical scanout position. Don't have
203 * horizontal scanout position.
204 */
205 *vpos = position & 0x1fff;
206 *hpos = 0;
207 } else {
208 /* Have access to pixelcount since start of frame.
209 * We can split this into vertical and horizontal
210 * scanout position.
211 */
212 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
213
214 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
215 *vpos = position / htotal;
216 *hpos = position - (*vpos * htotal);
217 }
218
219 /* Query vblank area. */
220 vbl = I915_READ(VBLANK(pipe));
221
222 /* Test position against vblank region. */
223 vbl_start = vbl & 0x1fff;
224 vbl_end = (vbl >> 16) & 0x1fff;
225
226 if ((*vpos < vbl_start) || (*vpos > vbl_end))
227 in_vbl = false;
228
229 /* Inside "upper part" of vblank area? Apply corrective offset: */
230 if (in_vbl && (*vpos >= vbl_start))
231 *vpos = *vpos - vtotal;
232
233 /* Readouts valid? */
234 if (vbl > 0)
235 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
236
237 /* In vblank? */
238 if (in_vbl)
239 ret |= DRM_SCANOUTPOS_INVBL;
240
241 return ret;
242 }
243
244 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
245 int *max_error,
246 struct timeval *vblank_time,
247 unsigned flags)
248 {
249 struct drm_i915_private *dev_priv = dev->dev_private;
250 struct drm_crtc *crtc;
251
252 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
253 DRM_ERROR("Invalid crtc %d\n", pipe);
254 return -EINVAL;
255 }
256
257 /* Get drm_crtc to timestamp: */
258 crtc = intel_get_crtc_for_pipe(dev, pipe);
259 if (crtc == NULL) {
260 DRM_ERROR("Invalid crtc %d\n", pipe);
261 return -EINVAL;
262 }
263
264 if (!crtc->enabled) {
265 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
266 return -EBUSY;
267 }
268
269 /* Helper routine in DRM core does all the work: */
270 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
271 vblank_time, flags,
272 crtc);
273 }
274
275 /*
276 * Handle hotplug events outside the interrupt handler proper.
277 */
278 static void i915_hotplug_work_func(struct work_struct *work)
279 {
280 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
281 hotplug_work);
282 struct drm_device *dev = dev_priv->dev;
283 struct drm_mode_config *mode_config = &dev->mode_config;
284 struct intel_encoder *encoder;
285
286 mutex_lock(&mode_config->mutex);
287 DRM_DEBUG_KMS("running encoder hotplug functions\n");
288
289 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
290 if (encoder->hot_plug)
291 encoder->hot_plug(encoder);
292
293 mutex_unlock(&mode_config->mutex);
294
295 /* Just fire off a uevent and let userspace tell us what to do */
296 drm_helper_hpd_irq_event(dev);
297 }
298
299 static void i915_handle_rps_change(struct drm_device *dev)
300 {
301 drm_i915_private_t *dev_priv = dev->dev_private;
302 u32 busy_up, busy_down, max_avg, min_avg;
303 u8 new_delay = dev_priv->cur_delay;
304
305 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
306 busy_up = I915_READ(RCPREVBSYTUPAVG);
307 busy_down = I915_READ(RCPREVBSYTDNAVG);
308 max_avg = I915_READ(RCBMAXAVG);
309 min_avg = I915_READ(RCBMINAVG);
310
311 /* Handle RCS change request from hw */
312 if (busy_up > max_avg) {
313 if (dev_priv->cur_delay != dev_priv->max_delay)
314 new_delay = dev_priv->cur_delay - 1;
315 if (new_delay < dev_priv->max_delay)
316 new_delay = dev_priv->max_delay;
317 } else if (busy_down < min_avg) {
318 if (dev_priv->cur_delay != dev_priv->min_delay)
319 new_delay = dev_priv->cur_delay + 1;
320 if (new_delay > dev_priv->min_delay)
321 new_delay = dev_priv->min_delay;
322 }
323
324 if (ironlake_set_drps(dev, new_delay))
325 dev_priv->cur_delay = new_delay;
326
327 return;
328 }
329
330 static void notify_ring(struct drm_device *dev,
331 struct intel_ring_buffer *ring)
332 {
333 struct drm_i915_private *dev_priv = dev->dev_private;
334 u32 seqno;
335
336 if (ring->obj == NULL)
337 return;
338
339 seqno = ring->get_seqno(ring);
340 trace_i915_gem_request_complete(ring, seqno);
341
342 ring->irq_seqno = seqno;
343 wake_up_all(&ring->irq_queue);
344 if (i915_enable_hangcheck) {
345 dev_priv->hangcheck_count = 0;
346 mod_timer(&dev_priv->hangcheck_timer,
347 jiffies +
348 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
349 }
350 }
351
352 static void gen6_pm_rps_work(struct work_struct *work)
353 {
354 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
355 rps_work);
356 u8 new_delay = dev_priv->cur_delay;
357 u32 pm_iir, pm_imr;
358
359 spin_lock_irq(&dev_priv->rps_lock);
360 pm_iir = dev_priv->pm_iir;
361 dev_priv->pm_iir = 0;
362 pm_imr = I915_READ(GEN6_PMIMR);
363 I915_WRITE(GEN6_PMIMR, 0);
364 spin_unlock_irq(&dev_priv->rps_lock);
365
366 if (!pm_iir)
367 return;
368
369 mutex_lock(&dev_priv->dev->struct_mutex);
370 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
371 if (dev_priv->cur_delay != dev_priv->max_delay)
372 new_delay = dev_priv->cur_delay + 1;
373 if (new_delay > dev_priv->max_delay)
374 new_delay = dev_priv->max_delay;
375 } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
376 gen6_gt_force_wake_get(dev_priv);
377 if (dev_priv->cur_delay != dev_priv->min_delay)
378 new_delay = dev_priv->cur_delay - 1;
379 if (new_delay < dev_priv->min_delay) {
380 new_delay = dev_priv->min_delay;
381 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
382 I915_READ(GEN6_RP_INTERRUPT_LIMITS) |
383 ((new_delay << 16) & 0x3f0000));
384 } else {
385 /* Make sure we continue to get down interrupts
386 * until we hit the minimum frequency */
387 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
388 I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
389 }
390 gen6_gt_force_wake_put(dev_priv);
391 }
392
393 gen6_set_rps(dev_priv->dev, new_delay);
394 dev_priv->cur_delay = new_delay;
395
396 /*
397 * rps_lock not held here because clearing is non-destructive. There is
398 * an *extremely* unlikely race with gen6_rps_enable() that is prevented
399 * by holding struct_mutex for the duration of the write.
400 */
401 mutex_unlock(&dev_priv->dev->struct_mutex);
402 }
403
404 static void snb_gt_irq_handler(struct drm_device *dev,
405 struct drm_i915_private *dev_priv,
406 u32 gt_iir)
407 {
408
409 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
410 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
411 notify_ring(dev, &dev_priv->ring[RCS]);
412 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
413 notify_ring(dev, &dev_priv->ring[VCS]);
414 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
415 notify_ring(dev, &dev_priv->ring[BCS]);
416
417 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
418 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
419 GT_RENDER_CS_ERROR_INTERRUPT)) {
420 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
421 i915_handle_error(dev, false);
422 }
423 }
424
425 static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
426 u32 pm_iir)
427 {
428 unsigned long flags;
429
430 /*
431 * IIR bits should never already be set because IMR should
432 * prevent an interrupt from being shown in IIR. The warning
433 * displays a case where we've unsafely cleared
434 * dev_priv->pm_iir. Although missing an interrupt of the same
435 * type is not a problem, it displays a problem in the logic.
436 *
437 * The mask bit in IMR is cleared by rps_work.
438 */
439
440 spin_lock_irqsave(&dev_priv->rps_lock, flags);
441 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
442 dev_priv->pm_iir |= pm_iir;
443 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
444 POSTING_READ(GEN6_PMIMR);
445 spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
446
447 queue_work(dev_priv->wq, &dev_priv->rps_work);
448 }
449
450 static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
451 {
452 struct drm_device *dev = (struct drm_device *) arg;
453 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
454 u32 iir, gt_iir, pm_iir;
455 irqreturn_t ret = IRQ_NONE;
456 unsigned long irqflags;
457 int pipe;
458 u32 pipe_stats[I915_MAX_PIPES];
459 u32 vblank_status;
460 int vblank = 0;
461 bool blc_event;
462
463 atomic_inc(&dev_priv->irq_received);
464
465 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS |
466 PIPE_VBLANK_INTERRUPT_STATUS;
467
468 while (true) {
469 iir = I915_READ(VLV_IIR);
470 gt_iir = I915_READ(GTIIR);
471 pm_iir = I915_READ(GEN6_PMIIR);
472
473 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
474 goto out;
475
476 ret = IRQ_HANDLED;
477
478 snb_gt_irq_handler(dev, dev_priv, gt_iir);
479
480 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
481 for_each_pipe(pipe) {
482 int reg = PIPESTAT(pipe);
483 pipe_stats[pipe] = I915_READ(reg);
484
485 /*
486 * Clear the PIPE*STAT regs before the IIR
487 */
488 if (pipe_stats[pipe] & 0x8000ffff) {
489 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
490 DRM_DEBUG_DRIVER("pipe %c underrun\n",
491 pipe_name(pipe));
492 I915_WRITE(reg, pipe_stats[pipe]);
493 }
494 }
495 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
496
497 /* Consume port. Then clear IIR or we'll miss events */
498 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
499 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
500
501 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
502 hotplug_status);
503 if (hotplug_status & dev_priv->hotplug_supported_mask)
504 queue_work(dev_priv->wq,
505 &dev_priv->hotplug_work);
506
507 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
508 I915_READ(PORT_HOTPLUG_STAT);
509 }
510
511
512 if (iir & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT) {
513 drm_handle_vblank(dev, 0);
514 vblank++;
515 intel_finish_page_flip(dev, 0);
516 }
517
518 if (iir & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) {
519 drm_handle_vblank(dev, 1);
520 vblank++;
521 intel_finish_page_flip(dev, 0);
522 }
523
524 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
525 blc_event = true;
526
527 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
528 gen6_queue_rps_work(dev_priv, pm_iir);
529
530 I915_WRITE(GTIIR, gt_iir);
531 I915_WRITE(GEN6_PMIIR, pm_iir);
532 I915_WRITE(VLV_IIR, iir);
533 }
534
535 out:
536 return ret;
537 }
538
539 static void pch_irq_handler(struct drm_device *dev)
540 {
541 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
542 u32 pch_iir;
543 int pipe;
544
545 pch_iir = I915_READ(SDEIIR);
546
547 if (pch_iir & SDE_AUDIO_POWER_MASK)
548 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
549 (pch_iir & SDE_AUDIO_POWER_MASK) >>
550 SDE_AUDIO_POWER_SHIFT);
551
552 if (pch_iir & SDE_GMBUS)
553 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
554
555 if (pch_iir & SDE_AUDIO_HDCP_MASK)
556 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
557
558 if (pch_iir & SDE_AUDIO_TRANS_MASK)
559 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
560
561 if (pch_iir & SDE_POISON)
562 DRM_ERROR("PCH poison interrupt\n");
563
564 if (pch_iir & SDE_FDI_MASK)
565 for_each_pipe(pipe)
566 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
567 pipe_name(pipe),
568 I915_READ(FDI_RX_IIR(pipe)));
569
570 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
571 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
572
573 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
574 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
575
576 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
577 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
578 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
579 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
580 }
581
582 static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
583 {
584 struct drm_device *dev = (struct drm_device *) arg;
585 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
586 int ret = IRQ_NONE;
587 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
588 struct drm_i915_master_private *master_priv;
589
590 atomic_inc(&dev_priv->irq_received);
591
592 /* disable master interrupt before clearing iir */
593 de_ier = I915_READ(DEIER);
594 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
595 POSTING_READ(DEIER);
596
597 de_iir = I915_READ(DEIIR);
598 gt_iir = I915_READ(GTIIR);
599 pch_iir = I915_READ(SDEIIR);
600 pm_iir = I915_READ(GEN6_PMIIR);
601
602 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && pm_iir == 0)
603 goto done;
604
605 ret = IRQ_HANDLED;
606
607 if (dev->primary->master) {
608 master_priv = dev->primary->master->driver_priv;
609 if (master_priv->sarea_priv)
610 master_priv->sarea_priv->last_dispatch =
611 READ_BREADCRUMB(dev_priv);
612 }
613
614 snb_gt_irq_handler(dev, dev_priv, gt_iir);
615
616 if (de_iir & DE_GSE_IVB)
617 intel_opregion_gse_intr(dev);
618
619 if (de_iir & DE_PLANEA_FLIP_DONE_IVB) {
620 intel_prepare_page_flip(dev, 0);
621 intel_finish_page_flip_plane(dev, 0);
622 }
623
624 if (de_iir & DE_PLANEB_FLIP_DONE_IVB) {
625 intel_prepare_page_flip(dev, 1);
626 intel_finish_page_flip_plane(dev, 1);
627 }
628
629 if (de_iir & DE_PIPEA_VBLANK_IVB)
630 drm_handle_vblank(dev, 0);
631
632 if (de_iir & DE_PIPEB_VBLANK_IVB)
633 drm_handle_vblank(dev, 1);
634
635 /* check event from PCH */
636 if (de_iir & DE_PCH_EVENT_IVB) {
637 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
638 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
639 pch_irq_handler(dev);
640 }
641
642 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
643 gen6_queue_rps_work(dev_priv, pm_iir);
644
645 /* should clear PCH hotplug event before clear CPU irq */
646 I915_WRITE(SDEIIR, pch_iir);
647 I915_WRITE(GTIIR, gt_iir);
648 I915_WRITE(DEIIR, de_iir);
649 I915_WRITE(GEN6_PMIIR, pm_iir);
650
651 done:
652 I915_WRITE(DEIER, de_ier);
653 POSTING_READ(DEIER);
654
655 return ret;
656 }
657
658 static void ilk_gt_irq_handler(struct drm_device *dev,
659 struct drm_i915_private *dev_priv,
660 u32 gt_iir)
661 {
662 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
663 notify_ring(dev, &dev_priv->ring[RCS]);
664 if (gt_iir & GT_BSD_USER_INTERRUPT)
665 notify_ring(dev, &dev_priv->ring[VCS]);
666 }
667
668 static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
669 {
670 struct drm_device *dev = (struct drm_device *) arg;
671 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
672 int ret = IRQ_NONE;
673 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
674 u32 hotplug_mask;
675 struct drm_i915_master_private *master_priv;
676
677 atomic_inc(&dev_priv->irq_received);
678
679 /* disable master interrupt before clearing iir */
680 de_ier = I915_READ(DEIER);
681 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
682 POSTING_READ(DEIER);
683
684 de_iir = I915_READ(DEIIR);
685 gt_iir = I915_READ(GTIIR);
686 pch_iir = I915_READ(SDEIIR);
687 pm_iir = I915_READ(GEN6_PMIIR);
688
689 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
690 (!IS_GEN6(dev) || pm_iir == 0))
691 goto done;
692
693 if (HAS_PCH_CPT(dev))
694 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
695 else
696 hotplug_mask = SDE_HOTPLUG_MASK;
697
698 ret = IRQ_HANDLED;
699
700 if (dev->primary->master) {
701 master_priv = dev->primary->master->driver_priv;
702 if (master_priv->sarea_priv)
703 master_priv->sarea_priv->last_dispatch =
704 READ_BREADCRUMB(dev_priv);
705 }
706
707 if (IS_GEN5(dev))
708 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
709 else
710 snb_gt_irq_handler(dev, dev_priv, gt_iir);
711
712 if (de_iir & DE_GSE)
713 intel_opregion_gse_intr(dev);
714
715 if (de_iir & DE_PLANEA_FLIP_DONE) {
716 intel_prepare_page_flip(dev, 0);
717 intel_finish_page_flip_plane(dev, 0);
718 }
719
720 if (de_iir & DE_PLANEB_FLIP_DONE) {
721 intel_prepare_page_flip(dev, 1);
722 intel_finish_page_flip_plane(dev, 1);
723 }
724
725 if (de_iir & DE_PIPEA_VBLANK)
726 drm_handle_vblank(dev, 0);
727
728 if (de_iir & DE_PIPEB_VBLANK)
729 drm_handle_vblank(dev, 1);
730
731 /* check event from PCH */
732 if (de_iir & DE_PCH_EVENT) {
733 if (pch_iir & hotplug_mask)
734 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
735 pch_irq_handler(dev);
736 }
737
738 if (de_iir & DE_PCU_EVENT) {
739 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
740 i915_handle_rps_change(dev);
741 }
742
743 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
744 gen6_queue_rps_work(dev_priv, pm_iir);
745
746 /* should clear PCH hotplug event before clear CPU irq */
747 I915_WRITE(SDEIIR, pch_iir);
748 I915_WRITE(GTIIR, gt_iir);
749 I915_WRITE(DEIIR, de_iir);
750 I915_WRITE(GEN6_PMIIR, pm_iir);
751
752 done:
753 I915_WRITE(DEIER, de_ier);
754 POSTING_READ(DEIER);
755
756 return ret;
757 }
758
759 /**
760 * i915_error_work_func - do process context error handling work
761 * @work: work struct
762 *
763 * Fire an error uevent so userspace can see that a hang or error
764 * was detected.
765 */
766 static void i915_error_work_func(struct work_struct *work)
767 {
768 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
769 error_work);
770 struct drm_device *dev = dev_priv->dev;
771 char *error_event[] = { "ERROR=1", NULL };
772 char *reset_event[] = { "RESET=1", NULL };
773 char *reset_done_event[] = { "ERROR=0", NULL };
774
775 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
776
777 if (atomic_read(&dev_priv->mm.wedged)) {
778 DRM_DEBUG_DRIVER("resetting chip\n");
779 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
780 if (!i915_reset(dev, GRDOM_RENDER)) {
781 atomic_set(&dev_priv->mm.wedged, 0);
782 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
783 }
784 complete_all(&dev_priv->error_completion);
785 }
786 }
787
788 #ifdef CONFIG_DEBUG_FS
789 static struct drm_i915_error_object *
790 i915_error_object_create(struct drm_i915_private *dev_priv,
791 struct drm_i915_gem_object *src)
792 {
793 struct drm_i915_error_object *dst;
794 int page, page_count;
795 u32 reloc_offset;
796
797 if (src == NULL || src->pages == NULL)
798 return NULL;
799
800 page_count = src->base.size / PAGE_SIZE;
801
802 dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC);
803 if (dst == NULL)
804 return NULL;
805
806 reloc_offset = src->gtt_offset;
807 for (page = 0; page < page_count; page++) {
808 unsigned long flags;
809 void *d;
810
811 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
812 if (d == NULL)
813 goto unwind;
814
815 local_irq_save(flags);
816 if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
817 src->has_global_gtt_mapping) {
818 void __iomem *s;
819
820 /* Simply ignore tiling or any overlapping fence.
821 * It's part of the error state, and this hopefully
822 * captures what the GPU read.
823 */
824
825 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
826 reloc_offset);
827 memcpy_fromio(d, s, PAGE_SIZE);
828 io_mapping_unmap_atomic(s);
829 } else {
830 void *s;
831
832 drm_clflush_pages(&src->pages[page], 1);
833
834 s = kmap_atomic(src->pages[page]);
835 memcpy(d, s, PAGE_SIZE);
836 kunmap_atomic(s);
837
838 drm_clflush_pages(&src->pages[page], 1);
839 }
840 local_irq_restore(flags);
841
842 dst->pages[page] = d;
843
844 reloc_offset += PAGE_SIZE;
845 }
846 dst->page_count = page_count;
847 dst->gtt_offset = src->gtt_offset;
848
849 return dst;
850
851 unwind:
852 while (page--)
853 kfree(dst->pages[page]);
854 kfree(dst);
855 return NULL;
856 }
857
858 static void
859 i915_error_object_free(struct drm_i915_error_object *obj)
860 {
861 int page;
862
863 if (obj == NULL)
864 return;
865
866 for (page = 0; page < obj->page_count; page++)
867 kfree(obj->pages[page]);
868
869 kfree(obj);
870 }
871
872 static void
873 i915_error_state_free(struct drm_device *dev,
874 struct drm_i915_error_state *error)
875 {
876 int i;
877
878 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
879 i915_error_object_free(error->ring[i].batchbuffer);
880 i915_error_object_free(error->ring[i].ringbuffer);
881 kfree(error->ring[i].requests);
882 }
883
884 kfree(error->active_bo);
885 kfree(error->overlay);
886 kfree(error);
887 }
888 static void capture_bo(struct drm_i915_error_buffer *err,
889 struct drm_i915_gem_object *obj)
890 {
891 err->size = obj->base.size;
892 err->name = obj->base.name;
893 err->seqno = obj->last_rendering_seqno;
894 err->gtt_offset = obj->gtt_offset;
895 err->read_domains = obj->base.read_domains;
896 err->write_domain = obj->base.write_domain;
897 err->fence_reg = obj->fence_reg;
898 err->pinned = 0;
899 if (obj->pin_count > 0)
900 err->pinned = 1;
901 if (obj->user_pin_count > 0)
902 err->pinned = -1;
903 err->tiling = obj->tiling_mode;
904 err->dirty = obj->dirty;
905 err->purgeable = obj->madv != I915_MADV_WILLNEED;
906 err->ring = obj->ring ? obj->ring->id : -1;
907 err->cache_level = obj->cache_level;
908 }
909
910 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
911 int count, struct list_head *head)
912 {
913 struct drm_i915_gem_object *obj;
914 int i = 0;
915
916 list_for_each_entry(obj, head, mm_list) {
917 capture_bo(err++, obj);
918 if (++i == count)
919 break;
920 }
921
922 return i;
923 }
924
925 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
926 int count, struct list_head *head)
927 {
928 struct drm_i915_gem_object *obj;
929 int i = 0;
930
931 list_for_each_entry(obj, head, gtt_list) {
932 if (obj->pin_count == 0)
933 continue;
934
935 capture_bo(err++, obj);
936 if (++i == count)
937 break;
938 }
939
940 return i;
941 }
942
943 static void i915_gem_record_fences(struct drm_device *dev,
944 struct drm_i915_error_state *error)
945 {
946 struct drm_i915_private *dev_priv = dev->dev_private;
947 int i;
948
949 /* Fences */
950 switch (INTEL_INFO(dev)->gen) {
951 case 7:
952 case 6:
953 for (i = 0; i < 16; i++)
954 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
955 break;
956 case 5:
957 case 4:
958 for (i = 0; i < 16; i++)
959 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
960 break;
961 case 3:
962 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
963 for (i = 0; i < 8; i++)
964 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
965 case 2:
966 for (i = 0; i < 8; i++)
967 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
968 break;
969
970 }
971 }
972
973 static struct drm_i915_error_object *
974 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
975 struct intel_ring_buffer *ring)
976 {
977 struct drm_i915_gem_object *obj;
978 u32 seqno;
979
980 if (!ring->get_seqno)
981 return NULL;
982
983 seqno = ring->get_seqno(ring);
984 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
985 if (obj->ring != ring)
986 continue;
987
988 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
989 continue;
990
991 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
992 continue;
993
994 /* We need to copy these to an anonymous buffer as the simplest
995 * method to avoid being overwritten by userspace.
996 */
997 return i915_error_object_create(dev_priv, obj);
998 }
999
1000 return NULL;
1001 }
1002
1003 static void i915_record_ring_state(struct drm_device *dev,
1004 struct drm_i915_error_state *error,
1005 struct intel_ring_buffer *ring)
1006 {
1007 struct drm_i915_private *dev_priv = dev->dev_private;
1008
1009 if (INTEL_INFO(dev)->gen >= 6) {
1010 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
1011 error->semaphore_mboxes[ring->id][0]
1012 = I915_READ(RING_SYNC_0(ring->mmio_base));
1013 error->semaphore_mboxes[ring->id][1]
1014 = I915_READ(RING_SYNC_1(ring->mmio_base));
1015 }
1016
1017 if (INTEL_INFO(dev)->gen >= 4) {
1018 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
1019 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1020 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1021 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
1022 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
1023 if (ring->id == RCS) {
1024 error->instdone1 = I915_READ(INSTDONE1);
1025 error->bbaddr = I915_READ64(BB_ADDR);
1026 }
1027 } else {
1028 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
1029 error->ipeir[ring->id] = I915_READ(IPEIR);
1030 error->ipehr[ring->id] = I915_READ(IPEHR);
1031 error->instdone[ring->id] = I915_READ(INSTDONE);
1032 }
1033
1034 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
1035 error->seqno[ring->id] = ring->get_seqno(ring);
1036 error->acthd[ring->id] = intel_ring_get_active_head(ring);
1037 error->head[ring->id] = I915_READ_HEAD(ring);
1038 error->tail[ring->id] = I915_READ_TAIL(ring);
1039
1040 error->cpu_ring_head[ring->id] = ring->head;
1041 error->cpu_ring_tail[ring->id] = ring->tail;
1042 }
1043
1044 static void i915_gem_record_rings(struct drm_device *dev,
1045 struct drm_i915_error_state *error)
1046 {
1047 struct drm_i915_private *dev_priv = dev->dev_private;
1048 struct drm_i915_gem_request *request;
1049 int i, count;
1050
1051 for (i = 0; i < I915_NUM_RINGS; i++) {
1052 struct intel_ring_buffer *ring = &dev_priv->ring[i];
1053
1054 if (ring->obj == NULL)
1055 continue;
1056
1057 i915_record_ring_state(dev, error, ring);
1058
1059 error->ring[i].batchbuffer =
1060 i915_error_first_batchbuffer(dev_priv, ring);
1061
1062 error->ring[i].ringbuffer =
1063 i915_error_object_create(dev_priv, ring->obj);
1064
1065 count = 0;
1066 list_for_each_entry(request, &ring->request_list, list)
1067 count++;
1068
1069 error->ring[i].num_requests = count;
1070 error->ring[i].requests =
1071 kmalloc(count*sizeof(struct drm_i915_error_request),
1072 GFP_ATOMIC);
1073 if (error->ring[i].requests == NULL) {
1074 error->ring[i].num_requests = 0;
1075 continue;
1076 }
1077
1078 count = 0;
1079 list_for_each_entry(request, &ring->request_list, list) {
1080 struct drm_i915_error_request *erq;
1081
1082 erq = &error->ring[i].requests[count++];
1083 erq->seqno = request->seqno;
1084 erq->jiffies = request->emitted_jiffies;
1085 erq->tail = request->tail;
1086 }
1087 }
1088 }
1089
1090 /**
1091 * i915_capture_error_state - capture an error record for later analysis
1092 * @dev: drm device
1093 *
1094 * Should be called when an error is detected (either a hang or an error
1095 * interrupt) to capture error state from the time of the error. Fills
1096 * out a structure which becomes available in debugfs for user level tools
1097 * to pick up.
1098 */
1099 static void i915_capture_error_state(struct drm_device *dev)
1100 {
1101 struct drm_i915_private *dev_priv = dev->dev_private;
1102 struct drm_i915_gem_object *obj;
1103 struct drm_i915_error_state *error;
1104 unsigned long flags;
1105 int i, pipe;
1106
1107 spin_lock_irqsave(&dev_priv->error_lock, flags);
1108 error = dev_priv->first_error;
1109 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1110 if (error)
1111 return;
1112
1113 /* Account for pipe specific data like PIPE*STAT */
1114 error = kzalloc(sizeof(*error), GFP_ATOMIC);
1115 if (!error) {
1116 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1117 return;
1118 }
1119
1120 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1121 dev->primary->index);
1122
1123 error->eir = I915_READ(EIR);
1124 error->pgtbl_er = I915_READ(PGTBL_ER);
1125
1126 if (HAS_PCH_SPLIT(dev))
1127 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1128 else if (IS_VALLEYVIEW(dev))
1129 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1130 else if (IS_GEN2(dev))
1131 error->ier = I915_READ16(IER);
1132 else
1133 error->ier = I915_READ(IER);
1134
1135 for_each_pipe(pipe)
1136 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1137
1138 if (INTEL_INFO(dev)->gen >= 6) {
1139 error->error = I915_READ(ERROR_GEN6);
1140 error->done_reg = I915_READ(DONE_REG);
1141 }
1142
1143 i915_gem_record_fences(dev, error);
1144 i915_gem_record_rings(dev, error);
1145
1146 /* Record buffers on the active and pinned lists. */
1147 error->active_bo = NULL;
1148 error->pinned_bo = NULL;
1149
1150 i = 0;
1151 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1152 i++;
1153 error->active_bo_count = i;
1154 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
1155 if (obj->pin_count)
1156 i++;
1157 error->pinned_bo_count = i - error->active_bo_count;
1158
1159 error->active_bo = NULL;
1160 error->pinned_bo = NULL;
1161 if (i) {
1162 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
1163 GFP_ATOMIC);
1164 if (error->active_bo)
1165 error->pinned_bo =
1166 error->active_bo + error->active_bo_count;
1167 }
1168
1169 if (error->active_bo)
1170 error->active_bo_count =
1171 capture_active_bo(error->active_bo,
1172 error->active_bo_count,
1173 &dev_priv->mm.active_list);
1174
1175 if (error->pinned_bo)
1176 error->pinned_bo_count =
1177 capture_pinned_bo(error->pinned_bo,
1178 error->pinned_bo_count,
1179 &dev_priv->mm.gtt_list);
1180
1181 do_gettimeofday(&error->time);
1182
1183 error->overlay = intel_overlay_capture_error_state(dev);
1184 error->display = intel_display_capture_error_state(dev);
1185
1186 spin_lock_irqsave(&dev_priv->error_lock, flags);
1187 if (dev_priv->first_error == NULL) {
1188 dev_priv->first_error = error;
1189 error = NULL;
1190 }
1191 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1192
1193 if (error)
1194 i915_error_state_free(dev, error);
1195 }
1196
1197 void i915_destroy_error_state(struct drm_device *dev)
1198 {
1199 struct drm_i915_private *dev_priv = dev->dev_private;
1200 struct drm_i915_error_state *error;
1201 unsigned long flags;
1202
1203 spin_lock_irqsave(&dev_priv->error_lock, flags);
1204 error = dev_priv->first_error;
1205 dev_priv->first_error = NULL;
1206 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1207
1208 if (error)
1209 i915_error_state_free(dev, error);
1210 }
1211 #else
1212 #define i915_capture_error_state(x)
1213 #endif
1214
1215 static void i915_report_and_clear_eir(struct drm_device *dev)
1216 {
1217 struct drm_i915_private *dev_priv = dev->dev_private;
1218 u32 eir = I915_READ(EIR);
1219 int pipe;
1220
1221 if (!eir)
1222 return;
1223
1224 pr_err("render error detected, EIR: 0x%08x\n", eir);
1225
1226 if (IS_G4X(dev)) {
1227 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1228 u32 ipeir = I915_READ(IPEIR_I965);
1229
1230 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1231 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1232 pr_err(" INSTDONE: 0x%08x\n",
1233 I915_READ(INSTDONE_I965));
1234 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1235 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1236 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1237 I915_WRITE(IPEIR_I965, ipeir);
1238 POSTING_READ(IPEIR_I965);
1239 }
1240 if (eir & GM45_ERROR_PAGE_TABLE) {
1241 u32 pgtbl_err = I915_READ(PGTBL_ER);
1242 pr_err("page table error\n");
1243 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
1244 I915_WRITE(PGTBL_ER, pgtbl_err);
1245 POSTING_READ(PGTBL_ER);
1246 }
1247 }
1248
1249 if (!IS_GEN2(dev)) {
1250 if (eir & I915_ERROR_PAGE_TABLE) {
1251 u32 pgtbl_err = I915_READ(PGTBL_ER);
1252 pr_err("page table error\n");
1253 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
1254 I915_WRITE(PGTBL_ER, pgtbl_err);
1255 POSTING_READ(PGTBL_ER);
1256 }
1257 }
1258
1259 if (eir & I915_ERROR_MEMORY_REFRESH) {
1260 pr_err("memory refresh error:\n");
1261 for_each_pipe(pipe)
1262 pr_err("pipe %c stat: 0x%08x\n",
1263 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1264 /* pipestat has already been acked */
1265 }
1266 if (eir & I915_ERROR_INSTRUCTION) {
1267 pr_err("instruction error\n");
1268 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
1269 if (INTEL_INFO(dev)->gen < 4) {
1270 u32 ipeir = I915_READ(IPEIR);
1271
1272 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1273 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
1274 pr_err(" INSTDONE: 0x%08x\n", I915_READ(INSTDONE));
1275 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
1276 I915_WRITE(IPEIR, ipeir);
1277 POSTING_READ(IPEIR);
1278 } else {
1279 u32 ipeir = I915_READ(IPEIR_I965);
1280
1281 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1282 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1283 pr_err(" INSTDONE: 0x%08x\n",
1284 I915_READ(INSTDONE_I965));
1285 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1286 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1287 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1288 I915_WRITE(IPEIR_I965, ipeir);
1289 POSTING_READ(IPEIR_I965);
1290 }
1291 }
1292
1293 I915_WRITE(EIR, eir);
1294 POSTING_READ(EIR);
1295 eir = I915_READ(EIR);
1296 if (eir) {
1297 /*
1298 * some errors might have become stuck,
1299 * mask them.
1300 */
1301 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1302 I915_WRITE(EMR, I915_READ(EMR) | eir);
1303 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1304 }
1305 }
1306
1307 /**
1308 * i915_handle_error - handle an error interrupt
1309 * @dev: drm device
1310 *
1311 * Do some basic checking of regsiter state at error interrupt time and
1312 * dump it to the syslog. Also call i915_capture_error_state() to make
1313 * sure we get a record and make it available in debugfs. Fire a uevent
1314 * so userspace knows something bad happened (should trigger collection
1315 * of a ring dump etc.).
1316 */
1317 void i915_handle_error(struct drm_device *dev, bool wedged)
1318 {
1319 struct drm_i915_private *dev_priv = dev->dev_private;
1320
1321 i915_capture_error_state(dev);
1322 i915_report_and_clear_eir(dev);
1323
1324 if (wedged) {
1325 INIT_COMPLETION(dev_priv->error_completion);
1326 atomic_set(&dev_priv->mm.wedged, 1);
1327
1328 /*
1329 * Wakeup waiting processes so they don't hang
1330 */
1331 wake_up_all(&dev_priv->ring[RCS].irq_queue);
1332 if (HAS_BSD(dev))
1333 wake_up_all(&dev_priv->ring[VCS].irq_queue);
1334 if (HAS_BLT(dev))
1335 wake_up_all(&dev_priv->ring[BCS].irq_queue);
1336 }
1337
1338 queue_work(dev_priv->wq, &dev_priv->error_work);
1339 }
1340
1341 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1342 {
1343 drm_i915_private_t *dev_priv = dev->dev_private;
1344 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1345 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1346 struct drm_i915_gem_object *obj;
1347 struct intel_unpin_work *work;
1348 unsigned long flags;
1349 bool stall_detected;
1350
1351 /* Ignore early vblank irqs */
1352 if (intel_crtc == NULL)
1353 return;
1354
1355 spin_lock_irqsave(&dev->event_lock, flags);
1356 work = intel_crtc->unpin_work;
1357
1358 if (work == NULL || work->pending || !work->enable_stall_check) {
1359 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1360 spin_unlock_irqrestore(&dev->event_lock, flags);
1361 return;
1362 }
1363
1364 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1365 obj = work->pending_flip_obj;
1366 if (INTEL_INFO(dev)->gen >= 4) {
1367 int dspsurf = DSPSURF(intel_crtc->plane);
1368 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1369 obj->gtt_offset;
1370 } else {
1371 int dspaddr = DSPADDR(intel_crtc->plane);
1372 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1373 crtc->y * crtc->fb->pitches[0] +
1374 crtc->x * crtc->fb->bits_per_pixel/8);
1375 }
1376
1377 spin_unlock_irqrestore(&dev->event_lock, flags);
1378
1379 if (stall_detected) {
1380 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1381 intel_prepare_page_flip(dev, intel_crtc->plane);
1382 }
1383 }
1384
1385 static int i915_emit_irq(struct drm_device * dev)
1386 {
1387 drm_i915_private_t *dev_priv = dev->dev_private;
1388 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1389
1390 i915_kernel_lost_context(dev);
1391
1392 DRM_DEBUG_DRIVER("\n");
1393
1394 dev_priv->counter++;
1395 if (dev_priv->counter > 0x7FFFFFFFUL)
1396 dev_priv->counter = 1;
1397 if (master_priv->sarea_priv)
1398 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1399
1400 if (BEGIN_LP_RING(4) == 0) {
1401 OUT_RING(MI_STORE_DWORD_INDEX);
1402 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1403 OUT_RING(dev_priv->counter);
1404 OUT_RING(MI_USER_INTERRUPT);
1405 ADVANCE_LP_RING();
1406 }
1407
1408 return dev_priv->counter;
1409 }
1410
1411 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1412 {
1413 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1414 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1415 int ret = 0;
1416 struct intel_ring_buffer *ring = LP_RING(dev_priv);
1417
1418 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1419 READ_BREADCRUMB(dev_priv));
1420
1421 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1422 if (master_priv->sarea_priv)
1423 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1424 return 0;
1425 }
1426
1427 if (master_priv->sarea_priv)
1428 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1429
1430 if (ring->irq_get(ring)) {
1431 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
1432 READ_BREADCRUMB(dev_priv) >= irq_nr);
1433 ring->irq_put(ring);
1434 } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
1435 ret = -EBUSY;
1436
1437 if (ret == -EBUSY) {
1438 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1439 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1440 }
1441
1442 return ret;
1443 }
1444
1445 /* Needs the lock as it touches the ring.
1446 */
1447 int i915_irq_emit(struct drm_device *dev, void *data,
1448 struct drm_file *file_priv)
1449 {
1450 drm_i915_private_t *dev_priv = dev->dev_private;
1451 drm_i915_irq_emit_t *emit = data;
1452 int result;
1453
1454 if (drm_core_check_feature(dev, DRIVER_MODESET))
1455 return -ENODEV;
1456
1457 if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
1458 DRM_ERROR("called with no initialization\n");
1459 return -EINVAL;
1460 }
1461
1462 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1463
1464 mutex_lock(&dev->struct_mutex);
1465 result = i915_emit_irq(dev);
1466 mutex_unlock(&dev->struct_mutex);
1467
1468 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1469 DRM_ERROR("copy_to_user\n");
1470 return -EFAULT;
1471 }
1472
1473 return 0;
1474 }
1475
1476 /* Doesn't need the hardware lock.
1477 */
1478 int i915_irq_wait(struct drm_device *dev, void *data,
1479 struct drm_file *file_priv)
1480 {
1481 drm_i915_private_t *dev_priv = dev->dev_private;
1482 drm_i915_irq_wait_t *irqwait = data;
1483
1484 if (drm_core_check_feature(dev, DRIVER_MODESET))
1485 return -ENODEV;
1486
1487 if (!dev_priv) {
1488 DRM_ERROR("called with no initialization\n");
1489 return -EINVAL;
1490 }
1491
1492 return i915_wait_irq(dev, irqwait->irq_seq);
1493 }
1494
1495 /* Called from drm generic code, passed 'crtc' which
1496 * we use as a pipe index
1497 */
1498 static int i915_enable_vblank(struct drm_device *dev, int pipe)
1499 {
1500 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1501 unsigned long irqflags;
1502
1503 if (!i915_pipe_enabled(dev, pipe))
1504 return -EINVAL;
1505
1506 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1507 if (INTEL_INFO(dev)->gen >= 4)
1508 i915_enable_pipestat(dev_priv, pipe,
1509 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1510 else
1511 i915_enable_pipestat(dev_priv, pipe,
1512 PIPE_VBLANK_INTERRUPT_ENABLE);
1513
1514 /* maintain vblank delivery even in deep C-states */
1515 if (dev_priv->info->gen == 3)
1516 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1517 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1518
1519 return 0;
1520 }
1521
1522 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1523 {
1524 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1525 unsigned long irqflags;
1526
1527 if (!i915_pipe_enabled(dev, pipe))
1528 return -EINVAL;
1529
1530 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1531 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1532 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1533 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1534
1535 return 0;
1536 }
1537
1538 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1539 {
1540 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1541 unsigned long irqflags;
1542
1543 if (!i915_pipe_enabled(dev, pipe))
1544 return -EINVAL;
1545
1546 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1547 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1548 DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1549 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1550
1551 return 0;
1552 }
1553
1554 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1555 {
1556 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1557 unsigned long irqflags;
1558 u32 dpfl, imr;
1559
1560 if (!i915_pipe_enabled(dev, pipe))
1561 return -EINVAL;
1562
1563 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1564 dpfl = I915_READ(VLV_DPFLIPSTAT);
1565 imr = I915_READ(VLV_IMR);
1566 if (pipe == 0) {
1567 dpfl |= PIPEA_VBLANK_INT_EN;
1568 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1569 } else {
1570 dpfl |= PIPEA_VBLANK_INT_EN;
1571 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1572 }
1573 I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1574 I915_WRITE(VLV_IMR, imr);
1575 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1576
1577 return 0;
1578 }
1579
1580 /* Called from drm generic code, passed 'crtc' which
1581 * we use as a pipe index
1582 */
1583 static void i915_disable_vblank(struct drm_device *dev, int pipe)
1584 {
1585 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1586 unsigned long irqflags;
1587
1588 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1589 if (dev_priv->info->gen == 3)
1590 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
1591
1592 i915_disable_pipestat(dev_priv, pipe,
1593 PIPE_VBLANK_INTERRUPT_ENABLE |
1594 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1595 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1596 }
1597
1598 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1599 {
1600 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1601 unsigned long irqflags;
1602
1603 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1604 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1605 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1606 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1607 }
1608
1609 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1610 {
1611 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1612 unsigned long irqflags;
1613
1614 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1615 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1616 DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1617 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1618 }
1619
1620 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1621 {
1622 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1623 unsigned long irqflags;
1624 u32 dpfl, imr;
1625
1626 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1627 dpfl = I915_READ(VLV_DPFLIPSTAT);
1628 imr = I915_READ(VLV_IMR);
1629 if (pipe == 0) {
1630 dpfl &= ~PIPEA_VBLANK_INT_EN;
1631 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1632 } else {
1633 dpfl &= ~PIPEB_VBLANK_INT_EN;
1634 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1635 }
1636 I915_WRITE(VLV_IMR, imr);
1637 I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1638 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1639 }
1640
1641
1642 /* Set the vblank monitor pipe
1643 */
1644 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1645 struct drm_file *file_priv)
1646 {
1647 drm_i915_private_t *dev_priv = dev->dev_private;
1648
1649 if (drm_core_check_feature(dev, DRIVER_MODESET))
1650 return -ENODEV;
1651
1652 if (!dev_priv) {
1653 DRM_ERROR("called with no initialization\n");
1654 return -EINVAL;
1655 }
1656
1657 return 0;
1658 }
1659
1660 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1661 struct drm_file *file_priv)
1662 {
1663 drm_i915_private_t *dev_priv = dev->dev_private;
1664 drm_i915_vblank_pipe_t *pipe = data;
1665
1666 if (drm_core_check_feature(dev, DRIVER_MODESET))
1667 return -ENODEV;
1668
1669 if (!dev_priv) {
1670 DRM_ERROR("called with no initialization\n");
1671 return -EINVAL;
1672 }
1673
1674 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1675
1676 return 0;
1677 }
1678
1679 /**
1680 * Schedule buffer swap at given vertical blank.
1681 */
1682 int i915_vblank_swap(struct drm_device *dev, void *data,
1683 struct drm_file *file_priv)
1684 {
1685 /* The delayed swap mechanism was fundamentally racy, and has been
1686 * removed. The model was that the client requested a delayed flip/swap
1687 * from the kernel, then waited for vblank before continuing to perform
1688 * rendering. The problem was that the kernel might wake the client
1689 * up before it dispatched the vblank swap (since the lock has to be
1690 * held while touching the ringbuffer), in which case the client would
1691 * clear and start the next frame before the swap occurred, and
1692 * flicker would occur in addition to likely missing the vblank.
1693 *
1694 * In the absence of this ioctl, userland falls back to a correct path
1695 * of waiting for a vblank, then dispatching the swap on its own.
1696 * Context switching to userland and back is plenty fast enough for
1697 * meeting the requirements of vblank swapping.
1698 */
1699 return -EINVAL;
1700 }
1701
1702 static u32
1703 ring_last_seqno(struct intel_ring_buffer *ring)
1704 {
1705 return list_entry(ring->request_list.prev,
1706 struct drm_i915_gem_request, list)->seqno;
1707 }
1708
1709 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1710 {
1711 if (list_empty(&ring->request_list) ||
1712 i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1713 /* Issue a wake-up to catch stuck h/w. */
1714 if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) {
1715 DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n",
1716 ring->name,
1717 ring->waiting_seqno,
1718 ring->get_seqno(ring));
1719 wake_up_all(&ring->irq_queue);
1720 *err = true;
1721 }
1722 return true;
1723 }
1724 return false;
1725 }
1726
1727 static bool kick_ring(struct intel_ring_buffer *ring)
1728 {
1729 struct drm_device *dev = ring->dev;
1730 struct drm_i915_private *dev_priv = dev->dev_private;
1731 u32 tmp = I915_READ_CTL(ring);
1732 if (tmp & RING_WAIT) {
1733 DRM_ERROR("Kicking stuck wait on %s\n",
1734 ring->name);
1735 I915_WRITE_CTL(ring, tmp);
1736 return true;
1737 }
1738 return false;
1739 }
1740
1741 static bool i915_hangcheck_hung(struct drm_device *dev)
1742 {
1743 drm_i915_private_t *dev_priv = dev->dev_private;
1744
1745 if (dev_priv->hangcheck_count++ > 1) {
1746 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1747 i915_handle_error(dev, true);
1748
1749 if (!IS_GEN2(dev)) {
1750 /* Is the chip hanging on a WAIT_FOR_EVENT?
1751 * If so we can simply poke the RB_WAIT bit
1752 * and break the hang. This should work on
1753 * all but the second generation chipsets.
1754 */
1755 if (kick_ring(&dev_priv->ring[RCS]))
1756 return false;
1757
1758 if (HAS_BSD(dev) && kick_ring(&dev_priv->ring[VCS]))
1759 return false;
1760
1761 if (HAS_BLT(dev) && kick_ring(&dev_priv->ring[BCS]))
1762 return false;
1763 }
1764
1765 return true;
1766 }
1767
1768 return false;
1769 }
1770
1771 /**
1772 * This is called when the chip hasn't reported back with completed
1773 * batchbuffers in a long time. The first time this is called we simply record
1774 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1775 * again, we assume the chip is wedged and try to fix it.
1776 */
1777 void i915_hangcheck_elapsed(unsigned long data)
1778 {
1779 struct drm_device *dev = (struct drm_device *)data;
1780 drm_i915_private_t *dev_priv = dev->dev_private;
1781 uint32_t acthd, instdone, instdone1, acthd_bsd, acthd_blt;
1782 bool err = false;
1783
1784 if (!i915_enable_hangcheck)
1785 return;
1786
1787 /* If all work is done then ACTHD clearly hasn't advanced. */
1788 if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) &&
1789 i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) &&
1790 i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) {
1791 if (err) {
1792 if (i915_hangcheck_hung(dev))
1793 return;
1794
1795 goto repeat;
1796 }
1797
1798 dev_priv->hangcheck_count = 0;
1799 return;
1800 }
1801
1802 if (INTEL_INFO(dev)->gen < 4) {
1803 instdone = I915_READ(INSTDONE);
1804 instdone1 = 0;
1805 } else {
1806 instdone = I915_READ(INSTDONE_I965);
1807 instdone1 = I915_READ(INSTDONE1);
1808 }
1809 acthd = intel_ring_get_active_head(&dev_priv->ring[RCS]);
1810 acthd_bsd = HAS_BSD(dev) ?
1811 intel_ring_get_active_head(&dev_priv->ring[VCS]) : 0;
1812 acthd_blt = HAS_BLT(dev) ?
1813 intel_ring_get_active_head(&dev_priv->ring[BCS]) : 0;
1814
1815 if (dev_priv->last_acthd == acthd &&
1816 dev_priv->last_acthd_bsd == acthd_bsd &&
1817 dev_priv->last_acthd_blt == acthd_blt &&
1818 dev_priv->last_instdone == instdone &&
1819 dev_priv->last_instdone1 == instdone1) {
1820 if (i915_hangcheck_hung(dev))
1821 return;
1822 } else {
1823 dev_priv->hangcheck_count = 0;
1824
1825 dev_priv->last_acthd = acthd;
1826 dev_priv->last_acthd_bsd = acthd_bsd;
1827 dev_priv->last_acthd_blt = acthd_blt;
1828 dev_priv->last_instdone = instdone;
1829 dev_priv->last_instdone1 = instdone1;
1830 }
1831
1832 repeat:
1833 /* Reset timer case chip hangs without another request being added */
1834 mod_timer(&dev_priv->hangcheck_timer,
1835 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1836 }
1837
1838 /* drm_dma.h hooks
1839 */
1840 static void ironlake_irq_preinstall(struct drm_device *dev)
1841 {
1842 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1843
1844 atomic_set(&dev_priv->irq_received, 0);
1845
1846
1847 I915_WRITE(HWSTAM, 0xeffe);
1848
1849 /* XXX hotplug from PCH */
1850
1851 I915_WRITE(DEIMR, 0xffffffff);
1852 I915_WRITE(DEIER, 0x0);
1853 POSTING_READ(DEIER);
1854
1855 /* and GT */
1856 I915_WRITE(GTIMR, 0xffffffff);
1857 I915_WRITE(GTIER, 0x0);
1858 POSTING_READ(GTIER);
1859
1860 /* south display irq */
1861 I915_WRITE(SDEIMR, 0xffffffff);
1862 I915_WRITE(SDEIER, 0x0);
1863 POSTING_READ(SDEIER);
1864 }
1865
1866 static void valleyview_irq_preinstall(struct drm_device *dev)
1867 {
1868 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1869 int pipe;
1870
1871 atomic_set(&dev_priv->irq_received, 0);
1872
1873 /* VLV magic */
1874 I915_WRITE(VLV_IMR, 0);
1875 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1876 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1877 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1878
1879 /* and GT */
1880 I915_WRITE(GTIIR, I915_READ(GTIIR));
1881 I915_WRITE(GTIIR, I915_READ(GTIIR));
1882 I915_WRITE(GTIMR, 0xffffffff);
1883 I915_WRITE(GTIER, 0x0);
1884 POSTING_READ(GTIER);
1885
1886 I915_WRITE(DPINVGTT, 0xff);
1887
1888 I915_WRITE(PORT_HOTPLUG_EN, 0);
1889 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1890 for_each_pipe(pipe)
1891 I915_WRITE(PIPESTAT(pipe), 0xffff);
1892 I915_WRITE(VLV_IIR, 0xffffffff);
1893 I915_WRITE(VLV_IMR, 0xffffffff);
1894 I915_WRITE(VLV_IER, 0x0);
1895 POSTING_READ(VLV_IER);
1896 }
1897
1898 /*
1899 * Enable digital hotplug on the PCH, and configure the DP short pulse
1900 * duration to 2ms (which is the minimum in the Display Port spec)
1901 *
1902 * This register is the same on all known PCH chips.
1903 */
1904
1905 static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1906 {
1907 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1908 u32 hotplug;
1909
1910 hotplug = I915_READ(PCH_PORT_HOTPLUG);
1911 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1912 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1913 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1914 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1915 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1916 }
1917
1918 static int ironlake_irq_postinstall(struct drm_device *dev)
1919 {
1920 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1921 /* enable kind of interrupts always enabled */
1922 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1923 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1924 u32 render_irqs;
1925 u32 hotplug_mask;
1926
1927 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1928 dev_priv->irq_mask = ~display_mask;
1929
1930 /* should always can generate irq */
1931 I915_WRITE(DEIIR, I915_READ(DEIIR));
1932 I915_WRITE(DEIMR, dev_priv->irq_mask);
1933 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
1934 POSTING_READ(DEIER);
1935
1936 dev_priv->gt_irq_mask = ~0;
1937
1938 I915_WRITE(GTIIR, I915_READ(GTIIR));
1939 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1940
1941 if (IS_GEN6(dev))
1942 render_irqs =
1943 GT_USER_INTERRUPT |
1944 GEN6_BSD_USER_INTERRUPT |
1945 GEN6_BLITTER_USER_INTERRUPT;
1946 else
1947 render_irqs =
1948 GT_USER_INTERRUPT |
1949 GT_PIPE_NOTIFY |
1950 GT_BSD_USER_INTERRUPT;
1951 I915_WRITE(GTIER, render_irqs);
1952 POSTING_READ(GTIER);
1953
1954 if (HAS_PCH_CPT(dev)) {
1955 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1956 SDE_PORTB_HOTPLUG_CPT |
1957 SDE_PORTC_HOTPLUG_CPT |
1958 SDE_PORTD_HOTPLUG_CPT);
1959 } else {
1960 hotplug_mask = (SDE_CRT_HOTPLUG |
1961 SDE_PORTB_HOTPLUG |
1962 SDE_PORTC_HOTPLUG |
1963 SDE_PORTD_HOTPLUG |
1964 SDE_AUX_MASK);
1965 }
1966
1967 dev_priv->pch_irq_mask = ~hotplug_mask;
1968
1969 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1970 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1971 I915_WRITE(SDEIER, hotplug_mask);
1972 POSTING_READ(SDEIER);
1973
1974 ironlake_enable_pch_hotplug(dev);
1975
1976 if (IS_IRONLAKE_M(dev)) {
1977 /* Clear & enable PCU event interrupts */
1978 I915_WRITE(DEIIR, DE_PCU_EVENT);
1979 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1980 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1981 }
1982
1983 return 0;
1984 }
1985
1986 static int ivybridge_irq_postinstall(struct drm_device *dev)
1987 {
1988 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1989 /* enable kind of interrupts always enabled */
1990 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
1991 DE_PCH_EVENT_IVB | DE_PLANEA_FLIP_DONE_IVB |
1992 DE_PLANEB_FLIP_DONE_IVB;
1993 u32 render_irqs;
1994 u32 hotplug_mask;
1995
1996 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1997 dev_priv->irq_mask = ~display_mask;
1998
1999 /* should always can generate irq */
2000 I915_WRITE(DEIIR, I915_READ(DEIIR));
2001 I915_WRITE(DEIMR, dev_priv->irq_mask);
2002 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK_IVB |
2003 DE_PIPEB_VBLANK_IVB);
2004 POSTING_READ(DEIER);
2005
2006 dev_priv->gt_irq_mask = ~0;
2007
2008 I915_WRITE(GTIIR, I915_READ(GTIIR));
2009 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2010
2011 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2012 GEN6_BLITTER_USER_INTERRUPT;
2013 I915_WRITE(GTIER, render_irqs);
2014 POSTING_READ(GTIER);
2015
2016 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
2017 SDE_PORTB_HOTPLUG_CPT |
2018 SDE_PORTC_HOTPLUG_CPT |
2019 SDE_PORTD_HOTPLUG_CPT);
2020 dev_priv->pch_irq_mask = ~hotplug_mask;
2021
2022 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2023 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
2024 I915_WRITE(SDEIER, hotplug_mask);
2025 POSTING_READ(SDEIER);
2026
2027 ironlake_enable_pch_hotplug(dev);
2028
2029 return 0;
2030 }
2031
2032 static int valleyview_irq_postinstall(struct drm_device *dev)
2033 {
2034 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2035 u32 render_irqs;
2036 u32 enable_mask;
2037 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2038 u16 msid;
2039
2040 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
2041 enable_mask |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2042 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2043
2044 dev_priv->irq_mask = ~enable_mask;
2045
2046 dev_priv->pipestat[0] = 0;
2047 dev_priv->pipestat[1] = 0;
2048
2049 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
2050
2051 /* Hack for broken MSIs on VLV */
2052 pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
2053 pci_read_config_word(dev->pdev, 0x98, &msid);
2054 msid &= 0xff; /* mask out delivery bits */
2055 msid |= (1<<14);
2056 pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
2057
2058 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2059 I915_WRITE(VLV_IER, enable_mask);
2060 I915_WRITE(VLV_IIR, 0xffffffff);
2061 I915_WRITE(PIPESTAT(0), 0xffff);
2062 I915_WRITE(PIPESTAT(1), 0xffff);
2063 POSTING_READ(VLV_IER);
2064
2065 I915_WRITE(VLV_IIR, 0xffffffff);
2066 I915_WRITE(VLV_IIR, 0xffffffff);
2067
2068 render_irqs = GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
2069 GT_GEN6_BLT_CS_ERROR_INTERRUPT |
2070 GT_GEN6_BLT_USER_INTERRUPT |
2071 GT_GEN6_BSD_USER_INTERRUPT |
2072 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
2073 GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
2074 GT_PIPE_NOTIFY |
2075 GT_RENDER_CS_ERROR_INTERRUPT |
2076 GT_SYNC_STATUS |
2077 GT_USER_INTERRUPT;
2078
2079 dev_priv->gt_irq_mask = ~render_irqs;
2080
2081 I915_WRITE(GTIIR, I915_READ(GTIIR));
2082 I915_WRITE(GTIIR, I915_READ(GTIIR));
2083 I915_WRITE(GTIMR, 0);
2084 I915_WRITE(GTIER, render_irqs);
2085 POSTING_READ(GTIER);
2086
2087 /* ack & enable invalid PTE error interrupts */
2088 #if 0 /* FIXME: add support to irq handler for checking these bits */
2089 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2090 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2091 #endif
2092
2093 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2094 #if 0 /* FIXME: check register definitions; some have moved */
2095 /* Note HDMI and DP share bits */
2096 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2097 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2098 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2099 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2100 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2101 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2102 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2103 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2104 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2105 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2106 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2107 hotplug_en |= CRT_HOTPLUG_INT_EN;
2108 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2109 }
2110 #endif
2111
2112 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2113
2114 return 0;
2115 }
2116
2117 static void valleyview_irq_uninstall(struct drm_device *dev)
2118 {
2119 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2120 int pipe;
2121
2122 if (!dev_priv)
2123 return;
2124
2125 dev_priv->vblank_pipe = 0;
2126
2127 for_each_pipe(pipe)
2128 I915_WRITE(PIPESTAT(pipe), 0xffff);
2129
2130 I915_WRITE(HWSTAM, 0xffffffff);
2131 I915_WRITE(PORT_HOTPLUG_EN, 0);
2132 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2133 for_each_pipe(pipe)
2134 I915_WRITE(PIPESTAT(pipe), 0xffff);
2135 I915_WRITE(VLV_IIR, 0xffffffff);
2136 I915_WRITE(VLV_IMR, 0xffffffff);
2137 I915_WRITE(VLV_IER, 0x0);
2138 POSTING_READ(VLV_IER);
2139 }
2140
2141 static void ironlake_irq_uninstall(struct drm_device *dev)
2142 {
2143 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2144
2145 if (!dev_priv)
2146 return;
2147
2148 dev_priv->vblank_pipe = 0;
2149
2150 I915_WRITE(HWSTAM, 0xffffffff);
2151
2152 I915_WRITE(DEIMR, 0xffffffff);
2153 I915_WRITE(DEIER, 0x0);
2154 I915_WRITE(DEIIR, I915_READ(DEIIR));
2155
2156 I915_WRITE(GTIMR, 0xffffffff);
2157 I915_WRITE(GTIER, 0x0);
2158 I915_WRITE(GTIIR, I915_READ(GTIIR));
2159
2160 I915_WRITE(SDEIMR, 0xffffffff);
2161 I915_WRITE(SDEIER, 0x0);
2162 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2163 }
2164
2165 static void i8xx_irq_preinstall(struct drm_device * dev)
2166 {
2167 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2168 int pipe;
2169
2170 atomic_set(&dev_priv->irq_received, 0);
2171
2172 for_each_pipe(pipe)
2173 I915_WRITE(PIPESTAT(pipe), 0);
2174 I915_WRITE16(IMR, 0xffff);
2175 I915_WRITE16(IER, 0x0);
2176 POSTING_READ16(IER);
2177 }
2178
2179 static int i8xx_irq_postinstall(struct drm_device *dev)
2180 {
2181 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2182
2183 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
2184
2185 dev_priv->pipestat[0] = 0;
2186 dev_priv->pipestat[1] = 0;
2187
2188 I915_WRITE16(EMR,
2189 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2190
2191 /* Unmask the interrupts that we always want on. */
2192 dev_priv->irq_mask =
2193 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2194 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2195 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2196 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2197 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2198 I915_WRITE16(IMR, dev_priv->irq_mask);
2199
2200 I915_WRITE16(IER,
2201 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2202 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2203 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2204 I915_USER_INTERRUPT);
2205 POSTING_READ16(IER);
2206
2207 return 0;
2208 }
2209
2210 static irqreturn_t i8xx_irq_handler(DRM_IRQ_ARGS)
2211 {
2212 struct drm_device *dev = (struct drm_device *) arg;
2213 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2214 struct drm_i915_master_private *master_priv;
2215 u16 iir, new_iir;
2216 u32 pipe_stats[2];
2217 unsigned long irqflags;
2218 int irq_received;
2219 int pipe;
2220 u16 flip_mask =
2221 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2222 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2223
2224 atomic_inc(&dev_priv->irq_received);
2225
2226 iir = I915_READ16(IIR);
2227 if (iir == 0)
2228 return IRQ_NONE;
2229
2230 while (iir & ~flip_mask) {
2231 /* Can't rely on pipestat interrupt bit in iir as it might
2232 * have been cleared after the pipestat interrupt was received.
2233 * It doesn't set the bit in iir again, but it still produces
2234 * interrupts (for non-MSI).
2235 */
2236 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2237 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2238 i915_handle_error(dev, false);
2239
2240 for_each_pipe(pipe) {
2241 int reg = PIPESTAT(pipe);
2242 pipe_stats[pipe] = I915_READ(reg);
2243
2244 /*
2245 * Clear the PIPE*STAT regs before the IIR
2246 */
2247 if (pipe_stats[pipe] & 0x8000ffff) {
2248 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2249 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2250 pipe_name(pipe));
2251 I915_WRITE(reg, pipe_stats[pipe]);
2252 irq_received = 1;
2253 }
2254 }
2255 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2256
2257 I915_WRITE16(IIR, iir & ~flip_mask);
2258 new_iir = I915_READ16(IIR); /* Flush posted writes */
2259
2260 if (dev->primary->master) {
2261 master_priv = dev->primary->master->driver_priv;
2262 if (master_priv->sarea_priv)
2263 master_priv->sarea_priv->last_dispatch =
2264 READ_BREADCRUMB(dev_priv);
2265 }
2266
2267 if (iir & I915_USER_INTERRUPT)
2268 notify_ring(dev, &dev_priv->ring[RCS]);
2269
2270 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2271 drm_handle_vblank(dev, 0)) {
2272 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2273 intel_prepare_page_flip(dev, 0);
2274 intel_finish_page_flip(dev, 0);
2275 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2276 }
2277 }
2278
2279 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2280 drm_handle_vblank(dev, 1)) {
2281 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2282 intel_prepare_page_flip(dev, 1);
2283 intel_finish_page_flip(dev, 1);
2284 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2285 }
2286 }
2287
2288 iir = new_iir;
2289 }
2290
2291 return IRQ_HANDLED;
2292 }
2293
2294 static void i8xx_irq_uninstall(struct drm_device * dev)
2295 {
2296 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2297 int pipe;
2298
2299 dev_priv->vblank_pipe = 0;
2300
2301 for_each_pipe(pipe) {
2302 /* Clear enable bits; then clear status bits */
2303 I915_WRITE(PIPESTAT(pipe), 0);
2304 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2305 }
2306 I915_WRITE16(IMR, 0xffff);
2307 I915_WRITE16(IER, 0x0);
2308 I915_WRITE16(IIR, I915_READ16(IIR));
2309 }
2310
2311 static void i915_irq_preinstall(struct drm_device * dev)
2312 {
2313 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2314 int pipe;
2315
2316 atomic_set(&dev_priv->irq_received, 0);
2317
2318 if (I915_HAS_HOTPLUG(dev)) {
2319 I915_WRITE(PORT_HOTPLUG_EN, 0);
2320 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2321 }
2322
2323 I915_WRITE16(HWSTAM, 0xeffe);
2324 for_each_pipe(pipe)
2325 I915_WRITE(PIPESTAT(pipe), 0);
2326 I915_WRITE(IMR, 0xffffffff);
2327 I915_WRITE(IER, 0x0);
2328 POSTING_READ(IER);
2329 }
2330
2331 static int i915_irq_postinstall(struct drm_device *dev)
2332 {
2333 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2334 u32 enable_mask;
2335
2336 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
2337
2338 dev_priv->pipestat[0] = 0;
2339 dev_priv->pipestat[1] = 0;
2340
2341 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2342
2343 /* Unmask the interrupts that we always want on. */
2344 dev_priv->irq_mask =
2345 ~(I915_ASLE_INTERRUPT |
2346 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2347 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2348 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2349 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2350 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2351
2352 enable_mask =
2353 I915_ASLE_INTERRUPT |
2354 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2355 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2356 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2357 I915_USER_INTERRUPT;
2358
2359 if (I915_HAS_HOTPLUG(dev)) {
2360 /* Enable in IER... */
2361 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2362 /* and unmask in IMR */
2363 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2364 }
2365
2366 I915_WRITE(IMR, dev_priv->irq_mask);
2367 I915_WRITE(IER, enable_mask);
2368 POSTING_READ(IER);
2369
2370 if (I915_HAS_HOTPLUG(dev)) {
2371 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2372
2373 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2374 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2375 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2376 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2377 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2378 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2379 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2380 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2381 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2382 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2383 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2384 hotplug_en |= CRT_HOTPLUG_INT_EN;
2385 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2386 }
2387
2388 /* Ignore TV since it's buggy */
2389
2390 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2391 }
2392
2393 intel_opregion_enable_asle(dev);
2394
2395 return 0;
2396 }
2397
2398 static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS)
2399 {
2400 struct drm_device *dev = (struct drm_device *) arg;
2401 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2402 struct drm_i915_master_private *master_priv;
2403 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
2404 unsigned long irqflags;
2405 u32 flip_mask =
2406 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2407 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2408 u32 flip[2] = {
2409 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
2410 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2411 };
2412 int pipe, ret = IRQ_NONE;
2413
2414 atomic_inc(&dev_priv->irq_received);
2415
2416 iir = I915_READ(IIR);
2417 do {
2418 bool irq_received = (iir & ~flip_mask) != 0;
2419 bool blc_event = false;
2420
2421 /* Can't rely on pipestat interrupt bit in iir as it might
2422 * have been cleared after the pipestat interrupt was received.
2423 * It doesn't set the bit in iir again, but it still produces
2424 * interrupts (for non-MSI).
2425 */
2426 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2427 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2428 i915_handle_error(dev, false);
2429
2430 for_each_pipe(pipe) {
2431 int reg = PIPESTAT(pipe);
2432 pipe_stats[pipe] = I915_READ(reg);
2433
2434 /* Clear the PIPE*STAT regs before the IIR */
2435 if (pipe_stats[pipe] & 0x8000ffff) {
2436 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2437 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2438 pipe_name(pipe));
2439 I915_WRITE(reg, pipe_stats[pipe]);
2440 irq_received = true;
2441 }
2442 }
2443 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2444
2445 if (!irq_received)
2446 break;
2447
2448 /* Consume port. Then clear IIR or we'll miss events */
2449 if ((I915_HAS_HOTPLUG(dev)) &&
2450 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2451 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2452
2453 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2454 hotplug_status);
2455 if (hotplug_status & dev_priv->hotplug_supported_mask)
2456 queue_work(dev_priv->wq,
2457 &dev_priv->hotplug_work);
2458
2459 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2460 POSTING_READ(PORT_HOTPLUG_STAT);
2461 }
2462
2463 I915_WRITE(IIR, iir & ~flip_mask);
2464 new_iir = I915_READ(IIR); /* Flush posted writes */
2465
2466 if (iir & I915_USER_INTERRUPT)
2467 notify_ring(dev, &dev_priv->ring[RCS]);
2468
2469 for_each_pipe(pipe) {
2470 int plane = pipe;
2471 if (IS_MOBILE(dev))
2472 plane = !plane;
2473 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
2474 drm_handle_vblank(dev, pipe)) {
2475 if (iir & flip[plane]) {
2476 intel_prepare_page_flip(dev, plane);
2477 intel_finish_page_flip(dev, pipe);
2478 flip_mask &= ~flip[plane];
2479 }
2480 }
2481
2482 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2483 blc_event = true;
2484 }
2485
2486 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2487 intel_opregion_asle_intr(dev);
2488
2489 /* With MSI, interrupts are only generated when iir
2490 * transitions from zero to nonzero. If another bit got
2491 * set while we were handling the existing iir bits, then
2492 * we would never get another interrupt.
2493 *
2494 * This is fine on non-MSI as well, as if we hit this path
2495 * we avoid exiting the interrupt handler only to generate
2496 * another one.
2497 *
2498 * Note that for MSI this could cause a stray interrupt report
2499 * if an interrupt landed in the time between writing IIR and
2500 * the posting read. This should be rare enough to never
2501 * trigger the 99% of 100,000 interrupts test for disabling
2502 * stray interrupts.
2503 */
2504 ret = IRQ_HANDLED;
2505 iir = new_iir;
2506 } while (iir & ~flip_mask);
2507
2508 if (dev->primary->master) {
2509 master_priv = dev->primary->master->driver_priv;
2510 if (master_priv->sarea_priv)
2511 master_priv->sarea_priv->last_dispatch =
2512 READ_BREADCRUMB(dev_priv);
2513 }
2514
2515 return ret;
2516 }
2517
2518 static void i915_irq_uninstall(struct drm_device * dev)
2519 {
2520 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2521 int pipe;
2522
2523 dev_priv->vblank_pipe = 0;
2524
2525 if (I915_HAS_HOTPLUG(dev)) {
2526 I915_WRITE(PORT_HOTPLUG_EN, 0);
2527 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2528 }
2529
2530 I915_WRITE16(HWSTAM, 0xffff);
2531 for_each_pipe(pipe) {
2532 /* Clear enable bits; then clear status bits */
2533 I915_WRITE(PIPESTAT(pipe), 0);
2534 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2535 }
2536 I915_WRITE(IMR, 0xffffffff);
2537 I915_WRITE(IER, 0x0);
2538
2539 I915_WRITE(IIR, I915_READ(IIR));
2540 }
2541
2542 static void i965_irq_preinstall(struct drm_device * dev)
2543 {
2544 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2545 int pipe;
2546
2547 atomic_set(&dev_priv->irq_received, 0);
2548
2549 if (I915_HAS_HOTPLUG(dev)) {
2550 I915_WRITE(PORT_HOTPLUG_EN, 0);
2551 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2552 }
2553
2554 I915_WRITE(HWSTAM, 0xeffe);
2555 for_each_pipe(pipe)
2556 I915_WRITE(PIPESTAT(pipe), 0);
2557 I915_WRITE(IMR, 0xffffffff);
2558 I915_WRITE(IER, 0x0);
2559 POSTING_READ(IER);
2560 }
2561
2562 static int i965_irq_postinstall(struct drm_device *dev)
2563 {
2564 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2565 u32 enable_mask;
2566 u32 error_mask;
2567
2568 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
2569
2570 /* Unmask the interrupts that we always want on. */
2571 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
2572 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2573 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2574 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2575 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2576 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2577
2578 enable_mask = ~dev_priv->irq_mask;
2579 enable_mask |= I915_USER_INTERRUPT;
2580
2581 if (IS_G4X(dev))
2582 enable_mask |= I915_BSD_USER_INTERRUPT;
2583
2584 dev_priv->pipestat[0] = 0;
2585 dev_priv->pipestat[1] = 0;
2586
2587 if (I915_HAS_HOTPLUG(dev)) {
2588 /* Enable in IER... */
2589 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2590 /* and unmask in IMR */
2591 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2592 }
2593
2594 /*
2595 * Enable some error detection, note the instruction error mask
2596 * bit is reserved, so we leave it masked.
2597 */
2598 if (IS_G4X(dev)) {
2599 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2600 GM45_ERROR_MEM_PRIV |
2601 GM45_ERROR_CP_PRIV |
2602 I915_ERROR_MEMORY_REFRESH);
2603 } else {
2604 error_mask = ~(I915_ERROR_PAGE_TABLE |
2605 I915_ERROR_MEMORY_REFRESH);
2606 }
2607 I915_WRITE(EMR, error_mask);
2608
2609 I915_WRITE(IMR, dev_priv->irq_mask);
2610 I915_WRITE(IER, enable_mask);
2611 POSTING_READ(IER);
2612
2613 if (I915_HAS_HOTPLUG(dev)) {
2614 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2615
2616 /* Note HDMI and DP share bits */
2617 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2618 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2619 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2620 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2621 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2622 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2623 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2624 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2625 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2626 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2627 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2628 hotplug_en |= CRT_HOTPLUG_INT_EN;
2629
2630 /* Programming the CRT detection parameters tends
2631 to generate a spurious hotplug event about three
2632 seconds later. So just do it once.
2633 */
2634 if (IS_G4X(dev))
2635 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2636 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2637 }
2638
2639 /* Ignore TV since it's buggy */
2640
2641 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2642 }
2643
2644 intel_opregion_enable_asle(dev);
2645
2646 return 0;
2647 }
2648
2649 static irqreturn_t i965_irq_handler(DRM_IRQ_ARGS)
2650 {
2651 struct drm_device *dev = (struct drm_device *) arg;
2652 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2653 struct drm_i915_master_private *master_priv;
2654 u32 iir, new_iir;
2655 u32 pipe_stats[I915_MAX_PIPES];
2656 unsigned long irqflags;
2657 int irq_received;
2658 int ret = IRQ_NONE, pipe;
2659
2660 atomic_inc(&dev_priv->irq_received);
2661
2662 iir = I915_READ(IIR);
2663
2664 for (;;) {
2665 bool blc_event = false;
2666
2667 irq_received = iir != 0;
2668
2669 /* Can't rely on pipestat interrupt bit in iir as it might
2670 * have been cleared after the pipestat interrupt was received.
2671 * It doesn't set the bit in iir again, but it still produces
2672 * interrupts (for non-MSI).
2673 */
2674 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2675 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2676 i915_handle_error(dev, false);
2677
2678 for_each_pipe(pipe) {
2679 int reg = PIPESTAT(pipe);
2680 pipe_stats[pipe] = I915_READ(reg);
2681
2682 /*
2683 * Clear the PIPE*STAT regs before the IIR
2684 */
2685 if (pipe_stats[pipe] & 0x8000ffff) {
2686 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2687 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2688 pipe_name(pipe));
2689 I915_WRITE(reg, pipe_stats[pipe]);
2690 irq_received = 1;
2691 }
2692 }
2693 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2694
2695 if (!irq_received)
2696 break;
2697
2698 ret = IRQ_HANDLED;
2699
2700 /* Consume port. Then clear IIR or we'll miss events */
2701 if ((I915_HAS_HOTPLUG(dev)) &&
2702 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2703 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2704
2705 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2706 hotplug_status);
2707 if (hotplug_status & dev_priv->hotplug_supported_mask)
2708 queue_work(dev_priv->wq,
2709 &dev_priv->hotplug_work);
2710
2711 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2712 I915_READ(PORT_HOTPLUG_STAT);
2713 }
2714
2715 I915_WRITE(IIR, iir);
2716 new_iir = I915_READ(IIR); /* Flush posted writes */
2717
2718 if (iir & I915_USER_INTERRUPT)
2719 notify_ring(dev, &dev_priv->ring[RCS]);
2720 if (iir & I915_BSD_USER_INTERRUPT)
2721 notify_ring(dev, &dev_priv->ring[VCS]);
2722
2723 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
2724 intel_prepare_page_flip(dev, 0);
2725
2726 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
2727 intel_prepare_page_flip(dev, 1);
2728
2729 for_each_pipe(pipe) {
2730 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
2731 drm_handle_vblank(dev, pipe)) {
2732 i915_pageflip_stall_check(dev, pipe);
2733 intel_finish_page_flip(dev, pipe);
2734 }
2735
2736 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2737 blc_event = true;
2738 }
2739
2740
2741 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2742 intel_opregion_asle_intr(dev);
2743
2744 /* With MSI, interrupts are only generated when iir
2745 * transitions from zero to nonzero. If another bit got
2746 * set while we were handling the existing iir bits, then
2747 * we would never get another interrupt.
2748 *
2749 * This is fine on non-MSI as well, as if we hit this path
2750 * we avoid exiting the interrupt handler only to generate
2751 * another one.
2752 *
2753 * Note that for MSI this could cause a stray interrupt report
2754 * if an interrupt landed in the time between writing IIR and
2755 * the posting read. This should be rare enough to never
2756 * trigger the 99% of 100,000 interrupts test for disabling
2757 * stray interrupts.
2758 */
2759 iir = new_iir;
2760 }
2761
2762 if (dev->primary->master) {
2763 master_priv = dev->primary->master->driver_priv;
2764 if (master_priv->sarea_priv)
2765 master_priv->sarea_priv->last_dispatch =
2766 READ_BREADCRUMB(dev_priv);
2767 }
2768
2769 return ret;
2770 }
2771
2772 static void i965_irq_uninstall(struct drm_device * dev)
2773 {
2774 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2775 int pipe;
2776
2777 if (!dev_priv)
2778 return;
2779
2780 dev_priv->vblank_pipe = 0;
2781
2782 if (I915_HAS_HOTPLUG(dev)) {
2783 I915_WRITE(PORT_HOTPLUG_EN, 0);
2784 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2785 }
2786
2787 I915_WRITE(HWSTAM, 0xffffffff);
2788 for_each_pipe(pipe)
2789 I915_WRITE(PIPESTAT(pipe), 0);
2790 I915_WRITE(IMR, 0xffffffff);
2791 I915_WRITE(IER, 0x0);
2792
2793 for_each_pipe(pipe)
2794 I915_WRITE(PIPESTAT(pipe),
2795 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2796 I915_WRITE(IIR, I915_READ(IIR));
2797 }
2798
2799 void intel_irq_init(struct drm_device *dev)
2800 {
2801 struct drm_i915_private *dev_priv = dev->dev_private;
2802
2803 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2804 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
2805 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
2806
2807 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2808 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2809 if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev) ||
2810 IS_VALLEYVIEW(dev)) {
2811 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2812 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2813 }
2814
2815 if (drm_core_check_feature(dev, DRIVER_MODESET))
2816 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2817 else
2818 dev->driver->get_vblank_timestamp = NULL;
2819 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2820
2821 if (IS_VALLEYVIEW(dev)) {
2822 dev->driver->irq_handler = valleyview_irq_handler;
2823 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2824 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2825 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2826 dev->driver->enable_vblank = valleyview_enable_vblank;
2827 dev->driver->disable_vblank = valleyview_disable_vblank;
2828 } else if (IS_IVYBRIDGE(dev)) {
2829 /* Share pre & uninstall handlers with ILK/SNB */
2830 dev->driver->irq_handler = ivybridge_irq_handler;
2831 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2832 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2833 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2834 dev->driver->enable_vblank = ivybridge_enable_vblank;
2835 dev->driver->disable_vblank = ivybridge_disable_vblank;
2836 } else if (HAS_PCH_SPLIT(dev)) {
2837 dev->driver->irq_handler = ironlake_irq_handler;
2838 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2839 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2840 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2841 dev->driver->enable_vblank = ironlake_enable_vblank;
2842 dev->driver->disable_vblank = ironlake_disable_vblank;
2843 } else {
2844 if (INTEL_INFO(dev)->gen == 2) {
2845 dev->driver->irq_preinstall = i8xx_irq_preinstall;
2846 dev->driver->irq_postinstall = i8xx_irq_postinstall;
2847 dev->driver->irq_handler = i8xx_irq_handler;
2848 dev->driver->irq_uninstall = i8xx_irq_uninstall;
2849 } else if (INTEL_INFO(dev)->gen == 3) {
2850 /* IIR "flip pending" means done if this bit is set */
2851 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
2852
2853 dev->driver->irq_preinstall = i915_irq_preinstall;
2854 dev->driver->irq_postinstall = i915_irq_postinstall;
2855 dev->driver->irq_uninstall = i915_irq_uninstall;
2856 dev->driver->irq_handler = i915_irq_handler;
2857 } else {
2858 dev->driver->irq_preinstall = i965_irq_preinstall;
2859 dev->driver->irq_postinstall = i965_irq_postinstall;
2860 dev->driver->irq_uninstall = i965_irq_uninstall;
2861 dev->driver->irq_handler = i965_irq_handler;
2862 }
2863 dev->driver->enable_vblank = i915_enable_vblank;
2864 dev->driver->disable_vblank = i915_disable_vblank;
2865 }
2866 }
Linux kernel - Deliverables
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