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drm/i915: Split the ringbuffers from the rings (2/3)
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
34 #include <drm/drmP.h>
35 #include <drm/i915_drm.h>
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "intel_drv.h"
39
40 static const u32 hpd_ibx[] = {
41 [HPD_CRT] = SDE_CRT_HOTPLUG,
42 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
43 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
44 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
45 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
46 };
47
48 static const u32 hpd_cpt[] = {
49 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
50 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
51 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
52 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
53 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
54 };
55
56 static const u32 hpd_mask_i915[] = {
57 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
58 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
59 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
60 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
61 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
62 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
63 };
64
65 static const u32 hpd_status_g4x[] = {
66 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
67 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
68 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
69 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
70 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
71 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
72 };
73
74 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
75 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
76 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
77 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
78 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
79 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
80 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
81 };
82
83 /* IIR can theoretically queue up two events. Be paranoid. */
84 #define GEN8_IRQ_RESET_NDX(type, which) do { \
85 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
86 POSTING_READ(GEN8_##type##_IMR(which)); \
87 I915_WRITE(GEN8_##type##_IER(which), 0); \
88 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
89 POSTING_READ(GEN8_##type##_IIR(which)); \
90 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
91 POSTING_READ(GEN8_##type##_IIR(which)); \
92 } while (0)
93
94 #define GEN5_IRQ_RESET(type) do { \
95 I915_WRITE(type##IMR, 0xffffffff); \
96 POSTING_READ(type##IMR); \
97 I915_WRITE(type##IER, 0); \
98 I915_WRITE(type##IIR, 0xffffffff); \
99 POSTING_READ(type##IIR); \
100 I915_WRITE(type##IIR, 0xffffffff); \
101 POSTING_READ(type##IIR); \
102 } while (0)
103
104 /*
105 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
106 */
107 #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
108 u32 val = I915_READ(reg); \
109 if (val) { \
110 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
111 (reg), val); \
112 I915_WRITE((reg), 0xffffffff); \
113 POSTING_READ(reg); \
114 I915_WRITE((reg), 0xffffffff); \
115 POSTING_READ(reg); \
116 } \
117 } while (0)
118
119 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
120 GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
121 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
122 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
123 POSTING_READ(GEN8_##type##_IER(which)); \
124 } while (0)
125
126 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
127 GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
128 I915_WRITE(type##IMR, (imr_val)); \
129 I915_WRITE(type##IER, (ier_val)); \
130 POSTING_READ(type##IER); \
131 } while (0)
132
133 /* For display hotplug interrupt */
134 static void
135 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
136 {
137 assert_spin_locked(&dev_priv->irq_lock);
138
139 if (WARN_ON(dev_priv->pm.irqs_disabled))
140 return;
141
142 if ((dev_priv->irq_mask & mask) != 0) {
143 dev_priv->irq_mask &= ~mask;
144 I915_WRITE(DEIMR, dev_priv->irq_mask);
145 POSTING_READ(DEIMR);
146 }
147 }
148
149 static void
150 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
151 {
152 assert_spin_locked(&dev_priv->irq_lock);
153
154 if (WARN_ON(dev_priv->pm.irqs_disabled))
155 return;
156
157 if ((dev_priv->irq_mask & mask) != mask) {
158 dev_priv->irq_mask |= mask;
159 I915_WRITE(DEIMR, dev_priv->irq_mask);
160 POSTING_READ(DEIMR);
161 }
162 }
163
164 /**
165 * ilk_update_gt_irq - update GTIMR
166 * @dev_priv: driver private
167 * @interrupt_mask: mask of interrupt bits to update
168 * @enabled_irq_mask: mask of interrupt bits to enable
169 */
170 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
171 uint32_t interrupt_mask,
172 uint32_t enabled_irq_mask)
173 {
174 assert_spin_locked(&dev_priv->irq_lock);
175
176 if (WARN_ON(dev_priv->pm.irqs_disabled))
177 return;
178
179 dev_priv->gt_irq_mask &= ~interrupt_mask;
180 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
181 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
182 POSTING_READ(GTIMR);
183 }
184
185 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
186 {
187 ilk_update_gt_irq(dev_priv, mask, mask);
188 }
189
190 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
191 {
192 ilk_update_gt_irq(dev_priv, mask, 0);
193 }
194
195 /**
196 * snb_update_pm_irq - update GEN6_PMIMR
197 * @dev_priv: driver private
198 * @interrupt_mask: mask of interrupt bits to update
199 * @enabled_irq_mask: mask of interrupt bits to enable
200 */
201 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
202 uint32_t interrupt_mask,
203 uint32_t enabled_irq_mask)
204 {
205 uint32_t new_val;
206
207 assert_spin_locked(&dev_priv->irq_lock);
208
209 if (WARN_ON(dev_priv->pm.irqs_disabled))
210 return;
211
212 new_val = dev_priv->pm_irq_mask;
213 new_val &= ~interrupt_mask;
214 new_val |= (~enabled_irq_mask & interrupt_mask);
215
216 if (new_val != dev_priv->pm_irq_mask) {
217 dev_priv->pm_irq_mask = new_val;
218 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
219 POSTING_READ(GEN6_PMIMR);
220 }
221 }
222
223 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
224 {
225 snb_update_pm_irq(dev_priv, mask, mask);
226 }
227
228 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
229 {
230 snb_update_pm_irq(dev_priv, mask, 0);
231 }
232
233 static bool ivb_can_enable_err_int(struct drm_device *dev)
234 {
235 struct drm_i915_private *dev_priv = dev->dev_private;
236 struct intel_crtc *crtc;
237 enum pipe pipe;
238
239 assert_spin_locked(&dev_priv->irq_lock);
240
241 for_each_pipe(pipe) {
242 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
243
244 if (crtc->cpu_fifo_underrun_disabled)
245 return false;
246 }
247
248 return true;
249 }
250
251 /**
252 * bdw_update_pm_irq - update GT interrupt 2
253 * @dev_priv: driver private
254 * @interrupt_mask: mask of interrupt bits to update
255 * @enabled_irq_mask: mask of interrupt bits to enable
256 *
257 * Copied from the snb function, updated with relevant register offsets
258 */
259 static void bdw_update_pm_irq(struct drm_i915_private *dev_priv,
260 uint32_t interrupt_mask,
261 uint32_t enabled_irq_mask)
262 {
263 uint32_t new_val;
264
265 assert_spin_locked(&dev_priv->irq_lock);
266
267 if (WARN_ON(dev_priv->pm.irqs_disabled))
268 return;
269
270 new_val = dev_priv->pm_irq_mask;
271 new_val &= ~interrupt_mask;
272 new_val |= (~enabled_irq_mask & interrupt_mask);
273
274 if (new_val != dev_priv->pm_irq_mask) {
275 dev_priv->pm_irq_mask = new_val;
276 I915_WRITE(GEN8_GT_IMR(2), dev_priv->pm_irq_mask);
277 POSTING_READ(GEN8_GT_IMR(2));
278 }
279 }
280
281 void bdw_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
282 {
283 bdw_update_pm_irq(dev_priv, mask, mask);
284 }
285
286 void bdw_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
287 {
288 bdw_update_pm_irq(dev_priv, mask, 0);
289 }
290
291 static bool cpt_can_enable_serr_int(struct drm_device *dev)
292 {
293 struct drm_i915_private *dev_priv = dev->dev_private;
294 enum pipe pipe;
295 struct intel_crtc *crtc;
296
297 assert_spin_locked(&dev_priv->irq_lock);
298
299 for_each_pipe(pipe) {
300 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
301
302 if (crtc->pch_fifo_underrun_disabled)
303 return false;
304 }
305
306 return true;
307 }
308
309 void i9xx_check_fifo_underruns(struct drm_device *dev)
310 {
311 struct drm_i915_private *dev_priv = dev->dev_private;
312 struct intel_crtc *crtc;
313 unsigned long flags;
314
315 spin_lock_irqsave(&dev_priv->irq_lock, flags);
316
317 for_each_intel_crtc(dev, crtc) {
318 u32 reg = PIPESTAT(crtc->pipe);
319 u32 pipestat;
320
321 if (crtc->cpu_fifo_underrun_disabled)
322 continue;
323
324 pipestat = I915_READ(reg) & 0xffff0000;
325 if ((pipestat & PIPE_FIFO_UNDERRUN_STATUS) == 0)
326 continue;
327
328 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
329 POSTING_READ(reg);
330
331 DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe));
332 }
333
334 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
335 }
336
337 static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
338 enum pipe pipe, bool enable)
339 {
340 struct drm_i915_private *dev_priv = dev->dev_private;
341 u32 reg = PIPESTAT(pipe);
342 u32 pipestat = I915_READ(reg) & 0xffff0000;
343
344 assert_spin_locked(&dev_priv->irq_lock);
345
346 if (enable) {
347 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
348 POSTING_READ(reg);
349 } else {
350 if (pipestat & PIPE_FIFO_UNDERRUN_STATUS)
351 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
352 }
353 }
354
355 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
356 enum pipe pipe, bool enable)
357 {
358 struct drm_i915_private *dev_priv = dev->dev_private;
359 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
360 DE_PIPEB_FIFO_UNDERRUN;
361
362 if (enable)
363 ironlake_enable_display_irq(dev_priv, bit);
364 else
365 ironlake_disable_display_irq(dev_priv, bit);
366 }
367
368 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
369 enum pipe pipe, bool enable)
370 {
371 struct drm_i915_private *dev_priv = dev->dev_private;
372 if (enable) {
373 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
374
375 if (!ivb_can_enable_err_int(dev))
376 return;
377
378 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
379 } else {
380 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
381
382 if (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {
383 DRM_ERROR("uncleared fifo underrun on pipe %c\n",
384 pipe_name(pipe));
385 }
386 }
387 }
388
389 static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
390 enum pipe pipe, bool enable)
391 {
392 struct drm_i915_private *dev_priv = dev->dev_private;
393
394 assert_spin_locked(&dev_priv->irq_lock);
395
396 if (enable)
397 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;
398 else
399 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
400 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
401 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
402 }
403
404 /**
405 * ibx_display_interrupt_update - update SDEIMR
406 * @dev_priv: driver private
407 * @interrupt_mask: mask of interrupt bits to update
408 * @enabled_irq_mask: mask of interrupt bits to enable
409 */
410 static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
411 uint32_t interrupt_mask,
412 uint32_t enabled_irq_mask)
413 {
414 uint32_t sdeimr = I915_READ(SDEIMR);
415 sdeimr &= ~interrupt_mask;
416 sdeimr |= (~enabled_irq_mask & interrupt_mask);
417
418 assert_spin_locked(&dev_priv->irq_lock);
419
420 if (WARN_ON(dev_priv->pm.irqs_disabled))
421 return;
422
423 I915_WRITE(SDEIMR, sdeimr);
424 POSTING_READ(SDEIMR);
425 }
426 #define ibx_enable_display_interrupt(dev_priv, bits) \
427 ibx_display_interrupt_update((dev_priv), (bits), (bits))
428 #define ibx_disable_display_interrupt(dev_priv, bits) \
429 ibx_display_interrupt_update((dev_priv), (bits), 0)
430
431 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
432 enum transcoder pch_transcoder,
433 bool enable)
434 {
435 struct drm_i915_private *dev_priv = dev->dev_private;
436 uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
437 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
438
439 if (enable)
440 ibx_enable_display_interrupt(dev_priv, bit);
441 else
442 ibx_disable_display_interrupt(dev_priv, bit);
443 }
444
445 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
446 enum transcoder pch_transcoder,
447 bool enable)
448 {
449 struct drm_i915_private *dev_priv = dev->dev_private;
450
451 if (enable) {
452 I915_WRITE(SERR_INT,
453 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
454
455 if (!cpt_can_enable_serr_int(dev))
456 return;
457
458 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
459 } else {
460 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
461
462 if (I915_READ(SERR_INT) & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) {
463 DRM_ERROR("uncleared pch fifo underrun on pch transcoder %c\n",
464 transcoder_name(pch_transcoder));
465 }
466 }
467 }
468
469 /**
470 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
471 * @dev: drm device
472 * @pipe: pipe
473 * @enable: true if we want to report FIFO underrun errors, false otherwise
474 *
475 * This function makes us disable or enable CPU fifo underruns for a specific
476 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
477 * reporting for one pipe may also disable all the other CPU error interruts for
478 * the other pipes, due to the fact that there's just one interrupt mask/enable
479 * bit for all the pipes.
480 *
481 * Returns the previous state of underrun reporting.
482 */
483 static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
484 enum pipe pipe, bool enable)
485 {
486 struct drm_i915_private *dev_priv = dev->dev_private;
487 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
488 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
489 bool ret;
490
491 assert_spin_locked(&dev_priv->irq_lock);
492
493 ret = !intel_crtc->cpu_fifo_underrun_disabled;
494
495 if (enable == ret)
496 goto done;
497
498 intel_crtc->cpu_fifo_underrun_disabled = !enable;
499
500 if (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
501 i9xx_set_fifo_underrun_reporting(dev, pipe, enable);
502 else if (IS_GEN5(dev) || IS_GEN6(dev))
503 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
504 else if (IS_GEN7(dev))
505 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
506 else if (IS_GEN8(dev))
507 broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
508
509 done:
510 return ret;
511 }
512
513 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
514 enum pipe pipe, bool enable)
515 {
516 struct drm_i915_private *dev_priv = dev->dev_private;
517 unsigned long flags;
518 bool ret;
519
520 spin_lock_irqsave(&dev_priv->irq_lock, flags);
521 ret = __intel_set_cpu_fifo_underrun_reporting(dev, pipe, enable);
522 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
523
524 return ret;
525 }
526
527 static bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev,
528 enum pipe pipe)
529 {
530 struct drm_i915_private *dev_priv = dev->dev_private;
531 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
532 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
533
534 return !intel_crtc->cpu_fifo_underrun_disabled;
535 }
536
537 /**
538 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
539 * @dev: drm device
540 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
541 * @enable: true if we want to report FIFO underrun errors, false otherwise
542 *
543 * This function makes us disable or enable PCH fifo underruns for a specific
544 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
545 * underrun reporting for one transcoder may also disable all the other PCH
546 * error interruts for the other transcoders, due to the fact that there's just
547 * one interrupt mask/enable bit for all the transcoders.
548 *
549 * Returns the previous state of underrun reporting.
550 */
551 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
552 enum transcoder pch_transcoder,
553 bool enable)
554 {
555 struct drm_i915_private *dev_priv = dev->dev_private;
556 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
558 unsigned long flags;
559 bool ret;
560
561 /*
562 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
563 * has only one pch transcoder A that all pipes can use. To avoid racy
564 * pch transcoder -> pipe lookups from interrupt code simply store the
565 * underrun statistics in crtc A. Since we never expose this anywhere
566 * nor use it outside of the fifo underrun code here using the "wrong"
567 * crtc on LPT won't cause issues.
568 */
569
570 spin_lock_irqsave(&dev_priv->irq_lock, flags);
571
572 ret = !intel_crtc->pch_fifo_underrun_disabled;
573
574 if (enable == ret)
575 goto done;
576
577 intel_crtc->pch_fifo_underrun_disabled = !enable;
578
579 if (HAS_PCH_IBX(dev))
580 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
581 else
582 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
583
584 done:
585 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
586 return ret;
587 }
588
589
590 static void
591 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
592 u32 enable_mask, u32 status_mask)
593 {
594 u32 reg = PIPESTAT(pipe);
595 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
596
597 assert_spin_locked(&dev_priv->irq_lock);
598
599 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
600 status_mask & ~PIPESTAT_INT_STATUS_MASK,
601 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
602 pipe_name(pipe), enable_mask, status_mask))
603 return;
604
605 if ((pipestat & enable_mask) == enable_mask)
606 return;
607
608 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
609
610 /* Enable the interrupt, clear any pending status */
611 pipestat |= enable_mask | status_mask;
612 I915_WRITE(reg, pipestat);
613 POSTING_READ(reg);
614 }
615
616 static void
617 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
618 u32 enable_mask, u32 status_mask)
619 {
620 u32 reg = PIPESTAT(pipe);
621 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
622
623 assert_spin_locked(&dev_priv->irq_lock);
624
625 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
626 status_mask & ~PIPESTAT_INT_STATUS_MASK,
627 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
628 pipe_name(pipe), enable_mask, status_mask))
629 return;
630
631 if ((pipestat & enable_mask) == 0)
632 return;
633
634 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
635
636 pipestat &= ~enable_mask;
637 I915_WRITE(reg, pipestat);
638 POSTING_READ(reg);
639 }
640
641 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
642 {
643 u32 enable_mask = status_mask << 16;
644
645 /*
646 * On pipe A we don't support the PSR interrupt yet,
647 * on pipe B and C the same bit MBZ.
648 */
649 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
650 return 0;
651 /*
652 * On pipe B and C we don't support the PSR interrupt yet, on pipe
653 * A the same bit is for perf counters which we don't use either.
654 */
655 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
656 return 0;
657
658 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
659 SPRITE0_FLIP_DONE_INT_EN_VLV |
660 SPRITE1_FLIP_DONE_INT_EN_VLV);
661 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
662 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
663 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
664 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
665
666 return enable_mask;
667 }
668
669 void
670 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
671 u32 status_mask)
672 {
673 u32 enable_mask;
674
675 if (IS_VALLEYVIEW(dev_priv->dev))
676 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
677 status_mask);
678 else
679 enable_mask = status_mask << 16;
680 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
681 }
682
683 void
684 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
685 u32 status_mask)
686 {
687 u32 enable_mask;
688
689 if (IS_VALLEYVIEW(dev_priv->dev))
690 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
691 status_mask);
692 else
693 enable_mask = status_mask << 16;
694 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
695 }
696
697 /**
698 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
699 */
700 static void i915_enable_asle_pipestat(struct drm_device *dev)
701 {
702 struct drm_i915_private *dev_priv = dev->dev_private;
703 unsigned long irqflags;
704
705 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
706 return;
707
708 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
709
710 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
711 if (INTEL_INFO(dev)->gen >= 4)
712 i915_enable_pipestat(dev_priv, PIPE_A,
713 PIPE_LEGACY_BLC_EVENT_STATUS);
714
715 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
716 }
717
718 /**
719 * i915_pipe_enabled - check if a pipe is enabled
720 * @dev: DRM device
721 * @pipe: pipe to check
722 *
723 * Reading certain registers when the pipe is disabled can hang the chip.
724 * Use this routine to make sure the PLL is running and the pipe is active
725 * before reading such registers if unsure.
726 */
727 static int
728 i915_pipe_enabled(struct drm_device *dev, int pipe)
729 {
730 struct drm_i915_private *dev_priv = dev->dev_private;
731
732 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
733 /* Locking is horribly broken here, but whatever. */
734 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
735 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
736
737 return intel_crtc->active;
738 } else {
739 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
740 }
741 }
742
743 /*
744 * This timing diagram depicts the video signal in and
745 * around the vertical blanking period.
746 *
747 * Assumptions about the fictitious mode used in this example:
748 * vblank_start >= 3
749 * vsync_start = vblank_start + 1
750 * vsync_end = vblank_start + 2
751 * vtotal = vblank_start + 3
752 *
753 * start of vblank:
754 * latch double buffered registers
755 * increment frame counter (ctg+)
756 * generate start of vblank interrupt (gen4+)
757 * |
758 * | frame start:
759 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
760 * | may be shifted forward 1-3 extra lines via PIPECONF
761 * | |
762 * | | start of vsync:
763 * | | generate vsync interrupt
764 * | | |
765 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
766 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
767 * ----va---> <-----------------vb--------------------> <--------va-------------
768 * | | <----vs-----> |
769 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
770 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
771 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
772 * | | |
773 * last visible pixel first visible pixel
774 * | increment frame counter (gen3/4)
775 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
776 *
777 * x = horizontal active
778 * _ = horizontal blanking
779 * hs = horizontal sync
780 * va = vertical active
781 * vb = vertical blanking
782 * vs = vertical sync
783 * vbs = vblank_start (number)
784 *
785 * Summary:
786 * - most events happen at the start of horizontal sync
787 * - frame start happens at the start of horizontal blank, 1-4 lines
788 * (depending on PIPECONF settings) after the start of vblank
789 * - gen3/4 pixel and frame counter are synchronized with the start
790 * of horizontal active on the first line of vertical active
791 */
792
793 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
794 {
795 /* Gen2 doesn't have a hardware frame counter */
796 return 0;
797 }
798
799 /* Called from drm generic code, passed a 'crtc', which
800 * we use as a pipe index
801 */
802 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
803 {
804 struct drm_i915_private *dev_priv = dev->dev_private;
805 unsigned long high_frame;
806 unsigned long low_frame;
807 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
808
809 if (!i915_pipe_enabled(dev, pipe)) {
810 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
811 "pipe %c\n", pipe_name(pipe));
812 return 0;
813 }
814
815 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
816 struct intel_crtc *intel_crtc =
817 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
818 const struct drm_display_mode *mode =
819 &intel_crtc->config.adjusted_mode;
820
821 htotal = mode->crtc_htotal;
822 hsync_start = mode->crtc_hsync_start;
823 vbl_start = mode->crtc_vblank_start;
824 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
825 vbl_start = DIV_ROUND_UP(vbl_start, 2);
826 } else {
827 enum transcoder cpu_transcoder = (enum transcoder) pipe;
828
829 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
830 hsync_start = (I915_READ(HSYNC(cpu_transcoder)) & 0x1fff) + 1;
831 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
832 if ((I915_READ(PIPECONF(cpu_transcoder)) &
833 PIPECONF_INTERLACE_MASK) != PIPECONF_PROGRESSIVE)
834 vbl_start = DIV_ROUND_UP(vbl_start, 2);
835 }
836
837 /* Convert to pixel count */
838 vbl_start *= htotal;
839
840 /* Start of vblank event occurs at start of hsync */
841 vbl_start -= htotal - hsync_start;
842
843 high_frame = PIPEFRAME(pipe);
844 low_frame = PIPEFRAMEPIXEL(pipe);
845
846 /*
847 * High & low register fields aren't synchronized, so make sure
848 * we get a low value that's stable across two reads of the high
849 * register.
850 */
851 do {
852 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
853 low = I915_READ(low_frame);
854 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
855 } while (high1 != high2);
856
857 high1 >>= PIPE_FRAME_HIGH_SHIFT;
858 pixel = low & PIPE_PIXEL_MASK;
859 low >>= PIPE_FRAME_LOW_SHIFT;
860
861 /*
862 * The frame counter increments at beginning of active.
863 * Cook up a vblank counter by also checking the pixel
864 * counter against vblank start.
865 */
866 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
867 }
868
869 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
870 {
871 struct drm_i915_private *dev_priv = dev->dev_private;
872 int reg = PIPE_FRMCOUNT_GM45(pipe);
873
874 if (!i915_pipe_enabled(dev, pipe)) {
875 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
876 "pipe %c\n", pipe_name(pipe));
877 return 0;
878 }
879
880 return I915_READ(reg);
881 }
882
883 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
884 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
885
886 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
887 {
888 struct drm_device *dev = crtc->base.dev;
889 struct drm_i915_private *dev_priv = dev->dev_private;
890 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
891 enum pipe pipe = crtc->pipe;
892 int position, vtotal;
893
894 vtotal = mode->crtc_vtotal;
895 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
896 vtotal /= 2;
897
898 if (IS_GEN2(dev))
899 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
900 else
901 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
902
903 /*
904 * See update_scanline_offset() for the details on the
905 * scanline_offset adjustment.
906 */
907 return (position + crtc->scanline_offset) % vtotal;
908 }
909
910 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
911 unsigned int flags, int *vpos, int *hpos,
912 ktime_t *stime, ktime_t *etime)
913 {
914 struct drm_i915_private *dev_priv = dev->dev_private;
915 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
917 const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
918 int position;
919 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
920 bool in_vbl = true;
921 int ret = 0;
922 unsigned long irqflags;
923
924 if (!intel_crtc->active) {
925 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
926 "pipe %c\n", pipe_name(pipe));
927 return 0;
928 }
929
930 htotal = mode->crtc_htotal;
931 hsync_start = mode->crtc_hsync_start;
932 vtotal = mode->crtc_vtotal;
933 vbl_start = mode->crtc_vblank_start;
934 vbl_end = mode->crtc_vblank_end;
935
936 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
937 vbl_start = DIV_ROUND_UP(vbl_start, 2);
938 vbl_end /= 2;
939 vtotal /= 2;
940 }
941
942 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
943
944 /*
945 * Lock uncore.lock, as we will do multiple timing critical raw
946 * register reads, potentially with preemption disabled, so the
947 * following code must not block on uncore.lock.
948 */
949 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
950
951 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
952
953 /* Get optional system timestamp before query. */
954 if (stime)
955 *stime = ktime_get();
956
957 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
958 /* No obvious pixelcount register. Only query vertical
959 * scanout position from Display scan line register.
960 */
961 position = __intel_get_crtc_scanline(intel_crtc);
962 } else {
963 /* Have access to pixelcount since start of frame.
964 * We can split this into vertical and horizontal
965 * scanout position.
966 */
967 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
968
969 /* convert to pixel counts */
970 vbl_start *= htotal;
971 vbl_end *= htotal;
972 vtotal *= htotal;
973
974 /*
975 * In interlaced modes, the pixel counter counts all pixels,
976 * so one field will have htotal more pixels. In order to avoid
977 * the reported position from jumping backwards when the pixel
978 * counter is beyond the length of the shorter field, just
979 * clamp the position the length of the shorter field. This
980 * matches how the scanline counter based position works since
981 * the scanline counter doesn't count the two half lines.
982 */
983 if (position >= vtotal)
984 position = vtotal - 1;
985
986 /*
987 * Start of vblank interrupt is triggered at start of hsync,
988 * just prior to the first active line of vblank. However we
989 * consider lines to start at the leading edge of horizontal
990 * active. So, should we get here before we've crossed into
991 * the horizontal active of the first line in vblank, we would
992 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
993 * always add htotal-hsync_start to the current pixel position.
994 */
995 position = (position + htotal - hsync_start) % vtotal;
996 }
997
998 /* Get optional system timestamp after query. */
999 if (etime)
1000 *etime = ktime_get();
1001
1002 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1003
1004 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1005
1006 in_vbl = position >= vbl_start && position < vbl_end;
1007
1008 /*
1009 * While in vblank, position will be negative
1010 * counting up towards 0 at vbl_end. And outside
1011 * vblank, position will be positive counting
1012 * up since vbl_end.
1013 */
1014 if (position >= vbl_start)
1015 position -= vbl_end;
1016 else
1017 position += vtotal - vbl_end;
1018
1019 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
1020 *vpos = position;
1021 *hpos = 0;
1022 } else {
1023 *vpos = position / htotal;
1024 *hpos = position - (*vpos * htotal);
1025 }
1026
1027 /* In vblank? */
1028 if (in_vbl)
1029 ret |= DRM_SCANOUTPOS_INVBL;
1030
1031 return ret;
1032 }
1033
1034 int intel_get_crtc_scanline(struct intel_crtc *crtc)
1035 {
1036 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1037 unsigned long irqflags;
1038 int position;
1039
1040 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1041 position = __intel_get_crtc_scanline(crtc);
1042 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1043
1044 return position;
1045 }
1046
1047 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
1048 int *max_error,
1049 struct timeval *vblank_time,
1050 unsigned flags)
1051 {
1052 struct drm_crtc *crtc;
1053
1054 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
1055 DRM_ERROR("Invalid crtc %d\n", pipe);
1056 return -EINVAL;
1057 }
1058
1059 /* Get drm_crtc to timestamp: */
1060 crtc = intel_get_crtc_for_pipe(dev, pipe);
1061 if (crtc == NULL) {
1062 DRM_ERROR("Invalid crtc %d\n", pipe);
1063 return -EINVAL;
1064 }
1065
1066 if (!crtc->enabled) {
1067 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
1068 return -EBUSY;
1069 }
1070
1071 /* Helper routine in DRM core does all the work: */
1072 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
1073 vblank_time, flags,
1074 crtc,
1075 &to_intel_crtc(crtc)->config.adjusted_mode);
1076 }
1077
1078 static bool intel_hpd_irq_event(struct drm_device *dev,
1079 struct drm_connector *connector)
1080 {
1081 enum drm_connector_status old_status;
1082
1083 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1084 old_status = connector->status;
1085
1086 connector->status = connector->funcs->detect(connector, false);
1087 if (old_status == connector->status)
1088 return false;
1089
1090 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
1091 connector->base.id,
1092 drm_get_connector_name(connector),
1093 drm_get_connector_status_name(old_status),
1094 drm_get_connector_status_name(connector->status));
1095
1096 return true;
1097 }
1098
1099 /*
1100 * Handle hotplug events outside the interrupt handler proper.
1101 */
1102 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
1103
1104 static void i915_hotplug_work_func(struct work_struct *work)
1105 {
1106 struct drm_i915_private *dev_priv =
1107 container_of(work, struct drm_i915_private, hotplug_work);
1108 struct drm_device *dev = dev_priv->dev;
1109 struct drm_mode_config *mode_config = &dev->mode_config;
1110 struct intel_connector *intel_connector;
1111 struct intel_encoder *intel_encoder;
1112 struct drm_connector *connector;
1113 unsigned long irqflags;
1114 bool hpd_disabled = false;
1115 bool changed = false;
1116 u32 hpd_event_bits;
1117
1118 /* HPD irq before everything is fully set up. */
1119 if (!dev_priv->enable_hotplug_processing)
1120 return;
1121
1122 mutex_lock(&mode_config->mutex);
1123 DRM_DEBUG_KMS("running encoder hotplug functions\n");
1124
1125 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1126
1127 hpd_event_bits = dev_priv->hpd_event_bits;
1128 dev_priv->hpd_event_bits = 0;
1129 list_for_each_entry(connector, &mode_config->connector_list, head) {
1130 intel_connector = to_intel_connector(connector);
1131 intel_encoder = intel_connector->encoder;
1132 if (intel_encoder->hpd_pin > HPD_NONE &&
1133 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
1134 connector->polled == DRM_CONNECTOR_POLL_HPD) {
1135 DRM_INFO("HPD interrupt storm detected on connector %s: "
1136 "switching from hotplug detection to polling\n",
1137 drm_get_connector_name(connector));
1138 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
1139 connector->polled = DRM_CONNECTOR_POLL_CONNECT
1140 | DRM_CONNECTOR_POLL_DISCONNECT;
1141 hpd_disabled = true;
1142 }
1143 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
1144 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
1145 drm_get_connector_name(connector), intel_encoder->hpd_pin);
1146 }
1147 }
1148 /* if there were no outputs to poll, poll was disabled,
1149 * therefore make sure it's enabled when disabling HPD on
1150 * some connectors */
1151 if (hpd_disabled) {
1152 drm_kms_helper_poll_enable(dev);
1153 mod_timer(&dev_priv->hotplug_reenable_timer,
1154 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
1155 }
1156
1157 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1158
1159 list_for_each_entry(connector, &mode_config->connector_list, head) {
1160 intel_connector = to_intel_connector(connector);
1161 intel_encoder = intel_connector->encoder;
1162 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
1163 if (intel_encoder->hot_plug)
1164 intel_encoder->hot_plug(intel_encoder);
1165 if (intel_hpd_irq_event(dev, connector))
1166 changed = true;
1167 }
1168 }
1169 mutex_unlock(&mode_config->mutex);
1170
1171 if (changed)
1172 drm_kms_helper_hotplug_event(dev);
1173 }
1174
1175 static void intel_hpd_irq_uninstall(struct drm_i915_private *dev_priv)
1176 {
1177 del_timer_sync(&dev_priv->hotplug_reenable_timer);
1178 }
1179
1180 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
1181 {
1182 struct drm_i915_private *dev_priv = dev->dev_private;
1183 u32 busy_up, busy_down, max_avg, min_avg;
1184 u8 new_delay;
1185
1186 spin_lock(&mchdev_lock);
1187
1188 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
1189
1190 new_delay = dev_priv->ips.cur_delay;
1191
1192 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
1193 busy_up = I915_READ(RCPREVBSYTUPAVG);
1194 busy_down = I915_READ(RCPREVBSYTDNAVG);
1195 max_avg = I915_READ(RCBMAXAVG);
1196 min_avg = I915_READ(RCBMINAVG);
1197
1198 /* Handle RCS change request from hw */
1199 if (busy_up > max_avg) {
1200 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
1201 new_delay = dev_priv->ips.cur_delay - 1;
1202 if (new_delay < dev_priv->ips.max_delay)
1203 new_delay = dev_priv->ips.max_delay;
1204 } else if (busy_down < min_avg) {
1205 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
1206 new_delay = dev_priv->ips.cur_delay + 1;
1207 if (new_delay > dev_priv->ips.min_delay)
1208 new_delay = dev_priv->ips.min_delay;
1209 }
1210
1211 if (ironlake_set_drps(dev, new_delay))
1212 dev_priv->ips.cur_delay = new_delay;
1213
1214 spin_unlock(&mchdev_lock);
1215
1216 return;
1217 }
1218
1219 static void notify_ring(struct drm_device *dev,
1220 struct intel_engine_cs *ring)
1221 {
1222 if (ring->buffer->obj == NULL)
1223 return;
1224
1225 trace_i915_gem_request_complete(ring);
1226
1227 wake_up_all(&ring->irq_queue);
1228 i915_queue_hangcheck(dev);
1229 }
1230
1231 static void gen6_pm_rps_work(struct work_struct *work)
1232 {
1233 struct drm_i915_private *dev_priv =
1234 container_of(work, struct drm_i915_private, rps.work);
1235 u32 pm_iir;
1236 int new_delay, adj;
1237
1238 spin_lock_irq(&dev_priv->irq_lock);
1239 pm_iir = dev_priv->rps.pm_iir;
1240 dev_priv->rps.pm_iir = 0;
1241 if (IS_BROADWELL(dev_priv->dev))
1242 bdw_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1243 else {
1244 /* Make sure not to corrupt PMIMR state used by ringbuffer */
1245 snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1246 }
1247 spin_unlock_irq(&dev_priv->irq_lock);
1248
1249 /* Make sure we didn't queue anything we're not going to process. */
1250 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1251
1252 if ((pm_iir & dev_priv->pm_rps_events) == 0)
1253 return;
1254
1255 mutex_lock(&dev_priv->rps.hw_lock);
1256
1257 adj = dev_priv->rps.last_adj;
1258 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1259 if (adj > 0)
1260 adj *= 2;
1261 else
1262 adj = 1;
1263 new_delay = dev_priv->rps.cur_freq + adj;
1264
1265 /*
1266 * For better performance, jump directly
1267 * to RPe if we're below it.
1268 */
1269 if (new_delay < dev_priv->rps.efficient_freq)
1270 new_delay = dev_priv->rps.efficient_freq;
1271 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1272 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1273 new_delay = dev_priv->rps.efficient_freq;
1274 else
1275 new_delay = dev_priv->rps.min_freq_softlimit;
1276 adj = 0;
1277 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1278 if (adj < 0)
1279 adj *= 2;
1280 else
1281 adj = -1;
1282 new_delay = dev_priv->rps.cur_freq + adj;
1283 } else { /* unknown event */
1284 new_delay = dev_priv->rps.cur_freq;
1285 }
1286
1287 /* sysfs frequency interfaces may have snuck in while servicing the
1288 * interrupt
1289 */
1290 new_delay = clamp_t(int, new_delay,
1291 dev_priv->rps.min_freq_softlimit,
1292 dev_priv->rps.max_freq_softlimit);
1293
1294 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq;
1295
1296 if (IS_VALLEYVIEW(dev_priv->dev))
1297 valleyview_set_rps(dev_priv->dev, new_delay);
1298 else
1299 gen6_set_rps(dev_priv->dev, new_delay);
1300
1301 mutex_unlock(&dev_priv->rps.hw_lock);
1302 }
1303
1304
1305 /**
1306 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1307 * occurred.
1308 * @work: workqueue struct
1309 *
1310 * Doesn't actually do anything except notify userspace. As a consequence of
1311 * this event, userspace should try to remap the bad rows since statistically
1312 * it is likely the same row is more likely to go bad again.
1313 */
1314 static void ivybridge_parity_work(struct work_struct *work)
1315 {
1316 struct drm_i915_private *dev_priv =
1317 container_of(work, struct drm_i915_private, l3_parity.error_work);
1318 u32 error_status, row, bank, subbank;
1319 char *parity_event[6];
1320 uint32_t misccpctl;
1321 unsigned long flags;
1322 uint8_t slice = 0;
1323
1324 /* We must turn off DOP level clock gating to access the L3 registers.
1325 * In order to prevent a get/put style interface, acquire struct mutex
1326 * any time we access those registers.
1327 */
1328 mutex_lock(&dev_priv->dev->struct_mutex);
1329
1330 /* If we've screwed up tracking, just let the interrupt fire again */
1331 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1332 goto out;
1333
1334 misccpctl = I915_READ(GEN7_MISCCPCTL);
1335 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1336 POSTING_READ(GEN7_MISCCPCTL);
1337
1338 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1339 u32 reg;
1340
1341 slice--;
1342 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1343 break;
1344
1345 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1346
1347 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1348
1349 error_status = I915_READ(reg);
1350 row = GEN7_PARITY_ERROR_ROW(error_status);
1351 bank = GEN7_PARITY_ERROR_BANK(error_status);
1352 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1353
1354 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1355 POSTING_READ(reg);
1356
1357 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1358 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1359 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1360 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1361 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1362 parity_event[5] = NULL;
1363
1364 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1365 KOBJ_CHANGE, parity_event);
1366
1367 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1368 slice, row, bank, subbank);
1369
1370 kfree(parity_event[4]);
1371 kfree(parity_event[3]);
1372 kfree(parity_event[2]);
1373 kfree(parity_event[1]);
1374 }
1375
1376 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1377
1378 out:
1379 WARN_ON(dev_priv->l3_parity.which_slice);
1380 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1381 ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1382 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1383
1384 mutex_unlock(&dev_priv->dev->struct_mutex);
1385 }
1386
1387 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1388 {
1389 struct drm_i915_private *dev_priv = dev->dev_private;
1390
1391 if (!HAS_L3_DPF(dev))
1392 return;
1393
1394 spin_lock(&dev_priv->irq_lock);
1395 ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1396 spin_unlock(&dev_priv->irq_lock);
1397
1398 iir &= GT_PARITY_ERROR(dev);
1399 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1400 dev_priv->l3_parity.which_slice |= 1 << 1;
1401
1402 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1403 dev_priv->l3_parity.which_slice |= 1 << 0;
1404
1405 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1406 }
1407
1408 static void ilk_gt_irq_handler(struct drm_device *dev,
1409 struct drm_i915_private *dev_priv,
1410 u32 gt_iir)
1411 {
1412 if (gt_iir &
1413 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1414 notify_ring(dev, &dev_priv->ring[RCS]);
1415 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1416 notify_ring(dev, &dev_priv->ring[VCS]);
1417 }
1418
1419 static void snb_gt_irq_handler(struct drm_device *dev,
1420 struct drm_i915_private *dev_priv,
1421 u32 gt_iir)
1422 {
1423
1424 if (gt_iir &
1425 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1426 notify_ring(dev, &dev_priv->ring[RCS]);
1427 if (gt_iir & GT_BSD_USER_INTERRUPT)
1428 notify_ring(dev, &dev_priv->ring[VCS]);
1429 if (gt_iir & GT_BLT_USER_INTERRUPT)
1430 notify_ring(dev, &dev_priv->ring[BCS]);
1431
1432 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1433 GT_BSD_CS_ERROR_INTERRUPT |
1434 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
1435 i915_handle_error(dev, false, "GT error interrupt 0x%08x",
1436 gt_iir);
1437 }
1438
1439 if (gt_iir & GT_PARITY_ERROR(dev))
1440 ivybridge_parity_error_irq_handler(dev, gt_iir);
1441 }
1442
1443 static void gen8_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1444 {
1445 if ((pm_iir & dev_priv->pm_rps_events) == 0)
1446 return;
1447
1448 spin_lock(&dev_priv->irq_lock);
1449 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1450 bdw_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1451 spin_unlock(&dev_priv->irq_lock);
1452
1453 queue_work(dev_priv->wq, &dev_priv->rps.work);
1454 }
1455
1456 static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1457 struct drm_i915_private *dev_priv,
1458 u32 master_ctl)
1459 {
1460 u32 rcs, bcs, vcs;
1461 uint32_t tmp = 0;
1462 irqreturn_t ret = IRQ_NONE;
1463
1464 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1465 tmp = I915_READ(GEN8_GT_IIR(0));
1466 if (tmp) {
1467 ret = IRQ_HANDLED;
1468 rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1469 bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1470 if (rcs & GT_RENDER_USER_INTERRUPT)
1471 notify_ring(dev, &dev_priv->ring[RCS]);
1472 if (bcs & GT_RENDER_USER_INTERRUPT)
1473 notify_ring(dev, &dev_priv->ring[BCS]);
1474 I915_WRITE(GEN8_GT_IIR(0), tmp);
1475 } else
1476 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1477 }
1478
1479 if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1480 tmp = I915_READ(GEN8_GT_IIR(1));
1481 if (tmp) {
1482 ret = IRQ_HANDLED;
1483 vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1484 if (vcs & GT_RENDER_USER_INTERRUPT)
1485 notify_ring(dev, &dev_priv->ring[VCS]);
1486 vcs = tmp >> GEN8_VCS2_IRQ_SHIFT;
1487 if (vcs & GT_RENDER_USER_INTERRUPT)
1488 notify_ring(dev, &dev_priv->ring[VCS2]);
1489 I915_WRITE(GEN8_GT_IIR(1), tmp);
1490 } else
1491 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1492 }
1493
1494 if (master_ctl & GEN8_GT_PM_IRQ) {
1495 tmp = I915_READ(GEN8_GT_IIR(2));
1496 if (tmp & dev_priv->pm_rps_events) {
1497 ret = IRQ_HANDLED;
1498 gen8_rps_irq_handler(dev_priv, tmp);
1499 I915_WRITE(GEN8_GT_IIR(2),
1500 tmp & dev_priv->pm_rps_events);
1501 } else
1502 DRM_ERROR("The master control interrupt lied (PM)!\n");
1503 }
1504
1505 if (master_ctl & GEN8_GT_VECS_IRQ) {
1506 tmp = I915_READ(GEN8_GT_IIR(3));
1507 if (tmp) {
1508 ret = IRQ_HANDLED;
1509 vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1510 if (vcs & GT_RENDER_USER_INTERRUPT)
1511 notify_ring(dev, &dev_priv->ring[VECS]);
1512 I915_WRITE(GEN8_GT_IIR(3), tmp);
1513 } else
1514 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1515 }
1516
1517 return ret;
1518 }
1519
1520 #define HPD_STORM_DETECT_PERIOD 1000
1521 #define HPD_STORM_THRESHOLD 5
1522
1523 static inline void intel_hpd_irq_handler(struct drm_device *dev,
1524 u32 hotplug_trigger,
1525 const u32 *hpd)
1526 {
1527 struct drm_i915_private *dev_priv = dev->dev_private;
1528 int i;
1529 bool storm_detected = false;
1530
1531 if (!hotplug_trigger)
1532 return;
1533
1534 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1535 hotplug_trigger);
1536
1537 spin_lock(&dev_priv->irq_lock);
1538 for (i = 1; i < HPD_NUM_PINS; i++) {
1539
1540 if (hpd[i] & hotplug_trigger &&
1541 dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) {
1542 /*
1543 * On GMCH platforms the interrupt mask bits only
1544 * prevent irq generation, not the setting of the
1545 * hotplug bits itself. So only WARN about unexpected
1546 * interrupts on saner platforms.
1547 */
1548 WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
1549 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1550 hotplug_trigger, i, hpd[i]);
1551
1552 continue;
1553 }
1554
1555 if (!(hpd[i] & hotplug_trigger) ||
1556 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1557 continue;
1558
1559 dev_priv->hpd_event_bits |= (1 << i);
1560 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1561 dev_priv->hpd_stats[i].hpd_last_jiffies
1562 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1563 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1564 dev_priv->hpd_stats[i].hpd_cnt = 0;
1565 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1566 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1567 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1568 dev_priv->hpd_event_bits &= ~(1 << i);
1569 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1570 storm_detected = true;
1571 } else {
1572 dev_priv->hpd_stats[i].hpd_cnt++;
1573 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1574 dev_priv->hpd_stats[i].hpd_cnt);
1575 }
1576 }
1577
1578 if (storm_detected)
1579 dev_priv->display.hpd_irq_setup(dev);
1580 spin_unlock(&dev_priv->irq_lock);
1581
1582 /*
1583 * Our hotplug handler can grab modeset locks (by calling down into the
1584 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1585 * queue for otherwise the flush_work in the pageflip code will
1586 * deadlock.
1587 */
1588 schedule_work(&dev_priv->hotplug_work);
1589 }
1590
1591 static void gmbus_irq_handler(struct drm_device *dev)
1592 {
1593 struct drm_i915_private *dev_priv = dev->dev_private;
1594
1595 wake_up_all(&dev_priv->gmbus_wait_queue);
1596 }
1597
1598 static void dp_aux_irq_handler(struct drm_device *dev)
1599 {
1600 struct drm_i915_private *dev_priv = dev->dev_private;
1601
1602 wake_up_all(&dev_priv->gmbus_wait_queue);
1603 }
1604
1605 #if defined(CONFIG_DEBUG_FS)
1606 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1607 uint32_t crc0, uint32_t crc1,
1608 uint32_t crc2, uint32_t crc3,
1609 uint32_t crc4)
1610 {
1611 struct drm_i915_private *dev_priv = dev->dev_private;
1612 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1613 struct intel_pipe_crc_entry *entry;
1614 int head, tail;
1615
1616 spin_lock(&pipe_crc->lock);
1617
1618 if (!pipe_crc->entries) {
1619 spin_unlock(&pipe_crc->lock);
1620 DRM_ERROR("spurious interrupt\n");
1621 return;
1622 }
1623
1624 head = pipe_crc->head;
1625 tail = pipe_crc->tail;
1626
1627 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1628 spin_unlock(&pipe_crc->lock);
1629 DRM_ERROR("CRC buffer overflowing\n");
1630 return;
1631 }
1632
1633 entry = &pipe_crc->entries[head];
1634
1635 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1636 entry->crc[0] = crc0;
1637 entry->crc[1] = crc1;
1638 entry->crc[2] = crc2;
1639 entry->crc[3] = crc3;
1640 entry->crc[4] = crc4;
1641
1642 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1643 pipe_crc->head = head;
1644
1645 spin_unlock(&pipe_crc->lock);
1646
1647 wake_up_interruptible(&pipe_crc->wq);
1648 }
1649 #else
1650 static inline void
1651 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1652 uint32_t crc0, uint32_t crc1,
1653 uint32_t crc2, uint32_t crc3,
1654 uint32_t crc4) {}
1655 #endif
1656
1657
1658 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1659 {
1660 struct drm_i915_private *dev_priv = dev->dev_private;
1661
1662 display_pipe_crc_irq_handler(dev, pipe,
1663 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1664 0, 0, 0, 0);
1665 }
1666
1667 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1668 {
1669 struct drm_i915_private *dev_priv = dev->dev_private;
1670
1671 display_pipe_crc_irq_handler(dev, pipe,
1672 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1673 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1674 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1675 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1676 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1677 }
1678
1679 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1680 {
1681 struct drm_i915_private *dev_priv = dev->dev_private;
1682 uint32_t res1, res2;
1683
1684 if (INTEL_INFO(dev)->gen >= 3)
1685 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1686 else
1687 res1 = 0;
1688
1689 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1690 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1691 else
1692 res2 = 0;
1693
1694 display_pipe_crc_irq_handler(dev, pipe,
1695 I915_READ(PIPE_CRC_RES_RED(pipe)),
1696 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1697 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1698 res1, res2);
1699 }
1700
1701 /* The RPS events need forcewake, so we add them to a work queue and mask their
1702 * IMR bits until the work is done. Other interrupts can be processed without
1703 * the work queue. */
1704 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1705 {
1706 if (pm_iir & dev_priv->pm_rps_events) {
1707 spin_lock(&dev_priv->irq_lock);
1708 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1709 snb_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1710 spin_unlock(&dev_priv->irq_lock);
1711
1712 queue_work(dev_priv->wq, &dev_priv->rps.work);
1713 }
1714
1715 if (HAS_VEBOX(dev_priv->dev)) {
1716 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1717 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1718
1719 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1720 i915_handle_error(dev_priv->dev, false,
1721 "VEBOX CS error interrupt 0x%08x",
1722 pm_iir);
1723 }
1724 }
1725 }
1726
1727 static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
1728 {
1729 struct intel_crtc *crtc;
1730
1731 if (!drm_handle_vblank(dev, pipe))
1732 return false;
1733
1734 crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
1735 wake_up(&crtc->vbl_wait);
1736
1737 return true;
1738 }
1739
1740 static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1741 {
1742 struct drm_i915_private *dev_priv = dev->dev_private;
1743 u32 pipe_stats[I915_MAX_PIPES] = { };
1744 int pipe;
1745
1746 spin_lock(&dev_priv->irq_lock);
1747 for_each_pipe(pipe) {
1748 int reg;
1749 u32 mask, iir_bit = 0;
1750
1751 /*
1752 * PIPESTAT bits get signalled even when the interrupt is
1753 * disabled with the mask bits, and some of the status bits do
1754 * not generate interrupts at all (like the underrun bit). Hence
1755 * we need to be careful that we only handle what we want to
1756 * handle.
1757 */
1758 mask = 0;
1759 if (__cpu_fifo_underrun_reporting_enabled(dev, pipe))
1760 mask |= PIPE_FIFO_UNDERRUN_STATUS;
1761
1762 switch (pipe) {
1763 case PIPE_A:
1764 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1765 break;
1766 case PIPE_B:
1767 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1768 break;
1769 case PIPE_C:
1770 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1771 break;
1772 }
1773 if (iir & iir_bit)
1774 mask |= dev_priv->pipestat_irq_mask[pipe];
1775
1776 if (!mask)
1777 continue;
1778
1779 reg = PIPESTAT(pipe);
1780 mask |= PIPESTAT_INT_ENABLE_MASK;
1781 pipe_stats[pipe] = I915_READ(reg) & mask;
1782
1783 /*
1784 * Clear the PIPE*STAT regs before the IIR
1785 */
1786 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1787 PIPESTAT_INT_STATUS_MASK))
1788 I915_WRITE(reg, pipe_stats[pipe]);
1789 }
1790 spin_unlock(&dev_priv->irq_lock);
1791
1792 for_each_pipe(pipe) {
1793 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1794 intel_pipe_handle_vblank(dev, pipe);
1795
1796 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
1797 intel_prepare_page_flip(dev, pipe);
1798 intel_finish_page_flip(dev, pipe);
1799 }
1800
1801 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1802 i9xx_pipe_crc_irq_handler(dev, pipe);
1803
1804 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
1805 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1806 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
1807 }
1808
1809 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1810 gmbus_irq_handler(dev);
1811 }
1812
1813 static void i9xx_hpd_irq_handler(struct drm_device *dev)
1814 {
1815 struct drm_i915_private *dev_priv = dev->dev_private;
1816 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1817
1818 if (IS_G4X(dev)) {
1819 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1820
1821 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_g4x);
1822 } else {
1823 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1824
1825 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1826 }
1827
1828 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) &&
1829 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1830 dp_aux_irq_handler(dev);
1831
1832 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1833 /*
1834 * Make sure hotplug status is cleared before we clear IIR, or else we
1835 * may miss hotplug events.
1836 */
1837 POSTING_READ(PORT_HOTPLUG_STAT);
1838 }
1839
1840 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1841 {
1842 struct drm_device *dev = arg;
1843 struct drm_i915_private *dev_priv = dev->dev_private;
1844 u32 iir, gt_iir, pm_iir;
1845 irqreturn_t ret = IRQ_NONE;
1846
1847 while (true) {
1848 iir = I915_READ(VLV_IIR);
1849 gt_iir = I915_READ(GTIIR);
1850 pm_iir = I915_READ(GEN6_PMIIR);
1851
1852 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1853 goto out;
1854
1855 ret = IRQ_HANDLED;
1856
1857 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1858
1859 valleyview_pipestat_irq_handler(dev, iir);
1860
1861 /* Consume port. Then clear IIR or we'll miss events */
1862 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1863 i9xx_hpd_irq_handler(dev);
1864
1865 if (pm_iir)
1866 gen6_rps_irq_handler(dev_priv, pm_iir);
1867
1868 I915_WRITE(GTIIR, gt_iir);
1869 I915_WRITE(GEN6_PMIIR, pm_iir);
1870 I915_WRITE(VLV_IIR, iir);
1871 }
1872
1873 out:
1874 return ret;
1875 }
1876
1877 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1878 {
1879 struct drm_device *dev = arg;
1880 struct drm_i915_private *dev_priv = dev->dev_private;
1881 u32 master_ctl, iir;
1882 irqreturn_t ret = IRQ_NONE;
1883
1884 for (;;) {
1885 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1886 iir = I915_READ(VLV_IIR);
1887
1888 if (master_ctl == 0 && iir == 0)
1889 break;
1890
1891 I915_WRITE(GEN8_MASTER_IRQ, 0);
1892
1893 gen8_gt_irq_handler(dev, dev_priv, master_ctl);
1894
1895 valleyview_pipestat_irq_handler(dev, iir);
1896
1897 /* Consume port. Then clear IIR or we'll miss events */
1898 i9xx_hpd_irq_handler(dev);
1899
1900 I915_WRITE(VLV_IIR, iir);
1901
1902 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
1903 POSTING_READ(GEN8_MASTER_IRQ);
1904
1905 ret = IRQ_HANDLED;
1906 }
1907
1908 return ret;
1909 }
1910
1911 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1912 {
1913 struct drm_i915_private *dev_priv = dev->dev_private;
1914 int pipe;
1915 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1916
1917 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1918
1919 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1920 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1921 SDE_AUDIO_POWER_SHIFT);
1922 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1923 port_name(port));
1924 }
1925
1926 if (pch_iir & SDE_AUX_MASK)
1927 dp_aux_irq_handler(dev);
1928
1929 if (pch_iir & SDE_GMBUS)
1930 gmbus_irq_handler(dev);
1931
1932 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1933 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1934
1935 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1936 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1937
1938 if (pch_iir & SDE_POISON)
1939 DRM_ERROR("PCH poison interrupt\n");
1940
1941 if (pch_iir & SDE_FDI_MASK)
1942 for_each_pipe(pipe)
1943 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1944 pipe_name(pipe),
1945 I915_READ(FDI_RX_IIR(pipe)));
1946
1947 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1948 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1949
1950 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1951 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1952
1953 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1954 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1955 false))
1956 DRM_ERROR("PCH transcoder A FIFO underrun\n");
1957
1958 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1959 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1960 false))
1961 DRM_ERROR("PCH transcoder B FIFO underrun\n");
1962 }
1963
1964 static void ivb_err_int_handler(struct drm_device *dev)
1965 {
1966 struct drm_i915_private *dev_priv = dev->dev_private;
1967 u32 err_int = I915_READ(GEN7_ERR_INT);
1968 enum pipe pipe;
1969
1970 if (err_int & ERR_INT_POISON)
1971 DRM_ERROR("Poison interrupt\n");
1972
1973 for_each_pipe(pipe) {
1974 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
1975 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1976 false))
1977 DRM_ERROR("Pipe %c FIFO underrun\n",
1978 pipe_name(pipe));
1979 }
1980
1981 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1982 if (IS_IVYBRIDGE(dev))
1983 ivb_pipe_crc_irq_handler(dev, pipe);
1984 else
1985 hsw_pipe_crc_irq_handler(dev, pipe);
1986 }
1987 }
1988
1989 I915_WRITE(GEN7_ERR_INT, err_int);
1990 }
1991
1992 static void cpt_serr_int_handler(struct drm_device *dev)
1993 {
1994 struct drm_i915_private *dev_priv = dev->dev_private;
1995 u32 serr_int = I915_READ(SERR_INT);
1996
1997 if (serr_int & SERR_INT_POISON)
1998 DRM_ERROR("PCH poison interrupt\n");
1999
2000 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2001 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
2002 false))
2003 DRM_ERROR("PCH transcoder A FIFO underrun\n");
2004
2005 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2006 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
2007 false))
2008 DRM_ERROR("PCH transcoder B FIFO underrun\n");
2009
2010 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2011 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
2012 false))
2013 DRM_ERROR("PCH transcoder C FIFO underrun\n");
2014
2015 I915_WRITE(SERR_INT, serr_int);
2016 }
2017
2018 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
2019 {
2020 struct drm_i915_private *dev_priv = dev->dev_private;
2021 int pipe;
2022 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2023
2024 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
2025
2026 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2027 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2028 SDE_AUDIO_POWER_SHIFT_CPT);
2029 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2030 port_name(port));
2031 }
2032
2033 if (pch_iir & SDE_AUX_MASK_CPT)
2034 dp_aux_irq_handler(dev);
2035
2036 if (pch_iir & SDE_GMBUS_CPT)
2037 gmbus_irq_handler(dev);
2038
2039 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2040 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2041
2042 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2043 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2044
2045 if (pch_iir & SDE_FDI_MASK_CPT)
2046 for_each_pipe(pipe)
2047 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2048 pipe_name(pipe),
2049 I915_READ(FDI_RX_IIR(pipe)));
2050
2051 if (pch_iir & SDE_ERROR_CPT)
2052 cpt_serr_int_handler(dev);
2053 }
2054
2055 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
2056 {
2057 struct drm_i915_private *dev_priv = dev->dev_private;
2058 enum pipe pipe;
2059
2060 if (de_iir & DE_AUX_CHANNEL_A)
2061 dp_aux_irq_handler(dev);
2062
2063 if (de_iir & DE_GSE)
2064 intel_opregion_asle_intr(dev);
2065
2066 if (de_iir & DE_POISON)
2067 DRM_ERROR("Poison interrupt\n");
2068
2069 for_each_pipe(pipe) {
2070 if (de_iir & DE_PIPE_VBLANK(pipe))
2071 intel_pipe_handle_vblank(dev, pipe);
2072
2073 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2074 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
2075 DRM_ERROR("Pipe %c FIFO underrun\n",
2076 pipe_name(pipe));
2077
2078 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2079 i9xx_pipe_crc_irq_handler(dev, pipe);
2080
2081 /* plane/pipes map 1:1 on ilk+ */
2082 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
2083 intel_prepare_page_flip(dev, pipe);
2084 intel_finish_page_flip_plane(dev, pipe);
2085 }
2086 }
2087
2088 /* check event from PCH */
2089 if (de_iir & DE_PCH_EVENT) {
2090 u32 pch_iir = I915_READ(SDEIIR);
2091
2092 if (HAS_PCH_CPT(dev))
2093 cpt_irq_handler(dev, pch_iir);
2094 else
2095 ibx_irq_handler(dev, pch_iir);
2096
2097 /* should clear PCH hotplug event before clear CPU irq */
2098 I915_WRITE(SDEIIR, pch_iir);
2099 }
2100
2101 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
2102 ironlake_rps_change_irq_handler(dev);
2103 }
2104
2105 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
2106 {
2107 struct drm_i915_private *dev_priv = dev->dev_private;
2108 enum pipe pipe;
2109
2110 if (de_iir & DE_ERR_INT_IVB)
2111 ivb_err_int_handler(dev);
2112
2113 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2114 dp_aux_irq_handler(dev);
2115
2116 if (de_iir & DE_GSE_IVB)
2117 intel_opregion_asle_intr(dev);
2118
2119 for_each_pipe(pipe) {
2120 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
2121 intel_pipe_handle_vblank(dev, pipe);
2122
2123 /* plane/pipes map 1:1 on ilk+ */
2124 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
2125 intel_prepare_page_flip(dev, pipe);
2126 intel_finish_page_flip_plane(dev, pipe);
2127 }
2128 }
2129
2130 /* check event from PCH */
2131 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
2132 u32 pch_iir = I915_READ(SDEIIR);
2133
2134 cpt_irq_handler(dev, pch_iir);
2135
2136 /* clear PCH hotplug event before clear CPU irq */
2137 I915_WRITE(SDEIIR, pch_iir);
2138 }
2139 }
2140
2141 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2142 {
2143 struct drm_device *dev = arg;
2144 struct drm_i915_private *dev_priv = dev->dev_private;
2145 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2146 irqreturn_t ret = IRQ_NONE;
2147
2148 /* We get interrupts on unclaimed registers, so check for this before we
2149 * do any I915_{READ,WRITE}. */
2150 intel_uncore_check_errors(dev);
2151
2152 /* disable master interrupt before clearing iir */
2153 de_ier = I915_READ(DEIER);
2154 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2155 POSTING_READ(DEIER);
2156
2157 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2158 * interrupts will will be stored on its back queue, and then we'll be
2159 * able to process them after we restore SDEIER (as soon as we restore
2160 * it, we'll get an interrupt if SDEIIR still has something to process
2161 * due to its back queue). */
2162 if (!HAS_PCH_NOP(dev)) {
2163 sde_ier = I915_READ(SDEIER);
2164 I915_WRITE(SDEIER, 0);
2165 POSTING_READ(SDEIER);
2166 }
2167
2168 gt_iir = I915_READ(GTIIR);
2169 if (gt_iir) {
2170 if (INTEL_INFO(dev)->gen >= 6)
2171 snb_gt_irq_handler(dev, dev_priv, gt_iir);
2172 else
2173 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
2174 I915_WRITE(GTIIR, gt_iir);
2175 ret = IRQ_HANDLED;
2176 }
2177
2178 de_iir = I915_READ(DEIIR);
2179 if (de_iir) {
2180 if (INTEL_INFO(dev)->gen >= 7)
2181 ivb_display_irq_handler(dev, de_iir);
2182 else
2183 ilk_display_irq_handler(dev, de_iir);
2184 I915_WRITE(DEIIR, de_iir);
2185 ret = IRQ_HANDLED;
2186 }
2187
2188 if (INTEL_INFO(dev)->gen >= 6) {
2189 u32 pm_iir = I915_READ(GEN6_PMIIR);
2190 if (pm_iir) {
2191 gen6_rps_irq_handler(dev_priv, pm_iir);
2192 I915_WRITE(GEN6_PMIIR, pm_iir);
2193 ret = IRQ_HANDLED;
2194 }
2195 }
2196
2197 I915_WRITE(DEIER, de_ier);
2198 POSTING_READ(DEIER);
2199 if (!HAS_PCH_NOP(dev)) {
2200 I915_WRITE(SDEIER, sde_ier);
2201 POSTING_READ(SDEIER);
2202 }
2203
2204 return ret;
2205 }
2206
2207 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2208 {
2209 struct drm_device *dev = arg;
2210 struct drm_i915_private *dev_priv = dev->dev_private;
2211 u32 master_ctl;
2212 irqreturn_t ret = IRQ_NONE;
2213 uint32_t tmp = 0;
2214 enum pipe pipe;
2215
2216 master_ctl = I915_READ(GEN8_MASTER_IRQ);
2217 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2218 if (!master_ctl)
2219 return IRQ_NONE;
2220
2221 I915_WRITE(GEN8_MASTER_IRQ, 0);
2222 POSTING_READ(GEN8_MASTER_IRQ);
2223
2224 ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
2225
2226 if (master_ctl & GEN8_DE_MISC_IRQ) {
2227 tmp = I915_READ(GEN8_DE_MISC_IIR);
2228 if (tmp & GEN8_DE_MISC_GSE)
2229 intel_opregion_asle_intr(dev);
2230 else if (tmp)
2231 DRM_ERROR("Unexpected DE Misc interrupt\n");
2232 else
2233 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2234
2235 if (tmp) {
2236 I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2237 ret = IRQ_HANDLED;
2238 }
2239 }
2240
2241 if (master_ctl & GEN8_DE_PORT_IRQ) {
2242 tmp = I915_READ(GEN8_DE_PORT_IIR);
2243 if (tmp & GEN8_AUX_CHANNEL_A)
2244 dp_aux_irq_handler(dev);
2245 else if (tmp)
2246 DRM_ERROR("Unexpected DE Port interrupt\n");
2247 else
2248 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2249
2250 if (tmp) {
2251 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2252 ret = IRQ_HANDLED;
2253 }
2254 }
2255
2256 for_each_pipe(pipe) {
2257 uint32_t pipe_iir;
2258
2259 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2260 continue;
2261
2262 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2263 if (pipe_iir & GEN8_PIPE_VBLANK)
2264 intel_pipe_handle_vblank(dev, pipe);
2265
2266 if (pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE) {
2267 intel_prepare_page_flip(dev, pipe);
2268 intel_finish_page_flip_plane(dev, pipe);
2269 }
2270
2271 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2272 hsw_pipe_crc_irq_handler(dev, pipe);
2273
2274 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
2275 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
2276 false))
2277 DRM_ERROR("Pipe %c FIFO underrun\n",
2278 pipe_name(pipe));
2279 }
2280
2281 if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
2282 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2283 pipe_name(pipe),
2284 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2285 }
2286
2287 if (pipe_iir) {
2288 ret = IRQ_HANDLED;
2289 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2290 } else
2291 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2292 }
2293
2294 if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
2295 /*
2296 * FIXME(BDW): Assume for now that the new interrupt handling
2297 * scheme also closed the SDE interrupt handling race we've seen
2298 * on older pch-split platforms. But this needs testing.
2299 */
2300 u32 pch_iir = I915_READ(SDEIIR);
2301
2302 cpt_irq_handler(dev, pch_iir);
2303
2304 if (pch_iir) {
2305 I915_WRITE(SDEIIR, pch_iir);
2306 ret = IRQ_HANDLED;
2307 }
2308 }
2309
2310 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2311 POSTING_READ(GEN8_MASTER_IRQ);
2312
2313 return ret;
2314 }
2315
2316 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2317 bool reset_completed)
2318 {
2319 struct intel_engine_cs *ring;
2320 int i;
2321
2322 /*
2323 * Notify all waiters for GPU completion events that reset state has
2324 * been changed, and that they need to restart their wait after
2325 * checking for potential errors (and bail out to drop locks if there is
2326 * a gpu reset pending so that i915_error_work_func can acquire them).
2327 */
2328
2329 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2330 for_each_ring(ring, dev_priv, i)
2331 wake_up_all(&ring->irq_queue);
2332
2333 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2334 wake_up_all(&dev_priv->pending_flip_queue);
2335
2336 /*
2337 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2338 * reset state is cleared.
2339 */
2340 if (reset_completed)
2341 wake_up_all(&dev_priv->gpu_error.reset_queue);
2342 }
2343
2344 /**
2345 * i915_error_work_func - do process context error handling work
2346 * @work: work struct
2347 *
2348 * Fire an error uevent so userspace can see that a hang or error
2349 * was detected.
2350 */
2351 static void i915_error_work_func(struct work_struct *work)
2352 {
2353 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
2354 work);
2355 struct drm_i915_private *dev_priv =
2356 container_of(error, struct drm_i915_private, gpu_error);
2357 struct drm_device *dev = dev_priv->dev;
2358 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2359 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2360 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2361 int ret;
2362
2363 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2364
2365 /*
2366 * Note that there's only one work item which does gpu resets, so we
2367 * need not worry about concurrent gpu resets potentially incrementing
2368 * error->reset_counter twice. We only need to take care of another
2369 * racing irq/hangcheck declaring the gpu dead for a second time. A
2370 * quick check for that is good enough: schedule_work ensures the
2371 * correct ordering between hang detection and this work item, and since
2372 * the reset in-progress bit is only ever set by code outside of this
2373 * work we don't need to worry about any other races.
2374 */
2375 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2376 DRM_DEBUG_DRIVER("resetting chip\n");
2377 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2378 reset_event);
2379
2380 /*
2381 * In most cases it's guaranteed that we get here with an RPM
2382 * reference held, for example because there is a pending GPU
2383 * request that won't finish until the reset is done. This
2384 * isn't the case at least when we get here by doing a
2385 * simulated reset via debugs, so get an RPM reference.
2386 */
2387 intel_runtime_pm_get(dev_priv);
2388 /*
2389 * All state reset _must_ be completed before we update the
2390 * reset counter, for otherwise waiters might miss the reset
2391 * pending state and not properly drop locks, resulting in
2392 * deadlocks with the reset work.
2393 */
2394 ret = i915_reset(dev);
2395
2396 intel_display_handle_reset(dev);
2397
2398 intel_runtime_pm_put(dev_priv);
2399
2400 if (ret == 0) {
2401 /*
2402 * After all the gem state is reset, increment the reset
2403 * counter and wake up everyone waiting for the reset to
2404 * complete.
2405 *
2406 * Since unlock operations are a one-sided barrier only,
2407 * we need to insert a barrier here to order any seqno
2408 * updates before
2409 * the counter increment.
2410 */
2411 smp_mb__before_atomic_inc();
2412 atomic_inc(&dev_priv->gpu_error.reset_counter);
2413
2414 kobject_uevent_env(&dev->primary->kdev->kobj,
2415 KOBJ_CHANGE, reset_done_event);
2416 } else {
2417 atomic_set_mask(I915_WEDGED, &error->reset_counter);
2418 }
2419
2420 /*
2421 * Note: The wake_up also serves as a memory barrier so that
2422 * waiters see the update value of the reset counter atomic_t.
2423 */
2424 i915_error_wake_up(dev_priv, true);
2425 }
2426 }
2427
2428 static void i915_report_and_clear_eir(struct drm_device *dev)
2429 {
2430 struct drm_i915_private *dev_priv = dev->dev_private;
2431 uint32_t instdone[I915_NUM_INSTDONE_REG];
2432 u32 eir = I915_READ(EIR);
2433 int pipe, i;
2434
2435 if (!eir)
2436 return;
2437
2438 pr_err("render error detected, EIR: 0x%08x\n", eir);
2439
2440 i915_get_extra_instdone(dev, instdone);
2441
2442 if (IS_G4X(dev)) {
2443 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2444 u32 ipeir = I915_READ(IPEIR_I965);
2445
2446 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2447 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2448 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2449 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2450 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2451 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2452 I915_WRITE(IPEIR_I965, ipeir);
2453 POSTING_READ(IPEIR_I965);
2454 }
2455 if (eir & GM45_ERROR_PAGE_TABLE) {
2456 u32 pgtbl_err = I915_READ(PGTBL_ER);
2457 pr_err("page table error\n");
2458 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2459 I915_WRITE(PGTBL_ER, pgtbl_err);
2460 POSTING_READ(PGTBL_ER);
2461 }
2462 }
2463
2464 if (!IS_GEN2(dev)) {
2465 if (eir & I915_ERROR_PAGE_TABLE) {
2466 u32 pgtbl_err = I915_READ(PGTBL_ER);
2467 pr_err("page table error\n");
2468 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2469 I915_WRITE(PGTBL_ER, pgtbl_err);
2470 POSTING_READ(PGTBL_ER);
2471 }
2472 }
2473
2474 if (eir & I915_ERROR_MEMORY_REFRESH) {
2475 pr_err("memory refresh error:\n");
2476 for_each_pipe(pipe)
2477 pr_err("pipe %c stat: 0x%08x\n",
2478 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2479 /* pipestat has already been acked */
2480 }
2481 if (eir & I915_ERROR_INSTRUCTION) {
2482 pr_err("instruction error\n");
2483 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
2484 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2485 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2486 if (INTEL_INFO(dev)->gen < 4) {
2487 u32 ipeir = I915_READ(IPEIR);
2488
2489 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2490 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
2491 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
2492 I915_WRITE(IPEIR, ipeir);
2493 POSTING_READ(IPEIR);
2494 } else {
2495 u32 ipeir = I915_READ(IPEIR_I965);
2496
2497 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2498 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2499 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2500 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2501 I915_WRITE(IPEIR_I965, ipeir);
2502 POSTING_READ(IPEIR_I965);
2503 }
2504 }
2505
2506 I915_WRITE(EIR, eir);
2507 POSTING_READ(EIR);
2508 eir = I915_READ(EIR);
2509 if (eir) {
2510 /*
2511 * some errors might have become stuck,
2512 * mask them.
2513 */
2514 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2515 I915_WRITE(EMR, I915_READ(EMR) | eir);
2516 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2517 }
2518 }
2519
2520 /**
2521 * i915_handle_error - handle an error interrupt
2522 * @dev: drm device
2523 *
2524 * Do some basic checking of regsiter state at error interrupt time and
2525 * dump it to the syslog. Also call i915_capture_error_state() to make
2526 * sure we get a record and make it available in debugfs. Fire a uevent
2527 * so userspace knows something bad happened (should trigger collection
2528 * of a ring dump etc.).
2529 */
2530 void i915_handle_error(struct drm_device *dev, bool wedged,
2531 const char *fmt, ...)
2532 {
2533 struct drm_i915_private *dev_priv = dev->dev_private;
2534 va_list args;
2535 char error_msg[80];
2536
2537 va_start(args, fmt);
2538 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2539 va_end(args);
2540
2541 i915_capture_error_state(dev, wedged, error_msg);
2542 i915_report_and_clear_eir(dev);
2543
2544 if (wedged) {
2545 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2546 &dev_priv->gpu_error.reset_counter);
2547
2548 /*
2549 * Wakeup waiting processes so that the reset work function
2550 * i915_error_work_func doesn't deadlock trying to grab various
2551 * locks. By bumping the reset counter first, the woken
2552 * processes will see a reset in progress and back off,
2553 * releasing their locks and then wait for the reset completion.
2554 * We must do this for _all_ gpu waiters that might hold locks
2555 * that the reset work needs to acquire.
2556 *
2557 * Note: The wake_up serves as the required memory barrier to
2558 * ensure that the waiters see the updated value of the reset
2559 * counter atomic_t.
2560 */
2561 i915_error_wake_up(dev_priv, false);
2562 }
2563
2564 /*
2565 * Our reset work can grab modeset locks (since it needs to reset the
2566 * state of outstanding pagelips). Hence it must not be run on our own
2567 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2568 * code will deadlock.
2569 */
2570 schedule_work(&dev_priv->gpu_error.work);
2571 }
2572
2573 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
2574 {
2575 struct drm_i915_private *dev_priv = dev->dev_private;
2576 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2577 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2578 struct drm_i915_gem_object *obj;
2579 struct intel_unpin_work *work;
2580 unsigned long flags;
2581 bool stall_detected;
2582
2583 /* Ignore early vblank irqs */
2584 if (intel_crtc == NULL)
2585 return;
2586
2587 spin_lock_irqsave(&dev->event_lock, flags);
2588 work = intel_crtc->unpin_work;
2589
2590 if (work == NULL ||
2591 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2592 !work->enable_stall_check) {
2593 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2594 spin_unlock_irqrestore(&dev->event_lock, flags);
2595 return;
2596 }
2597
2598 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2599 obj = work->pending_flip_obj;
2600 if (INTEL_INFO(dev)->gen >= 4) {
2601 int dspsurf = DSPSURF(intel_crtc->plane);
2602 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
2603 i915_gem_obj_ggtt_offset(obj);
2604 } else {
2605 int dspaddr = DSPADDR(intel_crtc->plane);
2606 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
2607 crtc->y * crtc->primary->fb->pitches[0] +
2608 crtc->x * crtc->primary->fb->bits_per_pixel/8);
2609 }
2610
2611 spin_unlock_irqrestore(&dev->event_lock, flags);
2612
2613 if (stall_detected) {
2614 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2615 intel_prepare_page_flip(dev, intel_crtc->plane);
2616 }
2617 }
2618
2619 /* Called from drm generic code, passed 'crtc' which
2620 * we use as a pipe index
2621 */
2622 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2623 {
2624 struct drm_i915_private *dev_priv = dev->dev_private;
2625 unsigned long irqflags;
2626
2627 if (!i915_pipe_enabled(dev, pipe))
2628 return -EINVAL;
2629
2630 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2631 if (INTEL_INFO(dev)->gen >= 4)
2632 i915_enable_pipestat(dev_priv, pipe,
2633 PIPE_START_VBLANK_INTERRUPT_STATUS);
2634 else
2635 i915_enable_pipestat(dev_priv, pipe,
2636 PIPE_VBLANK_INTERRUPT_STATUS);
2637
2638 /* maintain vblank delivery even in deep C-states */
2639 if (INTEL_INFO(dev)->gen == 3)
2640 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
2641 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2642
2643 return 0;
2644 }
2645
2646 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2647 {
2648 struct drm_i915_private *dev_priv = dev->dev_private;
2649 unsigned long irqflags;
2650 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2651 DE_PIPE_VBLANK(pipe);
2652
2653 if (!i915_pipe_enabled(dev, pipe))
2654 return -EINVAL;
2655
2656 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2657 ironlake_enable_display_irq(dev_priv, bit);
2658 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2659
2660 return 0;
2661 }
2662
2663 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2664 {
2665 struct drm_i915_private *dev_priv = dev->dev_private;
2666 unsigned long irqflags;
2667
2668 if (!i915_pipe_enabled(dev, pipe))
2669 return -EINVAL;
2670
2671 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2672 i915_enable_pipestat(dev_priv, pipe,
2673 PIPE_START_VBLANK_INTERRUPT_STATUS);
2674 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2675
2676 return 0;
2677 }
2678
2679 static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2680 {
2681 struct drm_i915_private *dev_priv = dev->dev_private;
2682 unsigned long irqflags;
2683
2684 if (!i915_pipe_enabled(dev, pipe))
2685 return -EINVAL;
2686
2687 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2688 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2689 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2690 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2691 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2692 return 0;
2693 }
2694
2695 /* Called from drm generic code, passed 'crtc' which
2696 * we use as a pipe index
2697 */
2698 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2699 {
2700 struct drm_i915_private *dev_priv = dev->dev_private;
2701 unsigned long irqflags;
2702
2703 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2704 if (INTEL_INFO(dev)->gen == 3)
2705 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
2706
2707 i915_disable_pipestat(dev_priv, pipe,
2708 PIPE_VBLANK_INTERRUPT_STATUS |
2709 PIPE_START_VBLANK_INTERRUPT_STATUS);
2710 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2711 }
2712
2713 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2714 {
2715 struct drm_i915_private *dev_priv = dev->dev_private;
2716 unsigned long irqflags;
2717 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2718 DE_PIPE_VBLANK(pipe);
2719
2720 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2721 ironlake_disable_display_irq(dev_priv, bit);
2722 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2723 }
2724
2725 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2726 {
2727 struct drm_i915_private *dev_priv = dev->dev_private;
2728 unsigned long irqflags;
2729
2730 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2731 i915_disable_pipestat(dev_priv, pipe,
2732 PIPE_START_VBLANK_INTERRUPT_STATUS);
2733 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2734 }
2735
2736 static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2737 {
2738 struct drm_i915_private *dev_priv = dev->dev_private;
2739 unsigned long irqflags;
2740
2741 if (!i915_pipe_enabled(dev, pipe))
2742 return;
2743
2744 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2745 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2746 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2747 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2748 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2749 }
2750
2751 static u32
2752 ring_last_seqno(struct intel_engine_cs *ring)
2753 {
2754 return list_entry(ring->request_list.prev,
2755 struct drm_i915_gem_request, list)->seqno;
2756 }
2757
2758 static bool
2759 ring_idle(struct intel_engine_cs *ring, u32 seqno)
2760 {
2761 return (list_empty(&ring->request_list) ||
2762 i915_seqno_passed(seqno, ring_last_seqno(ring)));
2763 }
2764
2765 static bool
2766 ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
2767 {
2768 if (INTEL_INFO(dev)->gen >= 8) {
2769 /*
2770 * FIXME: gen8 semaphore support - currently we don't emit
2771 * semaphores on bdw anyway, but this needs to be addressed when
2772 * we merge that code.
2773 */
2774 return false;
2775 } else {
2776 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2777 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2778 MI_SEMAPHORE_REGISTER);
2779 }
2780 }
2781
2782 static struct intel_engine_cs *
2783 semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr)
2784 {
2785 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2786 struct intel_engine_cs *signaller;
2787 int i;
2788
2789 if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
2790 /*
2791 * FIXME: gen8 semaphore support - currently we don't emit
2792 * semaphores on bdw anyway, but this needs to be addressed when
2793 * we merge that code.
2794 */
2795 return NULL;
2796 } else {
2797 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2798
2799 for_each_ring(signaller, dev_priv, i) {
2800 if(ring == signaller)
2801 continue;
2802
2803 if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
2804 return signaller;
2805 }
2806 }
2807
2808 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x\n",
2809 ring->id, ipehr);
2810
2811 return NULL;
2812 }
2813
2814 static struct intel_engine_cs *
2815 semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
2816 {
2817 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2818 u32 cmd, ipehr, head;
2819 int i;
2820
2821 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2822 if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
2823 return NULL;
2824
2825 /*
2826 * HEAD is likely pointing to the dword after the actual command,
2827 * so scan backwards until we find the MBOX. But limit it to just 3
2828 * dwords. Note that we don't care about ACTHD here since that might
2829 * point at at batch, and semaphores are always emitted into the
2830 * ringbuffer itself.
2831 */
2832 head = I915_READ_HEAD(ring) & HEAD_ADDR;
2833
2834 for (i = 4; i; --i) {
2835 /*
2836 * Be paranoid and presume the hw has gone off into the wild -
2837 * our ring is smaller than what the hardware (and hence
2838 * HEAD_ADDR) allows. Also handles wrap-around.
2839 */
2840 head &= ring->buffer->size - 1;
2841
2842 /* This here seems to blow up */
2843 cmd = ioread32(ring->buffer->virtual_start + head);
2844 if (cmd == ipehr)
2845 break;
2846
2847 head -= 4;
2848 }
2849
2850 if (!i)
2851 return NULL;
2852
2853 *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
2854 return semaphore_wait_to_signaller_ring(ring, ipehr);
2855 }
2856
2857 static int semaphore_passed(struct intel_engine_cs *ring)
2858 {
2859 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2860 struct intel_engine_cs *signaller;
2861 u32 seqno, ctl;
2862
2863 ring->hangcheck.deadlock = true;
2864
2865 signaller = semaphore_waits_for(ring, &seqno);
2866 if (signaller == NULL || signaller->hangcheck.deadlock)
2867 return -1;
2868
2869 /* cursory check for an unkickable deadlock */
2870 ctl = I915_READ_CTL(signaller);
2871 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2872 return -1;
2873
2874 return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
2875 }
2876
2877 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2878 {
2879 struct intel_engine_cs *ring;
2880 int i;
2881
2882 for_each_ring(ring, dev_priv, i)
2883 ring->hangcheck.deadlock = false;
2884 }
2885
2886 static enum intel_ring_hangcheck_action
2887 ring_stuck(struct intel_engine_cs *ring, u64 acthd)
2888 {
2889 struct drm_device *dev = ring->dev;
2890 struct drm_i915_private *dev_priv = dev->dev_private;
2891 u32 tmp;
2892
2893 if (ring->hangcheck.acthd != acthd)
2894 return HANGCHECK_ACTIVE;
2895
2896 if (IS_GEN2(dev))
2897 return HANGCHECK_HUNG;
2898
2899 /* Is the chip hanging on a WAIT_FOR_EVENT?
2900 * If so we can simply poke the RB_WAIT bit
2901 * and break the hang. This should work on
2902 * all but the second generation chipsets.
2903 */
2904 tmp = I915_READ_CTL(ring);
2905 if (tmp & RING_WAIT) {
2906 i915_handle_error(dev, false,
2907 "Kicking stuck wait on %s",
2908 ring->name);
2909 I915_WRITE_CTL(ring, tmp);
2910 return HANGCHECK_KICK;
2911 }
2912
2913 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2914 switch (semaphore_passed(ring)) {
2915 default:
2916 return HANGCHECK_HUNG;
2917 case 1:
2918 i915_handle_error(dev, false,
2919 "Kicking stuck semaphore on %s",
2920 ring->name);
2921 I915_WRITE_CTL(ring, tmp);
2922 return HANGCHECK_KICK;
2923 case 0:
2924 return HANGCHECK_WAIT;
2925 }
2926 }
2927
2928 return HANGCHECK_HUNG;
2929 }
2930
2931 /**
2932 * This is called when the chip hasn't reported back with completed
2933 * batchbuffers in a long time. We keep track per ring seqno progress and
2934 * if there are no progress, hangcheck score for that ring is increased.
2935 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2936 * we kick the ring. If we see no progress on three subsequent calls
2937 * we assume chip is wedged and try to fix it by resetting the chip.
2938 */
2939 static void i915_hangcheck_elapsed(unsigned long data)
2940 {
2941 struct drm_device *dev = (struct drm_device *)data;
2942 struct drm_i915_private *dev_priv = dev->dev_private;
2943 struct intel_engine_cs *ring;
2944 int i;
2945 int busy_count = 0, rings_hung = 0;
2946 bool stuck[I915_NUM_RINGS] = { 0 };
2947 #define BUSY 1
2948 #define KICK 5
2949 #define HUNG 20
2950
2951 if (!i915.enable_hangcheck)
2952 return;
2953
2954 for_each_ring(ring, dev_priv, i) {
2955 u64 acthd;
2956 u32 seqno;
2957 bool busy = true;
2958
2959 semaphore_clear_deadlocks(dev_priv);
2960
2961 seqno = ring->get_seqno(ring, false);
2962 acthd = intel_ring_get_active_head(ring);
2963
2964 if (ring->hangcheck.seqno == seqno) {
2965 if (ring_idle(ring, seqno)) {
2966 ring->hangcheck.action = HANGCHECK_IDLE;
2967
2968 if (waitqueue_active(&ring->irq_queue)) {
2969 /* Issue a wake-up to catch stuck h/w. */
2970 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2971 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2972 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2973 ring->name);
2974 else
2975 DRM_INFO("Fake missed irq on %s\n",
2976 ring->name);
2977 wake_up_all(&ring->irq_queue);
2978 }
2979 /* Safeguard against driver failure */
2980 ring->hangcheck.score += BUSY;
2981 } else
2982 busy = false;
2983 } else {
2984 /* We always increment the hangcheck score
2985 * if the ring is busy and still processing
2986 * the same request, so that no single request
2987 * can run indefinitely (such as a chain of
2988 * batches). The only time we do not increment
2989 * the hangcheck score on this ring, if this
2990 * ring is in a legitimate wait for another
2991 * ring. In that case the waiting ring is a
2992 * victim and we want to be sure we catch the
2993 * right culprit. Then every time we do kick
2994 * the ring, add a small increment to the
2995 * score so that we can catch a batch that is
2996 * being repeatedly kicked and so responsible
2997 * for stalling the machine.
2998 */
2999 ring->hangcheck.action = ring_stuck(ring,
3000 acthd);
3001
3002 switch (ring->hangcheck.action) {
3003 case HANGCHECK_IDLE:
3004 case HANGCHECK_WAIT:
3005 break;
3006 case HANGCHECK_ACTIVE:
3007 ring->hangcheck.score += BUSY;
3008 break;
3009 case HANGCHECK_KICK:
3010 ring->hangcheck.score += KICK;
3011 break;
3012 case HANGCHECK_HUNG:
3013 ring->hangcheck.score += HUNG;
3014 stuck[i] = true;
3015 break;
3016 }
3017 }
3018 } else {
3019 ring->hangcheck.action = HANGCHECK_ACTIVE;
3020
3021 /* Gradually reduce the count so that we catch DoS
3022 * attempts across multiple batches.
3023 */
3024 if (ring->hangcheck.score > 0)
3025 ring->hangcheck.score--;
3026 }
3027
3028 ring->hangcheck.seqno = seqno;
3029 ring->hangcheck.acthd = acthd;
3030 busy_count += busy;
3031 }
3032
3033 for_each_ring(ring, dev_priv, i) {
3034 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3035 DRM_INFO("%s on %s\n",
3036 stuck[i] ? "stuck" : "no progress",
3037 ring->name);
3038 rings_hung++;
3039 }
3040 }
3041
3042 if (rings_hung)
3043 return i915_handle_error(dev, true, "Ring hung");
3044
3045 if (busy_count)
3046 /* Reset timer case chip hangs without another request
3047 * being added */
3048 i915_queue_hangcheck(dev);
3049 }
3050
3051 void i915_queue_hangcheck(struct drm_device *dev)
3052 {
3053 struct drm_i915_private *dev_priv = dev->dev_private;
3054 if (!i915.enable_hangcheck)
3055 return;
3056
3057 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
3058 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
3059 }
3060
3061 static void ibx_irq_reset(struct drm_device *dev)
3062 {
3063 struct drm_i915_private *dev_priv = dev->dev_private;
3064
3065 if (HAS_PCH_NOP(dev))
3066 return;
3067
3068 GEN5_IRQ_RESET(SDE);
3069
3070 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3071 I915_WRITE(SERR_INT, 0xffffffff);
3072 }
3073
3074 /*
3075 * SDEIER is also touched by the interrupt handler to work around missed PCH
3076 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3077 * instead we unconditionally enable all PCH interrupt sources here, but then
3078 * only unmask them as needed with SDEIMR.
3079 *
3080 * This function needs to be called before interrupts are enabled.
3081 */
3082 static void ibx_irq_pre_postinstall(struct drm_device *dev)
3083 {
3084 struct drm_i915_private *dev_priv = dev->dev_private;
3085
3086 if (HAS_PCH_NOP(dev))
3087 return;
3088
3089 WARN_ON(I915_READ(SDEIER) != 0);
3090 I915_WRITE(SDEIER, 0xffffffff);
3091 POSTING_READ(SDEIER);
3092 }
3093
3094 static void gen5_gt_irq_reset(struct drm_device *dev)
3095 {
3096 struct drm_i915_private *dev_priv = dev->dev_private;
3097
3098 GEN5_IRQ_RESET(GT);
3099 if (INTEL_INFO(dev)->gen >= 6)
3100 GEN5_IRQ_RESET(GEN6_PM);
3101 }
3102
3103 /* drm_dma.h hooks
3104 */
3105 static void ironlake_irq_reset(struct drm_device *dev)
3106 {
3107 struct drm_i915_private *dev_priv = dev->dev_private;
3108
3109 I915_WRITE(HWSTAM, 0xffffffff);
3110
3111 GEN5_IRQ_RESET(DE);
3112 if (IS_GEN7(dev))
3113 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3114
3115 gen5_gt_irq_reset(dev);
3116
3117 ibx_irq_reset(dev);
3118 }
3119
3120 static void ironlake_irq_preinstall(struct drm_device *dev)
3121 {
3122 ironlake_irq_reset(dev);
3123 }
3124
3125 static void valleyview_irq_preinstall(struct drm_device *dev)
3126 {
3127 struct drm_i915_private *dev_priv = dev->dev_private;
3128 int pipe;
3129
3130 /* VLV magic */
3131 I915_WRITE(VLV_IMR, 0);
3132 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
3133 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
3134 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
3135
3136 /* and GT */
3137 I915_WRITE(GTIIR, I915_READ(GTIIR));
3138 I915_WRITE(GTIIR, I915_READ(GTIIR));
3139
3140 gen5_gt_irq_reset(dev);
3141
3142 I915_WRITE(DPINVGTT, 0xff);
3143
3144 I915_WRITE(PORT_HOTPLUG_EN, 0);
3145 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3146 for_each_pipe(pipe)
3147 I915_WRITE(PIPESTAT(pipe), 0xffff);
3148 I915_WRITE(VLV_IIR, 0xffffffff);
3149 I915_WRITE(VLV_IMR, 0xffffffff);
3150 I915_WRITE(VLV_IER, 0x0);
3151 POSTING_READ(VLV_IER);
3152 }
3153
3154 static void gen8_irq_reset(struct drm_device *dev)
3155 {
3156 struct drm_i915_private *dev_priv = dev->dev_private;
3157 int pipe;
3158
3159 I915_WRITE(GEN8_MASTER_IRQ, 0);
3160 POSTING_READ(GEN8_MASTER_IRQ);
3161
3162 GEN8_IRQ_RESET_NDX(GT, 0);
3163 GEN8_IRQ_RESET_NDX(GT, 1);
3164 GEN8_IRQ_RESET_NDX(GT, 2);
3165 GEN8_IRQ_RESET_NDX(GT, 3);
3166
3167 for_each_pipe(pipe)
3168 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3169
3170 GEN5_IRQ_RESET(GEN8_DE_PORT_);
3171 GEN5_IRQ_RESET(GEN8_DE_MISC_);
3172 GEN5_IRQ_RESET(GEN8_PCU_);
3173
3174 ibx_irq_reset(dev);
3175 }
3176
3177 static void gen8_irq_preinstall(struct drm_device *dev)
3178 {
3179 gen8_irq_reset(dev);
3180 }
3181
3182 static void cherryview_irq_preinstall(struct drm_device *dev)
3183 {
3184 struct drm_i915_private *dev_priv = dev->dev_private;
3185 int pipe;
3186
3187 I915_WRITE(GEN8_MASTER_IRQ, 0);
3188 POSTING_READ(GEN8_MASTER_IRQ);
3189
3190 GEN8_IRQ_RESET_NDX(GT, 0);
3191 GEN8_IRQ_RESET_NDX(GT, 1);
3192 GEN8_IRQ_RESET_NDX(GT, 2);
3193 GEN8_IRQ_RESET_NDX(GT, 3);
3194
3195 GEN5_IRQ_RESET(GEN8_PCU_);
3196
3197 POSTING_READ(GEN8_PCU_IIR);
3198
3199 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3200
3201 I915_WRITE(PORT_HOTPLUG_EN, 0);
3202 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3203
3204 for_each_pipe(pipe)
3205 I915_WRITE(PIPESTAT(pipe), 0xffff);
3206
3207 I915_WRITE(VLV_IMR, 0xffffffff);
3208 I915_WRITE(VLV_IER, 0x0);
3209 I915_WRITE(VLV_IIR, 0xffffffff);
3210 POSTING_READ(VLV_IIR);
3211 }
3212
3213 static void ibx_hpd_irq_setup(struct drm_device *dev)
3214 {
3215 struct drm_i915_private *dev_priv = dev->dev_private;
3216 struct drm_mode_config *mode_config = &dev->mode_config;
3217 struct intel_encoder *intel_encoder;
3218 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
3219
3220 if (HAS_PCH_IBX(dev)) {
3221 hotplug_irqs = SDE_HOTPLUG_MASK;
3222 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3223 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3224 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
3225 } else {
3226 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3227 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3228 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3229 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
3230 }
3231
3232 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3233
3234 /*
3235 * Enable digital hotplug on the PCH, and configure the DP short pulse
3236 * duration to 2ms (which is the minimum in the Display Port spec)
3237 *
3238 * This register is the same on all known PCH chips.
3239 */
3240 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3241 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3242 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3243 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3244 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3245 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3246 }
3247
3248 static void ibx_irq_postinstall(struct drm_device *dev)
3249 {
3250 struct drm_i915_private *dev_priv = dev->dev_private;
3251 u32 mask;
3252
3253 if (HAS_PCH_NOP(dev))
3254 return;
3255
3256 if (HAS_PCH_IBX(dev))
3257 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3258 else
3259 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3260
3261 GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
3262 I915_WRITE(SDEIMR, ~mask);
3263 }
3264
3265 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3266 {
3267 struct drm_i915_private *dev_priv = dev->dev_private;
3268 u32 pm_irqs, gt_irqs;
3269
3270 pm_irqs = gt_irqs = 0;
3271
3272 dev_priv->gt_irq_mask = ~0;
3273 if (HAS_L3_DPF(dev)) {
3274 /* L3 parity interrupt is always unmasked. */
3275 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3276 gt_irqs |= GT_PARITY_ERROR(dev);
3277 }
3278
3279 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3280 if (IS_GEN5(dev)) {
3281 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3282 ILK_BSD_USER_INTERRUPT;
3283 } else {
3284 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3285 }
3286
3287 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3288
3289 if (INTEL_INFO(dev)->gen >= 6) {
3290 pm_irqs |= dev_priv->pm_rps_events;
3291
3292 if (HAS_VEBOX(dev))
3293 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3294
3295 dev_priv->pm_irq_mask = 0xffffffff;
3296 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3297 }
3298 }
3299
3300 static int ironlake_irq_postinstall(struct drm_device *dev)
3301 {
3302 unsigned long irqflags;
3303 struct drm_i915_private *dev_priv = dev->dev_private;
3304 u32 display_mask, extra_mask;
3305
3306 if (INTEL_INFO(dev)->gen >= 7) {
3307 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3308 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3309 DE_PLANEB_FLIP_DONE_IVB |
3310 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3311 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3312 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
3313 } else {
3314 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3315 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3316 DE_AUX_CHANNEL_A |
3317 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3318 DE_POISON);
3319 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3320 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
3321 }
3322
3323 dev_priv->irq_mask = ~display_mask;
3324
3325 I915_WRITE(HWSTAM, 0xeffe);
3326
3327 ibx_irq_pre_postinstall(dev);
3328
3329 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3330
3331 gen5_gt_irq_postinstall(dev);
3332
3333 ibx_irq_postinstall(dev);
3334
3335 if (IS_IRONLAKE_M(dev)) {
3336 /* Enable PCU event interrupts
3337 *
3338 * spinlocking not required here for correctness since interrupt
3339 * setup is guaranteed to run in single-threaded context. But we
3340 * need it to make the assert_spin_locked happy. */
3341 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3342 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
3343 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3344 }
3345
3346 return 0;
3347 }
3348
3349 static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3350 {
3351 u32 pipestat_mask;
3352 u32 iir_mask;
3353
3354 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3355 PIPE_FIFO_UNDERRUN_STATUS;
3356
3357 I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3358 I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3359 POSTING_READ(PIPESTAT(PIPE_A));
3360
3361 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3362 PIPE_CRC_DONE_INTERRUPT_STATUS;
3363
3364 i915_enable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3365 PIPE_GMBUS_INTERRUPT_STATUS);
3366 i915_enable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3367
3368 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3369 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3370 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3371 dev_priv->irq_mask &= ~iir_mask;
3372
3373 I915_WRITE(VLV_IIR, iir_mask);
3374 I915_WRITE(VLV_IIR, iir_mask);
3375 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3376 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3377 POSTING_READ(VLV_IER);
3378 }
3379
3380 static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3381 {
3382 u32 pipestat_mask;
3383 u32 iir_mask;
3384
3385 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3386 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3387 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3388
3389 dev_priv->irq_mask |= iir_mask;
3390 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3391 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3392 I915_WRITE(VLV_IIR, iir_mask);
3393 I915_WRITE(VLV_IIR, iir_mask);
3394 POSTING_READ(VLV_IIR);
3395
3396 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3397 PIPE_CRC_DONE_INTERRUPT_STATUS;
3398
3399 i915_disable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3400 PIPE_GMBUS_INTERRUPT_STATUS);
3401 i915_disable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3402
3403 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3404 PIPE_FIFO_UNDERRUN_STATUS;
3405 I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3406 I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3407 POSTING_READ(PIPESTAT(PIPE_A));
3408 }
3409
3410 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3411 {
3412 assert_spin_locked(&dev_priv->irq_lock);
3413
3414 if (dev_priv->display_irqs_enabled)
3415 return;
3416
3417 dev_priv->display_irqs_enabled = true;
3418
3419 if (dev_priv->dev->irq_enabled)
3420 valleyview_display_irqs_install(dev_priv);
3421 }
3422
3423 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3424 {
3425 assert_spin_locked(&dev_priv->irq_lock);
3426
3427 if (!dev_priv->display_irqs_enabled)
3428 return;
3429
3430 dev_priv->display_irqs_enabled = false;
3431
3432 if (dev_priv->dev->irq_enabled)
3433 valleyview_display_irqs_uninstall(dev_priv);
3434 }
3435
3436 static int valleyview_irq_postinstall(struct drm_device *dev)
3437 {
3438 struct drm_i915_private *dev_priv = dev->dev_private;
3439 unsigned long irqflags;
3440
3441 dev_priv->irq_mask = ~0;
3442
3443 I915_WRITE(PORT_HOTPLUG_EN, 0);
3444 POSTING_READ(PORT_HOTPLUG_EN);
3445
3446 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3447 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3448 I915_WRITE(VLV_IIR, 0xffffffff);
3449 POSTING_READ(VLV_IER);
3450
3451 /* Interrupt setup is already guaranteed to be single-threaded, this is
3452 * just to make the assert_spin_locked check happy. */
3453 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3454 if (dev_priv->display_irqs_enabled)
3455 valleyview_display_irqs_install(dev_priv);
3456 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3457
3458 I915_WRITE(VLV_IIR, 0xffffffff);
3459 I915_WRITE(VLV_IIR, 0xffffffff);
3460
3461 gen5_gt_irq_postinstall(dev);
3462
3463 /* ack & enable invalid PTE error interrupts */
3464 #if 0 /* FIXME: add support to irq handler for checking these bits */
3465 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3466 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3467 #endif
3468
3469 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3470
3471 return 0;
3472 }
3473
3474 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3475 {
3476 int i;
3477
3478 /* These are interrupts we'll toggle with the ring mask register */
3479 uint32_t gt_interrupts[] = {
3480 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3481 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3482 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3483 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3484 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3485 0,
3486 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3487 };
3488
3489 for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++)
3490 GEN8_IRQ_INIT_NDX(GT, i, ~gt_interrupts[i], gt_interrupts[i]);
3491
3492 dev_priv->pm_irq_mask = 0xffffffff;
3493 }
3494
3495 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3496 {
3497 struct drm_device *dev = dev_priv->dev;
3498 uint32_t de_pipe_masked = GEN8_PIPE_PRIMARY_FLIP_DONE |
3499 GEN8_PIPE_CDCLK_CRC_DONE |
3500 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3501 uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3502 GEN8_PIPE_FIFO_UNDERRUN;
3503 int pipe;
3504 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3505 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3506 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3507
3508 for_each_pipe(pipe)
3509 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, dev_priv->de_irq_mask[pipe],
3510 de_pipe_enables);
3511
3512 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~GEN8_AUX_CHANNEL_A, GEN8_AUX_CHANNEL_A);
3513 }
3514
3515 static int gen8_irq_postinstall(struct drm_device *dev)
3516 {
3517 struct drm_i915_private *dev_priv = dev->dev_private;
3518
3519 ibx_irq_pre_postinstall(dev);
3520
3521 gen8_gt_irq_postinstall(dev_priv);
3522 gen8_de_irq_postinstall(dev_priv);
3523
3524 ibx_irq_postinstall(dev);
3525
3526 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3527 POSTING_READ(GEN8_MASTER_IRQ);
3528
3529 return 0;
3530 }
3531
3532 static int cherryview_irq_postinstall(struct drm_device *dev)
3533 {
3534 struct drm_i915_private *dev_priv = dev->dev_private;
3535 u32 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
3536 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3537 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3538 I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3539 u32 pipestat_enable = PLANE_FLIP_DONE_INT_STATUS_VLV |
3540 PIPE_CRC_DONE_INTERRUPT_STATUS;
3541 unsigned long irqflags;
3542 int pipe;
3543
3544 /*
3545 * Leave vblank interrupts masked initially. enable/disable will
3546 * toggle them based on usage.
3547 */
3548 dev_priv->irq_mask = ~enable_mask;
3549
3550 for_each_pipe(pipe)
3551 I915_WRITE(PIPESTAT(pipe), 0xffff);
3552
3553 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3554 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3555 for_each_pipe(pipe)
3556 i915_enable_pipestat(dev_priv, pipe, pipestat_enable);
3557 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3558
3559 I915_WRITE(VLV_IIR, 0xffffffff);
3560 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3561 I915_WRITE(VLV_IER, enable_mask);
3562
3563 gen8_gt_irq_postinstall(dev_priv);
3564
3565 I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
3566 POSTING_READ(GEN8_MASTER_IRQ);
3567
3568 return 0;
3569 }
3570
3571 static void gen8_irq_uninstall(struct drm_device *dev)
3572 {
3573 struct drm_i915_private *dev_priv = dev->dev_private;
3574
3575 if (!dev_priv)
3576 return;
3577
3578 intel_hpd_irq_uninstall(dev_priv);
3579
3580 gen8_irq_reset(dev);
3581 }
3582
3583 static void valleyview_irq_uninstall(struct drm_device *dev)
3584 {
3585 struct drm_i915_private *dev_priv = dev->dev_private;
3586 unsigned long irqflags;
3587 int pipe;
3588
3589 if (!dev_priv)
3590 return;
3591
3592 I915_WRITE(VLV_MASTER_IER, 0);
3593
3594 intel_hpd_irq_uninstall(dev_priv);
3595
3596 for_each_pipe(pipe)
3597 I915_WRITE(PIPESTAT(pipe), 0xffff);
3598
3599 I915_WRITE(HWSTAM, 0xffffffff);
3600 I915_WRITE(PORT_HOTPLUG_EN, 0);
3601 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3602
3603 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3604 if (dev_priv->display_irqs_enabled)
3605 valleyview_display_irqs_uninstall(dev_priv);
3606 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3607
3608 dev_priv->irq_mask = 0;
3609
3610 I915_WRITE(VLV_IIR, 0xffffffff);
3611 I915_WRITE(VLV_IMR, 0xffffffff);
3612 I915_WRITE(VLV_IER, 0x0);
3613 POSTING_READ(VLV_IER);
3614 }
3615
3616 static void cherryview_irq_uninstall(struct drm_device *dev)
3617 {
3618 struct drm_i915_private *dev_priv = dev->dev_private;
3619 int pipe;
3620
3621 if (!dev_priv)
3622 return;
3623
3624 I915_WRITE(GEN8_MASTER_IRQ, 0);
3625 POSTING_READ(GEN8_MASTER_IRQ);
3626
3627 #define GEN8_IRQ_FINI_NDX(type, which) \
3628 do { \
3629 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
3630 I915_WRITE(GEN8_##type##_IER(which), 0); \
3631 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
3632 POSTING_READ(GEN8_##type##_IIR(which)); \
3633 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
3634 } while (0)
3635
3636 #define GEN8_IRQ_FINI(type) \
3637 do { \
3638 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
3639 I915_WRITE(GEN8_##type##_IER, 0); \
3640 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
3641 POSTING_READ(GEN8_##type##_IIR); \
3642 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
3643 } while (0)
3644
3645 GEN8_IRQ_FINI_NDX(GT, 0);
3646 GEN8_IRQ_FINI_NDX(GT, 1);
3647 GEN8_IRQ_FINI_NDX(GT, 2);
3648 GEN8_IRQ_FINI_NDX(GT, 3);
3649
3650 GEN8_IRQ_FINI(PCU);
3651
3652 #undef GEN8_IRQ_FINI
3653 #undef GEN8_IRQ_FINI_NDX
3654
3655 I915_WRITE(PORT_HOTPLUG_EN, 0);
3656 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3657
3658 for_each_pipe(pipe)
3659 I915_WRITE(PIPESTAT(pipe), 0xffff);
3660
3661 I915_WRITE(VLV_IMR, 0xffffffff);
3662 I915_WRITE(VLV_IER, 0x0);
3663 I915_WRITE(VLV_IIR, 0xffffffff);
3664 POSTING_READ(VLV_IIR);
3665 }
3666
3667 static void ironlake_irq_uninstall(struct drm_device *dev)
3668 {
3669 struct drm_i915_private *dev_priv = dev->dev_private;
3670
3671 if (!dev_priv)
3672 return;
3673
3674 intel_hpd_irq_uninstall(dev_priv);
3675
3676 ironlake_irq_reset(dev);
3677 }
3678
3679 static void i8xx_irq_preinstall(struct drm_device * dev)
3680 {
3681 struct drm_i915_private *dev_priv = dev->dev_private;
3682 int pipe;
3683
3684 for_each_pipe(pipe)
3685 I915_WRITE(PIPESTAT(pipe), 0);
3686 I915_WRITE16(IMR, 0xffff);
3687 I915_WRITE16(IER, 0x0);
3688 POSTING_READ16(IER);
3689 }
3690
3691 static int i8xx_irq_postinstall(struct drm_device *dev)
3692 {
3693 struct drm_i915_private *dev_priv = dev->dev_private;
3694 unsigned long irqflags;
3695
3696 I915_WRITE16(EMR,
3697 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3698
3699 /* Unmask the interrupts that we always want on. */
3700 dev_priv->irq_mask =
3701 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3702 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3703 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3704 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3705 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3706 I915_WRITE16(IMR, dev_priv->irq_mask);
3707
3708 I915_WRITE16(IER,
3709 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3710 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3711 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3712 I915_USER_INTERRUPT);
3713 POSTING_READ16(IER);
3714
3715 /* Interrupt setup is already guaranteed to be single-threaded, this is
3716 * just to make the assert_spin_locked check happy. */
3717 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3718 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3719 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3720 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3721
3722 return 0;
3723 }
3724
3725 /*
3726 * Returns true when a page flip has completed.
3727 */
3728 static bool i8xx_handle_vblank(struct drm_device *dev,
3729 int plane, int pipe, u32 iir)
3730 {
3731 struct drm_i915_private *dev_priv = dev->dev_private;
3732 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3733
3734 if (!intel_pipe_handle_vblank(dev, pipe))
3735 return false;
3736
3737 if ((iir & flip_pending) == 0)
3738 return false;
3739
3740 intel_prepare_page_flip(dev, plane);
3741
3742 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3743 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3744 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3745 * the flip is completed (no longer pending). Since this doesn't raise
3746 * an interrupt per se, we watch for the change at vblank.
3747 */
3748 if (I915_READ16(ISR) & flip_pending)
3749 return false;
3750
3751 intel_finish_page_flip(dev, pipe);
3752
3753 return true;
3754 }
3755
3756 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3757 {
3758 struct drm_device *dev = arg;
3759 struct drm_i915_private *dev_priv = dev->dev_private;
3760 u16 iir, new_iir;
3761 u32 pipe_stats[2];
3762 unsigned long irqflags;
3763 int pipe;
3764 u16 flip_mask =
3765 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3766 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3767
3768 iir = I915_READ16(IIR);
3769 if (iir == 0)
3770 return IRQ_NONE;
3771
3772 while (iir & ~flip_mask) {
3773 /* Can't rely on pipestat interrupt bit in iir as it might
3774 * have been cleared after the pipestat interrupt was received.
3775 * It doesn't set the bit in iir again, but it still produces
3776 * interrupts (for non-MSI).
3777 */
3778 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3779 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3780 i915_handle_error(dev, false,
3781 "Command parser error, iir 0x%08x",
3782 iir);
3783
3784 for_each_pipe(pipe) {
3785 int reg = PIPESTAT(pipe);
3786 pipe_stats[pipe] = I915_READ(reg);
3787
3788 /*
3789 * Clear the PIPE*STAT regs before the IIR
3790 */
3791 if (pipe_stats[pipe] & 0x8000ffff)
3792 I915_WRITE(reg, pipe_stats[pipe]);
3793 }
3794 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3795
3796 I915_WRITE16(IIR, iir & ~flip_mask);
3797 new_iir = I915_READ16(IIR); /* Flush posted writes */
3798
3799 i915_update_dri1_breadcrumb(dev);
3800
3801 if (iir & I915_USER_INTERRUPT)
3802 notify_ring(dev, &dev_priv->ring[RCS]);
3803
3804 for_each_pipe(pipe) {
3805 int plane = pipe;
3806 if (HAS_FBC(dev))
3807 plane = !plane;
3808
3809 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3810 i8xx_handle_vblank(dev, plane, pipe, iir))
3811 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3812
3813 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3814 i9xx_pipe_crc_irq_handler(dev, pipe);
3815
3816 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3817 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3818 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3819 }
3820
3821 iir = new_iir;
3822 }
3823
3824 return IRQ_HANDLED;
3825 }
3826
3827 static void i8xx_irq_uninstall(struct drm_device * dev)
3828 {
3829 struct drm_i915_private *dev_priv = dev->dev_private;
3830 int pipe;
3831
3832 for_each_pipe(pipe) {
3833 /* Clear enable bits; then clear status bits */
3834 I915_WRITE(PIPESTAT(pipe), 0);
3835 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3836 }
3837 I915_WRITE16(IMR, 0xffff);
3838 I915_WRITE16(IER, 0x0);
3839 I915_WRITE16(IIR, I915_READ16(IIR));
3840 }
3841
3842 static void i915_irq_preinstall(struct drm_device * dev)
3843 {
3844 struct drm_i915_private *dev_priv = dev->dev_private;
3845 int pipe;
3846
3847 if (I915_HAS_HOTPLUG(dev)) {
3848 I915_WRITE(PORT_HOTPLUG_EN, 0);
3849 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3850 }
3851
3852 I915_WRITE16(HWSTAM, 0xeffe);
3853 for_each_pipe(pipe)
3854 I915_WRITE(PIPESTAT(pipe), 0);
3855 I915_WRITE(IMR, 0xffffffff);
3856 I915_WRITE(IER, 0x0);
3857 POSTING_READ(IER);
3858 }
3859
3860 static int i915_irq_postinstall(struct drm_device *dev)
3861 {
3862 struct drm_i915_private *dev_priv = dev->dev_private;
3863 u32 enable_mask;
3864 unsigned long irqflags;
3865
3866 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3867
3868 /* Unmask the interrupts that we always want on. */
3869 dev_priv->irq_mask =
3870 ~(I915_ASLE_INTERRUPT |
3871 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3872 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3873 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3874 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3875 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3876
3877 enable_mask =
3878 I915_ASLE_INTERRUPT |
3879 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3880 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3881 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3882 I915_USER_INTERRUPT;
3883
3884 if (I915_HAS_HOTPLUG(dev)) {
3885 I915_WRITE(PORT_HOTPLUG_EN, 0);
3886 POSTING_READ(PORT_HOTPLUG_EN);
3887
3888 /* Enable in IER... */
3889 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3890 /* and unmask in IMR */
3891 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3892 }
3893
3894 I915_WRITE(IMR, dev_priv->irq_mask);
3895 I915_WRITE(IER, enable_mask);
3896 POSTING_READ(IER);
3897
3898 i915_enable_asle_pipestat(dev);
3899
3900 /* Interrupt setup is already guaranteed to be single-threaded, this is
3901 * just to make the assert_spin_locked check happy. */
3902 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3903 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3904 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3905 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3906
3907 return 0;
3908 }
3909
3910 /*
3911 * Returns true when a page flip has completed.
3912 */
3913 static bool i915_handle_vblank(struct drm_device *dev,
3914 int plane, int pipe, u32 iir)
3915 {
3916 struct drm_i915_private *dev_priv = dev->dev_private;
3917 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3918
3919 if (!intel_pipe_handle_vblank(dev, pipe))
3920 return false;
3921
3922 if ((iir & flip_pending) == 0)
3923 return false;
3924
3925 intel_prepare_page_flip(dev, plane);
3926
3927 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3928 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3929 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3930 * the flip is completed (no longer pending). Since this doesn't raise
3931 * an interrupt per se, we watch for the change at vblank.
3932 */
3933 if (I915_READ(ISR) & flip_pending)
3934 return false;
3935
3936 intel_finish_page_flip(dev, pipe);
3937
3938 return true;
3939 }
3940
3941 static irqreturn_t i915_irq_handler(int irq, void *arg)
3942 {
3943 struct drm_device *dev = arg;
3944 struct drm_i915_private *dev_priv = dev->dev_private;
3945 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3946 unsigned long irqflags;
3947 u32 flip_mask =
3948 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3949 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3950 int pipe, ret = IRQ_NONE;
3951
3952 iir = I915_READ(IIR);
3953 do {
3954 bool irq_received = (iir & ~flip_mask) != 0;
3955 bool blc_event = false;
3956
3957 /* Can't rely on pipestat interrupt bit in iir as it might
3958 * have been cleared after the pipestat interrupt was received.
3959 * It doesn't set the bit in iir again, but it still produces
3960 * interrupts (for non-MSI).
3961 */
3962 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3963 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3964 i915_handle_error(dev, false,
3965 "Command parser error, iir 0x%08x",
3966 iir);
3967
3968 for_each_pipe(pipe) {
3969 int reg = PIPESTAT(pipe);
3970 pipe_stats[pipe] = I915_READ(reg);
3971
3972 /* Clear the PIPE*STAT regs before the IIR */
3973 if (pipe_stats[pipe] & 0x8000ffff) {
3974 I915_WRITE(reg, pipe_stats[pipe]);
3975 irq_received = true;
3976 }
3977 }
3978 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3979
3980 if (!irq_received)
3981 break;
3982
3983 /* Consume port. Then clear IIR or we'll miss events */
3984 if (I915_HAS_HOTPLUG(dev) &&
3985 iir & I915_DISPLAY_PORT_INTERRUPT)
3986 i9xx_hpd_irq_handler(dev);
3987
3988 I915_WRITE(IIR, iir & ~flip_mask);
3989 new_iir = I915_READ(IIR); /* Flush posted writes */
3990
3991 if (iir & I915_USER_INTERRUPT)
3992 notify_ring(dev, &dev_priv->ring[RCS]);
3993
3994 for_each_pipe(pipe) {
3995 int plane = pipe;
3996 if (HAS_FBC(dev))
3997 plane = !plane;
3998
3999 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4000 i915_handle_vblank(dev, plane, pipe, iir))
4001 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4002
4003 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4004 blc_event = true;
4005
4006 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4007 i9xx_pipe_crc_irq_handler(dev, pipe);
4008
4009 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
4010 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
4011 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
4012 }
4013
4014 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4015 intel_opregion_asle_intr(dev);
4016
4017 /* With MSI, interrupts are only generated when iir
4018 * transitions from zero to nonzero. If another bit got
4019 * set while we were handling the existing iir bits, then
4020 * we would never get another interrupt.
4021 *
4022 * This is fine on non-MSI as well, as if we hit this path
4023 * we avoid exiting the interrupt handler only to generate
4024 * another one.
4025 *
4026 * Note that for MSI this could cause a stray interrupt report
4027 * if an interrupt landed in the time between writing IIR and
4028 * the posting read. This should be rare enough to never
4029 * trigger the 99% of 100,000 interrupts test for disabling
4030 * stray interrupts.
4031 */
4032 ret = IRQ_HANDLED;
4033 iir = new_iir;
4034 } while (iir & ~flip_mask);
4035
4036 i915_update_dri1_breadcrumb(dev);
4037
4038 return ret;
4039 }
4040
4041 static void i915_irq_uninstall(struct drm_device * dev)
4042 {
4043 struct drm_i915_private *dev_priv = dev->dev_private;
4044 int pipe;
4045
4046 intel_hpd_irq_uninstall(dev_priv);
4047
4048 if (I915_HAS_HOTPLUG(dev)) {
4049 I915_WRITE(PORT_HOTPLUG_EN, 0);
4050 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4051 }
4052
4053 I915_WRITE16(HWSTAM, 0xffff);
4054 for_each_pipe(pipe) {
4055 /* Clear enable bits; then clear status bits */
4056 I915_WRITE(PIPESTAT(pipe), 0);
4057 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4058 }
4059 I915_WRITE(IMR, 0xffffffff);
4060 I915_WRITE(IER, 0x0);
4061
4062 I915_WRITE(IIR, I915_READ(IIR));
4063 }
4064
4065 static void i965_irq_preinstall(struct drm_device * dev)
4066 {
4067 struct drm_i915_private *dev_priv = dev->dev_private;
4068 int pipe;
4069
4070 I915_WRITE(PORT_HOTPLUG_EN, 0);
4071 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4072
4073 I915_WRITE(HWSTAM, 0xeffe);
4074 for_each_pipe(pipe)
4075 I915_WRITE(PIPESTAT(pipe), 0);
4076 I915_WRITE(IMR, 0xffffffff);
4077 I915_WRITE(IER, 0x0);
4078 POSTING_READ(IER);
4079 }
4080
4081 static int i965_irq_postinstall(struct drm_device *dev)
4082 {
4083 struct drm_i915_private *dev_priv = dev->dev_private;
4084 u32 enable_mask;
4085 u32 error_mask;
4086 unsigned long irqflags;
4087
4088 /* Unmask the interrupts that we always want on. */
4089 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4090 I915_DISPLAY_PORT_INTERRUPT |
4091 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4092 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4093 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4094 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4095 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4096
4097 enable_mask = ~dev_priv->irq_mask;
4098 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4099 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4100 enable_mask |= I915_USER_INTERRUPT;
4101
4102 if (IS_G4X(dev))
4103 enable_mask |= I915_BSD_USER_INTERRUPT;
4104
4105 /* Interrupt setup is already guaranteed to be single-threaded, this is
4106 * just to make the assert_spin_locked check happy. */
4107 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4108 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4109 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4110 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4111 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4112
4113 /*
4114 * Enable some error detection, note the instruction error mask
4115 * bit is reserved, so we leave it masked.
4116 */
4117 if (IS_G4X(dev)) {
4118 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4119 GM45_ERROR_MEM_PRIV |
4120 GM45_ERROR_CP_PRIV |
4121 I915_ERROR_MEMORY_REFRESH);
4122 } else {
4123 error_mask = ~(I915_ERROR_PAGE_TABLE |
4124 I915_ERROR_MEMORY_REFRESH);
4125 }
4126 I915_WRITE(EMR, error_mask);
4127
4128 I915_WRITE(IMR, dev_priv->irq_mask);
4129 I915_WRITE(IER, enable_mask);
4130 POSTING_READ(IER);
4131
4132 I915_WRITE(PORT_HOTPLUG_EN, 0);
4133 POSTING_READ(PORT_HOTPLUG_EN);
4134
4135 i915_enable_asle_pipestat(dev);
4136
4137 return 0;
4138 }
4139
4140 static void i915_hpd_irq_setup(struct drm_device *dev)
4141 {
4142 struct drm_i915_private *dev_priv = dev->dev_private;
4143 struct drm_mode_config *mode_config = &dev->mode_config;
4144 struct intel_encoder *intel_encoder;
4145 u32 hotplug_en;
4146
4147 assert_spin_locked(&dev_priv->irq_lock);
4148
4149 if (I915_HAS_HOTPLUG(dev)) {
4150 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
4151 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
4152 /* Note HDMI and DP share hotplug bits */
4153 /* enable bits are the same for all generations */
4154 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
4155 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
4156 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
4157 /* Programming the CRT detection parameters tends
4158 to generate a spurious hotplug event about three
4159 seconds later. So just do it once.
4160 */
4161 if (IS_G4X(dev))
4162 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4163 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
4164 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4165
4166 /* Ignore TV since it's buggy */
4167 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
4168 }
4169 }
4170
4171 static irqreturn_t i965_irq_handler(int irq, void *arg)
4172 {
4173 struct drm_device *dev = arg;
4174 struct drm_i915_private *dev_priv = dev->dev_private;
4175 u32 iir, new_iir;
4176 u32 pipe_stats[I915_MAX_PIPES];
4177 unsigned long irqflags;
4178 int ret = IRQ_NONE, pipe;
4179 u32 flip_mask =
4180 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4181 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4182
4183 iir = I915_READ(IIR);
4184
4185 for (;;) {
4186 bool irq_received = (iir & ~flip_mask) != 0;
4187 bool blc_event = false;
4188
4189 /* Can't rely on pipestat interrupt bit in iir as it might
4190 * have been cleared after the pipestat interrupt was received.
4191 * It doesn't set the bit in iir again, but it still produces
4192 * interrupts (for non-MSI).
4193 */
4194 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4195 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4196 i915_handle_error(dev, false,
4197 "Command parser error, iir 0x%08x",
4198 iir);
4199
4200 for_each_pipe(pipe) {
4201 int reg = PIPESTAT(pipe);
4202 pipe_stats[pipe] = I915_READ(reg);
4203
4204 /*
4205 * Clear the PIPE*STAT regs before the IIR
4206 */
4207 if (pipe_stats[pipe] & 0x8000ffff) {
4208 I915_WRITE(reg, pipe_stats[pipe]);
4209 irq_received = true;
4210 }
4211 }
4212 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4213
4214 if (!irq_received)
4215 break;
4216
4217 ret = IRQ_HANDLED;
4218
4219 /* Consume port. Then clear IIR or we'll miss events */
4220 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4221 i9xx_hpd_irq_handler(dev);
4222
4223 I915_WRITE(IIR, iir & ~flip_mask);
4224 new_iir = I915_READ(IIR); /* Flush posted writes */
4225
4226 if (iir & I915_USER_INTERRUPT)
4227 notify_ring(dev, &dev_priv->ring[RCS]);
4228 if (iir & I915_BSD_USER_INTERRUPT)
4229 notify_ring(dev, &dev_priv->ring[VCS]);
4230
4231 for_each_pipe(pipe) {
4232 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4233 i915_handle_vblank(dev, pipe, pipe, iir))
4234 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4235
4236 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4237 blc_event = true;
4238
4239 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4240 i9xx_pipe_crc_irq_handler(dev, pipe);
4241
4242 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
4243 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
4244 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
4245 }
4246
4247 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4248 intel_opregion_asle_intr(dev);
4249
4250 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4251 gmbus_irq_handler(dev);
4252
4253 /* With MSI, interrupts are only generated when iir
4254 * transitions from zero to nonzero. If another bit got
4255 * set while we were handling the existing iir bits, then
4256 * we would never get another interrupt.
4257 *
4258 * This is fine on non-MSI as well, as if we hit this path
4259 * we avoid exiting the interrupt handler only to generate
4260 * another one.
4261 *
4262 * Note that for MSI this could cause a stray interrupt report
4263 * if an interrupt landed in the time between writing IIR and
4264 * the posting read. This should be rare enough to never
4265 * trigger the 99% of 100,000 interrupts test for disabling
4266 * stray interrupts.
4267 */
4268 iir = new_iir;
4269 }
4270
4271 i915_update_dri1_breadcrumb(dev);
4272
4273 return ret;
4274 }
4275
4276 static void i965_irq_uninstall(struct drm_device * dev)
4277 {
4278 struct drm_i915_private *dev_priv = dev->dev_private;
4279 int pipe;
4280
4281 if (!dev_priv)
4282 return;
4283
4284 intel_hpd_irq_uninstall(dev_priv);
4285
4286 I915_WRITE(PORT_HOTPLUG_EN, 0);
4287 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4288
4289 I915_WRITE(HWSTAM, 0xffffffff);
4290 for_each_pipe(pipe)
4291 I915_WRITE(PIPESTAT(pipe), 0);
4292 I915_WRITE(IMR, 0xffffffff);
4293 I915_WRITE(IER, 0x0);
4294
4295 for_each_pipe(pipe)
4296 I915_WRITE(PIPESTAT(pipe),
4297 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4298 I915_WRITE(IIR, I915_READ(IIR));
4299 }
4300
4301 static void intel_hpd_irq_reenable(unsigned long data)
4302 {
4303 struct drm_i915_private *dev_priv = (struct drm_i915_private *)data;
4304 struct drm_device *dev = dev_priv->dev;
4305 struct drm_mode_config *mode_config = &dev->mode_config;
4306 unsigned long irqflags;
4307 int i;
4308
4309 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4310 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
4311 struct drm_connector *connector;
4312
4313 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
4314 continue;
4315
4316 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4317
4318 list_for_each_entry(connector, &mode_config->connector_list, head) {
4319 struct intel_connector *intel_connector = to_intel_connector(connector);
4320
4321 if (intel_connector->encoder->hpd_pin == i) {
4322 if (connector->polled != intel_connector->polled)
4323 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
4324 drm_get_connector_name(connector));
4325 connector->polled = intel_connector->polled;
4326 if (!connector->polled)
4327 connector->polled = DRM_CONNECTOR_POLL_HPD;
4328 }
4329 }
4330 }
4331 if (dev_priv->display.hpd_irq_setup)
4332 dev_priv->display.hpd_irq_setup(dev);
4333 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4334 }
4335
4336 void intel_irq_init(struct drm_device *dev)
4337 {
4338 struct drm_i915_private *dev_priv = dev->dev_private;
4339
4340 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
4341 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
4342 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4343 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4344
4345 /* Let's track the enabled rps events */
4346 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4347
4348 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
4349 i915_hangcheck_elapsed,
4350 (unsigned long) dev);
4351 setup_timer(&dev_priv->hotplug_reenable_timer, intel_hpd_irq_reenable,
4352 (unsigned long) dev_priv);
4353
4354 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4355
4356 if (IS_GEN2(dev)) {
4357 dev->max_vblank_count = 0;
4358 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4359 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
4360 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4361 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
4362 } else {
4363 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4364 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4365 }
4366
4367 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
4368 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4369 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4370 }
4371
4372 if (IS_CHERRYVIEW(dev)) {
4373 dev->driver->irq_handler = cherryview_irq_handler;
4374 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4375 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4376 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4377 dev->driver->enable_vblank = valleyview_enable_vblank;
4378 dev->driver->disable_vblank = valleyview_disable_vblank;
4379 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4380 } else if (IS_VALLEYVIEW(dev)) {
4381 dev->driver->irq_handler = valleyview_irq_handler;
4382 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4383 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4384 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4385 dev->driver->enable_vblank = valleyview_enable_vblank;
4386 dev->driver->disable_vblank = valleyview_disable_vblank;
4387 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4388 } else if (IS_GEN8(dev)) {
4389 dev->driver->irq_handler = gen8_irq_handler;
4390 dev->driver->irq_preinstall = gen8_irq_preinstall;
4391 dev->driver->irq_postinstall = gen8_irq_postinstall;
4392 dev->driver->irq_uninstall = gen8_irq_uninstall;
4393 dev->driver->enable_vblank = gen8_enable_vblank;
4394 dev->driver->disable_vblank = gen8_disable_vblank;
4395 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4396 } else if (HAS_PCH_SPLIT(dev)) {
4397 dev->driver->irq_handler = ironlake_irq_handler;
4398 dev->driver->irq_preinstall = ironlake_irq_preinstall;
4399 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4400 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4401 dev->driver->enable_vblank = ironlake_enable_vblank;
4402 dev->driver->disable_vblank = ironlake_disable_vblank;
4403 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4404 } else {
4405 if (INTEL_INFO(dev)->gen == 2) {
4406 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4407 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4408 dev->driver->irq_handler = i8xx_irq_handler;
4409 dev->driver->irq_uninstall = i8xx_irq_uninstall;
4410 } else if (INTEL_INFO(dev)->gen == 3) {
4411 dev->driver->irq_preinstall = i915_irq_preinstall;
4412 dev->driver->irq_postinstall = i915_irq_postinstall;
4413 dev->driver->irq_uninstall = i915_irq_uninstall;
4414 dev->driver->irq_handler = i915_irq_handler;
4415 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4416 } else {
4417 dev->driver->irq_preinstall = i965_irq_preinstall;
4418 dev->driver->irq_postinstall = i965_irq_postinstall;
4419 dev->driver->irq_uninstall = i965_irq_uninstall;
4420 dev->driver->irq_handler = i965_irq_handler;
4421 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4422 }
4423 dev->driver->enable_vblank = i915_enable_vblank;
4424 dev->driver->disable_vblank = i915_disable_vblank;
4425 }
4426 }
4427
4428 void intel_hpd_init(struct drm_device *dev)
4429 {
4430 struct drm_i915_private *dev_priv = dev->dev_private;
4431 struct drm_mode_config *mode_config = &dev->mode_config;
4432 struct drm_connector *connector;
4433 unsigned long irqflags;
4434 int i;
4435
4436 for (i = 1; i < HPD_NUM_PINS; i++) {
4437 dev_priv->hpd_stats[i].hpd_cnt = 0;
4438 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4439 }
4440 list_for_each_entry(connector, &mode_config->connector_list, head) {
4441 struct intel_connector *intel_connector = to_intel_connector(connector);
4442 connector->polled = intel_connector->polled;
4443 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
4444 connector->polled = DRM_CONNECTOR_POLL_HPD;
4445 }
4446
4447 /* Interrupt setup is already guaranteed to be single-threaded, this is
4448 * just to make the assert_spin_locked checks happy. */
4449 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4450 if (dev_priv->display.hpd_irq_setup)
4451 dev_priv->display.hpd_irq_setup(dev);
4452 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4453 }
4454
4455 /* Disable interrupts so we can allow runtime PM. */
4456 void intel_runtime_pm_disable_interrupts(struct drm_device *dev)
4457 {
4458 struct drm_i915_private *dev_priv = dev->dev_private;
4459
4460 dev->driver->irq_uninstall(dev);
4461 dev_priv->pm.irqs_disabled = true;
4462 }
4463
4464 /* Restore interrupts so we can recover from runtime PM. */
4465 void intel_runtime_pm_restore_interrupts(struct drm_device *dev)
4466 {
4467 struct drm_i915_private *dev_priv = dev->dev_private;
4468
4469 dev_priv->pm.irqs_disabled = false;
4470 dev->driver->irq_preinstall(dev);
4471 dev->driver->irq_postinstall(dev);
4472 }
Linux kernel - Deliverables
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