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drm/i915: WARN if we receive any rps interrupts on gen>9
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
34 #include <drm/drmP.h>
35 #include <drm/i915_drm.h>
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "intel_drv.h"
39
40 /**
41 * DOC: interrupt handling
42 *
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
46 */
47
48 static const u32 hpd_ibx[] = {
49 [HPD_CRT] = SDE_CRT_HOTPLUG,
50 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
51 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
52 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
53 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
54 };
55
56 static const u32 hpd_cpt[] = {
57 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
58 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
59 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
60 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
61 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
62 };
63
64 static const u32 hpd_mask_i915[] = {
65 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
66 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
67 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
68 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
69 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
70 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
71 };
72
73 static const u32 hpd_status_g4x[] = {
74 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
75 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
76 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
77 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
78 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
79 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
80 };
81
82 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
83 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
84 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
85 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
86 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
87 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
88 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
89 };
90
91 /* IIR can theoretically queue up two events. Be paranoid. */
92 #define GEN8_IRQ_RESET_NDX(type, which) do { \
93 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
94 POSTING_READ(GEN8_##type##_IMR(which)); \
95 I915_WRITE(GEN8_##type##_IER(which), 0); \
96 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
97 POSTING_READ(GEN8_##type##_IIR(which)); \
98 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
99 POSTING_READ(GEN8_##type##_IIR(which)); \
100 } while (0)
101
102 #define GEN5_IRQ_RESET(type) do { \
103 I915_WRITE(type##IMR, 0xffffffff); \
104 POSTING_READ(type##IMR); \
105 I915_WRITE(type##IER, 0); \
106 I915_WRITE(type##IIR, 0xffffffff); \
107 POSTING_READ(type##IIR); \
108 I915_WRITE(type##IIR, 0xffffffff); \
109 POSTING_READ(type##IIR); \
110 } while (0)
111
112 /*
113 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
114 */
115 #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
116 u32 val = I915_READ(reg); \
117 if (val) { \
118 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
119 (reg), val); \
120 I915_WRITE((reg), 0xffffffff); \
121 POSTING_READ(reg); \
122 I915_WRITE((reg), 0xffffffff); \
123 POSTING_READ(reg); \
124 } \
125 } while (0)
126
127 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
128 GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
129 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
130 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
131 POSTING_READ(GEN8_##type##_IMR(which)); \
132 } while (0)
133
134 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
135 GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
136 I915_WRITE(type##IER, (ier_val)); \
137 I915_WRITE(type##IMR, (imr_val)); \
138 POSTING_READ(type##IMR); \
139 } while (0)
140
141 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
142
143 /* For display hotplug interrupt */
144 void
145 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
146 {
147 assert_spin_locked(&dev_priv->irq_lock);
148
149 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
150 return;
151
152 if ((dev_priv->irq_mask & mask) != 0) {
153 dev_priv->irq_mask &= ~mask;
154 I915_WRITE(DEIMR, dev_priv->irq_mask);
155 POSTING_READ(DEIMR);
156 }
157 }
158
159 void
160 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
161 {
162 assert_spin_locked(&dev_priv->irq_lock);
163
164 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
165 return;
166
167 if ((dev_priv->irq_mask & mask) != mask) {
168 dev_priv->irq_mask |= mask;
169 I915_WRITE(DEIMR, dev_priv->irq_mask);
170 POSTING_READ(DEIMR);
171 }
172 }
173
174 /**
175 * ilk_update_gt_irq - update GTIMR
176 * @dev_priv: driver private
177 * @interrupt_mask: mask of interrupt bits to update
178 * @enabled_irq_mask: mask of interrupt bits to enable
179 */
180 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
181 uint32_t interrupt_mask,
182 uint32_t enabled_irq_mask)
183 {
184 assert_spin_locked(&dev_priv->irq_lock);
185
186 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
187 return;
188
189 dev_priv->gt_irq_mask &= ~interrupt_mask;
190 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
191 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
192 POSTING_READ(GTIMR);
193 }
194
195 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
196 {
197 ilk_update_gt_irq(dev_priv, mask, mask);
198 }
199
200 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
201 {
202 ilk_update_gt_irq(dev_priv, mask, 0);
203 }
204
205 static u32 gen6_pm_iir(struct drm_i915_private *dev_priv)
206 {
207 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
208 }
209
210 static u32 gen6_pm_imr(struct drm_i915_private *dev_priv)
211 {
212 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
213 }
214
215 static u32 gen6_pm_ier(struct drm_i915_private *dev_priv)
216 {
217 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
218 }
219
220 /**
221 * snb_update_pm_irq - update GEN6_PMIMR
222 * @dev_priv: driver private
223 * @interrupt_mask: mask of interrupt bits to update
224 * @enabled_irq_mask: mask of interrupt bits to enable
225 */
226 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
227 uint32_t interrupt_mask,
228 uint32_t enabled_irq_mask)
229 {
230 uint32_t new_val;
231
232 assert_spin_locked(&dev_priv->irq_lock);
233
234 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
235 return;
236
237 new_val = dev_priv->pm_irq_mask;
238 new_val &= ~interrupt_mask;
239 new_val |= (~enabled_irq_mask & interrupt_mask);
240
241 if (new_val != dev_priv->pm_irq_mask) {
242 dev_priv->pm_irq_mask = new_val;
243 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
244 POSTING_READ(gen6_pm_imr(dev_priv));
245 }
246 }
247
248 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
249 {
250 snb_update_pm_irq(dev_priv, mask, mask);
251 }
252
253 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
254 {
255 snb_update_pm_irq(dev_priv, mask, 0);
256 }
257
258 void gen6_enable_rps_interrupts(struct drm_device *dev)
259 {
260 struct drm_i915_private *dev_priv = dev->dev_private;
261
262 spin_lock_irq(&dev_priv->irq_lock);
263 WARN_ON(dev_priv->rps.pm_iir);
264 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
265 I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events);
266 spin_unlock_irq(&dev_priv->irq_lock);
267 }
268
269 void gen6_disable_rps_interrupts(struct drm_device *dev)
270 {
271 struct drm_i915_private *dev_priv = dev->dev_private;
272
273 I915_WRITE(GEN6_PMINTRMSK, INTEL_INFO(dev_priv)->gen >= 8 ?
274 ~GEN8_PMINTR_REDIRECT_TO_NON_DISP : ~0);
275 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
276 ~dev_priv->pm_rps_events);
277 /* Complete PM interrupt masking here doesn't race with the rps work
278 * item again unmasking PM interrupts because that is using a different
279 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
280 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
281
282 spin_lock_irq(&dev_priv->irq_lock);
283 dev_priv->rps.pm_iir = 0;
284 spin_unlock_irq(&dev_priv->irq_lock);
285
286 I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events);
287 }
288
289 /**
290 * ibx_display_interrupt_update - update SDEIMR
291 * @dev_priv: driver private
292 * @interrupt_mask: mask of interrupt bits to update
293 * @enabled_irq_mask: mask of interrupt bits to enable
294 */
295 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
296 uint32_t interrupt_mask,
297 uint32_t enabled_irq_mask)
298 {
299 uint32_t sdeimr = I915_READ(SDEIMR);
300 sdeimr &= ~interrupt_mask;
301 sdeimr |= (~enabled_irq_mask & interrupt_mask);
302
303 assert_spin_locked(&dev_priv->irq_lock);
304
305 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
306 return;
307
308 I915_WRITE(SDEIMR, sdeimr);
309 POSTING_READ(SDEIMR);
310 }
311
312 static void
313 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
314 u32 enable_mask, u32 status_mask)
315 {
316 u32 reg = PIPESTAT(pipe);
317 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
318
319 assert_spin_locked(&dev_priv->irq_lock);
320 WARN_ON(!intel_irqs_enabled(dev_priv));
321
322 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
323 status_mask & ~PIPESTAT_INT_STATUS_MASK,
324 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
325 pipe_name(pipe), enable_mask, status_mask))
326 return;
327
328 if ((pipestat & enable_mask) == enable_mask)
329 return;
330
331 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
332
333 /* Enable the interrupt, clear any pending status */
334 pipestat |= enable_mask | status_mask;
335 I915_WRITE(reg, pipestat);
336 POSTING_READ(reg);
337 }
338
339 static void
340 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
341 u32 enable_mask, u32 status_mask)
342 {
343 u32 reg = PIPESTAT(pipe);
344 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
345
346 assert_spin_locked(&dev_priv->irq_lock);
347 WARN_ON(!intel_irqs_enabled(dev_priv));
348
349 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
350 status_mask & ~PIPESTAT_INT_STATUS_MASK,
351 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
352 pipe_name(pipe), enable_mask, status_mask))
353 return;
354
355 if ((pipestat & enable_mask) == 0)
356 return;
357
358 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
359
360 pipestat &= ~enable_mask;
361 I915_WRITE(reg, pipestat);
362 POSTING_READ(reg);
363 }
364
365 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
366 {
367 u32 enable_mask = status_mask << 16;
368
369 /*
370 * On pipe A we don't support the PSR interrupt yet,
371 * on pipe B and C the same bit MBZ.
372 */
373 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
374 return 0;
375 /*
376 * On pipe B and C we don't support the PSR interrupt yet, on pipe
377 * A the same bit is for perf counters which we don't use either.
378 */
379 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
380 return 0;
381
382 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
383 SPRITE0_FLIP_DONE_INT_EN_VLV |
384 SPRITE1_FLIP_DONE_INT_EN_VLV);
385 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
386 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
387 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
388 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
389
390 return enable_mask;
391 }
392
393 void
394 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
395 u32 status_mask)
396 {
397 u32 enable_mask;
398
399 if (IS_VALLEYVIEW(dev_priv->dev))
400 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
401 status_mask);
402 else
403 enable_mask = status_mask << 16;
404 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
405 }
406
407 void
408 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
409 u32 status_mask)
410 {
411 u32 enable_mask;
412
413 if (IS_VALLEYVIEW(dev_priv->dev))
414 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
415 status_mask);
416 else
417 enable_mask = status_mask << 16;
418 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
419 }
420
421 /**
422 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
423 */
424 static void i915_enable_asle_pipestat(struct drm_device *dev)
425 {
426 struct drm_i915_private *dev_priv = dev->dev_private;
427
428 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
429 return;
430
431 spin_lock_irq(&dev_priv->irq_lock);
432
433 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
434 if (INTEL_INFO(dev)->gen >= 4)
435 i915_enable_pipestat(dev_priv, PIPE_A,
436 PIPE_LEGACY_BLC_EVENT_STATUS);
437
438 spin_unlock_irq(&dev_priv->irq_lock);
439 }
440
441 /**
442 * i915_pipe_enabled - check if a pipe is enabled
443 * @dev: DRM device
444 * @pipe: pipe to check
445 *
446 * Reading certain registers when the pipe is disabled can hang the chip.
447 * Use this routine to make sure the PLL is running and the pipe is active
448 * before reading such registers if unsure.
449 */
450 static int
451 i915_pipe_enabled(struct drm_device *dev, int pipe)
452 {
453 struct drm_i915_private *dev_priv = dev->dev_private;
454
455 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
456 /* Locking is horribly broken here, but whatever. */
457 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
458 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
459
460 return intel_crtc->active;
461 } else {
462 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
463 }
464 }
465
466 /*
467 * This timing diagram depicts the video signal in and
468 * around the vertical blanking period.
469 *
470 * Assumptions about the fictitious mode used in this example:
471 * vblank_start >= 3
472 * vsync_start = vblank_start + 1
473 * vsync_end = vblank_start + 2
474 * vtotal = vblank_start + 3
475 *
476 * start of vblank:
477 * latch double buffered registers
478 * increment frame counter (ctg+)
479 * generate start of vblank interrupt (gen4+)
480 * |
481 * | frame start:
482 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
483 * | may be shifted forward 1-3 extra lines via PIPECONF
484 * | |
485 * | | start of vsync:
486 * | | generate vsync interrupt
487 * | | |
488 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
489 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
490 * ----va---> <-----------------vb--------------------> <--------va-------------
491 * | | <----vs-----> |
492 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
493 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
494 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
495 * | | |
496 * last visible pixel first visible pixel
497 * | increment frame counter (gen3/4)
498 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
499 *
500 * x = horizontal active
501 * _ = horizontal blanking
502 * hs = horizontal sync
503 * va = vertical active
504 * vb = vertical blanking
505 * vs = vertical sync
506 * vbs = vblank_start (number)
507 *
508 * Summary:
509 * - most events happen at the start of horizontal sync
510 * - frame start happens at the start of horizontal blank, 1-4 lines
511 * (depending on PIPECONF settings) after the start of vblank
512 * - gen3/4 pixel and frame counter are synchronized with the start
513 * of horizontal active on the first line of vertical active
514 */
515
516 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
517 {
518 /* Gen2 doesn't have a hardware frame counter */
519 return 0;
520 }
521
522 /* Called from drm generic code, passed a 'crtc', which
523 * we use as a pipe index
524 */
525 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
526 {
527 struct drm_i915_private *dev_priv = dev->dev_private;
528 unsigned long high_frame;
529 unsigned long low_frame;
530 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
531
532 if (!i915_pipe_enabled(dev, pipe)) {
533 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
534 "pipe %c\n", pipe_name(pipe));
535 return 0;
536 }
537
538 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
539 struct intel_crtc *intel_crtc =
540 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
541 const struct drm_display_mode *mode =
542 &intel_crtc->config.adjusted_mode;
543
544 htotal = mode->crtc_htotal;
545 hsync_start = mode->crtc_hsync_start;
546 vbl_start = mode->crtc_vblank_start;
547 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
548 vbl_start = DIV_ROUND_UP(vbl_start, 2);
549 } else {
550 enum transcoder cpu_transcoder = (enum transcoder) pipe;
551
552 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
553 hsync_start = (I915_READ(HSYNC(cpu_transcoder)) & 0x1fff) + 1;
554 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
555 if ((I915_READ(PIPECONF(cpu_transcoder)) &
556 PIPECONF_INTERLACE_MASK) != PIPECONF_PROGRESSIVE)
557 vbl_start = DIV_ROUND_UP(vbl_start, 2);
558 }
559
560 /* Convert to pixel count */
561 vbl_start *= htotal;
562
563 /* Start of vblank event occurs at start of hsync */
564 vbl_start -= htotal - hsync_start;
565
566 high_frame = PIPEFRAME(pipe);
567 low_frame = PIPEFRAMEPIXEL(pipe);
568
569 /*
570 * High & low register fields aren't synchronized, so make sure
571 * we get a low value that's stable across two reads of the high
572 * register.
573 */
574 do {
575 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
576 low = I915_READ(low_frame);
577 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
578 } while (high1 != high2);
579
580 high1 >>= PIPE_FRAME_HIGH_SHIFT;
581 pixel = low & PIPE_PIXEL_MASK;
582 low >>= PIPE_FRAME_LOW_SHIFT;
583
584 /*
585 * The frame counter increments at beginning of active.
586 * Cook up a vblank counter by also checking the pixel
587 * counter against vblank start.
588 */
589 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
590 }
591
592 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
593 {
594 struct drm_i915_private *dev_priv = dev->dev_private;
595 int reg = PIPE_FRMCOUNT_GM45(pipe);
596
597 if (!i915_pipe_enabled(dev, pipe)) {
598 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
599 "pipe %c\n", pipe_name(pipe));
600 return 0;
601 }
602
603 return I915_READ(reg);
604 }
605
606 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
607 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
608
609 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
610 {
611 struct drm_device *dev = crtc->base.dev;
612 struct drm_i915_private *dev_priv = dev->dev_private;
613 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
614 enum pipe pipe = crtc->pipe;
615 int position, vtotal;
616
617 vtotal = mode->crtc_vtotal;
618 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
619 vtotal /= 2;
620
621 if (IS_GEN2(dev))
622 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
623 else
624 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
625
626 /*
627 * See update_scanline_offset() for the details on the
628 * scanline_offset adjustment.
629 */
630 return (position + crtc->scanline_offset) % vtotal;
631 }
632
633 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
634 unsigned int flags, int *vpos, int *hpos,
635 ktime_t *stime, ktime_t *etime)
636 {
637 struct drm_i915_private *dev_priv = dev->dev_private;
638 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
639 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
640 const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
641 int position;
642 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
643 bool in_vbl = true;
644 int ret = 0;
645 unsigned long irqflags;
646
647 if (!intel_crtc->active) {
648 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
649 "pipe %c\n", pipe_name(pipe));
650 return 0;
651 }
652
653 htotal = mode->crtc_htotal;
654 hsync_start = mode->crtc_hsync_start;
655 vtotal = mode->crtc_vtotal;
656 vbl_start = mode->crtc_vblank_start;
657 vbl_end = mode->crtc_vblank_end;
658
659 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
660 vbl_start = DIV_ROUND_UP(vbl_start, 2);
661 vbl_end /= 2;
662 vtotal /= 2;
663 }
664
665 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
666
667 /*
668 * Lock uncore.lock, as we will do multiple timing critical raw
669 * register reads, potentially with preemption disabled, so the
670 * following code must not block on uncore.lock.
671 */
672 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
673
674 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
675
676 /* Get optional system timestamp before query. */
677 if (stime)
678 *stime = ktime_get();
679
680 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
681 /* No obvious pixelcount register. Only query vertical
682 * scanout position from Display scan line register.
683 */
684 position = __intel_get_crtc_scanline(intel_crtc);
685 } else {
686 /* Have access to pixelcount since start of frame.
687 * We can split this into vertical and horizontal
688 * scanout position.
689 */
690 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
691
692 /* convert to pixel counts */
693 vbl_start *= htotal;
694 vbl_end *= htotal;
695 vtotal *= htotal;
696
697 /*
698 * In interlaced modes, the pixel counter counts all pixels,
699 * so one field will have htotal more pixels. In order to avoid
700 * the reported position from jumping backwards when the pixel
701 * counter is beyond the length of the shorter field, just
702 * clamp the position the length of the shorter field. This
703 * matches how the scanline counter based position works since
704 * the scanline counter doesn't count the two half lines.
705 */
706 if (position >= vtotal)
707 position = vtotal - 1;
708
709 /*
710 * Start of vblank interrupt is triggered at start of hsync,
711 * just prior to the first active line of vblank. However we
712 * consider lines to start at the leading edge of horizontal
713 * active. So, should we get here before we've crossed into
714 * the horizontal active of the first line in vblank, we would
715 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
716 * always add htotal-hsync_start to the current pixel position.
717 */
718 position = (position + htotal - hsync_start) % vtotal;
719 }
720
721 /* Get optional system timestamp after query. */
722 if (etime)
723 *etime = ktime_get();
724
725 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
726
727 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
728
729 in_vbl = position >= vbl_start && position < vbl_end;
730
731 /*
732 * While in vblank, position will be negative
733 * counting up towards 0 at vbl_end. And outside
734 * vblank, position will be positive counting
735 * up since vbl_end.
736 */
737 if (position >= vbl_start)
738 position -= vbl_end;
739 else
740 position += vtotal - vbl_end;
741
742 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
743 *vpos = position;
744 *hpos = 0;
745 } else {
746 *vpos = position / htotal;
747 *hpos = position - (*vpos * htotal);
748 }
749
750 /* In vblank? */
751 if (in_vbl)
752 ret |= DRM_SCANOUTPOS_IN_VBLANK;
753
754 return ret;
755 }
756
757 int intel_get_crtc_scanline(struct intel_crtc *crtc)
758 {
759 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
760 unsigned long irqflags;
761 int position;
762
763 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
764 position = __intel_get_crtc_scanline(crtc);
765 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
766
767 return position;
768 }
769
770 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
771 int *max_error,
772 struct timeval *vblank_time,
773 unsigned flags)
774 {
775 struct drm_crtc *crtc;
776
777 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
778 DRM_ERROR("Invalid crtc %d\n", pipe);
779 return -EINVAL;
780 }
781
782 /* Get drm_crtc to timestamp: */
783 crtc = intel_get_crtc_for_pipe(dev, pipe);
784 if (crtc == NULL) {
785 DRM_ERROR("Invalid crtc %d\n", pipe);
786 return -EINVAL;
787 }
788
789 if (!crtc->enabled) {
790 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
791 return -EBUSY;
792 }
793
794 /* Helper routine in DRM core does all the work: */
795 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
796 vblank_time, flags,
797 crtc,
798 &to_intel_crtc(crtc)->config.adjusted_mode);
799 }
800
801 static bool intel_hpd_irq_event(struct drm_device *dev,
802 struct drm_connector *connector)
803 {
804 enum drm_connector_status old_status;
805
806 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
807 old_status = connector->status;
808
809 connector->status = connector->funcs->detect(connector, false);
810 if (old_status == connector->status)
811 return false;
812
813 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
814 connector->base.id,
815 connector->name,
816 drm_get_connector_status_name(old_status),
817 drm_get_connector_status_name(connector->status));
818
819 return true;
820 }
821
822 static void i915_digport_work_func(struct work_struct *work)
823 {
824 struct drm_i915_private *dev_priv =
825 container_of(work, struct drm_i915_private, dig_port_work);
826 u32 long_port_mask, short_port_mask;
827 struct intel_digital_port *intel_dig_port;
828 int i, ret;
829 u32 old_bits = 0;
830
831 spin_lock_irq(&dev_priv->irq_lock);
832 long_port_mask = dev_priv->long_hpd_port_mask;
833 dev_priv->long_hpd_port_mask = 0;
834 short_port_mask = dev_priv->short_hpd_port_mask;
835 dev_priv->short_hpd_port_mask = 0;
836 spin_unlock_irq(&dev_priv->irq_lock);
837
838 for (i = 0; i < I915_MAX_PORTS; i++) {
839 bool valid = false;
840 bool long_hpd = false;
841 intel_dig_port = dev_priv->hpd_irq_port[i];
842 if (!intel_dig_port || !intel_dig_port->hpd_pulse)
843 continue;
844
845 if (long_port_mask & (1 << i)) {
846 valid = true;
847 long_hpd = true;
848 } else if (short_port_mask & (1 << i))
849 valid = true;
850
851 if (valid) {
852 ret = intel_dig_port->hpd_pulse(intel_dig_port, long_hpd);
853 if (ret == true) {
854 /* if we get true fallback to old school hpd */
855 old_bits |= (1 << intel_dig_port->base.hpd_pin);
856 }
857 }
858 }
859
860 if (old_bits) {
861 spin_lock_irq(&dev_priv->irq_lock);
862 dev_priv->hpd_event_bits |= old_bits;
863 spin_unlock_irq(&dev_priv->irq_lock);
864 schedule_work(&dev_priv->hotplug_work);
865 }
866 }
867
868 /*
869 * Handle hotplug events outside the interrupt handler proper.
870 */
871 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
872
873 static void i915_hotplug_work_func(struct work_struct *work)
874 {
875 struct drm_i915_private *dev_priv =
876 container_of(work, struct drm_i915_private, hotplug_work);
877 struct drm_device *dev = dev_priv->dev;
878 struct drm_mode_config *mode_config = &dev->mode_config;
879 struct intel_connector *intel_connector;
880 struct intel_encoder *intel_encoder;
881 struct drm_connector *connector;
882 bool hpd_disabled = false;
883 bool changed = false;
884 u32 hpd_event_bits;
885
886 mutex_lock(&mode_config->mutex);
887 DRM_DEBUG_KMS("running encoder hotplug functions\n");
888
889 spin_lock_irq(&dev_priv->irq_lock);
890
891 hpd_event_bits = dev_priv->hpd_event_bits;
892 dev_priv->hpd_event_bits = 0;
893 list_for_each_entry(connector, &mode_config->connector_list, head) {
894 intel_connector = to_intel_connector(connector);
895 if (!intel_connector->encoder)
896 continue;
897 intel_encoder = intel_connector->encoder;
898 if (intel_encoder->hpd_pin > HPD_NONE &&
899 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
900 connector->polled == DRM_CONNECTOR_POLL_HPD) {
901 DRM_INFO("HPD interrupt storm detected on connector %s: "
902 "switching from hotplug detection to polling\n",
903 connector->name);
904 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
905 connector->polled = DRM_CONNECTOR_POLL_CONNECT
906 | DRM_CONNECTOR_POLL_DISCONNECT;
907 hpd_disabled = true;
908 }
909 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
910 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
911 connector->name, intel_encoder->hpd_pin);
912 }
913 }
914 /* if there were no outputs to poll, poll was disabled,
915 * therefore make sure it's enabled when disabling HPD on
916 * some connectors */
917 if (hpd_disabled) {
918 drm_kms_helper_poll_enable(dev);
919 mod_delayed_work(system_wq, &dev_priv->hotplug_reenable_work,
920 msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
921 }
922
923 spin_unlock_irq(&dev_priv->irq_lock);
924
925 list_for_each_entry(connector, &mode_config->connector_list, head) {
926 intel_connector = to_intel_connector(connector);
927 if (!intel_connector->encoder)
928 continue;
929 intel_encoder = intel_connector->encoder;
930 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
931 if (intel_encoder->hot_plug)
932 intel_encoder->hot_plug(intel_encoder);
933 if (intel_hpd_irq_event(dev, connector))
934 changed = true;
935 }
936 }
937 mutex_unlock(&mode_config->mutex);
938
939 if (changed)
940 drm_kms_helper_hotplug_event(dev);
941 }
942
943 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
944 {
945 struct drm_i915_private *dev_priv = dev->dev_private;
946 u32 busy_up, busy_down, max_avg, min_avg;
947 u8 new_delay;
948
949 spin_lock(&mchdev_lock);
950
951 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
952
953 new_delay = dev_priv->ips.cur_delay;
954
955 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
956 busy_up = I915_READ(RCPREVBSYTUPAVG);
957 busy_down = I915_READ(RCPREVBSYTDNAVG);
958 max_avg = I915_READ(RCBMAXAVG);
959 min_avg = I915_READ(RCBMINAVG);
960
961 /* Handle RCS change request from hw */
962 if (busy_up > max_avg) {
963 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
964 new_delay = dev_priv->ips.cur_delay - 1;
965 if (new_delay < dev_priv->ips.max_delay)
966 new_delay = dev_priv->ips.max_delay;
967 } else if (busy_down < min_avg) {
968 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
969 new_delay = dev_priv->ips.cur_delay + 1;
970 if (new_delay > dev_priv->ips.min_delay)
971 new_delay = dev_priv->ips.min_delay;
972 }
973
974 if (ironlake_set_drps(dev, new_delay))
975 dev_priv->ips.cur_delay = new_delay;
976
977 spin_unlock(&mchdev_lock);
978
979 return;
980 }
981
982 static void notify_ring(struct drm_device *dev,
983 struct intel_engine_cs *ring)
984 {
985 if (!intel_ring_initialized(ring))
986 return;
987
988 trace_i915_gem_request_complete(ring);
989
990 wake_up_all(&ring->irq_queue);
991 }
992
993 static u32 vlv_c0_residency(struct drm_i915_private *dev_priv,
994 struct intel_rps_ei *rps_ei)
995 {
996 u32 cz_ts, cz_freq_khz;
997 u32 render_count, media_count;
998 u32 elapsed_render, elapsed_media, elapsed_time;
999 u32 residency = 0;
1000
1001 cz_ts = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
1002 cz_freq_khz = DIV_ROUND_CLOSEST(dev_priv->mem_freq * 1000, 4);
1003
1004 render_count = I915_READ(VLV_RENDER_C0_COUNT_REG);
1005 media_count = I915_READ(VLV_MEDIA_C0_COUNT_REG);
1006
1007 if (rps_ei->cz_clock == 0) {
1008 rps_ei->cz_clock = cz_ts;
1009 rps_ei->render_c0 = render_count;
1010 rps_ei->media_c0 = media_count;
1011
1012 return dev_priv->rps.cur_freq;
1013 }
1014
1015 elapsed_time = cz_ts - rps_ei->cz_clock;
1016 rps_ei->cz_clock = cz_ts;
1017
1018 elapsed_render = render_count - rps_ei->render_c0;
1019 rps_ei->render_c0 = render_count;
1020
1021 elapsed_media = media_count - rps_ei->media_c0;
1022 rps_ei->media_c0 = media_count;
1023
1024 /* Convert all the counters into common unit of milli sec */
1025 elapsed_time /= VLV_CZ_CLOCK_TO_MILLI_SEC;
1026 elapsed_render /= cz_freq_khz;
1027 elapsed_media /= cz_freq_khz;
1028
1029 /*
1030 * Calculate overall C0 residency percentage
1031 * only if elapsed time is non zero
1032 */
1033 if (elapsed_time) {
1034 residency =
1035 ((max(elapsed_render, elapsed_media) * 100)
1036 / elapsed_time);
1037 }
1038
1039 return residency;
1040 }
1041
1042 /**
1043 * vlv_calc_delay_from_C0_counters - Increase/Decrease freq based on GPU
1044 * busy-ness calculated from C0 counters of render & media power wells
1045 * @dev_priv: DRM device private
1046 *
1047 */
1048 static int vlv_calc_delay_from_C0_counters(struct drm_i915_private *dev_priv)
1049 {
1050 u32 residency_C0_up = 0, residency_C0_down = 0;
1051 int new_delay, adj;
1052
1053 dev_priv->rps.ei_interrupt_count++;
1054
1055 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
1056
1057
1058 if (dev_priv->rps.up_ei.cz_clock == 0) {
1059 vlv_c0_residency(dev_priv, &dev_priv->rps.up_ei);
1060 vlv_c0_residency(dev_priv, &dev_priv->rps.down_ei);
1061 return dev_priv->rps.cur_freq;
1062 }
1063
1064
1065 /*
1066 * To down throttle, C0 residency should be less than down threshold
1067 * for continous EI intervals. So calculate down EI counters
1068 * once in VLV_INT_COUNT_FOR_DOWN_EI
1069 */
1070 if (dev_priv->rps.ei_interrupt_count == VLV_INT_COUNT_FOR_DOWN_EI) {
1071
1072 dev_priv->rps.ei_interrupt_count = 0;
1073
1074 residency_C0_down = vlv_c0_residency(dev_priv,
1075 &dev_priv->rps.down_ei);
1076 } else {
1077 residency_C0_up = vlv_c0_residency(dev_priv,
1078 &dev_priv->rps.up_ei);
1079 }
1080
1081 new_delay = dev_priv->rps.cur_freq;
1082
1083 adj = dev_priv->rps.last_adj;
1084 /* C0 residency is greater than UP threshold. Increase Frequency */
1085 if (residency_C0_up >= VLV_RP_UP_EI_THRESHOLD) {
1086 if (adj > 0)
1087 adj *= 2;
1088 else
1089 adj = 1;
1090
1091 if (dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit)
1092 new_delay = dev_priv->rps.cur_freq + adj;
1093
1094 /*
1095 * For better performance, jump directly
1096 * to RPe if we're below it.
1097 */
1098 if (new_delay < dev_priv->rps.efficient_freq)
1099 new_delay = dev_priv->rps.efficient_freq;
1100
1101 } else if (!dev_priv->rps.ei_interrupt_count &&
1102 (residency_C0_down < VLV_RP_DOWN_EI_THRESHOLD)) {
1103 if (adj < 0)
1104 adj *= 2;
1105 else
1106 adj = -1;
1107 /*
1108 * This means, C0 residency is less than down threshold over
1109 * a period of VLV_INT_COUNT_FOR_DOWN_EI. So, reduce the freq
1110 */
1111 if (dev_priv->rps.cur_freq > dev_priv->rps.min_freq_softlimit)
1112 new_delay = dev_priv->rps.cur_freq + adj;
1113 }
1114
1115 return new_delay;
1116 }
1117
1118 static void gen6_pm_rps_work(struct work_struct *work)
1119 {
1120 struct drm_i915_private *dev_priv =
1121 container_of(work, struct drm_i915_private, rps.work);
1122 u32 pm_iir;
1123 int new_delay, adj;
1124
1125 spin_lock_irq(&dev_priv->irq_lock);
1126 pm_iir = dev_priv->rps.pm_iir;
1127 dev_priv->rps.pm_iir = 0;
1128 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1129 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1130 spin_unlock_irq(&dev_priv->irq_lock);
1131
1132 /* Make sure we didn't queue anything we're not going to process. */
1133 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1134
1135 if ((pm_iir & dev_priv->pm_rps_events) == 0)
1136 return;
1137
1138 mutex_lock(&dev_priv->rps.hw_lock);
1139
1140 adj = dev_priv->rps.last_adj;
1141 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1142 if (adj > 0)
1143 adj *= 2;
1144 else {
1145 /* CHV needs even encode values */
1146 adj = IS_CHERRYVIEW(dev_priv->dev) ? 2 : 1;
1147 }
1148 new_delay = dev_priv->rps.cur_freq + adj;
1149
1150 /*
1151 * For better performance, jump directly
1152 * to RPe if we're below it.
1153 */
1154 if (new_delay < dev_priv->rps.efficient_freq)
1155 new_delay = dev_priv->rps.efficient_freq;
1156 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1157 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1158 new_delay = dev_priv->rps.efficient_freq;
1159 else
1160 new_delay = dev_priv->rps.min_freq_softlimit;
1161 adj = 0;
1162 } else if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1163 new_delay = vlv_calc_delay_from_C0_counters(dev_priv);
1164 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1165 if (adj < 0)
1166 adj *= 2;
1167 else {
1168 /* CHV needs even encode values */
1169 adj = IS_CHERRYVIEW(dev_priv->dev) ? -2 : -1;
1170 }
1171 new_delay = dev_priv->rps.cur_freq + adj;
1172 } else { /* unknown event */
1173 new_delay = dev_priv->rps.cur_freq;
1174 }
1175
1176 /* sysfs frequency interfaces may have snuck in while servicing the
1177 * interrupt
1178 */
1179 new_delay = clamp_t(int, new_delay,
1180 dev_priv->rps.min_freq_softlimit,
1181 dev_priv->rps.max_freq_softlimit);
1182
1183 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq;
1184
1185 if (IS_VALLEYVIEW(dev_priv->dev))
1186 valleyview_set_rps(dev_priv->dev, new_delay);
1187 else
1188 gen6_set_rps(dev_priv->dev, new_delay);
1189
1190 mutex_unlock(&dev_priv->rps.hw_lock);
1191 }
1192
1193
1194 /**
1195 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1196 * occurred.
1197 * @work: workqueue struct
1198 *
1199 * Doesn't actually do anything except notify userspace. As a consequence of
1200 * this event, userspace should try to remap the bad rows since statistically
1201 * it is likely the same row is more likely to go bad again.
1202 */
1203 static void ivybridge_parity_work(struct work_struct *work)
1204 {
1205 struct drm_i915_private *dev_priv =
1206 container_of(work, struct drm_i915_private, l3_parity.error_work);
1207 u32 error_status, row, bank, subbank;
1208 char *parity_event[6];
1209 uint32_t misccpctl;
1210 uint8_t slice = 0;
1211
1212 /* We must turn off DOP level clock gating to access the L3 registers.
1213 * In order to prevent a get/put style interface, acquire struct mutex
1214 * any time we access those registers.
1215 */
1216 mutex_lock(&dev_priv->dev->struct_mutex);
1217
1218 /* If we've screwed up tracking, just let the interrupt fire again */
1219 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1220 goto out;
1221
1222 misccpctl = I915_READ(GEN7_MISCCPCTL);
1223 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1224 POSTING_READ(GEN7_MISCCPCTL);
1225
1226 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1227 u32 reg;
1228
1229 slice--;
1230 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1231 break;
1232
1233 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1234
1235 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1236
1237 error_status = I915_READ(reg);
1238 row = GEN7_PARITY_ERROR_ROW(error_status);
1239 bank = GEN7_PARITY_ERROR_BANK(error_status);
1240 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1241
1242 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1243 POSTING_READ(reg);
1244
1245 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1246 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1247 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1248 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1249 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1250 parity_event[5] = NULL;
1251
1252 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1253 KOBJ_CHANGE, parity_event);
1254
1255 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1256 slice, row, bank, subbank);
1257
1258 kfree(parity_event[4]);
1259 kfree(parity_event[3]);
1260 kfree(parity_event[2]);
1261 kfree(parity_event[1]);
1262 }
1263
1264 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1265
1266 out:
1267 WARN_ON(dev_priv->l3_parity.which_slice);
1268 spin_lock_irq(&dev_priv->irq_lock);
1269 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1270 spin_unlock_irq(&dev_priv->irq_lock);
1271
1272 mutex_unlock(&dev_priv->dev->struct_mutex);
1273 }
1274
1275 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1276 {
1277 struct drm_i915_private *dev_priv = dev->dev_private;
1278
1279 if (!HAS_L3_DPF(dev))
1280 return;
1281
1282 spin_lock(&dev_priv->irq_lock);
1283 gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1284 spin_unlock(&dev_priv->irq_lock);
1285
1286 iir &= GT_PARITY_ERROR(dev);
1287 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1288 dev_priv->l3_parity.which_slice |= 1 << 1;
1289
1290 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1291 dev_priv->l3_parity.which_slice |= 1 << 0;
1292
1293 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1294 }
1295
1296 static void ilk_gt_irq_handler(struct drm_device *dev,
1297 struct drm_i915_private *dev_priv,
1298 u32 gt_iir)
1299 {
1300 if (gt_iir &
1301 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1302 notify_ring(dev, &dev_priv->ring[RCS]);
1303 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1304 notify_ring(dev, &dev_priv->ring[VCS]);
1305 }
1306
1307 static void snb_gt_irq_handler(struct drm_device *dev,
1308 struct drm_i915_private *dev_priv,
1309 u32 gt_iir)
1310 {
1311
1312 if (gt_iir &
1313 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1314 notify_ring(dev, &dev_priv->ring[RCS]);
1315 if (gt_iir & GT_BSD_USER_INTERRUPT)
1316 notify_ring(dev, &dev_priv->ring[VCS]);
1317 if (gt_iir & GT_BLT_USER_INTERRUPT)
1318 notify_ring(dev, &dev_priv->ring[BCS]);
1319
1320 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1321 GT_BSD_CS_ERROR_INTERRUPT |
1322 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
1323 i915_handle_error(dev, false, "GT error interrupt 0x%08x",
1324 gt_iir);
1325 }
1326
1327 if (gt_iir & GT_PARITY_ERROR(dev))
1328 ivybridge_parity_error_irq_handler(dev, gt_iir);
1329 }
1330
1331 static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1332 struct drm_i915_private *dev_priv,
1333 u32 master_ctl)
1334 {
1335 struct intel_engine_cs *ring;
1336 u32 rcs, bcs, vcs;
1337 uint32_t tmp = 0;
1338 irqreturn_t ret = IRQ_NONE;
1339
1340 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1341 tmp = I915_READ(GEN8_GT_IIR(0));
1342 if (tmp) {
1343 I915_WRITE(GEN8_GT_IIR(0), tmp);
1344 ret = IRQ_HANDLED;
1345
1346 rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1347 ring = &dev_priv->ring[RCS];
1348 if (rcs & GT_RENDER_USER_INTERRUPT)
1349 notify_ring(dev, ring);
1350 if (rcs & GT_CONTEXT_SWITCH_INTERRUPT)
1351 intel_execlists_handle_ctx_events(ring);
1352
1353 bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1354 ring = &dev_priv->ring[BCS];
1355 if (bcs & GT_RENDER_USER_INTERRUPT)
1356 notify_ring(dev, ring);
1357 if (bcs & GT_CONTEXT_SWITCH_INTERRUPT)
1358 intel_execlists_handle_ctx_events(ring);
1359 } else
1360 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1361 }
1362
1363 if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1364 tmp = I915_READ(GEN8_GT_IIR(1));
1365 if (tmp) {
1366 I915_WRITE(GEN8_GT_IIR(1), tmp);
1367 ret = IRQ_HANDLED;
1368
1369 vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1370 ring = &dev_priv->ring[VCS];
1371 if (vcs & GT_RENDER_USER_INTERRUPT)
1372 notify_ring(dev, ring);
1373 if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1374 intel_execlists_handle_ctx_events(ring);
1375
1376 vcs = tmp >> GEN8_VCS2_IRQ_SHIFT;
1377 ring = &dev_priv->ring[VCS2];
1378 if (vcs & GT_RENDER_USER_INTERRUPT)
1379 notify_ring(dev, ring);
1380 if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1381 intel_execlists_handle_ctx_events(ring);
1382 } else
1383 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1384 }
1385
1386 if (master_ctl & GEN8_GT_PM_IRQ) {
1387 tmp = I915_READ(GEN8_GT_IIR(2));
1388 if (tmp & dev_priv->pm_rps_events) {
1389 I915_WRITE(GEN8_GT_IIR(2),
1390 tmp & dev_priv->pm_rps_events);
1391 ret = IRQ_HANDLED;
1392 gen6_rps_irq_handler(dev_priv, tmp);
1393 } else
1394 DRM_ERROR("The master control interrupt lied (PM)!\n");
1395 }
1396
1397 if (master_ctl & GEN8_GT_VECS_IRQ) {
1398 tmp = I915_READ(GEN8_GT_IIR(3));
1399 if (tmp) {
1400 I915_WRITE(GEN8_GT_IIR(3), tmp);
1401 ret = IRQ_HANDLED;
1402
1403 vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1404 ring = &dev_priv->ring[VECS];
1405 if (vcs & GT_RENDER_USER_INTERRUPT)
1406 notify_ring(dev, ring);
1407 if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1408 intel_execlists_handle_ctx_events(ring);
1409 } else
1410 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1411 }
1412
1413 return ret;
1414 }
1415
1416 #define HPD_STORM_DETECT_PERIOD 1000
1417 #define HPD_STORM_THRESHOLD 5
1418
1419 static int pch_port_to_hotplug_shift(enum port port)
1420 {
1421 switch (port) {
1422 case PORT_A:
1423 case PORT_E:
1424 default:
1425 return -1;
1426 case PORT_B:
1427 return 0;
1428 case PORT_C:
1429 return 8;
1430 case PORT_D:
1431 return 16;
1432 }
1433 }
1434
1435 static int i915_port_to_hotplug_shift(enum port port)
1436 {
1437 switch (port) {
1438 case PORT_A:
1439 case PORT_E:
1440 default:
1441 return -1;
1442 case PORT_B:
1443 return 17;
1444 case PORT_C:
1445 return 19;
1446 case PORT_D:
1447 return 21;
1448 }
1449 }
1450
1451 static inline enum port get_port_from_pin(enum hpd_pin pin)
1452 {
1453 switch (pin) {
1454 case HPD_PORT_B:
1455 return PORT_B;
1456 case HPD_PORT_C:
1457 return PORT_C;
1458 case HPD_PORT_D:
1459 return PORT_D;
1460 default:
1461 return PORT_A; /* no hpd */
1462 }
1463 }
1464
1465 static inline void intel_hpd_irq_handler(struct drm_device *dev,
1466 u32 hotplug_trigger,
1467 u32 dig_hotplug_reg,
1468 const u32 *hpd)
1469 {
1470 struct drm_i915_private *dev_priv = dev->dev_private;
1471 int i;
1472 enum port port;
1473 bool storm_detected = false;
1474 bool queue_dig = false, queue_hp = false;
1475 u32 dig_shift;
1476 u32 dig_port_mask = 0;
1477
1478 if (!hotplug_trigger)
1479 return;
1480
1481 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x\n",
1482 hotplug_trigger, dig_hotplug_reg);
1483
1484 spin_lock(&dev_priv->irq_lock);
1485 for (i = 1; i < HPD_NUM_PINS; i++) {
1486 if (!(hpd[i] & hotplug_trigger))
1487 continue;
1488
1489 port = get_port_from_pin(i);
1490 if (port && dev_priv->hpd_irq_port[port]) {
1491 bool long_hpd;
1492
1493 if (HAS_PCH_SPLIT(dev)) {
1494 dig_shift = pch_port_to_hotplug_shift(port);
1495 long_hpd = (dig_hotplug_reg >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
1496 } else {
1497 dig_shift = i915_port_to_hotplug_shift(port);
1498 long_hpd = (hotplug_trigger >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
1499 }
1500
1501 DRM_DEBUG_DRIVER("digital hpd port %c - %s\n",
1502 port_name(port),
1503 long_hpd ? "long" : "short");
1504 /* for long HPD pulses we want to have the digital queue happen,
1505 but we still want HPD storm detection to function. */
1506 if (long_hpd) {
1507 dev_priv->long_hpd_port_mask |= (1 << port);
1508 dig_port_mask |= hpd[i];
1509 } else {
1510 /* for short HPD just trigger the digital queue */
1511 dev_priv->short_hpd_port_mask |= (1 << port);
1512 hotplug_trigger &= ~hpd[i];
1513 }
1514 queue_dig = true;
1515 }
1516 }
1517
1518 for (i = 1; i < HPD_NUM_PINS; i++) {
1519 if (hpd[i] & hotplug_trigger &&
1520 dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) {
1521 /*
1522 * On GMCH platforms the interrupt mask bits only
1523 * prevent irq generation, not the setting of the
1524 * hotplug bits itself. So only WARN about unexpected
1525 * interrupts on saner platforms.
1526 */
1527 WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
1528 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1529 hotplug_trigger, i, hpd[i]);
1530
1531 continue;
1532 }
1533
1534 if (!(hpd[i] & hotplug_trigger) ||
1535 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1536 continue;
1537
1538 if (!(dig_port_mask & hpd[i])) {
1539 dev_priv->hpd_event_bits |= (1 << i);
1540 queue_hp = true;
1541 }
1542
1543 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1544 dev_priv->hpd_stats[i].hpd_last_jiffies
1545 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1546 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1547 dev_priv->hpd_stats[i].hpd_cnt = 0;
1548 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1549 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1550 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1551 dev_priv->hpd_event_bits &= ~(1 << i);
1552 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1553 storm_detected = true;
1554 } else {
1555 dev_priv->hpd_stats[i].hpd_cnt++;
1556 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1557 dev_priv->hpd_stats[i].hpd_cnt);
1558 }
1559 }
1560
1561 if (storm_detected)
1562 dev_priv->display.hpd_irq_setup(dev);
1563 spin_unlock(&dev_priv->irq_lock);
1564
1565 /*
1566 * Our hotplug handler can grab modeset locks (by calling down into the
1567 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1568 * queue for otherwise the flush_work in the pageflip code will
1569 * deadlock.
1570 */
1571 if (queue_dig)
1572 queue_work(dev_priv->dp_wq, &dev_priv->dig_port_work);
1573 if (queue_hp)
1574 schedule_work(&dev_priv->hotplug_work);
1575 }
1576
1577 static void gmbus_irq_handler(struct drm_device *dev)
1578 {
1579 struct drm_i915_private *dev_priv = dev->dev_private;
1580
1581 wake_up_all(&dev_priv->gmbus_wait_queue);
1582 }
1583
1584 static void dp_aux_irq_handler(struct drm_device *dev)
1585 {
1586 struct drm_i915_private *dev_priv = dev->dev_private;
1587
1588 wake_up_all(&dev_priv->gmbus_wait_queue);
1589 }
1590
1591 #if defined(CONFIG_DEBUG_FS)
1592 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1593 uint32_t crc0, uint32_t crc1,
1594 uint32_t crc2, uint32_t crc3,
1595 uint32_t crc4)
1596 {
1597 struct drm_i915_private *dev_priv = dev->dev_private;
1598 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1599 struct intel_pipe_crc_entry *entry;
1600 int head, tail;
1601
1602 spin_lock(&pipe_crc->lock);
1603
1604 if (!pipe_crc->entries) {
1605 spin_unlock(&pipe_crc->lock);
1606 DRM_ERROR("spurious interrupt\n");
1607 return;
1608 }
1609
1610 head = pipe_crc->head;
1611 tail = pipe_crc->tail;
1612
1613 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1614 spin_unlock(&pipe_crc->lock);
1615 DRM_ERROR("CRC buffer overflowing\n");
1616 return;
1617 }
1618
1619 entry = &pipe_crc->entries[head];
1620
1621 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1622 entry->crc[0] = crc0;
1623 entry->crc[1] = crc1;
1624 entry->crc[2] = crc2;
1625 entry->crc[3] = crc3;
1626 entry->crc[4] = crc4;
1627
1628 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1629 pipe_crc->head = head;
1630
1631 spin_unlock(&pipe_crc->lock);
1632
1633 wake_up_interruptible(&pipe_crc->wq);
1634 }
1635 #else
1636 static inline void
1637 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1638 uint32_t crc0, uint32_t crc1,
1639 uint32_t crc2, uint32_t crc3,
1640 uint32_t crc4) {}
1641 #endif
1642
1643
1644 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1645 {
1646 struct drm_i915_private *dev_priv = dev->dev_private;
1647
1648 display_pipe_crc_irq_handler(dev, pipe,
1649 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1650 0, 0, 0, 0);
1651 }
1652
1653 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1654 {
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1656
1657 display_pipe_crc_irq_handler(dev, pipe,
1658 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1659 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1660 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1661 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1662 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1663 }
1664
1665 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1666 {
1667 struct drm_i915_private *dev_priv = dev->dev_private;
1668 uint32_t res1, res2;
1669
1670 if (INTEL_INFO(dev)->gen >= 3)
1671 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1672 else
1673 res1 = 0;
1674
1675 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1676 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1677 else
1678 res2 = 0;
1679
1680 display_pipe_crc_irq_handler(dev, pipe,
1681 I915_READ(PIPE_CRC_RES_RED(pipe)),
1682 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1683 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1684 res1, res2);
1685 }
1686
1687 /* The RPS events need forcewake, so we add them to a work queue and mask their
1688 * IMR bits until the work is done. Other interrupts can be processed without
1689 * the work queue. */
1690 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1691 {
1692 /* TODO: RPS on GEN9+ is not supported yet. */
1693 if (WARN_ONCE(INTEL_INFO(dev_priv)->gen >= 9,
1694 "GEN9+: unexpected RPS IRQ\n"))
1695 return;
1696
1697 if (pm_iir & dev_priv->pm_rps_events) {
1698 spin_lock(&dev_priv->irq_lock);
1699 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1700 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1701 spin_unlock(&dev_priv->irq_lock);
1702
1703 queue_work(dev_priv->wq, &dev_priv->rps.work);
1704 }
1705
1706 if (INTEL_INFO(dev_priv)->gen >= 8)
1707 return;
1708
1709 if (HAS_VEBOX(dev_priv->dev)) {
1710 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1711 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1712
1713 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1714 i915_handle_error(dev_priv->dev, false,
1715 "VEBOX CS error interrupt 0x%08x",
1716 pm_iir);
1717 }
1718 }
1719 }
1720
1721 static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
1722 {
1723 if (!drm_handle_vblank(dev, pipe))
1724 return false;
1725
1726 return true;
1727 }
1728
1729 static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1730 {
1731 struct drm_i915_private *dev_priv = dev->dev_private;
1732 u32 pipe_stats[I915_MAX_PIPES] = { };
1733 int pipe;
1734
1735 spin_lock(&dev_priv->irq_lock);
1736 for_each_pipe(dev_priv, pipe) {
1737 int reg;
1738 u32 mask, iir_bit = 0;
1739
1740 /*
1741 * PIPESTAT bits get signalled even when the interrupt is
1742 * disabled with the mask bits, and some of the status bits do
1743 * not generate interrupts at all (like the underrun bit). Hence
1744 * we need to be careful that we only handle what we want to
1745 * handle.
1746 */
1747
1748 /* fifo underruns are filterered in the underrun handler. */
1749 mask = PIPE_FIFO_UNDERRUN_STATUS;
1750
1751 switch (pipe) {
1752 case PIPE_A:
1753 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1754 break;
1755 case PIPE_B:
1756 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1757 break;
1758 case PIPE_C:
1759 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1760 break;
1761 }
1762 if (iir & iir_bit)
1763 mask |= dev_priv->pipestat_irq_mask[pipe];
1764
1765 if (!mask)
1766 continue;
1767
1768 reg = PIPESTAT(pipe);
1769 mask |= PIPESTAT_INT_ENABLE_MASK;
1770 pipe_stats[pipe] = I915_READ(reg) & mask;
1771
1772 /*
1773 * Clear the PIPE*STAT regs before the IIR
1774 */
1775 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1776 PIPESTAT_INT_STATUS_MASK))
1777 I915_WRITE(reg, pipe_stats[pipe]);
1778 }
1779 spin_unlock(&dev_priv->irq_lock);
1780
1781 for_each_pipe(dev_priv, pipe) {
1782 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1783 intel_pipe_handle_vblank(dev, pipe))
1784 intel_check_page_flip(dev, pipe);
1785
1786 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
1787 intel_prepare_page_flip(dev, pipe);
1788 intel_finish_page_flip(dev, pipe);
1789 }
1790
1791 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1792 i9xx_pipe_crc_irq_handler(dev, pipe);
1793
1794 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1795 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1796 }
1797
1798 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1799 gmbus_irq_handler(dev);
1800 }
1801
1802 static void i9xx_hpd_irq_handler(struct drm_device *dev)
1803 {
1804 struct drm_i915_private *dev_priv = dev->dev_private;
1805 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1806
1807 if (hotplug_status) {
1808 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1809 /*
1810 * Make sure hotplug status is cleared before we clear IIR, or else we
1811 * may miss hotplug events.
1812 */
1813 POSTING_READ(PORT_HOTPLUG_STAT);
1814
1815 if (IS_G4X(dev)) {
1816 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1817
1818 intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_g4x);
1819 } else {
1820 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1821
1822 intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_i915);
1823 }
1824
1825 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) &&
1826 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1827 dp_aux_irq_handler(dev);
1828 }
1829 }
1830
1831 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1832 {
1833 struct drm_device *dev = arg;
1834 struct drm_i915_private *dev_priv = dev->dev_private;
1835 u32 iir, gt_iir, pm_iir;
1836 irqreturn_t ret = IRQ_NONE;
1837
1838 while (true) {
1839 /* Find, clear, then process each source of interrupt */
1840
1841 gt_iir = I915_READ(GTIIR);
1842 if (gt_iir)
1843 I915_WRITE(GTIIR, gt_iir);
1844
1845 pm_iir = I915_READ(GEN6_PMIIR);
1846 if (pm_iir)
1847 I915_WRITE(GEN6_PMIIR, pm_iir);
1848
1849 iir = I915_READ(VLV_IIR);
1850 if (iir) {
1851 /* Consume port before clearing IIR or we'll miss events */
1852 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1853 i9xx_hpd_irq_handler(dev);
1854 I915_WRITE(VLV_IIR, iir);
1855 }
1856
1857 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1858 goto out;
1859
1860 ret = IRQ_HANDLED;
1861
1862 if (gt_iir)
1863 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1864 if (pm_iir)
1865 gen6_rps_irq_handler(dev_priv, pm_iir);
1866 /* Call regardless, as some status bits might not be
1867 * signalled in iir */
1868 valleyview_pipestat_irq_handler(dev, iir);
1869 }
1870
1871 out:
1872 return ret;
1873 }
1874
1875 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1876 {
1877 struct drm_device *dev = arg;
1878 struct drm_i915_private *dev_priv = dev->dev_private;
1879 u32 master_ctl, iir;
1880 irqreturn_t ret = IRQ_NONE;
1881
1882 for (;;) {
1883 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1884 iir = I915_READ(VLV_IIR);
1885
1886 if (master_ctl == 0 && iir == 0)
1887 break;
1888
1889 ret = IRQ_HANDLED;
1890
1891 I915_WRITE(GEN8_MASTER_IRQ, 0);
1892
1893 /* Find, clear, then process each source of interrupt */
1894
1895 if (iir) {
1896 /* Consume port before clearing IIR or we'll miss events */
1897 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1898 i9xx_hpd_irq_handler(dev);
1899 I915_WRITE(VLV_IIR, iir);
1900 }
1901
1902 gen8_gt_irq_handler(dev, dev_priv, master_ctl);
1903
1904 /* Call regardless, as some status bits might not be
1905 * signalled in iir */
1906 valleyview_pipestat_irq_handler(dev, iir);
1907
1908 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
1909 POSTING_READ(GEN8_MASTER_IRQ);
1910 }
1911
1912 return ret;
1913 }
1914
1915 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1916 {
1917 struct drm_i915_private *dev_priv = dev->dev_private;
1918 int pipe;
1919 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1920 u32 dig_hotplug_reg;
1921
1922 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1923 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1924
1925 intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_ibx);
1926
1927 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1928 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1929 SDE_AUDIO_POWER_SHIFT);
1930 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1931 port_name(port));
1932 }
1933
1934 if (pch_iir & SDE_AUX_MASK)
1935 dp_aux_irq_handler(dev);
1936
1937 if (pch_iir & SDE_GMBUS)
1938 gmbus_irq_handler(dev);
1939
1940 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1941 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1942
1943 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1944 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1945
1946 if (pch_iir & SDE_POISON)
1947 DRM_ERROR("PCH poison interrupt\n");
1948
1949 if (pch_iir & SDE_FDI_MASK)
1950 for_each_pipe(dev_priv, pipe)
1951 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1952 pipe_name(pipe),
1953 I915_READ(FDI_RX_IIR(pipe)));
1954
1955 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1956 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1957
1958 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1959 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1960
1961 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1962 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1963
1964 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1965 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
1966 }
1967
1968 static void ivb_err_int_handler(struct drm_device *dev)
1969 {
1970 struct drm_i915_private *dev_priv = dev->dev_private;
1971 u32 err_int = I915_READ(GEN7_ERR_INT);
1972 enum pipe pipe;
1973
1974 if (err_int & ERR_INT_POISON)
1975 DRM_ERROR("Poison interrupt\n");
1976
1977 for_each_pipe(dev_priv, pipe) {
1978 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
1979 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1980
1981 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1982 if (IS_IVYBRIDGE(dev))
1983 ivb_pipe_crc_irq_handler(dev, pipe);
1984 else
1985 hsw_pipe_crc_irq_handler(dev, pipe);
1986 }
1987 }
1988
1989 I915_WRITE(GEN7_ERR_INT, err_int);
1990 }
1991
1992 static void cpt_serr_int_handler(struct drm_device *dev)
1993 {
1994 struct drm_i915_private *dev_priv = dev->dev_private;
1995 u32 serr_int = I915_READ(SERR_INT);
1996
1997 if (serr_int & SERR_INT_POISON)
1998 DRM_ERROR("PCH poison interrupt\n");
1999
2000 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2001 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2002
2003 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2004 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2005
2006 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2007 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
2008
2009 I915_WRITE(SERR_INT, serr_int);
2010 }
2011
2012 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
2013 {
2014 struct drm_i915_private *dev_priv = dev->dev_private;
2015 int pipe;
2016 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2017 u32 dig_hotplug_reg;
2018
2019 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2020 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2021
2022 intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_cpt);
2023
2024 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2025 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2026 SDE_AUDIO_POWER_SHIFT_CPT);
2027 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2028 port_name(port));
2029 }
2030
2031 if (pch_iir & SDE_AUX_MASK_CPT)
2032 dp_aux_irq_handler(dev);
2033
2034 if (pch_iir & SDE_GMBUS_CPT)
2035 gmbus_irq_handler(dev);
2036
2037 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2038 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2039
2040 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2041 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2042
2043 if (pch_iir & SDE_FDI_MASK_CPT)
2044 for_each_pipe(dev_priv, pipe)
2045 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2046 pipe_name(pipe),
2047 I915_READ(FDI_RX_IIR(pipe)));
2048
2049 if (pch_iir & SDE_ERROR_CPT)
2050 cpt_serr_int_handler(dev);
2051 }
2052
2053 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
2054 {
2055 struct drm_i915_private *dev_priv = dev->dev_private;
2056 enum pipe pipe;
2057
2058 if (de_iir & DE_AUX_CHANNEL_A)
2059 dp_aux_irq_handler(dev);
2060
2061 if (de_iir & DE_GSE)
2062 intel_opregion_asle_intr(dev);
2063
2064 if (de_iir & DE_POISON)
2065 DRM_ERROR("Poison interrupt\n");
2066
2067 for_each_pipe(dev_priv, pipe) {
2068 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2069 intel_pipe_handle_vblank(dev, pipe))
2070 intel_check_page_flip(dev, pipe);
2071
2072 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2073 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2074
2075 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2076 i9xx_pipe_crc_irq_handler(dev, pipe);
2077
2078 /* plane/pipes map 1:1 on ilk+ */
2079 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
2080 intel_prepare_page_flip(dev, pipe);
2081 intel_finish_page_flip_plane(dev, pipe);
2082 }
2083 }
2084
2085 /* check event from PCH */
2086 if (de_iir & DE_PCH_EVENT) {
2087 u32 pch_iir = I915_READ(SDEIIR);
2088
2089 if (HAS_PCH_CPT(dev))
2090 cpt_irq_handler(dev, pch_iir);
2091 else
2092 ibx_irq_handler(dev, pch_iir);
2093
2094 /* should clear PCH hotplug event before clear CPU irq */
2095 I915_WRITE(SDEIIR, pch_iir);
2096 }
2097
2098 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
2099 ironlake_rps_change_irq_handler(dev);
2100 }
2101
2102 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
2103 {
2104 struct drm_i915_private *dev_priv = dev->dev_private;
2105 enum pipe pipe;
2106
2107 if (de_iir & DE_ERR_INT_IVB)
2108 ivb_err_int_handler(dev);
2109
2110 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2111 dp_aux_irq_handler(dev);
2112
2113 if (de_iir & DE_GSE_IVB)
2114 intel_opregion_asle_intr(dev);
2115
2116 for_each_pipe(dev_priv, pipe) {
2117 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2118 intel_pipe_handle_vblank(dev, pipe))
2119 intel_check_page_flip(dev, pipe);
2120
2121 /* plane/pipes map 1:1 on ilk+ */
2122 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
2123 intel_prepare_page_flip(dev, pipe);
2124 intel_finish_page_flip_plane(dev, pipe);
2125 }
2126 }
2127
2128 /* check event from PCH */
2129 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
2130 u32 pch_iir = I915_READ(SDEIIR);
2131
2132 cpt_irq_handler(dev, pch_iir);
2133
2134 /* clear PCH hotplug event before clear CPU irq */
2135 I915_WRITE(SDEIIR, pch_iir);
2136 }
2137 }
2138
2139 /*
2140 * To handle irqs with the minimum potential races with fresh interrupts, we:
2141 * 1 - Disable Master Interrupt Control.
2142 * 2 - Find the source(s) of the interrupt.
2143 * 3 - Clear the Interrupt Identity bits (IIR).
2144 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2145 * 5 - Re-enable Master Interrupt Control.
2146 */
2147 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2148 {
2149 struct drm_device *dev = arg;
2150 struct drm_i915_private *dev_priv = dev->dev_private;
2151 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2152 irqreturn_t ret = IRQ_NONE;
2153
2154 /* We get interrupts on unclaimed registers, so check for this before we
2155 * do any I915_{READ,WRITE}. */
2156 intel_uncore_check_errors(dev);
2157
2158 /* disable master interrupt before clearing iir */
2159 de_ier = I915_READ(DEIER);
2160 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2161 POSTING_READ(DEIER);
2162
2163 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2164 * interrupts will will be stored on its back queue, and then we'll be
2165 * able to process them after we restore SDEIER (as soon as we restore
2166 * it, we'll get an interrupt if SDEIIR still has something to process
2167 * due to its back queue). */
2168 if (!HAS_PCH_NOP(dev)) {
2169 sde_ier = I915_READ(SDEIER);
2170 I915_WRITE(SDEIER, 0);
2171 POSTING_READ(SDEIER);
2172 }
2173
2174 /* Find, clear, then process each source of interrupt */
2175
2176 gt_iir = I915_READ(GTIIR);
2177 if (gt_iir) {
2178 I915_WRITE(GTIIR, gt_iir);
2179 ret = IRQ_HANDLED;
2180 if (INTEL_INFO(dev)->gen >= 6)
2181 snb_gt_irq_handler(dev, dev_priv, gt_iir);
2182 else
2183 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
2184 }
2185
2186 de_iir = I915_READ(DEIIR);
2187 if (de_iir) {
2188 I915_WRITE(DEIIR, de_iir);
2189 ret = IRQ_HANDLED;
2190 if (INTEL_INFO(dev)->gen >= 7)
2191 ivb_display_irq_handler(dev, de_iir);
2192 else
2193 ilk_display_irq_handler(dev, de_iir);
2194 }
2195
2196 if (INTEL_INFO(dev)->gen >= 6) {
2197 u32 pm_iir = I915_READ(GEN6_PMIIR);
2198 if (pm_iir) {
2199 I915_WRITE(GEN6_PMIIR, pm_iir);
2200 ret = IRQ_HANDLED;
2201 gen6_rps_irq_handler(dev_priv, pm_iir);
2202 }
2203 }
2204
2205 I915_WRITE(DEIER, de_ier);
2206 POSTING_READ(DEIER);
2207 if (!HAS_PCH_NOP(dev)) {
2208 I915_WRITE(SDEIER, sde_ier);
2209 POSTING_READ(SDEIER);
2210 }
2211
2212 return ret;
2213 }
2214
2215 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2216 {
2217 struct drm_device *dev = arg;
2218 struct drm_i915_private *dev_priv = dev->dev_private;
2219 u32 master_ctl;
2220 irqreturn_t ret = IRQ_NONE;
2221 uint32_t tmp = 0;
2222 enum pipe pipe;
2223 u32 aux_mask = GEN8_AUX_CHANNEL_A;
2224
2225 if (IS_GEN9(dev))
2226 aux_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
2227 GEN9_AUX_CHANNEL_D;
2228
2229 master_ctl = I915_READ(GEN8_MASTER_IRQ);
2230 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2231 if (!master_ctl)
2232 return IRQ_NONE;
2233
2234 I915_WRITE(GEN8_MASTER_IRQ, 0);
2235 POSTING_READ(GEN8_MASTER_IRQ);
2236
2237 /* Find, clear, then process each source of interrupt */
2238
2239 ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
2240
2241 if (master_ctl & GEN8_DE_MISC_IRQ) {
2242 tmp = I915_READ(GEN8_DE_MISC_IIR);
2243 if (tmp) {
2244 I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2245 ret = IRQ_HANDLED;
2246 if (tmp & GEN8_DE_MISC_GSE)
2247 intel_opregion_asle_intr(dev);
2248 else
2249 DRM_ERROR("Unexpected DE Misc interrupt\n");
2250 }
2251 else
2252 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2253 }
2254
2255 if (master_ctl & GEN8_DE_PORT_IRQ) {
2256 tmp = I915_READ(GEN8_DE_PORT_IIR);
2257 if (tmp) {
2258 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2259 ret = IRQ_HANDLED;
2260
2261 if (tmp & aux_mask)
2262 dp_aux_irq_handler(dev);
2263 else
2264 DRM_ERROR("Unexpected DE Port interrupt\n");
2265 }
2266 else
2267 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2268 }
2269
2270 for_each_pipe(dev_priv, pipe) {
2271 uint32_t pipe_iir, flip_done = 0, fault_errors = 0;
2272
2273 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2274 continue;
2275
2276 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2277 if (pipe_iir) {
2278 ret = IRQ_HANDLED;
2279 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2280
2281 if (pipe_iir & GEN8_PIPE_VBLANK &&
2282 intel_pipe_handle_vblank(dev, pipe))
2283 intel_check_page_flip(dev, pipe);
2284
2285 if (IS_GEN9(dev))
2286 flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE;
2287 else
2288 flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE;
2289
2290 if (flip_done) {
2291 intel_prepare_page_flip(dev, pipe);
2292 intel_finish_page_flip_plane(dev, pipe);
2293 }
2294
2295 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2296 hsw_pipe_crc_irq_handler(dev, pipe);
2297
2298 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN)
2299 intel_cpu_fifo_underrun_irq_handler(dev_priv,
2300 pipe);
2301
2302
2303 if (IS_GEN9(dev))
2304 fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2305 else
2306 fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2307
2308 if (fault_errors)
2309 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2310 pipe_name(pipe),
2311 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2312 } else
2313 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2314 }
2315
2316 if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
2317 /*
2318 * FIXME(BDW): Assume for now that the new interrupt handling
2319 * scheme also closed the SDE interrupt handling race we've seen
2320 * on older pch-split platforms. But this needs testing.
2321 */
2322 u32 pch_iir = I915_READ(SDEIIR);
2323 if (pch_iir) {
2324 I915_WRITE(SDEIIR, pch_iir);
2325 ret = IRQ_HANDLED;
2326 cpt_irq_handler(dev, pch_iir);
2327 } else
2328 DRM_ERROR("The master control interrupt lied (SDE)!\n");
2329
2330 }
2331
2332 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2333 POSTING_READ(GEN8_MASTER_IRQ);
2334
2335 return ret;
2336 }
2337
2338 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2339 bool reset_completed)
2340 {
2341 struct intel_engine_cs *ring;
2342 int i;
2343
2344 /*
2345 * Notify all waiters for GPU completion events that reset state has
2346 * been changed, and that they need to restart their wait after
2347 * checking for potential errors (and bail out to drop locks if there is
2348 * a gpu reset pending so that i915_error_work_func can acquire them).
2349 */
2350
2351 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2352 for_each_ring(ring, dev_priv, i)
2353 wake_up_all(&ring->irq_queue);
2354
2355 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2356 wake_up_all(&dev_priv->pending_flip_queue);
2357
2358 /*
2359 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2360 * reset state is cleared.
2361 */
2362 if (reset_completed)
2363 wake_up_all(&dev_priv->gpu_error.reset_queue);
2364 }
2365
2366 /**
2367 * i915_error_work_func - do process context error handling work
2368 * @work: work struct
2369 *
2370 * Fire an error uevent so userspace can see that a hang or error
2371 * was detected.
2372 */
2373 static void i915_error_work_func(struct work_struct *work)
2374 {
2375 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
2376 work);
2377 struct drm_i915_private *dev_priv =
2378 container_of(error, struct drm_i915_private, gpu_error);
2379 struct drm_device *dev = dev_priv->dev;
2380 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2381 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2382 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2383 int ret;
2384
2385 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2386
2387 /*
2388 * Note that there's only one work item which does gpu resets, so we
2389 * need not worry about concurrent gpu resets potentially incrementing
2390 * error->reset_counter twice. We only need to take care of another
2391 * racing irq/hangcheck declaring the gpu dead for a second time. A
2392 * quick check for that is good enough: schedule_work ensures the
2393 * correct ordering between hang detection and this work item, and since
2394 * the reset in-progress bit is only ever set by code outside of this
2395 * work we don't need to worry about any other races.
2396 */
2397 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2398 DRM_DEBUG_DRIVER("resetting chip\n");
2399 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2400 reset_event);
2401
2402 /*
2403 * In most cases it's guaranteed that we get here with an RPM
2404 * reference held, for example because there is a pending GPU
2405 * request that won't finish until the reset is done. This
2406 * isn't the case at least when we get here by doing a
2407 * simulated reset via debugs, so get an RPM reference.
2408 */
2409 intel_runtime_pm_get(dev_priv);
2410 /*
2411 * All state reset _must_ be completed before we update the
2412 * reset counter, for otherwise waiters might miss the reset
2413 * pending state and not properly drop locks, resulting in
2414 * deadlocks with the reset work.
2415 */
2416 ret = i915_reset(dev);
2417
2418 intel_display_handle_reset(dev);
2419
2420 intel_runtime_pm_put(dev_priv);
2421
2422 if (ret == 0) {
2423 /*
2424 * After all the gem state is reset, increment the reset
2425 * counter and wake up everyone waiting for the reset to
2426 * complete.
2427 *
2428 * Since unlock operations are a one-sided barrier only,
2429 * we need to insert a barrier here to order any seqno
2430 * updates before
2431 * the counter increment.
2432 */
2433 smp_mb__before_atomic();
2434 atomic_inc(&dev_priv->gpu_error.reset_counter);
2435
2436 kobject_uevent_env(&dev->primary->kdev->kobj,
2437 KOBJ_CHANGE, reset_done_event);
2438 } else {
2439 atomic_set_mask(I915_WEDGED, &error->reset_counter);
2440 }
2441
2442 /*
2443 * Note: The wake_up also serves as a memory barrier so that
2444 * waiters see the update value of the reset counter atomic_t.
2445 */
2446 i915_error_wake_up(dev_priv, true);
2447 }
2448 }
2449
2450 static void i915_report_and_clear_eir(struct drm_device *dev)
2451 {
2452 struct drm_i915_private *dev_priv = dev->dev_private;
2453 uint32_t instdone[I915_NUM_INSTDONE_REG];
2454 u32 eir = I915_READ(EIR);
2455 int pipe, i;
2456
2457 if (!eir)
2458 return;
2459
2460 pr_err("render error detected, EIR: 0x%08x\n", eir);
2461
2462 i915_get_extra_instdone(dev, instdone);
2463
2464 if (IS_G4X(dev)) {
2465 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2466 u32 ipeir = I915_READ(IPEIR_I965);
2467
2468 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2469 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2470 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2471 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2472 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2473 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2474 I915_WRITE(IPEIR_I965, ipeir);
2475 POSTING_READ(IPEIR_I965);
2476 }
2477 if (eir & GM45_ERROR_PAGE_TABLE) {
2478 u32 pgtbl_err = I915_READ(PGTBL_ER);
2479 pr_err("page table error\n");
2480 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2481 I915_WRITE(PGTBL_ER, pgtbl_err);
2482 POSTING_READ(PGTBL_ER);
2483 }
2484 }
2485
2486 if (!IS_GEN2(dev)) {
2487 if (eir & I915_ERROR_PAGE_TABLE) {
2488 u32 pgtbl_err = I915_READ(PGTBL_ER);
2489 pr_err("page table error\n");
2490 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2491 I915_WRITE(PGTBL_ER, pgtbl_err);
2492 POSTING_READ(PGTBL_ER);
2493 }
2494 }
2495
2496 if (eir & I915_ERROR_MEMORY_REFRESH) {
2497 pr_err("memory refresh error:\n");
2498 for_each_pipe(dev_priv, pipe)
2499 pr_err("pipe %c stat: 0x%08x\n",
2500 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2501 /* pipestat has already been acked */
2502 }
2503 if (eir & I915_ERROR_INSTRUCTION) {
2504 pr_err("instruction error\n");
2505 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
2506 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2507 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2508 if (INTEL_INFO(dev)->gen < 4) {
2509 u32 ipeir = I915_READ(IPEIR);
2510
2511 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2512 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
2513 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
2514 I915_WRITE(IPEIR, ipeir);
2515 POSTING_READ(IPEIR);
2516 } else {
2517 u32 ipeir = I915_READ(IPEIR_I965);
2518
2519 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2520 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2521 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2522 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2523 I915_WRITE(IPEIR_I965, ipeir);
2524 POSTING_READ(IPEIR_I965);
2525 }
2526 }
2527
2528 I915_WRITE(EIR, eir);
2529 POSTING_READ(EIR);
2530 eir = I915_READ(EIR);
2531 if (eir) {
2532 /*
2533 * some errors might have become stuck,
2534 * mask them.
2535 */
2536 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2537 I915_WRITE(EMR, I915_READ(EMR) | eir);
2538 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2539 }
2540 }
2541
2542 /**
2543 * i915_handle_error - handle an error interrupt
2544 * @dev: drm device
2545 *
2546 * Do some basic checking of regsiter state at error interrupt time and
2547 * dump it to the syslog. Also call i915_capture_error_state() to make
2548 * sure we get a record and make it available in debugfs. Fire a uevent
2549 * so userspace knows something bad happened (should trigger collection
2550 * of a ring dump etc.).
2551 */
2552 void i915_handle_error(struct drm_device *dev, bool wedged,
2553 const char *fmt, ...)
2554 {
2555 struct drm_i915_private *dev_priv = dev->dev_private;
2556 va_list args;
2557 char error_msg[80];
2558
2559 va_start(args, fmt);
2560 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2561 va_end(args);
2562
2563 i915_capture_error_state(dev, wedged, error_msg);
2564 i915_report_and_clear_eir(dev);
2565
2566 if (wedged) {
2567 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2568 &dev_priv->gpu_error.reset_counter);
2569
2570 /*
2571 * Wakeup waiting processes so that the reset work function
2572 * i915_error_work_func doesn't deadlock trying to grab various
2573 * locks. By bumping the reset counter first, the woken
2574 * processes will see a reset in progress and back off,
2575 * releasing their locks and then wait for the reset completion.
2576 * We must do this for _all_ gpu waiters that might hold locks
2577 * that the reset work needs to acquire.
2578 *
2579 * Note: The wake_up serves as the required memory barrier to
2580 * ensure that the waiters see the updated value of the reset
2581 * counter atomic_t.
2582 */
2583 i915_error_wake_up(dev_priv, false);
2584 }
2585
2586 /*
2587 * Our reset work can grab modeset locks (since it needs to reset the
2588 * state of outstanding pagelips). Hence it must not be run on our own
2589 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2590 * code will deadlock.
2591 */
2592 schedule_work(&dev_priv->gpu_error.work);
2593 }
2594
2595 /* Called from drm generic code, passed 'crtc' which
2596 * we use as a pipe index
2597 */
2598 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2599 {
2600 struct drm_i915_private *dev_priv = dev->dev_private;
2601 unsigned long irqflags;
2602
2603 if (!i915_pipe_enabled(dev, pipe))
2604 return -EINVAL;
2605
2606 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2607 if (INTEL_INFO(dev)->gen >= 4)
2608 i915_enable_pipestat(dev_priv, pipe,
2609 PIPE_START_VBLANK_INTERRUPT_STATUS);
2610 else
2611 i915_enable_pipestat(dev_priv, pipe,
2612 PIPE_VBLANK_INTERRUPT_STATUS);
2613 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2614
2615 return 0;
2616 }
2617
2618 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2619 {
2620 struct drm_i915_private *dev_priv = dev->dev_private;
2621 unsigned long irqflags;
2622 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2623 DE_PIPE_VBLANK(pipe);
2624
2625 if (!i915_pipe_enabled(dev, pipe))
2626 return -EINVAL;
2627
2628 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2629 ironlake_enable_display_irq(dev_priv, bit);
2630 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2631
2632 return 0;
2633 }
2634
2635 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2636 {
2637 struct drm_i915_private *dev_priv = dev->dev_private;
2638 unsigned long irqflags;
2639
2640 if (!i915_pipe_enabled(dev, pipe))
2641 return -EINVAL;
2642
2643 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2644 i915_enable_pipestat(dev_priv, pipe,
2645 PIPE_START_VBLANK_INTERRUPT_STATUS);
2646 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2647
2648 return 0;
2649 }
2650
2651 static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2652 {
2653 struct drm_i915_private *dev_priv = dev->dev_private;
2654 unsigned long irqflags;
2655
2656 if (!i915_pipe_enabled(dev, pipe))
2657 return -EINVAL;
2658
2659 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2660 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2661 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2662 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2663 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2664 return 0;
2665 }
2666
2667 /* Called from drm generic code, passed 'crtc' which
2668 * we use as a pipe index
2669 */
2670 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2671 {
2672 struct drm_i915_private *dev_priv = dev->dev_private;
2673 unsigned long irqflags;
2674
2675 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2676 i915_disable_pipestat(dev_priv, pipe,
2677 PIPE_VBLANK_INTERRUPT_STATUS |
2678 PIPE_START_VBLANK_INTERRUPT_STATUS);
2679 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2680 }
2681
2682 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2683 {
2684 struct drm_i915_private *dev_priv = dev->dev_private;
2685 unsigned long irqflags;
2686 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2687 DE_PIPE_VBLANK(pipe);
2688
2689 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2690 ironlake_disable_display_irq(dev_priv, bit);
2691 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2692 }
2693
2694 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2695 {
2696 struct drm_i915_private *dev_priv = dev->dev_private;
2697 unsigned long irqflags;
2698
2699 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2700 i915_disable_pipestat(dev_priv, pipe,
2701 PIPE_START_VBLANK_INTERRUPT_STATUS);
2702 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2703 }
2704
2705 static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2706 {
2707 struct drm_i915_private *dev_priv = dev->dev_private;
2708 unsigned long irqflags;
2709
2710 if (!i915_pipe_enabled(dev, pipe))
2711 return;
2712
2713 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2714 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2715 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2716 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2717 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2718 }
2719
2720 static u32
2721 ring_last_seqno(struct intel_engine_cs *ring)
2722 {
2723 return list_entry(ring->request_list.prev,
2724 struct drm_i915_gem_request, list)->seqno;
2725 }
2726
2727 static bool
2728 ring_idle(struct intel_engine_cs *ring, u32 seqno)
2729 {
2730 return (list_empty(&ring->request_list) ||
2731 i915_seqno_passed(seqno, ring_last_seqno(ring)));
2732 }
2733
2734 static bool
2735 ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
2736 {
2737 if (INTEL_INFO(dev)->gen >= 8) {
2738 return (ipehr >> 23) == 0x1c;
2739 } else {
2740 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2741 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2742 MI_SEMAPHORE_REGISTER);
2743 }
2744 }
2745
2746 static struct intel_engine_cs *
2747 semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset)
2748 {
2749 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2750 struct intel_engine_cs *signaller;
2751 int i;
2752
2753 if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
2754 for_each_ring(signaller, dev_priv, i) {
2755 if (ring == signaller)
2756 continue;
2757
2758 if (offset == signaller->semaphore.signal_ggtt[ring->id])
2759 return signaller;
2760 }
2761 } else {
2762 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2763
2764 for_each_ring(signaller, dev_priv, i) {
2765 if(ring == signaller)
2766 continue;
2767
2768 if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
2769 return signaller;
2770 }
2771 }
2772
2773 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2774 ring->id, ipehr, offset);
2775
2776 return NULL;
2777 }
2778
2779 static struct intel_engine_cs *
2780 semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
2781 {
2782 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2783 u32 cmd, ipehr, head;
2784 u64 offset = 0;
2785 int i, backwards;
2786
2787 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2788 if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
2789 return NULL;
2790
2791 /*
2792 * HEAD is likely pointing to the dword after the actual command,
2793 * so scan backwards until we find the MBOX. But limit it to just 3
2794 * or 4 dwords depending on the semaphore wait command size.
2795 * Note that we don't care about ACTHD here since that might
2796 * point at at batch, and semaphores are always emitted into the
2797 * ringbuffer itself.
2798 */
2799 head = I915_READ_HEAD(ring) & HEAD_ADDR;
2800 backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4;
2801
2802 for (i = backwards; i; --i) {
2803 /*
2804 * Be paranoid and presume the hw has gone off into the wild -
2805 * our ring is smaller than what the hardware (and hence
2806 * HEAD_ADDR) allows. Also handles wrap-around.
2807 */
2808 head &= ring->buffer->size - 1;
2809
2810 /* This here seems to blow up */
2811 cmd = ioread32(ring->buffer->virtual_start + head);
2812 if (cmd == ipehr)
2813 break;
2814
2815 head -= 4;
2816 }
2817
2818 if (!i)
2819 return NULL;
2820
2821 *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
2822 if (INTEL_INFO(ring->dev)->gen >= 8) {
2823 offset = ioread32(ring->buffer->virtual_start + head + 12);
2824 offset <<= 32;
2825 offset = ioread32(ring->buffer->virtual_start + head + 8);
2826 }
2827 return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
2828 }
2829
2830 static int semaphore_passed(struct intel_engine_cs *ring)
2831 {
2832 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2833 struct intel_engine_cs *signaller;
2834 u32 seqno;
2835
2836 ring->hangcheck.deadlock++;
2837
2838 signaller = semaphore_waits_for(ring, &seqno);
2839 if (signaller == NULL)
2840 return -1;
2841
2842 /* Prevent pathological recursion due to driver bugs */
2843 if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
2844 return -1;
2845
2846 if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
2847 return 1;
2848
2849 /* cursory check for an unkickable deadlock */
2850 if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
2851 semaphore_passed(signaller) < 0)
2852 return -1;
2853
2854 return 0;
2855 }
2856
2857 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2858 {
2859 struct intel_engine_cs *ring;
2860 int i;
2861
2862 for_each_ring(ring, dev_priv, i)
2863 ring->hangcheck.deadlock = 0;
2864 }
2865
2866 static enum intel_ring_hangcheck_action
2867 ring_stuck(struct intel_engine_cs *ring, u64 acthd)
2868 {
2869 struct drm_device *dev = ring->dev;
2870 struct drm_i915_private *dev_priv = dev->dev_private;
2871 u32 tmp;
2872
2873 if (acthd != ring->hangcheck.acthd) {
2874 if (acthd > ring->hangcheck.max_acthd) {
2875 ring->hangcheck.max_acthd = acthd;
2876 return HANGCHECK_ACTIVE;
2877 }
2878
2879 return HANGCHECK_ACTIVE_LOOP;
2880 }
2881
2882 if (IS_GEN2(dev))
2883 return HANGCHECK_HUNG;
2884
2885 /* Is the chip hanging on a WAIT_FOR_EVENT?
2886 * If so we can simply poke the RB_WAIT bit
2887 * and break the hang. This should work on
2888 * all but the second generation chipsets.
2889 */
2890 tmp = I915_READ_CTL(ring);
2891 if (tmp & RING_WAIT) {
2892 i915_handle_error(dev, false,
2893 "Kicking stuck wait on %s",
2894 ring->name);
2895 I915_WRITE_CTL(ring, tmp);
2896 return HANGCHECK_KICK;
2897 }
2898
2899 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2900 switch (semaphore_passed(ring)) {
2901 default:
2902 return HANGCHECK_HUNG;
2903 case 1:
2904 i915_handle_error(dev, false,
2905 "Kicking stuck semaphore on %s",
2906 ring->name);
2907 I915_WRITE_CTL(ring, tmp);
2908 return HANGCHECK_KICK;
2909 case 0:
2910 return HANGCHECK_WAIT;
2911 }
2912 }
2913
2914 return HANGCHECK_HUNG;
2915 }
2916
2917 /**
2918 * This is called when the chip hasn't reported back with completed
2919 * batchbuffers in a long time. We keep track per ring seqno progress and
2920 * if there are no progress, hangcheck score for that ring is increased.
2921 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2922 * we kick the ring. If we see no progress on three subsequent calls
2923 * we assume chip is wedged and try to fix it by resetting the chip.
2924 */
2925 static void i915_hangcheck_elapsed(unsigned long data)
2926 {
2927 struct drm_device *dev = (struct drm_device *)data;
2928 struct drm_i915_private *dev_priv = dev->dev_private;
2929 struct intel_engine_cs *ring;
2930 int i;
2931 int busy_count = 0, rings_hung = 0;
2932 bool stuck[I915_NUM_RINGS] = { 0 };
2933 #define BUSY 1
2934 #define KICK 5
2935 #define HUNG 20
2936
2937 if (!i915.enable_hangcheck)
2938 return;
2939
2940 for_each_ring(ring, dev_priv, i) {
2941 u64 acthd;
2942 u32 seqno;
2943 bool busy = true;
2944
2945 semaphore_clear_deadlocks(dev_priv);
2946
2947 seqno = ring->get_seqno(ring, false);
2948 acthd = intel_ring_get_active_head(ring);
2949
2950 if (ring->hangcheck.seqno == seqno) {
2951 if (ring_idle(ring, seqno)) {
2952 ring->hangcheck.action = HANGCHECK_IDLE;
2953
2954 if (waitqueue_active(&ring->irq_queue)) {
2955 /* Issue a wake-up to catch stuck h/w. */
2956 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2957 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2958 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2959 ring->name);
2960 else
2961 DRM_INFO("Fake missed irq on %s\n",
2962 ring->name);
2963 wake_up_all(&ring->irq_queue);
2964 }
2965 /* Safeguard against driver failure */
2966 ring->hangcheck.score += BUSY;
2967 } else
2968 busy = false;
2969 } else {
2970 /* We always increment the hangcheck score
2971 * if the ring is busy and still processing
2972 * the same request, so that no single request
2973 * can run indefinitely (such as a chain of
2974 * batches). The only time we do not increment
2975 * the hangcheck score on this ring, if this
2976 * ring is in a legitimate wait for another
2977 * ring. In that case the waiting ring is a
2978 * victim and we want to be sure we catch the
2979 * right culprit. Then every time we do kick
2980 * the ring, add a small increment to the
2981 * score so that we can catch a batch that is
2982 * being repeatedly kicked and so responsible
2983 * for stalling the machine.
2984 */
2985 ring->hangcheck.action = ring_stuck(ring,
2986 acthd);
2987
2988 switch (ring->hangcheck.action) {
2989 case HANGCHECK_IDLE:
2990 case HANGCHECK_WAIT:
2991 case HANGCHECK_ACTIVE:
2992 break;
2993 case HANGCHECK_ACTIVE_LOOP:
2994 ring->hangcheck.score += BUSY;
2995 break;
2996 case HANGCHECK_KICK:
2997 ring->hangcheck.score += KICK;
2998 break;
2999 case HANGCHECK_HUNG:
3000 ring->hangcheck.score += HUNG;
3001 stuck[i] = true;
3002 break;
3003 }
3004 }
3005 } else {
3006 ring->hangcheck.action = HANGCHECK_ACTIVE;
3007
3008 /* Gradually reduce the count so that we catch DoS
3009 * attempts across multiple batches.
3010 */
3011 if (ring->hangcheck.score > 0)
3012 ring->hangcheck.score--;
3013
3014 ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0;
3015 }
3016
3017 ring->hangcheck.seqno = seqno;
3018 ring->hangcheck.acthd = acthd;
3019 busy_count += busy;
3020 }
3021
3022 for_each_ring(ring, dev_priv, i) {
3023 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3024 DRM_INFO("%s on %s\n",
3025 stuck[i] ? "stuck" : "no progress",
3026 ring->name);
3027 rings_hung++;
3028 }
3029 }
3030
3031 if (rings_hung)
3032 return i915_handle_error(dev, true, "Ring hung");
3033
3034 if (busy_count)
3035 /* Reset timer case chip hangs without another request
3036 * being added */
3037 i915_queue_hangcheck(dev);
3038 }
3039
3040 void i915_queue_hangcheck(struct drm_device *dev)
3041 {
3042 struct drm_i915_private *dev_priv = dev->dev_private;
3043 struct timer_list *timer = &dev_priv->gpu_error.hangcheck_timer;
3044
3045 if (!i915.enable_hangcheck)
3046 return;
3047
3048 /* Don't continually defer the hangcheck, but make sure it is active */
3049 if (!timer_pending(timer))
3050 timer->expires = round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES);
3051 mod_timer(timer, timer->expires);
3052 }
3053
3054 static void ibx_irq_reset(struct drm_device *dev)
3055 {
3056 struct drm_i915_private *dev_priv = dev->dev_private;
3057
3058 if (HAS_PCH_NOP(dev))
3059 return;
3060
3061 GEN5_IRQ_RESET(SDE);
3062
3063 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3064 I915_WRITE(SERR_INT, 0xffffffff);
3065 }
3066
3067 /*
3068 * SDEIER is also touched by the interrupt handler to work around missed PCH
3069 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3070 * instead we unconditionally enable all PCH interrupt sources here, but then
3071 * only unmask them as needed with SDEIMR.
3072 *
3073 * This function needs to be called before interrupts are enabled.
3074 */
3075 static void ibx_irq_pre_postinstall(struct drm_device *dev)
3076 {
3077 struct drm_i915_private *dev_priv = dev->dev_private;
3078
3079 if (HAS_PCH_NOP(dev))
3080 return;
3081
3082 WARN_ON(I915_READ(SDEIER) != 0);
3083 I915_WRITE(SDEIER, 0xffffffff);
3084 POSTING_READ(SDEIER);
3085 }
3086
3087 static void gen5_gt_irq_reset(struct drm_device *dev)
3088 {
3089 struct drm_i915_private *dev_priv = dev->dev_private;
3090
3091 GEN5_IRQ_RESET(GT);
3092 if (INTEL_INFO(dev)->gen >= 6)
3093 GEN5_IRQ_RESET(GEN6_PM);
3094 }
3095
3096 /* drm_dma.h hooks
3097 */
3098 static void ironlake_irq_reset(struct drm_device *dev)
3099 {
3100 struct drm_i915_private *dev_priv = dev->dev_private;
3101
3102 I915_WRITE(HWSTAM, 0xffffffff);
3103
3104 GEN5_IRQ_RESET(DE);
3105 if (IS_GEN7(dev))
3106 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3107
3108 gen5_gt_irq_reset(dev);
3109
3110 ibx_irq_reset(dev);
3111 }
3112
3113 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3114 {
3115 enum pipe pipe;
3116
3117 I915_WRITE(PORT_HOTPLUG_EN, 0);
3118 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3119
3120 for_each_pipe(dev_priv, pipe)
3121 I915_WRITE(PIPESTAT(pipe), 0xffff);
3122
3123 GEN5_IRQ_RESET(VLV_);
3124 }
3125
3126 static void valleyview_irq_preinstall(struct drm_device *dev)
3127 {
3128 struct drm_i915_private *dev_priv = dev->dev_private;
3129
3130 /* VLV magic */
3131 I915_WRITE(VLV_IMR, 0);
3132 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
3133 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
3134 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
3135
3136 gen5_gt_irq_reset(dev);
3137
3138 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3139
3140 vlv_display_irq_reset(dev_priv);
3141 }
3142
3143 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3144 {
3145 GEN8_IRQ_RESET_NDX(GT, 0);
3146 GEN8_IRQ_RESET_NDX(GT, 1);
3147 GEN8_IRQ_RESET_NDX(GT, 2);
3148 GEN8_IRQ_RESET_NDX(GT, 3);
3149 }
3150
3151 static void gen8_irq_reset(struct drm_device *dev)
3152 {
3153 struct drm_i915_private *dev_priv = dev->dev_private;
3154 int pipe;
3155
3156 I915_WRITE(GEN8_MASTER_IRQ, 0);
3157 POSTING_READ(GEN8_MASTER_IRQ);
3158
3159 gen8_gt_irq_reset(dev_priv);
3160
3161 for_each_pipe(dev_priv, pipe)
3162 if (intel_display_power_is_enabled(dev_priv,
3163 POWER_DOMAIN_PIPE(pipe)))
3164 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3165
3166 GEN5_IRQ_RESET(GEN8_DE_PORT_);
3167 GEN5_IRQ_RESET(GEN8_DE_MISC_);
3168 GEN5_IRQ_RESET(GEN8_PCU_);
3169
3170 ibx_irq_reset(dev);
3171 }
3172
3173 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv)
3174 {
3175 uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3176
3177 spin_lock_irq(&dev_priv->irq_lock);
3178 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B],
3179 ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
3180 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C],
3181 ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
3182 spin_unlock_irq(&dev_priv->irq_lock);
3183 }
3184
3185 static void cherryview_irq_preinstall(struct drm_device *dev)
3186 {
3187 struct drm_i915_private *dev_priv = dev->dev_private;
3188
3189 I915_WRITE(GEN8_MASTER_IRQ, 0);
3190 POSTING_READ(GEN8_MASTER_IRQ);
3191
3192 gen8_gt_irq_reset(dev_priv);
3193
3194 GEN5_IRQ_RESET(GEN8_PCU_);
3195
3196 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3197
3198 vlv_display_irq_reset(dev_priv);
3199 }
3200
3201 static void ibx_hpd_irq_setup(struct drm_device *dev)
3202 {
3203 struct drm_i915_private *dev_priv = dev->dev_private;
3204 struct intel_encoder *intel_encoder;
3205 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
3206
3207 if (HAS_PCH_IBX(dev)) {
3208 hotplug_irqs = SDE_HOTPLUG_MASK;
3209 for_each_intel_encoder(dev, intel_encoder)
3210 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3211 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
3212 } else {
3213 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3214 for_each_intel_encoder(dev, intel_encoder)
3215 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3216 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
3217 }
3218
3219 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3220
3221 /*
3222 * Enable digital hotplug on the PCH, and configure the DP short pulse
3223 * duration to 2ms (which is the minimum in the Display Port spec)
3224 *
3225 * This register is the same on all known PCH chips.
3226 */
3227 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3228 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3229 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3230 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3231 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3232 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3233 }
3234
3235 static void ibx_irq_postinstall(struct drm_device *dev)
3236 {
3237 struct drm_i915_private *dev_priv = dev->dev_private;
3238 u32 mask;
3239
3240 if (HAS_PCH_NOP(dev))
3241 return;
3242
3243 if (HAS_PCH_IBX(dev))
3244 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3245 else
3246 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3247
3248 GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
3249 I915_WRITE(SDEIMR, ~mask);
3250 }
3251
3252 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3253 {
3254 struct drm_i915_private *dev_priv = dev->dev_private;
3255 u32 pm_irqs, gt_irqs;
3256
3257 pm_irqs = gt_irqs = 0;
3258
3259 dev_priv->gt_irq_mask = ~0;
3260 if (HAS_L3_DPF(dev)) {
3261 /* L3 parity interrupt is always unmasked. */
3262 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3263 gt_irqs |= GT_PARITY_ERROR(dev);
3264 }
3265
3266 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3267 if (IS_GEN5(dev)) {
3268 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3269 ILK_BSD_USER_INTERRUPT;
3270 } else {
3271 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3272 }
3273
3274 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3275
3276 if (INTEL_INFO(dev)->gen >= 6) {
3277 pm_irqs |= dev_priv->pm_rps_events;
3278
3279 if (HAS_VEBOX(dev))
3280 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3281
3282 dev_priv->pm_irq_mask = 0xffffffff;
3283 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3284 }
3285 }
3286
3287 static int ironlake_irq_postinstall(struct drm_device *dev)
3288 {
3289 struct drm_i915_private *dev_priv = dev->dev_private;
3290 u32 display_mask, extra_mask;
3291
3292 if (INTEL_INFO(dev)->gen >= 7) {
3293 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3294 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3295 DE_PLANEB_FLIP_DONE_IVB |
3296 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3297 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3298 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
3299 } else {
3300 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3301 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3302 DE_AUX_CHANNEL_A |
3303 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3304 DE_POISON);
3305 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3306 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
3307 }
3308
3309 dev_priv->irq_mask = ~display_mask;
3310
3311 I915_WRITE(HWSTAM, 0xeffe);
3312
3313 ibx_irq_pre_postinstall(dev);
3314
3315 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3316
3317 gen5_gt_irq_postinstall(dev);
3318
3319 ibx_irq_postinstall(dev);
3320
3321 if (IS_IRONLAKE_M(dev)) {
3322 /* Enable PCU event interrupts
3323 *
3324 * spinlocking not required here for correctness since interrupt
3325 * setup is guaranteed to run in single-threaded context. But we
3326 * need it to make the assert_spin_locked happy. */
3327 spin_lock_irq(&dev_priv->irq_lock);
3328 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
3329 spin_unlock_irq(&dev_priv->irq_lock);
3330 }
3331
3332 return 0;
3333 }
3334
3335 static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3336 {
3337 u32 pipestat_mask;
3338 u32 iir_mask;
3339 enum pipe pipe;
3340
3341 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3342 PIPE_FIFO_UNDERRUN_STATUS;
3343
3344 for_each_pipe(dev_priv, pipe)
3345 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3346 POSTING_READ(PIPESTAT(PIPE_A));
3347
3348 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3349 PIPE_CRC_DONE_INTERRUPT_STATUS;
3350
3351 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3352 for_each_pipe(dev_priv, pipe)
3353 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3354
3355 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3356 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3357 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3358 if (IS_CHERRYVIEW(dev_priv))
3359 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3360 dev_priv->irq_mask &= ~iir_mask;
3361
3362 I915_WRITE(VLV_IIR, iir_mask);
3363 I915_WRITE(VLV_IIR, iir_mask);
3364 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3365 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3366 POSTING_READ(VLV_IMR);
3367 }
3368
3369 static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3370 {
3371 u32 pipestat_mask;
3372 u32 iir_mask;
3373 enum pipe pipe;
3374
3375 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3376 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3377 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3378 if (IS_CHERRYVIEW(dev_priv))
3379 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3380
3381 dev_priv->irq_mask |= iir_mask;
3382 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3383 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3384 I915_WRITE(VLV_IIR, iir_mask);
3385 I915_WRITE(VLV_IIR, iir_mask);
3386 POSTING_READ(VLV_IIR);
3387
3388 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3389 PIPE_CRC_DONE_INTERRUPT_STATUS;
3390
3391 i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3392 for_each_pipe(dev_priv, pipe)
3393 i915_disable_pipestat(dev_priv, pipe, pipestat_mask);
3394
3395 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3396 PIPE_FIFO_UNDERRUN_STATUS;
3397
3398 for_each_pipe(dev_priv, pipe)
3399 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3400 POSTING_READ(PIPESTAT(PIPE_A));
3401 }
3402
3403 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3404 {
3405 assert_spin_locked(&dev_priv->irq_lock);
3406
3407 if (dev_priv->display_irqs_enabled)
3408 return;
3409
3410 dev_priv->display_irqs_enabled = true;
3411
3412 if (intel_irqs_enabled(dev_priv))
3413 valleyview_display_irqs_install(dev_priv);
3414 }
3415
3416 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3417 {
3418 assert_spin_locked(&dev_priv->irq_lock);
3419
3420 if (!dev_priv->display_irqs_enabled)
3421 return;
3422
3423 dev_priv->display_irqs_enabled = false;
3424
3425 if (intel_irqs_enabled(dev_priv))
3426 valleyview_display_irqs_uninstall(dev_priv);
3427 }
3428
3429 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3430 {
3431 dev_priv->irq_mask = ~0;
3432
3433 I915_WRITE(PORT_HOTPLUG_EN, 0);
3434 POSTING_READ(PORT_HOTPLUG_EN);
3435
3436 I915_WRITE(VLV_IIR, 0xffffffff);
3437 I915_WRITE(VLV_IIR, 0xffffffff);
3438 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3439 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3440 POSTING_READ(VLV_IMR);
3441
3442 /* Interrupt setup is already guaranteed to be single-threaded, this is
3443 * just to make the assert_spin_locked check happy. */
3444 spin_lock_irq(&dev_priv->irq_lock);
3445 if (dev_priv->display_irqs_enabled)
3446 valleyview_display_irqs_install(dev_priv);
3447 spin_unlock_irq(&dev_priv->irq_lock);
3448 }
3449
3450 static int valleyview_irq_postinstall(struct drm_device *dev)
3451 {
3452 struct drm_i915_private *dev_priv = dev->dev_private;
3453
3454 vlv_display_irq_postinstall(dev_priv);
3455
3456 gen5_gt_irq_postinstall(dev);
3457
3458 /* ack & enable invalid PTE error interrupts */
3459 #if 0 /* FIXME: add support to irq handler for checking these bits */
3460 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3461 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3462 #endif
3463
3464 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3465
3466 return 0;
3467 }
3468
3469 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3470 {
3471 /* These are interrupts we'll toggle with the ring mask register */
3472 uint32_t gt_interrupts[] = {
3473 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3474 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3475 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3476 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3477 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3478 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3479 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3480 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3481 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3482 0,
3483 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3484 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3485 };
3486
3487 dev_priv->pm_irq_mask = 0xffffffff;
3488 GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3489 GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3490 GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, dev_priv->pm_rps_events);
3491 GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3492 }
3493
3494 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3495 {
3496 uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3497 uint32_t de_pipe_enables;
3498 int pipe;
3499 u32 aux_en = GEN8_AUX_CHANNEL_A;
3500
3501 if (IS_GEN9(dev_priv)) {
3502 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3503 GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3504 aux_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3505 GEN9_AUX_CHANNEL_D;
3506 } else
3507 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3508 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3509
3510 de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3511 GEN8_PIPE_FIFO_UNDERRUN;
3512
3513 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3514 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3515 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3516
3517 for_each_pipe(dev_priv, pipe)
3518 if (intel_display_power_is_enabled(dev_priv,
3519 POWER_DOMAIN_PIPE(pipe)))
3520 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3521 dev_priv->de_irq_mask[pipe],
3522 de_pipe_enables);
3523
3524 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~aux_en, aux_en);
3525 }
3526
3527 static int gen8_irq_postinstall(struct drm_device *dev)
3528 {
3529 struct drm_i915_private *dev_priv = dev->dev_private;
3530
3531 ibx_irq_pre_postinstall(dev);
3532
3533 gen8_gt_irq_postinstall(dev_priv);
3534 gen8_de_irq_postinstall(dev_priv);
3535
3536 ibx_irq_postinstall(dev);
3537
3538 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3539 POSTING_READ(GEN8_MASTER_IRQ);
3540
3541 return 0;
3542 }
3543
3544 static int cherryview_irq_postinstall(struct drm_device *dev)
3545 {
3546 struct drm_i915_private *dev_priv = dev->dev_private;
3547
3548 vlv_display_irq_postinstall(dev_priv);
3549
3550 gen8_gt_irq_postinstall(dev_priv);
3551
3552 I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
3553 POSTING_READ(GEN8_MASTER_IRQ);
3554
3555 return 0;
3556 }
3557
3558 static void gen8_irq_uninstall(struct drm_device *dev)
3559 {
3560 struct drm_i915_private *dev_priv = dev->dev_private;
3561
3562 if (!dev_priv)
3563 return;
3564
3565 gen8_irq_reset(dev);
3566 }
3567
3568 static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv)
3569 {
3570 /* Interrupt setup is already guaranteed to be single-threaded, this is
3571 * just to make the assert_spin_locked check happy. */
3572 spin_lock_irq(&dev_priv->irq_lock);
3573 if (dev_priv->display_irqs_enabled)
3574 valleyview_display_irqs_uninstall(dev_priv);
3575 spin_unlock_irq(&dev_priv->irq_lock);
3576
3577 vlv_display_irq_reset(dev_priv);
3578
3579 dev_priv->irq_mask = 0;
3580 }
3581
3582 static void valleyview_irq_uninstall(struct drm_device *dev)
3583 {
3584 struct drm_i915_private *dev_priv = dev->dev_private;
3585
3586 if (!dev_priv)
3587 return;
3588
3589 I915_WRITE(VLV_MASTER_IER, 0);
3590
3591 gen5_gt_irq_reset(dev);
3592
3593 I915_WRITE(HWSTAM, 0xffffffff);
3594
3595 vlv_display_irq_uninstall(dev_priv);
3596 }
3597
3598 static void cherryview_irq_uninstall(struct drm_device *dev)
3599 {
3600 struct drm_i915_private *dev_priv = dev->dev_private;
3601
3602 if (!dev_priv)
3603 return;
3604
3605 I915_WRITE(GEN8_MASTER_IRQ, 0);
3606 POSTING_READ(GEN8_MASTER_IRQ);
3607
3608 gen8_gt_irq_reset(dev_priv);
3609
3610 GEN5_IRQ_RESET(GEN8_PCU_);
3611
3612 vlv_display_irq_uninstall(dev_priv);
3613 }
3614
3615 static void ironlake_irq_uninstall(struct drm_device *dev)
3616 {
3617 struct drm_i915_private *dev_priv = dev->dev_private;
3618
3619 if (!dev_priv)
3620 return;
3621
3622 ironlake_irq_reset(dev);
3623 }
3624
3625 static void i8xx_irq_preinstall(struct drm_device * dev)
3626 {
3627 struct drm_i915_private *dev_priv = dev->dev_private;
3628 int pipe;
3629
3630 for_each_pipe(dev_priv, pipe)
3631 I915_WRITE(PIPESTAT(pipe), 0);
3632 I915_WRITE16(IMR, 0xffff);
3633 I915_WRITE16(IER, 0x0);
3634 POSTING_READ16(IER);
3635 }
3636
3637 static int i8xx_irq_postinstall(struct drm_device *dev)
3638 {
3639 struct drm_i915_private *dev_priv = dev->dev_private;
3640
3641 I915_WRITE16(EMR,
3642 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3643
3644 /* Unmask the interrupts that we always want on. */
3645 dev_priv->irq_mask =
3646 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3647 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3648 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3649 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3650 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3651 I915_WRITE16(IMR, dev_priv->irq_mask);
3652
3653 I915_WRITE16(IER,
3654 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3655 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3656 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3657 I915_USER_INTERRUPT);
3658 POSTING_READ16(IER);
3659
3660 /* Interrupt setup is already guaranteed to be single-threaded, this is
3661 * just to make the assert_spin_locked check happy. */
3662 spin_lock_irq(&dev_priv->irq_lock);
3663 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3664 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3665 spin_unlock_irq(&dev_priv->irq_lock);
3666
3667 return 0;
3668 }
3669
3670 /*
3671 * Returns true when a page flip has completed.
3672 */
3673 static bool i8xx_handle_vblank(struct drm_device *dev,
3674 int plane, int pipe, u32 iir)
3675 {
3676 struct drm_i915_private *dev_priv = dev->dev_private;
3677 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3678
3679 if (!intel_pipe_handle_vblank(dev, pipe))
3680 return false;
3681
3682 if ((iir & flip_pending) == 0)
3683 goto check_page_flip;
3684
3685 intel_prepare_page_flip(dev, plane);
3686
3687 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3688 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3689 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3690 * the flip is completed (no longer pending). Since this doesn't raise
3691 * an interrupt per se, we watch for the change at vblank.
3692 */
3693 if (I915_READ16(ISR) & flip_pending)
3694 goto check_page_flip;
3695
3696 intel_finish_page_flip(dev, pipe);
3697 return true;
3698
3699 check_page_flip:
3700 intel_check_page_flip(dev, pipe);
3701 return false;
3702 }
3703
3704 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3705 {
3706 struct drm_device *dev = arg;
3707 struct drm_i915_private *dev_priv = dev->dev_private;
3708 u16 iir, new_iir;
3709 u32 pipe_stats[2];
3710 int pipe;
3711 u16 flip_mask =
3712 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3713 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3714
3715 iir = I915_READ16(IIR);
3716 if (iir == 0)
3717 return IRQ_NONE;
3718
3719 while (iir & ~flip_mask) {
3720 /* Can't rely on pipestat interrupt bit in iir as it might
3721 * have been cleared after the pipestat interrupt was received.
3722 * It doesn't set the bit in iir again, but it still produces
3723 * interrupts (for non-MSI).
3724 */
3725 spin_lock(&dev_priv->irq_lock);
3726 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3727 i915_handle_error(dev, false,
3728 "Command parser error, iir 0x%08x",
3729 iir);
3730
3731 for_each_pipe(dev_priv, pipe) {
3732 int reg = PIPESTAT(pipe);
3733 pipe_stats[pipe] = I915_READ(reg);
3734
3735 /*
3736 * Clear the PIPE*STAT regs before the IIR
3737 */
3738 if (pipe_stats[pipe] & 0x8000ffff)
3739 I915_WRITE(reg, pipe_stats[pipe]);
3740 }
3741 spin_unlock(&dev_priv->irq_lock);
3742
3743 I915_WRITE16(IIR, iir & ~flip_mask);
3744 new_iir = I915_READ16(IIR); /* Flush posted writes */
3745
3746 i915_update_dri1_breadcrumb(dev);
3747
3748 if (iir & I915_USER_INTERRUPT)
3749 notify_ring(dev, &dev_priv->ring[RCS]);
3750
3751 for_each_pipe(dev_priv, pipe) {
3752 int plane = pipe;
3753 if (HAS_FBC(dev))
3754 plane = !plane;
3755
3756 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3757 i8xx_handle_vblank(dev, plane, pipe, iir))
3758 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3759
3760 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3761 i9xx_pipe_crc_irq_handler(dev, pipe);
3762
3763 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3764 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3765 pipe);
3766 }
3767
3768 iir = new_iir;
3769 }
3770
3771 return IRQ_HANDLED;
3772 }
3773
3774 static void i8xx_irq_uninstall(struct drm_device * dev)
3775 {
3776 struct drm_i915_private *dev_priv = dev->dev_private;
3777 int pipe;
3778
3779 for_each_pipe(dev_priv, pipe) {
3780 /* Clear enable bits; then clear status bits */
3781 I915_WRITE(PIPESTAT(pipe), 0);
3782 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3783 }
3784 I915_WRITE16(IMR, 0xffff);
3785 I915_WRITE16(IER, 0x0);
3786 I915_WRITE16(IIR, I915_READ16(IIR));
3787 }
3788
3789 static void i915_irq_preinstall(struct drm_device * dev)
3790 {
3791 struct drm_i915_private *dev_priv = dev->dev_private;
3792 int pipe;
3793
3794 if (I915_HAS_HOTPLUG(dev)) {
3795 I915_WRITE(PORT_HOTPLUG_EN, 0);
3796 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3797 }
3798
3799 I915_WRITE16(HWSTAM, 0xeffe);
3800 for_each_pipe(dev_priv, pipe)
3801 I915_WRITE(PIPESTAT(pipe), 0);
3802 I915_WRITE(IMR, 0xffffffff);
3803 I915_WRITE(IER, 0x0);
3804 POSTING_READ(IER);
3805 }
3806
3807 static int i915_irq_postinstall(struct drm_device *dev)
3808 {
3809 struct drm_i915_private *dev_priv = dev->dev_private;
3810 u32 enable_mask;
3811
3812 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3813
3814 /* Unmask the interrupts that we always want on. */
3815 dev_priv->irq_mask =
3816 ~(I915_ASLE_INTERRUPT |
3817 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3818 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3819 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3820 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3821 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3822
3823 enable_mask =
3824 I915_ASLE_INTERRUPT |
3825 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3826 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3827 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3828 I915_USER_INTERRUPT;
3829
3830 if (I915_HAS_HOTPLUG(dev)) {
3831 I915_WRITE(PORT_HOTPLUG_EN, 0);
3832 POSTING_READ(PORT_HOTPLUG_EN);
3833
3834 /* Enable in IER... */
3835 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3836 /* and unmask in IMR */
3837 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3838 }
3839
3840 I915_WRITE(IMR, dev_priv->irq_mask);
3841 I915_WRITE(IER, enable_mask);
3842 POSTING_READ(IER);
3843
3844 i915_enable_asle_pipestat(dev);
3845
3846 /* Interrupt setup is already guaranteed to be single-threaded, this is
3847 * just to make the assert_spin_locked check happy. */
3848 spin_lock_irq(&dev_priv->irq_lock);
3849 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3850 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3851 spin_unlock_irq(&dev_priv->irq_lock);
3852
3853 return 0;
3854 }
3855
3856 /*
3857 * Returns true when a page flip has completed.
3858 */
3859 static bool i915_handle_vblank(struct drm_device *dev,
3860 int plane, int pipe, u32 iir)
3861 {
3862 struct drm_i915_private *dev_priv = dev->dev_private;
3863 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3864
3865 if (!intel_pipe_handle_vblank(dev, pipe))
3866 return false;
3867
3868 if ((iir & flip_pending) == 0)
3869 goto check_page_flip;
3870
3871 intel_prepare_page_flip(dev, plane);
3872
3873 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3874 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3875 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3876 * the flip is completed (no longer pending). Since this doesn't raise
3877 * an interrupt per se, we watch for the change at vblank.
3878 */
3879 if (I915_READ(ISR) & flip_pending)
3880 goto check_page_flip;
3881
3882 intel_finish_page_flip(dev, pipe);
3883 return true;
3884
3885 check_page_flip:
3886 intel_check_page_flip(dev, pipe);
3887 return false;
3888 }
3889
3890 static irqreturn_t i915_irq_handler(int irq, void *arg)
3891 {
3892 struct drm_device *dev = arg;
3893 struct drm_i915_private *dev_priv = dev->dev_private;
3894 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3895 u32 flip_mask =
3896 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3897 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3898 int pipe, ret = IRQ_NONE;
3899
3900 iir = I915_READ(IIR);
3901 do {
3902 bool irq_received = (iir & ~flip_mask) != 0;
3903 bool blc_event = false;
3904
3905 /* Can't rely on pipestat interrupt bit in iir as it might
3906 * have been cleared after the pipestat interrupt was received.
3907 * It doesn't set the bit in iir again, but it still produces
3908 * interrupts (for non-MSI).
3909 */
3910 spin_lock(&dev_priv->irq_lock);
3911 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3912 i915_handle_error(dev, false,
3913 "Command parser error, iir 0x%08x",
3914 iir);
3915
3916 for_each_pipe(dev_priv, pipe) {
3917 int reg = PIPESTAT(pipe);
3918 pipe_stats[pipe] = I915_READ(reg);
3919
3920 /* Clear the PIPE*STAT regs before the IIR */
3921 if (pipe_stats[pipe] & 0x8000ffff) {
3922 I915_WRITE(reg, pipe_stats[pipe]);
3923 irq_received = true;
3924 }
3925 }
3926 spin_unlock(&dev_priv->irq_lock);
3927
3928 if (!irq_received)
3929 break;
3930
3931 /* Consume port. Then clear IIR or we'll miss events */
3932 if (I915_HAS_HOTPLUG(dev) &&
3933 iir & I915_DISPLAY_PORT_INTERRUPT)
3934 i9xx_hpd_irq_handler(dev);
3935
3936 I915_WRITE(IIR, iir & ~flip_mask);
3937 new_iir = I915_READ(IIR); /* Flush posted writes */
3938
3939 if (iir & I915_USER_INTERRUPT)
3940 notify_ring(dev, &dev_priv->ring[RCS]);
3941
3942 for_each_pipe(dev_priv, pipe) {
3943 int plane = pipe;
3944 if (HAS_FBC(dev))
3945 plane = !plane;
3946
3947 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3948 i915_handle_vblank(dev, plane, pipe, iir))
3949 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3950
3951 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3952 blc_event = true;
3953
3954 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3955 i9xx_pipe_crc_irq_handler(dev, pipe);
3956
3957 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3958 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3959 pipe);
3960 }
3961
3962 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3963 intel_opregion_asle_intr(dev);
3964
3965 /* With MSI, interrupts are only generated when iir
3966 * transitions from zero to nonzero. If another bit got
3967 * set while we were handling the existing iir bits, then
3968 * we would never get another interrupt.
3969 *
3970 * This is fine on non-MSI as well, as if we hit this path
3971 * we avoid exiting the interrupt handler only to generate
3972 * another one.
3973 *
3974 * Note that for MSI this could cause a stray interrupt report
3975 * if an interrupt landed in the time between writing IIR and
3976 * the posting read. This should be rare enough to never
3977 * trigger the 99% of 100,000 interrupts test for disabling
3978 * stray interrupts.
3979 */
3980 ret = IRQ_HANDLED;
3981 iir = new_iir;
3982 } while (iir & ~flip_mask);
3983
3984 i915_update_dri1_breadcrumb(dev);
3985
3986 return ret;
3987 }
3988
3989 static void i915_irq_uninstall(struct drm_device * dev)
3990 {
3991 struct drm_i915_private *dev_priv = dev->dev_private;
3992 int pipe;
3993
3994 if (I915_HAS_HOTPLUG(dev)) {
3995 I915_WRITE(PORT_HOTPLUG_EN, 0);
3996 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3997 }
3998
3999 I915_WRITE16(HWSTAM, 0xffff);
4000 for_each_pipe(dev_priv, pipe) {
4001 /* Clear enable bits; then clear status bits */
4002 I915_WRITE(PIPESTAT(pipe), 0);
4003 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4004 }
4005 I915_WRITE(IMR, 0xffffffff);
4006 I915_WRITE(IER, 0x0);
4007
4008 I915_WRITE(IIR, I915_READ(IIR));
4009 }
4010
4011 static void i965_irq_preinstall(struct drm_device * dev)
4012 {
4013 struct drm_i915_private *dev_priv = dev->dev_private;
4014 int pipe;
4015
4016 I915_WRITE(PORT_HOTPLUG_EN, 0);
4017 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4018
4019 I915_WRITE(HWSTAM, 0xeffe);
4020 for_each_pipe(dev_priv, pipe)
4021 I915_WRITE(PIPESTAT(pipe), 0);
4022 I915_WRITE(IMR, 0xffffffff);
4023 I915_WRITE(IER, 0x0);
4024 POSTING_READ(IER);
4025 }
4026
4027 static int i965_irq_postinstall(struct drm_device *dev)
4028 {
4029 struct drm_i915_private *dev_priv = dev->dev_private;
4030 u32 enable_mask;
4031 u32 error_mask;
4032
4033 /* Unmask the interrupts that we always want on. */
4034 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4035 I915_DISPLAY_PORT_INTERRUPT |
4036 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4037 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4038 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4039 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4040 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4041
4042 enable_mask = ~dev_priv->irq_mask;
4043 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4044 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4045 enable_mask |= I915_USER_INTERRUPT;
4046
4047 if (IS_G4X(dev))
4048 enable_mask |= I915_BSD_USER_INTERRUPT;
4049
4050 /* Interrupt setup is already guaranteed to be single-threaded, this is
4051 * just to make the assert_spin_locked check happy. */
4052 spin_lock_irq(&dev_priv->irq_lock);
4053 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4054 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4055 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4056 spin_unlock_irq(&dev_priv->irq_lock);
4057
4058 /*
4059 * Enable some error detection, note the instruction error mask
4060 * bit is reserved, so we leave it masked.
4061 */
4062 if (IS_G4X(dev)) {
4063 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4064 GM45_ERROR_MEM_PRIV |
4065 GM45_ERROR_CP_PRIV |
4066 I915_ERROR_MEMORY_REFRESH);
4067 } else {
4068 error_mask = ~(I915_ERROR_PAGE_TABLE |
4069 I915_ERROR_MEMORY_REFRESH);
4070 }
4071 I915_WRITE(EMR, error_mask);
4072
4073 I915_WRITE(IMR, dev_priv->irq_mask);
4074 I915_WRITE(IER, enable_mask);
4075 POSTING_READ(IER);
4076
4077 I915_WRITE(PORT_HOTPLUG_EN, 0);
4078 POSTING_READ(PORT_HOTPLUG_EN);
4079
4080 i915_enable_asle_pipestat(dev);
4081
4082 return 0;
4083 }
4084
4085 static void i915_hpd_irq_setup(struct drm_device *dev)
4086 {
4087 struct drm_i915_private *dev_priv = dev->dev_private;
4088 struct intel_encoder *intel_encoder;
4089 u32 hotplug_en;
4090
4091 assert_spin_locked(&dev_priv->irq_lock);
4092
4093 if (I915_HAS_HOTPLUG(dev)) {
4094 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
4095 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
4096 /* Note HDMI and DP share hotplug bits */
4097 /* enable bits are the same for all generations */
4098 for_each_intel_encoder(dev, intel_encoder)
4099 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
4100 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
4101 /* Programming the CRT detection parameters tends
4102 to generate a spurious hotplug event about three
4103 seconds later. So just do it once.
4104 */
4105 if (IS_G4X(dev))
4106 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4107 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
4108 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4109
4110 /* Ignore TV since it's buggy */
4111 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
4112 }
4113 }
4114
4115 static irqreturn_t i965_irq_handler(int irq, void *arg)
4116 {
4117 struct drm_device *dev = arg;
4118 struct drm_i915_private *dev_priv = dev->dev_private;
4119 u32 iir, new_iir;
4120 u32 pipe_stats[I915_MAX_PIPES];
4121 int ret = IRQ_NONE, pipe;
4122 u32 flip_mask =
4123 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4124 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4125
4126 iir = I915_READ(IIR);
4127
4128 for (;;) {
4129 bool irq_received = (iir & ~flip_mask) != 0;
4130 bool blc_event = false;
4131
4132 /* Can't rely on pipestat interrupt bit in iir as it might
4133 * have been cleared after the pipestat interrupt was received.
4134 * It doesn't set the bit in iir again, but it still produces
4135 * interrupts (for non-MSI).
4136 */
4137 spin_lock(&dev_priv->irq_lock);
4138 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4139 i915_handle_error(dev, false,
4140 "Command parser error, iir 0x%08x",
4141 iir);
4142
4143 for_each_pipe(dev_priv, pipe) {
4144 int reg = PIPESTAT(pipe);
4145 pipe_stats[pipe] = I915_READ(reg);
4146
4147 /*
4148 * Clear the PIPE*STAT regs before the IIR
4149 */
4150 if (pipe_stats[pipe] & 0x8000ffff) {
4151 I915_WRITE(reg, pipe_stats[pipe]);
4152 irq_received = true;
4153 }
4154 }
4155 spin_unlock(&dev_priv->irq_lock);
4156
4157 if (!irq_received)
4158 break;
4159
4160 ret = IRQ_HANDLED;
4161
4162 /* Consume port. Then clear IIR or we'll miss events */
4163 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4164 i9xx_hpd_irq_handler(dev);
4165
4166 I915_WRITE(IIR, iir & ~flip_mask);
4167 new_iir = I915_READ(IIR); /* Flush posted writes */
4168
4169 if (iir & I915_USER_INTERRUPT)
4170 notify_ring(dev, &dev_priv->ring[RCS]);
4171 if (iir & I915_BSD_USER_INTERRUPT)
4172 notify_ring(dev, &dev_priv->ring[VCS]);
4173
4174 for_each_pipe(dev_priv, pipe) {
4175 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4176 i915_handle_vblank(dev, pipe, pipe, iir))
4177 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4178
4179 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4180 blc_event = true;
4181
4182 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4183 i9xx_pipe_crc_irq_handler(dev, pipe);
4184
4185 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4186 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4187 }
4188
4189 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4190 intel_opregion_asle_intr(dev);
4191
4192 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4193 gmbus_irq_handler(dev);
4194
4195 /* With MSI, interrupts are only generated when iir
4196 * transitions from zero to nonzero. If another bit got
4197 * set while we were handling the existing iir bits, then
4198 * we would never get another interrupt.
4199 *
4200 * This is fine on non-MSI as well, as if we hit this path
4201 * we avoid exiting the interrupt handler only to generate
4202 * another one.
4203 *
4204 * Note that for MSI this could cause a stray interrupt report
4205 * if an interrupt landed in the time between writing IIR and
4206 * the posting read. This should be rare enough to never
4207 * trigger the 99% of 100,000 interrupts test for disabling
4208 * stray interrupts.
4209 */
4210 iir = new_iir;
4211 }
4212
4213 i915_update_dri1_breadcrumb(dev);
4214
4215 return ret;
4216 }
4217
4218 static void i965_irq_uninstall(struct drm_device * dev)
4219 {
4220 struct drm_i915_private *dev_priv = dev->dev_private;
4221 int pipe;
4222
4223 if (!dev_priv)
4224 return;
4225
4226 I915_WRITE(PORT_HOTPLUG_EN, 0);
4227 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4228
4229 I915_WRITE(HWSTAM, 0xffffffff);
4230 for_each_pipe(dev_priv, pipe)
4231 I915_WRITE(PIPESTAT(pipe), 0);
4232 I915_WRITE(IMR, 0xffffffff);
4233 I915_WRITE(IER, 0x0);
4234
4235 for_each_pipe(dev_priv, pipe)
4236 I915_WRITE(PIPESTAT(pipe),
4237 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4238 I915_WRITE(IIR, I915_READ(IIR));
4239 }
4240
4241 static void intel_hpd_irq_reenable_work(struct work_struct *work)
4242 {
4243 struct drm_i915_private *dev_priv =
4244 container_of(work, typeof(*dev_priv),
4245 hotplug_reenable_work.work);
4246 struct drm_device *dev = dev_priv->dev;
4247 struct drm_mode_config *mode_config = &dev->mode_config;
4248 int i;
4249
4250 intel_runtime_pm_get(dev_priv);
4251
4252 spin_lock_irq(&dev_priv->irq_lock);
4253 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
4254 struct drm_connector *connector;
4255
4256 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
4257 continue;
4258
4259 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4260
4261 list_for_each_entry(connector, &mode_config->connector_list, head) {
4262 struct intel_connector *intel_connector = to_intel_connector(connector);
4263
4264 if (intel_connector->encoder->hpd_pin == i) {
4265 if (connector->polled != intel_connector->polled)
4266 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
4267 connector->name);
4268 connector->polled = intel_connector->polled;
4269 if (!connector->polled)
4270 connector->polled = DRM_CONNECTOR_POLL_HPD;
4271 }
4272 }
4273 }
4274 if (dev_priv->display.hpd_irq_setup)
4275 dev_priv->display.hpd_irq_setup(dev);
4276 spin_unlock_irq(&dev_priv->irq_lock);
4277
4278 intel_runtime_pm_put(dev_priv);
4279 }
4280
4281 /**
4282 * intel_irq_init - initializes irq support
4283 * @dev_priv: i915 device instance
4284 *
4285 * This function initializes all the irq support including work items, timers
4286 * and all the vtables. It does not setup the interrupt itself though.
4287 */
4288 void intel_irq_init(struct drm_i915_private *dev_priv)
4289 {
4290 struct drm_device *dev = dev_priv->dev;
4291
4292 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
4293 INIT_WORK(&dev_priv->dig_port_work, i915_digport_work_func);
4294 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
4295 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4296 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4297
4298 /* Let's track the enabled rps events */
4299 if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
4300 /* WaGsvRC0ResidencyMethod:vlv */
4301 dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
4302 else
4303 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4304
4305 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
4306 i915_hangcheck_elapsed,
4307 (unsigned long) dev);
4308 INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work,
4309 intel_hpd_irq_reenable_work);
4310
4311 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4312
4313 if (IS_GEN2(dev_priv)) {
4314 dev->max_vblank_count = 0;
4315 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4316 } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4317 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4318 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
4319 } else {
4320 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4321 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4322 }
4323
4324 /*
4325 * Opt out of the vblank disable timer on everything except gen2.
4326 * Gen2 doesn't have a hardware frame counter and so depends on
4327 * vblank interrupts to produce sane vblank seuquence numbers.
4328 */
4329 if (!IS_GEN2(dev_priv))
4330 dev->vblank_disable_immediate = true;
4331
4332 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
4333 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4334 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4335 }
4336
4337 if (IS_CHERRYVIEW(dev_priv)) {
4338 dev->driver->irq_handler = cherryview_irq_handler;
4339 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4340 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4341 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4342 dev->driver->enable_vblank = valleyview_enable_vblank;
4343 dev->driver->disable_vblank = valleyview_disable_vblank;
4344 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4345 } else if (IS_VALLEYVIEW(dev_priv)) {
4346 dev->driver->irq_handler = valleyview_irq_handler;
4347 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4348 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4349 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4350 dev->driver->enable_vblank = valleyview_enable_vblank;
4351 dev->driver->disable_vblank = valleyview_disable_vblank;
4352 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4353 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
4354 dev->driver->irq_handler = gen8_irq_handler;
4355 dev->driver->irq_preinstall = gen8_irq_reset;
4356 dev->driver->irq_postinstall = gen8_irq_postinstall;
4357 dev->driver->irq_uninstall = gen8_irq_uninstall;
4358 dev->driver->enable_vblank = gen8_enable_vblank;
4359 dev->driver->disable_vblank = gen8_disable_vblank;
4360 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4361 } else if (HAS_PCH_SPLIT(dev)) {
4362 dev->driver->irq_handler = ironlake_irq_handler;
4363 dev->driver->irq_preinstall = ironlake_irq_reset;
4364 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4365 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4366 dev->driver->enable_vblank = ironlake_enable_vblank;
4367 dev->driver->disable_vblank = ironlake_disable_vblank;
4368 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4369 } else {
4370 if (INTEL_INFO(dev_priv)->gen == 2) {
4371 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4372 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4373 dev->driver->irq_handler = i8xx_irq_handler;
4374 dev->driver->irq_uninstall = i8xx_irq_uninstall;
4375 } else if (INTEL_INFO(dev_priv)->gen == 3) {
4376 dev->driver->irq_preinstall = i915_irq_preinstall;
4377 dev->driver->irq_postinstall = i915_irq_postinstall;
4378 dev->driver->irq_uninstall = i915_irq_uninstall;
4379 dev->driver->irq_handler = i915_irq_handler;
4380 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4381 } else {
4382 dev->driver->irq_preinstall = i965_irq_preinstall;
4383 dev->driver->irq_postinstall = i965_irq_postinstall;
4384 dev->driver->irq_uninstall = i965_irq_uninstall;
4385 dev->driver->irq_handler = i965_irq_handler;
4386 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4387 }
4388 dev->driver->enable_vblank = i915_enable_vblank;
4389 dev->driver->disable_vblank = i915_disable_vblank;
4390 }
4391 }
4392
4393 /**
4394 * intel_hpd_init - initializes and enables hpd support
4395 * @dev_priv: i915 device instance
4396 *
4397 * This function enables the hotplug support. It requires that interrupts have
4398 * already been enabled with intel_irq_init_hw(). From this point on hotplug and
4399 * poll request can run concurrently to other code, so locking rules must be
4400 * obeyed.
4401 *
4402 * This is a separate step from interrupt enabling to simplify the locking rules
4403 * in the driver load and resume code.
4404 */
4405 void intel_hpd_init(struct drm_i915_private *dev_priv)
4406 {
4407 struct drm_device *dev = dev_priv->dev;
4408 struct drm_mode_config *mode_config = &dev->mode_config;
4409 struct drm_connector *connector;
4410 int i;
4411
4412 for (i = 1; i < HPD_NUM_PINS; i++) {
4413 dev_priv->hpd_stats[i].hpd_cnt = 0;
4414 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4415 }
4416 list_for_each_entry(connector, &mode_config->connector_list, head) {
4417 struct intel_connector *intel_connector = to_intel_connector(connector);
4418 connector->polled = intel_connector->polled;
4419 if (connector->encoder && !connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
4420 connector->polled = DRM_CONNECTOR_POLL_HPD;
4421 if (intel_connector->mst_port)
4422 connector->polled = DRM_CONNECTOR_POLL_HPD;
4423 }
4424
4425 /* Interrupt setup is already guaranteed to be single-threaded, this is
4426 * just to make the assert_spin_locked checks happy. */
4427 spin_lock_irq(&dev_priv->irq_lock);
4428 if (dev_priv->display.hpd_irq_setup)
4429 dev_priv->display.hpd_irq_setup(dev);
4430 spin_unlock_irq(&dev_priv->irq_lock);
4431 }
4432
4433 /**
4434 * intel_irq_install - enables the hardware interrupt
4435 * @dev_priv: i915 device instance
4436 *
4437 * This function enables the hardware interrupt handling, but leaves the hotplug
4438 * handling still disabled. It is called after intel_irq_init().
4439 *
4440 * In the driver load and resume code we need working interrupts in a few places
4441 * but don't want to deal with the hassle of concurrent probe and hotplug
4442 * workers. Hence the split into this two-stage approach.
4443 */
4444 int intel_irq_install(struct drm_i915_private *dev_priv)
4445 {
4446 /*
4447 * We enable some interrupt sources in our postinstall hooks, so mark
4448 * interrupts as enabled _before_ actually enabling them to avoid
4449 * special cases in our ordering checks.
4450 */
4451 dev_priv->pm.irqs_enabled = true;
4452
4453 return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
4454 }
4455
4456 /**
4457 * intel_irq_uninstall - finilizes all irq handling
4458 * @dev_priv: i915 device instance
4459 *
4460 * This stops interrupt and hotplug handling and unregisters and frees all
4461 * resources acquired in the init functions.
4462 */
4463 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4464 {
4465 drm_irq_uninstall(dev_priv->dev);
4466 intel_hpd_cancel_work(dev_priv);
4467 dev_priv->pm.irqs_enabled = false;
4468 }
4469
4470 /**
4471 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4472 * @dev_priv: i915 device instance
4473 *
4474 * This function is used to disable interrupts at runtime, both in the runtime
4475 * pm and the system suspend/resume code.
4476 */
4477 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4478 {
4479 dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
4480 dev_priv->pm.irqs_enabled = false;
4481 }
4482
4483 /**
4484 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4485 * @dev_priv: i915 device instance
4486 *
4487 * This function is used to enable interrupts at runtime, both in the runtime
4488 * pm and the system suspend/resume code.
4489 */
4490 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4491 {
4492 dev_priv->pm.irqs_enabled = true;
4493 dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
4494 dev_priv->dev->driver->irq_postinstall(dev_priv->dev);
4495 }
Linux kernel - Deliverables
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