1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
34 #include <drm/i915_drm.h>
36 #include "i915_trace.h"
37 #include "intel_drv.h"
39 /* For display hotplug interrupt */
41 ironlake_enable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
43 if ((dev_priv
->irq_mask
& mask
) != 0) {
44 dev_priv
->irq_mask
&= ~mask
;
45 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
51 ironlake_disable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
53 if ((dev_priv
->irq_mask
& mask
) != mask
) {
54 dev_priv
->irq_mask
|= mask
;
55 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
61 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
63 if ((dev_priv
->pipestat
[pipe
] & mask
) != mask
) {
64 u32 reg
= PIPESTAT(pipe
);
66 dev_priv
->pipestat
[pipe
] |= mask
;
67 /* Enable the interrupt, clear any pending status */
68 I915_WRITE(reg
, dev_priv
->pipestat
[pipe
] | (mask
>> 16));
74 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
76 if ((dev_priv
->pipestat
[pipe
] & mask
) != 0) {
77 u32 reg
= PIPESTAT(pipe
);
79 dev_priv
->pipestat
[pipe
] &= ~mask
;
80 I915_WRITE(reg
, dev_priv
->pipestat
[pipe
]);
86 * intel_enable_asle - enable ASLE interrupt for OpRegion
88 void intel_enable_asle(struct drm_device
*dev
)
90 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
91 unsigned long irqflags
;
93 /* FIXME: opregion/asle for VLV */
94 if (IS_VALLEYVIEW(dev
))
97 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
99 if (HAS_PCH_SPLIT(dev
))
100 ironlake_enable_display_irq(dev_priv
, DE_GSE
);
102 i915_enable_pipestat(dev_priv
, 1,
103 PIPE_LEGACY_BLC_EVENT_ENABLE
);
104 if (INTEL_INFO(dev
)->gen
>= 4)
105 i915_enable_pipestat(dev_priv
, 0,
106 PIPE_LEGACY_BLC_EVENT_ENABLE
);
109 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
113 * i915_pipe_enabled - check if a pipe is enabled
115 * @pipe: pipe to check
117 * Reading certain registers when the pipe is disabled can hang the chip.
118 * Use this routine to make sure the PLL is running and the pipe is active
119 * before reading such registers if unsure.
122 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
124 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
125 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
128 return I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_ENABLE
;
131 /* Called from drm generic code, passed a 'crtc', which
132 * we use as a pipe index
134 static u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
136 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
137 unsigned long high_frame
;
138 unsigned long low_frame
;
139 u32 high1
, high2
, low
;
141 if (!i915_pipe_enabled(dev
, pipe
)) {
142 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
143 "pipe %c\n", pipe_name(pipe
));
147 high_frame
= PIPEFRAME(pipe
);
148 low_frame
= PIPEFRAMEPIXEL(pipe
);
151 * High & low register fields aren't synchronized, so make sure
152 * we get a low value that's stable across two reads of the high
156 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
157 low
= I915_READ(low_frame
) & PIPE_FRAME_LOW_MASK
;
158 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
159 } while (high1
!= high2
);
161 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
162 low
>>= PIPE_FRAME_LOW_SHIFT
;
163 return (high1
<< 8) | low
;
166 static u32
gm45_get_vblank_counter(struct drm_device
*dev
, int pipe
)
168 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
169 int reg
= PIPE_FRMCOUNT_GM45(pipe
);
171 if (!i915_pipe_enabled(dev
, pipe
)) {
172 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
173 "pipe %c\n", pipe_name(pipe
));
177 return I915_READ(reg
);
180 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, int pipe
,
181 int *vpos
, int *hpos
)
183 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
184 u32 vbl
= 0, position
= 0;
185 int vbl_start
, vbl_end
, htotal
, vtotal
;
188 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
191 if (!i915_pipe_enabled(dev
, pipe
)) {
192 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
193 "pipe %c\n", pipe_name(pipe
));
198 vtotal
= 1 + ((I915_READ(VTOTAL(cpu_transcoder
)) >> 16) & 0x1fff);
200 if (INTEL_INFO(dev
)->gen
>= 4) {
201 /* No obvious pixelcount register. Only query vertical
202 * scanout position from Display scan line register.
204 position
= I915_READ(PIPEDSL(pipe
));
206 /* Decode into vertical scanout position. Don't have
207 * horizontal scanout position.
209 *vpos
= position
& 0x1fff;
212 /* Have access to pixelcount since start of frame.
213 * We can split this into vertical and horizontal
216 position
= (I915_READ(PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
218 htotal
= 1 + ((I915_READ(HTOTAL(cpu_transcoder
)) >> 16) & 0x1fff);
219 *vpos
= position
/ htotal
;
220 *hpos
= position
- (*vpos
* htotal
);
223 /* Query vblank area. */
224 vbl
= I915_READ(VBLANK(cpu_transcoder
));
226 /* Test position against vblank region. */
227 vbl_start
= vbl
& 0x1fff;
228 vbl_end
= (vbl
>> 16) & 0x1fff;
230 if ((*vpos
< vbl_start
) || (*vpos
> vbl_end
))
233 /* Inside "upper part" of vblank area? Apply corrective offset: */
234 if (in_vbl
&& (*vpos
>= vbl_start
))
235 *vpos
= *vpos
- vtotal
;
237 /* Readouts valid? */
239 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
243 ret
|= DRM_SCANOUTPOS_INVBL
;
248 static int i915_get_vblank_timestamp(struct drm_device
*dev
, int pipe
,
250 struct timeval
*vblank_time
,
253 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
254 struct drm_crtc
*crtc
;
256 if (pipe
< 0 || pipe
>= dev_priv
->num_pipe
) {
257 DRM_ERROR("Invalid crtc %d\n", pipe
);
261 /* Get drm_crtc to timestamp: */
262 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
264 DRM_ERROR("Invalid crtc %d\n", pipe
);
268 if (!crtc
->enabled
) {
269 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
273 /* Helper routine in DRM core does all the work: */
274 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
280 * Handle hotplug events outside the interrupt handler proper.
282 static void i915_hotplug_work_func(struct work_struct
*work
)
284 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
286 struct drm_device
*dev
= dev_priv
->dev
;
287 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
288 struct intel_encoder
*encoder
;
290 mutex_lock(&mode_config
->mutex
);
291 DRM_DEBUG_KMS("running encoder hotplug functions\n");
293 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
)
294 if (encoder
->hot_plug
)
295 encoder
->hot_plug(encoder
);
297 mutex_unlock(&mode_config
->mutex
);
299 /* Just fire off a uevent and let userspace tell us what to do */
300 drm_helper_hpd_irq_event(dev
);
303 /* defined intel_pm.c */
304 extern spinlock_t mchdev_lock
;
306 static void ironlake_handle_rps_change(struct drm_device
*dev
)
308 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
309 u32 busy_up
, busy_down
, max_avg
, min_avg
;
313 spin_lock_irqsave(&mchdev_lock
, flags
);
315 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
317 new_delay
= dev_priv
->ips
.cur_delay
;
319 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
320 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
321 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
322 max_avg
= I915_READ(RCBMAXAVG
);
323 min_avg
= I915_READ(RCBMINAVG
);
325 /* Handle RCS change request from hw */
326 if (busy_up
> max_avg
) {
327 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
328 new_delay
= dev_priv
->ips
.cur_delay
- 1;
329 if (new_delay
< dev_priv
->ips
.max_delay
)
330 new_delay
= dev_priv
->ips
.max_delay
;
331 } else if (busy_down
< min_avg
) {
332 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
333 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
334 if (new_delay
> dev_priv
->ips
.min_delay
)
335 new_delay
= dev_priv
->ips
.min_delay
;
338 if (ironlake_set_drps(dev
, new_delay
))
339 dev_priv
->ips
.cur_delay
= new_delay
;
341 spin_unlock_irqrestore(&mchdev_lock
, flags
);
346 static void notify_ring(struct drm_device
*dev
,
347 struct intel_ring_buffer
*ring
)
349 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
351 if (ring
->obj
== NULL
)
354 trace_i915_gem_request_complete(ring
, ring
->get_seqno(ring
, false));
356 wake_up_all(&ring
->irq_queue
);
357 if (i915_enable_hangcheck
) {
358 dev_priv
->hangcheck_count
= 0;
359 mod_timer(&dev_priv
->hangcheck_timer
,
360 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
364 static void gen6_pm_rps_work(struct work_struct
*work
)
366 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
371 spin_lock_irq(&dev_priv
->rps
.lock
);
372 pm_iir
= dev_priv
->rps
.pm_iir
;
373 dev_priv
->rps
.pm_iir
= 0;
374 pm_imr
= I915_READ(GEN6_PMIMR
);
375 I915_WRITE(GEN6_PMIMR
, 0);
376 spin_unlock_irq(&dev_priv
->rps
.lock
);
378 if ((pm_iir
& GEN6_PM_DEFERRED_EVENTS
) == 0)
381 mutex_lock(&dev_priv
->rps
.hw_lock
);
383 if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
)
384 new_delay
= dev_priv
->rps
.cur_delay
+ 1;
386 new_delay
= dev_priv
->rps
.cur_delay
- 1;
388 /* sysfs frequency interfaces may have snuck in while servicing the
391 if (!(new_delay
> dev_priv
->rps
.max_delay
||
392 new_delay
< dev_priv
->rps
.min_delay
)) {
393 gen6_set_rps(dev_priv
->dev
, new_delay
);
396 mutex_unlock(&dev_priv
->rps
.hw_lock
);
401 * ivybridge_parity_work - Workqueue called when a parity error interrupt
403 * @work: workqueue struct
405 * Doesn't actually do anything except notify userspace. As a consequence of
406 * this event, userspace should try to remap the bad rows since statistically
407 * it is likely the same row is more likely to go bad again.
409 static void ivybridge_parity_work(struct work_struct
*work
)
411 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
412 l3_parity
.error_work
);
413 u32 error_status
, row
, bank
, subbank
;
414 char *parity_event
[5];
418 /* We must turn off DOP level clock gating to access the L3 registers.
419 * In order to prevent a get/put style interface, acquire struct mutex
420 * any time we access those registers.
422 mutex_lock(&dev_priv
->dev
->struct_mutex
);
424 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
425 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
426 POSTING_READ(GEN7_MISCCPCTL
);
428 error_status
= I915_READ(GEN7_L3CDERRST1
);
429 row
= GEN7_PARITY_ERROR_ROW(error_status
);
430 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
431 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
433 I915_WRITE(GEN7_L3CDERRST1
, GEN7_PARITY_ERROR_VALID
|
434 GEN7_L3CDERRST1_ENABLE
);
435 POSTING_READ(GEN7_L3CDERRST1
);
437 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
439 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
440 dev_priv
->gt_irq_mask
&= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT
;
441 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
442 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
444 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
446 parity_event
[0] = "L3_PARITY_ERROR=1";
447 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
448 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
449 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
450 parity_event
[4] = NULL
;
452 kobject_uevent_env(&dev_priv
->dev
->primary
->kdev
.kobj
,
453 KOBJ_CHANGE
, parity_event
);
455 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
458 kfree(parity_event
[3]);
459 kfree(parity_event
[2]);
460 kfree(parity_event
[1]);
463 static void ivybridge_handle_parity_error(struct drm_device
*dev
)
465 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
468 if (!HAS_L3_GPU_CACHE(dev
))
471 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
472 dev_priv
->gt_irq_mask
|= GT_GEN7_L3_PARITY_ERROR_INTERRUPT
;
473 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
474 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
476 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
479 static void snb_gt_irq_handler(struct drm_device
*dev
,
480 struct drm_i915_private
*dev_priv
,
484 if (gt_iir
& (GEN6_RENDER_USER_INTERRUPT
|
485 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT
))
486 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
487 if (gt_iir
& GEN6_BSD_USER_INTERRUPT
)
488 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
489 if (gt_iir
& GEN6_BLITTER_USER_INTERRUPT
)
490 notify_ring(dev
, &dev_priv
->ring
[BCS
]);
492 if (gt_iir
& (GT_GEN6_BLT_CS_ERROR_INTERRUPT
|
493 GT_GEN6_BSD_CS_ERROR_INTERRUPT
|
494 GT_RENDER_CS_ERROR_INTERRUPT
)) {
495 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir
);
496 i915_handle_error(dev
, false);
499 if (gt_iir
& GT_GEN7_L3_PARITY_ERROR_INTERRUPT
)
500 ivybridge_handle_parity_error(dev
);
503 static void gen6_queue_rps_work(struct drm_i915_private
*dev_priv
,
509 * IIR bits should never already be set because IMR should
510 * prevent an interrupt from being shown in IIR. The warning
511 * displays a case where we've unsafely cleared
512 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
513 * type is not a problem, it displays a problem in the logic.
515 * The mask bit in IMR is cleared by dev_priv->rps.work.
518 spin_lock_irqsave(&dev_priv
->rps
.lock
, flags
);
519 dev_priv
->rps
.pm_iir
|= pm_iir
;
520 I915_WRITE(GEN6_PMIMR
, dev_priv
->rps
.pm_iir
);
521 POSTING_READ(GEN6_PMIMR
);
522 spin_unlock_irqrestore(&dev_priv
->rps
.lock
, flags
);
524 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
527 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
529 struct drm_device
*dev
= (struct drm_device
*) arg
;
530 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
531 u32 iir
, gt_iir
, pm_iir
;
532 irqreturn_t ret
= IRQ_NONE
;
533 unsigned long irqflags
;
535 u32 pipe_stats
[I915_MAX_PIPES
];
538 atomic_inc(&dev_priv
->irq_received
);
541 iir
= I915_READ(VLV_IIR
);
542 gt_iir
= I915_READ(GTIIR
);
543 pm_iir
= I915_READ(GEN6_PMIIR
);
545 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
550 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
552 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
553 for_each_pipe(pipe
) {
554 int reg
= PIPESTAT(pipe
);
555 pipe_stats
[pipe
] = I915_READ(reg
);
558 * Clear the PIPE*STAT regs before the IIR
560 if (pipe_stats
[pipe
] & 0x8000ffff) {
561 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
562 DRM_DEBUG_DRIVER("pipe %c underrun\n",
564 I915_WRITE(reg
, pipe_stats
[pipe
]);
567 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
569 for_each_pipe(pipe
) {
570 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
)
571 drm_handle_vblank(dev
, pipe
);
573 if (pipe_stats
[pipe
] & PLANE_FLIPDONE_INT_STATUS_VLV
) {
574 intel_prepare_page_flip(dev
, pipe
);
575 intel_finish_page_flip(dev
, pipe
);
579 /* Consume port. Then clear IIR or we'll miss events */
580 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
581 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
583 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
585 if (hotplug_status
& dev_priv
->hotplug_supported_mask
)
586 queue_work(dev_priv
->wq
,
587 &dev_priv
->hotplug_work
);
589 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
590 I915_READ(PORT_HOTPLUG_STAT
);
593 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
596 if (pm_iir
& GEN6_PM_DEFERRED_EVENTS
)
597 gen6_queue_rps_work(dev_priv
, pm_iir
);
599 I915_WRITE(GTIIR
, gt_iir
);
600 I915_WRITE(GEN6_PMIIR
, pm_iir
);
601 I915_WRITE(VLV_IIR
, iir
);
608 static void ibx_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
610 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
613 if (pch_iir
& SDE_HOTPLUG_MASK
)
614 queue_work(dev_priv
->wq
, &dev_priv
->hotplug_work
);
616 if (pch_iir
& SDE_AUDIO_POWER_MASK
)
617 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
618 (pch_iir
& SDE_AUDIO_POWER_MASK
) >>
619 SDE_AUDIO_POWER_SHIFT
);
621 if (pch_iir
& SDE_GMBUS
)
622 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
624 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
625 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
627 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
628 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
630 if (pch_iir
& SDE_POISON
)
631 DRM_ERROR("PCH poison interrupt\n");
633 if (pch_iir
& SDE_FDI_MASK
)
635 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
637 I915_READ(FDI_RX_IIR(pipe
)));
639 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
640 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
642 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
643 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
645 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
646 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
647 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
648 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
651 static void cpt_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
653 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
656 if (pch_iir
& SDE_HOTPLUG_MASK_CPT
)
657 queue_work(dev_priv
->wq
, &dev_priv
->hotplug_work
);
659 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
)
660 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
661 (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
662 SDE_AUDIO_POWER_SHIFT_CPT
);
664 if (pch_iir
& SDE_AUX_MASK_CPT
)
665 DRM_DEBUG_DRIVER("AUX channel interrupt\n");
667 if (pch_iir
& SDE_GMBUS_CPT
)
668 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
670 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
671 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
673 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
674 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
676 if (pch_iir
& SDE_FDI_MASK_CPT
)
678 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
680 I915_READ(FDI_RX_IIR(pipe
)));
683 static irqreturn_t
ivybridge_irq_handler(int irq
, void *arg
)
685 struct drm_device
*dev
= (struct drm_device
*) arg
;
686 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
687 u32 de_iir
, gt_iir
, de_ier
, pm_iir
;
688 irqreturn_t ret
= IRQ_NONE
;
691 atomic_inc(&dev_priv
->irq_received
);
693 /* disable master interrupt before clearing iir */
694 de_ier
= I915_READ(DEIER
);
695 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
697 gt_iir
= I915_READ(GTIIR
);
699 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
700 I915_WRITE(GTIIR
, gt_iir
);
704 de_iir
= I915_READ(DEIIR
);
706 if (de_iir
& DE_GSE_IVB
)
707 intel_opregion_gse_intr(dev
);
709 for (i
= 0; i
< 3; i
++) {
710 if (de_iir
& (DE_PIPEA_VBLANK_IVB
<< (5 * i
)))
711 drm_handle_vblank(dev
, i
);
712 if (de_iir
& (DE_PLANEA_FLIP_DONE_IVB
<< (5 * i
))) {
713 intel_prepare_page_flip(dev
, i
);
714 intel_finish_page_flip_plane(dev
, i
);
718 /* check event from PCH */
719 if (de_iir
& DE_PCH_EVENT_IVB
) {
720 u32 pch_iir
= I915_READ(SDEIIR
);
722 cpt_irq_handler(dev
, pch_iir
);
724 /* clear PCH hotplug event before clear CPU irq */
725 I915_WRITE(SDEIIR
, pch_iir
);
728 I915_WRITE(DEIIR
, de_iir
);
732 pm_iir
= I915_READ(GEN6_PMIIR
);
734 if (pm_iir
& GEN6_PM_DEFERRED_EVENTS
)
735 gen6_queue_rps_work(dev_priv
, pm_iir
);
736 I915_WRITE(GEN6_PMIIR
, pm_iir
);
740 I915_WRITE(DEIER
, de_ier
);
746 static void ilk_gt_irq_handler(struct drm_device
*dev
,
747 struct drm_i915_private
*dev_priv
,
750 if (gt_iir
& (GT_USER_INTERRUPT
| GT_PIPE_NOTIFY
))
751 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
752 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
753 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
756 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
758 struct drm_device
*dev
= (struct drm_device
*) arg
;
759 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
761 u32 de_iir
, gt_iir
, de_ier
, pch_iir
, pm_iir
;
763 atomic_inc(&dev_priv
->irq_received
);
765 /* disable master interrupt before clearing iir */
766 de_ier
= I915_READ(DEIER
);
767 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
770 de_iir
= I915_READ(DEIIR
);
771 gt_iir
= I915_READ(GTIIR
);
772 pch_iir
= I915_READ(SDEIIR
);
773 pm_iir
= I915_READ(GEN6_PMIIR
);
775 if (de_iir
== 0 && gt_iir
== 0 && pch_iir
== 0 &&
776 (!IS_GEN6(dev
) || pm_iir
== 0))
782 ilk_gt_irq_handler(dev
, dev_priv
, gt_iir
);
784 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
787 intel_opregion_gse_intr(dev
);
789 if (de_iir
& DE_PIPEA_VBLANK
)
790 drm_handle_vblank(dev
, 0);
792 if (de_iir
& DE_PIPEB_VBLANK
)
793 drm_handle_vblank(dev
, 1);
795 if (de_iir
& DE_PLANEA_FLIP_DONE
) {
796 intel_prepare_page_flip(dev
, 0);
797 intel_finish_page_flip_plane(dev
, 0);
800 if (de_iir
& DE_PLANEB_FLIP_DONE
) {
801 intel_prepare_page_flip(dev
, 1);
802 intel_finish_page_flip_plane(dev
, 1);
805 /* check event from PCH */
806 if (de_iir
& DE_PCH_EVENT
) {
807 if (HAS_PCH_CPT(dev
))
808 cpt_irq_handler(dev
, pch_iir
);
810 ibx_irq_handler(dev
, pch_iir
);
813 if (IS_GEN5(dev
) && de_iir
& DE_PCU_EVENT
)
814 ironlake_handle_rps_change(dev
);
816 if (IS_GEN6(dev
) && pm_iir
& GEN6_PM_DEFERRED_EVENTS
)
817 gen6_queue_rps_work(dev_priv
, pm_iir
);
819 /* should clear PCH hotplug event before clear CPU irq */
820 I915_WRITE(SDEIIR
, pch_iir
);
821 I915_WRITE(GTIIR
, gt_iir
);
822 I915_WRITE(DEIIR
, de_iir
);
823 I915_WRITE(GEN6_PMIIR
, pm_iir
);
826 I915_WRITE(DEIER
, de_ier
);
833 * i915_error_work_func - do process context error handling work
836 * Fire an error uevent so userspace can see that a hang or error
839 static void i915_error_work_func(struct work_struct
*work
)
841 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
843 struct drm_device
*dev
= dev_priv
->dev
;
844 char *error_event
[] = { "ERROR=1", NULL
};
845 char *reset_event
[] = { "RESET=1", NULL
};
846 char *reset_done_event
[] = { "ERROR=0", NULL
};
848 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
, error_event
);
850 if (atomic_read(&dev_priv
->mm
.wedged
)) {
851 DRM_DEBUG_DRIVER("resetting chip\n");
852 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
, reset_event
);
853 if (!i915_reset(dev
)) {
854 atomic_set(&dev_priv
->mm
.wedged
, 0);
855 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
, reset_done_event
);
857 complete_all(&dev_priv
->error_completion
);
861 /* NB: please notice the memset */
862 static void i915_get_extra_instdone(struct drm_device
*dev
,
865 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
866 memset(instdone
, 0, sizeof(*instdone
) * I915_NUM_INSTDONE_REG
);
868 switch(INTEL_INFO(dev
)->gen
) {
871 instdone
[0] = I915_READ(INSTDONE
);
876 instdone
[0] = I915_READ(INSTDONE_I965
);
877 instdone
[1] = I915_READ(INSTDONE1
);
880 WARN_ONCE(1, "Unsupported platform\n");
882 instdone
[0] = I915_READ(GEN7_INSTDONE_1
);
883 instdone
[1] = I915_READ(GEN7_SC_INSTDONE
);
884 instdone
[2] = I915_READ(GEN7_SAMPLER_INSTDONE
);
885 instdone
[3] = I915_READ(GEN7_ROW_INSTDONE
);
890 #ifdef CONFIG_DEBUG_FS
891 static struct drm_i915_error_object
*
892 i915_error_object_create(struct drm_i915_private
*dev_priv
,
893 struct drm_i915_gem_object
*src
)
895 struct drm_i915_error_object
*dst
;
899 if (src
== NULL
|| src
->pages
== NULL
)
902 count
= src
->base
.size
/ PAGE_SIZE
;
904 dst
= kmalloc(sizeof(*dst
) + count
* sizeof(u32
*), GFP_ATOMIC
);
908 reloc_offset
= src
->gtt_offset
;
909 for (i
= 0; i
< count
; i
++) {
913 d
= kmalloc(PAGE_SIZE
, GFP_ATOMIC
);
917 local_irq_save(flags
);
918 if (reloc_offset
< dev_priv
->mm
.gtt_mappable_end
&&
919 src
->has_global_gtt_mapping
) {
922 /* Simply ignore tiling or any overlapping fence.
923 * It's part of the error state, and this hopefully
924 * captures what the GPU read.
927 s
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
929 memcpy_fromio(d
, s
, PAGE_SIZE
);
930 io_mapping_unmap_atomic(s
);
935 page
= i915_gem_object_get_page(src
, i
);
937 drm_clflush_pages(&page
, 1);
939 s
= kmap_atomic(page
);
940 memcpy(d
, s
, PAGE_SIZE
);
943 drm_clflush_pages(&page
, 1);
945 local_irq_restore(flags
);
949 reloc_offset
+= PAGE_SIZE
;
951 dst
->page_count
= count
;
952 dst
->gtt_offset
= src
->gtt_offset
;
958 kfree(dst
->pages
[i
]);
964 i915_error_object_free(struct drm_i915_error_object
*obj
)
971 for (page
= 0; page
< obj
->page_count
; page
++)
972 kfree(obj
->pages
[page
]);
978 i915_error_state_free(struct kref
*error_ref
)
980 struct drm_i915_error_state
*error
= container_of(error_ref
,
981 typeof(*error
), ref
);
984 for (i
= 0; i
< ARRAY_SIZE(error
->ring
); i
++) {
985 i915_error_object_free(error
->ring
[i
].batchbuffer
);
986 i915_error_object_free(error
->ring
[i
].ringbuffer
);
987 kfree(error
->ring
[i
].requests
);
990 kfree(error
->active_bo
);
991 kfree(error
->overlay
);
994 static void capture_bo(struct drm_i915_error_buffer
*err
,
995 struct drm_i915_gem_object
*obj
)
997 err
->size
= obj
->base
.size
;
998 err
->name
= obj
->base
.name
;
999 err
->rseqno
= obj
->last_read_seqno
;
1000 err
->wseqno
= obj
->last_write_seqno
;
1001 err
->gtt_offset
= obj
->gtt_offset
;
1002 err
->read_domains
= obj
->base
.read_domains
;
1003 err
->write_domain
= obj
->base
.write_domain
;
1004 err
->fence_reg
= obj
->fence_reg
;
1006 if (obj
->pin_count
> 0)
1008 if (obj
->user_pin_count
> 0)
1010 err
->tiling
= obj
->tiling_mode
;
1011 err
->dirty
= obj
->dirty
;
1012 err
->purgeable
= obj
->madv
!= I915_MADV_WILLNEED
;
1013 err
->ring
= obj
->ring
? obj
->ring
->id
: -1;
1014 err
->cache_level
= obj
->cache_level
;
1017 static u32
capture_active_bo(struct drm_i915_error_buffer
*err
,
1018 int count
, struct list_head
*head
)
1020 struct drm_i915_gem_object
*obj
;
1023 list_for_each_entry(obj
, head
, mm_list
) {
1024 capture_bo(err
++, obj
);
1032 static u32
capture_pinned_bo(struct drm_i915_error_buffer
*err
,
1033 int count
, struct list_head
*head
)
1035 struct drm_i915_gem_object
*obj
;
1038 list_for_each_entry(obj
, head
, gtt_list
) {
1039 if (obj
->pin_count
== 0)
1042 capture_bo(err
++, obj
);
1050 static void i915_gem_record_fences(struct drm_device
*dev
,
1051 struct drm_i915_error_state
*error
)
1053 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1057 switch (INTEL_INFO(dev
)->gen
) {
1060 for (i
= 0; i
< 16; i
++)
1061 error
->fence
[i
] = I915_READ64(FENCE_REG_SANDYBRIDGE_0
+ (i
* 8));
1065 for (i
= 0; i
< 16; i
++)
1066 error
->fence
[i
] = I915_READ64(FENCE_REG_965_0
+ (i
* 8));
1069 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
1070 for (i
= 0; i
< 8; i
++)
1071 error
->fence
[i
+8] = I915_READ(FENCE_REG_945_8
+ (i
* 4));
1073 for (i
= 0; i
< 8; i
++)
1074 error
->fence
[i
] = I915_READ(FENCE_REG_830_0
+ (i
* 4));
1080 static struct drm_i915_error_object
*
1081 i915_error_first_batchbuffer(struct drm_i915_private
*dev_priv
,
1082 struct intel_ring_buffer
*ring
)
1084 struct drm_i915_gem_object
*obj
;
1087 if (!ring
->get_seqno
)
1090 if (HAS_BROKEN_CS_TLB(dev_priv
->dev
)) {
1091 u32 acthd
= I915_READ(ACTHD
);
1093 if (WARN_ON(ring
->id
!= RCS
))
1096 obj
= ring
->private;
1097 if (acthd
>= obj
->gtt_offset
&&
1098 acthd
< obj
->gtt_offset
+ obj
->base
.size
)
1099 return i915_error_object_create(dev_priv
, obj
);
1102 seqno
= ring
->get_seqno(ring
, false);
1103 list_for_each_entry(obj
, &dev_priv
->mm
.active_list
, mm_list
) {
1104 if (obj
->ring
!= ring
)
1107 if (i915_seqno_passed(seqno
, obj
->last_read_seqno
))
1110 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_COMMAND
) == 0)
1113 /* We need to copy these to an anonymous buffer as the simplest
1114 * method to avoid being overwritten by userspace.
1116 return i915_error_object_create(dev_priv
, obj
);
1122 static void i915_record_ring_state(struct drm_device
*dev
,
1123 struct drm_i915_error_state
*error
,
1124 struct intel_ring_buffer
*ring
)
1126 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1128 if (INTEL_INFO(dev
)->gen
>= 6) {
1129 error
->rc_psmi
[ring
->id
] = I915_READ(ring
->mmio_base
+ 0x50);
1130 error
->fault_reg
[ring
->id
] = I915_READ(RING_FAULT_REG(ring
));
1131 error
->semaphore_mboxes
[ring
->id
][0]
1132 = I915_READ(RING_SYNC_0(ring
->mmio_base
));
1133 error
->semaphore_mboxes
[ring
->id
][1]
1134 = I915_READ(RING_SYNC_1(ring
->mmio_base
));
1135 error
->semaphore_seqno
[ring
->id
][0] = ring
->sync_seqno
[0];
1136 error
->semaphore_seqno
[ring
->id
][1] = ring
->sync_seqno
[1];
1139 if (INTEL_INFO(dev
)->gen
>= 4) {
1140 error
->faddr
[ring
->id
] = I915_READ(RING_DMA_FADD(ring
->mmio_base
));
1141 error
->ipeir
[ring
->id
] = I915_READ(RING_IPEIR(ring
->mmio_base
));
1142 error
->ipehr
[ring
->id
] = I915_READ(RING_IPEHR(ring
->mmio_base
));
1143 error
->instdone
[ring
->id
] = I915_READ(RING_INSTDONE(ring
->mmio_base
));
1144 error
->instps
[ring
->id
] = I915_READ(RING_INSTPS(ring
->mmio_base
));
1145 if (ring
->id
== RCS
)
1146 error
->bbaddr
= I915_READ64(BB_ADDR
);
1148 error
->faddr
[ring
->id
] = I915_READ(DMA_FADD_I8XX
);
1149 error
->ipeir
[ring
->id
] = I915_READ(IPEIR
);
1150 error
->ipehr
[ring
->id
] = I915_READ(IPEHR
);
1151 error
->instdone
[ring
->id
] = I915_READ(INSTDONE
);
1154 error
->waiting
[ring
->id
] = waitqueue_active(&ring
->irq_queue
);
1155 error
->instpm
[ring
->id
] = I915_READ(RING_INSTPM(ring
->mmio_base
));
1156 error
->seqno
[ring
->id
] = ring
->get_seqno(ring
, false);
1157 error
->acthd
[ring
->id
] = intel_ring_get_active_head(ring
);
1158 error
->head
[ring
->id
] = I915_READ_HEAD(ring
);
1159 error
->tail
[ring
->id
] = I915_READ_TAIL(ring
);
1161 error
->cpu_ring_head
[ring
->id
] = ring
->head
;
1162 error
->cpu_ring_tail
[ring
->id
] = ring
->tail
;
1165 static void i915_gem_record_rings(struct drm_device
*dev
,
1166 struct drm_i915_error_state
*error
)
1168 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1169 struct intel_ring_buffer
*ring
;
1170 struct drm_i915_gem_request
*request
;
1173 for_each_ring(ring
, dev_priv
, i
) {
1174 i915_record_ring_state(dev
, error
, ring
);
1176 error
->ring
[i
].batchbuffer
=
1177 i915_error_first_batchbuffer(dev_priv
, ring
);
1179 error
->ring
[i
].ringbuffer
=
1180 i915_error_object_create(dev_priv
, ring
->obj
);
1183 list_for_each_entry(request
, &ring
->request_list
, list
)
1186 error
->ring
[i
].num_requests
= count
;
1187 error
->ring
[i
].requests
=
1188 kmalloc(count
*sizeof(struct drm_i915_error_request
),
1190 if (error
->ring
[i
].requests
== NULL
) {
1191 error
->ring
[i
].num_requests
= 0;
1196 list_for_each_entry(request
, &ring
->request_list
, list
) {
1197 struct drm_i915_error_request
*erq
;
1199 erq
= &error
->ring
[i
].requests
[count
++];
1200 erq
->seqno
= request
->seqno
;
1201 erq
->jiffies
= request
->emitted_jiffies
;
1202 erq
->tail
= request
->tail
;
1208 * i915_capture_error_state - capture an error record for later analysis
1211 * Should be called when an error is detected (either a hang or an error
1212 * interrupt) to capture error state from the time of the error. Fills
1213 * out a structure which becomes available in debugfs for user level tools
1216 static void i915_capture_error_state(struct drm_device
*dev
)
1218 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1219 struct drm_i915_gem_object
*obj
;
1220 struct drm_i915_error_state
*error
;
1221 unsigned long flags
;
1224 spin_lock_irqsave(&dev_priv
->error_lock
, flags
);
1225 error
= dev_priv
->first_error
;
1226 spin_unlock_irqrestore(&dev_priv
->error_lock
, flags
);
1230 /* Account for pipe specific data like PIPE*STAT */
1231 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
1233 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1237 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1238 dev
->primary
->index
);
1240 kref_init(&error
->ref
);
1241 error
->eir
= I915_READ(EIR
);
1242 error
->pgtbl_er
= I915_READ(PGTBL_ER
);
1243 error
->ccid
= I915_READ(CCID
);
1245 if (HAS_PCH_SPLIT(dev
))
1246 error
->ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
1247 else if (IS_VALLEYVIEW(dev
))
1248 error
->ier
= I915_READ(GTIER
) | I915_READ(VLV_IER
);
1249 else if (IS_GEN2(dev
))
1250 error
->ier
= I915_READ16(IER
);
1252 error
->ier
= I915_READ(IER
);
1255 error
->pipestat
[pipe
] = I915_READ(PIPESTAT(pipe
));
1257 if (INTEL_INFO(dev
)->gen
>= 6) {
1258 error
->error
= I915_READ(ERROR_GEN6
);
1259 error
->done_reg
= I915_READ(DONE_REG
);
1262 if (INTEL_INFO(dev
)->gen
== 7)
1263 error
->err_int
= I915_READ(GEN7_ERR_INT
);
1265 i915_get_extra_instdone(dev
, error
->extra_instdone
);
1267 i915_gem_record_fences(dev
, error
);
1268 i915_gem_record_rings(dev
, error
);
1270 /* Record buffers on the active and pinned lists. */
1271 error
->active_bo
= NULL
;
1272 error
->pinned_bo
= NULL
;
1275 list_for_each_entry(obj
, &dev_priv
->mm
.active_list
, mm_list
)
1277 error
->active_bo_count
= i
;
1278 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, gtt_list
)
1281 error
->pinned_bo_count
= i
- error
->active_bo_count
;
1283 error
->active_bo
= NULL
;
1284 error
->pinned_bo
= NULL
;
1286 error
->active_bo
= kmalloc(sizeof(*error
->active_bo
)*i
,
1288 if (error
->active_bo
)
1290 error
->active_bo
+ error
->active_bo_count
;
1293 if (error
->active_bo
)
1294 error
->active_bo_count
=
1295 capture_active_bo(error
->active_bo
,
1296 error
->active_bo_count
,
1297 &dev_priv
->mm
.active_list
);
1299 if (error
->pinned_bo
)
1300 error
->pinned_bo_count
=
1301 capture_pinned_bo(error
->pinned_bo
,
1302 error
->pinned_bo_count
,
1303 &dev_priv
->mm
.bound_list
);
1305 do_gettimeofday(&error
->time
);
1307 error
->overlay
= intel_overlay_capture_error_state(dev
);
1308 error
->display
= intel_display_capture_error_state(dev
);
1310 spin_lock_irqsave(&dev_priv
->error_lock
, flags
);
1311 if (dev_priv
->first_error
== NULL
) {
1312 dev_priv
->first_error
= error
;
1315 spin_unlock_irqrestore(&dev_priv
->error_lock
, flags
);
1318 i915_error_state_free(&error
->ref
);
1321 void i915_destroy_error_state(struct drm_device
*dev
)
1323 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1324 struct drm_i915_error_state
*error
;
1325 unsigned long flags
;
1327 spin_lock_irqsave(&dev_priv
->error_lock
, flags
);
1328 error
= dev_priv
->first_error
;
1329 dev_priv
->first_error
= NULL
;
1330 spin_unlock_irqrestore(&dev_priv
->error_lock
, flags
);
1333 kref_put(&error
->ref
, i915_error_state_free
);
1336 #define i915_capture_error_state(x)
1339 static void i915_report_and_clear_eir(struct drm_device
*dev
)
1341 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1342 uint32_t instdone
[I915_NUM_INSTDONE_REG
];
1343 u32 eir
= I915_READ(EIR
);
1349 pr_err("render error detected, EIR: 0x%08x\n", eir
);
1351 i915_get_extra_instdone(dev
, instdone
);
1354 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
1355 u32 ipeir
= I915_READ(IPEIR_I965
);
1357 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1358 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1359 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
1360 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
1361 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1362 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1363 I915_WRITE(IPEIR_I965
, ipeir
);
1364 POSTING_READ(IPEIR_I965
);
1366 if (eir
& GM45_ERROR_PAGE_TABLE
) {
1367 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1368 pr_err("page table error\n");
1369 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1370 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1371 POSTING_READ(PGTBL_ER
);
1375 if (!IS_GEN2(dev
)) {
1376 if (eir
& I915_ERROR_PAGE_TABLE
) {
1377 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1378 pr_err("page table error\n");
1379 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1380 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1381 POSTING_READ(PGTBL_ER
);
1385 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
1386 pr_err("memory refresh error:\n");
1388 pr_err("pipe %c stat: 0x%08x\n",
1389 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
1390 /* pipestat has already been acked */
1392 if (eir
& I915_ERROR_INSTRUCTION
) {
1393 pr_err("instruction error\n");
1394 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
1395 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
1396 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
1397 if (INTEL_INFO(dev
)->gen
< 4) {
1398 u32 ipeir
= I915_READ(IPEIR
);
1400 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
1401 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
1402 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
1403 I915_WRITE(IPEIR
, ipeir
);
1404 POSTING_READ(IPEIR
);
1406 u32 ipeir
= I915_READ(IPEIR_I965
);
1408 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1409 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1410 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1411 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1412 I915_WRITE(IPEIR_I965
, ipeir
);
1413 POSTING_READ(IPEIR_I965
);
1417 I915_WRITE(EIR
, eir
);
1419 eir
= I915_READ(EIR
);
1422 * some errors might have become stuck,
1425 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
1426 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
1427 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
1432 * i915_handle_error - handle an error interrupt
1435 * Do some basic checking of regsiter state at error interrupt time and
1436 * dump it to the syslog. Also call i915_capture_error_state() to make
1437 * sure we get a record and make it available in debugfs. Fire a uevent
1438 * so userspace knows something bad happened (should trigger collection
1439 * of a ring dump etc.).
1441 void i915_handle_error(struct drm_device
*dev
, bool wedged
)
1443 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1444 struct intel_ring_buffer
*ring
;
1447 i915_capture_error_state(dev
);
1448 i915_report_and_clear_eir(dev
);
1451 INIT_COMPLETION(dev_priv
->error_completion
);
1452 atomic_set(&dev_priv
->mm
.wedged
, 1);
1455 * Wakeup waiting processes so they don't hang
1457 for_each_ring(ring
, dev_priv
, i
)
1458 wake_up_all(&ring
->irq_queue
);
1461 queue_work(dev_priv
->wq
, &dev_priv
->error_work
);
1464 static void i915_pageflip_stall_check(struct drm_device
*dev
, int pipe
)
1466 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1467 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1468 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1469 struct drm_i915_gem_object
*obj
;
1470 struct intel_unpin_work
*work
;
1471 unsigned long flags
;
1472 bool stall_detected
;
1474 /* Ignore early vblank irqs */
1475 if (intel_crtc
== NULL
)
1478 spin_lock_irqsave(&dev
->event_lock
, flags
);
1479 work
= intel_crtc
->unpin_work
;
1482 atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
||
1483 !work
->enable_stall_check
) {
1484 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1485 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1489 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1490 obj
= work
->pending_flip_obj
;
1491 if (INTEL_INFO(dev
)->gen
>= 4) {
1492 int dspsurf
= DSPSURF(intel_crtc
->plane
);
1493 stall_detected
= I915_HI_DISPBASE(I915_READ(dspsurf
)) ==
1496 int dspaddr
= DSPADDR(intel_crtc
->plane
);
1497 stall_detected
= I915_READ(dspaddr
) == (obj
->gtt_offset
+
1498 crtc
->y
* crtc
->fb
->pitches
[0] +
1499 crtc
->x
* crtc
->fb
->bits_per_pixel
/8);
1502 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1504 if (stall_detected
) {
1505 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1506 intel_prepare_page_flip(dev
, intel_crtc
->plane
);
1510 /* Called from drm generic code, passed 'crtc' which
1511 * we use as a pipe index
1513 static int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
1515 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1516 unsigned long irqflags
;
1518 if (!i915_pipe_enabled(dev
, pipe
))
1521 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1522 if (INTEL_INFO(dev
)->gen
>= 4)
1523 i915_enable_pipestat(dev_priv
, pipe
,
1524 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1526 i915_enable_pipestat(dev_priv
, pipe
,
1527 PIPE_VBLANK_INTERRUPT_ENABLE
);
1529 /* maintain vblank delivery even in deep C-states */
1530 if (dev_priv
->info
->gen
== 3)
1531 I915_WRITE(INSTPM
, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS
));
1532 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1537 static int ironlake_enable_vblank(struct drm_device
*dev
, int pipe
)
1539 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1540 unsigned long irqflags
;
1542 if (!i915_pipe_enabled(dev
, pipe
))
1545 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1546 ironlake_enable_display_irq(dev_priv
, (pipe
== 0) ?
1547 DE_PIPEA_VBLANK
: DE_PIPEB_VBLANK
);
1548 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1553 static int ivybridge_enable_vblank(struct drm_device
*dev
, int pipe
)
1555 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1556 unsigned long irqflags
;
1558 if (!i915_pipe_enabled(dev
, pipe
))
1561 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1562 ironlake_enable_display_irq(dev_priv
,
1563 DE_PIPEA_VBLANK_IVB
<< (5 * pipe
));
1564 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1569 static int valleyview_enable_vblank(struct drm_device
*dev
, int pipe
)
1571 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1572 unsigned long irqflags
;
1575 if (!i915_pipe_enabled(dev
, pipe
))
1578 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1579 imr
= I915_READ(VLV_IMR
);
1581 imr
&= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
1583 imr
&= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1584 I915_WRITE(VLV_IMR
, imr
);
1585 i915_enable_pipestat(dev_priv
, pipe
,
1586 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1587 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1592 /* Called from drm generic code, passed 'crtc' which
1593 * we use as a pipe index
1595 static void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
1597 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1598 unsigned long irqflags
;
1600 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1601 if (dev_priv
->info
->gen
== 3)
1602 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS
));
1604 i915_disable_pipestat(dev_priv
, pipe
,
1605 PIPE_VBLANK_INTERRUPT_ENABLE
|
1606 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1607 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1610 static void ironlake_disable_vblank(struct drm_device
*dev
, int pipe
)
1612 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1613 unsigned long irqflags
;
1615 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1616 ironlake_disable_display_irq(dev_priv
, (pipe
== 0) ?
1617 DE_PIPEA_VBLANK
: DE_PIPEB_VBLANK
);
1618 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1621 static void ivybridge_disable_vblank(struct drm_device
*dev
, int pipe
)
1623 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1624 unsigned long irqflags
;
1626 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1627 ironlake_disable_display_irq(dev_priv
,
1628 DE_PIPEA_VBLANK_IVB
<< (pipe
* 5));
1629 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1632 static void valleyview_disable_vblank(struct drm_device
*dev
, int pipe
)
1634 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1635 unsigned long irqflags
;
1638 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1639 i915_disable_pipestat(dev_priv
, pipe
,
1640 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1641 imr
= I915_READ(VLV_IMR
);
1643 imr
|= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
1645 imr
|= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1646 I915_WRITE(VLV_IMR
, imr
);
1647 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1651 ring_last_seqno(struct intel_ring_buffer
*ring
)
1653 return list_entry(ring
->request_list
.prev
,
1654 struct drm_i915_gem_request
, list
)->seqno
;
1657 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer
*ring
, bool *err
)
1659 if (list_empty(&ring
->request_list
) ||
1660 i915_seqno_passed(ring
->get_seqno(ring
, false),
1661 ring_last_seqno(ring
))) {
1662 /* Issue a wake-up to catch stuck h/w. */
1663 if (waitqueue_active(&ring
->irq_queue
)) {
1664 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1666 wake_up_all(&ring
->irq_queue
);
1674 static bool kick_ring(struct intel_ring_buffer
*ring
)
1676 struct drm_device
*dev
= ring
->dev
;
1677 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1678 u32 tmp
= I915_READ_CTL(ring
);
1679 if (tmp
& RING_WAIT
) {
1680 DRM_ERROR("Kicking stuck wait on %s\n",
1682 I915_WRITE_CTL(ring
, tmp
);
1688 static bool i915_hangcheck_hung(struct drm_device
*dev
)
1690 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1692 if (dev_priv
->hangcheck_count
++ > 1) {
1695 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1696 i915_handle_error(dev
, true);
1698 if (!IS_GEN2(dev
)) {
1699 struct intel_ring_buffer
*ring
;
1702 /* Is the chip hanging on a WAIT_FOR_EVENT?
1703 * If so we can simply poke the RB_WAIT bit
1704 * and break the hang. This should work on
1705 * all but the second generation chipsets.
1707 for_each_ring(ring
, dev_priv
, i
)
1708 hung
&= !kick_ring(ring
);
1718 * This is called when the chip hasn't reported back with completed
1719 * batchbuffers in a long time. The first time this is called we simply record
1720 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1721 * again, we assume the chip is wedged and try to fix it.
1723 void i915_hangcheck_elapsed(unsigned long data
)
1725 struct drm_device
*dev
= (struct drm_device
*)data
;
1726 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1727 uint32_t acthd
[I915_NUM_RINGS
], instdone
[I915_NUM_INSTDONE_REG
];
1728 struct intel_ring_buffer
*ring
;
1729 bool err
= false, idle
;
1732 if (!i915_enable_hangcheck
)
1735 memset(acthd
, 0, sizeof(acthd
));
1737 for_each_ring(ring
, dev_priv
, i
) {
1738 idle
&= i915_hangcheck_ring_idle(ring
, &err
);
1739 acthd
[i
] = intel_ring_get_active_head(ring
);
1742 /* If all work is done then ACTHD clearly hasn't advanced. */
1745 if (i915_hangcheck_hung(dev
))
1751 dev_priv
->hangcheck_count
= 0;
1755 i915_get_extra_instdone(dev
, instdone
);
1756 if (memcmp(dev_priv
->last_acthd
, acthd
, sizeof(acthd
)) == 0 &&
1757 memcmp(dev_priv
->prev_instdone
, instdone
, sizeof(instdone
)) == 0) {
1758 if (i915_hangcheck_hung(dev
))
1761 dev_priv
->hangcheck_count
= 0;
1763 memcpy(dev_priv
->last_acthd
, acthd
, sizeof(acthd
));
1764 memcpy(dev_priv
->prev_instdone
, instdone
, sizeof(instdone
));
1768 /* Reset timer case chip hangs without another request being added */
1769 mod_timer(&dev_priv
->hangcheck_timer
,
1770 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
1775 static void ironlake_irq_preinstall(struct drm_device
*dev
)
1777 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1779 atomic_set(&dev_priv
->irq_received
, 0);
1781 I915_WRITE(HWSTAM
, 0xeffe);
1783 /* XXX hotplug from PCH */
1785 I915_WRITE(DEIMR
, 0xffffffff);
1786 I915_WRITE(DEIER
, 0x0);
1787 POSTING_READ(DEIER
);
1790 I915_WRITE(GTIMR
, 0xffffffff);
1791 I915_WRITE(GTIER
, 0x0);
1792 POSTING_READ(GTIER
);
1794 /* south display irq */
1795 I915_WRITE(SDEIMR
, 0xffffffff);
1796 I915_WRITE(SDEIER
, 0x0);
1797 POSTING_READ(SDEIER
);
1800 static void valleyview_irq_preinstall(struct drm_device
*dev
)
1802 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1805 atomic_set(&dev_priv
->irq_received
, 0);
1808 I915_WRITE(VLV_IMR
, 0);
1809 I915_WRITE(RING_IMR(RENDER_RING_BASE
), 0);
1810 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE
), 0);
1811 I915_WRITE(RING_IMR(BLT_RING_BASE
), 0);
1814 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
1815 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
1816 I915_WRITE(GTIMR
, 0xffffffff);
1817 I915_WRITE(GTIER
, 0x0);
1818 POSTING_READ(GTIER
);
1820 I915_WRITE(DPINVGTT
, 0xff);
1822 I915_WRITE(PORT_HOTPLUG_EN
, 0);
1823 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
1825 I915_WRITE(PIPESTAT(pipe
), 0xffff);
1826 I915_WRITE(VLV_IIR
, 0xffffffff);
1827 I915_WRITE(VLV_IMR
, 0xffffffff);
1828 I915_WRITE(VLV_IER
, 0x0);
1829 POSTING_READ(VLV_IER
);
1833 * Enable digital hotplug on the PCH, and configure the DP short pulse
1834 * duration to 2ms (which is the minimum in the Display Port spec)
1836 * This register is the same on all known PCH chips.
1839 static void ironlake_enable_pch_hotplug(struct drm_device
*dev
)
1841 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1844 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
1845 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
1846 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
1847 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
1848 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
1849 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
1852 static int ironlake_irq_postinstall(struct drm_device
*dev
)
1854 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1855 /* enable kind of interrupts always enabled */
1856 u32 display_mask
= DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
1857 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
;
1861 dev_priv
->irq_mask
= ~display_mask
;
1863 /* should always can generate irq */
1864 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
1865 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
1866 I915_WRITE(DEIER
, display_mask
| DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
);
1867 POSTING_READ(DEIER
);
1869 dev_priv
->gt_irq_mask
= ~0;
1871 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
1872 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
1877 GEN6_BSD_USER_INTERRUPT
|
1878 GEN6_BLITTER_USER_INTERRUPT
;
1883 GT_BSD_USER_INTERRUPT
;
1884 I915_WRITE(GTIER
, render_irqs
);
1885 POSTING_READ(GTIER
);
1887 if (HAS_PCH_CPT(dev
)) {
1888 hotplug_mask
= (SDE_CRT_HOTPLUG_CPT
|
1889 SDE_PORTB_HOTPLUG_CPT
|
1890 SDE_PORTC_HOTPLUG_CPT
|
1891 SDE_PORTD_HOTPLUG_CPT
);
1893 hotplug_mask
= (SDE_CRT_HOTPLUG
|
1900 dev_priv
->pch_irq_mask
= ~hotplug_mask
;
1902 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
1903 I915_WRITE(SDEIMR
, dev_priv
->pch_irq_mask
);
1904 I915_WRITE(SDEIER
, hotplug_mask
);
1905 POSTING_READ(SDEIER
);
1907 ironlake_enable_pch_hotplug(dev
);
1909 if (IS_IRONLAKE_M(dev
)) {
1910 /* Clear & enable PCU event interrupts */
1911 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
1912 I915_WRITE(DEIER
, I915_READ(DEIER
) | DE_PCU_EVENT
);
1913 ironlake_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
1919 static int ivybridge_irq_postinstall(struct drm_device
*dev
)
1921 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1922 /* enable kind of interrupts always enabled */
1924 DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
| DE_PCH_EVENT_IVB
|
1925 DE_PLANEC_FLIP_DONE_IVB
|
1926 DE_PLANEB_FLIP_DONE_IVB
|
1927 DE_PLANEA_FLIP_DONE_IVB
;
1931 dev_priv
->irq_mask
= ~display_mask
;
1933 /* should always can generate irq */
1934 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
1935 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
1938 DE_PIPEC_VBLANK_IVB
|
1939 DE_PIPEB_VBLANK_IVB
|
1940 DE_PIPEA_VBLANK_IVB
);
1941 POSTING_READ(DEIER
);
1943 dev_priv
->gt_irq_mask
= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT
;
1945 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
1946 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
1948 render_irqs
= GT_USER_INTERRUPT
| GEN6_BSD_USER_INTERRUPT
|
1949 GEN6_BLITTER_USER_INTERRUPT
| GT_GEN7_L3_PARITY_ERROR_INTERRUPT
;
1950 I915_WRITE(GTIER
, render_irqs
);
1951 POSTING_READ(GTIER
);
1953 hotplug_mask
= (SDE_CRT_HOTPLUG_CPT
|
1954 SDE_PORTB_HOTPLUG_CPT
|
1955 SDE_PORTC_HOTPLUG_CPT
|
1956 SDE_PORTD_HOTPLUG_CPT
);
1957 dev_priv
->pch_irq_mask
= ~hotplug_mask
;
1959 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
1960 I915_WRITE(SDEIMR
, dev_priv
->pch_irq_mask
);
1961 I915_WRITE(SDEIER
, hotplug_mask
);
1962 POSTING_READ(SDEIER
);
1964 ironlake_enable_pch_hotplug(dev
);
1969 static int valleyview_irq_postinstall(struct drm_device
*dev
)
1971 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1973 u32 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
1974 u32 pipestat_enable
= PLANE_FLIP_DONE_INT_EN_VLV
;
1978 enable_mask
= I915_DISPLAY_PORT_INTERRUPT
;
1979 enable_mask
|= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
1980 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
1981 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
1982 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1985 *Leave vblank interrupts masked initially. enable/disable will
1986 * toggle them based on usage.
1988 dev_priv
->irq_mask
= (~enable_mask
) |
1989 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
1990 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1992 dev_priv
->pipestat
[0] = 0;
1993 dev_priv
->pipestat
[1] = 0;
1995 /* Hack for broken MSIs on VLV */
1996 pci_write_config_dword(dev_priv
->dev
->pdev
, 0x94, 0xfee00000);
1997 pci_read_config_word(dev
->pdev
, 0x98, &msid
);
1998 msid
&= 0xff; /* mask out delivery bits */
2000 pci_write_config_word(dev_priv
->dev
->pdev
, 0x98, msid
);
2002 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
2003 I915_WRITE(VLV_IER
, enable_mask
);
2004 I915_WRITE(VLV_IIR
, 0xffffffff);
2005 I915_WRITE(PIPESTAT(0), 0xffff);
2006 I915_WRITE(PIPESTAT(1), 0xffff);
2007 POSTING_READ(VLV_IER
);
2009 i915_enable_pipestat(dev_priv
, 0, pipestat_enable
);
2010 i915_enable_pipestat(dev_priv
, 1, pipestat_enable
);
2012 I915_WRITE(VLV_IIR
, 0xffffffff);
2013 I915_WRITE(VLV_IIR
, 0xffffffff);
2015 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2016 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
2018 render_irqs
= GT_USER_INTERRUPT
| GEN6_BSD_USER_INTERRUPT
|
2019 GEN6_BLITTER_USER_INTERRUPT
;
2020 I915_WRITE(GTIER
, render_irqs
);
2021 POSTING_READ(GTIER
);
2023 /* ack & enable invalid PTE error interrupts */
2024 #if 0 /* FIXME: add support to irq handler for checking these bits */
2025 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
2026 I915_WRITE(DPINVGTT
, DPINVGTT_EN_MASK
);
2029 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
2030 /* Note HDMI and DP share bits */
2031 if (dev_priv
->hotplug_supported_mask
& HDMIB_HOTPLUG_INT_STATUS
)
2032 hotplug_en
|= HDMIB_HOTPLUG_INT_EN
;
2033 if (dev_priv
->hotplug_supported_mask
& HDMIC_HOTPLUG_INT_STATUS
)
2034 hotplug_en
|= HDMIC_HOTPLUG_INT_EN
;
2035 if (dev_priv
->hotplug_supported_mask
& HDMID_HOTPLUG_INT_STATUS
)
2036 hotplug_en
|= HDMID_HOTPLUG_INT_EN
;
2037 if (dev_priv
->hotplug_supported_mask
& SDVOC_HOTPLUG_INT_STATUS_I915
)
2038 hotplug_en
|= SDVOC_HOTPLUG_INT_EN
;
2039 if (dev_priv
->hotplug_supported_mask
& SDVOB_HOTPLUG_INT_STATUS_I915
)
2040 hotplug_en
|= SDVOB_HOTPLUG_INT_EN
;
2041 if (dev_priv
->hotplug_supported_mask
& CRT_HOTPLUG_INT_STATUS
) {
2042 hotplug_en
|= CRT_HOTPLUG_INT_EN
;
2043 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
2046 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
2051 static void valleyview_irq_uninstall(struct drm_device
*dev
)
2053 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2060 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2062 I915_WRITE(HWSTAM
, 0xffffffff);
2063 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2064 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2066 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2067 I915_WRITE(VLV_IIR
, 0xffffffff);
2068 I915_WRITE(VLV_IMR
, 0xffffffff);
2069 I915_WRITE(VLV_IER
, 0x0);
2070 POSTING_READ(VLV_IER
);
2073 static void ironlake_irq_uninstall(struct drm_device
*dev
)
2075 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2080 I915_WRITE(HWSTAM
, 0xffffffff);
2082 I915_WRITE(DEIMR
, 0xffffffff);
2083 I915_WRITE(DEIER
, 0x0);
2084 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2086 I915_WRITE(GTIMR
, 0xffffffff);
2087 I915_WRITE(GTIER
, 0x0);
2088 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2090 I915_WRITE(SDEIMR
, 0xffffffff);
2091 I915_WRITE(SDEIER
, 0x0);
2092 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2095 static void i8xx_irq_preinstall(struct drm_device
* dev
)
2097 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2100 atomic_set(&dev_priv
->irq_received
, 0);
2103 I915_WRITE(PIPESTAT(pipe
), 0);
2104 I915_WRITE16(IMR
, 0xffff);
2105 I915_WRITE16(IER
, 0x0);
2106 POSTING_READ16(IER
);
2109 static int i8xx_irq_postinstall(struct drm_device
*dev
)
2111 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2113 dev_priv
->pipestat
[0] = 0;
2114 dev_priv
->pipestat
[1] = 0;
2117 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2119 /* Unmask the interrupts that we always want on. */
2120 dev_priv
->irq_mask
=
2121 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2122 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2123 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2124 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2125 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2126 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
2129 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2130 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2131 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2132 I915_USER_INTERRUPT
);
2133 POSTING_READ16(IER
);
2138 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
2140 struct drm_device
*dev
= (struct drm_device
*) arg
;
2141 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2144 unsigned long irqflags
;
2148 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2149 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2151 atomic_inc(&dev_priv
->irq_received
);
2153 iir
= I915_READ16(IIR
);
2157 while (iir
& ~flip_mask
) {
2158 /* Can't rely on pipestat interrupt bit in iir as it might
2159 * have been cleared after the pipestat interrupt was received.
2160 * It doesn't set the bit in iir again, but it still produces
2161 * interrupts (for non-MSI).
2163 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2164 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2165 i915_handle_error(dev
, false);
2167 for_each_pipe(pipe
) {
2168 int reg
= PIPESTAT(pipe
);
2169 pipe_stats
[pipe
] = I915_READ(reg
);
2172 * Clear the PIPE*STAT regs before the IIR
2174 if (pipe_stats
[pipe
] & 0x8000ffff) {
2175 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2176 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2178 I915_WRITE(reg
, pipe_stats
[pipe
]);
2182 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2184 I915_WRITE16(IIR
, iir
& ~flip_mask
);
2185 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
2187 i915_update_dri1_breadcrumb(dev
);
2189 if (iir
& I915_USER_INTERRUPT
)
2190 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2192 if (pipe_stats
[0] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2193 drm_handle_vblank(dev
, 0)) {
2194 if (iir
& I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
) {
2195 intel_prepare_page_flip(dev
, 0);
2196 intel_finish_page_flip(dev
, 0);
2197 flip_mask
&= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
;
2201 if (pipe_stats
[1] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2202 drm_handle_vblank(dev
, 1)) {
2203 if (iir
& I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
) {
2204 intel_prepare_page_flip(dev
, 1);
2205 intel_finish_page_flip(dev
, 1);
2206 flip_mask
&= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2216 static void i8xx_irq_uninstall(struct drm_device
* dev
)
2218 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2221 for_each_pipe(pipe
) {
2222 /* Clear enable bits; then clear status bits */
2223 I915_WRITE(PIPESTAT(pipe
), 0);
2224 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
2226 I915_WRITE16(IMR
, 0xffff);
2227 I915_WRITE16(IER
, 0x0);
2228 I915_WRITE16(IIR
, I915_READ16(IIR
));
2231 static void i915_irq_preinstall(struct drm_device
* dev
)
2233 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2236 atomic_set(&dev_priv
->irq_received
, 0);
2238 if (I915_HAS_HOTPLUG(dev
)) {
2239 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2240 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2243 I915_WRITE16(HWSTAM
, 0xeffe);
2245 I915_WRITE(PIPESTAT(pipe
), 0);
2246 I915_WRITE(IMR
, 0xffffffff);
2247 I915_WRITE(IER
, 0x0);
2251 static int i915_irq_postinstall(struct drm_device
*dev
)
2253 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2256 dev_priv
->pipestat
[0] = 0;
2257 dev_priv
->pipestat
[1] = 0;
2259 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2261 /* Unmask the interrupts that we always want on. */
2262 dev_priv
->irq_mask
=
2263 ~(I915_ASLE_INTERRUPT
|
2264 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2265 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2266 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2267 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2268 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2271 I915_ASLE_INTERRUPT
|
2272 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2273 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2274 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2275 I915_USER_INTERRUPT
;
2277 if (I915_HAS_HOTPLUG(dev
)) {
2278 /* Enable in IER... */
2279 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
2280 /* and unmask in IMR */
2281 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
2284 I915_WRITE(IMR
, dev_priv
->irq_mask
);
2285 I915_WRITE(IER
, enable_mask
);
2288 if (I915_HAS_HOTPLUG(dev
)) {
2289 u32 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
2291 if (dev_priv
->hotplug_supported_mask
& HDMIB_HOTPLUG_INT_STATUS
)
2292 hotplug_en
|= HDMIB_HOTPLUG_INT_EN
;
2293 if (dev_priv
->hotplug_supported_mask
& HDMIC_HOTPLUG_INT_STATUS
)
2294 hotplug_en
|= HDMIC_HOTPLUG_INT_EN
;
2295 if (dev_priv
->hotplug_supported_mask
& HDMID_HOTPLUG_INT_STATUS
)
2296 hotplug_en
|= HDMID_HOTPLUG_INT_EN
;
2297 if (dev_priv
->hotplug_supported_mask
& SDVOC_HOTPLUG_INT_STATUS_I915
)
2298 hotplug_en
|= SDVOC_HOTPLUG_INT_EN
;
2299 if (dev_priv
->hotplug_supported_mask
& SDVOB_HOTPLUG_INT_STATUS_I915
)
2300 hotplug_en
|= SDVOB_HOTPLUG_INT_EN
;
2301 if (dev_priv
->hotplug_supported_mask
& CRT_HOTPLUG_INT_STATUS
) {
2302 hotplug_en
|= CRT_HOTPLUG_INT_EN
;
2303 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
2306 /* Ignore TV since it's buggy */
2308 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
2311 intel_opregion_enable_asle(dev
);
2316 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
2318 struct drm_device
*dev
= (struct drm_device
*) arg
;
2319 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2320 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
2321 unsigned long irqflags
;
2323 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2324 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2326 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
,
2327 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2329 int pipe
, ret
= IRQ_NONE
;
2331 atomic_inc(&dev_priv
->irq_received
);
2333 iir
= I915_READ(IIR
);
2335 bool irq_received
= (iir
& ~flip_mask
) != 0;
2336 bool blc_event
= false;
2338 /* Can't rely on pipestat interrupt bit in iir as it might
2339 * have been cleared after the pipestat interrupt was received.
2340 * It doesn't set the bit in iir again, but it still produces
2341 * interrupts (for non-MSI).
2343 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2344 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2345 i915_handle_error(dev
, false);
2347 for_each_pipe(pipe
) {
2348 int reg
= PIPESTAT(pipe
);
2349 pipe_stats
[pipe
] = I915_READ(reg
);
2351 /* Clear the PIPE*STAT regs before the IIR */
2352 if (pipe_stats
[pipe
] & 0x8000ffff) {
2353 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2354 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2356 I915_WRITE(reg
, pipe_stats
[pipe
]);
2357 irq_received
= true;
2360 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2365 /* Consume port. Then clear IIR or we'll miss events */
2366 if ((I915_HAS_HOTPLUG(dev
)) &&
2367 (iir
& I915_DISPLAY_PORT_INTERRUPT
)) {
2368 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
2370 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2372 if (hotplug_status
& dev_priv
->hotplug_supported_mask
)
2373 queue_work(dev_priv
->wq
,
2374 &dev_priv
->hotplug_work
);
2376 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
2377 POSTING_READ(PORT_HOTPLUG_STAT
);
2380 I915_WRITE(IIR
, iir
& ~flip_mask
);
2381 new_iir
= I915_READ(IIR
); /* Flush posted writes */
2383 if (iir
& I915_USER_INTERRUPT
)
2384 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2386 for_each_pipe(pipe
) {
2390 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2391 drm_handle_vblank(dev
, pipe
)) {
2392 if (iir
& flip
[plane
]) {
2393 intel_prepare_page_flip(dev
, plane
);
2394 intel_finish_page_flip(dev
, pipe
);
2395 flip_mask
&= ~flip
[plane
];
2399 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
2403 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
2404 intel_opregion_asle_intr(dev
);
2406 /* With MSI, interrupts are only generated when iir
2407 * transitions from zero to nonzero. If another bit got
2408 * set while we were handling the existing iir bits, then
2409 * we would never get another interrupt.
2411 * This is fine on non-MSI as well, as if we hit this path
2412 * we avoid exiting the interrupt handler only to generate
2415 * Note that for MSI this could cause a stray interrupt report
2416 * if an interrupt landed in the time between writing IIR and
2417 * the posting read. This should be rare enough to never
2418 * trigger the 99% of 100,000 interrupts test for disabling
2423 } while (iir
& ~flip_mask
);
2425 i915_update_dri1_breadcrumb(dev
);
2430 static void i915_irq_uninstall(struct drm_device
* dev
)
2432 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2435 if (I915_HAS_HOTPLUG(dev
)) {
2436 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2437 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2440 I915_WRITE16(HWSTAM
, 0xffff);
2441 for_each_pipe(pipe
) {
2442 /* Clear enable bits; then clear status bits */
2443 I915_WRITE(PIPESTAT(pipe
), 0);
2444 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
2446 I915_WRITE(IMR
, 0xffffffff);
2447 I915_WRITE(IER
, 0x0);
2449 I915_WRITE(IIR
, I915_READ(IIR
));
2452 static void i965_irq_preinstall(struct drm_device
* dev
)
2454 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2457 atomic_set(&dev_priv
->irq_received
, 0);
2459 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2460 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2462 I915_WRITE(HWSTAM
, 0xeffe);
2464 I915_WRITE(PIPESTAT(pipe
), 0);
2465 I915_WRITE(IMR
, 0xffffffff);
2466 I915_WRITE(IER
, 0x0);
2470 static int i965_irq_postinstall(struct drm_device
*dev
)
2472 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2477 /* Unmask the interrupts that we always want on. */
2478 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
2479 I915_DISPLAY_PORT_INTERRUPT
|
2480 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2481 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2482 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2483 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2484 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2486 enable_mask
= ~dev_priv
->irq_mask
;
2487 enable_mask
|= I915_USER_INTERRUPT
;
2490 enable_mask
|= I915_BSD_USER_INTERRUPT
;
2492 dev_priv
->pipestat
[0] = 0;
2493 dev_priv
->pipestat
[1] = 0;
2496 * Enable some error detection, note the instruction error mask
2497 * bit is reserved, so we leave it masked.
2500 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
2501 GM45_ERROR_MEM_PRIV
|
2502 GM45_ERROR_CP_PRIV
|
2503 I915_ERROR_MEMORY_REFRESH
);
2505 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
2506 I915_ERROR_MEMORY_REFRESH
);
2508 I915_WRITE(EMR
, error_mask
);
2510 I915_WRITE(IMR
, dev_priv
->irq_mask
);
2511 I915_WRITE(IER
, enable_mask
);
2514 /* Note HDMI and DP share hotplug bits */
2516 if (dev_priv
->hotplug_supported_mask
& HDMIB_HOTPLUG_INT_STATUS
)
2517 hotplug_en
|= HDMIB_HOTPLUG_INT_EN
;
2518 if (dev_priv
->hotplug_supported_mask
& HDMIC_HOTPLUG_INT_STATUS
)
2519 hotplug_en
|= HDMIC_HOTPLUG_INT_EN
;
2520 if (dev_priv
->hotplug_supported_mask
& HDMID_HOTPLUG_INT_STATUS
)
2521 hotplug_en
|= HDMID_HOTPLUG_INT_EN
;
2523 if (dev_priv
->hotplug_supported_mask
& SDVOC_HOTPLUG_INT_STATUS_G4X
)
2524 hotplug_en
|= SDVOC_HOTPLUG_INT_EN
;
2525 if (dev_priv
->hotplug_supported_mask
& SDVOB_HOTPLUG_INT_STATUS_G4X
)
2526 hotplug_en
|= SDVOB_HOTPLUG_INT_EN
;
2528 if (dev_priv
->hotplug_supported_mask
& SDVOC_HOTPLUG_INT_STATUS_I965
)
2529 hotplug_en
|= SDVOC_HOTPLUG_INT_EN
;
2530 if (dev_priv
->hotplug_supported_mask
& SDVOB_HOTPLUG_INT_STATUS_I965
)
2531 hotplug_en
|= SDVOB_HOTPLUG_INT_EN
;
2533 if (dev_priv
->hotplug_supported_mask
& CRT_HOTPLUG_INT_STATUS
) {
2534 hotplug_en
|= CRT_HOTPLUG_INT_EN
;
2536 /* Programming the CRT detection parameters tends
2537 to generate a spurious hotplug event about three
2538 seconds later. So just do it once.
2541 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
2542 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
2545 /* Ignore TV since it's buggy */
2547 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
2549 intel_opregion_enable_asle(dev
);
2554 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
2556 struct drm_device
*dev
= (struct drm_device
*) arg
;
2557 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2559 u32 pipe_stats
[I915_MAX_PIPES
];
2560 unsigned long irqflags
;
2562 int ret
= IRQ_NONE
, pipe
;
2564 atomic_inc(&dev_priv
->irq_received
);
2566 iir
= I915_READ(IIR
);
2569 bool blc_event
= false;
2571 irq_received
= iir
!= 0;
2573 /* Can't rely on pipestat interrupt bit in iir as it might
2574 * have been cleared after the pipestat interrupt was received.
2575 * It doesn't set the bit in iir again, but it still produces
2576 * interrupts (for non-MSI).
2578 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2579 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2580 i915_handle_error(dev
, false);
2582 for_each_pipe(pipe
) {
2583 int reg
= PIPESTAT(pipe
);
2584 pipe_stats
[pipe
] = I915_READ(reg
);
2587 * Clear the PIPE*STAT regs before the IIR
2589 if (pipe_stats
[pipe
] & 0x8000ffff) {
2590 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2591 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2593 I915_WRITE(reg
, pipe_stats
[pipe
]);
2597 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2604 /* Consume port. Then clear IIR or we'll miss events */
2605 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
2606 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
2608 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2610 if (hotplug_status
& dev_priv
->hotplug_supported_mask
)
2611 queue_work(dev_priv
->wq
,
2612 &dev_priv
->hotplug_work
);
2614 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
2615 I915_READ(PORT_HOTPLUG_STAT
);
2618 I915_WRITE(IIR
, iir
);
2619 new_iir
= I915_READ(IIR
); /* Flush posted writes */
2621 if (iir
& I915_USER_INTERRUPT
)
2622 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2623 if (iir
& I915_BSD_USER_INTERRUPT
)
2624 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
2626 if (iir
& I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
)
2627 intel_prepare_page_flip(dev
, 0);
2629 if (iir
& I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
)
2630 intel_prepare_page_flip(dev
, 1);
2632 for_each_pipe(pipe
) {
2633 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
2634 drm_handle_vblank(dev
, pipe
)) {
2635 i915_pageflip_stall_check(dev
, pipe
);
2636 intel_finish_page_flip(dev
, pipe
);
2639 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
2644 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
2645 intel_opregion_asle_intr(dev
);
2647 /* With MSI, interrupts are only generated when iir
2648 * transitions from zero to nonzero. If another bit got
2649 * set while we were handling the existing iir bits, then
2650 * we would never get another interrupt.
2652 * This is fine on non-MSI as well, as if we hit this path
2653 * we avoid exiting the interrupt handler only to generate
2656 * Note that for MSI this could cause a stray interrupt report
2657 * if an interrupt landed in the time between writing IIR and
2658 * the posting read. This should be rare enough to never
2659 * trigger the 99% of 100,000 interrupts test for disabling
2665 i915_update_dri1_breadcrumb(dev
);
2670 static void i965_irq_uninstall(struct drm_device
* dev
)
2672 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2678 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2679 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2681 I915_WRITE(HWSTAM
, 0xffffffff);
2683 I915_WRITE(PIPESTAT(pipe
), 0);
2684 I915_WRITE(IMR
, 0xffffffff);
2685 I915_WRITE(IER
, 0x0);
2688 I915_WRITE(PIPESTAT(pipe
),
2689 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
2690 I915_WRITE(IIR
, I915_READ(IIR
));
2693 void intel_irq_init(struct drm_device
*dev
)
2695 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2697 INIT_WORK(&dev_priv
->hotplug_work
, i915_hotplug_work_func
);
2698 INIT_WORK(&dev_priv
->error_work
, i915_error_work_func
);
2699 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
2700 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
2702 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
2703 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
2704 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
2705 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
2706 dev
->driver
->get_vblank_counter
= gm45_get_vblank_counter
;
2709 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
2710 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
2712 dev
->driver
->get_vblank_timestamp
= NULL
;
2713 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
2715 if (IS_VALLEYVIEW(dev
)) {
2716 dev
->driver
->irq_handler
= valleyview_irq_handler
;
2717 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
2718 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
2719 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
2720 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
2721 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
2722 } else if (IS_IVYBRIDGE(dev
)) {
2723 /* Share pre & uninstall handlers with ILK/SNB */
2724 dev
->driver
->irq_handler
= ivybridge_irq_handler
;
2725 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
2726 dev
->driver
->irq_postinstall
= ivybridge_irq_postinstall
;
2727 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
2728 dev
->driver
->enable_vblank
= ivybridge_enable_vblank
;
2729 dev
->driver
->disable_vblank
= ivybridge_disable_vblank
;
2730 } else if (IS_HASWELL(dev
)) {
2731 /* Share interrupts handling with IVB */
2732 dev
->driver
->irq_handler
= ivybridge_irq_handler
;
2733 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
2734 dev
->driver
->irq_postinstall
= ivybridge_irq_postinstall
;
2735 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
2736 dev
->driver
->enable_vblank
= ivybridge_enable_vblank
;
2737 dev
->driver
->disable_vblank
= ivybridge_disable_vblank
;
2738 } else if (HAS_PCH_SPLIT(dev
)) {
2739 dev
->driver
->irq_handler
= ironlake_irq_handler
;
2740 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
2741 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
2742 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
2743 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
2744 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
2746 if (INTEL_INFO(dev
)->gen
== 2) {
2747 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
2748 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
2749 dev
->driver
->irq_handler
= i8xx_irq_handler
;
2750 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
2751 } else if (INTEL_INFO(dev
)->gen
== 3) {
2752 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
2753 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
2754 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
2755 dev
->driver
->irq_handler
= i915_irq_handler
;
2757 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
2758 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
2759 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
2760 dev
->driver
->irq_handler
= i965_irq_handler
;
2762 dev
->driver
->enable_vblank
= i915_enable_vblank
;
2763 dev
->driver
->disable_vblank
= i915_disable_vblank
;