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drm/i915: kill dev_priv->pm.regsave
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
34 #include <drm/drmP.h>
35 #include <drm/i915_drm.h>
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "intel_drv.h"
39
40 static const u32 hpd_ibx[] = {
41 [HPD_CRT] = SDE_CRT_HOTPLUG,
42 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
43 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
44 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
45 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
46 };
47
48 static const u32 hpd_cpt[] = {
49 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
50 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
51 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
52 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
53 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
54 };
55
56 static const u32 hpd_mask_i915[] = {
57 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
58 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
59 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
60 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
61 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
62 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
63 };
64
65 static const u32 hpd_status_g4x[] = {
66 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
67 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
68 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
69 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
70 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
71 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
72 };
73
74 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
75 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
76 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
77 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
78 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
79 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
80 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
81 };
82
83 /* IIR can theoretically queue up two events. Be paranoid. */
84 #define GEN8_IRQ_RESET_NDX(type, which) do { \
85 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
86 POSTING_READ(GEN8_##type##_IMR(which)); \
87 I915_WRITE(GEN8_##type##_IER(which), 0); \
88 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
89 POSTING_READ(GEN8_##type##_IIR(which)); \
90 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
91 POSTING_READ(GEN8_##type##_IIR(which)); \
92 } while (0)
93
94 #define GEN5_IRQ_RESET(type) do { \
95 I915_WRITE(type##IMR, 0xffffffff); \
96 POSTING_READ(type##IMR); \
97 I915_WRITE(type##IER, 0); \
98 I915_WRITE(type##IIR, 0xffffffff); \
99 POSTING_READ(type##IIR); \
100 I915_WRITE(type##IIR, 0xffffffff); \
101 POSTING_READ(type##IIR); \
102 } while (0)
103
104 /*
105 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
106 */
107 #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
108 u32 val = I915_READ(reg); \
109 if (val) { \
110 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
111 (reg), val); \
112 I915_WRITE((reg), 0xffffffff); \
113 POSTING_READ(reg); \
114 I915_WRITE((reg), 0xffffffff); \
115 POSTING_READ(reg); \
116 } \
117 } while (0)
118
119 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
120 GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
121 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
122 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
123 POSTING_READ(GEN8_##type##_IER(which)); \
124 } while (0)
125
126 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
127 GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
128 I915_WRITE(type##IMR, (imr_val)); \
129 I915_WRITE(type##IER, (ier_val)); \
130 POSTING_READ(type##IER); \
131 } while (0)
132
133 /* For display hotplug interrupt */
134 static void
135 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
136 {
137 assert_spin_locked(&dev_priv->irq_lock);
138
139 if (WARN_ON(dev_priv->pm.irqs_disabled))
140 return;
141
142 if ((dev_priv->irq_mask & mask) != 0) {
143 dev_priv->irq_mask &= ~mask;
144 I915_WRITE(DEIMR, dev_priv->irq_mask);
145 POSTING_READ(DEIMR);
146 }
147 }
148
149 static void
150 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
151 {
152 assert_spin_locked(&dev_priv->irq_lock);
153
154 if (WARN_ON(dev_priv->pm.irqs_disabled))
155 return;
156
157 if ((dev_priv->irq_mask & mask) != mask) {
158 dev_priv->irq_mask |= mask;
159 I915_WRITE(DEIMR, dev_priv->irq_mask);
160 POSTING_READ(DEIMR);
161 }
162 }
163
164 /**
165 * ilk_update_gt_irq - update GTIMR
166 * @dev_priv: driver private
167 * @interrupt_mask: mask of interrupt bits to update
168 * @enabled_irq_mask: mask of interrupt bits to enable
169 */
170 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
171 uint32_t interrupt_mask,
172 uint32_t enabled_irq_mask)
173 {
174 assert_spin_locked(&dev_priv->irq_lock);
175
176 if (WARN_ON(dev_priv->pm.irqs_disabled))
177 return;
178
179 dev_priv->gt_irq_mask &= ~interrupt_mask;
180 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
181 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
182 POSTING_READ(GTIMR);
183 }
184
185 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
186 {
187 ilk_update_gt_irq(dev_priv, mask, mask);
188 }
189
190 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
191 {
192 ilk_update_gt_irq(dev_priv, mask, 0);
193 }
194
195 /**
196 * snb_update_pm_irq - update GEN6_PMIMR
197 * @dev_priv: driver private
198 * @interrupt_mask: mask of interrupt bits to update
199 * @enabled_irq_mask: mask of interrupt bits to enable
200 */
201 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
202 uint32_t interrupt_mask,
203 uint32_t enabled_irq_mask)
204 {
205 uint32_t new_val;
206
207 assert_spin_locked(&dev_priv->irq_lock);
208
209 if (WARN_ON(dev_priv->pm.irqs_disabled))
210 return;
211
212 new_val = dev_priv->pm_irq_mask;
213 new_val &= ~interrupt_mask;
214 new_val |= (~enabled_irq_mask & interrupt_mask);
215
216 if (new_val != dev_priv->pm_irq_mask) {
217 dev_priv->pm_irq_mask = new_val;
218 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
219 POSTING_READ(GEN6_PMIMR);
220 }
221 }
222
223 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
224 {
225 snb_update_pm_irq(dev_priv, mask, mask);
226 }
227
228 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
229 {
230 snb_update_pm_irq(dev_priv, mask, 0);
231 }
232
233 static bool ivb_can_enable_err_int(struct drm_device *dev)
234 {
235 struct drm_i915_private *dev_priv = dev->dev_private;
236 struct intel_crtc *crtc;
237 enum pipe pipe;
238
239 assert_spin_locked(&dev_priv->irq_lock);
240
241 for_each_pipe(pipe) {
242 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
243
244 if (crtc->cpu_fifo_underrun_disabled)
245 return false;
246 }
247
248 return true;
249 }
250
251 static bool cpt_can_enable_serr_int(struct drm_device *dev)
252 {
253 struct drm_i915_private *dev_priv = dev->dev_private;
254 enum pipe pipe;
255 struct intel_crtc *crtc;
256
257 assert_spin_locked(&dev_priv->irq_lock);
258
259 for_each_pipe(pipe) {
260 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
261
262 if (crtc->pch_fifo_underrun_disabled)
263 return false;
264 }
265
266 return true;
267 }
268
269 static void i9xx_clear_fifo_underrun(struct drm_device *dev, enum pipe pipe)
270 {
271 struct drm_i915_private *dev_priv = dev->dev_private;
272 u32 reg = PIPESTAT(pipe);
273 u32 pipestat = I915_READ(reg) & 0x7fff0000;
274
275 assert_spin_locked(&dev_priv->irq_lock);
276
277 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
278 POSTING_READ(reg);
279 }
280
281 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
282 enum pipe pipe, bool enable)
283 {
284 struct drm_i915_private *dev_priv = dev->dev_private;
285 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
286 DE_PIPEB_FIFO_UNDERRUN;
287
288 if (enable)
289 ironlake_enable_display_irq(dev_priv, bit);
290 else
291 ironlake_disable_display_irq(dev_priv, bit);
292 }
293
294 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
295 enum pipe pipe, bool enable)
296 {
297 struct drm_i915_private *dev_priv = dev->dev_private;
298 if (enable) {
299 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
300
301 if (!ivb_can_enable_err_int(dev))
302 return;
303
304 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
305 } else {
306 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
307
308 /* Change the state _after_ we've read out the current one. */
309 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
310
311 if (!was_enabled &&
312 (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
313 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
314 pipe_name(pipe));
315 }
316 }
317 }
318
319 static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
320 enum pipe pipe, bool enable)
321 {
322 struct drm_i915_private *dev_priv = dev->dev_private;
323
324 assert_spin_locked(&dev_priv->irq_lock);
325
326 if (enable)
327 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;
328 else
329 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
330 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
331 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
332 }
333
334 /**
335 * ibx_display_interrupt_update - update SDEIMR
336 * @dev_priv: driver private
337 * @interrupt_mask: mask of interrupt bits to update
338 * @enabled_irq_mask: mask of interrupt bits to enable
339 */
340 static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
341 uint32_t interrupt_mask,
342 uint32_t enabled_irq_mask)
343 {
344 uint32_t sdeimr = I915_READ(SDEIMR);
345 sdeimr &= ~interrupt_mask;
346 sdeimr |= (~enabled_irq_mask & interrupt_mask);
347
348 assert_spin_locked(&dev_priv->irq_lock);
349
350 if (WARN_ON(dev_priv->pm.irqs_disabled))
351 return;
352
353 I915_WRITE(SDEIMR, sdeimr);
354 POSTING_READ(SDEIMR);
355 }
356 #define ibx_enable_display_interrupt(dev_priv, bits) \
357 ibx_display_interrupt_update((dev_priv), (bits), (bits))
358 #define ibx_disable_display_interrupt(dev_priv, bits) \
359 ibx_display_interrupt_update((dev_priv), (bits), 0)
360
361 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
362 enum transcoder pch_transcoder,
363 bool enable)
364 {
365 struct drm_i915_private *dev_priv = dev->dev_private;
366 uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
367 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
368
369 if (enable)
370 ibx_enable_display_interrupt(dev_priv, bit);
371 else
372 ibx_disable_display_interrupt(dev_priv, bit);
373 }
374
375 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
376 enum transcoder pch_transcoder,
377 bool enable)
378 {
379 struct drm_i915_private *dev_priv = dev->dev_private;
380
381 if (enable) {
382 I915_WRITE(SERR_INT,
383 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
384
385 if (!cpt_can_enable_serr_int(dev))
386 return;
387
388 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
389 } else {
390 uint32_t tmp = I915_READ(SERR_INT);
391 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
392
393 /* Change the state _after_ we've read out the current one. */
394 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
395
396 if (!was_enabled &&
397 (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
398 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
399 transcoder_name(pch_transcoder));
400 }
401 }
402 }
403
404 /**
405 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
406 * @dev: drm device
407 * @pipe: pipe
408 * @enable: true if we want to report FIFO underrun errors, false otherwise
409 *
410 * This function makes us disable or enable CPU fifo underruns for a specific
411 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
412 * reporting for one pipe may also disable all the other CPU error interruts for
413 * the other pipes, due to the fact that there's just one interrupt mask/enable
414 * bit for all the pipes.
415 *
416 * Returns the previous state of underrun reporting.
417 */
418 bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
419 enum pipe pipe, bool enable)
420 {
421 struct drm_i915_private *dev_priv = dev->dev_private;
422 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
423 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
424 bool ret;
425
426 assert_spin_locked(&dev_priv->irq_lock);
427
428 ret = !intel_crtc->cpu_fifo_underrun_disabled;
429
430 if (enable == ret)
431 goto done;
432
433 intel_crtc->cpu_fifo_underrun_disabled = !enable;
434
435 if (enable && (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)))
436 i9xx_clear_fifo_underrun(dev, pipe);
437 else if (IS_GEN5(dev) || IS_GEN6(dev))
438 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
439 else if (IS_GEN7(dev))
440 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
441 else if (IS_GEN8(dev))
442 broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
443
444 done:
445 return ret;
446 }
447
448 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
449 enum pipe pipe, bool enable)
450 {
451 struct drm_i915_private *dev_priv = dev->dev_private;
452 unsigned long flags;
453 bool ret;
454
455 spin_lock_irqsave(&dev_priv->irq_lock, flags);
456 ret = __intel_set_cpu_fifo_underrun_reporting(dev, pipe, enable);
457 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
458
459 return ret;
460 }
461
462 static bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev,
463 enum pipe pipe)
464 {
465 struct drm_i915_private *dev_priv = dev->dev_private;
466 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
467 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
468
469 return !intel_crtc->cpu_fifo_underrun_disabled;
470 }
471
472 /**
473 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
474 * @dev: drm device
475 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
476 * @enable: true if we want to report FIFO underrun errors, false otherwise
477 *
478 * This function makes us disable or enable PCH fifo underruns for a specific
479 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
480 * underrun reporting for one transcoder may also disable all the other PCH
481 * error interruts for the other transcoders, due to the fact that there's just
482 * one interrupt mask/enable bit for all the transcoders.
483 *
484 * Returns the previous state of underrun reporting.
485 */
486 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
487 enum transcoder pch_transcoder,
488 bool enable)
489 {
490 struct drm_i915_private *dev_priv = dev->dev_private;
491 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
493 unsigned long flags;
494 bool ret;
495
496 /*
497 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
498 * has only one pch transcoder A that all pipes can use. To avoid racy
499 * pch transcoder -> pipe lookups from interrupt code simply store the
500 * underrun statistics in crtc A. Since we never expose this anywhere
501 * nor use it outside of the fifo underrun code here using the "wrong"
502 * crtc on LPT won't cause issues.
503 */
504
505 spin_lock_irqsave(&dev_priv->irq_lock, flags);
506
507 ret = !intel_crtc->pch_fifo_underrun_disabled;
508
509 if (enable == ret)
510 goto done;
511
512 intel_crtc->pch_fifo_underrun_disabled = !enable;
513
514 if (HAS_PCH_IBX(dev))
515 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
516 else
517 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
518
519 done:
520 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
521 return ret;
522 }
523
524
525 static void
526 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
527 u32 enable_mask, u32 status_mask)
528 {
529 u32 reg = PIPESTAT(pipe);
530 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
531
532 assert_spin_locked(&dev_priv->irq_lock);
533
534 if (WARN_ON_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
535 status_mask & ~PIPESTAT_INT_STATUS_MASK))
536 return;
537
538 if ((pipestat & enable_mask) == enable_mask)
539 return;
540
541 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
542
543 /* Enable the interrupt, clear any pending status */
544 pipestat |= enable_mask | status_mask;
545 I915_WRITE(reg, pipestat);
546 POSTING_READ(reg);
547 }
548
549 static void
550 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
551 u32 enable_mask, u32 status_mask)
552 {
553 u32 reg = PIPESTAT(pipe);
554 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
555
556 assert_spin_locked(&dev_priv->irq_lock);
557
558 if (WARN_ON_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
559 status_mask & ~PIPESTAT_INT_STATUS_MASK))
560 return;
561
562 if ((pipestat & enable_mask) == 0)
563 return;
564
565 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
566
567 pipestat &= ~enable_mask;
568 I915_WRITE(reg, pipestat);
569 POSTING_READ(reg);
570 }
571
572 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
573 {
574 u32 enable_mask = status_mask << 16;
575
576 /*
577 * On pipe A we don't support the PSR interrupt yet, on pipe B the
578 * same bit MBZ.
579 */
580 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
581 return 0;
582
583 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
584 SPRITE0_FLIP_DONE_INT_EN_VLV |
585 SPRITE1_FLIP_DONE_INT_EN_VLV);
586 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
587 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
588 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
589 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
590
591 return enable_mask;
592 }
593
594 void
595 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
596 u32 status_mask)
597 {
598 u32 enable_mask;
599
600 if (IS_VALLEYVIEW(dev_priv->dev))
601 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
602 status_mask);
603 else
604 enable_mask = status_mask << 16;
605 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
606 }
607
608 void
609 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
610 u32 status_mask)
611 {
612 u32 enable_mask;
613
614 if (IS_VALLEYVIEW(dev_priv->dev))
615 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
616 status_mask);
617 else
618 enable_mask = status_mask << 16;
619 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
620 }
621
622 /**
623 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
624 */
625 static void i915_enable_asle_pipestat(struct drm_device *dev)
626 {
627 struct drm_i915_private *dev_priv = dev->dev_private;
628 unsigned long irqflags;
629
630 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
631 return;
632
633 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
634
635 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
636 if (INTEL_INFO(dev)->gen >= 4)
637 i915_enable_pipestat(dev_priv, PIPE_A,
638 PIPE_LEGACY_BLC_EVENT_STATUS);
639
640 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
641 }
642
643 /**
644 * i915_pipe_enabled - check if a pipe is enabled
645 * @dev: DRM device
646 * @pipe: pipe to check
647 *
648 * Reading certain registers when the pipe is disabled can hang the chip.
649 * Use this routine to make sure the PLL is running and the pipe is active
650 * before reading such registers if unsure.
651 */
652 static int
653 i915_pipe_enabled(struct drm_device *dev, int pipe)
654 {
655 struct drm_i915_private *dev_priv = dev->dev_private;
656
657 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
658 /* Locking is horribly broken here, but whatever. */
659 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
660 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
661
662 return intel_crtc->active;
663 } else {
664 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
665 }
666 }
667
668 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
669 {
670 /* Gen2 doesn't have a hardware frame counter */
671 return 0;
672 }
673
674 /* Called from drm generic code, passed a 'crtc', which
675 * we use as a pipe index
676 */
677 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
678 {
679 struct drm_i915_private *dev_priv = dev->dev_private;
680 unsigned long high_frame;
681 unsigned long low_frame;
682 u32 high1, high2, low, pixel, vbl_start;
683
684 if (!i915_pipe_enabled(dev, pipe)) {
685 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
686 "pipe %c\n", pipe_name(pipe));
687 return 0;
688 }
689
690 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
691 struct intel_crtc *intel_crtc =
692 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
693 const struct drm_display_mode *mode =
694 &intel_crtc->config.adjusted_mode;
695
696 vbl_start = mode->crtc_vblank_start * mode->crtc_htotal;
697 } else {
698 enum transcoder cpu_transcoder = (enum transcoder) pipe;
699 u32 htotal;
700
701 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
702 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
703
704 vbl_start *= htotal;
705 }
706
707 high_frame = PIPEFRAME(pipe);
708 low_frame = PIPEFRAMEPIXEL(pipe);
709
710 /*
711 * High & low register fields aren't synchronized, so make sure
712 * we get a low value that's stable across two reads of the high
713 * register.
714 */
715 do {
716 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
717 low = I915_READ(low_frame);
718 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
719 } while (high1 != high2);
720
721 high1 >>= PIPE_FRAME_HIGH_SHIFT;
722 pixel = low & PIPE_PIXEL_MASK;
723 low >>= PIPE_FRAME_LOW_SHIFT;
724
725 /*
726 * The frame counter increments at beginning of active.
727 * Cook up a vblank counter by also checking the pixel
728 * counter against vblank start.
729 */
730 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
731 }
732
733 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
734 {
735 struct drm_i915_private *dev_priv = dev->dev_private;
736 int reg = PIPE_FRMCOUNT_GM45(pipe);
737
738 if (!i915_pipe_enabled(dev, pipe)) {
739 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
740 "pipe %c\n", pipe_name(pipe));
741 return 0;
742 }
743
744 return I915_READ(reg);
745 }
746
747 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
748 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
749
750 static bool ilk_pipe_in_vblank_locked(struct drm_device *dev, enum pipe pipe)
751 {
752 struct drm_i915_private *dev_priv = dev->dev_private;
753 uint32_t status;
754 int reg;
755
756 if (INTEL_INFO(dev)->gen >= 8) {
757 status = GEN8_PIPE_VBLANK;
758 reg = GEN8_DE_PIPE_ISR(pipe);
759 } else if (INTEL_INFO(dev)->gen >= 7) {
760 status = DE_PIPE_VBLANK_IVB(pipe);
761 reg = DEISR;
762 } else {
763 status = DE_PIPE_VBLANK(pipe);
764 reg = DEISR;
765 }
766
767 return __raw_i915_read32(dev_priv, reg) & status;
768 }
769
770 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
771 unsigned int flags, int *vpos, int *hpos,
772 ktime_t *stime, ktime_t *etime)
773 {
774 struct drm_i915_private *dev_priv = dev->dev_private;
775 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
777 const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
778 int position;
779 int vbl_start, vbl_end, htotal, vtotal;
780 bool in_vbl = true;
781 int ret = 0;
782 unsigned long irqflags;
783
784 if (!intel_crtc->active) {
785 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
786 "pipe %c\n", pipe_name(pipe));
787 return 0;
788 }
789
790 htotal = mode->crtc_htotal;
791 vtotal = mode->crtc_vtotal;
792 vbl_start = mode->crtc_vblank_start;
793 vbl_end = mode->crtc_vblank_end;
794
795 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
796 vbl_start = DIV_ROUND_UP(vbl_start, 2);
797 vbl_end /= 2;
798 vtotal /= 2;
799 }
800
801 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
802
803 /*
804 * Lock uncore.lock, as we will do multiple timing critical raw
805 * register reads, potentially with preemption disabled, so the
806 * following code must not block on uncore.lock.
807 */
808 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
809
810 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
811
812 /* Get optional system timestamp before query. */
813 if (stime)
814 *stime = ktime_get();
815
816 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
817 /* No obvious pixelcount register. Only query vertical
818 * scanout position from Display scan line register.
819 */
820 if (IS_GEN2(dev))
821 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
822 else
823 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
824
825 if (HAS_DDI(dev)) {
826 /*
827 * On HSW HDMI outputs there seems to be a 2 line
828 * difference, whereas eDP has the normal 1 line
829 * difference that earlier platforms have. External
830 * DP is unknown. For now just check for the 2 line
831 * difference case on all output types on HSW+.
832 *
833 * This might misinterpret the scanline counter being
834 * one line too far along on eDP, but that's less
835 * dangerous than the alternative since that would lead
836 * the vblank timestamp code astray when it sees a
837 * scanline count before vblank_start during a vblank
838 * interrupt.
839 */
840 in_vbl = ilk_pipe_in_vblank_locked(dev, pipe);
841 if ((in_vbl && (position == vbl_start - 2 ||
842 position == vbl_start - 1)) ||
843 (!in_vbl && (position == vbl_end - 2 ||
844 position == vbl_end - 1)))
845 position = (position + 2) % vtotal;
846 } else if (HAS_PCH_SPLIT(dev)) {
847 /*
848 * The scanline counter increments at the leading edge
849 * of hsync, ie. it completely misses the active portion
850 * of the line. Fix up the counter at both edges of vblank
851 * to get a more accurate picture whether we're in vblank
852 * or not.
853 */
854 in_vbl = ilk_pipe_in_vblank_locked(dev, pipe);
855 if ((in_vbl && position == vbl_start - 1) ||
856 (!in_vbl && position == vbl_end - 1))
857 position = (position + 1) % vtotal;
858 } else {
859 /*
860 * ISR vblank status bits don't work the way we'd want
861 * them to work on non-PCH platforms (for
862 * ilk_pipe_in_vblank_locked()), and there doesn't
863 * appear any other way to determine if we're currently
864 * in vblank.
865 *
866 * Instead let's assume that we're already in vblank if
867 * we got called from the vblank interrupt and the
868 * scanline counter value indicates that we're on the
869 * line just prior to vblank start. This should result
870 * in the correct answer, unless the vblank interrupt
871 * delivery really got delayed for almost exactly one
872 * full frame/field.
873 */
874 if (flags & DRM_CALLED_FROM_VBLIRQ &&
875 position == vbl_start - 1) {
876 position = (position + 1) % vtotal;
877
878 /* Signal this correction as "applied". */
879 ret |= 0x8;
880 }
881 }
882 } else {
883 /* Have access to pixelcount since start of frame.
884 * We can split this into vertical and horizontal
885 * scanout position.
886 */
887 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
888
889 /* convert to pixel counts */
890 vbl_start *= htotal;
891 vbl_end *= htotal;
892 vtotal *= htotal;
893 }
894
895 /* Get optional system timestamp after query. */
896 if (etime)
897 *etime = ktime_get();
898
899 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
900
901 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
902
903 in_vbl = position >= vbl_start && position < vbl_end;
904
905 /*
906 * While in vblank, position will be negative
907 * counting up towards 0 at vbl_end. And outside
908 * vblank, position will be positive counting
909 * up since vbl_end.
910 */
911 if (position >= vbl_start)
912 position -= vbl_end;
913 else
914 position += vtotal - vbl_end;
915
916 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
917 *vpos = position;
918 *hpos = 0;
919 } else {
920 *vpos = position / htotal;
921 *hpos = position - (*vpos * htotal);
922 }
923
924 /* In vblank? */
925 if (in_vbl)
926 ret |= DRM_SCANOUTPOS_INVBL;
927
928 return ret;
929 }
930
931 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
932 int *max_error,
933 struct timeval *vblank_time,
934 unsigned flags)
935 {
936 struct drm_crtc *crtc;
937
938 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
939 DRM_ERROR("Invalid crtc %d\n", pipe);
940 return -EINVAL;
941 }
942
943 /* Get drm_crtc to timestamp: */
944 crtc = intel_get_crtc_for_pipe(dev, pipe);
945 if (crtc == NULL) {
946 DRM_ERROR("Invalid crtc %d\n", pipe);
947 return -EINVAL;
948 }
949
950 if (!crtc->enabled) {
951 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
952 return -EBUSY;
953 }
954
955 /* Helper routine in DRM core does all the work: */
956 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
957 vblank_time, flags,
958 crtc,
959 &to_intel_crtc(crtc)->config.adjusted_mode);
960 }
961
962 static bool intel_hpd_irq_event(struct drm_device *dev,
963 struct drm_connector *connector)
964 {
965 enum drm_connector_status old_status;
966
967 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
968 old_status = connector->status;
969
970 connector->status = connector->funcs->detect(connector, false);
971 if (old_status == connector->status)
972 return false;
973
974 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
975 connector->base.id,
976 drm_get_connector_name(connector),
977 drm_get_connector_status_name(old_status),
978 drm_get_connector_status_name(connector->status));
979
980 return true;
981 }
982
983 /*
984 * Handle hotplug events outside the interrupt handler proper.
985 */
986 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
987
988 static void i915_hotplug_work_func(struct work_struct *work)
989 {
990 struct drm_i915_private *dev_priv =
991 container_of(work, struct drm_i915_private, hotplug_work);
992 struct drm_device *dev = dev_priv->dev;
993 struct drm_mode_config *mode_config = &dev->mode_config;
994 struct intel_connector *intel_connector;
995 struct intel_encoder *intel_encoder;
996 struct drm_connector *connector;
997 unsigned long irqflags;
998 bool hpd_disabled = false;
999 bool changed = false;
1000 u32 hpd_event_bits;
1001
1002 /* HPD irq before everything is fully set up. */
1003 if (!dev_priv->enable_hotplug_processing)
1004 return;
1005
1006 mutex_lock(&mode_config->mutex);
1007 DRM_DEBUG_KMS("running encoder hotplug functions\n");
1008
1009 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1010
1011 hpd_event_bits = dev_priv->hpd_event_bits;
1012 dev_priv->hpd_event_bits = 0;
1013 list_for_each_entry(connector, &mode_config->connector_list, head) {
1014 intel_connector = to_intel_connector(connector);
1015 intel_encoder = intel_connector->encoder;
1016 if (intel_encoder->hpd_pin > HPD_NONE &&
1017 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
1018 connector->polled == DRM_CONNECTOR_POLL_HPD) {
1019 DRM_INFO("HPD interrupt storm detected on connector %s: "
1020 "switching from hotplug detection to polling\n",
1021 drm_get_connector_name(connector));
1022 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
1023 connector->polled = DRM_CONNECTOR_POLL_CONNECT
1024 | DRM_CONNECTOR_POLL_DISCONNECT;
1025 hpd_disabled = true;
1026 }
1027 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
1028 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
1029 drm_get_connector_name(connector), intel_encoder->hpd_pin);
1030 }
1031 }
1032 /* if there were no outputs to poll, poll was disabled,
1033 * therefore make sure it's enabled when disabling HPD on
1034 * some connectors */
1035 if (hpd_disabled) {
1036 drm_kms_helper_poll_enable(dev);
1037 mod_timer(&dev_priv->hotplug_reenable_timer,
1038 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
1039 }
1040
1041 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1042
1043 list_for_each_entry(connector, &mode_config->connector_list, head) {
1044 intel_connector = to_intel_connector(connector);
1045 intel_encoder = intel_connector->encoder;
1046 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
1047 if (intel_encoder->hot_plug)
1048 intel_encoder->hot_plug(intel_encoder);
1049 if (intel_hpd_irq_event(dev, connector))
1050 changed = true;
1051 }
1052 }
1053 mutex_unlock(&mode_config->mutex);
1054
1055 if (changed)
1056 drm_kms_helper_hotplug_event(dev);
1057 }
1058
1059 static void intel_hpd_irq_uninstall(struct drm_i915_private *dev_priv)
1060 {
1061 del_timer_sync(&dev_priv->hotplug_reenable_timer);
1062 }
1063
1064 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
1065 {
1066 struct drm_i915_private *dev_priv = dev->dev_private;
1067 u32 busy_up, busy_down, max_avg, min_avg;
1068 u8 new_delay;
1069
1070 spin_lock(&mchdev_lock);
1071
1072 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
1073
1074 new_delay = dev_priv->ips.cur_delay;
1075
1076 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
1077 busy_up = I915_READ(RCPREVBSYTUPAVG);
1078 busy_down = I915_READ(RCPREVBSYTDNAVG);
1079 max_avg = I915_READ(RCBMAXAVG);
1080 min_avg = I915_READ(RCBMINAVG);
1081
1082 /* Handle RCS change request from hw */
1083 if (busy_up > max_avg) {
1084 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
1085 new_delay = dev_priv->ips.cur_delay - 1;
1086 if (new_delay < dev_priv->ips.max_delay)
1087 new_delay = dev_priv->ips.max_delay;
1088 } else if (busy_down < min_avg) {
1089 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
1090 new_delay = dev_priv->ips.cur_delay + 1;
1091 if (new_delay > dev_priv->ips.min_delay)
1092 new_delay = dev_priv->ips.min_delay;
1093 }
1094
1095 if (ironlake_set_drps(dev, new_delay))
1096 dev_priv->ips.cur_delay = new_delay;
1097
1098 spin_unlock(&mchdev_lock);
1099
1100 return;
1101 }
1102
1103 static void notify_ring(struct drm_device *dev,
1104 struct intel_ring_buffer *ring)
1105 {
1106 if (ring->obj == NULL)
1107 return;
1108
1109 trace_i915_gem_request_complete(ring);
1110
1111 wake_up_all(&ring->irq_queue);
1112 i915_queue_hangcheck(dev);
1113 }
1114
1115 static void gen6_pm_rps_work(struct work_struct *work)
1116 {
1117 struct drm_i915_private *dev_priv =
1118 container_of(work, struct drm_i915_private, rps.work);
1119 u32 pm_iir;
1120 int new_delay, adj;
1121
1122 spin_lock_irq(&dev_priv->irq_lock);
1123 pm_iir = dev_priv->rps.pm_iir;
1124 dev_priv->rps.pm_iir = 0;
1125 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
1126 snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1127 spin_unlock_irq(&dev_priv->irq_lock);
1128
1129 /* Make sure we didn't queue anything we're not going to process. */
1130 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1131
1132 if ((pm_iir & dev_priv->pm_rps_events) == 0)
1133 return;
1134
1135 mutex_lock(&dev_priv->rps.hw_lock);
1136
1137 adj = dev_priv->rps.last_adj;
1138 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1139 if (adj > 0)
1140 adj *= 2;
1141 else
1142 adj = 1;
1143 new_delay = dev_priv->rps.cur_freq + adj;
1144
1145 /*
1146 * For better performance, jump directly
1147 * to RPe if we're below it.
1148 */
1149 if (new_delay < dev_priv->rps.efficient_freq)
1150 new_delay = dev_priv->rps.efficient_freq;
1151 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1152 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1153 new_delay = dev_priv->rps.efficient_freq;
1154 else
1155 new_delay = dev_priv->rps.min_freq_softlimit;
1156 adj = 0;
1157 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1158 if (adj < 0)
1159 adj *= 2;
1160 else
1161 adj = -1;
1162 new_delay = dev_priv->rps.cur_freq + adj;
1163 } else { /* unknown event */
1164 new_delay = dev_priv->rps.cur_freq;
1165 }
1166
1167 /* sysfs frequency interfaces may have snuck in while servicing the
1168 * interrupt
1169 */
1170 new_delay = clamp_t(int, new_delay,
1171 dev_priv->rps.min_freq_softlimit,
1172 dev_priv->rps.max_freq_softlimit);
1173
1174 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq;
1175
1176 if (IS_VALLEYVIEW(dev_priv->dev))
1177 valleyview_set_rps(dev_priv->dev, new_delay);
1178 else
1179 gen6_set_rps(dev_priv->dev, new_delay);
1180
1181 mutex_unlock(&dev_priv->rps.hw_lock);
1182 }
1183
1184
1185 /**
1186 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1187 * occurred.
1188 * @work: workqueue struct
1189 *
1190 * Doesn't actually do anything except notify userspace. As a consequence of
1191 * this event, userspace should try to remap the bad rows since statistically
1192 * it is likely the same row is more likely to go bad again.
1193 */
1194 static void ivybridge_parity_work(struct work_struct *work)
1195 {
1196 struct drm_i915_private *dev_priv =
1197 container_of(work, struct drm_i915_private, l3_parity.error_work);
1198 u32 error_status, row, bank, subbank;
1199 char *parity_event[6];
1200 uint32_t misccpctl;
1201 unsigned long flags;
1202 uint8_t slice = 0;
1203
1204 /* We must turn off DOP level clock gating to access the L3 registers.
1205 * In order to prevent a get/put style interface, acquire struct mutex
1206 * any time we access those registers.
1207 */
1208 mutex_lock(&dev_priv->dev->struct_mutex);
1209
1210 /* If we've screwed up tracking, just let the interrupt fire again */
1211 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1212 goto out;
1213
1214 misccpctl = I915_READ(GEN7_MISCCPCTL);
1215 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1216 POSTING_READ(GEN7_MISCCPCTL);
1217
1218 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1219 u32 reg;
1220
1221 slice--;
1222 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1223 break;
1224
1225 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1226
1227 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1228
1229 error_status = I915_READ(reg);
1230 row = GEN7_PARITY_ERROR_ROW(error_status);
1231 bank = GEN7_PARITY_ERROR_BANK(error_status);
1232 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1233
1234 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1235 POSTING_READ(reg);
1236
1237 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1238 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1239 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1240 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1241 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1242 parity_event[5] = NULL;
1243
1244 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1245 KOBJ_CHANGE, parity_event);
1246
1247 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1248 slice, row, bank, subbank);
1249
1250 kfree(parity_event[4]);
1251 kfree(parity_event[3]);
1252 kfree(parity_event[2]);
1253 kfree(parity_event[1]);
1254 }
1255
1256 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1257
1258 out:
1259 WARN_ON(dev_priv->l3_parity.which_slice);
1260 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1261 ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1262 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1263
1264 mutex_unlock(&dev_priv->dev->struct_mutex);
1265 }
1266
1267 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1268 {
1269 struct drm_i915_private *dev_priv = dev->dev_private;
1270
1271 if (!HAS_L3_DPF(dev))
1272 return;
1273
1274 spin_lock(&dev_priv->irq_lock);
1275 ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1276 spin_unlock(&dev_priv->irq_lock);
1277
1278 iir &= GT_PARITY_ERROR(dev);
1279 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1280 dev_priv->l3_parity.which_slice |= 1 << 1;
1281
1282 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1283 dev_priv->l3_parity.which_slice |= 1 << 0;
1284
1285 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1286 }
1287
1288 static void ilk_gt_irq_handler(struct drm_device *dev,
1289 struct drm_i915_private *dev_priv,
1290 u32 gt_iir)
1291 {
1292 if (gt_iir &
1293 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1294 notify_ring(dev, &dev_priv->ring[RCS]);
1295 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1296 notify_ring(dev, &dev_priv->ring[VCS]);
1297 }
1298
1299 static void snb_gt_irq_handler(struct drm_device *dev,
1300 struct drm_i915_private *dev_priv,
1301 u32 gt_iir)
1302 {
1303
1304 if (gt_iir &
1305 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1306 notify_ring(dev, &dev_priv->ring[RCS]);
1307 if (gt_iir & GT_BSD_USER_INTERRUPT)
1308 notify_ring(dev, &dev_priv->ring[VCS]);
1309 if (gt_iir & GT_BLT_USER_INTERRUPT)
1310 notify_ring(dev, &dev_priv->ring[BCS]);
1311
1312 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1313 GT_BSD_CS_ERROR_INTERRUPT |
1314 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
1315 i915_handle_error(dev, false, "GT error interrupt 0x%08x",
1316 gt_iir);
1317 }
1318
1319 if (gt_iir & GT_PARITY_ERROR(dev))
1320 ivybridge_parity_error_irq_handler(dev, gt_iir);
1321 }
1322
1323 static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1324 struct drm_i915_private *dev_priv,
1325 u32 master_ctl)
1326 {
1327 u32 rcs, bcs, vcs;
1328 uint32_t tmp = 0;
1329 irqreturn_t ret = IRQ_NONE;
1330
1331 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1332 tmp = I915_READ(GEN8_GT_IIR(0));
1333 if (tmp) {
1334 ret = IRQ_HANDLED;
1335 rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1336 bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1337 if (rcs & GT_RENDER_USER_INTERRUPT)
1338 notify_ring(dev, &dev_priv->ring[RCS]);
1339 if (bcs & GT_RENDER_USER_INTERRUPT)
1340 notify_ring(dev, &dev_priv->ring[BCS]);
1341 I915_WRITE(GEN8_GT_IIR(0), tmp);
1342 } else
1343 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1344 }
1345
1346 if (master_ctl & GEN8_GT_VCS1_IRQ) {
1347 tmp = I915_READ(GEN8_GT_IIR(1));
1348 if (tmp) {
1349 ret = IRQ_HANDLED;
1350 vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1351 if (vcs & GT_RENDER_USER_INTERRUPT)
1352 notify_ring(dev, &dev_priv->ring[VCS]);
1353 I915_WRITE(GEN8_GT_IIR(1), tmp);
1354 } else
1355 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1356 }
1357
1358 if (master_ctl & GEN8_GT_VECS_IRQ) {
1359 tmp = I915_READ(GEN8_GT_IIR(3));
1360 if (tmp) {
1361 ret = IRQ_HANDLED;
1362 vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1363 if (vcs & GT_RENDER_USER_INTERRUPT)
1364 notify_ring(dev, &dev_priv->ring[VECS]);
1365 I915_WRITE(GEN8_GT_IIR(3), tmp);
1366 } else
1367 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1368 }
1369
1370 return ret;
1371 }
1372
1373 #define HPD_STORM_DETECT_PERIOD 1000
1374 #define HPD_STORM_THRESHOLD 5
1375
1376 static inline void intel_hpd_irq_handler(struct drm_device *dev,
1377 u32 hotplug_trigger,
1378 const u32 *hpd)
1379 {
1380 struct drm_i915_private *dev_priv = dev->dev_private;
1381 int i;
1382 bool storm_detected = false;
1383
1384 if (!hotplug_trigger)
1385 return;
1386
1387 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1388 hotplug_trigger);
1389
1390 spin_lock(&dev_priv->irq_lock);
1391 for (i = 1; i < HPD_NUM_PINS; i++) {
1392
1393 WARN_ONCE(hpd[i] & hotplug_trigger &&
1394 dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED,
1395 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1396 hotplug_trigger, i, hpd[i]);
1397
1398 if (!(hpd[i] & hotplug_trigger) ||
1399 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1400 continue;
1401
1402 dev_priv->hpd_event_bits |= (1 << i);
1403 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1404 dev_priv->hpd_stats[i].hpd_last_jiffies
1405 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1406 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1407 dev_priv->hpd_stats[i].hpd_cnt = 0;
1408 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1409 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1410 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1411 dev_priv->hpd_event_bits &= ~(1 << i);
1412 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1413 storm_detected = true;
1414 } else {
1415 dev_priv->hpd_stats[i].hpd_cnt++;
1416 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1417 dev_priv->hpd_stats[i].hpd_cnt);
1418 }
1419 }
1420
1421 if (storm_detected)
1422 dev_priv->display.hpd_irq_setup(dev);
1423 spin_unlock(&dev_priv->irq_lock);
1424
1425 /*
1426 * Our hotplug handler can grab modeset locks (by calling down into the
1427 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1428 * queue for otherwise the flush_work in the pageflip code will
1429 * deadlock.
1430 */
1431 schedule_work(&dev_priv->hotplug_work);
1432 }
1433
1434 static void gmbus_irq_handler(struct drm_device *dev)
1435 {
1436 struct drm_i915_private *dev_priv = dev->dev_private;
1437
1438 wake_up_all(&dev_priv->gmbus_wait_queue);
1439 }
1440
1441 static void dp_aux_irq_handler(struct drm_device *dev)
1442 {
1443 struct drm_i915_private *dev_priv = dev->dev_private;
1444
1445 wake_up_all(&dev_priv->gmbus_wait_queue);
1446 }
1447
1448 #if defined(CONFIG_DEBUG_FS)
1449 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1450 uint32_t crc0, uint32_t crc1,
1451 uint32_t crc2, uint32_t crc3,
1452 uint32_t crc4)
1453 {
1454 struct drm_i915_private *dev_priv = dev->dev_private;
1455 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1456 struct intel_pipe_crc_entry *entry;
1457 int head, tail;
1458
1459 spin_lock(&pipe_crc->lock);
1460
1461 if (!pipe_crc->entries) {
1462 spin_unlock(&pipe_crc->lock);
1463 DRM_ERROR("spurious interrupt\n");
1464 return;
1465 }
1466
1467 head = pipe_crc->head;
1468 tail = pipe_crc->tail;
1469
1470 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1471 spin_unlock(&pipe_crc->lock);
1472 DRM_ERROR("CRC buffer overflowing\n");
1473 return;
1474 }
1475
1476 entry = &pipe_crc->entries[head];
1477
1478 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1479 entry->crc[0] = crc0;
1480 entry->crc[1] = crc1;
1481 entry->crc[2] = crc2;
1482 entry->crc[3] = crc3;
1483 entry->crc[4] = crc4;
1484
1485 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1486 pipe_crc->head = head;
1487
1488 spin_unlock(&pipe_crc->lock);
1489
1490 wake_up_interruptible(&pipe_crc->wq);
1491 }
1492 #else
1493 static inline void
1494 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1495 uint32_t crc0, uint32_t crc1,
1496 uint32_t crc2, uint32_t crc3,
1497 uint32_t crc4) {}
1498 #endif
1499
1500
1501 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1502 {
1503 struct drm_i915_private *dev_priv = dev->dev_private;
1504
1505 display_pipe_crc_irq_handler(dev, pipe,
1506 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1507 0, 0, 0, 0);
1508 }
1509
1510 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1511 {
1512 struct drm_i915_private *dev_priv = dev->dev_private;
1513
1514 display_pipe_crc_irq_handler(dev, pipe,
1515 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1516 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1517 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1518 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1519 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1520 }
1521
1522 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1523 {
1524 struct drm_i915_private *dev_priv = dev->dev_private;
1525 uint32_t res1, res2;
1526
1527 if (INTEL_INFO(dev)->gen >= 3)
1528 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1529 else
1530 res1 = 0;
1531
1532 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1533 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1534 else
1535 res2 = 0;
1536
1537 display_pipe_crc_irq_handler(dev, pipe,
1538 I915_READ(PIPE_CRC_RES_RED(pipe)),
1539 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1540 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1541 res1, res2);
1542 }
1543
1544 /* The RPS events need forcewake, so we add them to a work queue and mask their
1545 * IMR bits until the work is done. Other interrupts can be processed without
1546 * the work queue. */
1547 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1548 {
1549 if (pm_iir & dev_priv->pm_rps_events) {
1550 spin_lock(&dev_priv->irq_lock);
1551 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1552 snb_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1553 spin_unlock(&dev_priv->irq_lock);
1554
1555 queue_work(dev_priv->wq, &dev_priv->rps.work);
1556 }
1557
1558 if (HAS_VEBOX(dev_priv->dev)) {
1559 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1560 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1561
1562 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1563 i915_handle_error(dev_priv->dev, false,
1564 "VEBOX CS error interrupt 0x%08x",
1565 pm_iir);
1566 }
1567 }
1568 }
1569
1570 static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1571 {
1572 struct drm_i915_private *dev_priv = dev->dev_private;
1573 u32 pipe_stats[I915_MAX_PIPES] = { };
1574 int pipe;
1575
1576 spin_lock(&dev_priv->irq_lock);
1577 for_each_pipe(pipe) {
1578 int reg;
1579 u32 mask, iir_bit = 0;
1580
1581 /*
1582 * PIPESTAT bits get signalled even when the interrupt is
1583 * disabled with the mask bits, and some of the status bits do
1584 * not generate interrupts at all (like the underrun bit). Hence
1585 * we need to be careful that we only handle what we want to
1586 * handle.
1587 */
1588 mask = 0;
1589 if (__cpu_fifo_underrun_reporting_enabled(dev, pipe))
1590 mask |= PIPE_FIFO_UNDERRUN_STATUS;
1591
1592 switch (pipe) {
1593 case PIPE_A:
1594 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1595 break;
1596 case PIPE_B:
1597 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1598 break;
1599 }
1600 if (iir & iir_bit)
1601 mask |= dev_priv->pipestat_irq_mask[pipe];
1602
1603 if (!mask)
1604 continue;
1605
1606 reg = PIPESTAT(pipe);
1607 mask |= PIPESTAT_INT_ENABLE_MASK;
1608 pipe_stats[pipe] = I915_READ(reg) & mask;
1609
1610 /*
1611 * Clear the PIPE*STAT regs before the IIR
1612 */
1613 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1614 PIPESTAT_INT_STATUS_MASK))
1615 I915_WRITE(reg, pipe_stats[pipe]);
1616 }
1617 spin_unlock(&dev_priv->irq_lock);
1618
1619 for_each_pipe(pipe) {
1620 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1621 drm_handle_vblank(dev, pipe);
1622
1623 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
1624 intel_prepare_page_flip(dev, pipe);
1625 intel_finish_page_flip(dev, pipe);
1626 }
1627
1628 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1629 i9xx_pipe_crc_irq_handler(dev, pipe);
1630
1631 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
1632 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1633 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
1634 }
1635
1636 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1637 gmbus_irq_handler(dev);
1638 }
1639
1640 static void i9xx_hpd_irq_handler(struct drm_device *dev)
1641 {
1642 struct drm_i915_private *dev_priv = dev->dev_private;
1643 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1644
1645 if (IS_G4X(dev)) {
1646 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1647
1648 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_g4x);
1649 } else {
1650 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1651
1652 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1653 }
1654
1655 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) &&
1656 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1657 dp_aux_irq_handler(dev);
1658
1659 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1660 /*
1661 * Make sure hotplug status is cleared before we clear IIR, or else we
1662 * may miss hotplug events.
1663 */
1664 POSTING_READ(PORT_HOTPLUG_STAT);
1665 }
1666
1667 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1668 {
1669 struct drm_device *dev = (struct drm_device *) arg;
1670 struct drm_i915_private *dev_priv = dev->dev_private;
1671 u32 iir, gt_iir, pm_iir;
1672 irqreturn_t ret = IRQ_NONE;
1673
1674 while (true) {
1675 iir = I915_READ(VLV_IIR);
1676 gt_iir = I915_READ(GTIIR);
1677 pm_iir = I915_READ(GEN6_PMIIR);
1678
1679 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1680 goto out;
1681
1682 ret = IRQ_HANDLED;
1683
1684 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1685
1686 valleyview_pipestat_irq_handler(dev, iir);
1687
1688 /* Consume port. Then clear IIR or we'll miss events */
1689 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1690 i9xx_hpd_irq_handler(dev);
1691
1692 if (pm_iir)
1693 gen6_rps_irq_handler(dev_priv, pm_iir);
1694
1695 I915_WRITE(GTIIR, gt_iir);
1696 I915_WRITE(GEN6_PMIIR, pm_iir);
1697 I915_WRITE(VLV_IIR, iir);
1698 }
1699
1700 out:
1701 return ret;
1702 }
1703
1704 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1705 {
1706 struct drm_i915_private *dev_priv = dev->dev_private;
1707 int pipe;
1708 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1709
1710 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1711
1712 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1713 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1714 SDE_AUDIO_POWER_SHIFT);
1715 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1716 port_name(port));
1717 }
1718
1719 if (pch_iir & SDE_AUX_MASK)
1720 dp_aux_irq_handler(dev);
1721
1722 if (pch_iir & SDE_GMBUS)
1723 gmbus_irq_handler(dev);
1724
1725 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1726 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1727
1728 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1729 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1730
1731 if (pch_iir & SDE_POISON)
1732 DRM_ERROR("PCH poison interrupt\n");
1733
1734 if (pch_iir & SDE_FDI_MASK)
1735 for_each_pipe(pipe)
1736 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1737 pipe_name(pipe),
1738 I915_READ(FDI_RX_IIR(pipe)));
1739
1740 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1741 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1742
1743 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1744 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1745
1746 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1747 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1748 false))
1749 DRM_ERROR("PCH transcoder A FIFO underrun\n");
1750
1751 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1752 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1753 false))
1754 DRM_ERROR("PCH transcoder B FIFO underrun\n");
1755 }
1756
1757 static void ivb_err_int_handler(struct drm_device *dev)
1758 {
1759 struct drm_i915_private *dev_priv = dev->dev_private;
1760 u32 err_int = I915_READ(GEN7_ERR_INT);
1761 enum pipe pipe;
1762
1763 if (err_int & ERR_INT_POISON)
1764 DRM_ERROR("Poison interrupt\n");
1765
1766 for_each_pipe(pipe) {
1767 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
1768 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1769 false))
1770 DRM_ERROR("Pipe %c FIFO underrun\n",
1771 pipe_name(pipe));
1772 }
1773
1774 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1775 if (IS_IVYBRIDGE(dev))
1776 ivb_pipe_crc_irq_handler(dev, pipe);
1777 else
1778 hsw_pipe_crc_irq_handler(dev, pipe);
1779 }
1780 }
1781
1782 I915_WRITE(GEN7_ERR_INT, err_int);
1783 }
1784
1785 static void cpt_serr_int_handler(struct drm_device *dev)
1786 {
1787 struct drm_i915_private *dev_priv = dev->dev_private;
1788 u32 serr_int = I915_READ(SERR_INT);
1789
1790 if (serr_int & SERR_INT_POISON)
1791 DRM_ERROR("PCH poison interrupt\n");
1792
1793 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1794 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1795 false))
1796 DRM_ERROR("PCH transcoder A FIFO underrun\n");
1797
1798 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1799 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1800 false))
1801 DRM_ERROR("PCH transcoder B FIFO underrun\n");
1802
1803 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1804 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1805 false))
1806 DRM_ERROR("PCH transcoder C FIFO underrun\n");
1807
1808 I915_WRITE(SERR_INT, serr_int);
1809 }
1810
1811 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1812 {
1813 struct drm_i915_private *dev_priv = dev->dev_private;
1814 int pipe;
1815 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1816
1817 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1818
1819 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1820 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1821 SDE_AUDIO_POWER_SHIFT_CPT);
1822 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1823 port_name(port));
1824 }
1825
1826 if (pch_iir & SDE_AUX_MASK_CPT)
1827 dp_aux_irq_handler(dev);
1828
1829 if (pch_iir & SDE_GMBUS_CPT)
1830 gmbus_irq_handler(dev);
1831
1832 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1833 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1834
1835 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1836 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1837
1838 if (pch_iir & SDE_FDI_MASK_CPT)
1839 for_each_pipe(pipe)
1840 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1841 pipe_name(pipe),
1842 I915_READ(FDI_RX_IIR(pipe)));
1843
1844 if (pch_iir & SDE_ERROR_CPT)
1845 cpt_serr_int_handler(dev);
1846 }
1847
1848 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1849 {
1850 struct drm_i915_private *dev_priv = dev->dev_private;
1851 enum pipe pipe;
1852
1853 if (de_iir & DE_AUX_CHANNEL_A)
1854 dp_aux_irq_handler(dev);
1855
1856 if (de_iir & DE_GSE)
1857 intel_opregion_asle_intr(dev);
1858
1859 if (de_iir & DE_POISON)
1860 DRM_ERROR("Poison interrupt\n");
1861
1862 for_each_pipe(pipe) {
1863 if (de_iir & DE_PIPE_VBLANK(pipe))
1864 drm_handle_vblank(dev, pipe);
1865
1866 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
1867 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1868 DRM_ERROR("Pipe %c FIFO underrun\n",
1869 pipe_name(pipe));
1870
1871 if (de_iir & DE_PIPE_CRC_DONE(pipe))
1872 i9xx_pipe_crc_irq_handler(dev, pipe);
1873
1874 /* plane/pipes map 1:1 on ilk+ */
1875 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
1876 intel_prepare_page_flip(dev, pipe);
1877 intel_finish_page_flip_plane(dev, pipe);
1878 }
1879 }
1880
1881 /* check event from PCH */
1882 if (de_iir & DE_PCH_EVENT) {
1883 u32 pch_iir = I915_READ(SDEIIR);
1884
1885 if (HAS_PCH_CPT(dev))
1886 cpt_irq_handler(dev, pch_iir);
1887 else
1888 ibx_irq_handler(dev, pch_iir);
1889
1890 /* should clear PCH hotplug event before clear CPU irq */
1891 I915_WRITE(SDEIIR, pch_iir);
1892 }
1893
1894 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1895 ironlake_rps_change_irq_handler(dev);
1896 }
1897
1898 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
1899 {
1900 struct drm_i915_private *dev_priv = dev->dev_private;
1901 enum pipe pipe;
1902
1903 if (de_iir & DE_ERR_INT_IVB)
1904 ivb_err_int_handler(dev);
1905
1906 if (de_iir & DE_AUX_CHANNEL_A_IVB)
1907 dp_aux_irq_handler(dev);
1908
1909 if (de_iir & DE_GSE_IVB)
1910 intel_opregion_asle_intr(dev);
1911
1912 for_each_pipe(pipe) {
1913 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
1914 drm_handle_vblank(dev, pipe);
1915
1916 /* plane/pipes map 1:1 on ilk+ */
1917 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
1918 intel_prepare_page_flip(dev, pipe);
1919 intel_finish_page_flip_plane(dev, pipe);
1920 }
1921 }
1922
1923 /* check event from PCH */
1924 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1925 u32 pch_iir = I915_READ(SDEIIR);
1926
1927 cpt_irq_handler(dev, pch_iir);
1928
1929 /* clear PCH hotplug event before clear CPU irq */
1930 I915_WRITE(SDEIIR, pch_iir);
1931 }
1932 }
1933
1934 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
1935 {
1936 struct drm_device *dev = (struct drm_device *) arg;
1937 struct drm_i915_private *dev_priv = dev->dev_private;
1938 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
1939 irqreturn_t ret = IRQ_NONE;
1940
1941 /* We get interrupts on unclaimed registers, so check for this before we
1942 * do any I915_{READ,WRITE}. */
1943 intel_uncore_check_errors(dev);
1944
1945 /* disable master interrupt before clearing iir */
1946 de_ier = I915_READ(DEIER);
1947 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
1948 POSTING_READ(DEIER);
1949
1950 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1951 * interrupts will will be stored on its back queue, and then we'll be
1952 * able to process them after we restore SDEIER (as soon as we restore
1953 * it, we'll get an interrupt if SDEIIR still has something to process
1954 * due to its back queue). */
1955 if (!HAS_PCH_NOP(dev)) {
1956 sde_ier = I915_READ(SDEIER);
1957 I915_WRITE(SDEIER, 0);
1958 POSTING_READ(SDEIER);
1959 }
1960
1961 gt_iir = I915_READ(GTIIR);
1962 if (gt_iir) {
1963 if (INTEL_INFO(dev)->gen >= 6)
1964 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1965 else
1966 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1967 I915_WRITE(GTIIR, gt_iir);
1968 ret = IRQ_HANDLED;
1969 }
1970
1971 de_iir = I915_READ(DEIIR);
1972 if (de_iir) {
1973 if (INTEL_INFO(dev)->gen >= 7)
1974 ivb_display_irq_handler(dev, de_iir);
1975 else
1976 ilk_display_irq_handler(dev, de_iir);
1977 I915_WRITE(DEIIR, de_iir);
1978 ret = IRQ_HANDLED;
1979 }
1980
1981 if (INTEL_INFO(dev)->gen >= 6) {
1982 u32 pm_iir = I915_READ(GEN6_PMIIR);
1983 if (pm_iir) {
1984 gen6_rps_irq_handler(dev_priv, pm_iir);
1985 I915_WRITE(GEN6_PMIIR, pm_iir);
1986 ret = IRQ_HANDLED;
1987 }
1988 }
1989
1990 I915_WRITE(DEIER, de_ier);
1991 POSTING_READ(DEIER);
1992 if (!HAS_PCH_NOP(dev)) {
1993 I915_WRITE(SDEIER, sde_ier);
1994 POSTING_READ(SDEIER);
1995 }
1996
1997 return ret;
1998 }
1999
2000 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2001 {
2002 struct drm_device *dev = arg;
2003 struct drm_i915_private *dev_priv = dev->dev_private;
2004 u32 master_ctl;
2005 irqreturn_t ret = IRQ_NONE;
2006 uint32_t tmp = 0;
2007 enum pipe pipe;
2008
2009 master_ctl = I915_READ(GEN8_MASTER_IRQ);
2010 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2011 if (!master_ctl)
2012 return IRQ_NONE;
2013
2014 I915_WRITE(GEN8_MASTER_IRQ, 0);
2015 POSTING_READ(GEN8_MASTER_IRQ);
2016
2017 ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
2018
2019 if (master_ctl & GEN8_DE_MISC_IRQ) {
2020 tmp = I915_READ(GEN8_DE_MISC_IIR);
2021 if (tmp & GEN8_DE_MISC_GSE)
2022 intel_opregion_asle_intr(dev);
2023 else if (tmp)
2024 DRM_ERROR("Unexpected DE Misc interrupt\n");
2025 else
2026 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2027
2028 if (tmp) {
2029 I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2030 ret = IRQ_HANDLED;
2031 }
2032 }
2033
2034 if (master_ctl & GEN8_DE_PORT_IRQ) {
2035 tmp = I915_READ(GEN8_DE_PORT_IIR);
2036 if (tmp & GEN8_AUX_CHANNEL_A)
2037 dp_aux_irq_handler(dev);
2038 else if (tmp)
2039 DRM_ERROR("Unexpected DE Port interrupt\n");
2040 else
2041 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2042
2043 if (tmp) {
2044 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2045 ret = IRQ_HANDLED;
2046 }
2047 }
2048
2049 for_each_pipe(pipe) {
2050 uint32_t pipe_iir;
2051
2052 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2053 continue;
2054
2055 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2056 if (pipe_iir & GEN8_PIPE_VBLANK)
2057 drm_handle_vblank(dev, pipe);
2058
2059 if (pipe_iir & GEN8_PIPE_FLIP_DONE) {
2060 intel_prepare_page_flip(dev, pipe);
2061 intel_finish_page_flip_plane(dev, pipe);
2062 }
2063
2064 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2065 hsw_pipe_crc_irq_handler(dev, pipe);
2066
2067 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
2068 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
2069 false))
2070 DRM_ERROR("Pipe %c FIFO underrun\n",
2071 pipe_name(pipe));
2072 }
2073
2074 if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
2075 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2076 pipe_name(pipe),
2077 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2078 }
2079
2080 if (pipe_iir) {
2081 ret = IRQ_HANDLED;
2082 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2083 } else
2084 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2085 }
2086
2087 if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
2088 /*
2089 * FIXME(BDW): Assume for now that the new interrupt handling
2090 * scheme also closed the SDE interrupt handling race we've seen
2091 * on older pch-split platforms. But this needs testing.
2092 */
2093 u32 pch_iir = I915_READ(SDEIIR);
2094
2095 cpt_irq_handler(dev, pch_iir);
2096
2097 if (pch_iir) {
2098 I915_WRITE(SDEIIR, pch_iir);
2099 ret = IRQ_HANDLED;
2100 }
2101 }
2102
2103 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2104 POSTING_READ(GEN8_MASTER_IRQ);
2105
2106 return ret;
2107 }
2108
2109 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2110 bool reset_completed)
2111 {
2112 struct intel_ring_buffer *ring;
2113 int i;
2114
2115 /*
2116 * Notify all waiters for GPU completion events that reset state has
2117 * been changed, and that they need to restart their wait after
2118 * checking for potential errors (and bail out to drop locks if there is
2119 * a gpu reset pending so that i915_error_work_func can acquire them).
2120 */
2121
2122 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2123 for_each_ring(ring, dev_priv, i)
2124 wake_up_all(&ring->irq_queue);
2125
2126 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2127 wake_up_all(&dev_priv->pending_flip_queue);
2128
2129 /*
2130 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2131 * reset state is cleared.
2132 */
2133 if (reset_completed)
2134 wake_up_all(&dev_priv->gpu_error.reset_queue);
2135 }
2136
2137 /**
2138 * i915_error_work_func - do process context error handling work
2139 * @work: work struct
2140 *
2141 * Fire an error uevent so userspace can see that a hang or error
2142 * was detected.
2143 */
2144 static void i915_error_work_func(struct work_struct *work)
2145 {
2146 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
2147 work);
2148 struct drm_i915_private *dev_priv =
2149 container_of(error, struct drm_i915_private, gpu_error);
2150 struct drm_device *dev = dev_priv->dev;
2151 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2152 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2153 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2154 int ret;
2155
2156 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2157
2158 /*
2159 * Note that there's only one work item which does gpu resets, so we
2160 * need not worry about concurrent gpu resets potentially incrementing
2161 * error->reset_counter twice. We only need to take care of another
2162 * racing irq/hangcheck declaring the gpu dead for a second time. A
2163 * quick check for that is good enough: schedule_work ensures the
2164 * correct ordering between hang detection and this work item, and since
2165 * the reset in-progress bit is only ever set by code outside of this
2166 * work we don't need to worry about any other races.
2167 */
2168 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2169 DRM_DEBUG_DRIVER("resetting chip\n");
2170 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2171 reset_event);
2172
2173 /*
2174 * All state reset _must_ be completed before we update the
2175 * reset counter, for otherwise waiters might miss the reset
2176 * pending state and not properly drop locks, resulting in
2177 * deadlocks with the reset work.
2178 */
2179 ret = i915_reset(dev);
2180
2181 intel_display_handle_reset(dev);
2182
2183 if (ret == 0) {
2184 /*
2185 * After all the gem state is reset, increment the reset
2186 * counter and wake up everyone waiting for the reset to
2187 * complete.
2188 *
2189 * Since unlock operations are a one-sided barrier only,
2190 * we need to insert a barrier here to order any seqno
2191 * updates before
2192 * the counter increment.
2193 */
2194 smp_mb__before_atomic_inc();
2195 atomic_inc(&dev_priv->gpu_error.reset_counter);
2196
2197 kobject_uevent_env(&dev->primary->kdev->kobj,
2198 KOBJ_CHANGE, reset_done_event);
2199 } else {
2200 atomic_set_mask(I915_WEDGED, &error->reset_counter);
2201 }
2202
2203 /*
2204 * Note: The wake_up also serves as a memory barrier so that
2205 * waiters see the update value of the reset counter atomic_t.
2206 */
2207 i915_error_wake_up(dev_priv, true);
2208 }
2209 }
2210
2211 static void i915_report_and_clear_eir(struct drm_device *dev)
2212 {
2213 struct drm_i915_private *dev_priv = dev->dev_private;
2214 uint32_t instdone[I915_NUM_INSTDONE_REG];
2215 u32 eir = I915_READ(EIR);
2216 int pipe, i;
2217
2218 if (!eir)
2219 return;
2220
2221 pr_err("render error detected, EIR: 0x%08x\n", eir);
2222
2223 i915_get_extra_instdone(dev, instdone);
2224
2225 if (IS_G4X(dev)) {
2226 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2227 u32 ipeir = I915_READ(IPEIR_I965);
2228
2229 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2230 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2231 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2232 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2233 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2234 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2235 I915_WRITE(IPEIR_I965, ipeir);
2236 POSTING_READ(IPEIR_I965);
2237 }
2238 if (eir & GM45_ERROR_PAGE_TABLE) {
2239 u32 pgtbl_err = I915_READ(PGTBL_ER);
2240 pr_err("page table error\n");
2241 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2242 I915_WRITE(PGTBL_ER, pgtbl_err);
2243 POSTING_READ(PGTBL_ER);
2244 }
2245 }
2246
2247 if (!IS_GEN2(dev)) {
2248 if (eir & I915_ERROR_PAGE_TABLE) {
2249 u32 pgtbl_err = I915_READ(PGTBL_ER);
2250 pr_err("page table error\n");
2251 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2252 I915_WRITE(PGTBL_ER, pgtbl_err);
2253 POSTING_READ(PGTBL_ER);
2254 }
2255 }
2256
2257 if (eir & I915_ERROR_MEMORY_REFRESH) {
2258 pr_err("memory refresh error:\n");
2259 for_each_pipe(pipe)
2260 pr_err("pipe %c stat: 0x%08x\n",
2261 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2262 /* pipestat has already been acked */
2263 }
2264 if (eir & I915_ERROR_INSTRUCTION) {
2265 pr_err("instruction error\n");
2266 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
2267 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2268 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2269 if (INTEL_INFO(dev)->gen < 4) {
2270 u32 ipeir = I915_READ(IPEIR);
2271
2272 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2273 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
2274 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
2275 I915_WRITE(IPEIR, ipeir);
2276 POSTING_READ(IPEIR);
2277 } else {
2278 u32 ipeir = I915_READ(IPEIR_I965);
2279
2280 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2281 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2282 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2283 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2284 I915_WRITE(IPEIR_I965, ipeir);
2285 POSTING_READ(IPEIR_I965);
2286 }
2287 }
2288
2289 I915_WRITE(EIR, eir);
2290 POSTING_READ(EIR);
2291 eir = I915_READ(EIR);
2292 if (eir) {
2293 /*
2294 * some errors might have become stuck,
2295 * mask them.
2296 */
2297 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2298 I915_WRITE(EMR, I915_READ(EMR) | eir);
2299 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2300 }
2301 }
2302
2303 /**
2304 * i915_handle_error - handle an error interrupt
2305 * @dev: drm device
2306 *
2307 * Do some basic checking of regsiter state at error interrupt time and
2308 * dump it to the syslog. Also call i915_capture_error_state() to make
2309 * sure we get a record and make it available in debugfs. Fire a uevent
2310 * so userspace knows something bad happened (should trigger collection
2311 * of a ring dump etc.).
2312 */
2313 void i915_handle_error(struct drm_device *dev, bool wedged,
2314 const char *fmt, ...)
2315 {
2316 struct drm_i915_private *dev_priv = dev->dev_private;
2317 va_list args;
2318 char error_msg[80];
2319
2320 va_start(args, fmt);
2321 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2322 va_end(args);
2323
2324 i915_capture_error_state(dev, wedged, error_msg);
2325 i915_report_and_clear_eir(dev);
2326
2327 if (wedged) {
2328 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2329 &dev_priv->gpu_error.reset_counter);
2330
2331 /*
2332 * Wakeup waiting processes so that the reset work function
2333 * i915_error_work_func doesn't deadlock trying to grab various
2334 * locks. By bumping the reset counter first, the woken
2335 * processes will see a reset in progress and back off,
2336 * releasing their locks and then wait for the reset completion.
2337 * We must do this for _all_ gpu waiters that might hold locks
2338 * that the reset work needs to acquire.
2339 *
2340 * Note: The wake_up serves as the required memory barrier to
2341 * ensure that the waiters see the updated value of the reset
2342 * counter atomic_t.
2343 */
2344 i915_error_wake_up(dev_priv, false);
2345 }
2346
2347 /*
2348 * Our reset work can grab modeset locks (since it needs to reset the
2349 * state of outstanding pagelips). Hence it must not be run on our own
2350 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2351 * code will deadlock.
2352 */
2353 schedule_work(&dev_priv->gpu_error.work);
2354 }
2355
2356 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
2357 {
2358 struct drm_i915_private *dev_priv = dev->dev_private;
2359 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2361 struct drm_i915_gem_object *obj;
2362 struct intel_unpin_work *work;
2363 unsigned long flags;
2364 bool stall_detected;
2365
2366 /* Ignore early vblank irqs */
2367 if (intel_crtc == NULL)
2368 return;
2369
2370 spin_lock_irqsave(&dev->event_lock, flags);
2371 work = intel_crtc->unpin_work;
2372
2373 if (work == NULL ||
2374 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2375 !work->enable_stall_check) {
2376 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2377 spin_unlock_irqrestore(&dev->event_lock, flags);
2378 return;
2379 }
2380
2381 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2382 obj = work->pending_flip_obj;
2383 if (INTEL_INFO(dev)->gen >= 4) {
2384 int dspsurf = DSPSURF(intel_crtc->plane);
2385 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
2386 i915_gem_obj_ggtt_offset(obj);
2387 } else {
2388 int dspaddr = DSPADDR(intel_crtc->plane);
2389 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
2390 crtc->y * crtc->fb->pitches[0] +
2391 crtc->x * crtc->fb->bits_per_pixel/8);
2392 }
2393
2394 spin_unlock_irqrestore(&dev->event_lock, flags);
2395
2396 if (stall_detected) {
2397 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2398 intel_prepare_page_flip(dev, intel_crtc->plane);
2399 }
2400 }
2401
2402 /* Called from drm generic code, passed 'crtc' which
2403 * we use as a pipe index
2404 */
2405 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2406 {
2407 struct drm_i915_private *dev_priv = dev->dev_private;
2408 unsigned long irqflags;
2409
2410 if (!i915_pipe_enabled(dev, pipe))
2411 return -EINVAL;
2412
2413 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2414 if (INTEL_INFO(dev)->gen >= 4)
2415 i915_enable_pipestat(dev_priv, pipe,
2416 PIPE_START_VBLANK_INTERRUPT_STATUS);
2417 else
2418 i915_enable_pipestat(dev_priv, pipe,
2419 PIPE_VBLANK_INTERRUPT_STATUS);
2420
2421 /* maintain vblank delivery even in deep C-states */
2422 if (INTEL_INFO(dev)->gen == 3)
2423 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
2424 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2425
2426 return 0;
2427 }
2428
2429 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2430 {
2431 struct drm_i915_private *dev_priv = dev->dev_private;
2432 unsigned long irqflags;
2433 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2434 DE_PIPE_VBLANK(pipe);
2435
2436 if (!i915_pipe_enabled(dev, pipe))
2437 return -EINVAL;
2438
2439 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2440 ironlake_enable_display_irq(dev_priv, bit);
2441 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2442
2443 return 0;
2444 }
2445
2446 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2447 {
2448 struct drm_i915_private *dev_priv = dev->dev_private;
2449 unsigned long irqflags;
2450
2451 if (!i915_pipe_enabled(dev, pipe))
2452 return -EINVAL;
2453
2454 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2455 i915_enable_pipestat(dev_priv, pipe,
2456 PIPE_START_VBLANK_INTERRUPT_STATUS);
2457 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2458
2459 return 0;
2460 }
2461
2462 static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2463 {
2464 struct drm_i915_private *dev_priv = dev->dev_private;
2465 unsigned long irqflags;
2466
2467 if (!i915_pipe_enabled(dev, pipe))
2468 return -EINVAL;
2469
2470 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2471 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2472 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2473 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2474 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2475 return 0;
2476 }
2477
2478 /* Called from drm generic code, passed 'crtc' which
2479 * we use as a pipe index
2480 */
2481 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2482 {
2483 struct drm_i915_private *dev_priv = dev->dev_private;
2484 unsigned long irqflags;
2485
2486 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2487 if (INTEL_INFO(dev)->gen == 3)
2488 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
2489
2490 i915_disable_pipestat(dev_priv, pipe,
2491 PIPE_VBLANK_INTERRUPT_STATUS |
2492 PIPE_START_VBLANK_INTERRUPT_STATUS);
2493 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2494 }
2495
2496 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2497 {
2498 struct drm_i915_private *dev_priv = dev->dev_private;
2499 unsigned long irqflags;
2500 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2501 DE_PIPE_VBLANK(pipe);
2502
2503 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2504 ironlake_disable_display_irq(dev_priv, bit);
2505 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2506 }
2507
2508 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2509 {
2510 struct drm_i915_private *dev_priv = dev->dev_private;
2511 unsigned long irqflags;
2512
2513 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2514 i915_disable_pipestat(dev_priv, pipe,
2515 PIPE_START_VBLANK_INTERRUPT_STATUS);
2516 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2517 }
2518
2519 static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2520 {
2521 struct drm_i915_private *dev_priv = dev->dev_private;
2522 unsigned long irqflags;
2523
2524 if (!i915_pipe_enabled(dev, pipe))
2525 return;
2526
2527 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2528 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2529 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2530 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2531 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2532 }
2533
2534 static u32
2535 ring_last_seqno(struct intel_ring_buffer *ring)
2536 {
2537 return list_entry(ring->request_list.prev,
2538 struct drm_i915_gem_request, list)->seqno;
2539 }
2540
2541 static bool
2542 ring_idle(struct intel_ring_buffer *ring, u32 seqno)
2543 {
2544 return (list_empty(&ring->request_list) ||
2545 i915_seqno_passed(seqno, ring_last_seqno(ring)));
2546 }
2547
2548 static bool
2549 ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
2550 {
2551 if (INTEL_INFO(dev)->gen >= 8) {
2552 /*
2553 * FIXME: gen8 semaphore support - currently we don't emit
2554 * semaphores on bdw anyway, but this needs to be addressed when
2555 * we merge that code.
2556 */
2557 return false;
2558 } else {
2559 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2560 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2561 MI_SEMAPHORE_REGISTER);
2562 }
2563 }
2564
2565 static struct intel_ring_buffer *
2566 semaphore_wait_to_signaller_ring(struct intel_ring_buffer *ring, u32 ipehr)
2567 {
2568 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2569 struct intel_ring_buffer *signaller;
2570 int i;
2571
2572 if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
2573 /*
2574 * FIXME: gen8 semaphore support - currently we don't emit
2575 * semaphores on bdw anyway, but this needs to be addressed when
2576 * we merge that code.
2577 */
2578 return NULL;
2579 } else {
2580 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2581
2582 for_each_ring(signaller, dev_priv, i) {
2583 if(ring == signaller)
2584 continue;
2585
2586 if (sync_bits ==
2587 signaller->semaphore_register[ring->id])
2588 return signaller;
2589 }
2590 }
2591
2592 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x\n",
2593 ring->id, ipehr);
2594
2595 return NULL;
2596 }
2597
2598 static struct intel_ring_buffer *
2599 semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
2600 {
2601 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2602 u32 cmd, ipehr, head;
2603 int i;
2604
2605 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2606 if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
2607 return NULL;
2608
2609 /*
2610 * HEAD is likely pointing to the dword after the actual command,
2611 * so scan backwards until we find the MBOX. But limit it to just 3
2612 * dwords. Note that we don't care about ACTHD here since that might
2613 * point at at batch, and semaphores are always emitted into the
2614 * ringbuffer itself.
2615 */
2616 head = I915_READ_HEAD(ring) & HEAD_ADDR;
2617
2618 for (i = 4; i; --i) {
2619 /*
2620 * Be paranoid and presume the hw has gone off into the wild -
2621 * our ring is smaller than what the hardware (and hence
2622 * HEAD_ADDR) allows. Also handles wrap-around.
2623 */
2624 head &= ring->size - 1;
2625
2626 /* This here seems to blow up */
2627 cmd = ioread32(ring->virtual_start + head);
2628 if (cmd == ipehr)
2629 break;
2630
2631 head -= 4;
2632 }
2633
2634 if (!i)
2635 return NULL;
2636
2637 *seqno = ioread32(ring->virtual_start + head + 4) + 1;
2638 return semaphore_wait_to_signaller_ring(ring, ipehr);
2639 }
2640
2641 static int semaphore_passed(struct intel_ring_buffer *ring)
2642 {
2643 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2644 struct intel_ring_buffer *signaller;
2645 u32 seqno, ctl;
2646
2647 ring->hangcheck.deadlock = true;
2648
2649 signaller = semaphore_waits_for(ring, &seqno);
2650 if (signaller == NULL || signaller->hangcheck.deadlock)
2651 return -1;
2652
2653 /* cursory check for an unkickable deadlock */
2654 ctl = I915_READ_CTL(signaller);
2655 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2656 return -1;
2657
2658 return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
2659 }
2660
2661 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2662 {
2663 struct intel_ring_buffer *ring;
2664 int i;
2665
2666 for_each_ring(ring, dev_priv, i)
2667 ring->hangcheck.deadlock = false;
2668 }
2669
2670 static enum intel_ring_hangcheck_action
2671 ring_stuck(struct intel_ring_buffer *ring, u64 acthd)
2672 {
2673 struct drm_device *dev = ring->dev;
2674 struct drm_i915_private *dev_priv = dev->dev_private;
2675 u32 tmp;
2676
2677 if (ring->hangcheck.acthd != acthd)
2678 return HANGCHECK_ACTIVE;
2679
2680 if (IS_GEN2(dev))
2681 return HANGCHECK_HUNG;
2682
2683 /* Is the chip hanging on a WAIT_FOR_EVENT?
2684 * If so we can simply poke the RB_WAIT bit
2685 * and break the hang. This should work on
2686 * all but the second generation chipsets.
2687 */
2688 tmp = I915_READ_CTL(ring);
2689 if (tmp & RING_WAIT) {
2690 i915_handle_error(dev, false,
2691 "Kicking stuck wait on %s",
2692 ring->name);
2693 I915_WRITE_CTL(ring, tmp);
2694 return HANGCHECK_KICK;
2695 }
2696
2697 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2698 switch (semaphore_passed(ring)) {
2699 default:
2700 return HANGCHECK_HUNG;
2701 case 1:
2702 i915_handle_error(dev, false,
2703 "Kicking stuck semaphore on %s",
2704 ring->name);
2705 I915_WRITE_CTL(ring, tmp);
2706 return HANGCHECK_KICK;
2707 case 0:
2708 return HANGCHECK_WAIT;
2709 }
2710 }
2711
2712 return HANGCHECK_HUNG;
2713 }
2714
2715 /**
2716 * This is called when the chip hasn't reported back with completed
2717 * batchbuffers in a long time. We keep track per ring seqno progress and
2718 * if there are no progress, hangcheck score for that ring is increased.
2719 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2720 * we kick the ring. If we see no progress on three subsequent calls
2721 * we assume chip is wedged and try to fix it by resetting the chip.
2722 */
2723 static void i915_hangcheck_elapsed(unsigned long data)
2724 {
2725 struct drm_device *dev = (struct drm_device *)data;
2726 struct drm_i915_private *dev_priv = dev->dev_private;
2727 struct intel_ring_buffer *ring;
2728 int i;
2729 int busy_count = 0, rings_hung = 0;
2730 bool stuck[I915_NUM_RINGS] = { 0 };
2731 #define BUSY 1
2732 #define KICK 5
2733 #define HUNG 20
2734
2735 if (!i915.enable_hangcheck)
2736 return;
2737
2738 for_each_ring(ring, dev_priv, i) {
2739 u64 acthd;
2740 u32 seqno;
2741 bool busy = true;
2742
2743 semaphore_clear_deadlocks(dev_priv);
2744
2745 seqno = ring->get_seqno(ring, false);
2746 acthd = intel_ring_get_active_head(ring);
2747
2748 if (ring->hangcheck.seqno == seqno) {
2749 if (ring_idle(ring, seqno)) {
2750 ring->hangcheck.action = HANGCHECK_IDLE;
2751
2752 if (waitqueue_active(&ring->irq_queue)) {
2753 /* Issue a wake-up to catch stuck h/w. */
2754 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2755 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2756 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2757 ring->name);
2758 else
2759 DRM_INFO("Fake missed irq on %s\n",
2760 ring->name);
2761 wake_up_all(&ring->irq_queue);
2762 }
2763 /* Safeguard against driver failure */
2764 ring->hangcheck.score += BUSY;
2765 } else
2766 busy = false;
2767 } else {
2768 /* We always increment the hangcheck score
2769 * if the ring is busy and still processing
2770 * the same request, so that no single request
2771 * can run indefinitely (such as a chain of
2772 * batches). The only time we do not increment
2773 * the hangcheck score on this ring, if this
2774 * ring is in a legitimate wait for another
2775 * ring. In that case the waiting ring is a
2776 * victim and we want to be sure we catch the
2777 * right culprit. Then every time we do kick
2778 * the ring, add a small increment to the
2779 * score so that we can catch a batch that is
2780 * being repeatedly kicked and so responsible
2781 * for stalling the machine.
2782 */
2783 ring->hangcheck.action = ring_stuck(ring,
2784 acthd);
2785
2786 switch (ring->hangcheck.action) {
2787 case HANGCHECK_IDLE:
2788 case HANGCHECK_WAIT:
2789 break;
2790 case HANGCHECK_ACTIVE:
2791 ring->hangcheck.score += BUSY;
2792 break;
2793 case HANGCHECK_KICK:
2794 ring->hangcheck.score += KICK;
2795 break;
2796 case HANGCHECK_HUNG:
2797 ring->hangcheck.score += HUNG;
2798 stuck[i] = true;
2799 break;
2800 }
2801 }
2802 } else {
2803 ring->hangcheck.action = HANGCHECK_ACTIVE;
2804
2805 /* Gradually reduce the count so that we catch DoS
2806 * attempts across multiple batches.
2807 */
2808 if (ring->hangcheck.score > 0)
2809 ring->hangcheck.score--;
2810 }
2811
2812 ring->hangcheck.seqno = seqno;
2813 ring->hangcheck.acthd = acthd;
2814 busy_count += busy;
2815 }
2816
2817 for_each_ring(ring, dev_priv, i) {
2818 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
2819 DRM_INFO("%s on %s\n",
2820 stuck[i] ? "stuck" : "no progress",
2821 ring->name);
2822 rings_hung++;
2823 }
2824 }
2825
2826 if (rings_hung)
2827 return i915_handle_error(dev, true, "Ring hung");
2828
2829 if (busy_count)
2830 /* Reset timer case chip hangs without another request
2831 * being added */
2832 i915_queue_hangcheck(dev);
2833 }
2834
2835 void i915_queue_hangcheck(struct drm_device *dev)
2836 {
2837 struct drm_i915_private *dev_priv = dev->dev_private;
2838 if (!i915.enable_hangcheck)
2839 return;
2840
2841 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2842 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2843 }
2844
2845 static void ibx_irq_reset(struct drm_device *dev)
2846 {
2847 struct drm_i915_private *dev_priv = dev->dev_private;
2848
2849 if (HAS_PCH_NOP(dev))
2850 return;
2851
2852 GEN5_IRQ_RESET(SDE);
2853
2854 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
2855 I915_WRITE(SERR_INT, 0xffffffff);
2856 }
2857
2858 /*
2859 * SDEIER is also touched by the interrupt handler to work around missed PCH
2860 * interrupts. Hence we can't update it after the interrupt handler is enabled -
2861 * instead we unconditionally enable all PCH interrupt sources here, but then
2862 * only unmask them as needed with SDEIMR.
2863 *
2864 * This function needs to be called before interrupts are enabled.
2865 */
2866 static void ibx_irq_pre_postinstall(struct drm_device *dev)
2867 {
2868 struct drm_i915_private *dev_priv = dev->dev_private;
2869
2870 if (HAS_PCH_NOP(dev))
2871 return;
2872
2873 WARN_ON(I915_READ(SDEIER) != 0);
2874 I915_WRITE(SDEIER, 0xffffffff);
2875 POSTING_READ(SDEIER);
2876 }
2877
2878 static void gen5_gt_irq_reset(struct drm_device *dev)
2879 {
2880 struct drm_i915_private *dev_priv = dev->dev_private;
2881
2882 GEN5_IRQ_RESET(GT);
2883 if (INTEL_INFO(dev)->gen >= 6)
2884 GEN5_IRQ_RESET(GEN6_PM);
2885 }
2886
2887 /* drm_dma.h hooks
2888 */
2889 static void ironlake_irq_reset(struct drm_device *dev)
2890 {
2891 struct drm_i915_private *dev_priv = dev->dev_private;
2892
2893 I915_WRITE(HWSTAM, 0xffffffff);
2894
2895 GEN5_IRQ_RESET(DE);
2896 if (IS_GEN7(dev))
2897 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
2898
2899 gen5_gt_irq_reset(dev);
2900
2901 ibx_irq_reset(dev);
2902 }
2903
2904 static void ironlake_irq_preinstall(struct drm_device *dev)
2905 {
2906 ironlake_irq_reset(dev);
2907 }
2908
2909 static void valleyview_irq_preinstall(struct drm_device *dev)
2910 {
2911 struct drm_i915_private *dev_priv = dev->dev_private;
2912 int pipe;
2913
2914 /* VLV magic */
2915 I915_WRITE(VLV_IMR, 0);
2916 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2917 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2918 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2919
2920 /* and GT */
2921 I915_WRITE(GTIIR, I915_READ(GTIIR));
2922 I915_WRITE(GTIIR, I915_READ(GTIIR));
2923
2924 gen5_gt_irq_reset(dev);
2925
2926 I915_WRITE(DPINVGTT, 0xff);
2927
2928 I915_WRITE(PORT_HOTPLUG_EN, 0);
2929 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2930 for_each_pipe(pipe)
2931 I915_WRITE(PIPESTAT(pipe), 0xffff);
2932 I915_WRITE(VLV_IIR, 0xffffffff);
2933 I915_WRITE(VLV_IMR, 0xffffffff);
2934 I915_WRITE(VLV_IER, 0x0);
2935 POSTING_READ(VLV_IER);
2936 }
2937
2938 static void gen8_irq_reset(struct drm_device *dev)
2939 {
2940 struct drm_i915_private *dev_priv = dev->dev_private;
2941 int pipe;
2942
2943 I915_WRITE(GEN8_MASTER_IRQ, 0);
2944 POSTING_READ(GEN8_MASTER_IRQ);
2945
2946 GEN8_IRQ_RESET_NDX(GT, 0);
2947 GEN8_IRQ_RESET_NDX(GT, 1);
2948 GEN8_IRQ_RESET_NDX(GT, 2);
2949 GEN8_IRQ_RESET_NDX(GT, 3);
2950
2951 for_each_pipe(pipe)
2952 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
2953
2954 GEN5_IRQ_RESET(GEN8_DE_PORT_);
2955 GEN5_IRQ_RESET(GEN8_DE_MISC_);
2956 GEN5_IRQ_RESET(GEN8_PCU_);
2957
2958 ibx_irq_reset(dev);
2959 }
2960
2961 static void gen8_irq_preinstall(struct drm_device *dev)
2962 {
2963 gen8_irq_reset(dev);
2964 }
2965
2966 static void ibx_hpd_irq_setup(struct drm_device *dev)
2967 {
2968 struct drm_i915_private *dev_priv = dev->dev_private;
2969 struct drm_mode_config *mode_config = &dev->mode_config;
2970 struct intel_encoder *intel_encoder;
2971 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
2972
2973 if (HAS_PCH_IBX(dev)) {
2974 hotplug_irqs = SDE_HOTPLUG_MASK;
2975 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2976 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2977 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
2978 } else {
2979 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
2980 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2981 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2982 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
2983 }
2984
2985 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
2986
2987 /*
2988 * Enable digital hotplug on the PCH, and configure the DP short pulse
2989 * duration to 2ms (which is the minimum in the Display Port spec)
2990 *
2991 * This register is the same on all known PCH chips.
2992 */
2993 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2994 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2995 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2996 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2997 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2998 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2999 }
3000
3001 static void ibx_irq_postinstall(struct drm_device *dev)
3002 {
3003 struct drm_i915_private *dev_priv = dev->dev_private;
3004 u32 mask;
3005
3006 if (HAS_PCH_NOP(dev))
3007 return;
3008
3009 if (HAS_PCH_IBX(dev))
3010 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3011 else
3012 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3013
3014 GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
3015 I915_WRITE(SDEIMR, ~mask);
3016 }
3017
3018 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3019 {
3020 struct drm_i915_private *dev_priv = dev->dev_private;
3021 u32 pm_irqs, gt_irqs;
3022
3023 pm_irqs = gt_irqs = 0;
3024
3025 dev_priv->gt_irq_mask = ~0;
3026 if (HAS_L3_DPF(dev)) {
3027 /* L3 parity interrupt is always unmasked. */
3028 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3029 gt_irqs |= GT_PARITY_ERROR(dev);
3030 }
3031
3032 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3033 if (IS_GEN5(dev)) {
3034 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3035 ILK_BSD_USER_INTERRUPT;
3036 } else {
3037 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3038 }
3039
3040 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3041
3042 if (INTEL_INFO(dev)->gen >= 6) {
3043 pm_irqs |= dev_priv->pm_rps_events;
3044
3045 if (HAS_VEBOX(dev))
3046 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3047
3048 dev_priv->pm_irq_mask = 0xffffffff;
3049 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3050 }
3051 }
3052
3053 static int ironlake_irq_postinstall(struct drm_device *dev)
3054 {
3055 unsigned long irqflags;
3056 struct drm_i915_private *dev_priv = dev->dev_private;
3057 u32 display_mask, extra_mask;
3058
3059 if (INTEL_INFO(dev)->gen >= 7) {
3060 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3061 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3062 DE_PLANEB_FLIP_DONE_IVB |
3063 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3064 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3065 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
3066 } else {
3067 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3068 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3069 DE_AUX_CHANNEL_A |
3070 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3071 DE_POISON);
3072 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3073 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
3074 }
3075
3076 dev_priv->irq_mask = ~display_mask;
3077
3078 I915_WRITE(HWSTAM, 0xeffe);
3079
3080 ibx_irq_pre_postinstall(dev);
3081
3082 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3083
3084 gen5_gt_irq_postinstall(dev);
3085
3086 ibx_irq_postinstall(dev);
3087
3088 if (IS_IRONLAKE_M(dev)) {
3089 /* Enable PCU event interrupts
3090 *
3091 * spinlocking not required here for correctness since interrupt
3092 * setup is guaranteed to run in single-threaded context. But we
3093 * need it to make the assert_spin_locked happy. */
3094 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3095 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
3096 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3097 }
3098
3099 return 0;
3100 }
3101
3102 static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3103 {
3104 u32 pipestat_mask;
3105 u32 iir_mask;
3106
3107 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3108 PIPE_FIFO_UNDERRUN_STATUS;
3109
3110 I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3111 I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3112 POSTING_READ(PIPESTAT(PIPE_A));
3113
3114 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3115 PIPE_CRC_DONE_INTERRUPT_STATUS;
3116
3117 i915_enable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3118 PIPE_GMBUS_INTERRUPT_STATUS);
3119 i915_enable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3120
3121 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3122 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3123 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3124 dev_priv->irq_mask &= ~iir_mask;
3125
3126 I915_WRITE(VLV_IIR, iir_mask);
3127 I915_WRITE(VLV_IIR, iir_mask);
3128 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3129 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3130 POSTING_READ(VLV_IER);
3131 }
3132
3133 static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3134 {
3135 u32 pipestat_mask;
3136 u32 iir_mask;
3137
3138 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3139 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3140 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3141
3142 dev_priv->irq_mask |= iir_mask;
3143 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3144 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3145 I915_WRITE(VLV_IIR, iir_mask);
3146 I915_WRITE(VLV_IIR, iir_mask);
3147 POSTING_READ(VLV_IIR);
3148
3149 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3150 PIPE_CRC_DONE_INTERRUPT_STATUS;
3151
3152 i915_disable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3153 PIPE_GMBUS_INTERRUPT_STATUS);
3154 i915_disable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3155
3156 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3157 PIPE_FIFO_UNDERRUN_STATUS;
3158 I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3159 I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3160 POSTING_READ(PIPESTAT(PIPE_A));
3161 }
3162
3163 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3164 {
3165 assert_spin_locked(&dev_priv->irq_lock);
3166
3167 if (dev_priv->display_irqs_enabled)
3168 return;
3169
3170 dev_priv->display_irqs_enabled = true;
3171
3172 if (dev_priv->dev->irq_enabled)
3173 valleyview_display_irqs_install(dev_priv);
3174 }
3175
3176 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3177 {
3178 assert_spin_locked(&dev_priv->irq_lock);
3179
3180 if (!dev_priv->display_irqs_enabled)
3181 return;
3182
3183 dev_priv->display_irqs_enabled = false;
3184
3185 if (dev_priv->dev->irq_enabled)
3186 valleyview_display_irqs_uninstall(dev_priv);
3187 }
3188
3189 static int valleyview_irq_postinstall(struct drm_device *dev)
3190 {
3191 struct drm_i915_private *dev_priv = dev->dev_private;
3192 unsigned long irqflags;
3193
3194 dev_priv->irq_mask = ~0;
3195
3196 I915_WRITE(PORT_HOTPLUG_EN, 0);
3197 POSTING_READ(PORT_HOTPLUG_EN);
3198
3199 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3200 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3201 I915_WRITE(VLV_IIR, 0xffffffff);
3202 POSTING_READ(VLV_IER);
3203
3204 /* Interrupt setup is already guaranteed to be single-threaded, this is
3205 * just to make the assert_spin_locked check happy. */
3206 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3207 if (dev_priv->display_irqs_enabled)
3208 valleyview_display_irqs_install(dev_priv);
3209 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3210
3211 I915_WRITE(VLV_IIR, 0xffffffff);
3212 I915_WRITE(VLV_IIR, 0xffffffff);
3213
3214 gen5_gt_irq_postinstall(dev);
3215
3216 /* ack & enable invalid PTE error interrupts */
3217 #if 0 /* FIXME: add support to irq handler for checking these bits */
3218 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3219 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3220 #endif
3221
3222 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3223
3224 return 0;
3225 }
3226
3227 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3228 {
3229 int i;
3230
3231 /* These are interrupts we'll toggle with the ring mask register */
3232 uint32_t gt_interrupts[] = {
3233 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3234 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3235 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3236 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3237 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3238 0,
3239 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3240 };
3241
3242 for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++)
3243 GEN8_IRQ_INIT_NDX(GT, i, ~gt_interrupts[i], gt_interrupts[i]);
3244 }
3245
3246 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3247 {
3248 struct drm_device *dev = dev_priv->dev;
3249 uint32_t de_pipe_masked = GEN8_PIPE_FLIP_DONE |
3250 GEN8_PIPE_CDCLK_CRC_DONE |
3251 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3252 uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3253 GEN8_PIPE_FIFO_UNDERRUN;
3254 int pipe;
3255 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3256 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3257 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3258
3259 for_each_pipe(pipe)
3260 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, dev_priv->de_irq_mask[pipe],
3261 de_pipe_enables);
3262
3263 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~GEN8_AUX_CHANNEL_A, GEN8_AUX_CHANNEL_A);
3264 }
3265
3266 static int gen8_irq_postinstall(struct drm_device *dev)
3267 {
3268 struct drm_i915_private *dev_priv = dev->dev_private;
3269
3270 ibx_irq_pre_postinstall(dev);
3271
3272 gen8_gt_irq_postinstall(dev_priv);
3273 gen8_de_irq_postinstall(dev_priv);
3274
3275 ibx_irq_postinstall(dev);
3276
3277 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3278 POSTING_READ(GEN8_MASTER_IRQ);
3279
3280 return 0;
3281 }
3282
3283 static void gen8_irq_uninstall(struct drm_device *dev)
3284 {
3285 struct drm_i915_private *dev_priv = dev->dev_private;
3286
3287 if (!dev_priv)
3288 return;
3289
3290 intel_hpd_irq_uninstall(dev_priv);
3291
3292 gen8_irq_reset(dev);
3293 }
3294
3295 static void valleyview_irq_uninstall(struct drm_device *dev)
3296 {
3297 struct drm_i915_private *dev_priv = dev->dev_private;
3298 unsigned long irqflags;
3299 int pipe;
3300
3301 if (!dev_priv)
3302 return;
3303
3304 intel_hpd_irq_uninstall(dev_priv);
3305
3306 for_each_pipe(pipe)
3307 I915_WRITE(PIPESTAT(pipe), 0xffff);
3308
3309 I915_WRITE(HWSTAM, 0xffffffff);
3310 I915_WRITE(PORT_HOTPLUG_EN, 0);
3311 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3312
3313 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3314 if (dev_priv->display_irqs_enabled)
3315 valleyview_display_irqs_uninstall(dev_priv);
3316 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3317
3318 dev_priv->irq_mask = 0;
3319
3320 I915_WRITE(VLV_IIR, 0xffffffff);
3321 I915_WRITE(VLV_IMR, 0xffffffff);
3322 I915_WRITE(VLV_IER, 0x0);
3323 POSTING_READ(VLV_IER);
3324 }
3325
3326 static void ironlake_irq_uninstall(struct drm_device *dev)
3327 {
3328 struct drm_i915_private *dev_priv = dev->dev_private;
3329
3330 if (!dev_priv)
3331 return;
3332
3333 intel_hpd_irq_uninstall(dev_priv);
3334
3335 ironlake_irq_reset(dev);
3336 }
3337
3338 static void i8xx_irq_preinstall(struct drm_device * dev)
3339 {
3340 struct drm_i915_private *dev_priv = dev->dev_private;
3341 int pipe;
3342
3343 for_each_pipe(pipe)
3344 I915_WRITE(PIPESTAT(pipe), 0);
3345 I915_WRITE16(IMR, 0xffff);
3346 I915_WRITE16(IER, 0x0);
3347 POSTING_READ16(IER);
3348 }
3349
3350 static int i8xx_irq_postinstall(struct drm_device *dev)
3351 {
3352 struct drm_i915_private *dev_priv = dev->dev_private;
3353 unsigned long irqflags;
3354
3355 I915_WRITE16(EMR,
3356 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3357
3358 /* Unmask the interrupts that we always want on. */
3359 dev_priv->irq_mask =
3360 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3361 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3362 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3363 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3364 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3365 I915_WRITE16(IMR, dev_priv->irq_mask);
3366
3367 I915_WRITE16(IER,
3368 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3369 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3370 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3371 I915_USER_INTERRUPT);
3372 POSTING_READ16(IER);
3373
3374 /* Interrupt setup is already guaranteed to be single-threaded, this is
3375 * just to make the assert_spin_locked check happy. */
3376 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3377 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3378 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3379 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3380
3381 return 0;
3382 }
3383
3384 /*
3385 * Returns true when a page flip has completed.
3386 */
3387 static bool i8xx_handle_vblank(struct drm_device *dev,
3388 int plane, int pipe, u32 iir)
3389 {
3390 struct drm_i915_private *dev_priv = dev->dev_private;
3391 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3392
3393 if (!drm_handle_vblank(dev, pipe))
3394 return false;
3395
3396 if ((iir & flip_pending) == 0)
3397 return false;
3398
3399 intel_prepare_page_flip(dev, plane);
3400
3401 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3402 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3403 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3404 * the flip is completed (no longer pending). Since this doesn't raise
3405 * an interrupt per se, we watch for the change at vblank.
3406 */
3407 if (I915_READ16(ISR) & flip_pending)
3408 return false;
3409
3410 intel_finish_page_flip(dev, pipe);
3411
3412 return true;
3413 }
3414
3415 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3416 {
3417 struct drm_device *dev = (struct drm_device *) arg;
3418 struct drm_i915_private *dev_priv = dev->dev_private;
3419 u16 iir, new_iir;
3420 u32 pipe_stats[2];
3421 unsigned long irqflags;
3422 int pipe;
3423 u16 flip_mask =
3424 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3425 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3426
3427 iir = I915_READ16(IIR);
3428 if (iir == 0)
3429 return IRQ_NONE;
3430
3431 while (iir & ~flip_mask) {
3432 /* Can't rely on pipestat interrupt bit in iir as it might
3433 * have been cleared after the pipestat interrupt was received.
3434 * It doesn't set the bit in iir again, but it still produces
3435 * interrupts (for non-MSI).
3436 */
3437 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3438 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3439 i915_handle_error(dev, false,
3440 "Command parser error, iir 0x%08x",
3441 iir);
3442
3443 for_each_pipe(pipe) {
3444 int reg = PIPESTAT(pipe);
3445 pipe_stats[pipe] = I915_READ(reg);
3446
3447 /*
3448 * Clear the PIPE*STAT regs before the IIR
3449 */
3450 if (pipe_stats[pipe] & 0x8000ffff)
3451 I915_WRITE(reg, pipe_stats[pipe]);
3452 }
3453 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3454
3455 I915_WRITE16(IIR, iir & ~flip_mask);
3456 new_iir = I915_READ16(IIR); /* Flush posted writes */
3457
3458 i915_update_dri1_breadcrumb(dev);
3459
3460 if (iir & I915_USER_INTERRUPT)
3461 notify_ring(dev, &dev_priv->ring[RCS]);
3462
3463 for_each_pipe(pipe) {
3464 int plane = pipe;
3465 if (HAS_FBC(dev))
3466 plane = !plane;
3467
3468 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3469 i8xx_handle_vblank(dev, plane, pipe, iir))
3470 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3471
3472 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3473 i9xx_pipe_crc_irq_handler(dev, pipe);
3474
3475 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3476 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3477 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3478 }
3479
3480 iir = new_iir;
3481 }
3482
3483 return IRQ_HANDLED;
3484 }
3485
3486 static void i8xx_irq_uninstall(struct drm_device * dev)
3487 {
3488 struct drm_i915_private *dev_priv = dev->dev_private;
3489 int pipe;
3490
3491 for_each_pipe(pipe) {
3492 /* Clear enable bits; then clear status bits */
3493 I915_WRITE(PIPESTAT(pipe), 0);
3494 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3495 }
3496 I915_WRITE16(IMR, 0xffff);
3497 I915_WRITE16(IER, 0x0);
3498 I915_WRITE16(IIR, I915_READ16(IIR));
3499 }
3500
3501 static void i915_irq_preinstall(struct drm_device * dev)
3502 {
3503 struct drm_i915_private *dev_priv = dev->dev_private;
3504 int pipe;
3505
3506 if (I915_HAS_HOTPLUG(dev)) {
3507 I915_WRITE(PORT_HOTPLUG_EN, 0);
3508 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3509 }
3510
3511 I915_WRITE16(HWSTAM, 0xeffe);
3512 for_each_pipe(pipe)
3513 I915_WRITE(PIPESTAT(pipe), 0);
3514 I915_WRITE(IMR, 0xffffffff);
3515 I915_WRITE(IER, 0x0);
3516 POSTING_READ(IER);
3517 }
3518
3519 static int i915_irq_postinstall(struct drm_device *dev)
3520 {
3521 struct drm_i915_private *dev_priv = dev->dev_private;
3522 u32 enable_mask;
3523 unsigned long irqflags;
3524
3525 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3526
3527 /* Unmask the interrupts that we always want on. */
3528 dev_priv->irq_mask =
3529 ~(I915_ASLE_INTERRUPT |
3530 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3531 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3532 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3533 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3534 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3535
3536 enable_mask =
3537 I915_ASLE_INTERRUPT |
3538 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3539 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3540 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3541 I915_USER_INTERRUPT;
3542
3543 if (I915_HAS_HOTPLUG(dev)) {
3544 I915_WRITE(PORT_HOTPLUG_EN, 0);
3545 POSTING_READ(PORT_HOTPLUG_EN);
3546
3547 /* Enable in IER... */
3548 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3549 /* and unmask in IMR */
3550 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3551 }
3552
3553 I915_WRITE(IMR, dev_priv->irq_mask);
3554 I915_WRITE(IER, enable_mask);
3555 POSTING_READ(IER);
3556
3557 i915_enable_asle_pipestat(dev);
3558
3559 /* Interrupt setup is already guaranteed to be single-threaded, this is
3560 * just to make the assert_spin_locked check happy. */
3561 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3562 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3563 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3564 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3565
3566 return 0;
3567 }
3568
3569 /*
3570 * Returns true when a page flip has completed.
3571 */
3572 static bool i915_handle_vblank(struct drm_device *dev,
3573 int plane, int pipe, u32 iir)
3574 {
3575 struct drm_i915_private *dev_priv = dev->dev_private;
3576 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3577
3578 if (!drm_handle_vblank(dev, pipe))
3579 return false;
3580
3581 if ((iir & flip_pending) == 0)
3582 return false;
3583
3584 intel_prepare_page_flip(dev, plane);
3585
3586 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3587 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3588 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3589 * the flip is completed (no longer pending). Since this doesn't raise
3590 * an interrupt per se, we watch for the change at vblank.
3591 */
3592 if (I915_READ(ISR) & flip_pending)
3593 return false;
3594
3595 intel_finish_page_flip(dev, pipe);
3596
3597 return true;
3598 }
3599
3600 static irqreturn_t i915_irq_handler(int irq, void *arg)
3601 {
3602 struct drm_device *dev = (struct drm_device *) arg;
3603 struct drm_i915_private *dev_priv = dev->dev_private;
3604 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3605 unsigned long irqflags;
3606 u32 flip_mask =
3607 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3608 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3609 int pipe, ret = IRQ_NONE;
3610
3611 iir = I915_READ(IIR);
3612 do {
3613 bool irq_received = (iir & ~flip_mask) != 0;
3614 bool blc_event = false;
3615
3616 /* Can't rely on pipestat interrupt bit in iir as it might
3617 * have been cleared after the pipestat interrupt was received.
3618 * It doesn't set the bit in iir again, but it still produces
3619 * interrupts (for non-MSI).
3620 */
3621 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3622 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3623 i915_handle_error(dev, false,
3624 "Command parser error, iir 0x%08x",
3625 iir);
3626
3627 for_each_pipe(pipe) {
3628 int reg = PIPESTAT(pipe);
3629 pipe_stats[pipe] = I915_READ(reg);
3630
3631 /* Clear the PIPE*STAT regs before the IIR */
3632 if (pipe_stats[pipe] & 0x8000ffff) {
3633 I915_WRITE(reg, pipe_stats[pipe]);
3634 irq_received = true;
3635 }
3636 }
3637 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3638
3639 if (!irq_received)
3640 break;
3641
3642 /* Consume port. Then clear IIR or we'll miss events */
3643 if (I915_HAS_HOTPLUG(dev) &&
3644 iir & I915_DISPLAY_PORT_INTERRUPT)
3645 i9xx_hpd_irq_handler(dev);
3646
3647 I915_WRITE(IIR, iir & ~flip_mask);
3648 new_iir = I915_READ(IIR); /* Flush posted writes */
3649
3650 if (iir & I915_USER_INTERRUPT)
3651 notify_ring(dev, &dev_priv->ring[RCS]);
3652
3653 for_each_pipe(pipe) {
3654 int plane = pipe;
3655 if (HAS_FBC(dev))
3656 plane = !plane;
3657
3658 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3659 i915_handle_vblank(dev, plane, pipe, iir))
3660 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3661
3662 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3663 blc_event = true;
3664
3665 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3666 i9xx_pipe_crc_irq_handler(dev, pipe);
3667
3668 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3669 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3670 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3671 }
3672
3673 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3674 intel_opregion_asle_intr(dev);
3675
3676 /* With MSI, interrupts are only generated when iir
3677 * transitions from zero to nonzero. If another bit got
3678 * set while we were handling the existing iir bits, then
3679 * we would never get another interrupt.
3680 *
3681 * This is fine on non-MSI as well, as if we hit this path
3682 * we avoid exiting the interrupt handler only to generate
3683 * another one.
3684 *
3685 * Note that for MSI this could cause a stray interrupt report
3686 * if an interrupt landed in the time between writing IIR and
3687 * the posting read. This should be rare enough to never
3688 * trigger the 99% of 100,000 interrupts test for disabling
3689 * stray interrupts.
3690 */
3691 ret = IRQ_HANDLED;
3692 iir = new_iir;
3693 } while (iir & ~flip_mask);
3694
3695 i915_update_dri1_breadcrumb(dev);
3696
3697 return ret;
3698 }
3699
3700 static void i915_irq_uninstall(struct drm_device * dev)
3701 {
3702 struct drm_i915_private *dev_priv = dev->dev_private;
3703 int pipe;
3704
3705 intel_hpd_irq_uninstall(dev_priv);
3706
3707 if (I915_HAS_HOTPLUG(dev)) {
3708 I915_WRITE(PORT_HOTPLUG_EN, 0);
3709 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3710 }
3711
3712 I915_WRITE16(HWSTAM, 0xffff);
3713 for_each_pipe(pipe) {
3714 /* Clear enable bits; then clear status bits */
3715 I915_WRITE(PIPESTAT(pipe), 0);
3716 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3717 }
3718 I915_WRITE(IMR, 0xffffffff);
3719 I915_WRITE(IER, 0x0);
3720
3721 I915_WRITE(IIR, I915_READ(IIR));
3722 }
3723
3724 static void i965_irq_preinstall(struct drm_device * dev)
3725 {
3726 struct drm_i915_private *dev_priv = dev->dev_private;
3727 int pipe;
3728
3729 I915_WRITE(PORT_HOTPLUG_EN, 0);
3730 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3731
3732 I915_WRITE(HWSTAM, 0xeffe);
3733 for_each_pipe(pipe)
3734 I915_WRITE(PIPESTAT(pipe), 0);
3735 I915_WRITE(IMR, 0xffffffff);
3736 I915_WRITE(IER, 0x0);
3737 POSTING_READ(IER);
3738 }
3739
3740 static int i965_irq_postinstall(struct drm_device *dev)
3741 {
3742 struct drm_i915_private *dev_priv = dev->dev_private;
3743 u32 enable_mask;
3744 u32 error_mask;
3745 unsigned long irqflags;
3746
3747 /* Unmask the interrupts that we always want on. */
3748 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
3749 I915_DISPLAY_PORT_INTERRUPT |
3750 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3751 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3752 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3753 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3754 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3755
3756 enable_mask = ~dev_priv->irq_mask;
3757 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3758 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3759 enable_mask |= I915_USER_INTERRUPT;
3760
3761 if (IS_G4X(dev))
3762 enable_mask |= I915_BSD_USER_INTERRUPT;
3763
3764 /* Interrupt setup is already guaranteed to be single-threaded, this is
3765 * just to make the assert_spin_locked check happy. */
3766 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3767 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3768 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3769 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3770 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3771
3772 /*
3773 * Enable some error detection, note the instruction error mask
3774 * bit is reserved, so we leave it masked.
3775 */
3776 if (IS_G4X(dev)) {
3777 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3778 GM45_ERROR_MEM_PRIV |
3779 GM45_ERROR_CP_PRIV |
3780 I915_ERROR_MEMORY_REFRESH);
3781 } else {
3782 error_mask = ~(I915_ERROR_PAGE_TABLE |
3783 I915_ERROR_MEMORY_REFRESH);
3784 }
3785 I915_WRITE(EMR, error_mask);
3786
3787 I915_WRITE(IMR, dev_priv->irq_mask);
3788 I915_WRITE(IER, enable_mask);
3789 POSTING_READ(IER);
3790
3791 I915_WRITE(PORT_HOTPLUG_EN, 0);
3792 POSTING_READ(PORT_HOTPLUG_EN);
3793
3794 i915_enable_asle_pipestat(dev);
3795
3796 return 0;
3797 }
3798
3799 static void i915_hpd_irq_setup(struct drm_device *dev)
3800 {
3801 struct drm_i915_private *dev_priv = dev->dev_private;
3802 struct drm_mode_config *mode_config = &dev->mode_config;
3803 struct intel_encoder *intel_encoder;
3804 u32 hotplug_en;
3805
3806 assert_spin_locked(&dev_priv->irq_lock);
3807
3808 if (I915_HAS_HOTPLUG(dev)) {
3809 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3810 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3811 /* Note HDMI and DP share hotplug bits */
3812 /* enable bits are the same for all generations */
3813 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3814 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3815 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
3816 /* Programming the CRT detection parameters tends
3817 to generate a spurious hotplug event about three
3818 seconds later. So just do it once.
3819 */
3820 if (IS_G4X(dev))
3821 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
3822 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
3823 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
3824
3825 /* Ignore TV since it's buggy */
3826 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3827 }
3828 }
3829
3830 static irqreturn_t i965_irq_handler(int irq, void *arg)
3831 {
3832 struct drm_device *dev = (struct drm_device *) arg;
3833 struct drm_i915_private *dev_priv = dev->dev_private;
3834 u32 iir, new_iir;
3835 u32 pipe_stats[I915_MAX_PIPES];
3836 unsigned long irqflags;
3837 int ret = IRQ_NONE, pipe;
3838 u32 flip_mask =
3839 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3840 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3841
3842 iir = I915_READ(IIR);
3843
3844 for (;;) {
3845 bool irq_received = (iir & ~flip_mask) != 0;
3846 bool blc_event = false;
3847
3848 /* Can't rely on pipestat interrupt bit in iir as it might
3849 * have been cleared after the pipestat interrupt was received.
3850 * It doesn't set the bit in iir again, but it still produces
3851 * interrupts (for non-MSI).
3852 */
3853 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3854 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3855 i915_handle_error(dev, false,
3856 "Command parser error, iir 0x%08x",
3857 iir);
3858
3859 for_each_pipe(pipe) {
3860 int reg = PIPESTAT(pipe);
3861 pipe_stats[pipe] = I915_READ(reg);
3862
3863 /*
3864 * Clear the PIPE*STAT regs before the IIR
3865 */
3866 if (pipe_stats[pipe] & 0x8000ffff) {
3867 I915_WRITE(reg, pipe_stats[pipe]);
3868 irq_received = true;
3869 }
3870 }
3871 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3872
3873 if (!irq_received)
3874 break;
3875
3876 ret = IRQ_HANDLED;
3877
3878 /* Consume port. Then clear IIR or we'll miss events */
3879 if (iir & I915_DISPLAY_PORT_INTERRUPT)
3880 i9xx_hpd_irq_handler(dev);
3881
3882 I915_WRITE(IIR, iir & ~flip_mask);
3883 new_iir = I915_READ(IIR); /* Flush posted writes */
3884
3885 if (iir & I915_USER_INTERRUPT)
3886 notify_ring(dev, &dev_priv->ring[RCS]);
3887 if (iir & I915_BSD_USER_INTERRUPT)
3888 notify_ring(dev, &dev_priv->ring[VCS]);
3889
3890 for_each_pipe(pipe) {
3891 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
3892 i915_handle_vblank(dev, pipe, pipe, iir))
3893 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
3894
3895 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3896 blc_event = true;
3897
3898 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3899 i9xx_pipe_crc_irq_handler(dev, pipe);
3900
3901 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3902 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3903 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3904 }
3905
3906 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3907 intel_opregion_asle_intr(dev);
3908
3909 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3910 gmbus_irq_handler(dev);
3911
3912 /* With MSI, interrupts are only generated when iir
3913 * transitions from zero to nonzero. If another bit got
3914 * set while we were handling the existing iir bits, then
3915 * we would never get another interrupt.
3916 *
3917 * This is fine on non-MSI as well, as if we hit this path
3918 * we avoid exiting the interrupt handler only to generate
3919 * another one.
3920 *
3921 * Note that for MSI this could cause a stray interrupt report
3922 * if an interrupt landed in the time between writing IIR and
3923 * the posting read. This should be rare enough to never
3924 * trigger the 99% of 100,000 interrupts test for disabling
3925 * stray interrupts.
3926 */
3927 iir = new_iir;
3928 }
3929
3930 i915_update_dri1_breadcrumb(dev);
3931
3932 return ret;
3933 }
3934
3935 static void i965_irq_uninstall(struct drm_device * dev)
3936 {
3937 struct drm_i915_private *dev_priv = dev->dev_private;
3938 int pipe;
3939
3940 if (!dev_priv)
3941 return;
3942
3943 intel_hpd_irq_uninstall(dev_priv);
3944
3945 I915_WRITE(PORT_HOTPLUG_EN, 0);
3946 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3947
3948 I915_WRITE(HWSTAM, 0xffffffff);
3949 for_each_pipe(pipe)
3950 I915_WRITE(PIPESTAT(pipe), 0);
3951 I915_WRITE(IMR, 0xffffffff);
3952 I915_WRITE(IER, 0x0);
3953
3954 for_each_pipe(pipe)
3955 I915_WRITE(PIPESTAT(pipe),
3956 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3957 I915_WRITE(IIR, I915_READ(IIR));
3958 }
3959
3960 static void intel_hpd_irq_reenable(unsigned long data)
3961 {
3962 struct drm_i915_private *dev_priv = (struct drm_i915_private *)data;
3963 struct drm_device *dev = dev_priv->dev;
3964 struct drm_mode_config *mode_config = &dev->mode_config;
3965 unsigned long irqflags;
3966 int i;
3967
3968 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3969 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3970 struct drm_connector *connector;
3971
3972 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3973 continue;
3974
3975 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3976
3977 list_for_each_entry(connector, &mode_config->connector_list, head) {
3978 struct intel_connector *intel_connector = to_intel_connector(connector);
3979
3980 if (intel_connector->encoder->hpd_pin == i) {
3981 if (connector->polled != intel_connector->polled)
3982 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3983 drm_get_connector_name(connector));
3984 connector->polled = intel_connector->polled;
3985 if (!connector->polled)
3986 connector->polled = DRM_CONNECTOR_POLL_HPD;
3987 }
3988 }
3989 }
3990 if (dev_priv->display.hpd_irq_setup)
3991 dev_priv->display.hpd_irq_setup(dev);
3992 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3993 }
3994
3995 void intel_irq_init(struct drm_device *dev)
3996 {
3997 struct drm_i915_private *dev_priv = dev->dev_private;
3998
3999 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
4000 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
4001 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4002 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4003
4004 /* Let's track the enabled rps events */
4005 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4006
4007 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
4008 i915_hangcheck_elapsed,
4009 (unsigned long) dev);
4010 setup_timer(&dev_priv->hotplug_reenable_timer, intel_hpd_irq_reenable,
4011 (unsigned long) dev_priv);
4012
4013 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4014
4015 if (IS_GEN2(dev)) {
4016 dev->max_vblank_count = 0;
4017 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4018 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
4019 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4020 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
4021 } else {
4022 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4023 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4024 }
4025
4026 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
4027 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4028 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4029 }
4030
4031 if (IS_VALLEYVIEW(dev)) {
4032 dev->driver->irq_handler = valleyview_irq_handler;
4033 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4034 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4035 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4036 dev->driver->enable_vblank = valleyview_enable_vblank;
4037 dev->driver->disable_vblank = valleyview_disable_vblank;
4038 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4039 } else if (IS_GEN8(dev)) {
4040 dev->driver->irq_handler = gen8_irq_handler;
4041 dev->driver->irq_preinstall = gen8_irq_preinstall;
4042 dev->driver->irq_postinstall = gen8_irq_postinstall;
4043 dev->driver->irq_uninstall = gen8_irq_uninstall;
4044 dev->driver->enable_vblank = gen8_enable_vblank;
4045 dev->driver->disable_vblank = gen8_disable_vblank;
4046 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4047 } else if (HAS_PCH_SPLIT(dev)) {
4048 dev->driver->irq_handler = ironlake_irq_handler;
4049 dev->driver->irq_preinstall = ironlake_irq_preinstall;
4050 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4051 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4052 dev->driver->enable_vblank = ironlake_enable_vblank;
4053 dev->driver->disable_vblank = ironlake_disable_vblank;
4054 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4055 } else {
4056 if (INTEL_INFO(dev)->gen == 2) {
4057 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4058 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4059 dev->driver->irq_handler = i8xx_irq_handler;
4060 dev->driver->irq_uninstall = i8xx_irq_uninstall;
4061 } else if (INTEL_INFO(dev)->gen == 3) {
4062 dev->driver->irq_preinstall = i915_irq_preinstall;
4063 dev->driver->irq_postinstall = i915_irq_postinstall;
4064 dev->driver->irq_uninstall = i915_irq_uninstall;
4065 dev->driver->irq_handler = i915_irq_handler;
4066 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4067 } else {
4068 dev->driver->irq_preinstall = i965_irq_preinstall;
4069 dev->driver->irq_postinstall = i965_irq_postinstall;
4070 dev->driver->irq_uninstall = i965_irq_uninstall;
4071 dev->driver->irq_handler = i965_irq_handler;
4072 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4073 }
4074 dev->driver->enable_vblank = i915_enable_vblank;
4075 dev->driver->disable_vblank = i915_disable_vblank;
4076 }
4077 }
4078
4079 void intel_hpd_init(struct drm_device *dev)
4080 {
4081 struct drm_i915_private *dev_priv = dev->dev_private;
4082 struct drm_mode_config *mode_config = &dev->mode_config;
4083 struct drm_connector *connector;
4084 unsigned long irqflags;
4085 int i;
4086
4087 for (i = 1; i < HPD_NUM_PINS; i++) {
4088 dev_priv->hpd_stats[i].hpd_cnt = 0;
4089 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4090 }
4091 list_for_each_entry(connector, &mode_config->connector_list, head) {
4092 struct intel_connector *intel_connector = to_intel_connector(connector);
4093 connector->polled = intel_connector->polled;
4094 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
4095 connector->polled = DRM_CONNECTOR_POLL_HPD;
4096 }
4097
4098 /* Interrupt setup is already guaranteed to be single-threaded, this is
4099 * just to make the assert_spin_locked checks happy. */
4100 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4101 if (dev_priv->display.hpd_irq_setup)
4102 dev_priv->display.hpd_irq_setup(dev);
4103 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4104 }
4105
4106 /* Disable interrupts so we can allow runtime PM. */
4107 void intel_runtime_pm_disable_interrupts(struct drm_device *dev)
4108 {
4109 struct drm_i915_private *dev_priv = dev->dev_private;
4110
4111 dev->driver->irq_uninstall(dev);
4112 dev_priv->pm.irqs_disabled = true;
4113 }
4114
4115 /* Restore interrupts so we can recover from runtime PM. */
4116 void intel_runtime_pm_restore_interrupts(struct drm_device *dev)
4117 {
4118 struct drm_i915_private *dev_priv = dev->dev_private;
4119
4120 dev_priv->pm.irqs_disabled = false;
4121 dev->driver->irq_preinstall(dev);
4122 dev->driver->irq_postinstall(dev);
4123 }
Linux kernel - Deliverables
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