1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
35 #include <drm/i915_drm.h>
37 #include "i915_trace.h"
38 #include "intel_drv.h"
41 * DOC: interrupt handling
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
48 static const u32 hpd_ilk
[HPD_NUM_PINS
] = {
49 [HPD_PORT_A
] = DE_DP_A_HOTPLUG
,
52 static const u32 hpd_ivb
[HPD_NUM_PINS
] = {
53 [HPD_PORT_A
] = DE_DP_A_HOTPLUG_IVB
,
56 static const u32 hpd_bdw
[HPD_NUM_PINS
] = {
57 [HPD_PORT_A
] = GEN8_PORT_DP_A_HOTPLUG
,
60 static const u32 hpd_ibx
[HPD_NUM_PINS
] = {
61 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
62 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
63 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
64 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
65 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
68 static const u32 hpd_cpt
[HPD_NUM_PINS
] = {
69 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
70 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG_CPT
,
71 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
72 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
73 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
76 static const u32 hpd_spt
[HPD_NUM_PINS
] = {
77 [HPD_PORT_A
] = SDE_PORTA_HOTPLUG_SPT
,
78 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
79 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
80 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
,
81 [HPD_PORT_E
] = SDE_PORTE_HOTPLUG_SPT
84 static const u32 hpd_mask_i915
[HPD_NUM_PINS
] = {
85 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
86 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
87 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
88 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
89 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
90 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
93 static const u32 hpd_status_g4x
[HPD_NUM_PINS
] = {
94 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
95 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
96 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
97 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
98 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
99 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
102 static const u32 hpd_status_i915
[HPD_NUM_PINS
] = {
103 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
104 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
105 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
106 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
107 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
108 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
112 static const u32 hpd_bxt
[HPD_NUM_PINS
] = {
113 [HPD_PORT_A
] = BXT_DE_PORT_HP_DDIA
,
114 [HPD_PORT_B
] = BXT_DE_PORT_HP_DDIB
,
115 [HPD_PORT_C
] = BXT_DE_PORT_HP_DDIC
118 /* IIR can theoretically queue up two events. Be paranoid. */
119 #define GEN8_IRQ_RESET_NDX(type, which) do { \
120 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
121 POSTING_READ(GEN8_##type##_IMR(which)); \
122 I915_WRITE(GEN8_##type##_IER(which), 0); \
123 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
124 POSTING_READ(GEN8_##type##_IIR(which)); \
125 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
126 POSTING_READ(GEN8_##type##_IIR(which)); \
129 #define GEN5_IRQ_RESET(type) do { \
130 I915_WRITE(type##IMR, 0xffffffff); \
131 POSTING_READ(type##IMR); \
132 I915_WRITE(type##IER, 0); \
133 I915_WRITE(type##IIR, 0xffffffff); \
134 POSTING_READ(type##IIR); \
135 I915_WRITE(type##IIR, 0xffffffff); \
136 POSTING_READ(type##IIR); \
140 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
142 static void gen5_assert_iir_is_zero(struct drm_i915_private
*dev_priv
,
145 u32 val
= I915_READ(reg
);
150 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
151 i915_mmio_reg_offset(reg
), val
);
152 I915_WRITE(reg
, 0xffffffff);
154 I915_WRITE(reg
, 0xffffffff);
158 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
159 gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
160 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
161 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
162 POSTING_READ(GEN8_##type##_IMR(which)); \
165 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
166 gen5_assert_iir_is_zero(dev_priv, type##IIR); \
167 I915_WRITE(type##IER, (ier_val)); \
168 I915_WRITE(type##IMR, (imr_val)); \
169 POSTING_READ(type##IMR); \
172 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
);
174 /* For display hotplug interrupt */
176 i915_hotplug_interrupt_update_locked(struct drm_i915_private
*dev_priv
,
182 assert_spin_locked(&dev_priv
->irq_lock
);
183 WARN_ON(bits
& ~mask
);
185 val
= I915_READ(PORT_HOTPLUG_EN
);
188 I915_WRITE(PORT_HOTPLUG_EN
, val
);
192 * i915_hotplug_interrupt_update - update hotplug interrupt enable
193 * @dev_priv: driver private
194 * @mask: bits to update
195 * @bits: bits to enable
196 * NOTE: the HPD enable bits are modified both inside and outside
197 * of an interrupt context. To avoid that read-modify-write cycles
198 * interfer, these bits are protected by a spinlock. Since this
199 * function is usually not called from a context where the lock is
200 * held already, this function acquires the lock itself. A non-locking
201 * version is also available.
203 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
207 spin_lock_irq(&dev_priv
->irq_lock
);
208 i915_hotplug_interrupt_update_locked(dev_priv
, mask
, bits
);
209 spin_unlock_irq(&dev_priv
->irq_lock
);
213 * ilk_update_display_irq - update DEIMR
214 * @dev_priv: driver private
215 * @interrupt_mask: mask of interrupt bits to update
216 * @enabled_irq_mask: mask of interrupt bits to enable
218 void ilk_update_display_irq(struct drm_i915_private
*dev_priv
,
219 uint32_t interrupt_mask
,
220 uint32_t enabled_irq_mask
)
224 assert_spin_locked(&dev_priv
->irq_lock
);
226 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
228 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
231 new_val
= dev_priv
->irq_mask
;
232 new_val
&= ~interrupt_mask
;
233 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
235 if (new_val
!= dev_priv
->irq_mask
) {
236 dev_priv
->irq_mask
= new_val
;
237 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
243 * ilk_update_gt_irq - update GTIMR
244 * @dev_priv: driver private
245 * @interrupt_mask: mask of interrupt bits to update
246 * @enabled_irq_mask: mask of interrupt bits to enable
248 static void ilk_update_gt_irq(struct drm_i915_private
*dev_priv
,
249 uint32_t interrupt_mask
,
250 uint32_t enabled_irq_mask
)
252 assert_spin_locked(&dev_priv
->irq_lock
);
254 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
256 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
259 dev_priv
->gt_irq_mask
&= ~interrupt_mask
;
260 dev_priv
->gt_irq_mask
|= (~enabled_irq_mask
& interrupt_mask
);
261 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
265 void gen5_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
267 ilk_update_gt_irq(dev_priv
, mask
, mask
);
270 void gen5_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
272 ilk_update_gt_irq(dev_priv
, mask
, 0);
275 static i915_reg_t
gen6_pm_iir(struct drm_i915_private
*dev_priv
)
277 return INTEL_INFO(dev_priv
)->gen
>= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR
;
280 static i915_reg_t
gen6_pm_imr(struct drm_i915_private
*dev_priv
)
282 return INTEL_INFO(dev_priv
)->gen
>= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR
;
285 static i915_reg_t
gen6_pm_ier(struct drm_i915_private
*dev_priv
)
287 return INTEL_INFO(dev_priv
)->gen
>= 8 ? GEN8_GT_IER(2) : GEN6_PMIER
;
291 * snb_update_pm_irq - update GEN6_PMIMR
292 * @dev_priv: driver private
293 * @interrupt_mask: mask of interrupt bits to update
294 * @enabled_irq_mask: mask of interrupt bits to enable
296 static void snb_update_pm_irq(struct drm_i915_private
*dev_priv
,
297 uint32_t interrupt_mask
,
298 uint32_t enabled_irq_mask
)
302 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
304 assert_spin_locked(&dev_priv
->irq_lock
);
306 new_val
= dev_priv
->pm_irq_mask
;
307 new_val
&= ~interrupt_mask
;
308 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
310 if (new_val
!= dev_priv
->pm_irq_mask
) {
311 dev_priv
->pm_irq_mask
= new_val
;
312 I915_WRITE(gen6_pm_imr(dev_priv
), dev_priv
->pm_irq_mask
);
313 POSTING_READ(gen6_pm_imr(dev_priv
));
317 void gen6_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
319 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
322 snb_update_pm_irq(dev_priv
, mask
, mask
);
325 static void __gen6_disable_pm_irq(struct drm_i915_private
*dev_priv
,
328 snb_update_pm_irq(dev_priv
, mask
, 0);
331 void gen6_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
333 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
336 __gen6_disable_pm_irq(dev_priv
, mask
);
339 void gen6_reset_rps_interrupts(struct drm_i915_private
*dev_priv
)
341 i915_reg_t reg
= gen6_pm_iir(dev_priv
);
343 spin_lock_irq(&dev_priv
->irq_lock
);
344 I915_WRITE(reg
, dev_priv
->pm_rps_events
);
345 I915_WRITE(reg
, dev_priv
->pm_rps_events
);
347 dev_priv
->rps
.pm_iir
= 0;
348 spin_unlock_irq(&dev_priv
->irq_lock
);
351 void gen6_enable_rps_interrupts(struct drm_i915_private
*dev_priv
)
353 spin_lock_irq(&dev_priv
->irq_lock
);
355 WARN_ON(dev_priv
->rps
.pm_iir
);
356 WARN_ON(I915_READ(gen6_pm_iir(dev_priv
)) & dev_priv
->pm_rps_events
);
357 dev_priv
->rps
.interrupts_enabled
= true;
358 I915_WRITE(gen6_pm_ier(dev_priv
), I915_READ(gen6_pm_ier(dev_priv
)) |
359 dev_priv
->pm_rps_events
);
360 gen6_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
362 spin_unlock_irq(&dev_priv
->irq_lock
);
365 u32
gen6_sanitize_rps_pm_mask(struct drm_i915_private
*dev_priv
, u32 mask
)
367 return (mask
& ~dev_priv
->rps
.pm_intr_keep
);
370 void gen6_disable_rps_interrupts(struct drm_i915_private
*dev_priv
)
372 spin_lock_irq(&dev_priv
->irq_lock
);
373 dev_priv
->rps
.interrupts_enabled
= false;
374 spin_unlock_irq(&dev_priv
->irq_lock
);
376 cancel_work_sync(&dev_priv
->rps
.work
);
378 spin_lock_irq(&dev_priv
->irq_lock
);
380 I915_WRITE(GEN6_PMINTRMSK
, gen6_sanitize_rps_pm_mask(dev_priv
, ~0));
382 __gen6_disable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
383 I915_WRITE(gen6_pm_ier(dev_priv
), I915_READ(gen6_pm_ier(dev_priv
)) &
384 ~dev_priv
->pm_rps_events
);
386 spin_unlock_irq(&dev_priv
->irq_lock
);
388 synchronize_irq(dev_priv
->dev
->irq
);
392 * bdw_update_port_irq - update DE port interrupt
393 * @dev_priv: driver private
394 * @interrupt_mask: mask of interrupt bits to update
395 * @enabled_irq_mask: mask of interrupt bits to enable
397 static void bdw_update_port_irq(struct drm_i915_private
*dev_priv
,
398 uint32_t interrupt_mask
,
399 uint32_t enabled_irq_mask
)
404 assert_spin_locked(&dev_priv
->irq_lock
);
406 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
408 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
411 old_val
= I915_READ(GEN8_DE_PORT_IMR
);
414 new_val
&= ~interrupt_mask
;
415 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
417 if (new_val
!= old_val
) {
418 I915_WRITE(GEN8_DE_PORT_IMR
, new_val
);
419 POSTING_READ(GEN8_DE_PORT_IMR
);
424 * bdw_update_pipe_irq - update DE pipe interrupt
425 * @dev_priv: driver private
426 * @pipe: pipe whose interrupt to update
427 * @interrupt_mask: mask of interrupt bits to update
428 * @enabled_irq_mask: mask of interrupt bits to enable
430 void bdw_update_pipe_irq(struct drm_i915_private
*dev_priv
,
432 uint32_t interrupt_mask
,
433 uint32_t enabled_irq_mask
)
437 assert_spin_locked(&dev_priv
->irq_lock
);
439 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
441 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
444 new_val
= dev_priv
->de_irq_mask
[pipe
];
445 new_val
&= ~interrupt_mask
;
446 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
448 if (new_val
!= dev_priv
->de_irq_mask
[pipe
]) {
449 dev_priv
->de_irq_mask
[pipe
] = new_val
;
450 I915_WRITE(GEN8_DE_PIPE_IMR(pipe
), dev_priv
->de_irq_mask
[pipe
]);
451 POSTING_READ(GEN8_DE_PIPE_IMR(pipe
));
456 * ibx_display_interrupt_update - update SDEIMR
457 * @dev_priv: driver private
458 * @interrupt_mask: mask of interrupt bits to update
459 * @enabled_irq_mask: mask of interrupt bits to enable
461 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
462 uint32_t interrupt_mask
,
463 uint32_t enabled_irq_mask
)
465 uint32_t sdeimr
= I915_READ(SDEIMR
);
466 sdeimr
&= ~interrupt_mask
;
467 sdeimr
|= (~enabled_irq_mask
& interrupt_mask
);
469 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
471 assert_spin_locked(&dev_priv
->irq_lock
);
473 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
476 I915_WRITE(SDEIMR
, sdeimr
);
477 POSTING_READ(SDEIMR
);
481 __i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
482 u32 enable_mask
, u32 status_mask
)
484 i915_reg_t reg
= PIPESTAT(pipe
);
485 u32 pipestat
= I915_READ(reg
) & PIPESTAT_INT_ENABLE_MASK
;
487 assert_spin_locked(&dev_priv
->irq_lock
);
488 WARN_ON(!intel_irqs_enabled(dev_priv
));
490 if (WARN_ONCE(enable_mask
& ~PIPESTAT_INT_ENABLE_MASK
||
491 status_mask
& ~PIPESTAT_INT_STATUS_MASK
,
492 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
493 pipe_name(pipe
), enable_mask
, status_mask
))
496 if ((pipestat
& enable_mask
) == enable_mask
)
499 dev_priv
->pipestat_irq_mask
[pipe
] |= status_mask
;
501 /* Enable the interrupt, clear any pending status */
502 pipestat
|= enable_mask
| status_mask
;
503 I915_WRITE(reg
, pipestat
);
508 __i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
509 u32 enable_mask
, u32 status_mask
)
511 i915_reg_t reg
= PIPESTAT(pipe
);
512 u32 pipestat
= I915_READ(reg
) & PIPESTAT_INT_ENABLE_MASK
;
514 assert_spin_locked(&dev_priv
->irq_lock
);
515 WARN_ON(!intel_irqs_enabled(dev_priv
));
517 if (WARN_ONCE(enable_mask
& ~PIPESTAT_INT_ENABLE_MASK
||
518 status_mask
& ~PIPESTAT_INT_STATUS_MASK
,
519 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
520 pipe_name(pipe
), enable_mask
, status_mask
))
523 if ((pipestat
& enable_mask
) == 0)
526 dev_priv
->pipestat_irq_mask
[pipe
] &= ~status_mask
;
528 pipestat
&= ~enable_mask
;
529 I915_WRITE(reg
, pipestat
);
533 static u32
vlv_get_pipestat_enable_mask(struct drm_device
*dev
, u32 status_mask
)
535 u32 enable_mask
= status_mask
<< 16;
538 * On pipe A we don't support the PSR interrupt yet,
539 * on pipe B and C the same bit MBZ.
541 if (WARN_ON_ONCE(status_mask
& PIPE_A_PSR_STATUS_VLV
))
544 * On pipe B and C we don't support the PSR interrupt yet, on pipe
545 * A the same bit is for perf counters which we don't use either.
547 if (WARN_ON_ONCE(status_mask
& PIPE_B_PSR_STATUS_VLV
))
550 enable_mask
&= ~(PIPE_FIFO_UNDERRUN_STATUS
|
551 SPRITE0_FLIP_DONE_INT_EN_VLV
|
552 SPRITE1_FLIP_DONE_INT_EN_VLV
);
553 if (status_mask
& SPRITE0_FLIP_DONE_INT_STATUS_VLV
)
554 enable_mask
|= SPRITE0_FLIP_DONE_INT_EN_VLV
;
555 if (status_mask
& SPRITE1_FLIP_DONE_INT_STATUS_VLV
)
556 enable_mask
|= SPRITE1_FLIP_DONE_INT_EN_VLV
;
562 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
567 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
568 enable_mask
= vlv_get_pipestat_enable_mask(dev_priv
->dev
,
571 enable_mask
= status_mask
<< 16;
572 __i915_enable_pipestat(dev_priv
, pipe
, enable_mask
, status_mask
);
576 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
581 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
582 enable_mask
= vlv_get_pipestat_enable_mask(dev_priv
->dev
,
585 enable_mask
= status_mask
<< 16;
586 __i915_disable_pipestat(dev_priv
, pipe
, enable_mask
, status_mask
);
590 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
591 * @dev_priv: i915 device private
593 static void i915_enable_asle_pipestat(struct drm_i915_private
*dev_priv
)
595 if (!dev_priv
->opregion
.asle
|| !IS_MOBILE(dev_priv
))
598 spin_lock_irq(&dev_priv
->irq_lock
);
600 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_LEGACY_BLC_EVENT_STATUS
);
601 if (INTEL_GEN(dev_priv
) >= 4)
602 i915_enable_pipestat(dev_priv
, PIPE_A
,
603 PIPE_LEGACY_BLC_EVENT_STATUS
);
605 spin_unlock_irq(&dev_priv
->irq_lock
);
609 * This timing diagram depicts the video signal in and
610 * around the vertical blanking period.
612 * Assumptions about the fictitious mode used in this example:
614 * vsync_start = vblank_start + 1
615 * vsync_end = vblank_start + 2
616 * vtotal = vblank_start + 3
619 * latch double buffered registers
620 * increment frame counter (ctg+)
621 * generate start of vblank interrupt (gen4+)
624 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
625 * | may be shifted forward 1-3 extra lines via PIPECONF
627 * | | start of vsync:
628 * | | generate vsync interrupt
630 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
631 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
632 * ----va---> <-----------------vb--------------------> <--------va-------------
633 * | | <----vs-----> |
634 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
635 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
636 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
638 * last visible pixel first visible pixel
639 * | increment frame counter (gen3/4)
640 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
642 * x = horizontal active
643 * _ = horizontal blanking
644 * hs = horizontal sync
645 * va = vertical active
646 * vb = vertical blanking
648 * vbs = vblank_start (number)
651 * - most events happen at the start of horizontal sync
652 * - frame start happens at the start of horizontal blank, 1-4 lines
653 * (depending on PIPECONF settings) after the start of vblank
654 * - gen3/4 pixel and frame counter are synchronized with the start
655 * of horizontal active on the first line of vertical active
658 static u32
i8xx_get_vblank_counter(struct drm_device
*dev
, unsigned int pipe
)
660 /* Gen2 doesn't have a hardware frame counter */
664 /* Called from drm generic code, passed a 'crtc', which
665 * we use as a pipe index
667 static u32
i915_get_vblank_counter(struct drm_device
*dev
, unsigned int pipe
)
669 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
670 i915_reg_t high_frame
, low_frame
;
671 u32 high1
, high2
, low
, pixel
, vbl_start
, hsync_start
, htotal
;
672 struct intel_crtc
*intel_crtc
=
673 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
674 const struct drm_display_mode
*mode
= &intel_crtc
->base
.hwmode
;
676 htotal
= mode
->crtc_htotal
;
677 hsync_start
= mode
->crtc_hsync_start
;
678 vbl_start
= mode
->crtc_vblank_start
;
679 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
680 vbl_start
= DIV_ROUND_UP(vbl_start
, 2);
682 /* Convert to pixel count */
685 /* Start of vblank event occurs at start of hsync */
686 vbl_start
-= htotal
- hsync_start
;
688 high_frame
= PIPEFRAME(pipe
);
689 low_frame
= PIPEFRAMEPIXEL(pipe
);
692 * High & low register fields aren't synchronized, so make sure
693 * we get a low value that's stable across two reads of the high
697 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
698 low
= I915_READ(low_frame
);
699 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
700 } while (high1
!= high2
);
702 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
703 pixel
= low
& PIPE_PIXEL_MASK
;
704 low
>>= PIPE_FRAME_LOW_SHIFT
;
707 * The frame counter increments at beginning of active.
708 * Cook up a vblank counter by also checking the pixel
709 * counter against vblank start.
711 return (((high1
<< 8) | low
) + (pixel
>= vbl_start
)) & 0xffffff;
714 static u32
g4x_get_vblank_counter(struct drm_device
*dev
, unsigned int pipe
)
716 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
718 return I915_READ(PIPE_FRMCOUNT_G4X(pipe
));
721 /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
722 static int __intel_get_crtc_scanline(struct intel_crtc
*crtc
)
724 struct drm_device
*dev
= crtc
->base
.dev
;
725 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
726 const struct drm_display_mode
*mode
= &crtc
->base
.hwmode
;
727 enum pipe pipe
= crtc
->pipe
;
728 int position
, vtotal
;
730 vtotal
= mode
->crtc_vtotal
;
731 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
734 if (IS_GEN2(dev_priv
))
735 position
= I915_READ_FW(PIPEDSL(pipe
)) & DSL_LINEMASK_GEN2
;
737 position
= I915_READ_FW(PIPEDSL(pipe
)) & DSL_LINEMASK_GEN3
;
740 * On HSW, the DSL reg (0x70000) appears to return 0 if we
741 * read it just before the start of vblank. So try it again
742 * so we don't accidentally end up spanning a vblank frame
743 * increment, causing the pipe_update_end() code to squak at us.
745 * The nature of this problem means we can't simply check the ISR
746 * bit and return the vblank start value; nor can we use the scanline
747 * debug register in the transcoder as it appears to have the same
748 * problem. We may need to extend this to include other platforms,
749 * but so far testing only shows the problem on HSW.
751 if (HAS_DDI(dev_priv
) && !position
) {
754 for (i
= 0; i
< 100; i
++) {
756 temp
= __raw_i915_read32(dev_priv
, PIPEDSL(pipe
)) &
758 if (temp
!= position
) {
766 * See update_scanline_offset() for the details on the
767 * scanline_offset adjustment.
769 return (position
+ crtc
->scanline_offset
) % vtotal
;
772 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, unsigned int pipe
,
773 unsigned int flags
, int *vpos
, int *hpos
,
774 ktime_t
*stime
, ktime_t
*etime
,
775 const struct drm_display_mode
*mode
)
777 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
778 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
779 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
781 int vbl_start
, vbl_end
, hsync_start
, htotal
, vtotal
;
784 unsigned long irqflags
;
786 if (WARN_ON(!mode
->crtc_clock
)) {
787 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
788 "pipe %c\n", pipe_name(pipe
));
792 htotal
= mode
->crtc_htotal
;
793 hsync_start
= mode
->crtc_hsync_start
;
794 vtotal
= mode
->crtc_vtotal
;
795 vbl_start
= mode
->crtc_vblank_start
;
796 vbl_end
= mode
->crtc_vblank_end
;
798 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
799 vbl_start
= DIV_ROUND_UP(vbl_start
, 2);
804 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
807 * Lock uncore.lock, as we will do multiple timing critical raw
808 * register reads, potentially with preemption disabled, so the
809 * following code must not block on uncore.lock.
811 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
813 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
815 /* Get optional system timestamp before query. */
817 *stime
= ktime_get();
819 if (IS_GEN2(dev_priv
) || IS_G4X(dev_priv
) || INTEL_GEN(dev_priv
) >= 5) {
820 /* No obvious pixelcount register. Only query vertical
821 * scanout position from Display scan line register.
823 position
= __intel_get_crtc_scanline(intel_crtc
);
825 /* Have access to pixelcount since start of frame.
826 * We can split this into vertical and horizontal
829 position
= (I915_READ_FW(PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
831 /* convert to pixel counts */
837 * In interlaced modes, the pixel counter counts all pixels,
838 * so one field will have htotal more pixels. In order to avoid
839 * the reported position from jumping backwards when the pixel
840 * counter is beyond the length of the shorter field, just
841 * clamp the position the length of the shorter field. This
842 * matches how the scanline counter based position works since
843 * the scanline counter doesn't count the two half lines.
845 if (position
>= vtotal
)
846 position
= vtotal
- 1;
849 * Start of vblank interrupt is triggered at start of hsync,
850 * just prior to the first active line of vblank. However we
851 * consider lines to start at the leading edge of horizontal
852 * active. So, should we get here before we've crossed into
853 * the horizontal active of the first line in vblank, we would
854 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
855 * always add htotal-hsync_start to the current pixel position.
857 position
= (position
+ htotal
- hsync_start
) % vtotal
;
860 /* Get optional system timestamp after query. */
862 *etime
= ktime_get();
864 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
866 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
868 in_vbl
= position
>= vbl_start
&& position
< vbl_end
;
871 * While in vblank, position will be negative
872 * counting up towards 0 at vbl_end. And outside
873 * vblank, position will be positive counting
876 if (position
>= vbl_start
)
879 position
+= vtotal
- vbl_end
;
881 if (IS_GEN2(dev_priv
) || IS_G4X(dev_priv
) || INTEL_GEN(dev_priv
) >= 5) {
885 *vpos
= position
/ htotal
;
886 *hpos
= position
- (*vpos
* htotal
);
891 ret
|= DRM_SCANOUTPOS_IN_VBLANK
;
896 int intel_get_crtc_scanline(struct intel_crtc
*crtc
)
898 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
899 unsigned long irqflags
;
902 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
903 position
= __intel_get_crtc_scanline(crtc
);
904 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
909 static int i915_get_vblank_timestamp(struct drm_device
*dev
, unsigned int pipe
,
911 struct timeval
*vblank_time
,
914 struct drm_crtc
*crtc
;
916 if (pipe
>= INTEL_INFO(dev
)->num_pipes
) {
917 DRM_ERROR("Invalid crtc %u\n", pipe
);
921 /* Get drm_crtc to timestamp: */
922 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
924 DRM_ERROR("Invalid crtc %u\n", pipe
);
928 if (!crtc
->hwmode
.crtc_clock
) {
929 DRM_DEBUG_KMS("crtc %u is disabled\n", pipe
);
933 /* Helper routine in DRM core does all the work: */
934 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
939 static void ironlake_rps_change_irq_handler(struct drm_i915_private
*dev_priv
)
941 u32 busy_up
, busy_down
, max_avg
, min_avg
;
944 spin_lock(&mchdev_lock
);
946 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
948 new_delay
= dev_priv
->ips
.cur_delay
;
950 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
951 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
952 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
953 max_avg
= I915_READ(RCBMAXAVG
);
954 min_avg
= I915_READ(RCBMINAVG
);
956 /* Handle RCS change request from hw */
957 if (busy_up
> max_avg
) {
958 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
959 new_delay
= dev_priv
->ips
.cur_delay
- 1;
960 if (new_delay
< dev_priv
->ips
.max_delay
)
961 new_delay
= dev_priv
->ips
.max_delay
;
962 } else if (busy_down
< min_avg
) {
963 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
964 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
965 if (new_delay
> dev_priv
->ips
.min_delay
)
966 new_delay
= dev_priv
->ips
.min_delay
;
969 if (ironlake_set_drps(dev_priv
, new_delay
))
970 dev_priv
->ips
.cur_delay
= new_delay
;
972 spin_unlock(&mchdev_lock
);
977 static void notify_ring(struct intel_engine_cs
*engine
)
979 if (!intel_engine_initialized(engine
))
982 trace_i915_gem_request_notify(engine
);
983 engine
->user_interrupts
++;
985 wake_up_all(&engine
->irq_queue
);
988 static void vlv_c0_read(struct drm_i915_private
*dev_priv
,
989 struct intel_rps_ei
*ei
)
991 ei
->cz_clock
= vlv_punit_read(dev_priv
, PUNIT_REG_CZ_TIMESTAMP
);
992 ei
->render_c0
= I915_READ(VLV_RENDER_C0_COUNT
);
993 ei
->media_c0
= I915_READ(VLV_MEDIA_C0_COUNT
);
996 static bool vlv_c0_above(struct drm_i915_private
*dev_priv
,
997 const struct intel_rps_ei
*old
,
998 const struct intel_rps_ei
*now
,
1002 unsigned int mul
= 100;
1004 if (old
->cz_clock
== 0)
1007 if (I915_READ(VLV_COUNTER_CONTROL
) & VLV_COUNT_RANGE_HIGH
)
1010 time
= now
->cz_clock
- old
->cz_clock
;
1011 time
*= threshold
* dev_priv
->czclk_freq
;
1013 /* Workload can be split between render + media, e.g. SwapBuffers
1014 * being blitted in X after being rendered in mesa. To account for
1015 * this we need to combine both engines into our activity counter.
1017 c0
= now
->render_c0
- old
->render_c0
;
1018 c0
+= now
->media_c0
- old
->media_c0
;
1019 c0
*= mul
* VLV_CZ_CLOCK_TO_MILLI_SEC
;
1024 void gen6_rps_reset_ei(struct drm_i915_private
*dev_priv
)
1026 vlv_c0_read(dev_priv
, &dev_priv
->rps
.down_ei
);
1027 dev_priv
->rps
.up_ei
= dev_priv
->rps
.down_ei
;
1030 static u32
vlv_wa_c0_ei(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1032 struct intel_rps_ei now
;
1035 if ((pm_iir
& (GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_UP_EI_EXPIRED
)) == 0)
1038 vlv_c0_read(dev_priv
, &now
);
1039 if (now
.cz_clock
== 0)
1042 if (pm_iir
& GEN6_PM_RP_DOWN_EI_EXPIRED
) {
1043 if (!vlv_c0_above(dev_priv
,
1044 &dev_priv
->rps
.down_ei
, &now
,
1045 dev_priv
->rps
.down_threshold
))
1046 events
|= GEN6_PM_RP_DOWN_THRESHOLD
;
1047 dev_priv
->rps
.down_ei
= now
;
1050 if (pm_iir
& GEN6_PM_RP_UP_EI_EXPIRED
) {
1051 if (vlv_c0_above(dev_priv
,
1052 &dev_priv
->rps
.up_ei
, &now
,
1053 dev_priv
->rps
.up_threshold
))
1054 events
|= GEN6_PM_RP_UP_THRESHOLD
;
1055 dev_priv
->rps
.up_ei
= now
;
1061 static bool any_waiters(struct drm_i915_private
*dev_priv
)
1063 struct intel_engine_cs
*engine
;
1065 for_each_engine(engine
, dev_priv
)
1066 if (engine
->irq_refcount
)
1072 static void gen6_pm_rps_work(struct work_struct
*work
)
1074 struct drm_i915_private
*dev_priv
=
1075 container_of(work
, struct drm_i915_private
, rps
.work
);
1077 int new_delay
, adj
, min
, max
;
1080 spin_lock_irq(&dev_priv
->irq_lock
);
1081 /* Speed up work cancelation during disabling rps interrupts. */
1082 if (!dev_priv
->rps
.interrupts_enabled
) {
1083 spin_unlock_irq(&dev_priv
->irq_lock
);
1088 * The RPS work is synced during runtime suspend, we don't require a
1089 * wakeref. TODO: instead of disabling the asserts make sure that we
1090 * always hold an RPM reference while the work is running.
1092 DISABLE_RPM_WAKEREF_ASSERTS(dev_priv
);
1094 pm_iir
= dev_priv
->rps
.pm_iir
;
1095 dev_priv
->rps
.pm_iir
= 0;
1096 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1097 gen6_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
1098 client_boost
= dev_priv
->rps
.client_boost
;
1099 dev_priv
->rps
.client_boost
= false;
1100 spin_unlock_irq(&dev_priv
->irq_lock
);
1102 /* Make sure we didn't queue anything we're not going to process. */
1103 WARN_ON(pm_iir
& ~dev_priv
->pm_rps_events
);
1105 if ((pm_iir
& dev_priv
->pm_rps_events
) == 0 && !client_boost
)
1108 mutex_lock(&dev_priv
->rps
.hw_lock
);
1110 pm_iir
|= vlv_wa_c0_ei(dev_priv
, pm_iir
);
1112 adj
= dev_priv
->rps
.last_adj
;
1113 new_delay
= dev_priv
->rps
.cur_freq
;
1114 min
= dev_priv
->rps
.min_freq_softlimit
;
1115 max
= dev_priv
->rps
.max_freq_softlimit
;
1118 new_delay
= dev_priv
->rps
.max_freq_softlimit
;
1120 } else if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
) {
1123 else /* CHV needs even encode values */
1124 adj
= IS_CHERRYVIEW(dev_priv
) ? 2 : 1;
1126 * For better performance, jump directly
1127 * to RPe if we're below it.
1129 if (new_delay
< dev_priv
->rps
.efficient_freq
- adj
) {
1130 new_delay
= dev_priv
->rps
.efficient_freq
;
1133 } else if (any_waiters(dev_priv
)) {
1135 } else if (pm_iir
& GEN6_PM_RP_DOWN_TIMEOUT
) {
1136 if (dev_priv
->rps
.cur_freq
> dev_priv
->rps
.efficient_freq
)
1137 new_delay
= dev_priv
->rps
.efficient_freq
;
1139 new_delay
= dev_priv
->rps
.min_freq_softlimit
;
1141 } else if (pm_iir
& GEN6_PM_RP_DOWN_THRESHOLD
) {
1144 else /* CHV needs even encode values */
1145 adj
= IS_CHERRYVIEW(dev_priv
) ? -2 : -1;
1146 } else { /* unknown event */
1150 dev_priv
->rps
.last_adj
= adj
;
1152 /* sysfs frequency interfaces may have snuck in while servicing the
1156 new_delay
= clamp_t(int, new_delay
, min
, max
);
1158 intel_set_rps(dev_priv
, new_delay
);
1160 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1162 ENABLE_RPM_WAKEREF_ASSERTS(dev_priv
);
1167 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1169 * @work: workqueue struct
1171 * Doesn't actually do anything except notify userspace. As a consequence of
1172 * this event, userspace should try to remap the bad rows since statistically
1173 * it is likely the same row is more likely to go bad again.
1175 static void ivybridge_parity_work(struct work_struct
*work
)
1177 struct drm_i915_private
*dev_priv
=
1178 container_of(work
, struct drm_i915_private
, l3_parity
.error_work
);
1179 u32 error_status
, row
, bank
, subbank
;
1180 char *parity_event
[6];
1184 /* We must turn off DOP level clock gating to access the L3 registers.
1185 * In order to prevent a get/put style interface, acquire struct mutex
1186 * any time we access those registers.
1188 mutex_lock(&dev_priv
->dev
->struct_mutex
);
1190 /* If we've screwed up tracking, just let the interrupt fire again */
1191 if (WARN_ON(!dev_priv
->l3_parity
.which_slice
))
1194 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
1195 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
1196 POSTING_READ(GEN7_MISCCPCTL
);
1198 while ((slice
= ffs(dev_priv
->l3_parity
.which_slice
)) != 0) {
1202 if (WARN_ON_ONCE(slice
>= NUM_L3_SLICES(dev_priv
)))
1205 dev_priv
->l3_parity
.which_slice
&= ~(1<<slice
);
1207 reg
= GEN7_L3CDERRST1(slice
);
1209 error_status
= I915_READ(reg
);
1210 row
= GEN7_PARITY_ERROR_ROW(error_status
);
1211 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
1212 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
1214 I915_WRITE(reg
, GEN7_PARITY_ERROR_VALID
| GEN7_L3CDERRST1_ENABLE
);
1217 parity_event
[0] = I915_L3_PARITY_UEVENT
"=1";
1218 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
1219 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
1220 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
1221 parity_event
[4] = kasprintf(GFP_KERNEL
, "SLICE=%d", slice
);
1222 parity_event
[5] = NULL
;
1224 kobject_uevent_env(&dev_priv
->dev
->primary
->kdev
->kobj
,
1225 KOBJ_CHANGE
, parity_event
);
1227 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1228 slice
, row
, bank
, subbank
);
1230 kfree(parity_event
[4]);
1231 kfree(parity_event
[3]);
1232 kfree(parity_event
[2]);
1233 kfree(parity_event
[1]);
1236 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
1239 WARN_ON(dev_priv
->l3_parity
.which_slice
);
1240 spin_lock_irq(&dev_priv
->irq_lock
);
1241 gen5_enable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev_priv
));
1242 spin_unlock_irq(&dev_priv
->irq_lock
);
1244 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
1247 static void ivybridge_parity_error_irq_handler(struct drm_i915_private
*dev_priv
,
1250 if (!HAS_L3_DPF(dev_priv
))
1253 spin_lock(&dev_priv
->irq_lock
);
1254 gen5_disable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev_priv
));
1255 spin_unlock(&dev_priv
->irq_lock
);
1257 iir
&= GT_PARITY_ERROR(dev_priv
);
1258 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1
)
1259 dev_priv
->l3_parity
.which_slice
|= 1 << 1;
1261 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT
)
1262 dev_priv
->l3_parity
.which_slice
|= 1 << 0;
1264 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
1267 static void ilk_gt_irq_handler(struct drm_i915_private
*dev_priv
,
1271 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1272 notify_ring(&dev_priv
->engine
[RCS
]);
1273 if (gt_iir
& ILK_BSD_USER_INTERRUPT
)
1274 notify_ring(&dev_priv
->engine
[VCS
]);
1277 static void snb_gt_irq_handler(struct drm_i915_private
*dev_priv
,
1282 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1283 notify_ring(&dev_priv
->engine
[RCS
]);
1284 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
1285 notify_ring(&dev_priv
->engine
[VCS
]);
1286 if (gt_iir
& GT_BLT_USER_INTERRUPT
)
1287 notify_ring(&dev_priv
->engine
[BCS
]);
1289 if (gt_iir
& (GT_BLT_CS_ERROR_INTERRUPT
|
1290 GT_BSD_CS_ERROR_INTERRUPT
|
1291 GT_RENDER_CS_MASTER_ERROR_INTERRUPT
))
1292 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir
);
1294 if (gt_iir
& GT_PARITY_ERROR(dev_priv
))
1295 ivybridge_parity_error_irq_handler(dev_priv
, gt_iir
);
1298 static __always_inline
void
1299 gen8_cs_irq_handler(struct intel_engine_cs
*engine
, u32 iir
, int test_shift
)
1301 if (iir
& (GT_RENDER_USER_INTERRUPT
<< test_shift
))
1302 notify_ring(engine
);
1303 if (iir
& (GT_CONTEXT_SWITCH_INTERRUPT
<< test_shift
))
1304 tasklet_schedule(&engine
->irq_tasklet
);
1307 static irqreturn_t
gen8_gt_irq_ack(struct drm_i915_private
*dev_priv
,
1311 irqreturn_t ret
= IRQ_NONE
;
1313 if (master_ctl
& (GEN8_GT_RCS_IRQ
| GEN8_GT_BCS_IRQ
)) {
1314 gt_iir
[0] = I915_READ_FW(GEN8_GT_IIR(0));
1316 I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir
[0]);
1319 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1322 if (master_ctl
& (GEN8_GT_VCS1_IRQ
| GEN8_GT_VCS2_IRQ
)) {
1323 gt_iir
[1] = I915_READ_FW(GEN8_GT_IIR(1));
1325 I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir
[1]);
1328 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1331 if (master_ctl
& GEN8_GT_VECS_IRQ
) {
1332 gt_iir
[3] = I915_READ_FW(GEN8_GT_IIR(3));
1334 I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir
[3]);
1337 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1340 if (master_ctl
& GEN8_GT_PM_IRQ
) {
1341 gt_iir
[2] = I915_READ_FW(GEN8_GT_IIR(2));
1342 if (gt_iir
[2] & dev_priv
->pm_rps_events
) {
1343 I915_WRITE_FW(GEN8_GT_IIR(2),
1344 gt_iir
[2] & dev_priv
->pm_rps_events
);
1347 DRM_ERROR("The master control interrupt lied (PM)!\n");
1353 static void gen8_gt_irq_handler(struct drm_i915_private
*dev_priv
,
1357 gen8_cs_irq_handler(&dev_priv
->engine
[RCS
],
1358 gt_iir
[0], GEN8_RCS_IRQ_SHIFT
);
1359 gen8_cs_irq_handler(&dev_priv
->engine
[BCS
],
1360 gt_iir
[0], GEN8_BCS_IRQ_SHIFT
);
1364 gen8_cs_irq_handler(&dev_priv
->engine
[VCS
],
1365 gt_iir
[1], GEN8_VCS1_IRQ_SHIFT
);
1366 gen8_cs_irq_handler(&dev_priv
->engine
[VCS2
],
1367 gt_iir
[1], GEN8_VCS2_IRQ_SHIFT
);
1371 gen8_cs_irq_handler(&dev_priv
->engine
[VECS
],
1372 gt_iir
[3], GEN8_VECS_IRQ_SHIFT
);
1374 if (gt_iir
[2] & dev_priv
->pm_rps_events
)
1375 gen6_rps_irq_handler(dev_priv
, gt_iir
[2]);
1378 static bool bxt_port_hotplug_long_detect(enum port port
, u32 val
)
1382 return val
& PORTA_HOTPLUG_LONG_DETECT
;
1384 return val
& PORTB_HOTPLUG_LONG_DETECT
;
1386 return val
& PORTC_HOTPLUG_LONG_DETECT
;
1392 static bool spt_port_hotplug2_long_detect(enum port port
, u32 val
)
1396 return val
& PORTE_HOTPLUG_LONG_DETECT
;
1402 static bool spt_port_hotplug_long_detect(enum port port
, u32 val
)
1406 return val
& PORTA_HOTPLUG_LONG_DETECT
;
1408 return val
& PORTB_HOTPLUG_LONG_DETECT
;
1410 return val
& PORTC_HOTPLUG_LONG_DETECT
;
1412 return val
& PORTD_HOTPLUG_LONG_DETECT
;
1418 static bool ilk_port_hotplug_long_detect(enum port port
, u32 val
)
1422 return val
& DIGITAL_PORTA_HOTPLUG_LONG_DETECT
;
1428 static bool pch_port_hotplug_long_detect(enum port port
, u32 val
)
1432 return val
& PORTB_HOTPLUG_LONG_DETECT
;
1434 return val
& PORTC_HOTPLUG_LONG_DETECT
;
1436 return val
& PORTD_HOTPLUG_LONG_DETECT
;
1442 static bool i9xx_port_hotplug_long_detect(enum port port
, u32 val
)
1446 return val
& PORTB_HOTPLUG_INT_LONG_PULSE
;
1448 return val
& PORTC_HOTPLUG_INT_LONG_PULSE
;
1450 return val
& PORTD_HOTPLUG_INT_LONG_PULSE
;
1457 * Get a bit mask of pins that have triggered, and which ones may be long.
1458 * This can be called multiple times with the same masks to accumulate
1459 * hotplug detection results from several registers.
1461 * Note that the caller is expected to zero out the masks initially.
1463 static void intel_get_hpd_pins(u32
*pin_mask
, u32
*long_mask
,
1464 u32 hotplug_trigger
, u32 dig_hotplug_reg
,
1465 const u32 hpd
[HPD_NUM_PINS
],
1466 bool long_pulse_detect(enum port port
, u32 val
))
1471 for_each_hpd_pin(i
) {
1472 if ((hpd
[i
] & hotplug_trigger
) == 0)
1475 *pin_mask
|= BIT(i
);
1477 if (!intel_hpd_pin_to_port(i
, &port
))
1480 if (long_pulse_detect(port
, dig_hotplug_reg
))
1481 *long_mask
|= BIT(i
);
1484 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1485 hotplug_trigger
, dig_hotplug_reg
, *pin_mask
);
1489 static void gmbus_irq_handler(struct drm_i915_private
*dev_priv
)
1491 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1494 static void dp_aux_irq_handler(struct drm_i915_private
*dev_priv
)
1496 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1499 #if defined(CONFIG_DEBUG_FS)
1500 static void display_pipe_crc_irq_handler(struct drm_i915_private
*dev_priv
,
1502 uint32_t crc0
, uint32_t crc1
,
1503 uint32_t crc2
, uint32_t crc3
,
1506 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
1507 struct intel_pipe_crc_entry
*entry
;
1510 spin_lock(&pipe_crc
->lock
);
1512 if (!pipe_crc
->entries
) {
1513 spin_unlock(&pipe_crc
->lock
);
1514 DRM_DEBUG_KMS("spurious interrupt\n");
1518 head
= pipe_crc
->head
;
1519 tail
= pipe_crc
->tail
;
1521 if (CIRC_SPACE(head
, tail
, INTEL_PIPE_CRC_ENTRIES_NR
) < 1) {
1522 spin_unlock(&pipe_crc
->lock
);
1523 DRM_ERROR("CRC buffer overflowing\n");
1527 entry
= &pipe_crc
->entries
[head
];
1529 entry
->frame
= dev_priv
->dev
->driver
->get_vblank_counter(dev_priv
->dev
,
1531 entry
->crc
[0] = crc0
;
1532 entry
->crc
[1] = crc1
;
1533 entry
->crc
[2] = crc2
;
1534 entry
->crc
[3] = crc3
;
1535 entry
->crc
[4] = crc4
;
1537 head
= (head
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
1538 pipe_crc
->head
= head
;
1540 spin_unlock(&pipe_crc
->lock
);
1542 wake_up_interruptible(&pipe_crc
->wq
);
1546 display_pipe_crc_irq_handler(struct drm_i915_private
*dev_priv
,
1548 uint32_t crc0
, uint32_t crc1
,
1549 uint32_t crc2
, uint32_t crc3
,
1554 static void hsw_pipe_crc_irq_handler(struct drm_i915_private
*dev_priv
,
1557 display_pipe_crc_irq_handler(dev_priv
, pipe
,
1558 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1562 static void ivb_pipe_crc_irq_handler(struct drm_i915_private
*dev_priv
,
1565 display_pipe_crc_irq_handler(dev_priv
, pipe
,
1566 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1567 I915_READ(PIPE_CRC_RES_2_IVB(pipe
)),
1568 I915_READ(PIPE_CRC_RES_3_IVB(pipe
)),
1569 I915_READ(PIPE_CRC_RES_4_IVB(pipe
)),
1570 I915_READ(PIPE_CRC_RES_5_IVB(pipe
)));
1573 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private
*dev_priv
,
1576 uint32_t res1
, res2
;
1578 if (INTEL_GEN(dev_priv
) >= 3)
1579 res1
= I915_READ(PIPE_CRC_RES_RES1_I915(pipe
));
1583 if (INTEL_GEN(dev_priv
) >= 5 || IS_G4X(dev_priv
))
1584 res2
= I915_READ(PIPE_CRC_RES_RES2_G4X(pipe
));
1588 display_pipe_crc_irq_handler(dev_priv
, pipe
,
1589 I915_READ(PIPE_CRC_RES_RED(pipe
)),
1590 I915_READ(PIPE_CRC_RES_GREEN(pipe
)),
1591 I915_READ(PIPE_CRC_RES_BLUE(pipe
)),
1595 /* The RPS events need forcewake, so we add them to a work queue and mask their
1596 * IMR bits until the work is done. Other interrupts can be processed without
1597 * the work queue. */
1598 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1600 if (pm_iir
& dev_priv
->pm_rps_events
) {
1601 spin_lock(&dev_priv
->irq_lock
);
1602 gen6_disable_pm_irq(dev_priv
, pm_iir
& dev_priv
->pm_rps_events
);
1603 if (dev_priv
->rps
.interrupts_enabled
) {
1604 dev_priv
->rps
.pm_iir
|= pm_iir
& dev_priv
->pm_rps_events
;
1605 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
1607 spin_unlock(&dev_priv
->irq_lock
);
1610 if (INTEL_INFO(dev_priv
)->gen
>= 8)
1613 if (HAS_VEBOX(dev_priv
)) {
1614 if (pm_iir
& PM_VEBOX_USER_INTERRUPT
)
1615 notify_ring(&dev_priv
->engine
[VECS
]);
1617 if (pm_iir
& PM_VEBOX_CS_ERROR_INTERRUPT
)
1618 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir
);
1622 static bool intel_pipe_handle_vblank(struct drm_i915_private
*dev_priv
,
1627 ret
= drm_handle_vblank(dev_priv
->dev
, pipe
);
1629 intel_finish_page_flip_mmio(dev_priv
, pipe
);
1634 static void valleyview_pipestat_irq_ack(struct drm_i915_private
*dev_priv
,
1635 u32 iir
, u32 pipe_stats
[I915_MAX_PIPES
])
1639 spin_lock(&dev_priv
->irq_lock
);
1641 if (!dev_priv
->display_irqs_enabled
) {
1642 spin_unlock(&dev_priv
->irq_lock
);
1646 for_each_pipe(dev_priv
, pipe
) {
1648 u32 mask
, iir_bit
= 0;
1651 * PIPESTAT bits get signalled even when the interrupt is
1652 * disabled with the mask bits, and some of the status bits do
1653 * not generate interrupts at all (like the underrun bit). Hence
1654 * we need to be careful that we only handle what we want to
1658 /* fifo underruns are filterered in the underrun handler. */
1659 mask
= PIPE_FIFO_UNDERRUN_STATUS
;
1663 iir_bit
= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
;
1666 iir_bit
= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
1669 iir_bit
= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
;
1673 mask
|= dev_priv
->pipestat_irq_mask
[pipe
];
1678 reg
= PIPESTAT(pipe
);
1679 mask
|= PIPESTAT_INT_ENABLE_MASK
;
1680 pipe_stats
[pipe
] = I915_READ(reg
) & mask
;
1683 * Clear the PIPE*STAT regs before the IIR
1685 if (pipe_stats
[pipe
] & (PIPE_FIFO_UNDERRUN_STATUS
|
1686 PIPESTAT_INT_STATUS_MASK
))
1687 I915_WRITE(reg
, pipe_stats
[pipe
]);
1689 spin_unlock(&dev_priv
->irq_lock
);
1692 static void valleyview_pipestat_irq_handler(struct drm_i915_private
*dev_priv
,
1693 u32 pipe_stats
[I915_MAX_PIPES
])
1697 for_each_pipe(dev_priv
, pipe
) {
1698 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
1699 intel_pipe_handle_vblank(dev_priv
, pipe
))
1700 intel_check_page_flip(dev_priv
, pipe
);
1702 if (pipe_stats
[pipe
] & PLANE_FLIP_DONE_INT_STATUS_VLV
)
1703 intel_finish_page_flip_cs(dev_priv
, pipe
);
1705 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
1706 i9xx_pipe_crc_irq_handler(dev_priv
, pipe
);
1708 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
1709 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
1712 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1713 gmbus_irq_handler(dev_priv
);
1716 static u32
i9xx_hpd_irq_ack(struct drm_i915_private
*dev_priv
)
1718 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1721 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1723 return hotplug_status
;
1726 static void i9xx_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
1729 u32 pin_mask
= 0, long_mask
= 0;
1731 if (IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
1732 IS_CHERRYVIEW(dev_priv
)) {
1733 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_G4X
;
1735 if (hotplug_trigger
) {
1736 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
1737 hotplug_trigger
, hpd_status_g4x
,
1738 i9xx_port_hotplug_long_detect
);
1740 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
1743 if (hotplug_status
& DP_AUX_CHANNEL_MASK_INT_STATUS_G4X
)
1744 dp_aux_irq_handler(dev_priv
);
1746 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
1748 if (hotplug_trigger
) {
1749 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
1750 hotplug_trigger
, hpd_status_i915
,
1751 i9xx_port_hotplug_long_detect
);
1752 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
1757 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
1759 struct drm_device
*dev
= arg
;
1760 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1761 irqreturn_t ret
= IRQ_NONE
;
1763 if (!intel_irqs_enabled(dev_priv
))
1766 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1767 disable_rpm_wakeref_asserts(dev_priv
);
1770 u32 iir
, gt_iir
, pm_iir
;
1771 u32 pipe_stats
[I915_MAX_PIPES
] = {};
1772 u32 hotplug_status
= 0;
1775 gt_iir
= I915_READ(GTIIR
);
1776 pm_iir
= I915_READ(GEN6_PMIIR
);
1777 iir
= I915_READ(VLV_IIR
);
1779 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
1785 * Theory on interrupt generation, based on empirical evidence:
1787 * x = ((VLV_IIR & VLV_IER) ||
1788 * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1789 * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1791 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1792 * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1793 * guarantee the CPU interrupt will be raised again even if we
1794 * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1795 * bits this time around.
1797 I915_WRITE(VLV_MASTER_IER
, 0);
1798 ier
= I915_READ(VLV_IER
);
1799 I915_WRITE(VLV_IER
, 0);
1802 I915_WRITE(GTIIR
, gt_iir
);
1804 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1806 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
1807 hotplug_status
= i9xx_hpd_irq_ack(dev_priv
);
1809 /* Call regardless, as some status bits might not be
1810 * signalled in iir */
1811 valleyview_pipestat_irq_ack(dev_priv
, iir
, pipe_stats
);
1814 * VLV_IIR is single buffered, and reflects the level
1815 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1818 I915_WRITE(VLV_IIR
, iir
);
1820 I915_WRITE(VLV_IER
, ier
);
1821 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
1822 POSTING_READ(VLV_MASTER_IER
);
1825 snb_gt_irq_handler(dev_priv
, gt_iir
);
1827 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1830 i9xx_hpd_irq_handler(dev_priv
, hotplug_status
);
1832 valleyview_pipestat_irq_handler(dev_priv
, pipe_stats
);
1835 enable_rpm_wakeref_asserts(dev_priv
);
1840 static irqreturn_t
cherryview_irq_handler(int irq
, void *arg
)
1842 struct drm_device
*dev
= arg
;
1843 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1844 irqreturn_t ret
= IRQ_NONE
;
1846 if (!intel_irqs_enabled(dev_priv
))
1849 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1850 disable_rpm_wakeref_asserts(dev_priv
);
1853 u32 master_ctl
, iir
;
1855 u32 pipe_stats
[I915_MAX_PIPES
] = {};
1856 u32 hotplug_status
= 0;
1859 master_ctl
= I915_READ(GEN8_MASTER_IRQ
) & ~GEN8_MASTER_IRQ_CONTROL
;
1860 iir
= I915_READ(VLV_IIR
);
1862 if (master_ctl
== 0 && iir
== 0)
1868 * Theory on interrupt generation, based on empirical evidence:
1870 * x = ((VLV_IIR & VLV_IER) ||
1871 * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
1872 * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
1874 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1875 * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
1876 * guarantee the CPU interrupt will be raised again even if we
1877 * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
1878 * bits this time around.
1880 I915_WRITE(GEN8_MASTER_IRQ
, 0);
1881 ier
= I915_READ(VLV_IER
);
1882 I915_WRITE(VLV_IER
, 0);
1884 gen8_gt_irq_ack(dev_priv
, master_ctl
, gt_iir
);
1886 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
1887 hotplug_status
= i9xx_hpd_irq_ack(dev_priv
);
1889 /* Call regardless, as some status bits might not be
1890 * signalled in iir */
1891 valleyview_pipestat_irq_ack(dev_priv
, iir
, pipe_stats
);
1894 * VLV_IIR is single buffered, and reflects the level
1895 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1898 I915_WRITE(VLV_IIR
, iir
);
1900 I915_WRITE(VLV_IER
, ier
);
1901 I915_WRITE(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
1902 POSTING_READ(GEN8_MASTER_IRQ
);
1904 gen8_gt_irq_handler(dev_priv
, gt_iir
);
1907 i9xx_hpd_irq_handler(dev_priv
, hotplug_status
);
1909 valleyview_pipestat_irq_handler(dev_priv
, pipe_stats
);
1912 enable_rpm_wakeref_asserts(dev_priv
);
1917 static void ibx_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
1918 u32 hotplug_trigger
,
1919 const u32 hpd
[HPD_NUM_PINS
])
1921 u32 dig_hotplug_reg
, pin_mask
= 0, long_mask
= 0;
1924 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
1925 * unless we touch the hotplug register, even if hotplug_trigger is
1926 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
1929 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
1930 if (!hotplug_trigger
) {
1931 u32 mask
= PORTA_HOTPLUG_STATUS_MASK
|
1932 PORTD_HOTPLUG_STATUS_MASK
|
1933 PORTC_HOTPLUG_STATUS_MASK
|
1934 PORTB_HOTPLUG_STATUS_MASK
;
1935 dig_hotplug_reg
&= ~mask
;
1938 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
1939 if (!hotplug_trigger
)
1942 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
1943 dig_hotplug_reg
, hpd
,
1944 pch_port_hotplug_long_detect
);
1946 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
1949 static void ibx_irq_handler(struct drm_i915_private
*dev_priv
, u32 pch_iir
)
1952 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK
;
1954 ibx_hpd_irq_handler(dev_priv
, hotplug_trigger
, hpd_ibx
);
1956 if (pch_iir
& SDE_AUDIO_POWER_MASK
) {
1957 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK
) >>
1958 SDE_AUDIO_POWER_SHIFT
);
1959 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1963 if (pch_iir
& SDE_AUX_MASK
)
1964 dp_aux_irq_handler(dev_priv
);
1966 if (pch_iir
& SDE_GMBUS
)
1967 gmbus_irq_handler(dev_priv
);
1969 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
1970 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1972 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
1973 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1975 if (pch_iir
& SDE_POISON
)
1976 DRM_ERROR("PCH poison interrupt\n");
1978 if (pch_iir
& SDE_FDI_MASK
)
1979 for_each_pipe(dev_priv
, pipe
)
1980 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1982 I915_READ(FDI_RX_IIR(pipe
)));
1984 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
1985 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1987 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
1988 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1990 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
1991 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_A
);
1993 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
1994 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_B
);
1997 static void ivb_err_int_handler(struct drm_i915_private
*dev_priv
)
1999 u32 err_int
= I915_READ(GEN7_ERR_INT
);
2002 if (err_int
& ERR_INT_POISON
)
2003 DRM_ERROR("Poison interrupt\n");
2005 for_each_pipe(dev_priv
, pipe
) {
2006 if (err_int
& ERR_INT_FIFO_UNDERRUN(pipe
))
2007 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
2009 if (err_int
& ERR_INT_PIPE_CRC_DONE(pipe
)) {
2010 if (IS_IVYBRIDGE(dev_priv
))
2011 ivb_pipe_crc_irq_handler(dev_priv
, pipe
);
2013 hsw_pipe_crc_irq_handler(dev_priv
, pipe
);
2017 I915_WRITE(GEN7_ERR_INT
, err_int
);
2020 static void cpt_serr_int_handler(struct drm_i915_private
*dev_priv
)
2022 u32 serr_int
= I915_READ(SERR_INT
);
2024 if (serr_int
& SERR_INT_POISON
)
2025 DRM_ERROR("PCH poison interrupt\n");
2027 if (serr_int
& SERR_INT_TRANS_A_FIFO_UNDERRUN
)
2028 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_A
);
2030 if (serr_int
& SERR_INT_TRANS_B_FIFO_UNDERRUN
)
2031 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_B
);
2033 if (serr_int
& SERR_INT_TRANS_C_FIFO_UNDERRUN
)
2034 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_C
);
2036 I915_WRITE(SERR_INT
, serr_int
);
2039 static void cpt_irq_handler(struct drm_i915_private
*dev_priv
, u32 pch_iir
)
2042 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_CPT
;
2044 ibx_hpd_irq_handler(dev_priv
, hotplug_trigger
, hpd_cpt
);
2046 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) {
2047 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
2048 SDE_AUDIO_POWER_SHIFT_CPT
);
2049 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2053 if (pch_iir
& SDE_AUX_MASK_CPT
)
2054 dp_aux_irq_handler(dev_priv
);
2056 if (pch_iir
& SDE_GMBUS_CPT
)
2057 gmbus_irq_handler(dev_priv
);
2059 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
2060 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2062 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
2063 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2065 if (pch_iir
& SDE_FDI_MASK_CPT
)
2066 for_each_pipe(dev_priv
, pipe
)
2067 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2069 I915_READ(FDI_RX_IIR(pipe
)));
2071 if (pch_iir
& SDE_ERROR_CPT
)
2072 cpt_serr_int_handler(dev_priv
);
2075 static void spt_irq_handler(struct drm_i915_private
*dev_priv
, u32 pch_iir
)
2077 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_SPT
&
2078 ~SDE_PORTE_HOTPLUG_SPT
;
2079 u32 hotplug2_trigger
= pch_iir
& SDE_PORTE_HOTPLUG_SPT
;
2080 u32 pin_mask
= 0, long_mask
= 0;
2082 if (hotplug_trigger
) {
2083 u32 dig_hotplug_reg
;
2085 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
2086 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
2088 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
2089 dig_hotplug_reg
, hpd_spt
,
2090 spt_port_hotplug_long_detect
);
2093 if (hotplug2_trigger
) {
2094 u32 dig_hotplug_reg
;
2096 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG2
);
2097 I915_WRITE(PCH_PORT_HOTPLUG2
, dig_hotplug_reg
);
2099 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug2_trigger
,
2100 dig_hotplug_reg
, hpd_spt
,
2101 spt_port_hotplug2_long_detect
);
2105 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
2107 if (pch_iir
& SDE_GMBUS_CPT
)
2108 gmbus_irq_handler(dev_priv
);
2111 static void ilk_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
2112 u32 hotplug_trigger
,
2113 const u32 hpd
[HPD_NUM_PINS
])
2115 u32 dig_hotplug_reg
, pin_mask
= 0, long_mask
= 0;
2117 dig_hotplug_reg
= I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL
);
2118 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL
, dig_hotplug_reg
);
2120 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
2121 dig_hotplug_reg
, hpd
,
2122 ilk_port_hotplug_long_detect
);
2124 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
2127 static void ilk_display_irq_handler(struct drm_i915_private
*dev_priv
,
2131 u32 hotplug_trigger
= de_iir
& DE_DP_A_HOTPLUG
;
2133 if (hotplug_trigger
)
2134 ilk_hpd_irq_handler(dev_priv
, hotplug_trigger
, hpd_ilk
);
2136 if (de_iir
& DE_AUX_CHANNEL_A
)
2137 dp_aux_irq_handler(dev_priv
);
2139 if (de_iir
& DE_GSE
)
2140 intel_opregion_asle_intr(dev_priv
);
2142 if (de_iir
& DE_POISON
)
2143 DRM_ERROR("Poison interrupt\n");
2145 for_each_pipe(dev_priv
, pipe
) {
2146 if (de_iir
& DE_PIPE_VBLANK(pipe
) &&
2147 intel_pipe_handle_vblank(dev_priv
, pipe
))
2148 intel_check_page_flip(dev_priv
, pipe
);
2150 if (de_iir
& DE_PIPE_FIFO_UNDERRUN(pipe
))
2151 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
2153 if (de_iir
& DE_PIPE_CRC_DONE(pipe
))
2154 i9xx_pipe_crc_irq_handler(dev_priv
, pipe
);
2156 /* plane/pipes map 1:1 on ilk+ */
2157 if (de_iir
& DE_PLANE_FLIP_DONE(pipe
))
2158 intel_finish_page_flip_cs(dev_priv
, pipe
);
2161 /* check event from PCH */
2162 if (de_iir
& DE_PCH_EVENT
) {
2163 u32 pch_iir
= I915_READ(SDEIIR
);
2165 if (HAS_PCH_CPT(dev_priv
))
2166 cpt_irq_handler(dev_priv
, pch_iir
);
2168 ibx_irq_handler(dev_priv
, pch_iir
);
2170 /* should clear PCH hotplug event before clear CPU irq */
2171 I915_WRITE(SDEIIR
, pch_iir
);
2174 if (IS_GEN5(dev_priv
) && de_iir
& DE_PCU_EVENT
)
2175 ironlake_rps_change_irq_handler(dev_priv
);
2178 static void ivb_display_irq_handler(struct drm_i915_private
*dev_priv
,
2182 u32 hotplug_trigger
= de_iir
& DE_DP_A_HOTPLUG_IVB
;
2184 if (hotplug_trigger
)
2185 ilk_hpd_irq_handler(dev_priv
, hotplug_trigger
, hpd_ivb
);
2187 if (de_iir
& DE_ERR_INT_IVB
)
2188 ivb_err_int_handler(dev_priv
);
2190 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
2191 dp_aux_irq_handler(dev_priv
);
2193 if (de_iir
& DE_GSE_IVB
)
2194 intel_opregion_asle_intr(dev_priv
);
2196 for_each_pipe(dev_priv
, pipe
) {
2197 if (de_iir
& (DE_PIPE_VBLANK_IVB(pipe
)) &&
2198 intel_pipe_handle_vblank(dev_priv
, pipe
))
2199 intel_check_page_flip(dev_priv
, pipe
);
2201 /* plane/pipes map 1:1 on ilk+ */
2202 if (de_iir
& DE_PLANE_FLIP_DONE_IVB(pipe
))
2203 intel_finish_page_flip_cs(dev_priv
, pipe
);
2206 /* check event from PCH */
2207 if (!HAS_PCH_NOP(dev_priv
) && (de_iir
& DE_PCH_EVENT_IVB
)) {
2208 u32 pch_iir
= I915_READ(SDEIIR
);
2210 cpt_irq_handler(dev_priv
, pch_iir
);
2212 /* clear PCH hotplug event before clear CPU irq */
2213 I915_WRITE(SDEIIR
, pch_iir
);
2218 * To handle irqs with the minimum potential races with fresh interrupts, we:
2219 * 1 - Disable Master Interrupt Control.
2220 * 2 - Find the source(s) of the interrupt.
2221 * 3 - Clear the Interrupt Identity bits (IIR).
2222 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2223 * 5 - Re-enable Master Interrupt Control.
2225 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
2227 struct drm_device
*dev
= arg
;
2228 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2229 u32 de_iir
, gt_iir
, de_ier
, sde_ier
= 0;
2230 irqreturn_t ret
= IRQ_NONE
;
2232 if (!intel_irqs_enabled(dev_priv
))
2235 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2236 disable_rpm_wakeref_asserts(dev_priv
);
2238 /* disable master interrupt before clearing iir */
2239 de_ier
= I915_READ(DEIER
);
2240 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
2241 POSTING_READ(DEIER
);
2243 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2244 * interrupts will will be stored on its back queue, and then we'll be
2245 * able to process them after we restore SDEIER (as soon as we restore
2246 * it, we'll get an interrupt if SDEIIR still has something to process
2247 * due to its back queue). */
2248 if (!HAS_PCH_NOP(dev_priv
)) {
2249 sde_ier
= I915_READ(SDEIER
);
2250 I915_WRITE(SDEIER
, 0);
2251 POSTING_READ(SDEIER
);
2254 /* Find, clear, then process each source of interrupt */
2256 gt_iir
= I915_READ(GTIIR
);
2258 I915_WRITE(GTIIR
, gt_iir
);
2260 if (INTEL_GEN(dev_priv
) >= 6)
2261 snb_gt_irq_handler(dev_priv
, gt_iir
);
2263 ilk_gt_irq_handler(dev_priv
, gt_iir
);
2266 de_iir
= I915_READ(DEIIR
);
2268 I915_WRITE(DEIIR
, de_iir
);
2270 if (INTEL_GEN(dev_priv
) >= 7)
2271 ivb_display_irq_handler(dev_priv
, de_iir
);
2273 ilk_display_irq_handler(dev_priv
, de_iir
);
2276 if (INTEL_GEN(dev_priv
) >= 6) {
2277 u32 pm_iir
= I915_READ(GEN6_PMIIR
);
2279 I915_WRITE(GEN6_PMIIR
, pm_iir
);
2281 gen6_rps_irq_handler(dev_priv
, pm_iir
);
2285 I915_WRITE(DEIER
, de_ier
);
2286 POSTING_READ(DEIER
);
2287 if (!HAS_PCH_NOP(dev_priv
)) {
2288 I915_WRITE(SDEIER
, sde_ier
);
2289 POSTING_READ(SDEIER
);
2292 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2293 enable_rpm_wakeref_asserts(dev_priv
);
2298 static void bxt_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
2299 u32 hotplug_trigger
,
2300 const u32 hpd
[HPD_NUM_PINS
])
2302 u32 dig_hotplug_reg
, pin_mask
= 0, long_mask
= 0;
2304 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
2305 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
2307 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
2308 dig_hotplug_reg
, hpd
,
2309 bxt_port_hotplug_long_detect
);
2311 intel_hpd_irq_handler(dev_priv
, pin_mask
, long_mask
);
2315 gen8_de_irq_handler(struct drm_i915_private
*dev_priv
, u32 master_ctl
)
2317 irqreturn_t ret
= IRQ_NONE
;
2321 if (master_ctl
& GEN8_DE_MISC_IRQ
) {
2322 iir
= I915_READ(GEN8_DE_MISC_IIR
);
2324 I915_WRITE(GEN8_DE_MISC_IIR
, iir
);
2326 if (iir
& GEN8_DE_MISC_GSE
)
2327 intel_opregion_asle_intr(dev_priv
);
2329 DRM_ERROR("Unexpected DE Misc interrupt\n");
2332 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2335 if (master_ctl
& GEN8_DE_PORT_IRQ
) {
2336 iir
= I915_READ(GEN8_DE_PORT_IIR
);
2341 I915_WRITE(GEN8_DE_PORT_IIR
, iir
);
2344 tmp_mask
= GEN8_AUX_CHANNEL_A
;
2345 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2346 tmp_mask
|= GEN9_AUX_CHANNEL_B
|
2347 GEN9_AUX_CHANNEL_C
|
2350 if (iir
& tmp_mask
) {
2351 dp_aux_irq_handler(dev_priv
);
2355 if (IS_BROXTON(dev_priv
)) {
2356 tmp_mask
= iir
& BXT_DE_PORT_HOTPLUG_MASK
;
2358 bxt_hpd_irq_handler(dev_priv
, tmp_mask
,
2362 } else if (IS_BROADWELL(dev_priv
)) {
2363 tmp_mask
= iir
& GEN8_PORT_DP_A_HOTPLUG
;
2365 ilk_hpd_irq_handler(dev_priv
,
2371 if (IS_BROXTON(dev_priv
) && (iir
& BXT_DE_PORT_GMBUS
)) {
2372 gmbus_irq_handler(dev_priv
);
2377 DRM_ERROR("Unexpected DE Port interrupt\n");
2380 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2383 for_each_pipe(dev_priv
, pipe
) {
2384 u32 flip_done
, fault_errors
;
2386 if (!(master_ctl
& GEN8_DE_PIPE_IRQ(pipe
)))
2389 iir
= I915_READ(GEN8_DE_PIPE_IIR(pipe
));
2391 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2396 I915_WRITE(GEN8_DE_PIPE_IIR(pipe
), iir
);
2398 if (iir
& GEN8_PIPE_VBLANK
&&
2399 intel_pipe_handle_vblank(dev_priv
, pipe
))
2400 intel_check_page_flip(dev_priv
, pipe
);
2403 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2404 flip_done
&= GEN9_PIPE_PLANE1_FLIP_DONE
;
2406 flip_done
&= GEN8_PIPE_PRIMARY_FLIP_DONE
;
2409 intel_finish_page_flip_cs(dev_priv
, pipe
);
2411 if (iir
& GEN8_PIPE_CDCLK_CRC_DONE
)
2412 hsw_pipe_crc_irq_handler(dev_priv
, pipe
);
2414 if (iir
& GEN8_PIPE_FIFO_UNDERRUN
)
2415 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
2418 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2419 fault_errors
&= GEN9_DE_PIPE_IRQ_FAULT_ERRORS
;
2421 fault_errors
&= GEN8_DE_PIPE_IRQ_FAULT_ERRORS
;
2424 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2429 if (HAS_PCH_SPLIT(dev_priv
) && !HAS_PCH_NOP(dev_priv
) &&
2430 master_ctl
& GEN8_DE_PCH_IRQ
) {
2432 * FIXME(BDW): Assume for now that the new interrupt handling
2433 * scheme also closed the SDE interrupt handling race we've seen
2434 * on older pch-split platforms. But this needs testing.
2436 iir
= I915_READ(SDEIIR
);
2438 I915_WRITE(SDEIIR
, iir
);
2441 if (HAS_PCH_SPT(dev_priv
))
2442 spt_irq_handler(dev_priv
, iir
);
2444 cpt_irq_handler(dev_priv
, iir
);
2447 * Like on previous PCH there seems to be something
2448 * fishy going on with forwarding PCH interrupts.
2450 DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2457 static irqreturn_t
gen8_irq_handler(int irq
, void *arg
)
2459 struct drm_device
*dev
= arg
;
2460 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2465 if (!intel_irqs_enabled(dev_priv
))
2468 master_ctl
= I915_READ_FW(GEN8_MASTER_IRQ
);
2469 master_ctl
&= ~GEN8_MASTER_IRQ_CONTROL
;
2473 I915_WRITE_FW(GEN8_MASTER_IRQ
, 0);
2475 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2476 disable_rpm_wakeref_asserts(dev_priv
);
2478 /* Find, clear, then process each source of interrupt */
2479 ret
= gen8_gt_irq_ack(dev_priv
, master_ctl
, gt_iir
);
2480 gen8_gt_irq_handler(dev_priv
, gt_iir
);
2481 ret
|= gen8_de_irq_handler(dev_priv
, master_ctl
);
2483 I915_WRITE_FW(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
2484 POSTING_READ_FW(GEN8_MASTER_IRQ
);
2486 enable_rpm_wakeref_asserts(dev_priv
);
2491 static void i915_error_wake_up(struct drm_i915_private
*dev_priv
,
2492 bool reset_completed
)
2494 struct intel_engine_cs
*engine
;
2497 * Notify all waiters for GPU completion events that reset state has
2498 * been changed, and that they need to restart their wait after
2499 * checking for potential errors (and bail out to drop locks if there is
2500 * a gpu reset pending so that i915_error_work_func can acquire them).
2503 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2504 for_each_engine(engine
, dev_priv
)
2505 wake_up_all(&engine
->irq_queue
);
2507 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2508 wake_up_all(&dev_priv
->pending_flip_queue
);
2511 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2512 * reset state is cleared.
2514 if (reset_completed
)
2515 wake_up_all(&dev_priv
->gpu_error
.reset_queue
);
2519 * i915_reset_and_wakeup - do process context error handling work
2520 * @dev_priv: i915 device private
2522 * Fire an error uevent so userspace can see that a hang or error
2525 static void i915_reset_and_wakeup(struct drm_i915_private
*dev_priv
)
2527 struct kobject
*kobj
= &dev_priv
->dev
->primary
->kdev
->kobj
;
2528 char *error_event
[] = { I915_ERROR_UEVENT
"=1", NULL
};
2529 char *reset_event
[] = { I915_RESET_UEVENT
"=1", NULL
};
2530 char *reset_done_event
[] = { I915_ERROR_UEVENT
"=0", NULL
};
2533 kobject_uevent_env(kobj
, KOBJ_CHANGE
, error_event
);
2536 * Note that there's only one work item which does gpu resets, so we
2537 * need not worry about concurrent gpu resets potentially incrementing
2538 * error->reset_counter twice. We only need to take care of another
2539 * racing irq/hangcheck declaring the gpu dead for a second time. A
2540 * quick check for that is good enough: schedule_work ensures the
2541 * correct ordering between hang detection and this work item, and since
2542 * the reset in-progress bit is only ever set by code outside of this
2543 * work we don't need to worry about any other races.
2545 if (i915_reset_in_progress(&dev_priv
->gpu_error
)) {
2546 DRM_DEBUG_DRIVER("resetting chip\n");
2547 kobject_uevent_env(kobj
, KOBJ_CHANGE
, reset_event
);
2550 * In most cases it's guaranteed that we get here with an RPM
2551 * reference held, for example because there is a pending GPU
2552 * request that won't finish until the reset is done. This
2553 * isn't the case at least when we get here by doing a
2554 * simulated reset via debugs, so get an RPM reference.
2556 intel_runtime_pm_get(dev_priv
);
2558 intel_prepare_reset(dev_priv
);
2561 * All state reset _must_ be completed before we update the
2562 * reset counter, for otherwise waiters might miss the reset
2563 * pending state and not properly drop locks, resulting in
2564 * deadlocks with the reset work.
2566 ret
= i915_reset(dev_priv
);
2568 intel_finish_reset(dev_priv
);
2570 intel_runtime_pm_put(dev_priv
);
2573 kobject_uevent_env(kobj
,
2574 KOBJ_CHANGE
, reset_done_event
);
2577 * Note: The wake_up also serves as a memory barrier so that
2578 * waiters see the update value of the reset counter atomic_t.
2580 i915_error_wake_up(dev_priv
, true);
2584 static void i915_report_and_clear_eir(struct drm_i915_private
*dev_priv
)
2586 uint32_t instdone
[I915_NUM_INSTDONE_REG
];
2587 u32 eir
= I915_READ(EIR
);
2593 pr_err("render error detected, EIR: 0x%08x\n", eir
);
2595 i915_get_extra_instdone(dev_priv
, instdone
);
2597 if (IS_G4X(dev_priv
)) {
2598 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
2599 u32 ipeir
= I915_READ(IPEIR_I965
);
2601 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
2602 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
2603 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
2604 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
2605 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
2606 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
2607 I915_WRITE(IPEIR_I965
, ipeir
);
2608 POSTING_READ(IPEIR_I965
);
2610 if (eir
& GM45_ERROR_PAGE_TABLE
) {
2611 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
2612 pr_err("page table error\n");
2613 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
2614 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2615 POSTING_READ(PGTBL_ER
);
2619 if (!IS_GEN2(dev_priv
)) {
2620 if (eir
& I915_ERROR_PAGE_TABLE
) {
2621 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
2622 pr_err("page table error\n");
2623 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
2624 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2625 POSTING_READ(PGTBL_ER
);
2629 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
2630 pr_err("memory refresh error:\n");
2631 for_each_pipe(dev_priv
, pipe
)
2632 pr_err("pipe %c stat: 0x%08x\n",
2633 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
2634 /* pipestat has already been acked */
2636 if (eir
& I915_ERROR_INSTRUCTION
) {
2637 pr_err("instruction error\n");
2638 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
2639 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
2640 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
2641 if (INTEL_GEN(dev_priv
) < 4) {
2642 u32 ipeir
= I915_READ(IPEIR
);
2644 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
2645 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
2646 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
2647 I915_WRITE(IPEIR
, ipeir
);
2648 POSTING_READ(IPEIR
);
2650 u32 ipeir
= I915_READ(IPEIR_I965
);
2652 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
2653 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
2654 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
2655 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
2656 I915_WRITE(IPEIR_I965
, ipeir
);
2657 POSTING_READ(IPEIR_I965
);
2661 I915_WRITE(EIR
, eir
);
2663 eir
= I915_READ(EIR
);
2666 * some errors might have become stuck,
2669 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
2670 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
2671 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2676 * i915_handle_error - handle a gpu error
2677 * @dev_priv: i915 device private
2678 * @engine_mask: mask representing engines that are hung
2679 * Do some basic checking of register state at error time and
2680 * dump it to the syslog. Also call i915_capture_error_state() to make
2681 * sure we get a record and make it available in debugfs. Fire a uevent
2682 * so userspace knows something bad happened (should trigger collection
2683 * of a ring dump etc.).
2684 * @fmt: Error message format string
2686 void i915_handle_error(struct drm_i915_private
*dev_priv
,
2688 const char *fmt
, ...)
2693 va_start(args
, fmt
);
2694 vscnprintf(error_msg
, sizeof(error_msg
), fmt
, args
);
2697 i915_capture_error_state(dev_priv
, engine_mask
, error_msg
);
2698 i915_report_and_clear_eir(dev_priv
);
2701 atomic_or(I915_RESET_IN_PROGRESS_FLAG
,
2702 &dev_priv
->gpu_error
.reset_counter
);
2705 * Wakeup waiting processes so that the reset function
2706 * i915_reset_and_wakeup doesn't deadlock trying to grab
2707 * various locks. By bumping the reset counter first, the woken
2708 * processes will see a reset in progress and back off,
2709 * releasing their locks and then wait for the reset completion.
2710 * We must do this for _all_ gpu waiters that might hold locks
2711 * that the reset work needs to acquire.
2713 * Note: The wake_up serves as the required memory barrier to
2714 * ensure that the waiters see the updated value of the reset
2717 i915_error_wake_up(dev_priv
, false);
2720 i915_reset_and_wakeup(dev_priv
);
2723 /* Called from drm generic code, passed 'crtc' which
2724 * we use as a pipe index
2726 static int i915_enable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2728 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2729 unsigned long irqflags
;
2731 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2732 if (INTEL_INFO(dev
)->gen
>= 4)
2733 i915_enable_pipestat(dev_priv
, pipe
,
2734 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2736 i915_enable_pipestat(dev_priv
, pipe
,
2737 PIPE_VBLANK_INTERRUPT_STATUS
);
2738 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2743 static int ironlake_enable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2745 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2746 unsigned long irqflags
;
2747 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
2748 DE_PIPE_VBLANK(pipe
);
2750 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2751 ilk_enable_display_irq(dev_priv
, bit
);
2752 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2757 static int valleyview_enable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2759 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2760 unsigned long irqflags
;
2762 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2763 i915_enable_pipestat(dev_priv
, pipe
,
2764 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2765 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2770 static int gen8_enable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2772 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2773 unsigned long irqflags
;
2775 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2776 bdw_enable_pipe_irq(dev_priv
, pipe
, GEN8_PIPE_VBLANK
);
2777 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2782 /* Called from drm generic code, passed 'crtc' which
2783 * we use as a pipe index
2785 static void i915_disable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2787 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2788 unsigned long irqflags
;
2790 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2791 i915_disable_pipestat(dev_priv
, pipe
,
2792 PIPE_VBLANK_INTERRUPT_STATUS
|
2793 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2794 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2797 static void ironlake_disable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2799 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2800 unsigned long irqflags
;
2801 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
2802 DE_PIPE_VBLANK(pipe
);
2804 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2805 ilk_disable_display_irq(dev_priv
, bit
);
2806 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2809 static void valleyview_disable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2811 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2812 unsigned long irqflags
;
2814 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2815 i915_disable_pipestat(dev_priv
, pipe
,
2816 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2817 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2820 static void gen8_disable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2822 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2823 unsigned long irqflags
;
2825 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2826 bdw_disable_pipe_irq(dev_priv
, pipe
, GEN8_PIPE_VBLANK
);
2827 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2831 ring_idle(struct intel_engine_cs
*engine
, u32 seqno
)
2833 return i915_seqno_passed(seqno
,
2834 READ_ONCE(engine
->last_submitted_seqno
));
2838 ipehr_is_semaphore_wait(struct drm_i915_private
*dev_priv
, u32 ipehr
)
2840 if (INTEL_GEN(dev_priv
) >= 8) {
2841 return (ipehr
>> 23) == 0x1c;
2843 ipehr
&= ~MI_SEMAPHORE_SYNC_MASK
;
2844 return ipehr
== (MI_SEMAPHORE_MBOX
| MI_SEMAPHORE_COMPARE
|
2845 MI_SEMAPHORE_REGISTER
);
2849 static struct intel_engine_cs
*
2850 semaphore_wait_to_signaller_ring(struct intel_engine_cs
*engine
, u32 ipehr
,
2853 struct drm_i915_private
*dev_priv
= engine
->i915
;
2854 struct intel_engine_cs
*signaller
;
2856 if (INTEL_GEN(dev_priv
) >= 8) {
2857 for_each_engine(signaller
, dev_priv
) {
2858 if (engine
== signaller
)
2861 if (offset
== signaller
->semaphore
.signal_ggtt
[engine
->id
])
2865 u32 sync_bits
= ipehr
& MI_SEMAPHORE_SYNC_MASK
;
2867 for_each_engine(signaller
, dev_priv
) {
2868 if(engine
== signaller
)
2871 if (sync_bits
== signaller
->semaphore
.mbox
.wait
[engine
->id
])
2876 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2877 engine
->id
, ipehr
, offset
);
2882 static struct intel_engine_cs
*
2883 semaphore_waits_for(struct intel_engine_cs
*engine
, u32
*seqno
)
2885 struct drm_i915_private
*dev_priv
= engine
->i915
;
2886 u32 cmd
, ipehr
, head
;
2891 * This function does not support execlist mode - any attempt to
2892 * proceed further into this function will result in a kernel panic
2893 * when dereferencing ring->buffer, which is not set up in execlist
2896 * The correct way of doing it would be to derive the currently
2897 * executing ring buffer from the current context, which is derived
2898 * from the currently running request. Unfortunately, to get the
2899 * current request we would have to grab the struct_mutex before doing
2900 * anything else, which would be ill-advised since some other thread
2901 * might have grabbed it already and managed to hang itself, causing
2902 * the hang checker to deadlock.
2904 * Therefore, this function does not support execlist mode in its
2905 * current form. Just return NULL and move on.
2907 if (engine
->buffer
== NULL
)
2910 ipehr
= I915_READ(RING_IPEHR(engine
->mmio_base
));
2911 if (!ipehr_is_semaphore_wait(engine
->i915
, ipehr
))
2915 * HEAD is likely pointing to the dword after the actual command,
2916 * so scan backwards until we find the MBOX. But limit it to just 3
2917 * or 4 dwords depending on the semaphore wait command size.
2918 * Note that we don't care about ACTHD here since that might
2919 * point at at batch, and semaphores are always emitted into the
2920 * ringbuffer itself.
2922 head
= I915_READ_HEAD(engine
) & HEAD_ADDR
;
2923 backwards
= (INTEL_GEN(dev_priv
) >= 8) ? 5 : 4;
2925 for (i
= backwards
; i
; --i
) {
2927 * Be paranoid and presume the hw has gone off into the wild -
2928 * our ring is smaller than what the hardware (and hence
2929 * HEAD_ADDR) allows. Also handles wrap-around.
2931 head
&= engine
->buffer
->size
- 1;
2933 /* This here seems to blow up */
2934 cmd
= ioread32(engine
->buffer
->virtual_start
+ head
);
2944 *seqno
= ioread32(engine
->buffer
->virtual_start
+ head
+ 4) + 1;
2945 if (INTEL_GEN(dev_priv
) >= 8) {
2946 offset
= ioread32(engine
->buffer
->virtual_start
+ head
+ 12);
2948 offset
= ioread32(engine
->buffer
->virtual_start
+ head
+ 8);
2950 return semaphore_wait_to_signaller_ring(engine
, ipehr
, offset
);
2953 static int semaphore_passed(struct intel_engine_cs
*engine
)
2955 struct drm_i915_private
*dev_priv
= engine
->i915
;
2956 struct intel_engine_cs
*signaller
;
2959 engine
->hangcheck
.deadlock
++;
2961 signaller
= semaphore_waits_for(engine
, &seqno
);
2962 if (signaller
== NULL
)
2965 /* Prevent pathological recursion due to driver bugs */
2966 if (signaller
->hangcheck
.deadlock
>= I915_NUM_ENGINES
)
2969 if (i915_seqno_passed(signaller
->get_seqno(signaller
), seqno
))
2972 /* cursory check for an unkickable deadlock */
2973 if (I915_READ_CTL(signaller
) & RING_WAIT_SEMAPHORE
&&
2974 semaphore_passed(signaller
) < 0)
2980 static void semaphore_clear_deadlocks(struct drm_i915_private
*dev_priv
)
2982 struct intel_engine_cs
*engine
;
2984 for_each_engine(engine
, dev_priv
)
2985 engine
->hangcheck
.deadlock
= 0;
2988 static bool subunits_stuck(struct intel_engine_cs
*engine
)
2990 u32 instdone
[I915_NUM_INSTDONE_REG
];
2994 if (engine
->id
!= RCS
)
2997 i915_get_extra_instdone(engine
->i915
, instdone
);
2999 /* There might be unstable subunit states even when
3000 * actual head is not moving. Filter out the unstable ones by
3001 * accumulating the undone -> done transitions and only
3002 * consider those as progress.
3005 for (i
= 0; i
< I915_NUM_INSTDONE_REG
; i
++) {
3006 const u32 tmp
= instdone
[i
] | engine
->hangcheck
.instdone
[i
];
3008 if (tmp
!= engine
->hangcheck
.instdone
[i
])
3011 engine
->hangcheck
.instdone
[i
] |= tmp
;
3017 static enum intel_ring_hangcheck_action
3018 head_stuck(struct intel_engine_cs
*engine
, u64 acthd
)
3020 if (acthd
!= engine
->hangcheck
.acthd
) {
3022 /* Clear subunit states on head movement */
3023 memset(engine
->hangcheck
.instdone
, 0,
3024 sizeof(engine
->hangcheck
.instdone
));
3026 return HANGCHECK_ACTIVE
;
3029 if (!subunits_stuck(engine
))
3030 return HANGCHECK_ACTIVE
;
3032 return HANGCHECK_HUNG
;
3035 static enum intel_ring_hangcheck_action
3036 ring_stuck(struct intel_engine_cs
*engine
, u64 acthd
)
3038 struct drm_i915_private
*dev_priv
= engine
->i915
;
3039 enum intel_ring_hangcheck_action ha
;
3042 ha
= head_stuck(engine
, acthd
);
3043 if (ha
!= HANGCHECK_HUNG
)
3046 if (IS_GEN2(dev_priv
))
3047 return HANGCHECK_HUNG
;
3049 /* Is the chip hanging on a WAIT_FOR_EVENT?
3050 * If so we can simply poke the RB_WAIT bit
3051 * and break the hang. This should work on
3052 * all but the second generation chipsets.
3054 tmp
= I915_READ_CTL(engine
);
3055 if (tmp
& RING_WAIT
) {
3056 i915_handle_error(dev_priv
, 0,
3057 "Kicking stuck wait on %s",
3059 I915_WRITE_CTL(engine
, tmp
);
3060 return HANGCHECK_KICK
;
3063 if (INTEL_GEN(dev_priv
) >= 6 && tmp
& RING_WAIT_SEMAPHORE
) {
3064 switch (semaphore_passed(engine
)) {
3066 return HANGCHECK_HUNG
;
3068 i915_handle_error(dev_priv
, 0,
3069 "Kicking stuck semaphore on %s",
3071 I915_WRITE_CTL(engine
, tmp
);
3072 return HANGCHECK_KICK
;
3074 return HANGCHECK_WAIT
;
3078 return HANGCHECK_HUNG
;
3081 static unsigned kick_waiters(struct intel_engine_cs
*engine
)
3083 struct drm_i915_private
*i915
= engine
->i915
;
3084 unsigned user_interrupts
= READ_ONCE(engine
->user_interrupts
);
3086 if (engine
->hangcheck
.user_interrupts
== user_interrupts
&&
3087 !test_and_set_bit(engine
->id
, &i915
->gpu_error
.missed_irq_rings
)) {
3088 if (!(i915
->gpu_error
.test_irq_rings
& intel_engine_flag(engine
)))
3089 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
3092 DRM_INFO("Fake missed irq on %s\n",
3094 wake_up_all(&engine
->irq_queue
);
3097 return user_interrupts
;
3100 * This is called when the chip hasn't reported back with completed
3101 * batchbuffers in a long time. We keep track per ring seqno progress and
3102 * if there are no progress, hangcheck score for that ring is increased.
3103 * Further, acthd is inspected to see if the ring is stuck. On stuck case
3104 * we kick the ring. If we see no progress on three subsequent calls
3105 * we assume chip is wedged and try to fix it by resetting the chip.
3107 static void i915_hangcheck_elapsed(struct work_struct
*work
)
3109 struct drm_i915_private
*dev_priv
=
3110 container_of(work
, typeof(*dev_priv
),
3111 gpu_error
.hangcheck_work
.work
);
3112 struct intel_engine_cs
*engine
;
3113 enum intel_engine_id id
;
3114 int busy_count
= 0, rings_hung
= 0;
3115 bool stuck
[I915_NUM_ENGINES
] = { 0 };
3119 #define ACTIVE_DECAY 15
3121 if (!i915
.enable_hangcheck
)
3125 * The hangcheck work is synced during runtime suspend, we don't
3126 * require a wakeref. TODO: instead of disabling the asserts make
3127 * sure that we hold a reference when this work is running.
3129 DISABLE_RPM_WAKEREF_ASSERTS(dev_priv
);
3131 /* As enabling the GPU requires fairly extensive mmio access,
3132 * periodically arm the mmio checker to see if we are triggering
3133 * any invalid access.
3135 intel_uncore_arm_unclaimed_mmio_detection(dev_priv
);
3137 for_each_engine_id(engine
, dev_priv
, id
) {
3140 unsigned user_interrupts
;
3143 semaphore_clear_deadlocks(dev_priv
);
3145 /* We don't strictly need an irq-barrier here, as we are not
3146 * serving an interrupt request, be paranoid in case the
3147 * barrier has side-effects (such as preventing a broken
3148 * cacheline snoop) and so be sure that we can see the seqno
3149 * advance. If the seqno should stick, due to a stale
3150 * cacheline, we would erroneously declare the GPU hung.
3152 if (engine
->irq_seqno_barrier
)
3153 engine
->irq_seqno_barrier(engine
);
3155 acthd
= intel_ring_get_active_head(engine
);
3156 seqno
= engine
->get_seqno(engine
);
3158 /* Reset stuck interrupts between batch advances */
3159 user_interrupts
= 0;
3161 if (engine
->hangcheck
.seqno
== seqno
) {
3162 if (ring_idle(engine
, seqno
)) {
3163 engine
->hangcheck
.action
= HANGCHECK_IDLE
;
3164 if (waitqueue_active(&engine
->irq_queue
)) {
3165 /* Safeguard against driver failure */
3166 user_interrupts
= kick_waiters(engine
);
3167 engine
->hangcheck
.score
+= BUSY
;
3171 /* We always increment the hangcheck score
3172 * if the ring is busy and still processing
3173 * the same request, so that no single request
3174 * can run indefinitely (such as a chain of
3175 * batches). The only time we do not increment
3176 * the hangcheck score on this ring, if this
3177 * ring is in a legitimate wait for another
3178 * ring. In that case the waiting ring is a
3179 * victim and we want to be sure we catch the
3180 * right culprit. Then every time we do kick
3181 * the ring, add a small increment to the
3182 * score so that we can catch a batch that is
3183 * being repeatedly kicked and so responsible
3184 * for stalling the machine.
3186 engine
->hangcheck
.action
= ring_stuck(engine
,
3189 switch (engine
->hangcheck
.action
) {
3190 case HANGCHECK_IDLE
:
3191 case HANGCHECK_WAIT
:
3193 case HANGCHECK_ACTIVE
:
3194 engine
->hangcheck
.score
+= BUSY
;
3196 case HANGCHECK_KICK
:
3197 engine
->hangcheck
.score
+= KICK
;
3199 case HANGCHECK_HUNG
:
3200 engine
->hangcheck
.score
+= HUNG
;
3206 engine
->hangcheck
.action
= HANGCHECK_ACTIVE
;
3208 /* Gradually reduce the count so that we catch DoS
3209 * attempts across multiple batches.
3211 if (engine
->hangcheck
.score
> 0)
3212 engine
->hangcheck
.score
-= ACTIVE_DECAY
;
3213 if (engine
->hangcheck
.score
< 0)
3214 engine
->hangcheck
.score
= 0;
3216 /* Clear head and subunit states on seqno movement */
3219 memset(engine
->hangcheck
.instdone
, 0,
3220 sizeof(engine
->hangcheck
.instdone
));
3223 engine
->hangcheck
.seqno
= seqno
;
3224 engine
->hangcheck
.acthd
= acthd
;
3225 engine
->hangcheck
.user_interrupts
= user_interrupts
;
3229 for_each_engine_id(engine
, dev_priv
, id
) {
3230 if (engine
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
) {
3231 DRM_INFO("%s on %s\n",
3232 stuck
[id
] ? "stuck" : "no progress",
3234 rings_hung
|= intel_engine_flag(engine
);
3239 i915_handle_error(dev_priv
, rings_hung
, "Engine(s) hung");
3244 /* Reset timer case chip hangs without another request
3246 i915_queue_hangcheck(dev_priv
);
3249 ENABLE_RPM_WAKEREF_ASSERTS(dev_priv
);
3252 void i915_queue_hangcheck(struct drm_i915_private
*dev_priv
)
3254 struct i915_gpu_error
*e
= &dev_priv
->gpu_error
;
3256 if (!i915
.enable_hangcheck
)
3259 /* Don't continually defer the hangcheck so that it is always run at
3260 * least once after work has been scheduled on any ring. Otherwise,
3261 * we will ignore a hung ring if a second ring is kept busy.
3264 queue_delayed_work(e
->hangcheck_wq
, &e
->hangcheck_work
,
3265 round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES
));
3268 static void ibx_irq_reset(struct drm_device
*dev
)
3270 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3272 if (HAS_PCH_NOP(dev
))
3275 GEN5_IRQ_RESET(SDE
);
3277 if (HAS_PCH_CPT(dev
) || HAS_PCH_LPT(dev
))
3278 I915_WRITE(SERR_INT
, 0xffffffff);
3282 * SDEIER is also touched by the interrupt handler to work around missed PCH
3283 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3284 * instead we unconditionally enable all PCH interrupt sources here, but then
3285 * only unmask them as needed with SDEIMR.
3287 * This function needs to be called before interrupts are enabled.
3289 static void ibx_irq_pre_postinstall(struct drm_device
*dev
)
3291 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3293 if (HAS_PCH_NOP(dev
))
3296 WARN_ON(I915_READ(SDEIER
) != 0);
3297 I915_WRITE(SDEIER
, 0xffffffff);
3298 POSTING_READ(SDEIER
);
3301 static void gen5_gt_irq_reset(struct drm_device
*dev
)
3303 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3306 if (INTEL_INFO(dev
)->gen
>= 6)
3307 GEN5_IRQ_RESET(GEN6_PM
);
3310 static void vlv_display_irq_reset(struct drm_i915_private
*dev_priv
)
3314 if (IS_CHERRYVIEW(dev_priv
))
3315 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK_CHV
);
3317 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
3319 i915_hotplug_interrupt_update_locked(dev_priv
, 0xffffffff, 0);
3320 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3322 for_each_pipe(dev_priv
, pipe
) {
3323 I915_WRITE(PIPESTAT(pipe
),
3324 PIPE_FIFO_UNDERRUN_STATUS
|
3325 PIPESTAT_INT_STATUS_MASK
);
3326 dev_priv
->pipestat_irq_mask
[pipe
] = 0;
3329 GEN5_IRQ_RESET(VLV_
);
3330 dev_priv
->irq_mask
= ~0;
3333 static void vlv_display_irq_postinstall(struct drm_i915_private
*dev_priv
)
3339 pipestat_mask
= PLANE_FLIP_DONE_INT_STATUS_VLV
|
3340 PIPE_CRC_DONE_INTERRUPT_STATUS
;
3342 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
3343 for_each_pipe(dev_priv
, pipe
)
3344 i915_enable_pipestat(dev_priv
, pipe
, pipestat_mask
);
3346 enable_mask
= I915_DISPLAY_PORT_INTERRUPT
|
3347 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3348 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
3349 if (IS_CHERRYVIEW(dev_priv
))
3350 enable_mask
|= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
;
3352 WARN_ON(dev_priv
->irq_mask
!= ~0);
3354 dev_priv
->irq_mask
= ~enable_mask
;
3356 GEN5_IRQ_INIT(VLV_
, dev_priv
->irq_mask
, enable_mask
);
3361 static void ironlake_irq_reset(struct drm_device
*dev
)
3363 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3365 I915_WRITE(HWSTAM
, 0xffffffff);
3369 I915_WRITE(GEN7_ERR_INT
, 0xffffffff);
3371 gen5_gt_irq_reset(dev
);
3376 static void valleyview_irq_preinstall(struct drm_device
*dev
)
3378 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3380 I915_WRITE(VLV_MASTER_IER
, 0);
3381 POSTING_READ(VLV_MASTER_IER
);
3383 gen5_gt_irq_reset(dev
);
3385 spin_lock_irq(&dev_priv
->irq_lock
);
3386 if (dev_priv
->display_irqs_enabled
)
3387 vlv_display_irq_reset(dev_priv
);
3388 spin_unlock_irq(&dev_priv
->irq_lock
);
3391 static void gen8_gt_irq_reset(struct drm_i915_private
*dev_priv
)
3393 GEN8_IRQ_RESET_NDX(GT
, 0);
3394 GEN8_IRQ_RESET_NDX(GT
, 1);
3395 GEN8_IRQ_RESET_NDX(GT
, 2);
3396 GEN8_IRQ_RESET_NDX(GT
, 3);
3399 static void gen8_irq_reset(struct drm_device
*dev
)
3401 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3404 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3405 POSTING_READ(GEN8_MASTER_IRQ
);
3407 gen8_gt_irq_reset(dev_priv
);
3409 for_each_pipe(dev_priv
, pipe
)
3410 if (intel_display_power_is_enabled(dev_priv
,
3411 POWER_DOMAIN_PIPE(pipe
)))
3412 GEN8_IRQ_RESET_NDX(DE_PIPE
, pipe
);
3414 GEN5_IRQ_RESET(GEN8_DE_PORT_
);
3415 GEN5_IRQ_RESET(GEN8_DE_MISC_
);
3416 GEN5_IRQ_RESET(GEN8_PCU_
);
3418 if (HAS_PCH_SPLIT(dev
))
3422 void gen8_irq_power_well_post_enable(struct drm_i915_private
*dev_priv
,
3423 unsigned int pipe_mask
)
3425 uint32_t extra_ier
= GEN8_PIPE_VBLANK
| GEN8_PIPE_FIFO_UNDERRUN
;
3428 spin_lock_irq(&dev_priv
->irq_lock
);
3429 for_each_pipe_masked(dev_priv
, pipe
, pipe_mask
)
3430 GEN8_IRQ_INIT_NDX(DE_PIPE
, pipe
,
3431 dev_priv
->de_irq_mask
[pipe
],
3432 ~dev_priv
->de_irq_mask
[pipe
] | extra_ier
);
3433 spin_unlock_irq(&dev_priv
->irq_lock
);
3436 void gen8_irq_power_well_pre_disable(struct drm_i915_private
*dev_priv
,
3437 unsigned int pipe_mask
)
3441 spin_lock_irq(&dev_priv
->irq_lock
);
3442 for_each_pipe_masked(dev_priv
, pipe
, pipe_mask
)
3443 GEN8_IRQ_RESET_NDX(DE_PIPE
, pipe
);
3444 spin_unlock_irq(&dev_priv
->irq_lock
);
3446 /* make sure we're done processing display irqs */
3447 synchronize_irq(dev_priv
->dev
->irq
);
3450 static void cherryview_irq_preinstall(struct drm_device
*dev
)
3452 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3454 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3455 POSTING_READ(GEN8_MASTER_IRQ
);
3457 gen8_gt_irq_reset(dev_priv
);
3459 GEN5_IRQ_RESET(GEN8_PCU_
);
3461 spin_lock_irq(&dev_priv
->irq_lock
);
3462 if (dev_priv
->display_irqs_enabled
)
3463 vlv_display_irq_reset(dev_priv
);
3464 spin_unlock_irq(&dev_priv
->irq_lock
);
3467 static u32
intel_hpd_enabled_irqs(struct drm_i915_private
*dev_priv
,
3468 const u32 hpd
[HPD_NUM_PINS
])
3470 struct intel_encoder
*encoder
;
3471 u32 enabled_irqs
= 0;
3473 for_each_intel_encoder(dev_priv
->dev
, encoder
)
3474 if (dev_priv
->hotplug
.stats
[encoder
->hpd_pin
].state
== HPD_ENABLED
)
3475 enabled_irqs
|= hpd
[encoder
->hpd_pin
];
3477 return enabled_irqs
;
3480 static void ibx_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
3482 u32 hotplug_irqs
, hotplug
, enabled_irqs
;
3484 if (HAS_PCH_IBX(dev_priv
)) {
3485 hotplug_irqs
= SDE_HOTPLUG_MASK
;
3486 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_ibx
);
3488 hotplug_irqs
= SDE_HOTPLUG_MASK_CPT
;
3489 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_cpt
);
3492 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
3495 * Enable digital hotplug on the PCH, and configure the DP short pulse
3496 * duration to 2ms (which is the minimum in the Display Port spec).
3497 * The pulse duration bits are reserved on LPT+.
3499 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
3500 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
3501 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
3502 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
3503 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
3505 * When CPU and PCH are on the same package, port A
3506 * HPD must be enabled in both north and south.
3508 if (HAS_PCH_LPT_LP(dev_priv
))
3509 hotplug
|= PORTA_HOTPLUG_ENABLE
;
3510 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
3513 static void spt_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
3515 u32 hotplug_irqs
, hotplug
, enabled_irqs
;
3517 hotplug_irqs
= SDE_HOTPLUG_MASK_SPT
;
3518 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_spt
);
3520 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
3522 /* Enable digital hotplug on the PCH */
3523 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
3524 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTC_HOTPLUG_ENABLE
|
3525 PORTB_HOTPLUG_ENABLE
| PORTA_HOTPLUG_ENABLE
;
3526 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
3528 hotplug
= I915_READ(PCH_PORT_HOTPLUG2
);
3529 hotplug
|= PORTE_HOTPLUG_ENABLE
;
3530 I915_WRITE(PCH_PORT_HOTPLUG2
, hotplug
);
3533 static void ilk_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
3535 u32 hotplug_irqs
, hotplug
, enabled_irqs
;
3537 if (INTEL_GEN(dev_priv
) >= 8) {
3538 hotplug_irqs
= GEN8_PORT_DP_A_HOTPLUG
;
3539 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_bdw
);
3541 bdw_update_port_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3542 } else if (INTEL_GEN(dev_priv
) >= 7) {
3543 hotplug_irqs
= DE_DP_A_HOTPLUG_IVB
;
3544 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_ivb
);
3546 ilk_update_display_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3548 hotplug_irqs
= DE_DP_A_HOTPLUG
;
3549 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_ilk
);
3551 ilk_update_display_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3555 * Enable digital hotplug on the CPU, and configure the DP short pulse
3556 * duration to 2ms (which is the minimum in the Display Port spec)
3557 * The pulse duration bits are reserved on HSW+.
3559 hotplug
= I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL
);
3560 hotplug
&= ~DIGITAL_PORTA_PULSE_DURATION_MASK
;
3561 hotplug
|= DIGITAL_PORTA_HOTPLUG_ENABLE
| DIGITAL_PORTA_PULSE_DURATION_2ms
;
3562 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL
, hotplug
);
3564 ibx_hpd_irq_setup(dev_priv
);
3567 static void bxt_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
3569 u32 hotplug_irqs
, hotplug
, enabled_irqs
;
3571 enabled_irqs
= intel_hpd_enabled_irqs(dev_priv
, hpd_bxt
);
3572 hotplug_irqs
= BXT_DE_PORT_HOTPLUG_MASK
;
3574 bdw_update_port_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3576 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
3577 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTB_HOTPLUG_ENABLE
|
3578 PORTA_HOTPLUG_ENABLE
;
3580 DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
3581 hotplug
, enabled_irqs
);
3582 hotplug
&= ~BXT_DDI_HPD_INVERT_MASK
;
3585 * For BXT invert bit has to be set based on AOB design
3586 * for HPD detection logic, update it based on VBT fields.
3589 if ((enabled_irqs
& BXT_DE_PORT_HP_DDIA
) &&
3590 intel_bios_is_port_hpd_inverted(dev_priv
, PORT_A
))
3591 hotplug
|= BXT_DDIA_HPD_INVERT
;
3592 if ((enabled_irqs
& BXT_DE_PORT_HP_DDIB
) &&
3593 intel_bios_is_port_hpd_inverted(dev_priv
, PORT_B
))
3594 hotplug
|= BXT_DDIB_HPD_INVERT
;
3595 if ((enabled_irqs
& BXT_DE_PORT_HP_DDIC
) &&
3596 intel_bios_is_port_hpd_inverted(dev_priv
, PORT_C
))
3597 hotplug
|= BXT_DDIC_HPD_INVERT
;
3599 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
3602 static void ibx_irq_postinstall(struct drm_device
*dev
)
3604 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3607 if (HAS_PCH_NOP(dev
))
3610 if (HAS_PCH_IBX(dev
))
3611 mask
= SDE_GMBUS
| SDE_AUX_MASK
| SDE_POISON
;
3613 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
;
3615 gen5_assert_iir_is_zero(dev_priv
, SDEIIR
);
3616 I915_WRITE(SDEIMR
, ~mask
);
3619 static void gen5_gt_irq_postinstall(struct drm_device
*dev
)
3621 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3622 u32 pm_irqs
, gt_irqs
;
3624 pm_irqs
= gt_irqs
= 0;
3626 dev_priv
->gt_irq_mask
= ~0;
3627 if (HAS_L3_DPF(dev
)) {
3628 /* L3 parity interrupt is always unmasked. */
3629 dev_priv
->gt_irq_mask
= ~GT_PARITY_ERROR(dev
);
3630 gt_irqs
|= GT_PARITY_ERROR(dev
);
3633 gt_irqs
|= GT_RENDER_USER_INTERRUPT
;
3635 gt_irqs
|= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
|
3636 ILK_BSD_USER_INTERRUPT
;
3638 gt_irqs
|= GT_BLT_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
;
3641 GEN5_IRQ_INIT(GT
, dev_priv
->gt_irq_mask
, gt_irqs
);
3643 if (INTEL_INFO(dev
)->gen
>= 6) {
3645 * RPS interrupts will get enabled/disabled on demand when RPS
3646 * itself is enabled/disabled.
3649 pm_irqs
|= PM_VEBOX_USER_INTERRUPT
;
3651 dev_priv
->pm_irq_mask
= 0xffffffff;
3652 GEN5_IRQ_INIT(GEN6_PM
, dev_priv
->pm_irq_mask
, pm_irqs
);
3656 static int ironlake_irq_postinstall(struct drm_device
*dev
)
3658 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3659 u32 display_mask
, extra_mask
;
3661 if (INTEL_INFO(dev
)->gen
>= 7) {
3662 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
|
3663 DE_PCH_EVENT_IVB
| DE_PLANEC_FLIP_DONE_IVB
|
3664 DE_PLANEB_FLIP_DONE_IVB
|
3665 DE_PLANEA_FLIP_DONE_IVB
| DE_AUX_CHANNEL_A_IVB
);
3666 extra_mask
= (DE_PIPEC_VBLANK_IVB
| DE_PIPEB_VBLANK_IVB
|
3667 DE_PIPEA_VBLANK_IVB
| DE_ERR_INT_IVB
|
3668 DE_DP_A_HOTPLUG_IVB
);
3670 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
3671 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
|
3673 DE_PIPEB_CRC_DONE
| DE_PIPEA_CRC_DONE
|
3675 extra_mask
= (DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
| DE_PCU_EVENT
|
3676 DE_PIPEB_FIFO_UNDERRUN
| DE_PIPEA_FIFO_UNDERRUN
|
3680 dev_priv
->irq_mask
= ~display_mask
;
3682 I915_WRITE(HWSTAM
, 0xeffe);
3684 ibx_irq_pre_postinstall(dev
);
3686 GEN5_IRQ_INIT(DE
, dev_priv
->irq_mask
, display_mask
| extra_mask
);
3688 gen5_gt_irq_postinstall(dev
);
3690 ibx_irq_postinstall(dev
);
3692 if (IS_IRONLAKE_M(dev
)) {
3693 /* Enable PCU event interrupts
3695 * spinlocking not required here for correctness since interrupt
3696 * setup is guaranteed to run in single-threaded context. But we
3697 * need it to make the assert_spin_locked happy. */
3698 spin_lock_irq(&dev_priv
->irq_lock
);
3699 ilk_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
3700 spin_unlock_irq(&dev_priv
->irq_lock
);
3706 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
)
3708 assert_spin_locked(&dev_priv
->irq_lock
);
3710 if (dev_priv
->display_irqs_enabled
)
3713 dev_priv
->display_irqs_enabled
= true;
3715 if (intel_irqs_enabled(dev_priv
)) {
3716 vlv_display_irq_reset(dev_priv
);
3717 vlv_display_irq_postinstall(dev_priv
);
3721 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
)
3723 assert_spin_locked(&dev_priv
->irq_lock
);
3725 if (!dev_priv
->display_irqs_enabled
)
3728 dev_priv
->display_irqs_enabled
= false;
3730 if (intel_irqs_enabled(dev_priv
))
3731 vlv_display_irq_reset(dev_priv
);
3735 static int valleyview_irq_postinstall(struct drm_device
*dev
)
3737 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3739 gen5_gt_irq_postinstall(dev
);
3741 spin_lock_irq(&dev_priv
->irq_lock
);
3742 if (dev_priv
->display_irqs_enabled
)
3743 vlv_display_irq_postinstall(dev_priv
);
3744 spin_unlock_irq(&dev_priv
->irq_lock
);
3746 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
3747 POSTING_READ(VLV_MASTER_IER
);
3752 static void gen8_gt_irq_postinstall(struct drm_i915_private
*dev_priv
)
3754 /* These are interrupts we'll toggle with the ring mask register */
3755 uint32_t gt_interrupts
[] = {
3756 GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
3757 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
3758 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
|
3759 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
,
3760 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
|
3761 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
|
3762 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
|
3763 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
,
3765 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
|
3766 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
3769 if (HAS_L3_DPF(dev_priv
))
3770 gt_interrupts
[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
3772 dev_priv
->pm_irq_mask
= 0xffffffff;
3773 GEN8_IRQ_INIT_NDX(GT
, 0, ~gt_interrupts
[0], gt_interrupts
[0]);
3774 GEN8_IRQ_INIT_NDX(GT
, 1, ~gt_interrupts
[1], gt_interrupts
[1]);
3776 * RPS interrupts will get enabled/disabled on demand when RPS itself
3777 * is enabled/disabled.
3779 GEN8_IRQ_INIT_NDX(GT
, 2, dev_priv
->pm_irq_mask
, 0);
3780 GEN8_IRQ_INIT_NDX(GT
, 3, ~gt_interrupts
[3], gt_interrupts
[3]);
3783 static void gen8_de_irq_postinstall(struct drm_i915_private
*dev_priv
)
3785 uint32_t de_pipe_masked
= GEN8_PIPE_CDCLK_CRC_DONE
;
3786 uint32_t de_pipe_enables
;
3787 u32 de_port_masked
= GEN8_AUX_CHANNEL_A
;
3788 u32 de_port_enables
;
3789 u32 de_misc_masked
= GEN8_DE_MISC_GSE
;
3792 if (INTEL_INFO(dev_priv
)->gen
>= 9) {
3793 de_pipe_masked
|= GEN9_PIPE_PLANE1_FLIP_DONE
|
3794 GEN9_DE_PIPE_IRQ_FAULT_ERRORS
;
3795 de_port_masked
|= GEN9_AUX_CHANNEL_B
| GEN9_AUX_CHANNEL_C
|
3797 if (IS_BROXTON(dev_priv
))
3798 de_port_masked
|= BXT_DE_PORT_GMBUS
;
3800 de_pipe_masked
|= GEN8_PIPE_PRIMARY_FLIP_DONE
|
3801 GEN8_DE_PIPE_IRQ_FAULT_ERRORS
;
3804 de_pipe_enables
= de_pipe_masked
| GEN8_PIPE_VBLANK
|
3805 GEN8_PIPE_FIFO_UNDERRUN
;
3807 de_port_enables
= de_port_masked
;
3808 if (IS_BROXTON(dev_priv
))
3809 de_port_enables
|= BXT_DE_PORT_HOTPLUG_MASK
;
3810 else if (IS_BROADWELL(dev_priv
))
3811 de_port_enables
|= GEN8_PORT_DP_A_HOTPLUG
;
3813 dev_priv
->de_irq_mask
[PIPE_A
] = ~de_pipe_masked
;
3814 dev_priv
->de_irq_mask
[PIPE_B
] = ~de_pipe_masked
;
3815 dev_priv
->de_irq_mask
[PIPE_C
] = ~de_pipe_masked
;
3817 for_each_pipe(dev_priv
, pipe
)
3818 if (intel_display_power_is_enabled(dev_priv
,
3819 POWER_DOMAIN_PIPE(pipe
)))
3820 GEN8_IRQ_INIT_NDX(DE_PIPE
, pipe
,
3821 dev_priv
->de_irq_mask
[pipe
],
3824 GEN5_IRQ_INIT(GEN8_DE_PORT_
, ~de_port_masked
, de_port_enables
);
3825 GEN5_IRQ_INIT(GEN8_DE_MISC_
, ~de_misc_masked
, de_misc_masked
);
3828 static int gen8_irq_postinstall(struct drm_device
*dev
)
3830 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3832 if (HAS_PCH_SPLIT(dev
))
3833 ibx_irq_pre_postinstall(dev
);
3835 gen8_gt_irq_postinstall(dev_priv
);
3836 gen8_de_irq_postinstall(dev_priv
);
3838 if (HAS_PCH_SPLIT(dev
))
3839 ibx_irq_postinstall(dev
);
3841 I915_WRITE(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
3842 POSTING_READ(GEN8_MASTER_IRQ
);
3847 static int cherryview_irq_postinstall(struct drm_device
*dev
)
3849 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3851 gen8_gt_irq_postinstall(dev_priv
);
3853 spin_lock_irq(&dev_priv
->irq_lock
);
3854 if (dev_priv
->display_irqs_enabled
)
3855 vlv_display_irq_postinstall(dev_priv
);
3856 spin_unlock_irq(&dev_priv
->irq_lock
);
3858 I915_WRITE(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
3859 POSTING_READ(GEN8_MASTER_IRQ
);
3864 static void gen8_irq_uninstall(struct drm_device
*dev
)
3866 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3871 gen8_irq_reset(dev
);
3874 static void valleyview_irq_uninstall(struct drm_device
*dev
)
3876 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3881 I915_WRITE(VLV_MASTER_IER
, 0);
3882 POSTING_READ(VLV_MASTER_IER
);
3884 gen5_gt_irq_reset(dev
);
3886 I915_WRITE(HWSTAM
, 0xffffffff);
3888 spin_lock_irq(&dev_priv
->irq_lock
);
3889 if (dev_priv
->display_irqs_enabled
)
3890 vlv_display_irq_reset(dev_priv
);
3891 spin_unlock_irq(&dev_priv
->irq_lock
);
3894 static void cherryview_irq_uninstall(struct drm_device
*dev
)
3896 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3901 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3902 POSTING_READ(GEN8_MASTER_IRQ
);
3904 gen8_gt_irq_reset(dev_priv
);
3906 GEN5_IRQ_RESET(GEN8_PCU_
);
3908 spin_lock_irq(&dev_priv
->irq_lock
);
3909 if (dev_priv
->display_irqs_enabled
)
3910 vlv_display_irq_reset(dev_priv
);
3911 spin_unlock_irq(&dev_priv
->irq_lock
);
3914 static void ironlake_irq_uninstall(struct drm_device
*dev
)
3916 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3921 ironlake_irq_reset(dev
);
3924 static void i8xx_irq_preinstall(struct drm_device
* dev
)
3926 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3929 for_each_pipe(dev_priv
, pipe
)
3930 I915_WRITE(PIPESTAT(pipe
), 0);
3931 I915_WRITE16(IMR
, 0xffff);
3932 I915_WRITE16(IER
, 0x0);
3933 POSTING_READ16(IER
);
3936 static int i8xx_irq_postinstall(struct drm_device
*dev
)
3938 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3941 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
3943 /* Unmask the interrupts that we always want on. */
3944 dev_priv
->irq_mask
=
3945 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3946 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3947 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3948 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
3949 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
3952 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3953 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3954 I915_USER_INTERRUPT
);
3955 POSTING_READ16(IER
);
3957 /* Interrupt setup is already guaranteed to be single-threaded, this is
3958 * just to make the assert_spin_locked check happy. */
3959 spin_lock_irq(&dev_priv
->irq_lock
);
3960 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3961 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3962 spin_unlock_irq(&dev_priv
->irq_lock
);
3968 * Returns true when a page flip has completed.
3970 static bool i8xx_handle_vblank(struct drm_i915_private
*dev_priv
,
3971 int plane
, int pipe
, u32 iir
)
3973 u16 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
3975 if (!intel_pipe_handle_vblank(dev_priv
, pipe
))
3978 if ((iir
& flip_pending
) == 0)
3979 goto check_page_flip
;
3981 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3982 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3983 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3984 * the flip is completed (no longer pending). Since this doesn't raise
3985 * an interrupt per se, we watch for the change at vblank.
3987 if (I915_READ16(ISR
) & flip_pending
)
3988 goto check_page_flip
;
3990 intel_finish_page_flip_cs(dev_priv
, pipe
);
3994 intel_check_page_flip(dev_priv
, pipe
);
3998 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
4000 struct drm_device
*dev
= arg
;
4001 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4006 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4007 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
4010 if (!intel_irqs_enabled(dev_priv
))
4013 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4014 disable_rpm_wakeref_asserts(dev_priv
);
4017 iir
= I915_READ16(IIR
);
4021 while (iir
& ~flip_mask
) {
4022 /* Can't rely on pipestat interrupt bit in iir as it might
4023 * have been cleared after the pipestat interrupt was received.
4024 * It doesn't set the bit in iir again, but it still produces
4025 * interrupts (for non-MSI).
4027 spin_lock(&dev_priv
->irq_lock
);
4028 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
4029 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir
);
4031 for_each_pipe(dev_priv
, pipe
) {
4032 i915_reg_t reg
= PIPESTAT(pipe
);
4033 pipe_stats
[pipe
] = I915_READ(reg
);
4036 * Clear the PIPE*STAT regs before the IIR
4038 if (pipe_stats
[pipe
] & 0x8000ffff)
4039 I915_WRITE(reg
, pipe_stats
[pipe
]);
4041 spin_unlock(&dev_priv
->irq_lock
);
4043 I915_WRITE16(IIR
, iir
& ~flip_mask
);
4044 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
4046 if (iir
& I915_USER_INTERRUPT
)
4047 notify_ring(&dev_priv
->engine
[RCS
]);
4049 for_each_pipe(dev_priv
, pipe
) {
4051 if (HAS_FBC(dev_priv
))
4054 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
4055 i8xx_handle_vblank(dev_priv
, plane
, pipe
, iir
))
4056 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
4058 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
4059 i9xx_pipe_crc_irq_handler(dev_priv
, pipe
);
4061 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
4062 intel_cpu_fifo_underrun_irq_handler(dev_priv
,
4071 enable_rpm_wakeref_asserts(dev_priv
);
4076 static void i8xx_irq_uninstall(struct drm_device
* dev
)
4078 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4081 for_each_pipe(dev_priv
, pipe
) {
4082 /* Clear enable bits; then clear status bits */
4083 I915_WRITE(PIPESTAT(pipe
), 0);
4084 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
4086 I915_WRITE16(IMR
, 0xffff);
4087 I915_WRITE16(IER
, 0x0);
4088 I915_WRITE16(IIR
, I915_READ16(IIR
));
4091 static void i915_irq_preinstall(struct drm_device
* dev
)
4093 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4096 if (I915_HAS_HOTPLUG(dev
)) {
4097 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4098 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4101 I915_WRITE16(HWSTAM
, 0xeffe);
4102 for_each_pipe(dev_priv
, pipe
)
4103 I915_WRITE(PIPESTAT(pipe
), 0);
4104 I915_WRITE(IMR
, 0xffffffff);
4105 I915_WRITE(IER
, 0x0);
4109 static int i915_irq_postinstall(struct drm_device
*dev
)
4111 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4114 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
4116 /* Unmask the interrupts that we always want on. */
4117 dev_priv
->irq_mask
=
4118 ~(I915_ASLE_INTERRUPT
|
4119 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
4120 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
4121 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4122 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
4125 I915_ASLE_INTERRUPT
|
4126 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
4127 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
4128 I915_USER_INTERRUPT
;
4130 if (I915_HAS_HOTPLUG(dev
)) {
4131 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4132 POSTING_READ(PORT_HOTPLUG_EN
);
4134 /* Enable in IER... */
4135 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
4136 /* and unmask in IMR */
4137 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
4140 I915_WRITE(IMR
, dev_priv
->irq_mask
);
4141 I915_WRITE(IER
, enable_mask
);
4144 i915_enable_asle_pipestat(dev_priv
);
4146 /* Interrupt setup is already guaranteed to be single-threaded, this is
4147 * just to make the assert_spin_locked check happy. */
4148 spin_lock_irq(&dev_priv
->irq_lock
);
4149 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4150 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4151 spin_unlock_irq(&dev_priv
->irq_lock
);
4157 * Returns true when a page flip has completed.
4159 static bool i915_handle_vblank(struct drm_i915_private
*dev_priv
,
4160 int plane
, int pipe
, u32 iir
)
4162 u32 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
4164 if (!intel_pipe_handle_vblank(dev_priv
, pipe
))
4167 if ((iir
& flip_pending
) == 0)
4168 goto check_page_flip
;
4170 /* We detect FlipDone by looking for the change in PendingFlip from '1'
4171 * to '0' on the following vblank, i.e. IIR has the Pendingflip
4172 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
4173 * the flip is completed (no longer pending). Since this doesn't raise
4174 * an interrupt per se, we watch for the change at vblank.
4176 if (I915_READ(ISR
) & flip_pending
)
4177 goto check_page_flip
;
4179 intel_finish_page_flip_cs(dev_priv
, pipe
);
4183 intel_check_page_flip(dev_priv
, pipe
);
4187 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
4189 struct drm_device
*dev
= arg
;
4190 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4191 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
4193 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4194 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
4195 int pipe
, ret
= IRQ_NONE
;
4197 if (!intel_irqs_enabled(dev_priv
))
4200 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4201 disable_rpm_wakeref_asserts(dev_priv
);
4203 iir
= I915_READ(IIR
);
4205 bool irq_received
= (iir
& ~flip_mask
) != 0;
4206 bool blc_event
= false;
4208 /* Can't rely on pipestat interrupt bit in iir as it might
4209 * have been cleared after the pipestat interrupt was received.
4210 * It doesn't set the bit in iir again, but it still produces
4211 * interrupts (for non-MSI).
4213 spin_lock(&dev_priv
->irq_lock
);
4214 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
4215 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir
);
4217 for_each_pipe(dev_priv
, pipe
) {
4218 i915_reg_t reg
= PIPESTAT(pipe
);
4219 pipe_stats
[pipe
] = I915_READ(reg
);
4221 /* Clear the PIPE*STAT regs before the IIR */
4222 if (pipe_stats
[pipe
] & 0x8000ffff) {
4223 I915_WRITE(reg
, pipe_stats
[pipe
]);
4224 irq_received
= true;
4227 spin_unlock(&dev_priv
->irq_lock
);
4232 /* Consume port. Then clear IIR or we'll miss events */
4233 if (I915_HAS_HOTPLUG(dev_priv
) &&
4234 iir
& I915_DISPLAY_PORT_INTERRUPT
) {
4235 u32 hotplug_status
= i9xx_hpd_irq_ack(dev_priv
);
4237 i9xx_hpd_irq_handler(dev_priv
, hotplug_status
);
4240 I915_WRITE(IIR
, iir
& ~flip_mask
);
4241 new_iir
= I915_READ(IIR
); /* Flush posted writes */
4243 if (iir
& I915_USER_INTERRUPT
)
4244 notify_ring(&dev_priv
->engine
[RCS
]);
4246 for_each_pipe(dev_priv
, pipe
) {
4248 if (HAS_FBC(dev_priv
))
4251 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
4252 i915_handle_vblank(dev_priv
, plane
, pipe
, iir
))
4253 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
4255 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
4258 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
4259 i9xx_pipe_crc_irq_handler(dev_priv
, pipe
);
4261 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
4262 intel_cpu_fifo_underrun_irq_handler(dev_priv
,
4266 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
4267 intel_opregion_asle_intr(dev_priv
);
4269 /* With MSI, interrupts are only generated when iir
4270 * transitions from zero to nonzero. If another bit got
4271 * set while we were handling the existing iir bits, then
4272 * we would never get another interrupt.
4274 * This is fine on non-MSI as well, as if we hit this path
4275 * we avoid exiting the interrupt handler only to generate
4278 * Note that for MSI this could cause a stray interrupt report
4279 * if an interrupt landed in the time between writing IIR and
4280 * the posting read. This should be rare enough to never
4281 * trigger the 99% of 100,000 interrupts test for disabling
4286 } while (iir
& ~flip_mask
);
4288 enable_rpm_wakeref_asserts(dev_priv
);
4293 static void i915_irq_uninstall(struct drm_device
* dev
)
4295 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4298 if (I915_HAS_HOTPLUG(dev
)) {
4299 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4300 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4303 I915_WRITE16(HWSTAM
, 0xffff);
4304 for_each_pipe(dev_priv
, pipe
) {
4305 /* Clear enable bits; then clear status bits */
4306 I915_WRITE(PIPESTAT(pipe
), 0);
4307 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
4309 I915_WRITE(IMR
, 0xffffffff);
4310 I915_WRITE(IER
, 0x0);
4312 I915_WRITE(IIR
, I915_READ(IIR
));
4315 static void i965_irq_preinstall(struct drm_device
* dev
)
4317 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4320 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4321 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4323 I915_WRITE(HWSTAM
, 0xeffe);
4324 for_each_pipe(dev_priv
, pipe
)
4325 I915_WRITE(PIPESTAT(pipe
), 0);
4326 I915_WRITE(IMR
, 0xffffffff);
4327 I915_WRITE(IER
, 0x0);
4331 static int i965_irq_postinstall(struct drm_device
*dev
)
4333 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4337 /* Unmask the interrupts that we always want on. */
4338 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
4339 I915_DISPLAY_PORT_INTERRUPT
|
4340 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
4341 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
4342 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4343 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
4344 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
4346 enable_mask
= ~dev_priv
->irq_mask
;
4347 enable_mask
&= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4348 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
4349 enable_mask
|= I915_USER_INTERRUPT
;
4351 if (IS_G4X(dev_priv
))
4352 enable_mask
|= I915_BSD_USER_INTERRUPT
;
4354 /* Interrupt setup is already guaranteed to be single-threaded, this is
4355 * just to make the assert_spin_locked check happy. */
4356 spin_lock_irq(&dev_priv
->irq_lock
);
4357 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
4358 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4359 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4360 spin_unlock_irq(&dev_priv
->irq_lock
);
4363 * Enable some error detection, note the instruction error mask
4364 * bit is reserved, so we leave it masked.
4366 if (IS_G4X(dev_priv
)) {
4367 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
4368 GM45_ERROR_MEM_PRIV
|
4369 GM45_ERROR_CP_PRIV
|
4370 I915_ERROR_MEMORY_REFRESH
);
4372 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
4373 I915_ERROR_MEMORY_REFRESH
);
4375 I915_WRITE(EMR
, error_mask
);
4377 I915_WRITE(IMR
, dev_priv
->irq_mask
);
4378 I915_WRITE(IER
, enable_mask
);
4381 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4382 POSTING_READ(PORT_HOTPLUG_EN
);
4384 i915_enable_asle_pipestat(dev_priv
);
4389 static void i915_hpd_irq_setup(struct drm_i915_private
*dev_priv
)
4393 assert_spin_locked(&dev_priv
->irq_lock
);
4395 /* Note HDMI and DP share hotplug bits */
4396 /* enable bits are the same for all generations */
4397 hotplug_en
= intel_hpd_enabled_irqs(dev_priv
, hpd_mask_i915
);
4398 /* Programming the CRT detection parameters tends
4399 to generate a spurious hotplug event about three
4400 seconds later. So just do it once.
4402 if (IS_G4X(dev_priv
))
4403 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
4404 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
4406 /* Ignore TV since it's buggy */
4407 i915_hotplug_interrupt_update_locked(dev_priv
,
4408 HOTPLUG_INT_EN_MASK
|
4409 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK
|
4410 CRT_HOTPLUG_ACTIVATION_PERIOD_64
,
4414 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
4416 struct drm_device
*dev
= arg
;
4417 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4419 u32 pipe_stats
[I915_MAX_PIPES
];
4420 int ret
= IRQ_NONE
, pipe
;
4422 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4423 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
4425 if (!intel_irqs_enabled(dev_priv
))
4428 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4429 disable_rpm_wakeref_asserts(dev_priv
);
4431 iir
= I915_READ(IIR
);
4434 bool irq_received
= (iir
& ~flip_mask
) != 0;
4435 bool blc_event
= false;
4437 /* Can't rely on pipestat interrupt bit in iir as it might
4438 * have been cleared after the pipestat interrupt was received.
4439 * It doesn't set the bit in iir again, but it still produces
4440 * interrupts (for non-MSI).
4442 spin_lock(&dev_priv
->irq_lock
);
4443 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
4444 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir
);
4446 for_each_pipe(dev_priv
, pipe
) {
4447 i915_reg_t reg
= PIPESTAT(pipe
);
4448 pipe_stats
[pipe
] = I915_READ(reg
);
4451 * Clear the PIPE*STAT regs before the IIR
4453 if (pipe_stats
[pipe
] & 0x8000ffff) {
4454 I915_WRITE(reg
, pipe_stats
[pipe
]);
4455 irq_received
= true;
4458 spin_unlock(&dev_priv
->irq_lock
);
4465 /* Consume port. Then clear IIR or we'll miss events */
4466 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
4467 u32 hotplug_status
= i9xx_hpd_irq_ack(dev_priv
);
4469 i9xx_hpd_irq_handler(dev_priv
, hotplug_status
);
4472 I915_WRITE(IIR
, iir
& ~flip_mask
);
4473 new_iir
= I915_READ(IIR
); /* Flush posted writes */
4475 if (iir
& I915_USER_INTERRUPT
)
4476 notify_ring(&dev_priv
->engine
[RCS
]);
4477 if (iir
& I915_BSD_USER_INTERRUPT
)
4478 notify_ring(&dev_priv
->engine
[VCS
]);
4480 for_each_pipe(dev_priv
, pipe
) {
4481 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
4482 i915_handle_vblank(dev_priv
, pipe
, pipe
, iir
))
4483 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
4485 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
4488 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
4489 i9xx_pipe_crc_irq_handler(dev_priv
, pipe
);
4491 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
4492 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
4495 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
4496 intel_opregion_asle_intr(dev_priv
);
4498 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
4499 gmbus_irq_handler(dev_priv
);
4501 /* With MSI, interrupts are only generated when iir
4502 * transitions from zero to nonzero. If another bit got
4503 * set while we were handling the existing iir bits, then
4504 * we would never get another interrupt.
4506 * This is fine on non-MSI as well, as if we hit this path
4507 * we avoid exiting the interrupt handler only to generate
4510 * Note that for MSI this could cause a stray interrupt report
4511 * if an interrupt landed in the time between writing IIR and
4512 * the posting read. This should be rare enough to never
4513 * trigger the 99% of 100,000 interrupts test for disabling
4519 enable_rpm_wakeref_asserts(dev_priv
);
4524 static void i965_irq_uninstall(struct drm_device
* dev
)
4526 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4532 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4533 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4535 I915_WRITE(HWSTAM
, 0xffffffff);
4536 for_each_pipe(dev_priv
, pipe
)
4537 I915_WRITE(PIPESTAT(pipe
), 0);
4538 I915_WRITE(IMR
, 0xffffffff);
4539 I915_WRITE(IER
, 0x0);
4541 for_each_pipe(dev_priv
, pipe
)
4542 I915_WRITE(PIPESTAT(pipe
),
4543 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
4544 I915_WRITE(IIR
, I915_READ(IIR
));
4548 * intel_irq_init - initializes irq support
4549 * @dev_priv: i915 device instance
4551 * This function initializes all the irq support including work items, timers
4552 * and all the vtables. It does not setup the interrupt itself though.
4554 void intel_irq_init(struct drm_i915_private
*dev_priv
)
4556 struct drm_device
*dev
= dev_priv
->dev
;
4558 intel_hpd_init_work(dev_priv
);
4560 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
4561 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
4563 /* Let's track the enabled rps events */
4564 if (IS_VALLEYVIEW(dev_priv
))
4565 /* WaGsvRC0ResidencyMethod:vlv */
4566 dev_priv
->pm_rps_events
= GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_UP_EI_EXPIRED
;
4568 dev_priv
->pm_rps_events
= GEN6_PM_RPS_EVENTS
;
4570 dev_priv
->rps
.pm_intr_keep
= 0;
4573 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
4574 * if GEN6_PM_UP_EI_EXPIRED is masked.
4576 * TODO: verify if this can be reproduced on VLV,CHV.
4578 if (INTEL_INFO(dev_priv
)->gen
<= 7 && !IS_HASWELL(dev_priv
))
4579 dev_priv
->rps
.pm_intr_keep
|= GEN6_PM_RP_UP_EI_EXPIRED
;
4581 if (INTEL_INFO(dev_priv
)->gen
>= 8)
4582 dev_priv
->rps
.pm_intr_keep
|= GEN8_PMINTR_REDIRECT_TO_NON_DISP
;
4584 INIT_DELAYED_WORK(&dev_priv
->gpu_error
.hangcheck_work
,
4585 i915_hangcheck_elapsed
);
4587 if (IS_GEN2(dev_priv
)) {
4588 dev
->max_vblank_count
= 0;
4589 dev
->driver
->get_vblank_counter
= i8xx_get_vblank_counter
;
4590 } else if (IS_G4X(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 5) {
4591 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
4592 dev
->driver
->get_vblank_counter
= g4x_get_vblank_counter
;
4594 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
4595 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
4599 * Opt out of the vblank disable timer on everything except gen2.
4600 * Gen2 doesn't have a hardware frame counter and so depends on
4601 * vblank interrupts to produce sane vblank seuquence numbers.
4603 if (!IS_GEN2(dev_priv
))
4604 dev
->vblank_disable_immediate
= true;
4606 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
4607 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
4609 if (IS_CHERRYVIEW(dev_priv
)) {
4610 dev
->driver
->irq_handler
= cherryview_irq_handler
;
4611 dev
->driver
->irq_preinstall
= cherryview_irq_preinstall
;
4612 dev
->driver
->irq_postinstall
= cherryview_irq_postinstall
;
4613 dev
->driver
->irq_uninstall
= cherryview_irq_uninstall
;
4614 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
4615 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
4616 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4617 } else if (IS_VALLEYVIEW(dev_priv
)) {
4618 dev
->driver
->irq_handler
= valleyview_irq_handler
;
4619 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
4620 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
4621 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
4622 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
4623 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
4624 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4625 } else if (INTEL_INFO(dev_priv
)->gen
>= 8) {
4626 dev
->driver
->irq_handler
= gen8_irq_handler
;
4627 dev
->driver
->irq_preinstall
= gen8_irq_reset
;
4628 dev
->driver
->irq_postinstall
= gen8_irq_postinstall
;
4629 dev
->driver
->irq_uninstall
= gen8_irq_uninstall
;
4630 dev
->driver
->enable_vblank
= gen8_enable_vblank
;
4631 dev
->driver
->disable_vblank
= gen8_disable_vblank
;
4632 if (IS_BROXTON(dev
))
4633 dev_priv
->display
.hpd_irq_setup
= bxt_hpd_irq_setup
;
4634 else if (HAS_PCH_SPT(dev
))
4635 dev_priv
->display
.hpd_irq_setup
= spt_hpd_irq_setup
;
4637 dev_priv
->display
.hpd_irq_setup
= ilk_hpd_irq_setup
;
4638 } else if (HAS_PCH_SPLIT(dev
)) {
4639 dev
->driver
->irq_handler
= ironlake_irq_handler
;
4640 dev
->driver
->irq_preinstall
= ironlake_irq_reset
;
4641 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
4642 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
4643 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
4644 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
4645 dev_priv
->display
.hpd_irq_setup
= ilk_hpd_irq_setup
;
4647 if (IS_GEN2(dev_priv
)) {
4648 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
4649 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
4650 dev
->driver
->irq_handler
= i8xx_irq_handler
;
4651 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
4652 } else if (IS_GEN3(dev_priv
)) {
4653 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
4654 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
4655 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
4656 dev
->driver
->irq_handler
= i915_irq_handler
;
4658 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
4659 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
4660 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
4661 dev
->driver
->irq_handler
= i965_irq_handler
;
4663 if (I915_HAS_HOTPLUG(dev_priv
))
4664 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4665 dev
->driver
->enable_vblank
= i915_enable_vblank
;
4666 dev
->driver
->disable_vblank
= i915_disable_vblank
;
4671 * intel_irq_install - enables the hardware interrupt
4672 * @dev_priv: i915 device instance
4674 * This function enables the hardware interrupt handling, but leaves the hotplug
4675 * handling still disabled. It is called after intel_irq_init().
4677 * In the driver load and resume code we need working interrupts in a few places
4678 * but don't want to deal with the hassle of concurrent probe and hotplug
4679 * workers. Hence the split into this two-stage approach.
4681 int intel_irq_install(struct drm_i915_private
*dev_priv
)
4684 * We enable some interrupt sources in our postinstall hooks, so mark
4685 * interrupts as enabled _before_ actually enabling them to avoid
4686 * special cases in our ordering checks.
4688 dev_priv
->pm
.irqs_enabled
= true;
4690 return drm_irq_install(dev_priv
->dev
, dev_priv
->dev
->pdev
->irq
);
4694 * intel_irq_uninstall - finilizes all irq handling
4695 * @dev_priv: i915 device instance
4697 * This stops interrupt and hotplug handling and unregisters and frees all
4698 * resources acquired in the init functions.
4700 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
)
4702 drm_irq_uninstall(dev_priv
->dev
);
4703 intel_hpd_cancel_work(dev_priv
);
4704 dev_priv
->pm
.irqs_enabled
= false;
4708 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4709 * @dev_priv: i915 device instance
4711 * This function is used to disable interrupts at runtime, both in the runtime
4712 * pm and the system suspend/resume code.
4714 void intel_runtime_pm_disable_interrupts(struct drm_i915_private
*dev_priv
)
4716 dev_priv
->dev
->driver
->irq_uninstall(dev_priv
->dev
);
4717 dev_priv
->pm
.irqs_enabled
= false;
4718 synchronize_irq(dev_priv
->dev
->irq
);
4722 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4723 * @dev_priv: i915 device instance
4725 * This function is used to enable interrupts at runtime, both in the runtime
4726 * pm and the system suspend/resume code.
4728 void intel_runtime_pm_enable_interrupts(struct drm_i915_private
*dev_priv
)
4730 dev_priv
->pm
.irqs_enabled
= true;
4731 dev_priv
->dev
->driver
->irq_preinstall(dev_priv
->dev
);
4732 dev_priv
->dev
->driver
->irq_postinstall(dev_priv
->dev
);