1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
35 #include <drm/i915_drm.h>
37 #include "i915_trace.h"
38 #include "intel_drv.h"
40 static const u32 hpd_ibx
[] = {
41 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
42 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
43 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
44 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
45 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
48 static const u32 hpd_cpt
[] = {
49 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
50 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG_CPT
,
51 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
52 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
53 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
56 static const u32 hpd_mask_i915
[] = {
57 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
58 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
59 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
60 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
61 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
62 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
65 static const u32 hpd_status_g4x
[] = {
66 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
67 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
68 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
69 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
70 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
71 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
74 static const u32 hpd_status_i915
[] = { /* i915 and valleyview are the same */
75 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
76 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
77 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
78 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
79 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
80 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
83 /* IIR can theoretically queue up two events. Be paranoid. */
84 #define GEN8_IRQ_RESET_NDX(type, which) do { \
85 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
86 POSTING_READ(GEN8_##type##_IMR(which)); \
87 I915_WRITE(GEN8_##type##_IER(which), 0); \
88 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
89 POSTING_READ(GEN8_##type##_IIR(which)); \
90 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
91 POSTING_READ(GEN8_##type##_IIR(which)); \
94 #define GEN5_IRQ_RESET(type) do { \
95 I915_WRITE(type##IMR, 0xffffffff); \
96 POSTING_READ(type##IMR); \
97 I915_WRITE(type##IER, 0); \
98 I915_WRITE(type##IIR, 0xffffffff); \
99 POSTING_READ(type##IIR); \
100 I915_WRITE(type##IIR, 0xffffffff); \
101 POSTING_READ(type##IIR); \
105 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
107 #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
108 u32 val = I915_READ(reg); \
110 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
112 I915_WRITE((reg), 0xffffffff); \
114 I915_WRITE((reg), 0xffffffff); \
119 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
120 GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
121 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
122 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
123 POSTING_READ(GEN8_##type##_IER(which)); \
126 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
127 GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
128 I915_WRITE(type##IMR, (imr_val)); \
129 I915_WRITE(type##IER, (ier_val)); \
130 POSTING_READ(type##IER); \
133 /* For display hotplug interrupt */
135 ironlake_enable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
)
137 assert_spin_locked(&dev_priv
->irq_lock
);
139 if (WARN_ON(dev_priv
->pm
.irqs_disabled
))
142 if ((dev_priv
->irq_mask
& mask
) != 0) {
143 dev_priv
->irq_mask
&= ~mask
;
144 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
150 ironlake_disable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
)
152 assert_spin_locked(&dev_priv
->irq_lock
);
154 if (WARN_ON(dev_priv
->pm
.irqs_disabled
))
157 if ((dev_priv
->irq_mask
& mask
) != mask
) {
158 dev_priv
->irq_mask
|= mask
;
159 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
165 * ilk_update_gt_irq - update GTIMR
166 * @dev_priv: driver private
167 * @interrupt_mask: mask of interrupt bits to update
168 * @enabled_irq_mask: mask of interrupt bits to enable
170 static void ilk_update_gt_irq(struct drm_i915_private
*dev_priv
,
171 uint32_t interrupt_mask
,
172 uint32_t enabled_irq_mask
)
174 assert_spin_locked(&dev_priv
->irq_lock
);
176 if (WARN_ON(dev_priv
->pm
.irqs_disabled
))
179 dev_priv
->gt_irq_mask
&= ~interrupt_mask
;
180 dev_priv
->gt_irq_mask
|= (~enabled_irq_mask
& interrupt_mask
);
181 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
185 void ilk_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
187 ilk_update_gt_irq(dev_priv
, mask
, mask
);
190 void ilk_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
192 ilk_update_gt_irq(dev_priv
, mask
, 0);
196 * snb_update_pm_irq - update GEN6_PMIMR
197 * @dev_priv: driver private
198 * @interrupt_mask: mask of interrupt bits to update
199 * @enabled_irq_mask: mask of interrupt bits to enable
201 static void snb_update_pm_irq(struct drm_i915_private
*dev_priv
,
202 uint32_t interrupt_mask
,
203 uint32_t enabled_irq_mask
)
207 assert_spin_locked(&dev_priv
->irq_lock
);
209 if (WARN_ON(dev_priv
->pm
.irqs_disabled
))
212 new_val
= dev_priv
->pm_irq_mask
;
213 new_val
&= ~interrupt_mask
;
214 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
216 if (new_val
!= dev_priv
->pm_irq_mask
) {
217 dev_priv
->pm_irq_mask
= new_val
;
218 I915_WRITE(GEN6_PMIMR
, dev_priv
->pm_irq_mask
);
219 POSTING_READ(GEN6_PMIMR
);
223 void snb_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
225 snb_update_pm_irq(dev_priv
, mask
, mask
);
228 void snb_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
230 snb_update_pm_irq(dev_priv
, mask
, 0);
233 static bool ivb_can_enable_err_int(struct drm_device
*dev
)
235 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
236 struct intel_crtc
*crtc
;
239 assert_spin_locked(&dev_priv
->irq_lock
);
241 for_each_pipe(pipe
) {
242 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
244 if (crtc
->cpu_fifo_underrun_disabled
)
252 * bdw_update_pm_irq - update GT interrupt 2
253 * @dev_priv: driver private
254 * @interrupt_mask: mask of interrupt bits to update
255 * @enabled_irq_mask: mask of interrupt bits to enable
257 * Copied from the snb function, updated with relevant register offsets
259 static void bdw_update_pm_irq(struct drm_i915_private
*dev_priv
,
260 uint32_t interrupt_mask
,
261 uint32_t enabled_irq_mask
)
265 assert_spin_locked(&dev_priv
->irq_lock
);
267 if (WARN_ON(dev_priv
->pm
.irqs_disabled
))
270 new_val
= dev_priv
->pm_irq_mask
;
271 new_val
&= ~interrupt_mask
;
272 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
274 if (new_val
!= dev_priv
->pm_irq_mask
) {
275 dev_priv
->pm_irq_mask
= new_val
;
276 I915_WRITE(GEN8_GT_IMR(2), dev_priv
->pm_irq_mask
);
277 POSTING_READ(GEN8_GT_IMR(2));
281 void bdw_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
283 bdw_update_pm_irq(dev_priv
, mask
, mask
);
286 void bdw_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
288 bdw_update_pm_irq(dev_priv
, mask
, 0);
291 static bool cpt_can_enable_serr_int(struct drm_device
*dev
)
293 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
295 struct intel_crtc
*crtc
;
297 assert_spin_locked(&dev_priv
->irq_lock
);
299 for_each_pipe(pipe
) {
300 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
302 if (crtc
->pch_fifo_underrun_disabled
)
309 static void i9xx_clear_fifo_underrun(struct drm_device
*dev
, enum pipe pipe
)
311 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
312 u32 reg
= PIPESTAT(pipe
);
313 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
315 assert_spin_locked(&dev_priv
->irq_lock
);
317 I915_WRITE(reg
, pipestat
| PIPE_FIFO_UNDERRUN_STATUS
);
321 static void ironlake_set_fifo_underrun_reporting(struct drm_device
*dev
,
322 enum pipe pipe
, bool enable
)
324 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
325 uint32_t bit
= (pipe
== PIPE_A
) ? DE_PIPEA_FIFO_UNDERRUN
:
326 DE_PIPEB_FIFO_UNDERRUN
;
329 ironlake_enable_display_irq(dev_priv
, bit
);
331 ironlake_disable_display_irq(dev_priv
, bit
);
334 static void ivybridge_set_fifo_underrun_reporting(struct drm_device
*dev
,
335 enum pipe pipe
, bool enable
)
337 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
339 I915_WRITE(GEN7_ERR_INT
, ERR_INT_FIFO_UNDERRUN(pipe
));
341 if (!ivb_can_enable_err_int(dev
))
344 ironlake_enable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
346 bool was_enabled
= !(I915_READ(DEIMR
) & DE_ERR_INT_IVB
);
348 /* Change the state _after_ we've read out the current one. */
349 ironlake_disable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
352 (I915_READ(GEN7_ERR_INT
) & ERR_INT_FIFO_UNDERRUN(pipe
))) {
353 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
359 static void broadwell_set_fifo_underrun_reporting(struct drm_device
*dev
,
360 enum pipe pipe
, bool enable
)
362 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
364 assert_spin_locked(&dev_priv
->irq_lock
);
367 dev_priv
->de_irq_mask
[pipe
] &= ~GEN8_PIPE_FIFO_UNDERRUN
;
369 dev_priv
->de_irq_mask
[pipe
] |= GEN8_PIPE_FIFO_UNDERRUN
;
370 I915_WRITE(GEN8_DE_PIPE_IMR(pipe
), dev_priv
->de_irq_mask
[pipe
]);
371 POSTING_READ(GEN8_DE_PIPE_IMR(pipe
));
375 * ibx_display_interrupt_update - update SDEIMR
376 * @dev_priv: driver private
377 * @interrupt_mask: mask of interrupt bits to update
378 * @enabled_irq_mask: mask of interrupt bits to enable
380 static void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
381 uint32_t interrupt_mask
,
382 uint32_t enabled_irq_mask
)
384 uint32_t sdeimr
= I915_READ(SDEIMR
);
385 sdeimr
&= ~interrupt_mask
;
386 sdeimr
|= (~enabled_irq_mask
& interrupt_mask
);
388 assert_spin_locked(&dev_priv
->irq_lock
);
390 if (WARN_ON(dev_priv
->pm
.irqs_disabled
))
393 I915_WRITE(SDEIMR
, sdeimr
);
394 POSTING_READ(SDEIMR
);
396 #define ibx_enable_display_interrupt(dev_priv, bits) \
397 ibx_display_interrupt_update((dev_priv), (bits), (bits))
398 #define ibx_disable_display_interrupt(dev_priv, bits) \
399 ibx_display_interrupt_update((dev_priv), (bits), 0)
401 static void ibx_set_fifo_underrun_reporting(struct drm_device
*dev
,
402 enum transcoder pch_transcoder
,
405 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
406 uint32_t bit
= (pch_transcoder
== TRANSCODER_A
) ?
407 SDE_TRANSA_FIFO_UNDER
: SDE_TRANSB_FIFO_UNDER
;
410 ibx_enable_display_interrupt(dev_priv
, bit
);
412 ibx_disable_display_interrupt(dev_priv
, bit
);
415 static void cpt_set_fifo_underrun_reporting(struct drm_device
*dev
,
416 enum transcoder pch_transcoder
,
419 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
423 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
));
425 if (!cpt_can_enable_serr_int(dev
))
428 ibx_enable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
430 uint32_t tmp
= I915_READ(SERR_INT
);
431 bool was_enabled
= !(I915_READ(SDEIMR
) & SDE_ERROR_CPT
);
433 /* Change the state _after_ we've read out the current one. */
434 ibx_disable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
437 (tmp
& SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
))) {
438 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
439 transcoder_name(pch_transcoder
));
445 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
448 * @enable: true if we want to report FIFO underrun errors, false otherwise
450 * This function makes us disable or enable CPU fifo underruns for a specific
451 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
452 * reporting for one pipe may also disable all the other CPU error interruts for
453 * the other pipes, due to the fact that there's just one interrupt mask/enable
454 * bit for all the pipes.
456 * Returns the previous state of underrun reporting.
458 bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device
*dev
,
459 enum pipe pipe
, bool enable
)
461 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
462 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
463 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
466 assert_spin_locked(&dev_priv
->irq_lock
);
468 ret
= !intel_crtc
->cpu_fifo_underrun_disabled
;
473 intel_crtc
->cpu_fifo_underrun_disabled
= !enable
;
475 if (enable
&& (INTEL_INFO(dev
)->gen
< 5 || IS_VALLEYVIEW(dev
)))
476 i9xx_clear_fifo_underrun(dev
, pipe
);
477 else if (IS_GEN5(dev
) || IS_GEN6(dev
))
478 ironlake_set_fifo_underrun_reporting(dev
, pipe
, enable
);
479 else if (IS_GEN7(dev
))
480 ivybridge_set_fifo_underrun_reporting(dev
, pipe
, enable
);
481 else if (IS_GEN8(dev
))
482 broadwell_set_fifo_underrun_reporting(dev
, pipe
, enable
);
488 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device
*dev
,
489 enum pipe pipe
, bool enable
)
491 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
495 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
496 ret
= __intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, enable
);
497 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
502 static bool __cpu_fifo_underrun_reporting_enabled(struct drm_device
*dev
,
505 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
506 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
507 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
509 return !intel_crtc
->cpu_fifo_underrun_disabled
;
513 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
515 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
516 * @enable: true if we want to report FIFO underrun errors, false otherwise
518 * This function makes us disable or enable PCH fifo underruns for a specific
519 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
520 * underrun reporting for one transcoder may also disable all the other PCH
521 * error interruts for the other transcoders, due to the fact that there's just
522 * one interrupt mask/enable bit for all the transcoders.
524 * Returns the previous state of underrun reporting.
526 bool intel_set_pch_fifo_underrun_reporting(struct drm_device
*dev
,
527 enum transcoder pch_transcoder
,
530 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
531 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pch_transcoder
];
532 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
537 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
538 * has only one pch transcoder A that all pipes can use. To avoid racy
539 * pch transcoder -> pipe lookups from interrupt code simply store the
540 * underrun statistics in crtc A. Since we never expose this anywhere
541 * nor use it outside of the fifo underrun code here using the "wrong"
542 * crtc on LPT won't cause issues.
545 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
547 ret
= !intel_crtc
->pch_fifo_underrun_disabled
;
552 intel_crtc
->pch_fifo_underrun_disabled
= !enable
;
554 if (HAS_PCH_IBX(dev
))
555 ibx_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
557 cpt_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
560 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
566 __i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
567 u32 enable_mask
, u32 status_mask
)
569 u32 reg
= PIPESTAT(pipe
);
570 u32 pipestat
= I915_READ(reg
) & PIPESTAT_INT_ENABLE_MASK
;
572 assert_spin_locked(&dev_priv
->irq_lock
);
574 if (WARN_ONCE(enable_mask
& ~PIPESTAT_INT_ENABLE_MASK
||
575 status_mask
& ~PIPESTAT_INT_STATUS_MASK
,
576 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
577 pipe_name(pipe
), enable_mask
, status_mask
))
580 if ((pipestat
& enable_mask
) == enable_mask
)
583 dev_priv
->pipestat_irq_mask
[pipe
] |= status_mask
;
585 /* Enable the interrupt, clear any pending status */
586 pipestat
|= enable_mask
| status_mask
;
587 I915_WRITE(reg
, pipestat
);
592 __i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
593 u32 enable_mask
, u32 status_mask
)
595 u32 reg
= PIPESTAT(pipe
);
596 u32 pipestat
= I915_READ(reg
) & PIPESTAT_INT_ENABLE_MASK
;
598 assert_spin_locked(&dev_priv
->irq_lock
);
600 if (WARN_ONCE(enable_mask
& ~PIPESTAT_INT_ENABLE_MASK
||
601 status_mask
& ~PIPESTAT_INT_STATUS_MASK
,
602 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
603 pipe_name(pipe
), enable_mask
, status_mask
))
606 if ((pipestat
& enable_mask
) == 0)
609 dev_priv
->pipestat_irq_mask
[pipe
] &= ~status_mask
;
611 pipestat
&= ~enable_mask
;
612 I915_WRITE(reg
, pipestat
);
616 static u32
vlv_get_pipestat_enable_mask(struct drm_device
*dev
, u32 status_mask
)
618 u32 enable_mask
= status_mask
<< 16;
621 * On pipe A we don't support the PSR interrupt yet, on pipe B the
624 if (WARN_ON_ONCE(status_mask
& PIPE_A_PSR_STATUS_VLV
))
627 enable_mask
&= ~(PIPE_FIFO_UNDERRUN_STATUS
|
628 SPRITE0_FLIP_DONE_INT_EN_VLV
|
629 SPRITE1_FLIP_DONE_INT_EN_VLV
);
630 if (status_mask
& SPRITE0_FLIP_DONE_INT_STATUS_VLV
)
631 enable_mask
|= SPRITE0_FLIP_DONE_INT_EN_VLV
;
632 if (status_mask
& SPRITE1_FLIP_DONE_INT_STATUS_VLV
)
633 enable_mask
|= SPRITE1_FLIP_DONE_INT_EN_VLV
;
639 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
644 if (IS_VALLEYVIEW(dev_priv
->dev
))
645 enable_mask
= vlv_get_pipestat_enable_mask(dev_priv
->dev
,
648 enable_mask
= status_mask
<< 16;
649 __i915_enable_pipestat(dev_priv
, pipe
, enable_mask
, status_mask
);
653 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
658 if (IS_VALLEYVIEW(dev_priv
->dev
))
659 enable_mask
= vlv_get_pipestat_enable_mask(dev_priv
->dev
,
662 enable_mask
= status_mask
<< 16;
663 __i915_disable_pipestat(dev_priv
, pipe
, enable_mask
, status_mask
);
667 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
669 static void i915_enable_asle_pipestat(struct drm_device
*dev
)
671 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
672 unsigned long irqflags
;
674 if (!dev_priv
->opregion
.asle
|| !IS_MOBILE(dev
))
677 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
679 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_LEGACY_BLC_EVENT_STATUS
);
680 if (INTEL_INFO(dev
)->gen
>= 4)
681 i915_enable_pipestat(dev_priv
, PIPE_A
,
682 PIPE_LEGACY_BLC_EVENT_STATUS
);
684 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
688 * i915_pipe_enabled - check if a pipe is enabled
690 * @pipe: pipe to check
692 * Reading certain registers when the pipe is disabled can hang the chip.
693 * Use this routine to make sure the PLL is running and the pipe is active
694 * before reading such registers if unsure.
697 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
699 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
701 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
702 /* Locking is horribly broken here, but whatever. */
703 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
704 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
706 return intel_crtc
->active
;
708 return I915_READ(PIPECONF(pipe
)) & PIPECONF_ENABLE
;
712 static u32
i8xx_get_vblank_counter(struct drm_device
*dev
, int pipe
)
714 /* Gen2 doesn't have a hardware frame counter */
718 /* Called from drm generic code, passed a 'crtc', which
719 * we use as a pipe index
721 static u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
723 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
724 unsigned long high_frame
;
725 unsigned long low_frame
;
726 u32 high1
, high2
, low
, pixel
, vbl_start
;
728 if (!i915_pipe_enabled(dev
, pipe
)) {
729 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
730 "pipe %c\n", pipe_name(pipe
));
734 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
735 struct intel_crtc
*intel_crtc
=
736 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
737 const struct drm_display_mode
*mode
=
738 &intel_crtc
->config
.adjusted_mode
;
740 vbl_start
= mode
->crtc_vblank_start
* mode
->crtc_htotal
;
742 enum transcoder cpu_transcoder
= (enum transcoder
) pipe
;
745 htotal
= ((I915_READ(HTOTAL(cpu_transcoder
)) >> 16) & 0x1fff) + 1;
746 vbl_start
= (I915_READ(VBLANK(cpu_transcoder
)) & 0x1fff) + 1;
751 high_frame
= PIPEFRAME(pipe
);
752 low_frame
= PIPEFRAMEPIXEL(pipe
);
755 * High & low register fields aren't synchronized, so make sure
756 * we get a low value that's stable across two reads of the high
760 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
761 low
= I915_READ(low_frame
);
762 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
763 } while (high1
!= high2
);
765 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
766 pixel
= low
& PIPE_PIXEL_MASK
;
767 low
>>= PIPE_FRAME_LOW_SHIFT
;
770 * The frame counter increments at beginning of active.
771 * Cook up a vblank counter by also checking the pixel
772 * counter against vblank start.
774 return (((high1
<< 8) | low
) + (pixel
>= vbl_start
)) & 0xffffff;
777 static u32
gm45_get_vblank_counter(struct drm_device
*dev
, int pipe
)
779 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
780 int reg
= PIPE_FRMCOUNT_GM45(pipe
);
782 if (!i915_pipe_enabled(dev
, pipe
)) {
783 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
784 "pipe %c\n", pipe_name(pipe
));
788 return I915_READ(reg
);
791 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
792 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
794 static int __intel_get_crtc_scanline(struct intel_crtc
*crtc
)
796 struct drm_device
*dev
= crtc
->base
.dev
;
797 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
798 const struct drm_display_mode
*mode
= &crtc
->config
.adjusted_mode
;
799 enum pipe pipe
= crtc
->pipe
;
800 int vtotal
= mode
->crtc_vtotal
;
803 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
807 position
= __raw_i915_read32(dev_priv
, PIPEDSL(pipe
)) & DSL_LINEMASK_GEN2
;
809 position
= __raw_i915_read32(dev_priv
, PIPEDSL(pipe
)) & DSL_LINEMASK_GEN3
;
812 * Scanline counter increments at leading edge of hsync, and
813 * it starts counting from vtotal-1 on the first active line.
814 * That means the scanline counter value is always one less
815 * than what we would expect. Ie. just after start of vblank,
816 * which also occurs at start of hsync (on the last active line),
817 * the scanline counter will read vblank_start-1.
819 return (position
+ 1) % vtotal
;
822 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, int pipe
,
823 unsigned int flags
, int *vpos
, int *hpos
,
824 ktime_t
*stime
, ktime_t
*etime
)
826 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
827 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
828 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
829 const struct drm_display_mode
*mode
= &intel_crtc
->config
.adjusted_mode
;
831 int vbl_start
, vbl_end
, hsync_start
, htotal
, vtotal
;
834 unsigned long irqflags
;
836 if (!intel_crtc
->active
) {
837 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
838 "pipe %c\n", pipe_name(pipe
));
842 htotal
= mode
->crtc_htotal
;
843 hsync_start
= mode
->crtc_hsync_start
;
844 vtotal
= mode
->crtc_vtotal
;
845 vbl_start
= mode
->crtc_vblank_start
;
846 vbl_end
= mode
->crtc_vblank_end
;
848 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
849 vbl_start
= DIV_ROUND_UP(vbl_start
, 2);
854 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
857 * Lock uncore.lock, as we will do multiple timing critical raw
858 * register reads, potentially with preemption disabled, so the
859 * following code must not block on uncore.lock.
861 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
863 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
865 /* Get optional system timestamp before query. */
867 *stime
= ktime_get();
869 if (IS_GEN2(dev
) || IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
870 /* No obvious pixelcount register. Only query vertical
871 * scanout position from Display scan line register.
873 position
= __intel_get_crtc_scanline(intel_crtc
);
875 /* Have access to pixelcount since start of frame.
876 * We can split this into vertical and horizontal
879 position
= (__raw_i915_read32(dev_priv
, PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
881 /* convert to pixel counts */
887 * Start of vblank interrupt is triggered at start of hsync,
888 * just prior to the first active line of vblank. However we
889 * consider lines to start at the leading edge of horizontal
890 * active. So, should we get here before we've crossed into
891 * the horizontal active of the first line in vblank, we would
892 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
893 * always add htotal-hsync_start to the current pixel position.
895 position
= (position
+ htotal
- hsync_start
) % vtotal
;
898 /* Get optional system timestamp after query. */
900 *etime
= ktime_get();
902 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
904 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
906 in_vbl
= position
>= vbl_start
&& position
< vbl_end
;
909 * While in vblank, position will be negative
910 * counting up towards 0 at vbl_end. And outside
911 * vblank, position will be positive counting
914 if (position
>= vbl_start
)
917 position
+= vtotal
- vbl_end
;
919 if (IS_GEN2(dev
) || IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
923 *vpos
= position
/ htotal
;
924 *hpos
= position
- (*vpos
* htotal
);
929 ret
|= DRM_SCANOUTPOS_INVBL
;
934 int intel_get_crtc_scanline(struct intel_crtc
*crtc
)
936 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
937 unsigned long irqflags
;
940 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
941 position
= __intel_get_crtc_scanline(crtc
);
942 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
947 static int i915_get_vblank_timestamp(struct drm_device
*dev
, int pipe
,
949 struct timeval
*vblank_time
,
952 struct drm_crtc
*crtc
;
954 if (pipe
< 0 || pipe
>= INTEL_INFO(dev
)->num_pipes
) {
955 DRM_ERROR("Invalid crtc %d\n", pipe
);
959 /* Get drm_crtc to timestamp: */
960 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
962 DRM_ERROR("Invalid crtc %d\n", pipe
);
966 if (!crtc
->enabled
) {
967 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
971 /* Helper routine in DRM core does all the work: */
972 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
975 &to_intel_crtc(crtc
)->config
.adjusted_mode
);
978 static bool intel_hpd_irq_event(struct drm_device
*dev
,
979 struct drm_connector
*connector
)
981 enum drm_connector_status old_status
;
983 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
984 old_status
= connector
->status
;
986 connector
->status
= connector
->funcs
->detect(connector
, false);
987 if (old_status
== connector
->status
)
990 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
992 drm_get_connector_name(connector
),
993 drm_get_connector_status_name(old_status
),
994 drm_get_connector_status_name(connector
->status
));
1000 * Handle hotplug events outside the interrupt handler proper.
1002 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
1004 static void i915_hotplug_work_func(struct work_struct
*work
)
1006 struct drm_i915_private
*dev_priv
=
1007 container_of(work
, struct drm_i915_private
, hotplug_work
);
1008 struct drm_device
*dev
= dev_priv
->dev
;
1009 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
1010 struct intel_connector
*intel_connector
;
1011 struct intel_encoder
*intel_encoder
;
1012 struct drm_connector
*connector
;
1013 unsigned long irqflags
;
1014 bool hpd_disabled
= false;
1015 bool changed
= false;
1018 /* HPD irq before everything is fully set up. */
1019 if (!dev_priv
->enable_hotplug_processing
)
1022 mutex_lock(&mode_config
->mutex
);
1023 DRM_DEBUG_KMS("running encoder hotplug functions\n");
1025 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1027 hpd_event_bits
= dev_priv
->hpd_event_bits
;
1028 dev_priv
->hpd_event_bits
= 0;
1029 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
1030 intel_connector
= to_intel_connector(connector
);
1031 intel_encoder
= intel_connector
->encoder
;
1032 if (intel_encoder
->hpd_pin
> HPD_NONE
&&
1033 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_MARK_DISABLED
&&
1034 connector
->polled
== DRM_CONNECTOR_POLL_HPD
) {
1035 DRM_INFO("HPD interrupt storm detected on connector %s: "
1036 "switching from hotplug detection to polling\n",
1037 drm_get_connector_name(connector
));
1038 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
= HPD_DISABLED
;
1039 connector
->polled
= DRM_CONNECTOR_POLL_CONNECT
1040 | DRM_CONNECTOR_POLL_DISCONNECT
;
1041 hpd_disabled
= true;
1043 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
1044 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
1045 drm_get_connector_name(connector
), intel_encoder
->hpd_pin
);
1048 /* if there were no outputs to poll, poll was disabled,
1049 * therefore make sure it's enabled when disabling HPD on
1050 * some connectors */
1052 drm_kms_helper_poll_enable(dev
);
1053 mod_timer(&dev_priv
->hotplug_reenable_timer
,
1054 jiffies
+ msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY
));
1057 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1059 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
1060 intel_connector
= to_intel_connector(connector
);
1061 intel_encoder
= intel_connector
->encoder
;
1062 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
1063 if (intel_encoder
->hot_plug
)
1064 intel_encoder
->hot_plug(intel_encoder
);
1065 if (intel_hpd_irq_event(dev
, connector
))
1069 mutex_unlock(&mode_config
->mutex
);
1072 drm_kms_helper_hotplug_event(dev
);
1075 static void intel_hpd_irq_uninstall(struct drm_i915_private
*dev_priv
)
1077 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
1080 static void ironlake_rps_change_irq_handler(struct drm_device
*dev
)
1082 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1083 u32 busy_up
, busy_down
, max_avg
, min_avg
;
1086 spin_lock(&mchdev_lock
);
1088 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
1090 new_delay
= dev_priv
->ips
.cur_delay
;
1092 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
1093 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
1094 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
1095 max_avg
= I915_READ(RCBMAXAVG
);
1096 min_avg
= I915_READ(RCBMINAVG
);
1098 /* Handle RCS change request from hw */
1099 if (busy_up
> max_avg
) {
1100 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
1101 new_delay
= dev_priv
->ips
.cur_delay
- 1;
1102 if (new_delay
< dev_priv
->ips
.max_delay
)
1103 new_delay
= dev_priv
->ips
.max_delay
;
1104 } else if (busy_down
< min_avg
) {
1105 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
1106 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
1107 if (new_delay
> dev_priv
->ips
.min_delay
)
1108 new_delay
= dev_priv
->ips
.min_delay
;
1111 if (ironlake_set_drps(dev
, new_delay
))
1112 dev_priv
->ips
.cur_delay
= new_delay
;
1114 spin_unlock(&mchdev_lock
);
1119 static void notify_ring(struct drm_device
*dev
,
1120 struct intel_ring_buffer
*ring
)
1122 if (ring
->obj
== NULL
)
1125 trace_i915_gem_request_complete(ring
);
1127 wake_up_all(&ring
->irq_queue
);
1128 i915_queue_hangcheck(dev
);
1131 static void gen6_pm_rps_work(struct work_struct
*work
)
1133 struct drm_i915_private
*dev_priv
=
1134 container_of(work
, struct drm_i915_private
, rps
.work
);
1138 spin_lock_irq(&dev_priv
->irq_lock
);
1139 pm_iir
= dev_priv
->rps
.pm_iir
;
1140 dev_priv
->rps
.pm_iir
= 0;
1141 if (IS_BROADWELL(dev_priv
->dev
))
1142 bdw_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
1144 /* Make sure not to corrupt PMIMR state used by ringbuffer */
1145 snb_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
1147 spin_unlock_irq(&dev_priv
->irq_lock
);
1149 /* Make sure we didn't queue anything we're not going to process. */
1150 WARN_ON(pm_iir
& ~dev_priv
->pm_rps_events
);
1152 if ((pm_iir
& dev_priv
->pm_rps_events
) == 0)
1155 mutex_lock(&dev_priv
->rps
.hw_lock
);
1157 adj
= dev_priv
->rps
.last_adj
;
1158 if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
) {
1163 new_delay
= dev_priv
->rps
.cur_freq
+ adj
;
1166 * For better performance, jump directly
1167 * to RPe if we're below it.
1169 if (new_delay
< dev_priv
->rps
.efficient_freq
)
1170 new_delay
= dev_priv
->rps
.efficient_freq
;
1171 } else if (pm_iir
& GEN6_PM_RP_DOWN_TIMEOUT
) {
1172 if (dev_priv
->rps
.cur_freq
> dev_priv
->rps
.efficient_freq
)
1173 new_delay
= dev_priv
->rps
.efficient_freq
;
1175 new_delay
= dev_priv
->rps
.min_freq_softlimit
;
1177 } else if (pm_iir
& GEN6_PM_RP_DOWN_THRESHOLD
) {
1182 new_delay
= dev_priv
->rps
.cur_freq
+ adj
;
1183 } else { /* unknown event */
1184 new_delay
= dev_priv
->rps
.cur_freq
;
1187 /* sysfs frequency interfaces may have snuck in while servicing the
1190 new_delay
= clamp_t(int, new_delay
,
1191 dev_priv
->rps
.min_freq_softlimit
,
1192 dev_priv
->rps
.max_freq_softlimit
);
1194 dev_priv
->rps
.last_adj
= new_delay
- dev_priv
->rps
.cur_freq
;
1196 if (IS_VALLEYVIEW(dev_priv
->dev
))
1197 valleyview_set_rps(dev_priv
->dev
, new_delay
);
1199 gen6_set_rps(dev_priv
->dev
, new_delay
);
1201 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1206 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1208 * @work: workqueue struct
1210 * Doesn't actually do anything except notify userspace. As a consequence of
1211 * this event, userspace should try to remap the bad rows since statistically
1212 * it is likely the same row is more likely to go bad again.
1214 static void ivybridge_parity_work(struct work_struct
*work
)
1216 struct drm_i915_private
*dev_priv
=
1217 container_of(work
, struct drm_i915_private
, l3_parity
.error_work
);
1218 u32 error_status
, row
, bank
, subbank
;
1219 char *parity_event
[6];
1221 unsigned long flags
;
1224 /* We must turn off DOP level clock gating to access the L3 registers.
1225 * In order to prevent a get/put style interface, acquire struct mutex
1226 * any time we access those registers.
1228 mutex_lock(&dev_priv
->dev
->struct_mutex
);
1230 /* If we've screwed up tracking, just let the interrupt fire again */
1231 if (WARN_ON(!dev_priv
->l3_parity
.which_slice
))
1234 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
1235 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
1236 POSTING_READ(GEN7_MISCCPCTL
);
1238 while ((slice
= ffs(dev_priv
->l3_parity
.which_slice
)) != 0) {
1242 if (WARN_ON_ONCE(slice
>= NUM_L3_SLICES(dev_priv
->dev
)))
1245 dev_priv
->l3_parity
.which_slice
&= ~(1<<slice
);
1247 reg
= GEN7_L3CDERRST1
+ (slice
* 0x200);
1249 error_status
= I915_READ(reg
);
1250 row
= GEN7_PARITY_ERROR_ROW(error_status
);
1251 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
1252 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
1254 I915_WRITE(reg
, GEN7_PARITY_ERROR_VALID
| GEN7_L3CDERRST1_ENABLE
);
1257 parity_event
[0] = I915_L3_PARITY_UEVENT
"=1";
1258 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
1259 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
1260 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
1261 parity_event
[4] = kasprintf(GFP_KERNEL
, "SLICE=%d", slice
);
1262 parity_event
[5] = NULL
;
1264 kobject_uevent_env(&dev_priv
->dev
->primary
->kdev
->kobj
,
1265 KOBJ_CHANGE
, parity_event
);
1267 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1268 slice
, row
, bank
, subbank
);
1270 kfree(parity_event
[4]);
1271 kfree(parity_event
[3]);
1272 kfree(parity_event
[2]);
1273 kfree(parity_event
[1]);
1276 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
1279 WARN_ON(dev_priv
->l3_parity
.which_slice
);
1280 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1281 ilk_enable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev_priv
->dev
));
1282 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1284 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
1287 static void ivybridge_parity_error_irq_handler(struct drm_device
*dev
, u32 iir
)
1289 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1291 if (!HAS_L3_DPF(dev
))
1294 spin_lock(&dev_priv
->irq_lock
);
1295 ilk_disable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev
));
1296 spin_unlock(&dev_priv
->irq_lock
);
1298 iir
&= GT_PARITY_ERROR(dev
);
1299 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1
)
1300 dev_priv
->l3_parity
.which_slice
|= 1 << 1;
1302 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT
)
1303 dev_priv
->l3_parity
.which_slice
|= 1 << 0;
1305 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
1308 static void ilk_gt_irq_handler(struct drm_device
*dev
,
1309 struct drm_i915_private
*dev_priv
,
1313 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1314 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
1315 if (gt_iir
& ILK_BSD_USER_INTERRUPT
)
1316 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1319 static void snb_gt_irq_handler(struct drm_device
*dev
,
1320 struct drm_i915_private
*dev_priv
,
1325 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1326 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
1327 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
1328 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1329 if (gt_iir
& GT_BLT_USER_INTERRUPT
)
1330 notify_ring(dev
, &dev_priv
->ring
[BCS
]);
1332 if (gt_iir
& (GT_BLT_CS_ERROR_INTERRUPT
|
1333 GT_BSD_CS_ERROR_INTERRUPT
|
1334 GT_RENDER_CS_MASTER_ERROR_INTERRUPT
)) {
1335 i915_handle_error(dev
, false, "GT error interrupt 0x%08x",
1339 if (gt_iir
& GT_PARITY_ERROR(dev
))
1340 ivybridge_parity_error_irq_handler(dev
, gt_iir
);
1343 static void gen8_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1345 if ((pm_iir
& dev_priv
->pm_rps_events
) == 0)
1348 spin_lock(&dev_priv
->irq_lock
);
1349 dev_priv
->rps
.pm_iir
|= pm_iir
& dev_priv
->pm_rps_events
;
1350 bdw_disable_pm_irq(dev_priv
, pm_iir
& dev_priv
->pm_rps_events
);
1351 spin_unlock(&dev_priv
->irq_lock
);
1353 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
1356 static irqreturn_t
gen8_gt_irq_handler(struct drm_device
*dev
,
1357 struct drm_i915_private
*dev_priv
,
1362 irqreturn_t ret
= IRQ_NONE
;
1364 if (master_ctl
& (GEN8_GT_RCS_IRQ
| GEN8_GT_BCS_IRQ
)) {
1365 tmp
= I915_READ(GEN8_GT_IIR(0));
1368 rcs
= tmp
>> GEN8_RCS_IRQ_SHIFT
;
1369 bcs
= tmp
>> GEN8_BCS_IRQ_SHIFT
;
1370 if (rcs
& GT_RENDER_USER_INTERRUPT
)
1371 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
1372 if (bcs
& GT_RENDER_USER_INTERRUPT
)
1373 notify_ring(dev
, &dev_priv
->ring
[BCS
]);
1374 I915_WRITE(GEN8_GT_IIR(0), tmp
);
1376 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1379 if (master_ctl
& (GEN8_GT_VCS1_IRQ
| GEN8_GT_VCS2_IRQ
)) {
1380 tmp
= I915_READ(GEN8_GT_IIR(1));
1383 vcs
= tmp
>> GEN8_VCS1_IRQ_SHIFT
;
1384 if (vcs
& GT_RENDER_USER_INTERRUPT
)
1385 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1386 vcs
= tmp
>> GEN8_VCS2_IRQ_SHIFT
;
1387 if (vcs
& GT_RENDER_USER_INTERRUPT
)
1388 notify_ring(dev
, &dev_priv
->ring
[VCS2
]);
1389 I915_WRITE(GEN8_GT_IIR(1), tmp
);
1391 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1394 if (master_ctl
& GEN8_GT_PM_IRQ
) {
1395 tmp
= I915_READ(GEN8_GT_IIR(2));
1396 if (tmp
& dev_priv
->pm_rps_events
) {
1398 gen8_rps_irq_handler(dev_priv
, tmp
);
1399 I915_WRITE(GEN8_GT_IIR(2),
1400 tmp
& dev_priv
->pm_rps_events
);
1402 DRM_ERROR("The master control interrupt lied (PM)!\n");
1405 if (master_ctl
& GEN8_GT_VECS_IRQ
) {
1406 tmp
= I915_READ(GEN8_GT_IIR(3));
1409 vcs
= tmp
>> GEN8_VECS_IRQ_SHIFT
;
1410 if (vcs
& GT_RENDER_USER_INTERRUPT
)
1411 notify_ring(dev
, &dev_priv
->ring
[VECS
]);
1412 I915_WRITE(GEN8_GT_IIR(3), tmp
);
1414 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1420 #define HPD_STORM_DETECT_PERIOD 1000
1421 #define HPD_STORM_THRESHOLD 5
1423 static inline void intel_hpd_irq_handler(struct drm_device
*dev
,
1424 u32 hotplug_trigger
,
1427 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1429 bool storm_detected
= false;
1431 if (!hotplug_trigger
)
1434 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1437 spin_lock(&dev_priv
->irq_lock
);
1438 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
1440 if (hpd
[i
] & hotplug_trigger
&&
1441 dev_priv
->hpd_stats
[i
].hpd_mark
== HPD_DISABLED
) {
1443 * On GMCH platforms the interrupt mask bits only
1444 * prevent irq generation, not the setting of the
1445 * hotplug bits itself. So only WARN about unexpected
1446 * interrupts on saner platforms.
1448 WARN_ONCE(INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
),
1449 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1450 hotplug_trigger
, i
, hpd
[i
]);
1455 if (!(hpd
[i
] & hotplug_trigger
) ||
1456 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
)
1459 dev_priv
->hpd_event_bits
|= (1 << i
);
1460 if (!time_in_range(jiffies
, dev_priv
->hpd_stats
[i
].hpd_last_jiffies
,
1461 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
1462 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD
))) {
1463 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
= jiffies
;
1464 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
1465 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i
);
1466 } else if (dev_priv
->hpd_stats
[i
].hpd_cnt
> HPD_STORM_THRESHOLD
) {
1467 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_MARK_DISABLED
;
1468 dev_priv
->hpd_event_bits
&= ~(1 << i
);
1469 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i
);
1470 storm_detected
= true;
1472 dev_priv
->hpd_stats
[i
].hpd_cnt
++;
1473 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i
,
1474 dev_priv
->hpd_stats
[i
].hpd_cnt
);
1479 dev_priv
->display
.hpd_irq_setup(dev
);
1480 spin_unlock(&dev_priv
->irq_lock
);
1483 * Our hotplug handler can grab modeset locks (by calling down into the
1484 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1485 * queue for otherwise the flush_work in the pageflip code will
1488 schedule_work(&dev_priv
->hotplug_work
);
1491 static void gmbus_irq_handler(struct drm_device
*dev
)
1493 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1495 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1498 static void dp_aux_irq_handler(struct drm_device
*dev
)
1500 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1502 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1505 #if defined(CONFIG_DEBUG_FS)
1506 static void display_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
,
1507 uint32_t crc0
, uint32_t crc1
,
1508 uint32_t crc2
, uint32_t crc3
,
1511 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1512 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
1513 struct intel_pipe_crc_entry
*entry
;
1516 spin_lock(&pipe_crc
->lock
);
1518 if (!pipe_crc
->entries
) {
1519 spin_unlock(&pipe_crc
->lock
);
1520 DRM_ERROR("spurious interrupt\n");
1524 head
= pipe_crc
->head
;
1525 tail
= pipe_crc
->tail
;
1527 if (CIRC_SPACE(head
, tail
, INTEL_PIPE_CRC_ENTRIES_NR
) < 1) {
1528 spin_unlock(&pipe_crc
->lock
);
1529 DRM_ERROR("CRC buffer overflowing\n");
1533 entry
= &pipe_crc
->entries
[head
];
1535 entry
->frame
= dev
->driver
->get_vblank_counter(dev
, pipe
);
1536 entry
->crc
[0] = crc0
;
1537 entry
->crc
[1] = crc1
;
1538 entry
->crc
[2] = crc2
;
1539 entry
->crc
[3] = crc3
;
1540 entry
->crc
[4] = crc4
;
1542 head
= (head
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
1543 pipe_crc
->head
= head
;
1545 spin_unlock(&pipe_crc
->lock
);
1547 wake_up_interruptible(&pipe_crc
->wq
);
1551 display_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
,
1552 uint32_t crc0
, uint32_t crc1
,
1553 uint32_t crc2
, uint32_t crc3
,
1558 static void hsw_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
)
1560 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1562 display_pipe_crc_irq_handler(dev
, pipe
,
1563 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1567 static void ivb_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
)
1569 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1571 display_pipe_crc_irq_handler(dev
, pipe
,
1572 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1573 I915_READ(PIPE_CRC_RES_2_IVB(pipe
)),
1574 I915_READ(PIPE_CRC_RES_3_IVB(pipe
)),
1575 I915_READ(PIPE_CRC_RES_4_IVB(pipe
)),
1576 I915_READ(PIPE_CRC_RES_5_IVB(pipe
)));
1579 static void i9xx_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
)
1581 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1582 uint32_t res1
, res2
;
1584 if (INTEL_INFO(dev
)->gen
>= 3)
1585 res1
= I915_READ(PIPE_CRC_RES_RES1_I915(pipe
));
1589 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
1590 res2
= I915_READ(PIPE_CRC_RES_RES2_G4X(pipe
));
1594 display_pipe_crc_irq_handler(dev
, pipe
,
1595 I915_READ(PIPE_CRC_RES_RED(pipe
)),
1596 I915_READ(PIPE_CRC_RES_GREEN(pipe
)),
1597 I915_READ(PIPE_CRC_RES_BLUE(pipe
)),
1601 /* The RPS events need forcewake, so we add them to a work queue and mask their
1602 * IMR bits until the work is done. Other interrupts can be processed without
1603 * the work queue. */
1604 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1606 if (pm_iir
& dev_priv
->pm_rps_events
) {
1607 spin_lock(&dev_priv
->irq_lock
);
1608 dev_priv
->rps
.pm_iir
|= pm_iir
& dev_priv
->pm_rps_events
;
1609 snb_disable_pm_irq(dev_priv
, pm_iir
& dev_priv
->pm_rps_events
);
1610 spin_unlock(&dev_priv
->irq_lock
);
1612 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
1615 if (HAS_VEBOX(dev_priv
->dev
)) {
1616 if (pm_iir
& PM_VEBOX_USER_INTERRUPT
)
1617 notify_ring(dev_priv
->dev
, &dev_priv
->ring
[VECS
]);
1619 if (pm_iir
& PM_VEBOX_CS_ERROR_INTERRUPT
) {
1620 i915_handle_error(dev_priv
->dev
, false,
1621 "VEBOX CS error interrupt 0x%08x",
1627 static bool intel_pipe_handle_vblank(struct drm_device
*dev
, enum pipe pipe
)
1629 struct intel_crtc
*crtc
;
1631 if (!drm_handle_vblank(dev
, pipe
))
1634 crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
, pipe
));
1635 wake_up(&crtc
->vbl_wait
);
1640 static void valleyview_pipestat_irq_handler(struct drm_device
*dev
, u32 iir
)
1642 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1643 u32 pipe_stats
[I915_MAX_PIPES
] = { };
1646 spin_lock(&dev_priv
->irq_lock
);
1647 for_each_pipe(pipe
) {
1649 u32 mask
, iir_bit
= 0;
1652 * PIPESTAT bits get signalled even when the interrupt is
1653 * disabled with the mask bits, and some of the status bits do
1654 * not generate interrupts at all (like the underrun bit). Hence
1655 * we need to be careful that we only handle what we want to
1659 if (__cpu_fifo_underrun_reporting_enabled(dev
, pipe
))
1660 mask
|= PIPE_FIFO_UNDERRUN_STATUS
;
1664 iir_bit
= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
;
1667 iir_bit
= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
1671 mask
|= dev_priv
->pipestat_irq_mask
[pipe
];
1676 reg
= PIPESTAT(pipe
);
1677 mask
|= PIPESTAT_INT_ENABLE_MASK
;
1678 pipe_stats
[pipe
] = I915_READ(reg
) & mask
;
1681 * Clear the PIPE*STAT regs before the IIR
1683 if (pipe_stats
[pipe
] & (PIPE_FIFO_UNDERRUN_STATUS
|
1684 PIPESTAT_INT_STATUS_MASK
))
1685 I915_WRITE(reg
, pipe_stats
[pipe
]);
1687 spin_unlock(&dev_priv
->irq_lock
);
1689 for_each_pipe(pipe
) {
1690 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
)
1691 intel_pipe_handle_vblank(dev
, pipe
);
1693 if (pipe_stats
[pipe
] & PLANE_FLIP_DONE_INT_STATUS_VLV
) {
1694 intel_prepare_page_flip(dev
, pipe
);
1695 intel_finish_page_flip(dev
, pipe
);
1698 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
1699 i9xx_pipe_crc_irq_handler(dev
, pipe
);
1701 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
&&
1702 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, false))
1703 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe
));
1706 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1707 gmbus_irq_handler(dev
);
1710 static void i9xx_hpd_irq_handler(struct drm_device
*dev
)
1712 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1713 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1716 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_G4X
;
1718 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_g4x
);
1720 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
1722 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
1725 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) &&
1726 hotplug_status
& DP_AUX_CHANNEL_MASK_INT_STATUS_G4X
)
1727 dp_aux_irq_handler(dev
);
1729 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1731 * Make sure hotplug status is cleared before we clear IIR, or else we
1732 * may miss hotplug events.
1734 POSTING_READ(PORT_HOTPLUG_STAT
);
1737 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
1739 struct drm_device
*dev
= arg
;
1740 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1741 u32 iir
, gt_iir
, pm_iir
;
1742 irqreturn_t ret
= IRQ_NONE
;
1745 iir
= I915_READ(VLV_IIR
);
1746 gt_iir
= I915_READ(GTIIR
);
1747 pm_iir
= I915_READ(GEN6_PMIIR
);
1749 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
1754 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1756 valleyview_pipestat_irq_handler(dev
, iir
);
1758 /* Consume port. Then clear IIR or we'll miss events */
1759 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
1760 i9xx_hpd_irq_handler(dev
);
1763 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1765 I915_WRITE(GTIIR
, gt_iir
);
1766 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1767 I915_WRITE(VLV_IIR
, iir
);
1774 static irqreturn_t
cherryview_irq_handler(int irq
, void *arg
)
1776 struct drm_device
*dev
= arg
;
1777 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1778 u32 master_ctl
, iir
;
1779 irqreturn_t ret
= IRQ_NONE
;
1780 unsigned int pipes
= 0;
1782 master_ctl
= I915_READ(GEN8_MASTER_IRQ
);
1784 I915_WRITE(GEN8_MASTER_IRQ
, 0);
1786 ret
= gen8_gt_irq_handler(dev
, dev_priv
, master_ctl
);
1788 iir
= I915_READ(VLV_IIR
);
1790 if (iir
& (I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
| I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
))
1792 if (iir
& (I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
| I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
))
1794 if (iir
& (I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT
| I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
))
1798 u32 pipe_stats
[I915_MAX_PIPES
] = {};
1799 unsigned long irqflags
;
1802 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1803 for_each_pipe(pipe
) {
1806 if (!(pipes
& (1 << pipe
)))
1809 reg
= PIPESTAT(pipe
);
1810 pipe_stats
[pipe
] = I915_READ(reg
);
1813 * Clear the PIPE*STAT regs before the IIR
1815 if (pipe_stats
[pipe
] & 0x8000ffff) {
1816 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
1817 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1819 I915_WRITE(reg
, pipe_stats
[pipe
]);
1822 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1824 for_each_pipe(pipe
) {
1825 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
)
1826 drm_handle_vblank(dev
, pipe
);
1828 if (pipe_stats
[pipe
] & PLANE_FLIP_DONE_INT_STATUS_VLV
) {
1829 intel_prepare_page_flip(dev
, pipe
);
1830 intel_finish_page_flip(dev
, pipe
);
1834 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1835 gmbus_irq_handler(dev
);
1840 /* Consume port. Then clear IIR or we'll miss events */
1841 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
1842 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1844 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1846 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1848 if (hotplug_status
& HOTPLUG_INT_STATUS_I915
)
1849 queue_work(dev_priv
->wq
,
1850 &dev_priv
->hotplug_work
);
1855 I915_WRITE(VLV_IIR
, iir
);
1857 I915_WRITE(GEN8_MASTER_IRQ
, DE_MASTER_IRQ_CONTROL
);
1858 POSTING_READ(GEN8_MASTER_IRQ
);
1863 static void ibx_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1865 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1867 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK
;
1869 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_ibx
);
1871 if (pch_iir
& SDE_AUDIO_POWER_MASK
) {
1872 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK
) >>
1873 SDE_AUDIO_POWER_SHIFT
);
1874 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1878 if (pch_iir
& SDE_AUX_MASK
)
1879 dp_aux_irq_handler(dev
);
1881 if (pch_iir
& SDE_GMBUS
)
1882 gmbus_irq_handler(dev
);
1884 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
1885 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1887 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
1888 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1890 if (pch_iir
& SDE_POISON
)
1891 DRM_ERROR("PCH poison interrupt\n");
1893 if (pch_iir
& SDE_FDI_MASK
)
1895 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1897 I915_READ(FDI_RX_IIR(pipe
)));
1899 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
1900 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1902 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
1903 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1905 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
1906 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1908 DRM_ERROR("PCH transcoder A FIFO underrun\n");
1910 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
1911 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1913 DRM_ERROR("PCH transcoder B FIFO underrun\n");
1916 static void ivb_err_int_handler(struct drm_device
*dev
)
1918 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1919 u32 err_int
= I915_READ(GEN7_ERR_INT
);
1922 if (err_int
& ERR_INT_POISON
)
1923 DRM_ERROR("Poison interrupt\n");
1925 for_each_pipe(pipe
) {
1926 if (err_int
& ERR_INT_FIFO_UNDERRUN(pipe
)) {
1927 if (intel_set_cpu_fifo_underrun_reporting(dev
, pipe
,
1929 DRM_ERROR("Pipe %c FIFO underrun\n",
1933 if (err_int
& ERR_INT_PIPE_CRC_DONE(pipe
)) {
1934 if (IS_IVYBRIDGE(dev
))
1935 ivb_pipe_crc_irq_handler(dev
, pipe
);
1937 hsw_pipe_crc_irq_handler(dev
, pipe
);
1941 I915_WRITE(GEN7_ERR_INT
, err_int
);
1944 static void cpt_serr_int_handler(struct drm_device
*dev
)
1946 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1947 u32 serr_int
= I915_READ(SERR_INT
);
1949 if (serr_int
& SERR_INT_POISON
)
1950 DRM_ERROR("PCH poison interrupt\n");
1952 if (serr_int
& SERR_INT_TRANS_A_FIFO_UNDERRUN
)
1953 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1955 DRM_ERROR("PCH transcoder A FIFO underrun\n");
1957 if (serr_int
& SERR_INT_TRANS_B_FIFO_UNDERRUN
)
1958 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1960 DRM_ERROR("PCH transcoder B FIFO underrun\n");
1962 if (serr_int
& SERR_INT_TRANS_C_FIFO_UNDERRUN
)
1963 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_C
,
1965 DRM_ERROR("PCH transcoder C FIFO underrun\n");
1967 I915_WRITE(SERR_INT
, serr_int
);
1970 static void cpt_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1972 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1974 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_CPT
;
1976 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_cpt
);
1978 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) {
1979 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
1980 SDE_AUDIO_POWER_SHIFT_CPT
);
1981 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1985 if (pch_iir
& SDE_AUX_MASK_CPT
)
1986 dp_aux_irq_handler(dev
);
1988 if (pch_iir
& SDE_GMBUS_CPT
)
1989 gmbus_irq_handler(dev
);
1991 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
1992 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1994 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
1995 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1997 if (pch_iir
& SDE_FDI_MASK_CPT
)
1999 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2001 I915_READ(FDI_RX_IIR(pipe
)));
2003 if (pch_iir
& SDE_ERROR_CPT
)
2004 cpt_serr_int_handler(dev
);
2007 static void ilk_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
2009 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2012 if (de_iir
& DE_AUX_CHANNEL_A
)
2013 dp_aux_irq_handler(dev
);
2015 if (de_iir
& DE_GSE
)
2016 intel_opregion_asle_intr(dev
);
2018 if (de_iir
& DE_POISON
)
2019 DRM_ERROR("Poison interrupt\n");
2021 for_each_pipe(pipe
) {
2022 if (de_iir
& DE_PIPE_VBLANK(pipe
))
2023 intel_pipe_handle_vblank(dev
, pipe
);
2025 if (de_iir
& DE_PIPE_FIFO_UNDERRUN(pipe
))
2026 if (intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, false))
2027 DRM_ERROR("Pipe %c FIFO underrun\n",
2030 if (de_iir
& DE_PIPE_CRC_DONE(pipe
))
2031 i9xx_pipe_crc_irq_handler(dev
, pipe
);
2033 /* plane/pipes map 1:1 on ilk+ */
2034 if (de_iir
& DE_PLANE_FLIP_DONE(pipe
)) {
2035 intel_prepare_page_flip(dev
, pipe
);
2036 intel_finish_page_flip_plane(dev
, pipe
);
2040 /* check event from PCH */
2041 if (de_iir
& DE_PCH_EVENT
) {
2042 u32 pch_iir
= I915_READ(SDEIIR
);
2044 if (HAS_PCH_CPT(dev
))
2045 cpt_irq_handler(dev
, pch_iir
);
2047 ibx_irq_handler(dev
, pch_iir
);
2049 /* should clear PCH hotplug event before clear CPU irq */
2050 I915_WRITE(SDEIIR
, pch_iir
);
2053 if (IS_GEN5(dev
) && de_iir
& DE_PCU_EVENT
)
2054 ironlake_rps_change_irq_handler(dev
);
2057 static void ivb_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
2059 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2062 if (de_iir
& DE_ERR_INT_IVB
)
2063 ivb_err_int_handler(dev
);
2065 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
2066 dp_aux_irq_handler(dev
);
2068 if (de_iir
& DE_GSE_IVB
)
2069 intel_opregion_asle_intr(dev
);
2071 for_each_pipe(pipe
) {
2072 if (de_iir
& (DE_PIPE_VBLANK_IVB(pipe
)))
2073 intel_pipe_handle_vblank(dev
, pipe
);
2075 /* plane/pipes map 1:1 on ilk+ */
2076 if (de_iir
& DE_PLANE_FLIP_DONE_IVB(pipe
)) {
2077 intel_prepare_page_flip(dev
, pipe
);
2078 intel_finish_page_flip_plane(dev
, pipe
);
2082 /* check event from PCH */
2083 if (!HAS_PCH_NOP(dev
) && (de_iir
& DE_PCH_EVENT_IVB
)) {
2084 u32 pch_iir
= I915_READ(SDEIIR
);
2086 cpt_irq_handler(dev
, pch_iir
);
2088 /* clear PCH hotplug event before clear CPU irq */
2089 I915_WRITE(SDEIIR
, pch_iir
);
2093 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
2095 struct drm_device
*dev
= arg
;
2096 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2097 u32 de_iir
, gt_iir
, de_ier
, sde_ier
= 0;
2098 irqreturn_t ret
= IRQ_NONE
;
2100 /* We get interrupts on unclaimed registers, so check for this before we
2101 * do any I915_{READ,WRITE}. */
2102 intel_uncore_check_errors(dev
);
2104 /* disable master interrupt before clearing iir */
2105 de_ier
= I915_READ(DEIER
);
2106 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
2107 POSTING_READ(DEIER
);
2109 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2110 * interrupts will will be stored on its back queue, and then we'll be
2111 * able to process them after we restore SDEIER (as soon as we restore
2112 * it, we'll get an interrupt if SDEIIR still has something to process
2113 * due to its back queue). */
2114 if (!HAS_PCH_NOP(dev
)) {
2115 sde_ier
= I915_READ(SDEIER
);
2116 I915_WRITE(SDEIER
, 0);
2117 POSTING_READ(SDEIER
);
2120 gt_iir
= I915_READ(GTIIR
);
2122 if (INTEL_INFO(dev
)->gen
>= 6)
2123 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
2125 ilk_gt_irq_handler(dev
, dev_priv
, gt_iir
);
2126 I915_WRITE(GTIIR
, gt_iir
);
2130 de_iir
= I915_READ(DEIIR
);
2132 if (INTEL_INFO(dev
)->gen
>= 7)
2133 ivb_display_irq_handler(dev
, de_iir
);
2135 ilk_display_irq_handler(dev
, de_iir
);
2136 I915_WRITE(DEIIR
, de_iir
);
2140 if (INTEL_INFO(dev
)->gen
>= 6) {
2141 u32 pm_iir
= I915_READ(GEN6_PMIIR
);
2143 gen6_rps_irq_handler(dev_priv
, pm_iir
);
2144 I915_WRITE(GEN6_PMIIR
, pm_iir
);
2149 I915_WRITE(DEIER
, de_ier
);
2150 POSTING_READ(DEIER
);
2151 if (!HAS_PCH_NOP(dev
)) {
2152 I915_WRITE(SDEIER
, sde_ier
);
2153 POSTING_READ(SDEIER
);
2159 static irqreturn_t
gen8_irq_handler(int irq
, void *arg
)
2161 struct drm_device
*dev
= arg
;
2162 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2164 irqreturn_t ret
= IRQ_NONE
;
2168 master_ctl
= I915_READ(GEN8_MASTER_IRQ
);
2169 master_ctl
&= ~GEN8_MASTER_IRQ_CONTROL
;
2173 I915_WRITE(GEN8_MASTER_IRQ
, 0);
2174 POSTING_READ(GEN8_MASTER_IRQ
);
2176 ret
= gen8_gt_irq_handler(dev
, dev_priv
, master_ctl
);
2178 if (master_ctl
& GEN8_DE_MISC_IRQ
) {
2179 tmp
= I915_READ(GEN8_DE_MISC_IIR
);
2180 if (tmp
& GEN8_DE_MISC_GSE
)
2181 intel_opregion_asle_intr(dev
);
2183 DRM_ERROR("Unexpected DE Misc interrupt\n");
2185 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2188 I915_WRITE(GEN8_DE_MISC_IIR
, tmp
);
2193 if (master_ctl
& GEN8_DE_PORT_IRQ
) {
2194 tmp
= I915_READ(GEN8_DE_PORT_IIR
);
2195 if (tmp
& GEN8_AUX_CHANNEL_A
)
2196 dp_aux_irq_handler(dev
);
2198 DRM_ERROR("Unexpected DE Port interrupt\n");
2200 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2203 I915_WRITE(GEN8_DE_PORT_IIR
, tmp
);
2208 for_each_pipe(pipe
) {
2211 if (!(master_ctl
& GEN8_DE_PIPE_IRQ(pipe
)))
2214 pipe_iir
= I915_READ(GEN8_DE_PIPE_IIR(pipe
));
2215 if (pipe_iir
& GEN8_PIPE_VBLANK
)
2216 intel_pipe_handle_vblank(dev
, pipe
);
2218 if (pipe_iir
& GEN8_PIPE_PRIMARY_FLIP_DONE
) {
2219 intel_prepare_page_flip(dev
, pipe
);
2220 intel_finish_page_flip_plane(dev
, pipe
);
2223 if (pipe_iir
& GEN8_PIPE_CDCLK_CRC_DONE
)
2224 hsw_pipe_crc_irq_handler(dev
, pipe
);
2226 if (pipe_iir
& GEN8_PIPE_FIFO_UNDERRUN
) {
2227 if (intel_set_cpu_fifo_underrun_reporting(dev
, pipe
,
2229 DRM_ERROR("Pipe %c FIFO underrun\n",
2233 if (pipe_iir
& GEN8_DE_PIPE_IRQ_FAULT_ERRORS
) {
2234 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2236 pipe_iir
& GEN8_DE_PIPE_IRQ_FAULT_ERRORS
);
2241 I915_WRITE(GEN8_DE_PIPE_IIR(pipe
), pipe_iir
);
2243 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2246 if (!HAS_PCH_NOP(dev
) && master_ctl
& GEN8_DE_PCH_IRQ
) {
2248 * FIXME(BDW): Assume for now that the new interrupt handling
2249 * scheme also closed the SDE interrupt handling race we've seen
2250 * on older pch-split platforms. But this needs testing.
2252 u32 pch_iir
= I915_READ(SDEIIR
);
2254 cpt_irq_handler(dev
, pch_iir
);
2257 I915_WRITE(SDEIIR
, pch_iir
);
2262 I915_WRITE(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
2263 POSTING_READ(GEN8_MASTER_IRQ
);
2268 static void i915_error_wake_up(struct drm_i915_private
*dev_priv
,
2269 bool reset_completed
)
2271 struct intel_ring_buffer
*ring
;
2275 * Notify all waiters for GPU completion events that reset state has
2276 * been changed, and that they need to restart their wait after
2277 * checking for potential errors (and bail out to drop locks if there is
2278 * a gpu reset pending so that i915_error_work_func can acquire them).
2281 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2282 for_each_ring(ring
, dev_priv
, i
)
2283 wake_up_all(&ring
->irq_queue
);
2285 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2286 wake_up_all(&dev_priv
->pending_flip_queue
);
2289 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2290 * reset state is cleared.
2292 if (reset_completed
)
2293 wake_up_all(&dev_priv
->gpu_error
.reset_queue
);
2297 * i915_error_work_func - do process context error handling work
2298 * @work: work struct
2300 * Fire an error uevent so userspace can see that a hang or error
2303 static void i915_error_work_func(struct work_struct
*work
)
2305 struct i915_gpu_error
*error
= container_of(work
, struct i915_gpu_error
,
2307 struct drm_i915_private
*dev_priv
=
2308 container_of(error
, struct drm_i915_private
, gpu_error
);
2309 struct drm_device
*dev
= dev_priv
->dev
;
2310 char *error_event
[] = { I915_ERROR_UEVENT
"=1", NULL
};
2311 char *reset_event
[] = { I915_RESET_UEVENT
"=1", NULL
};
2312 char *reset_done_event
[] = { I915_ERROR_UEVENT
"=0", NULL
};
2315 kobject_uevent_env(&dev
->primary
->kdev
->kobj
, KOBJ_CHANGE
, error_event
);
2318 * Note that there's only one work item which does gpu resets, so we
2319 * need not worry about concurrent gpu resets potentially incrementing
2320 * error->reset_counter twice. We only need to take care of another
2321 * racing irq/hangcheck declaring the gpu dead for a second time. A
2322 * quick check for that is good enough: schedule_work ensures the
2323 * correct ordering between hang detection and this work item, and since
2324 * the reset in-progress bit is only ever set by code outside of this
2325 * work we don't need to worry about any other races.
2327 if (i915_reset_in_progress(error
) && !i915_terminally_wedged(error
)) {
2328 DRM_DEBUG_DRIVER("resetting chip\n");
2329 kobject_uevent_env(&dev
->primary
->kdev
->kobj
, KOBJ_CHANGE
,
2333 * In most cases it's guaranteed that we get here with an RPM
2334 * reference held, for example because there is a pending GPU
2335 * request that won't finish until the reset is done. This
2336 * isn't the case at least when we get here by doing a
2337 * simulated reset via debugs, so get an RPM reference.
2339 intel_runtime_pm_get(dev_priv
);
2341 * All state reset _must_ be completed before we update the
2342 * reset counter, for otherwise waiters might miss the reset
2343 * pending state and not properly drop locks, resulting in
2344 * deadlocks with the reset work.
2346 ret
= i915_reset(dev
);
2348 intel_display_handle_reset(dev
);
2350 intel_runtime_pm_put(dev_priv
);
2354 * After all the gem state is reset, increment the reset
2355 * counter and wake up everyone waiting for the reset to
2358 * Since unlock operations are a one-sided barrier only,
2359 * we need to insert a barrier here to order any seqno
2361 * the counter increment.
2363 smp_mb__before_atomic_inc();
2364 atomic_inc(&dev_priv
->gpu_error
.reset_counter
);
2366 kobject_uevent_env(&dev
->primary
->kdev
->kobj
,
2367 KOBJ_CHANGE
, reset_done_event
);
2369 atomic_set_mask(I915_WEDGED
, &error
->reset_counter
);
2373 * Note: The wake_up also serves as a memory barrier so that
2374 * waiters see the update value of the reset counter atomic_t.
2376 i915_error_wake_up(dev_priv
, true);
2380 static void i915_report_and_clear_eir(struct drm_device
*dev
)
2382 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2383 uint32_t instdone
[I915_NUM_INSTDONE_REG
];
2384 u32 eir
= I915_READ(EIR
);
2390 pr_err("render error detected, EIR: 0x%08x\n", eir
);
2392 i915_get_extra_instdone(dev
, instdone
);
2395 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
2396 u32 ipeir
= I915_READ(IPEIR_I965
);
2398 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
2399 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
2400 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
2401 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
2402 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
2403 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
2404 I915_WRITE(IPEIR_I965
, ipeir
);
2405 POSTING_READ(IPEIR_I965
);
2407 if (eir
& GM45_ERROR_PAGE_TABLE
) {
2408 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
2409 pr_err("page table error\n");
2410 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
2411 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2412 POSTING_READ(PGTBL_ER
);
2416 if (!IS_GEN2(dev
)) {
2417 if (eir
& I915_ERROR_PAGE_TABLE
) {
2418 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
2419 pr_err("page table error\n");
2420 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
2421 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2422 POSTING_READ(PGTBL_ER
);
2426 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
2427 pr_err("memory refresh error:\n");
2429 pr_err("pipe %c stat: 0x%08x\n",
2430 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
2431 /* pipestat has already been acked */
2433 if (eir
& I915_ERROR_INSTRUCTION
) {
2434 pr_err("instruction error\n");
2435 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
2436 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
2437 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
2438 if (INTEL_INFO(dev
)->gen
< 4) {
2439 u32 ipeir
= I915_READ(IPEIR
);
2441 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
2442 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
2443 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
2444 I915_WRITE(IPEIR
, ipeir
);
2445 POSTING_READ(IPEIR
);
2447 u32 ipeir
= I915_READ(IPEIR_I965
);
2449 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
2450 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
2451 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
2452 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
2453 I915_WRITE(IPEIR_I965
, ipeir
);
2454 POSTING_READ(IPEIR_I965
);
2458 I915_WRITE(EIR
, eir
);
2460 eir
= I915_READ(EIR
);
2463 * some errors might have become stuck,
2466 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
2467 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
2468 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2473 * i915_handle_error - handle an error interrupt
2476 * Do some basic checking of regsiter state at error interrupt time and
2477 * dump it to the syslog. Also call i915_capture_error_state() to make
2478 * sure we get a record and make it available in debugfs. Fire a uevent
2479 * so userspace knows something bad happened (should trigger collection
2480 * of a ring dump etc.).
2482 void i915_handle_error(struct drm_device
*dev
, bool wedged
,
2483 const char *fmt
, ...)
2485 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2489 va_start(args
, fmt
);
2490 vscnprintf(error_msg
, sizeof(error_msg
), fmt
, args
);
2493 i915_capture_error_state(dev
, wedged
, error_msg
);
2494 i915_report_and_clear_eir(dev
);
2497 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG
,
2498 &dev_priv
->gpu_error
.reset_counter
);
2501 * Wakeup waiting processes so that the reset work function
2502 * i915_error_work_func doesn't deadlock trying to grab various
2503 * locks. By bumping the reset counter first, the woken
2504 * processes will see a reset in progress and back off,
2505 * releasing their locks and then wait for the reset completion.
2506 * We must do this for _all_ gpu waiters that might hold locks
2507 * that the reset work needs to acquire.
2509 * Note: The wake_up serves as the required memory barrier to
2510 * ensure that the waiters see the updated value of the reset
2513 i915_error_wake_up(dev_priv
, false);
2517 * Our reset work can grab modeset locks (since it needs to reset the
2518 * state of outstanding pagelips). Hence it must not be run on our own
2519 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2520 * code will deadlock.
2522 schedule_work(&dev_priv
->gpu_error
.work
);
2525 static void __always_unused
i915_pageflip_stall_check(struct drm_device
*dev
, int pipe
)
2527 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2528 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
2529 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2530 struct drm_i915_gem_object
*obj
;
2531 struct intel_unpin_work
*work
;
2532 unsigned long flags
;
2533 bool stall_detected
;
2535 /* Ignore early vblank irqs */
2536 if (intel_crtc
== NULL
)
2539 spin_lock_irqsave(&dev
->event_lock
, flags
);
2540 work
= intel_crtc
->unpin_work
;
2543 atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
||
2544 !work
->enable_stall_check
) {
2545 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2546 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2550 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2551 obj
= work
->pending_flip_obj
;
2552 if (INTEL_INFO(dev
)->gen
>= 4) {
2553 int dspsurf
= DSPSURF(intel_crtc
->plane
);
2554 stall_detected
= I915_HI_DISPBASE(I915_READ(dspsurf
)) ==
2555 i915_gem_obj_ggtt_offset(obj
);
2557 int dspaddr
= DSPADDR(intel_crtc
->plane
);
2558 stall_detected
= I915_READ(dspaddr
) == (i915_gem_obj_ggtt_offset(obj
) +
2559 crtc
->y
* crtc
->primary
->fb
->pitches
[0] +
2560 crtc
->x
* crtc
->primary
->fb
->bits_per_pixel
/8);
2563 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2565 if (stall_detected
) {
2566 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2567 intel_prepare_page_flip(dev
, intel_crtc
->plane
);
2571 /* Called from drm generic code, passed 'crtc' which
2572 * we use as a pipe index
2574 static int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
2576 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2577 unsigned long irqflags
;
2579 if (!i915_pipe_enabled(dev
, pipe
))
2582 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2583 if (INTEL_INFO(dev
)->gen
>= 4)
2584 i915_enable_pipestat(dev_priv
, pipe
,
2585 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2587 i915_enable_pipestat(dev_priv
, pipe
,
2588 PIPE_VBLANK_INTERRUPT_STATUS
);
2590 /* maintain vblank delivery even in deep C-states */
2591 if (INTEL_INFO(dev
)->gen
== 3)
2592 I915_WRITE(INSTPM
, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS
));
2593 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2598 static int ironlake_enable_vblank(struct drm_device
*dev
, int pipe
)
2600 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2601 unsigned long irqflags
;
2602 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
2603 DE_PIPE_VBLANK(pipe
);
2605 if (!i915_pipe_enabled(dev
, pipe
))
2608 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2609 ironlake_enable_display_irq(dev_priv
, bit
);
2610 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2615 static int valleyview_enable_vblank(struct drm_device
*dev
, int pipe
)
2617 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2618 unsigned long irqflags
;
2620 if (!i915_pipe_enabled(dev
, pipe
))
2623 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2624 i915_enable_pipestat(dev_priv
, pipe
,
2625 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2626 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2631 static int gen8_enable_vblank(struct drm_device
*dev
, int pipe
)
2633 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2634 unsigned long irqflags
;
2636 if (!i915_pipe_enabled(dev
, pipe
))
2639 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2640 dev_priv
->de_irq_mask
[pipe
] &= ~GEN8_PIPE_VBLANK
;
2641 I915_WRITE(GEN8_DE_PIPE_IMR(pipe
), dev_priv
->de_irq_mask
[pipe
]);
2642 POSTING_READ(GEN8_DE_PIPE_IMR(pipe
));
2643 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2647 /* Called from drm generic code, passed 'crtc' which
2648 * we use as a pipe index
2650 static void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
2652 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2653 unsigned long irqflags
;
2655 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2656 if (INTEL_INFO(dev
)->gen
== 3)
2657 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS
));
2659 i915_disable_pipestat(dev_priv
, pipe
,
2660 PIPE_VBLANK_INTERRUPT_STATUS
|
2661 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2662 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2665 static void ironlake_disable_vblank(struct drm_device
*dev
, int pipe
)
2667 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2668 unsigned long irqflags
;
2669 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
2670 DE_PIPE_VBLANK(pipe
);
2672 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2673 ironlake_disable_display_irq(dev_priv
, bit
);
2674 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2677 static void valleyview_disable_vblank(struct drm_device
*dev
, int pipe
)
2679 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2680 unsigned long irqflags
;
2682 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2683 i915_disable_pipestat(dev_priv
, pipe
,
2684 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2685 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2688 static void gen8_disable_vblank(struct drm_device
*dev
, int pipe
)
2690 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2691 unsigned long irqflags
;
2693 if (!i915_pipe_enabled(dev
, pipe
))
2696 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2697 dev_priv
->de_irq_mask
[pipe
] |= GEN8_PIPE_VBLANK
;
2698 I915_WRITE(GEN8_DE_PIPE_IMR(pipe
), dev_priv
->de_irq_mask
[pipe
]);
2699 POSTING_READ(GEN8_DE_PIPE_IMR(pipe
));
2700 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2704 ring_last_seqno(struct intel_ring_buffer
*ring
)
2706 return list_entry(ring
->request_list
.prev
,
2707 struct drm_i915_gem_request
, list
)->seqno
;
2711 ring_idle(struct intel_ring_buffer
*ring
, u32 seqno
)
2713 return (list_empty(&ring
->request_list
) ||
2714 i915_seqno_passed(seqno
, ring_last_seqno(ring
)));
2718 ipehr_is_semaphore_wait(struct drm_device
*dev
, u32 ipehr
)
2720 if (INTEL_INFO(dev
)->gen
>= 8) {
2722 * FIXME: gen8 semaphore support - currently we don't emit
2723 * semaphores on bdw anyway, but this needs to be addressed when
2724 * we merge that code.
2728 ipehr
&= ~MI_SEMAPHORE_SYNC_MASK
;
2729 return ipehr
== (MI_SEMAPHORE_MBOX
| MI_SEMAPHORE_COMPARE
|
2730 MI_SEMAPHORE_REGISTER
);
2734 static struct intel_ring_buffer
*
2735 semaphore_wait_to_signaller_ring(struct intel_ring_buffer
*ring
, u32 ipehr
)
2737 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2738 struct intel_ring_buffer
*signaller
;
2741 if (INTEL_INFO(dev_priv
->dev
)->gen
>= 8) {
2743 * FIXME: gen8 semaphore support - currently we don't emit
2744 * semaphores on bdw anyway, but this needs to be addressed when
2745 * we merge that code.
2749 u32 sync_bits
= ipehr
& MI_SEMAPHORE_SYNC_MASK
;
2751 for_each_ring(signaller
, dev_priv
, i
) {
2752 if(ring
== signaller
)
2755 if (sync_bits
== signaller
->semaphore
.mbox
.wait
[ring
->id
])
2760 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x\n",
2766 static struct intel_ring_buffer
*
2767 semaphore_waits_for(struct intel_ring_buffer
*ring
, u32
*seqno
)
2769 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2770 u32 cmd
, ipehr
, head
;
2773 ipehr
= I915_READ(RING_IPEHR(ring
->mmio_base
));
2774 if (!ipehr_is_semaphore_wait(ring
->dev
, ipehr
))
2778 * HEAD is likely pointing to the dword after the actual command,
2779 * so scan backwards until we find the MBOX. But limit it to just 3
2780 * dwords. Note that we don't care about ACTHD here since that might
2781 * point at at batch, and semaphores are always emitted into the
2782 * ringbuffer itself.
2784 head
= I915_READ_HEAD(ring
) & HEAD_ADDR
;
2786 for (i
= 4; i
; --i
) {
2788 * Be paranoid and presume the hw has gone off into the wild -
2789 * our ring is smaller than what the hardware (and hence
2790 * HEAD_ADDR) allows. Also handles wrap-around.
2792 head
&= ring
->size
- 1;
2794 /* This here seems to blow up */
2795 cmd
= ioread32(ring
->virtual_start
+ head
);
2805 *seqno
= ioread32(ring
->virtual_start
+ head
+ 4) + 1;
2806 return semaphore_wait_to_signaller_ring(ring
, ipehr
);
2809 static int semaphore_passed(struct intel_ring_buffer
*ring
)
2811 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2812 struct intel_ring_buffer
*signaller
;
2815 ring
->hangcheck
.deadlock
= true;
2817 signaller
= semaphore_waits_for(ring
, &seqno
);
2818 if (signaller
== NULL
|| signaller
->hangcheck
.deadlock
)
2821 /* cursory check for an unkickable deadlock */
2822 ctl
= I915_READ_CTL(signaller
);
2823 if (ctl
& RING_WAIT_SEMAPHORE
&& semaphore_passed(signaller
) < 0)
2826 return i915_seqno_passed(signaller
->get_seqno(signaller
, false), seqno
);
2829 static void semaphore_clear_deadlocks(struct drm_i915_private
*dev_priv
)
2831 struct intel_ring_buffer
*ring
;
2834 for_each_ring(ring
, dev_priv
, i
)
2835 ring
->hangcheck
.deadlock
= false;
2838 static enum intel_ring_hangcheck_action
2839 ring_stuck(struct intel_ring_buffer
*ring
, u64 acthd
)
2841 struct drm_device
*dev
= ring
->dev
;
2842 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2845 if (ring
->hangcheck
.acthd
!= acthd
)
2846 return HANGCHECK_ACTIVE
;
2849 return HANGCHECK_HUNG
;
2851 /* Is the chip hanging on a WAIT_FOR_EVENT?
2852 * If so we can simply poke the RB_WAIT bit
2853 * and break the hang. This should work on
2854 * all but the second generation chipsets.
2856 tmp
= I915_READ_CTL(ring
);
2857 if (tmp
& RING_WAIT
) {
2858 i915_handle_error(dev
, false,
2859 "Kicking stuck wait on %s",
2861 I915_WRITE_CTL(ring
, tmp
);
2862 return HANGCHECK_KICK
;
2865 if (INTEL_INFO(dev
)->gen
>= 6 && tmp
& RING_WAIT_SEMAPHORE
) {
2866 switch (semaphore_passed(ring
)) {
2868 return HANGCHECK_HUNG
;
2870 i915_handle_error(dev
, false,
2871 "Kicking stuck semaphore on %s",
2873 I915_WRITE_CTL(ring
, tmp
);
2874 return HANGCHECK_KICK
;
2876 return HANGCHECK_WAIT
;
2880 return HANGCHECK_HUNG
;
2884 * This is called when the chip hasn't reported back with completed
2885 * batchbuffers in a long time. We keep track per ring seqno progress and
2886 * if there are no progress, hangcheck score for that ring is increased.
2887 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2888 * we kick the ring. If we see no progress on three subsequent calls
2889 * we assume chip is wedged and try to fix it by resetting the chip.
2891 static void i915_hangcheck_elapsed(unsigned long data
)
2893 struct drm_device
*dev
= (struct drm_device
*)data
;
2894 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2895 struct intel_ring_buffer
*ring
;
2897 int busy_count
= 0, rings_hung
= 0;
2898 bool stuck
[I915_NUM_RINGS
] = { 0 };
2903 if (!i915
.enable_hangcheck
)
2906 for_each_ring(ring
, dev_priv
, i
) {
2911 semaphore_clear_deadlocks(dev_priv
);
2913 seqno
= ring
->get_seqno(ring
, false);
2914 acthd
= intel_ring_get_active_head(ring
);
2916 if (ring
->hangcheck
.seqno
== seqno
) {
2917 if (ring_idle(ring
, seqno
)) {
2918 ring
->hangcheck
.action
= HANGCHECK_IDLE
;
2920 if (waitqueue_active(&ring
->irq_queue
)) {
2921 /* Issue a wake-up to catch stuck h/w. */
2922 if (!test_and_set_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
)) {
2923 if (!(dev_priv
->gpu_error
.test_irq_rings
& intel_ring_flag(ring
)))
2924 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2927 DRM_INFO("Fake missed irq on %s\n",
2929 wake_up_all(&ring
->irq_queue
);
2931 /* Safeguard against driver failure */
2932 ring
->hangcheck
.score
+= BUSY
;
2936 /* We always increment the hangcheck score
2937 * if the ring is busy and still processing
2938 * the same request, so that no single request
2939 * can run indefinitely (such as a chain of
2940 * batches). The only time we do not increment
2941 * the hangcheck score on this ring, if this
2942 * ring is in a legitimate wait for another
2943 * ring. In that case the waiting ring is a
2944 * victim and we want to be sure we catch the
2945 * right culprit. Then every time we do kick
2946 * the ring, add a small increment to the
2947 * score so that we can catch a batch that is
2948 * being repeatedly kicked and so responsible
2949 * for stalling the machine.
2951 ring
->hangcheck
.action
= ring_stuck(ring
,
2954 switch (ring
->hangcheck
.action
) {
2955 case HANGCHECK_IDLE
:
2956 case HANGCHECK_WAIT
:
2958 case HANGCHECK_ACTIVE
:
2959 ring
->hangcheck
.score
+= BUSY
;
2961 case HANGCHECK_KICK
:
2962 ring
->hangcheck
.score
+= KICK
;
2964 case HANGCHECK_HUNG
:
2965 ring
->hangcheck
.score
+= HUNG
;
2971 ring
->hangcheck
.action
= HANGCHECK_ACTIVE
;
2973 /* Gradually reduce the count so that we catch DoS
2974 * attempts across multiple batches.
2976 if (ring
->hangcheck
.score
> 0)
2977 ring
->hangcheck
.score
--;
2980 ring
->hangcheck
.seqno
= seqno
;
2981 ring
->hangcheck
.acthd
= acthd
;
2985 for_each_ring(ring
, dev_priv
, i
) {
2986 if (ring
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
) {
2987 DRM_INFO("%s on %s\n",
2988 stuck
[i
] ? "stuck" : "no progress",
2995 return i915_handle_error(dev
, true, "Ring hung");
2998 /* Reset timer case chip hangs without another request
3000 i915_queue_hangcheck(dev
);
3003 void i915_queue_hangcheck(struct drm_device
*dev
)
3005 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3006 if (!i915
.enable_hangcheck
)
3009 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
3010 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
3013 static void ibx_irq_reset(struct drm_device
*dev
)
3015 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3017 if (HAS_PCH_NOP(dev
))
3020 GEN5_IRQ_RESET(SDE
);
3022 if (HAS_PCH_CPT(dev
) || HAS_PCH_LPT(dev
))
3023 I915_WRITE(SERR_INT
, 0xffffffff);
3027 * SDEIER is also touched by the interrupt handler to work around missed PCH
3028 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3029 * instead we unconditionally enable all PCH interrupt sources here, but then
3030 * only unmask them as needed with SDEIMR.
3032 * This function needs to be called before interrupts are enabled.
3034 static void ibx_irq_pre_postinstall(struct drm_device
*dev
)
3036 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3038 if (HAS_PCH_NOP(dev
))
3041 WARN_ON(I915_READ(SDEIER
) != 0);
3042 I915_WRITE(SDEIER
, 0xffffffff);
3043 POSTING_READ(SDEIER
);
3046 static void gen5_gt_irq_reset(struct drm_device
*dev
)
3048 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3051 if (INTEL_INFO(dev
)->gen
>= 6)
3052 GEN5_IRQ_RESET(GEN6_PM
);
3057 static void ironlake_irq_reset(struct drm_device
*dev
)
3059 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3061 I915_WRITE(HWSTAM
, 0xffffffff);
3065 I915_WRITE(GEN7_ERR_INT
, 0xffffffff);
3067 gen5_gt_irq_reset(dev
);
3072 static void ironlake_irq_preinstall(struct drm_device
*dev
)
3074 ironlake_irq_reset(dev
);
3077 static void valleyview_irq_preinstall(struct drm_device
*dev
)
3079 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3083 I915_WRITE(VLV_IMR
, 0);
3084 I915_WRITE(RING_IMR(RENDER_RING_BASE
), 0);
3085 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE
), 0);
3086 I915_WRITE(RING_IMR(BLT_RING_BASE
), 0);
3089 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
3090 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
3092 gen5_gt_irq_reset(dev
);
3094 I915_WRITE(DPINVGTT
, 0xff);
3096 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3097 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3099 I915_WRITE(PIPESTAT(pipe
), 0xffff);
3100 I915_WRITE(VLV_IIR
, 0xffffffff);
3101 I915_WRITE(VLV_IMR
, 0xffffffff);
3102 I915_WRITE(VLV_IER
, 0x0);
3103 POSTING_READ(VLV_IER
);
3106 static void gen8_irq_reset(struct drm_device
*dev
)
3108 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3111 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3112 POSTING_READ(GEN8_MASTER_IRQ
);
3114 GEN8_IRQ_RESET_NDX(GT
, 0);
3115 GEN8_IRQ_RESET_NDX(GT
, 1);
3116 GEN8_IRQ_RESET_NDX(GT
, 2);
3117 GEN8_IRQ_RESET_NDX(GT
, 3);
3120 GEN8_IRQ_RESET_NDX(DE_PIPE
, pipe
);
3122 GEN5_IRQ_RESET(GEN8_DE_PORT_
);
3123 GEN5_IRQ_RESET(GEN8_DE_MISC_
);
3124 GEN5_IRQ_RESET(GEN8_PCU_
);
3129 static void gen8_irq_preinstall(struct drm_device
*dev
)
3131 gen8_irq_reset(dev
);
3134 static void cherryview_irq_preinstall(struct drm_device
*dev
)
3136 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3139 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3140 POSTING_READ(GEN8_MASTER_IRQ
);
3142 GEN8_IRQ_RESET_NDX(GT
, 0);
3143 GEN8_IRQ_RESET_NDX(GT
, 1);
3144 GEN8_IRQ_RESET_NDX(GT
, 2);
3145 GEN8_IRQ_RESET_NDX(GT
, 3);
3147 GEN5_IRQ_RESET(GEN8_PCU_
);
3149 POSTING_READ(GEN8_PCU_IIR
);
3151 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK_CHV
);
3153 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3154 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3157 I915_WRITE(PIPESTAT(pipe
), 0xffff);
3159 I915_WRITE(VLV_IMR
, 0xffffffff);
3160 I915_WRITE(VLV_IER
, 0x0);
3161 I915_WRITE(VLV_IIR
, 0xffffffff);
3162 POSTING_READ(VLV_IIR
);
3165 static void ibx_hpd_irq_setup(struct drm_device
*dev
)
3167 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3168 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3169 struct intel_encoder
*intel_encoder
;
3170 u32 hotplug_irqs
, hotplug
, enabled_irqs
= 0;
3172 if (HAS_PCH_IBX(dev
)) {
3173 hotplug_irqs
= SDE_HOTPLUG_MASK
;
3174 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
3175 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
3176 enabled_irqs
|= hpd_ibx
[intel_encoder
->hpd_pin
];
3178 hotplug_irqs
= SDE_HOTPLUG_MASK_CPT
;
3179 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
3180 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
3181 enabled_irqs
|= hpd_cpt
[intel_encoder
->hpd_pin
];
3184 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
3187 * Enable digital hotplug on the PCH, and configure the DP short pulse
3188 * duration to 2ms (which is the minimum in the Display Port spec)
3190 * This register is the same on all known PCH chips.
3192 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
3193 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
3194 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
3195 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
3196 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
3197 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
3200 static void ibx_irq_postinstall(struct drm_device
*dev
)
3202 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3205 if (HAS_PCH_NOP(dev
))
3208 if (HAS_PCH_IBX(dev
))
3209 mask
= SDE_GMBUS
| SDE_AUX_MASK
| SDE_POISON
;
3211 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
;
3213 GEN5_ASSERT_IIR_IS_ZERO(SDEIIR
);
3214 I915_WRITE(SDEIMR
, ~mask
);
3217 static void gen5_gt_irq_postinstall(struct drm_device
*dev
)
3219 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3220 u32 pm_irqs
, gt_irqs
;
3222 pm_irqs
= gt_irqs
= 0;
3224 dev_priv
->gt_irq_mask
= ~0;
3225 if (HAS_L3_DPF(dev
)) {
3226 /* L3 parity interrupt is always unmasked. */
3227 dev_priv
->gt_irq_mask
= ~GT_PARITY_ERROR(dev
);
3228 gt_irqs
|= GT_PARITY_ERROR(dev
);
3231 gt_irqs
|= GT_RENDER_USER_INTERRUPT
;
3233 gt_irqs
|= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
|
3234 ILK_BSD_USER_INTERRUPT
;
3236 gt_irqs
|= GT_BLT_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
;
3239 GEN5_IRQ_INIT(GT
, dev_priv
->gt_irq_mask
, gt_irqs
);
3241 if (INTEL_INFO(dev
)->gen
>= 6) {
3242 pm_irqs
|= dev_priv
->pm_rps_events
;
3245 pm_irqs
|= PM_VEBOX_USER_INTERRUPT
;
3247 dev_priv
->pm_irq_mask
= 0xffffffff;
3248 GEN5_IRQ_INIT(GEN6_PM
, dev_priv
->pm_irq_mask
, pm_irqs
);
3252 static int ironlake_irq_postinstall(struct drm_device
*dev
)
3254 unsigned long irqflags
;
3255 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3256 u32 display_mask
, extra_mask
;
3258 if (INTEL_INFO(dev
)->gen
>= 7) {
3259 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
|
3260 DE_PCH_EVENT_IVB
| DE_PLANEC_FLIP_DONE_IVB
|
3261 DE_PLANEB_FLIP_DONE_IVB
|
3262 DE_PLANEA_FLIP_DONE_IVB
| DE_AUX_CHANNEL_A_IVB
);
3263 extra_mask
= (DE_PIPEC_VBLANK_IVB
| DE_PIPEB_VBLANK_IVB
|
3264 DE_PIPEA_VBLANK_IVB
| DE_ERR_INT_IVB
);
3266 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
3267 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
|
3269 DE_PIPEB_CRC_DONE
| DE_PIPEA_CRC_DONE
|
3271 extra_mask
= DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
| DE_PCU_EVENT
|
3272 DE_PIPEB_FIFO_UNDERRUN
| DE_PIPEA_FIFO_UNDERRUN
;
3275 dev_priv
->irq_mask
= ~display_mask
;
3277 I915_WRITE(HWSTAM
, 0xeffe);
3279 ibx_irq_pre_postinstall(dev
);
3281 GEN5_IRQ_INIT(DE
, dev_priv
->irq_mask
, display_mask
| extra_mask
);
3283 gen5_gt_irq_postinstall(dev
);
3285 ibx_irq_postinstall(dev
);
3287 if (IS_IRONLAKE_M(dev
)) {
3288 /* Enable PCU event interrupts
3290 * spinlocking not required here for correctness since interrupt
3291 * setup is guaranteed to run in single-threaded context. But we
3292 * need it to make the assert_spin_locked happy. */
3293 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3294 ironlake_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
3295 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3301 static void valleyview_display_irqs_install(struct drm_i915_private
*dev_priv
)
3306 pipestat_mask
= PIPESTAT_INT_STATUS_MASK
|
3307 PIPE_FIFO_UNDERRUN_STATUS
;
3309 I915_WRITE(PIPESTAT(PIPE_A
), pipestat_mask
);
3310 I915_WRITE(PIPESTAT(PIPE_B
), pipestat_mask
);
3311 POSTING_READ(PIPESTAT(PIPE_A
));
3313 pipestat_mask
= PLANE_FLIP_DONE_INT_STATUS_VLV
|
3314 PIPE_CRC_DONE_INTERRUPT_STATUS
;
3316 i915_enable_pipestat(dev_priv
, PIPE_A
, pipestat_mask
|
3317 PIPE_GMBUS_INTERRUPT_STATUS
);
3318 i915_enable_pipestat(dev_priv
, PIPE_B
, pipestat_mask
);
3320 iir_mask
= I915_DISPLAY_PORT_INTERRUPT
|
3321 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3322 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
3323 dev_priv
->irq_mask
&= ~iir_mask
;
3325 I915_WRITE(VLV_IIR
, iir_mask
);
3326 I915_WRITE(VLV_IIR
, iir_mask
);
3327 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
3328 I915_WRITE(VLV_IER
, ~dev_priv
->irq_mask
);
3329 POSTING_READ(VLV_IER
);
3332 static void valleyview_display_irqs_uninstall(struct drm_i915_private
*dev_priv
)
3337 iir_mask
= I915_DISPLAY_PORT_INTERRUPT
|
3338 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3339 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
3341 dev_priv
->irq_mask
|= iir_mask
;
3342 I915_WRITE(VLV_IER
, ~dev_priv
->irq_mask
);
3343 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
3344 I915_WRITE(VLV_IIR
, iir_mask
);
3345 I915_WRITE(VLV_IIR
, iir_mask
);
3346 POSTING_READ(VLV_IIR
);
3348 pipestat_mask
= PLANE_FLIP_DONE_INT_STATUS_VLV
|
3349 PIPE_CRC_DONE_INTERRUPT_STATUS
;
3351 i915_disable_pipestat(dev_priv
, PIPE_A
, pipestat_mask
|
3352 PIPE_GMBUS_INTERRUPT_STATUS
);
3353 i915_disable_pipestat(dev_priv
, PIPE_B
, pipestat_mask
);
3355 pipestat_mask
= PIPESTAT_INT_STATUS_MASK
|
3356 PIPE_FIFO_UNDERRUN_STATUS
;
3357 I915_WRITE(PIPESTAT(PIPE_A
), pipestat_mask
);
3358 I915_WRITE(PIPESTAT(PIPE_B
), pipestat_mask
);
3359 POSTING_READ(PIPESTAT(PIPE_A
));
3362 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
)
3364 assert_spin_locked(&dev_priv
->irq_lock
);
3366 if (dev_priv
->display_irqs_enabled
)
3369 dev_priv
->display_irqs_enabled
= true;
3371 if (dev_priv
->dev
->irq_enabled
)
3372 valleyview_display_irqs_install(dev_priv
);
3375 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
)
3377 assert_spin_locked(&dev_priv
->irq_lock
);
3379 if (!dev_priv
->display_irqs_enabled
)
3382 dev_priv
->display_irqs_enabled
= false;
3384 if (dev_priv
->dev
->irq_enabled
)
3385 valleyview_display_irqs_uninstall(dev_priv
);
3388 static int valleyview_irq_postinstall(struct drm_device
*dev
)
3390 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3391 unsigned long irqflags
;
3393 dev_priv
->irq_mask
= ~0;
3395 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3396 POSTING_READ(PORT_HOTPLUG_EN
);
3398 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
3399 I915_WRITE(VLV_IER
, ~dev_priv
->irq_mask
);
3400 I915_WRITE(VLV_IIR
, 0xffffffff);
3401 POSTING_READ(VLV_IER
);
3403 /* Interrupt setup is already guaranteed to be single-threaded, this is
3404 * just to make the assert_spin_locked check happy. */
3405 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3406 if (dev_priv
->display_irqs_enabled
)
3407 valleyview_display_irqs_install(dev_priv
);
3408 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3410 I915_WRITE(VLV_IIR
, 0xffffffff);
3411 I915_WRITE(VLV_IIR
, 0xffffffff);
3413 gen5_gt_irq_postinstall(dev
);
3415 /* ack & enable invalid PTE error interrupts */
3416 #if 0 /* FIXME: add support to irq handler for checking these bits */
3417 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
3418 I915_WRITE(DPINVGTT
, DPINVGTT_EN_MASK
);
3421 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
3426 static void gen8_gt_irq_postinstall(struct drm_i915_private
*dev_priv
)
3430 /* These are interrupts we'll toggle with the ring mask register */
3431 uint32_t gt_interrupts
[] = {
3432 GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
3433 GT_RENDER_L3_PARITY_ERROR_INTERRUPT
|
3434 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
,
3435 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
|
3436 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
,
3438 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
3441 for (i
= 0; i
< ARRAY_SIZE(gt_interrupts
); i
++)
3442 GEN8_IRQ_INIT_NDX(GT
, i
, ~gt_interrupts
[i
], gt_interrupts
[i
]);
3444 dev_priv
->pm_irq_mask
= 0xffffffff;
3447 static void gen8_de_irq_postinstall(struct drm_i915_private
*dev_priv
)
3449 struct drm_device
*dev
= dev_priv
->dev
;
3450 uint32_t de_pipe_masked
= GEN8_PIPE_PRIMARY_FLIP_DONE
|
3451 GEN8_PIPE_CDCLK_CRC_DONE
|
3452 GEN8_DE_PIPE_IRQ_FAULT_ERRORS
;
3453 uint32_t de_pipe_enables
= de_pipe_masked
| GEN8_PIPE_VBLANK
|
3454 GEN8_PIPE_FIFO_UNDERRUN
;
3456 dev_priv
->de_irq_mask
[PIPE_A
] = ~de_pipe_masked
;
3457 dev_priv
->de_irq_mask
[PIPE_B
] = ~de_pipe_masked
;
3458 dev_priv
->de_irq_mask
[PIPE_C
] = ~de_pipe_masked
;
3461 GEN8_IRQ_INIT_NDX(DE_PIPE
, pipe
, dev_priv
->de_irq_mask
[pipe
],
3464 GEN5_IRQ_INIT(GEN8_DE_PORT_
, ~GEN8_AUX_CHANNEL_A
, GEN8_AUX_CHANNEL_A
);
3467 static int gen8_irq_postinstall(struct drm_device
*dev
)
3469 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3471 ibx_irq_pre_postinstall(dev
);
3473 gen8_gt_irq_postinstall(dev_priv
);
3474 gen8_de_irq_postinstall(dev_priv
);
3476 ibx_irq_postinstall(dev
);
3478 I915_WRITE(GEN8_MASTER_IRQ
, DE_MASTER_IRQ_CONTROL
);
3479 POSTING_READ(GEN8_MASTER_IRQ
);
3484 static int cherryview_irq_postinstall(struct drm_device
*dev
)
3486 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3487 u32 enable_mask
= I915_DISPLAY_PORT_INTERRUPT
|
3488 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3489 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
3490 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3491 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
|
3492 I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
|
3493 I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT
;
3494 u32 pipestat_enable
= PLANE_FLIP_DONE_INT_EN_VLV
;
3495 unsigned long irqflags
;
3499 * Leave vblank interrupts masked initially. enable/disable will
3500 * toggle them based on usage.
3502 dev_priv
->irq_mask
= ~enable_mask
|
3503 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
3504 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
|
3505 I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT
;
3508 I915_WRITE(PIPESTAT(pipe
), 0xffff);
3510 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3511 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
3513 i915_enable_pipestat(dev_priv
, pipe
, pipestat_enable
);
3514 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3516 I915_WRITE(VLV_IIR
, 0xffffffff);
3517 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
3518 I915_WRITE(VLV_IER
, enable_mask
);
3520 gen8_gt_irq_postinstall(dev_priv
);
3522 I915_WRITE(GEN8_MASTER_IRQ
, MASTER_INTERRUPT_ENABLE
);
3523 POSTING_READ(GEN8_MASTER_IRQ
);
3528 static void gen8_irq_uninstall(struct drm_device
*dev
)
3530 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3535 intel_hpd_irq_uninstall(dev_priv
);
3537 gen8_irq_reset(dev
);
3540 static void valleyview_irq_uninstall(struct drm_device
*dev
)
3542 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3543 unsigned long irqflags
;
3549 I915_WRITE(VLV_MASTER_IER
, 0);
3551 intel_hpd_irq_uninstall(dev_priv
);
3554 I915_WRITE(PIPESTAT(pipe
), 0xffff);
3556 I915_WRITE(HWSTAM
, 0xffffffff);
3557 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3558 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3560 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3561 if (dev_priv
->display_irqs_enabled
)
3562 valleyview_display_irqs_uninstall(dev_priv
);
3563 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3565 dev_priv
->irq_mask
= 0;
3567 I915_WRITE(VLV_IIR
, 0xffffffff);
3568 I915_WRITE(VLV_IMR
, 0xffffffff);
3569 I915_WRITE(VLV_IER
, 0x0);
3570 POSTING_READ(VLV_IER
);
3573 static void cherryview_irq_uninstall(struct drm_device
*dev
)
3575 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3581 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3582 POSTING_READ(GEN8_MASTER_IRQ
);
3584 #define GEN8_IRQ_FINI_NDX(type, which) \
3586 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
3587 I915_WRITE(GEN8_##type##_IER(which), 0); \
3588 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
3589 POSTING_READ(GEN8_##type##_IIR(which)); \
3590 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
3593 #define GEN8_IRQ_FINI(type) \
3595 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
3596 I915_WRITE(GEN8_##type##_IER, 0); \
3597 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
3598 POSTING_READ(GEN8_##type##_IIR); \
3599 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
3602 GEN8_IRQ_FINI_NDX(GT
, 0);
3603 GEN8_IRQ_FINI_NDX(GT
, 1);
3604 GEN8_IRQ_FINI_NDX(GT
, 2);
3605 GEN8_IRQ_FINI_NDX(GT
, 3);
3609 #undef GEN8_IRQ_FINI
3610 #undef GEN8_IRQ_FINI_NDX
3612 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3613 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3616 I915_WRITE(PIPESTAT(pipe
), 0xffff);
3618 I915_WRITE(VLV_IMR
, 0xffffffff);
3619 I915_WRITE(VLV_IER
, 0x0);
3620 I915_WRITE(VLV_IIR
, 0xffffffff);
3621 POSTING_READ(VLV_IIR
);
3624 static void ironlake_irq_uninstall(struct drm_device
*dev
)
3626 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3631 intel_hpd_irq_uninstall(dev_priv
);
3633 ironlake_irq_reset(dev
);
3636 static void i8xx_irq_preinstall(struct drm_device
* dev
)
3638 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3642 I915_WRITE(PIPESTAT(pipe
), 0);
3643 I915_WRITE16(IMR
, 0xffff);
3644 I915_WRITE16(IER
, 0x0);
3645 POSTING_READ16(IER
);
3648 static int i8xx_irq_postinstall(struct drm_device
*dev
)
3650 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3651 unsigned long irqflags
;
3654 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
3656 /* Unmask the interrupts that we always want on. */
3657 dev_priv
->irq_mask
=
3658 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3659 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3660 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3661 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
3662 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
3663 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
3666 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3667 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3668 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
3669 I915_USER_INTERRUPT
);
3670 POSTING_READ16(IER
);
3672 /* Interrupt setup is already guaranteed to be single-threaded, this is
3673 * just to make the assert_spin_locked check happy. */
3674 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3675 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3676 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3677 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3683 * Returns true when a page flip has completed.
3685 static bool i8xx_handle_vblank(struct drm_device
*dev
,
3686 int plane
, int pipe
, u32 iir
)
3688 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3689 u16 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
3691 if (!intel_pipe_handle_vblank(dev
, pipe
))
3694 if ((iir
& flip_pending
) == 0)
3697 intel_prepare_page_flip(dev
, plane
);
3699 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3700 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3701 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3702 * the flip is completed (no longer pending). Since this doesn't raise
3703 * an interrupt per se, we watch for the change at vblank.
3705 if (I915_READ16(ISR
) & flip_pending
)
3708 intel_finish_page_flip(dev
, pipe
);
3713 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
3715 struct drm_device
*dev
= arg
;
3716 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3719 unsigned long irqflags
;
3722 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3723 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3725 iir
= I915_READ16(IIR
);
3729 while (iir
& ~flip_mask
) {
3730 /* Can't rely on pipestat interrupt bit in iir as it might
3731 * have been cleared after the pipestat interrupt was received.
3732 * It doesn't set the bit in iir again, but it still produces
3733 * interrupts (for non-MSI).
3735 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3736 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3737 i915_handle_error(dev
, false,
3738 "Command parser error, iir 0x%08x",
3741 for_each_pipe(pipe
) {
3742 int reg
= PIPESTAT(pipe
);
3743 pipe_stats
[pipe
] = I915_READ(reg
);
3746 * Clear the PIPE*STAT regs before the IIR
3748 if (pipe_stats
[pipe
] & 0x8000ffff)
3749 I915_WRITE(reg
, pipe_stats
[pipe
]);
3751 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3753 I915_WRITE16(IIR
, iir
& ~flip_mask
);
3754 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
3756 i915_update_dri1_breadcrumb(dev
);
3758 if (iir
& I915_USER_INTERRUPT
)
3759 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
3761 for_each_pipe(pipe
) {
3766 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
3767 i8xx_handle_vblank(dev
, plane
, pipe
, iir
))
3768 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
3770 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
3771 i9xx_pipe_crc_irq_handler(dev
, pipe
);
3773 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
&&
3774 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, false))
3775 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe
));
3784 static void i8xx_irq_uninstall(struct drm_device
* dev
)
3786 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3789 for_each_pipe(pipe
) {
3790 /* Clear enable bits; then clear status bits */
3791 I915_WRITE(PIPESTAT(pipe
), 0);
3792 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
3794 I915_WRITE16(IMR
, 0xffff);
3795 I915_WRITE16(IER
, 0x0);
3796 I915_WRITE16(IIR
, I915_READ16(IIR
));
3799 static void i915_irq_preinstall(struct drm_device
* dev
)
3801 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3804 if (I915_HAS_HOTPLUG(dev
)) {
3805 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3806 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3809 I915_WRITE16(HWSTAM
, 0xeffe);
3811 I915_WRITE(PIPESTAT(pipe
), 0);
3812 I915_WRITE(IMR
, 0xffffffff);
3813 I915_WRITE(IER
, 0x0);
3817 static int i915_irq_postinstall(struct drm_device
*dev
)
3819 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3821 unsigned long irqflags
;
3823 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
3825 /* Unmask the interrupts that we always want on. */
3826 dev_priv
->irq_mask
=
3827 ~(I915_ASLE_INTERRUPT
|
3828 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3829 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3830 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3831 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
3832 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
3835 I915_ASLE_INTERRUPT
|
3836 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3837 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3838 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
3839 I915_USER_INTERRUPT
;
3841 if (I915_HAS_HOTPLUG(dev
)) {
3842 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3843 POSTING_READ(PORT_HOTPLUG_EN
);
3845 /* Enable in IER... */
3846 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
3847 /* and unmask in IMR */
3848 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
3851 I915_WRITE(IMR
, dev_priv
->irq_mask
);
3852 I915_WRITE(IER
, enable_mask
);
3855 i915_enable_asle_pipestat(dev
);
3857 /* Interrupt setup is already guaranteed to be single-threaded, this is
3858 * just to make the assert_spin_locked check happy. */
3859 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3860 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3861 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3862 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3868 * Returns true when a page flip has completed.
3870 static bool i915_handle_vblank(struct drm_device
*dev
,
3871 int plane
, int pipe
, u32 iir
)
3873 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3874 u32 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
3876 if (!intel_pipe_handle_vblank(dev
, pipe
))
3879 if ((iir
& flip_pending
) == 0)
3882 intel_prepare_page_flip(dev
, plane
);
3884 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3885 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3886 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3887 * the flip is completed (no longer pending). Since this doesn't raise
3888 * an interrupt per se, we watch for the change at vblank.
3890 if (I915_READ(ISR
) & flip_pending
)
3893 intel_finish_page_flip(dev
, pipe
);
3898 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
3900 struct drm_device
*dev
= arg
;
3901 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3902 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
3903 unsigned long irqflags
;
3905 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3906 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3907 int pipe
, ret
= IRQ_NONE
;
3909 iir
= I915_READ(IIR
);
3911 bool irq_received
= (iir
& ~flip_mask
) != 0;
3912 bool blc_event
= false;
3914 /* Can't rely on pipestat interrupt bit in iir as it might
3915 * have been cleared after the pipestat interrupt was received.
3916 * It doesn't set the bit in iir again, but it still produces
3917 * interrupts (for non-MSI).
3919 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3920 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3921 i915_handle_error(dev
, false,
3922 "Command parser error, iir 0x%08x",
3925 for_each_pipe(pipe
) {
3926 int reg
= PIPESTAT(pipe
);
3927 pipe_stats
[pipe
] = I915_READ(reg
);
3929 /* Clear the PIPE*STAT regs before the IIR */
3930 if (pipe_stats
[pipe
] & 0x8000ffff) {
3931 I915_WRITE(reg
, pipe_stats
[pipe
]);
3932 irq_received
= true;
3935 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3940 /* Consume port. Then clear IIR or we'll miss events */
3941 if (I915_HAS_HOTPLUG(dev
) &&
3942 iir
& I915_DISPLAY_PORT_INTERRUPT
)
3943 i9xx_hpd_irq_handler(dev
);
3945 I915_WRITE(IIR
, iir
& ~flip_mask
);
3946 new_iir
= I915_READ(IIR
); /* Flush posted writes */
3948 if (iir
& I915_USER_INTERRUPT
)
3949 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
3951 for_each_pipe(pipe
) {
3956 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
3957 i915_handle_vblank(dev
, plane
, pipe
, iir
))
3958 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
3960 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
3963 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
3964 i9xx_pipe_crc_irq_handler(dev
, pipe
);
3966 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
&&
3967 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, false))
3968 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe
));
3971 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
3972 intel_opregion_asle_intr(dev
);
3974 /* With MSI, interrupts are only generated when iir
3975 * transitions from zero to nonzero. If another bit got
3976 * set while we were handling the existing iir bits, then
3977 * we would never get another interrupt.
3979 * This is fine on non-MSI as well, as if we hit this path
3980 * we avoid exiting the interrupt handler only to generate
3983 * Note that for MSI this could cause a stray interrupt report
3984 * if an interrupt landed in the time between writing IIR and
3985 * the posting read. This should be rare enough to never
3986 * trigger the 99% of 100,000 interrupts test for disabling
3991 } while (iir
& ~flip_mask
);
3993 i915_update_dri1_breadcrumb(dev
);
3998 static void i915_irq_uninstall(struct drm_device
* dev
)
4000 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4003 intel_hpd_irq_uninstall(dev_priv
);
4005 if (I915_HAS_HOTPLUG(dev
)) {
4006 I915_WRITE(PORT_HOTPLUG_EN
, 0);
4007 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4010 I915_WRITE16(HWSTAM
, 0xffff);
4011 for_each_pipe(pipe
) {
4012 /* Clear enable bits; then clear status bits */
4013 I915_WRITE(PIPESTAT(pipe
), 0);
4014 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
4016 I915_WRITE(IMR
, 0xffffffff);
4017 I915_WRITE(IER
, 0x0);
4019 I915_WRITE(IIR
, I915_READ(IIR
));
4022 static void i965_irq_preinstall(struct drm_device
* dev
)
4024 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4027 I915_WRITE(PORT_HOTPLUG_EN
, 0);
4028 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4030 I915_WRITE(HWSTAM
, 0xeffe);
4032 I915_WRITE(PIPESTAT(pipe
), 0);
4033 I915_WRITE(IMR
, 0xffffffff);
4034 I915_WRITE(IER
, 0x0);
4038 static int i965_irq_postinstall(struct drm_device
*dev
)
4040 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4043 unsigned long irqflags
;
4045 /* Unmask the interrupts that we always want on. */
4046 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
4047 I915_DISPLAY_PORT_INTERRUPT
|
4048 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
4049 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
4050 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4051 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
4052 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
4054 enable_mask
= ~dev_priv
->irq_mask
;
4055 enable_mask
&= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4056 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
4057 enable_mask
|= I915_USER_INTERRUPT
;
4060 enable_mask
|= I915_BSD_USER_INTERRUPT
;
4062 /* Interrupt setup is already guaranteed to be single-threaded, this is
4063 * just to make the assert_spin_locked check happy. */
4064 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
4065 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
4066 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4067 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4068 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
4071 * Enable some error detection, note the instruction error mask
4072 * bit is reserved, so we leave it masked.
4075 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
4076 GM45_ERROR_MEM_PRIV
|
4077 GM45_ERROR_CP_PRIV
|
4078 I915_ERROR_MEMORY_REFRESH
);
4080 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
4081 I915_ERROR_MEMORY_REFRESH
);
4083 I915_WRITE(EMR
, error_mask
);
4085 I915_WRITE(IMR
, dev_priv
->irq_mask
);
4086 I915_WRITE(IER
, enable_mask
);
4089 I915_WRITE(PORT_HOTPLUG_EN
, 0);
4090 POSTING_READ(PORT_HOTPLUG_EN
);
4092 i915_enable_asle_pipestat(dev
);
4097 static void i915_hpd_irq_setup(struct drm_device
*dev
)
4099 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4100 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4101 struct intel_encoder
*intel_encoder
;
4104 assert_spin_locked(&dev_priv
->irq_lock
);
4106 if (I915_HAS_HOTPLUG(dev
)) {
4107 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
4108 hotplug_en
&= ~HOTPLUG_INT_EN_MASK
;
4109 /* Note HDMI and DP share hotplug bits */
4110 /* enable bits are the same for all generations */
4111 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
4112 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
4113 hotplug_en
|= hpd_mask_i915
[intel_encoder
->hpd_pin
];
4114 /* Programming the CRT detection parameters tends
4115 to generate a spurious hotplug event about three
4116 seconds later. So just do it once.
4119 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
4120 hotplug_en
&= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK
;
4121 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
4123 /* Ignore TV since it's buggy */
4124 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
4128 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
4130 struct drm_device
*dev
= arg
;
4131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4133 u32 pipe_stats
[I915_MAX_PIPES
];
4134 unsigned long irqflags
;
4135 int ret
= IRQ_NONE
, pipe
;
4137 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4138 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
4140 iir
= I915_READ(IIR
);
4143 bool irq_received
= (iir
& ~flip_mask
) != 0;
4144 bool blc_event
= false;
4146 /* Can't rely on pipestat interrupt bit in iir as it might
4147 * have been cleared after the pipestat interrupt was received.
4148 * It doesn't set the bit in iir again, but it still produces
4149 * interrupts (for non-MSI).
4151 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
4152 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
4153 i915_handle_error(dev
, false,
4154 "Command parser error, iir 0x%08x",
4157 for_each_pipe(pipe
) {
4158 int reg
= PIPESTAT(pipe
);
4159 pipe_stats
[pipe
] = I915_READ(reg
);
4162 * Clear the PIPE*STAT regs before the IIR
4164 if (pipe_stats
[pipe
] & 0x8000ffff) {
4165 I915_WRITE(reg
, pipe_stats
[pipe
]);
4166 irq_received
= true;
4169 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
4176 /* Consume port. Then clear IIR or we'll miss events */
4177 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
4178 i9xx_hpd_irq_handler(dev
);
4180 I915_WRITE(IIR
, iir
& ~flip_mask
);
4181 new_iir
= I915_READ(IIR
); /* Flush posted writes */
4183 if (iir
& I915_USER_INTERRUPT
)
4184 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
4185 if (iir
& I915_BSD_USER_INTERRUPT
)
4186 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
4188 for_each_pipe(pipe
) {
4189 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
4190 i915_handle_vblank(dev
, pipe
, pipe
, iir
))
4191 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
4193 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
4196 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
4197 i9xx_pipe_crc_irq_handler(dev
, pipe
);
4199 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
&&
4200 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, false))
4201 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe
));
4204 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
4205 intel_opregion_asle_intr(dev
);
4207 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
4208 gmbus_irq_handler(dev
);
4210 /* With MSI, interrupts are only generated when iir
4211 * transitions from zero to nonzero. If another bit got
4212 * set while we were handling the existing iir bits, then
4213 * we would never get another interrupt.
4215 * This is fine on non-MSI as well, as if we hit this path
4216 * we avoid exiting the interrupt handler only to generate
4219 * Note that for MSI this could cause a stray interrupt report
4220 * if an interrupt landed in the time between writing IIR and
4221 * the posting read. This should be rare enough to never
4222 * trigger the 99% of 100,000 interrupts test for disabling
4228 i915_update_dri1_breadcrumb(dev
);
4233 static void i965_irq_uninstall(struct drm_device
* dev
)
4235 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4241 intel_hpd_irq_uninstall(dev_priv
);
4243 I915_WRITE(PORT_HOTPLUG_EN
, 0);
4244 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4246 I915_WRITE(HWSTAM
, 0xffffffff);
4248 I915_WRITE(PIPESTAT(pipe
), 0);
4249 I915_WRITE(IMR
, 0xffffffff);
4250 I915_WRITE(IER
, 0x0);
4253 I915_WRITE(PIPESTAT(pipe
),
4254 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
4255 I915_WRITE(IIR
, I915_READ(IIR
));
4258 static void intel_hpd_irq_reenable(unsigned long data
)
4260 struct drm_i915_private
*dev_priv
= (struct drm_i915_private
*)data
;
4261 struct drm_device
*dev
= dev_priv
->dev
;
4262 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4263 unsigned long irqflags
;
4266 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
4267 for (i
= (HPD_NONE
+ 1); i
< HPD_NUM_PINS
; i
++) {
4268 struct drm_connector
*connector
;
4270 if (dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_DISABLED
)
4273 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
4275 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
4276 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4278 if (intel_connector
->encoder
->hpd_pin
== i
) {
4279 if (connector
->polled
!= intel_connector
->polled
)
4280 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
4281 drm_get_connector_name(connector
));
4282 connector
->polled
= intel_connector
->polled
;
4283 if (!connector
->polled
)
4284 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
4288 if (dev_priv
->display
.hpd_irq_setup
)
4289 dev_priv
->display
.hpd_irq_setup(dev
);
4290 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
4293 void intel_irq_init(struct drm_device
*dev
)
4295 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4297 INIT_WORK(&dev_priv
->hotplug_work
, i915_hotplug_work_func
);
4298 INIT_WORK(&dev_priv
->gpu_error
.work
, i915_error_work_func
);
4299 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
4300 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
4302 /* Let's track the enabled rps events */
4303 dev_priv
->pm_rps_events
= GEN6_PM_RPS_EVENTS
;
4305 setup_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
4306 i915_hangcheck_elapsed
,
4307 (unsigned long) dev
);
4308 setup_timer(&dev_priv
->hotplug_reenable_timer
, intel_hpd_irq_reenable
,
4309 (unsigned long) dev_priv
);
4311 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
, PM_QOS_DEFAULT_VALUE
);
4314 dev
->max_vblank_count
= 0;
4315 dev
->driver
->get_vblank_counter
= i8xx_get_vblank_counter
;
4316 } else if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
4317 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
4318 dev
->driver
->get_vblank_counter
= gm45_get_vblank_counter
;
4320 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
4321 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
4324 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
4325 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
4326 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
4329 if (IS_CHERRYVIEW(dev
)) {
4330 dev
->driver
->irq_handler
= cherryview_irq_handler
;
4331 dev
->driver
->irq_preinstall
= cherryview_irq_preinstall
;
4332 dev
->driver
->irq_postinstall
= cherryview_irq_postinstall
;
4333 dev
->driver
->irq_uninstall
= cherryview_irq_uninstall
;
4334 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
4335 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
4336 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4337 } else if (IS_VALLEYVIEW(dev
)) {
4338 dev
->driver
->irq_handler
= valleyview_irq_handler
;
4339 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
4340 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
4341 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
4342 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
4343 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
4344 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4345 } else if (IS_GEN8(dev
)) {
4346 dev
->driver
->irq_handler
= gen8_irq_handler
;
4347 dev
->driver
->irq_preinstall
= gen8_irq_preinstall
;
4348 dev
->driver
->irq_postinstall
= gen8_irq_postinstall
;
4349 dev
->driver
->irq_uninstall
= gen8_irq_uninstall
;
4350 dev
->driver
->enable_vblank
= gen8_enable_vblank
;
4351 dev
->driver
->disable_vblank
= gen8_disable_vblank
;
4352 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
4353 } else if (HAS_PCH_SPLIT(dev
)) {
4354 dev
->driver
->irq_handler
= ironlake_irq_handler
;
4355 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
4356 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
4357 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
4358 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
4359 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
4360 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
4362 if (INTEL_INFO(dev
)->gen
== 2) {
4363 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
4364 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
4365 dev
->driver
->irq_handler
= i8xx_irq_handler
;
4366 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
4367 } else if (INTEL_INFO(dev
)->gen
== 3) {
4368 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
4369 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
4370 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
4371 dev
->driver
->irq_handler
= i915_irq_handler
;
4372 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4374 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
4375 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
4376 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
4377 dev
->driver
->irq_handler
= i965_irq_handler
;
4378 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4380 dev
->driver
->enable_vblank
= i915_enable_vblank
;
4381 dev
->driver
->disable_vblank
= i915_disable_vblank
;
4385 void intel_hpd_init(struct drm_device
*dev
)
4387 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4388 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4389 struct drm_connector
*connector
;
4390 unsigned long irqflags
;
4393 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
4394 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
4395 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
4397 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
4398 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4399 connector
->polled
= intel_connector
->polled
;
4400 if (!connector
->polled
&& I915_HAS_HOTPLUG(dev
) && intel_connector
->encoder
->hpd_pin
> HPD_NONE
)
4401 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
4404 /* Interrupt setup is already guaranteed to be single-threaded, this is
4405 * just to make the assert_spin_locked checks happy. */
4406 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
4407 if (dev_priv
->display
.hpd_irq_setup
)
4408 dev_priv
->display
.hpd_irq_setup(dev
);
4409 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
4412 /* Disable interrupts so we can allow runtime PM. */
4413 void intel_runtime_pm_disable_interrupts(struct drm_device
*dev
)
4415 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4417 dev
->driver
->irq_uninstall(dev
);
4418 dev_priv
->pm
.irqs_disabled
= true;
4421 /* Restore interrupts so we can recover from runtime PM. */
4422 void intel_runtime_pm_restore_interrupts(struct drm_device
*dev
)
4424 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4426 dev_priv
->pm
.irqs_disabled
= false;
4427 dev
->driver
->irq_preinstall(dev
);
4428 dev
->driver
->irq_postinstall(dev
);