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drm/i915/vlv: WA to fix Voltage not getting dropped to Vmin when Gfx is power gated.
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
34 #include <drm/drmP.h>
35 #include <drm/i915_drm.h>
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "intel_drv.h"
39
40 static const u32 hpd_ibx[] = {
41 [HPD_CRT] = SDE_CRT_HOTPLUG,
42 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
43 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
44 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
45 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
46 };
47
48 static const u32 hpd_cpt[] = {
49 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
50 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
51 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
52 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
53 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
54 };
55
56 static const u32 hpd_mask_i915[] = {
57 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
58 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
59 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
60 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
61 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
62 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
63 };
64
65 static const u32 hpd_status_g4x[] = {
66 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
67 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
68 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
69 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
70 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
71 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
72 };
73
74 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
75 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
76 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
77 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
78 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
79 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
80 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
81 };
82
83 /* For display hotplug interrupt */
84 static void
85 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
86 {
87 assert_spin_locked(&dev_priv->irq_lock);
88
89 if (dev_priv->pc8.irqs_disabled) {
90 WARN(1, "IRQs disabled\n");
91 dev_priv->pc8.regsave.deimr &= ~mask;
92 return;
93 }
94
95 if ((dev_priv->irq_mask & mask) != 0) {
96 dev_priv->irq_mask &= ~mask;
97 I915_WRITE(DEIMR, dev_priv->irq_mask);
98 POSTING_READ(DEIMR);
99 }
100 }
101
102 static void
103 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
104 {
105 assert_spin_locked(&dev_priv->irq_lock);
106
107 if (dev_priv->pc8.irqs_disabled) {
108 WARN(1, "IRQs disabled\n");
109 dev_priv->pc8.regsave.deimr |= mask;
110 return;
111 }
112
113 if ((dev_priv->irq_mask & mask) != mask) {
114 dev_priv->irq_mask |= mask;
115 I915_WRITE(DEIMR, dev_priv->irq_mask);
116 POSTING_READ(DEIMR);
117 }
118 }
119
120 /**
121 * ilk_update_gt_irq - update GTIMR
122 * @dev_priv: driver private
123 * @interrupt_mask: mask of interrupt bits to update
124 * @enabled_irq_mask: mask of interrupt bits to enable
125 */
126 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
127 uint32_t interrupt_mask,
128 uint32_t enabled_irq_mask)
129 {
130 assert_spin_locked(&dev_priv->irq_lock);
131
132 if (dev_priv->pc8.irqs_disabled) {
133 WARN(1, "IRQs disabled\n");
134 dev_priv->pc8.regsave.gtimr &= ~interrupt_mask;
135 dev_priv->pc8.regsave.gtimr |= (~enabled_irq_mask &
136 interrupt_mask);
137 return;
138 }
139
140 dev_priv->gt_irq_mask &= ~interrupt_mask;
141 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
142 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
143 POSTING_READ(GTIMR);
144 }
145
146 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
147 {
148 ilk_update_gt_irq(dev_priv, mask, mask);
149 }
150
151 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
152 {
153 ilk_update_gt_irq(dev_priv, mask, 0);
154 }
155
156 /**
157 * snb_update_pm_irq - update GEN6_PMIMR
158 * @dev_priv: driver private
159 * @interrupt_mask: mask of interrupt bits to update
160 * @enabled_irq_mask: mask of interrupt bits to enable
161 */
162 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
163 uint32_t interrupt_mask,
164 uint32_t enabled_irq_mask)
165 {
166 uint32_t new_val;
167
168 assert_spin_locked(&dev_priv->irq_lock);
169
170 if (dev_priv->pc8.irqs_disabled) {
171 WARN(1, "IRQs disabled\n");
172 dev_priv->pc8.regsave.gen6_pmimr &= ~interrupt_mask;
173 dev_priv->pc8.regsave.gen6_pmimr |= (~enabled_irq_mask &
174 interrupt_mask);
175 return;
176 }
177
178 new_val = dev_priv->pm_irq_mask;
179 new_val &= ~interrupt_mask;
180 new_val |= (~enabled_irq_mask & interrupt_mask);
181
182 if (new_val != dev_priv->pm_irq_mask) {
183 dev_priv->pm_irq_mask = new_val;
184 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
185 POSTING_READ(GEN6_PMIMR);
186 }
187 }
188
189 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
190 {
191 snb_update_pm_irq(dev_priv, mask, mask);
192 }
193
194 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
195 {
196 snb_update_pm_irq(dev_priv, mask, 0);
197 }
198
199 static bool ivb_can_enable_err_int(struct drm_device *dev)
200 {
201 struct drm_i915_private *dev_priv = dev->dev_private;
202 struct intel_crtc *crtc;
203 enum pipe pipe;
204
205 assert_spin_locked(&dev_priv->irq_lock);
206
207 for_each_pipe(pipe) {
208 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
209
210 if (crtc->cpu_fifo_underrun_disabled)
211 return false;
212 }
213
214 return true;
215 }
216
217 static bool cpt_can_enable_serr_int(struct drm_device *dev)
218 {
219 struct drm_i915_private *dev_priv = dev->dev_private;
220 enum pipe pipe;
221 struct intel_crtc *crtc;
222
223 assert_spin_locked(&dev_priv->irq_lock);
224
225 for_each_pipe(pipe) {
226 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
227
228 if (crtc->pch_fifo_underrun_disabled)
229 return false;
230 }
231
232 return true;
233 }
234
235 static void i9xx_clear_fifo_underrun(struct drm_device *dev, enum pipe pipe)
236 {
237 struct drm_i915_private *dev_priv = dev->dev_private;
238 u32 reg = PIPESTAT(pipe);
239 u32 pipestat = I915_READ(reg) & 0x7fff0000;
240
241 assert_spin_locked(&dev_priv->irq_lock);
242
243 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
244 POSTING_READ(reg);
245 }
246
247 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
248 enum pipe pipe, bool enable)
249 {
250 struct drm_i915_private *dev_priv = dev->dev_private;
251 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
252 DE_PIPEB_FIFO_UNDERRUN;
253
254 if (enable)
255 ironlake_enable_display_irq(dev_priv, bit);
256 else
257 ironlake_disable_display_irq(dev_priv, bit);
258 }
259
260 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
261 enum pipe pipe, bool enable)
262 {
263 struct drm_i915_private *dev_priv = dev->dev_private;
264 if (enable) {
265 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
266
267 if (!ivb_can_enable_err_int(dev))
268 return;
269
270 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
271 } else {
272 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
273
274 /* Change the state _after_ we've read out the current one. */
275 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
276
277 if (!was_enabled &&
278 (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
279 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
280 pipe_name(pipe));
281 }
282 }
283 }
284
285 static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
286 enum pipe pipe, bool enable)
287 {
288 struct drm_i915_private *dev_priv = dev->dev_private;
289
290 assert_spin_locked(&dev_priv->irq_lock);
291
292 if (enable)
293 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;
294 else
295 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
296 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
297 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
298 }
299
300 /**
301 * ibx_display_interrupt_update - update SDEIMR
302 * @dev_priv: driver private
303 * @interrupt_mask: mask of interrupt bits to update
304 * @enabled_irq_mask: mask of interrupt bits to enable
305 */
306 static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
307 uint32_t interrupt_mask,
308 uint32_t enabled_irq_mask)
309 {
310 uint32_t sdeimr = I915_READ(SDEIMR);
311 sdeimr &= ~interrupt_mask;
312 sdeimr |= (~enabled_irq_mask & interrupt_mask);
313
314 assert_spin_locked(&dev_priv->irq_lock);
315
316 if (dev_priv->pc8.irqs_disabled &&
317 (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) {
318 WARN(1, "IRQs disabled\n");
319 dev_priv->pc8.regsave.sdeimr &= ~interrupt_mask;
320 dev_priv->pc8.regsave.sdeimr |= (~enabled_irq_mask &
321 interrupt_mask);
322 return;
323 }
324
325 I915_WRITE(SDEIMR, sdeimr);
326 POSTING_READ(SDEIMR);
327 }
328 #define ibx_enable_display_interrupt(dev_priv, bits) \
329 ibx_display_interrupt_update((dev_priv), (bits), (bits))
330 #define ibx_disable_display_interrupt(dev_priv, bits) \
331 ibx_display_interrupt_update((dev_priv), (bits), 0)
332
333 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
334 enum transcoder pch_transcoder,
335 bool enable)
336 {
337 struct drm_i915_private *dev_priv = dev->dev_private;
338 uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
339 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
340
341 if (enable)
342 ibx_enable_display_interrupt(dev_priv, bit);
343 else
344 ibx_disable_display_interrupt(dev_priv, bit);
345 }
346
347 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
348 enum transcoder pch_transcoder,
349 bool enable)
350 {
351 struct drm_i915_private *dev_priv = dev->dev_private;
352
353 if (enable) {
354 I915_WRITE(SERR_INT,
355 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
356
357 if (!cpt_can_enable_serr_int(dev))
358 return;
359
360 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
361 } else {
362 uint32_t tmp = I915_READ(SERR_INT);
363 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
364
365 /* Change the state _after_ we've read out the current one. */
366 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
367
368 if (!was_enabled &&
369 (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
370 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
371 transcoder_name(pch_transcoder));
372 }
373 }
374 }
375
376 /**
377 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
378 * @dev: drm device
379 * @pipe: pipe
380 * @enable: true if we want to report FIFO underrun errors, false otherwise
381 *
382 * This function makes us disable or enable CPU fifo underruns for a specific
383 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
384 * reporting for one pipe may also disable all the other CPU error interruts for
385 * the other pipes, due to the fact that there's just one interrupt mask/enable
386 * bit for all the pipes.
387 *
388 * Returns the previous state of underrun reporting.
389 */
390 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
391 enum pipe pipe, bool enable)
392 {
393 struct drm_i915_private *dev_priv = dev->dev_private;
394 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
396 unsigned long flags;
397 bool ret;
398
399 spin_lock_irqsave(&dev_priv->irq_lock, flags);
400
401 ret = !intel_crtc->cpu_fifo_underrun_disabled;
402
403 if (enable == ret)
404 goto done;
405
406 intel_crtc->cpu_fifo_underrun_disabled = !enable;
407
408 if (enable && (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)))
409 i9xx_clear_fifo_underrun(dev, pipe);
410 else if (IS_GEN5(dev) || IS_GEN6(dev))
411 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
412 else if (IS_GEN7(dev))
413 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
414 else if (IS_GEN8(dev))
415 broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
416
417 done:
418 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
419 return ret;
420 }
421
422 /**
423 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
424 * @dev: drm device
425 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
426 * @enable: true if we want to report FIFO underrun errors, false otherwise
427 *
428 * This function makes us disable or enable PCH fifo underruns for a specific
429 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
430 * underrun reporting for one transcoder may also disable all the other PCH
431 * error interruts for the other transcoders, due to the fact that there's just
432 * one interrupt mask/enable bit for all the transcoders.
433 *
434 * Returns the previous state of underrun reporting.
435 */
436 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
437 enum transcoder pch_transcoder,
438 bool enable)
439 {
440 struct drm_i915_private *dev_priv = dev->dev_private;
441 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
442 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
443 unsigned long flags;
444 bool ret;
445
446 /*
447 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
448 * has only one pch transcoder A that all pipes can use. To avoid racy
449 * pch transcoder -> pipe lookups from interrupt code simply store the
450 * underrun statistics in crtc A. Since we never expose this anywhere
451 * nor use it outside of the fifo underrun code here using the "wrong"
452 * crtc on LPT won't cause issues.
453 */
454
455 spin_lock_irqsave(&dev_priv->irq_lock, flags);
456
457 ret = !intel_crtc->pch_fifo_underrun_disabled;
458
459 if (enable == ret)
460 goto done;
461
462 intel_crtc->pch_fifo_underrun_disabled = !enable;
463
464 if (HAS_PCH_IBX(dev))
465 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
466 else
467 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
468
469 done:
470 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
471 return ret;
472 }
473
474
475 void
476 i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask)
477 {
478 u32 reg = PIPESTAT(pipe);
479 u32 pipestat = I915_READ(reg) & 0x7fff0000;
480
481 assert_spin_locked(&dev_priv->irq_lock);
482
483 if ((pipestat & mask) == mask)
484 return;
485
486 /* Enable the interrupt, clear any pending status */
487 pipestat |= mask | (mask >> 16);
488 I915_WRITE(reg, pipestat);
489 POSTING_READ(reg);
490 }
491
492 void
493 i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask)
494 {
495 u32 reg = PIPESTAT(pipe);
496 u32 pipestat = I915_READ(reg) & 0x7fff0000;
497
498 assert_spin_locked(&dev_priv->irq_lock);
499
500 if ((pipestat & mask) == 0)
501 return;
502
503 pipestat &= ~mask;
504 I915_WRITE(reg, pipestat);
505 POSTING_READ(reg);
506 }
507
508 /**
509 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
510 */
511 static void i915_enable_asle_pipestat(struct drm_device *dev)
512 {
513 drm_i915_private_t *dev_priv = dev->dev_private;
514 unsigned long irqflags;
515
516 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
517 return;
518
519 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
520
521 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_ENABLE);
522 if (INTEL_INFO(dev)->gen >= 4)
523 i915_enable_pipestat(dev_priv, PIPE_A,
524 PIPE_LEGACY_BLC_EVENT_ENABLE);
525
526 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
527 }
528
529 /**
530 * i915_pipe_enabled - check if a pipe is enabled
531 * @dev: DRM device
532 * @pipe: pipe to check
533 *
534 * Reading certain registers when the pipe is disabled can hang the chip.
535 * Use this routine to make sure the PLL is running and the pipe is active
536 * before reading such registers if unsure.
537 */
538 static int
539 i915_pipe_enabled(struct drm_device *dev, int pipe)
540 {
541 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
542
543 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
544 /* Locking is horribly broken here, but whatever. */
545 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
546 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
547
548 return intel_crtc->active;
549 } else {
550 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
551 }
552 }
553
554 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
555 {
556 /* Gen2 doesn't have a hardware frame counter */
557 return 0;
558 }
559
560 /* Called from drm generic code, passed a 'crtc', which
561 * we use as a pipe index
562 */
563 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
564 {
565 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
566 unsigned long high_frame;
567 unsigned long low_frame;
568 u32 high1, high2, low, pixel, vbl_start;
569
570 if (!i915_pipe_enabled(dev, pipe)) {
571 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
572 "pipe %c\n", pipe_name(pipe));
573 return 0;
574 }
575
576 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
577 struct intel_crtc *intel_crtc =
578 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
579 const struct drm_display_mode *mode =
580 &intel_crtc->config.adjusted_mode;
581
582 vbl_start = mode->crtc_vblank_start * mode->crtc_htotal;
583 } else {
584 enum transcoder cpu_transcoder =
585 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
586 u32 htotal;
587
588 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
589 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
590
591 vbl_start *= htotal;
592 }
593
594 high_frame = PIPEFRAME(pipe);
595 low_frame = PIPEFRAMEPIXEL(pipe);
596
597 /*
598 * High & low register fields aren't synchronized, so make sure
599 * we get a low value that's stable across two reads of the high
600 * register.
601 */
602 do {
603 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
604 low = I915_READ(low_frame);
605 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
606 } while (high1 != high2);
607
608 high1 >>= PIPE_FRAME_HIGH_SHIFT;
609 pixel = low & PIPE_PIXEL_MASK;
610 low >>= PIPE_FRAME_LOW_SHIFT;
611
612 /*
613 * The frame counter increments at beginning of active.
614 * Cook up a vblank counter by also checking the pixel
615 * counter against vblank start.
616 */
617 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
618 }
619
620 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
621 {
622 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
623 int reg = PIPE_FRMCOUNT_GM45(pipe);
624
625 if (!i915_pipe_enabled(dev, pipe)) {
626 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
627 "pipe %c\n", pipe_name(pipe));
628 return 0;
629 }
630
631 return I915_READ(reg);
632 }
633
634 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
635 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
636 #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
637
638 static bool ilk_pipe_in_vblank_locked(struct drm_device *dev, enum pipe pipe)
639 {
640 struct drm_i915_private *dev_priv = dev->dev_private;
641 uint32_t status;
642
643 if (INTEL_INFO(dev)->gen < 7) {
644 status = pipe == PIPE_A ?
645 DE_PIPEA_VBLANK :
646 DE_PIPEB_VBLANK;
647 } else {
648 switch (pipe) {
649 default:
650 case PIPE_A:
651 status = DE_PIPEA_VBLANK_IVB;
652 break;
653 case PIPE_B:
654 status = DE_PIPEB_VBLANK_IVB;
655 break;
656 case PIPE_C:
657 status = DE_PIPEC_VBLANK_IVB;
658 break;
659 }
660 }
661
662 return __raw_i915_read32(dev_priv, DEISR) & status;
663 }
664
665 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
666 unsigned int flags, int *vpos, int *hpos,
667 ktime_t *stime, ktime_t *etime)
668 {
669 struct drm_i915_private *dev_priv = dev->dev_private;
670 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
671 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
672 const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
673 int position;
674 int vbl_start, vbl_end, htotal, vtotal;
675 bool in_vbl = true;
676 int ret = 0;
677 unsigned long irqflags;
678
679 if (!intel_crtc->active) {
680 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
681 "pipe %c\n", pipe_name(pipe));
682 return 0;
683 }
684
685 htotal = mode->crtc_htotal;
686 vtotal = mode->crtc_vtotal;
687 vbl_start = mode->crtc_vblank_start;
688 vbl_end = mode->crtc_vblank_end;
689
690 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
691 vbl_start = DIV_ROUND_UP(vbl_start, 2);
692 vbl_end /= 2;
693 vtotal /= 2;
694 }
695
696 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
697
698 /*
699 * Lock uncore.lock, as we will do multiple timing critical raw
700 * register reads, potentially with preemption disabled, so the
701 * following code must not block on uncore.lock.
702 */
703 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
704
705 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
706
707 /* Get optional system timestamp before query. */
708 if (stime)
709 *stime = ktime_get();
710
711 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
712 /* No obvious pixelcount register. Only query vertical
713 * scanout position from Display scan line register.
714 */
715 if (IS_GEN2(dev))
716 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
717 else
718 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
719
720 if (HAS_PCH_SPLIT(dev)) {
721 /*
722 * The scanline counter increments at the leading edge
723 * of hsync, ie. it completely misses the active portion
724 * of the line. Fix up the counter at both edges of vblank
725 * to get a more accurate picture whether we're in vblank
726 * or not.
727 */
728 in_vbl = ilk_pipe_in_vblank_locked(dev, pipe);
729 if ((in_vbl && position == vbl_start - 1) ||
730 (!in_vbl && position == vbl_end - 1))
731 position = (position + 1) % vtotal;
732 } else {
733 /*
734 * ISR vblank status bits don't work the way we'd want
735 * them to work on non-PCH platforms (for
736 * ilk_pipe_in_vblank_locked()), and there doesn't
737 * appear any other way to determine if we're currently
738 * in vblank.
739 *
740 * Instead let's assume that we're already in vblank if
741 * we got called from the vblank interrupt and the
742 * scanline counter value indicates that we're on the
743 * line just prior to vblank start. This should result
744 * in the correct answer, unless the vblank interrupt
745 * delivery really got delayed for almost exactly one
746 * full frame/field.
747 */
748 if (flags & DRM_CALLED_FROM_VBLIRQ &&
749 position == vbl_start - 1) {
750 position = (position + 1) % vtotal;
751
752 /* Signal this correction as "applied". */
753 ret |= 0x8;
754 }
755 }
756 } else {
757 /* Have access to pixelcount since start of frame.
758 * We can split this into vertical and horizontal
759 * scanout position.
760 */
761 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
762
763 /* convert to pixel counts */
764 vbl_start *= htotal;
765 vbl_end *= htotal;
766 vtotal *= htotal;
767 }
768
769 /* Get optional system timestamp after query. */
770 if (etime)
771 *etime = ktime_get();
772
773 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
774
775 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
776
777 in_vbl = position >= vbl_start && position < vbl_end;
778
779 /*
780 * While in vblank, position will be negative
781 * counting up towards 0 at vbl_end. And outside
782 * vblank, position will be positive counting
783 * up since vbl_end.
784 */
785 if (position >= vbl_start)
786 position -= vbl_end;
787 else
788 position += vtotal - vbl_end;
789
790 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
791 *vpos = position;
792 *hpos = 0;
793 } else {
794 *vpos = position / htotal;
795 *hpos = position - (*vpos * htotal);
796 }
797
798 /* In vblank? */
799 if (in_vbl)
800 ret |= DRM_SCANOUTPOS_INVBL;
801
802 return ret;
803 }
804
805 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
806 int *max_error,
807 struct timeval *vblank_time,
808 unsigned flags)
809 {
810 struct drm_crtc *crtc;
811
812 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
813 DRM_ERROR("Invalid crtc %d\n", pipe);
814 return -EINVAL;
815 }
816
817 /* Get drm_crtc to timestamp: */
818 crtc = intel_get_crtc_for_pipe(dev, pipe);
819 if (crtc == NULL) {
820 DRM_ERROR("Invalid crtc %d\n", pipe);
821 return -EINVAL;
822 }
823
824 if (!crtc->enabled) {
825 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
826 return -EBUSY;
827 }
828
829 /* Helper routine in DRM core does all the work: */
830 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
831 vblank_time, flags,
832 crtc,
833 &to_intel_crtc(crtc)->config.adjusted_mode);
834 }
835
836 static bool intel_hpd_irq_event(struct drm_device *dev,
837 struct drm_connector *connector)
838 {
839 enum drm_connector_status old_status;
840
841 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
842 old_status = connector->status;
843
844 connector->status = connector->funcs->detect(connector, false);
845 if (old_status == connector->status)
846 return false;
847
848 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
849 connector->base.id,
850 drm_get_connector_name(connector),
851 drm_get_connector_status_name(old_status),
852 drm_get_connector_status_name(connector->status));
853
854 return true;
855 }
856
857 /*
858 * Handle hotplug events outside the interrupt handler proper.
859 */
860 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
861
862 static void i915_hotplug_work_func(struct work_struct *work)
863 {
864 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
865 hotplug_work);
866 struct drm_device *dev = dev_priv->dev;
867 struct drm_mode_config *mode_config = &dev->mode_config;
868 struct intel_connector *intel_connector;
869 struct intel_encoder *intel_encoder;
870 struct drm_connector *connector;
871 unsigned long irqflags;
872 bool hpd_disabled = false;
873 bool changed = false;
874 u32 hpd_event_bits;
875
876 /* HPD irq before everything is fully set up. */
877 if (!dev_priv->enable_hotplug_processing)
878 return;
879
880 mutex_lock(&mode_config->mutex);
881 DRM_DEBUG_KMS("running encoder hotplug functions\n");
882
883 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
884
885 hpd_event_bits = dev_priv->hpd_event_bits;
886 dev_priv->hpd_event_bits = 0;
887 list_for_each_entry(connector, &mode_config->connector_list, head) {
888 intel_connector = to_intel_connector(connector);
889 intel_encoder = intel_connector->encoder;
890 if (intel_encoder->hpd_pin > HPD_NONE &&
891 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
892 connector->polled == DRM_CONNECTOR_POLL_HPD) {
893 DRM_INFO("HPD interrupt storm detected on connector %s: "
894 "switching from hotplug detection to polling\n",
895 drm_get_connector_name(connector));
896 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
897 connector->polled = DRM_CONNECTOR_POLL_CONNECT
898 | DRM_CONNECTOR_POLL_DISCONNECT;
899 hpd_disabled = true;
900 }
901 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
902 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
903 drm_get_connector_name(connector), intel_encoder->hpd_pin);
904 }
905 }
906 /* if there were no outputs to poll, poll was disabled,
907 * therefore make sure it's enabled when disabling HPD on
908 * some connectors */
909 if (hpd_disabled) {
910 drm_kms_helper_poll_enable(dev);
911 mod_timer(&dev_priv->hotplug_reenable_timer,
912 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
913 }
914
915 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
916
917 list_for_each_entry(connector, &mode_config->connector_list, head) {
918 intel_connector = to_intel_connector(connector);
919 intel_encoder = intel_connector->encoder;
920 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
921 if (intel_encoder->hot_plug)
922 intel_encoder->hot_plug(intel_encoder);
923 if (intel_hpd_irq_event(dev, connector))
924 changed = true;
925 }
926 }
927 mutex_unlock(&mode_config->mutex);
928
929 if (changed)
930 drm_kms_helper_hotplug_event(dev);
931 }
932
933 static void intel_hpd_irq_uninstall(struct drm_i915_private *dev_priv)
934 {
935 del_timer_sync(&dev_priv->hotplug_reenable_timer);
936 }
937
938 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
939 {
940 drm_i915_private_t *dev_priv = dev->dev_private;
941 u32 busy_up, busy_down, max_avg, min_avg;
942 u8 new_delay;
943
944 spin_lock(&mchdev_lock);
945
946 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
947
948 new_delay = dev_priv->ips.cur_delay;
949
950 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
951 busy_up = I915_READ(RCPREVBSYTUPAVG);
952 busy_down = I915_READ(RCPREVBSYTDNAVG);
953 max_avg = I915_READ(RCBMAXAVG);
954 min_avg = I915_READ(RCBMINAVG);
955
956 /* Handle RCS change request from hw */
957 if (busy_up > max_avg) {
958 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
959 new_delay = dev_priv->ips.cur_delay - 1;
960 if (new_delay < dev_priv->ips.max_delay)
961 new_delay = dev_priv->ips.max_delay;
962 } else if (busy_down < min_avg) {
963 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
964 new_delay = dev_priv->ips.cur_delay + 1;
965 if (new_delay > dev_priv->ips.min_delay)
966 new_delay = dev_priv->ips.min_delay;
967 }
968
969 if (ironlake_set_drps(dev, new_delay))
970 dev_priv->ips.cur_delay = new_delay;
971
972 spin_unlock(&mchdev_lock);
973
974 return;
975 }
976
977 static void notify_ring(struct drm_device *dev,
978 struct intel_ring_buffer *ring)
979 {
980 if (ring->obj == NULL)
981 return;
982
983 trace_i915_gem_request_complete(ring);
984
985 wake_up_all(&ring->irq_queue);
986 i915_queue_hangcheck(dev);
987 }
988
989 void gen6_set_pm_mask(struct drm_i915_private *dev_priv,
990 u32 pm_iir, int new_delay)
991 {
992 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
993 if (new_delay >= dev_priv->rps.max_delay) {
994 /* Mask UP THRESHOLD Interrupts */
995 I915_WRITE(GEN6_PMINTRMSK,
996 I915_READ(GEN6_PMINTRMSK) |
997 GEN6_PM_RP_UP_THRESHOLD);
998 dev_priv->rps.rp_up_masked = true;
999 }
1000 if (dev_priv->rps.rp_down_masked) {
1001 /* UnMask DOWN THRESHOLD Interrupts */
1002 I915_WRITE(GEN6_PMINTRMSK,
1003 I915_READ(GEN6_PMINTRMSK) &
1004 ~GEN6_PM_RP_DOWN_THRESHOLD);
1005 dev_priv->rps.rp_down_masked = false;
1006 }
1007 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1008 if (new_delay <= dev_priv->rps.min_delay) {
1009 /* Mask DOWN THRESHOLD Interrupts */
1010 I915_WRITE(GEN6_PMINTRMSK,
1011 I915_READ(GEN6_PMINTRMSK) |
1012 GEN6_PM_RP_DOWN_THRESHOLD);
1013 dev_priv->rps.rp_down_masked = true;
1014 }
1015
1016 if (dev_priv->rps.rp_up_masked) {
1017 /* UnMask UP THRESHOLD Interrupts */
1018 I915_WRITE(GEN6_PMINTRMSK,
1019 I915_READ(GEN6_PMINTRMSK) &
1020 ~GEN6_PM_RP_UP_THRESHOLD);
1021 dev_priv->rps.rp_up_masked = false;
1022 }
1023 }
1024 }
1025
1026 static void gen6_pm_rps_work(struct work_struct *work)
1027 {
1028 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
1029 rps.work);
1030 u32 pm_iir;
1031 int new_delay, adj;
1032
1033 spin_lock_irq(&dev_priv->irq_lock);
1034 pm_iir = dev_priv->rps.pm_iir;
1035 dev_priv->rps.pm_iir = 0;
1036 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
1037 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
1038 spin_unlock_irq(&dev_priv->irq_lock);
1039
1040 /* Make sure we didn't queue anything we're not going to process. */
1041 WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS);
1042
1043 if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
1044 return;
1045
1046 mutex_lock(&dev_priv->rps.hw_lock);
1047
1048 adj = dev_priv->rps.last_adj;
1049 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1050 if (adj > 0)
1051 adj *= 2;
1052 else
1053 adj = 1;
1054 new_delay = dev_priv->rps.cur_delay + adj;
1055
1056 /*
1057 * For better performance, jump directly
1058 * to RPe if we're below it.
1059 */
1060 if (new_delay < dev_priv->rps.rpe_delay)
1061 new_delay = dev_priv->rps.rpe_delay;
1062 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1063 if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
1064 new_delay = dev_priv->rps.rpe_delay;
1065 else
1066 new_delay = dev_priv->rps.min_delay;
1067 adj = 0;
1068 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1069 if (adj < 0)
1070 adj *= 2;
1071 else
1072 adj = -1;
1073 new_delay = dev_priv->rps.cur_delay + adj;
1074 } else { /* unknown event */
1075 new_delay = dev_priv->rps.cur_delay;
1076 }
1077
1078 /* sysfs frequency interfaces may have snuck in while servicing the
1079 * interrupt
1080 */
1081 new_delay = clamp_t(int, new_delay,
1082 dev_priv->rps.min_delay, dev_priv->rps.max_delay);
1083
1084 gen6_set_pm_mask(dev_priv, pm_iir, new_delay);
1085 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay;
1086
1087 if (IS_VALLEYVIEW(dev_priv->dev))
1088 valleyview_set_rps(dev_priv->dev, new_delay);
1089 else
1090 gen6_set_rps(dev_priv->dev, new_delay);
1091
1092 mutex_unlock(&dev_priv->rps.hw_lock);
1093 }
1094
1095
1096 /**
1097 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1098 * occurred.
1099 * @work: workqueue struct
1100 *
1101 * Doesn't actually do anything except notify userspace. As a consequence of
1102 * this event, userspace should try to remap the bad rows since statistically
1103 * it is likely the same row is more likely to go bad again.
1104 */
1105 static void ivybridge_parity_work(struct work_struct *work)
1106 {
1107 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
1108 l3_parity.error_work);
1109 u32 error_status, row, bank, subbank;
1110 char *parity_event[6];
1111 uint32_t misccpctl;
1112 unsigned long flags;
1113 uint8_t slice = 0;
1114
1115 /* We must turn off DOP level clock gating to access the L3 registers.
1116 * In order to prevent a get/put style interface, acquire struct mutex
1117 * any time we access those registers.
1118 */
1119 mutex_lock(&dev_priv->dev->struct_mutex);
1120
1121 /* If we've screwed up tracking, just let the interrupt fire again */
1122 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1123 goto out;
1124
1125 misccpctl = I915_READ(GEN7_MISCCPCTL);
1126 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1127 POSTING_READ(GEN7_MISCCPCTL);
1128
1129 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1130 u32 reg;
1131
1132 slice--;
1133 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1134 break;
1135
1136 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1137
1138 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1139
1140 error_status = I915_READ(reg);
1141 row = GEN7_PARITY_ERROR_ROW(error_status);
1142 bank = GEN7_PARITY_ERROR_BANK(error_status);
1143 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1144
1145 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1146 POSTING_READ(reg);
1147
1148 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1149 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1150 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1151 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1152 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1153 parity_event[5] = NULL;
1154
1155 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1156 KOBJ_CHANGE, parity_event);
1157
1158 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1159 slice, row, bank, subbank);
1160
1161 kfree(parity_event[4]);
1162 kfree(parity_event[3]);
1163 kfree(parity_event[2]);
1164 kfree(parity_event[1]);
1165 }
1166
1167 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1168
1169 out:
1170 WARN_ON(dev_priv->l3_parity.which_slice);
1171 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1172 ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1173 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1174
1175 mutex_unlock(&dev_priv->dev->struct_mutex);
1176 }
1177
1178 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1179 {
1180 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1181
1182 if (!HAS_L3_DPF(dev))
1183 return;
1184
1185 spin_lock(&dev_priv->irq_lock);
1186 ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1187 spin_unlock(&dev_priv->irq_lock);
1188
1189 iir &= GT_PARITY_ERROR(dev);
1190 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1191 dev_priv->l3_parity.which_slice |= 1 << 1;
1192
1193 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1194 dev_priv->l3_parity.which_slice |= 1 << 0;
1195
1196 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1197 }
1198
1199 static void ilk_gt_irq_handler(struct drm_device *dev,
1200 struct drm_i915_private *dev_priv,
1201 u32 gt_iir)
1202 {
1203 if (gt_iir &
1204 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1205 notify_ring(dev, &dev_priv->ring[RCS]);
1206 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1207 notify_ring(dev, &dev_priv->ring[VCS]);
1208 }
1209
1210 static void snb_gt_irq_handler(struct drm_device *dev,
1211 struct drm_i915_private *dev_priv,
1212 u32 gt_iir)
1213 {
1214
1215 if (gt_iir &
1216 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1217 notify_ring(dev, &dev_priv->ring[RCS]);
1218 if (gt_iir & GT_BSD_USER_INTERRUPT)
1219 notify_ring(dev, &dev_priv->ring[VCS]);
1220 if (gt_iir & GT_BLT_USER_INTERRUPT)
1221 notify_ring(dev, &dev_priv->ring[BCS]);
1222
1223 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1224 GT_BSD_CS_ERROR_INTERRUPT |
1225 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
1226 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
1227 i915_handle_error(dev, false);
1228 }
1229
1230 if (gt_iir & GT_PARITY_ERROR(dev))
1231 ivybridge_parity_error_irq_handler(dev, gt_iir);
1232 }
1233
1234 static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1235 struct drm_i915_private *dev_priv,
1236 u32 master_ctl)
1237 {
1238 u32 rcs, bcs, vcs;
1239 uint32_t tmp = 0;
1240 irqreturn_t ret = IRQ_NONE;
1241
1242 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1243 tmp = I915_READ(GEN8_GT_IIR(0));
1244 if (tmp) {
1245 ret = IRQ_HANDLED;
1246 rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1247 bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1248 if (rcs & GT_RENDER_USER_INTERRUPT)
1249 notify_ring(dev, &dev_priv->ring[RCS]);
1250 if (bcs & GT_RENDER_USER_INTERRUPT)
1251 notify_ring(dev, &dev_priv->ring[BCS]);
1252 I915_WRITE(GEN8_GT_IIR(0), tmp);
1253 } else
1254 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1255 }
1256
1257 if (master_ctl & GEN8_GT_VCS1_IRQ) {
1258 tmp = I915_READ(GEN8_GT_IIR(1));
1259 if (tmp) {
1260 ret = IRQ_HANDLED;
1261 vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1262 if (vcs & GT_RENDER_USER_INTERRUPT)
1263 notify_ring(dev, &dev_priv->ring[VCS]);
1264 I915_WRITE(GEN8_GT_IIR(1), tmp);
1265 } else
1266 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1267 }
1268
1269 if (master_ctl & GEN8_GT_VECS_IRQ) {
1270 tmp = I915_READ(GEN8_GT_IIR(3));
1271 if (tmp) {
1272 ret = IRQ_HANDLED;
1273 vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1274 if (vcs & GT_RENDER_USER_INTERRUPT)
1275 notify_ring(dev, &dev_priv->ring[VECS]);
1276 I915_WRITE(GEN8_GT_IIR(3), tmp);
1277 } else
1278 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1279 }
1280
1281 return ret;
1282 }
1283
1284 #define HPD_STORM_DETECT_PERIOD 1000
1285 #define HPD_STORM_THRESHOLD 5
1286
1287 static inline void intel_hpd_irq_handler(struct drm_device *dev,
1288 u32 hotplug_trigger,
1289 const u32 *hpd)
1290 {
1291 drm_i915_private_t *dev_priv = dev->dev_private;
1292 int i;
1293 bool storm_detected = false;
1294
1295 if (!hotplug_trigger)
1296 return;
1297
1298 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1299 hotplug_trigger);
1300
1301 spin_lock(&dev_priv->irq_lock);
1302 for (i = 1; i < HPD_NUM_PINS; i++) {
1303
1304 WARN_ONCE(hpd[i] & hotplug_trigger &&
1305 dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED,
1306 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1307 hotplug_trigger, i, hpd[i]);
1308
1309 if (!(hpd[i] & hotplug_trigger) ||
1310 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1311 continue;
1312
1313 dev_priv->hpd_event_bits |= (1 << i);
1314 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1315 dev_priv->hpd_stats[i].hpd_last_jiffies
1316 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1317 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1318 dev_priv->hpd_stats[i].hpd_cnt = 0;
1319 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1320 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1321 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1322 dev_priv->hpd_event_bits &= ~(1 << i);
1323 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1324 storm_detected = true;
1325 } else {
1326 dev_priv->hpd_stats[i].hpd_cnt++;
1327 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1328 dev_priv->hpd_stats[i].hpd_cnt);
1329 }
1330 }
1331
1332 if (storm_detected)
1333 dev_priv->display.hpd_irq_setup(dev);
1334 spin_unlock(&dev_priv->irq_lock);
1335
1336 /*
1337 * Our hotplug handler can grab modeset locks (by calling down into the
1338 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1339 * queue for otherwise the flush_work in the pageflip code will
1340 * deadlock.
1341 */
1342 schedule_work(&dev_priv->hotplug_work);
1343 }
1344
1345 static void gmbus_irq_handler(struct drm_device *dev)
1346 {
1347 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1348
1349 wake_up_all(&dev_priv->gmbus_wait_queue);
1350 }
1351
1352 static void dp_aux_irq_handler(struct drm_device *dev)
1353 {
1354 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1355
1356 wake_up_all(&dev_priv->gmbus_wait_queue);
1357 }
1358
1359 #if defined(CONFIG_DEBUG_FS)
1360 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1361 uint32_t crc0, uint32_t crc1,
1362 uint32_t crc2, uint32_t crc3,
1363 uint32_t crc4)
1364 {
1365 struct drm_i915_private *dev_priv = dev->dev_private;
1366 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1367 struct intel_pipe_crc_entry *entry;
1368 int head, tail;
1369
1370 spin_lock(&pipe_crc->lock);
1371
1372 if (!pipe_crc->entries) {
1373 spin_unlock(&pipe_crc->lock);
1374 DRM_ERROR("spurious interrupt\n");
1375 return;
1376 }
1377
1378 head = pipe_crc->head;
1379 tail = pipe_crc->tail;
1380
1381 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1382 spin_unlock(&pipe_crc->lock);
1383 DRM_ERROR("CRC buffer overflowing\n");
1384 return;
1385 }
1386
1387 entry = &pipe_crc->entries[head];
1388
1389 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1390 entry->crc[0] = crc0;
1391 entry->crc[1] = crc1;
1392 entry->crc[2] = crc2;
1393 entry->crc[3] = crc3;
1394 entry->crc[4] = crc4;
1395
1396 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1397 pipe_crc->head = head;
1398
1399 spin_unlock(&pipe_crc->lock);
1400
1401 wake_up_interruptible(&pipe_crc->wq);
1402 }
1403 #else
1404 static inline void
1405 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1406 uint32_t crc0, uint32_t crc1,
1407 uint32_t crc2, uint32_t crc3,
1408 uint32_t crc4) {}
1409 #endif
1410
1411
1412 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1413 {
1414 struct drm_i915_private *dev_priv = dev->dev_private;
1415
1416 display_pipe_crc_irq_handler(dev, pipe,
1417 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1418 0, 0, 0, 0);
1419 }
1420
1421 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1422 {
1423 struct drm_i915_private *dev_priv = dev->dev_private;
1424
1425 display_pipe_crc_irq_handler(dev, pipe,
1426 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1427 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1428 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1429 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1430 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1431 }
1432
1433 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1434 {
1435 struct drm_i915_private *dev_priv = dev->dev_private;
1436 uint32_t res1, res2;
1437
1438 if (INTEL_INFO(dev)->gen >= 3)
1439 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1440 else
1441 res1 = 0;
1442
1443 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1444 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1445 else
1446 res2 = 0;
1447
1448 display_pipe_crc_irq_handler(dev, pipe,
1449 I915_READ(PIPE_CRC_RES_RED(pipe)),
1450 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1451 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1452 res1, res2);
1453 }
1454
1455 /* The RPS events need forcewake, so we add them to a work queue and mask their
1456 * IMR bits until the work is done. Other interrupts can be processed without
1457 * the work queue. */
1458 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1459 {
1460 if (pm_iir & GEN6_PM_RPS_EVENTS) {
1461 spin_lock(&dev_priv->irq_lock);
1462 dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
1463 snb_disable_pm_irq(dev_priv, pm_iir & GEN6_PM_RPS_EVENTS);
1464 spin_unlock(&dev_priv->irq_lock);
1465
1466 queue_work(dev_priv->wq, &dev_priv->rps.work);
1467 }
1468
1469 if (HAS_VEBOX(dev_priv->dev)) {
1470 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1471 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1472
1473 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1474 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
1475 i915_handle_error(dev_priv->dev, false);
1476 }
1477 }
1478 }
1479
1480 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1481 {
1482 struct drm_device *dev = (struct drm_device *) arg;
1483 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1484 u32 iir, gt_iir, pm_iir;
1485 irqreturn_t ret = IRQ_NONE;
1486 unsigned long irqflags;
1487 int pipe;
1488 u32 pipe_stats[I915_MAX_PIPES];
1489
1490 while (true) {
1491 iir = I915_READ(VLV_IIR);
1492 gt_iir = I915_READ(GTIIR);
1493 pm_iir = I915_READ(GEN6_PMIIR);
1494
1495 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1496 goto out;
1497
1498 ret = IRQ_HANDLED;
1499
1500 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1501
1502 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1503 for_each_pipe(pipe) {
1504 int reg = PIPESTAT(pipe);
1505 pipe_stats[pipe] = I915_READ(reg);
1506
1507 /*
1508 * Clear the PIPE*STAT regs before the IIR
1509 */
1510 if (pipe_stats[pipe] & 0x8000ffff)
1511 I915_WRITE(reg, pipe_stats[pipe]);
1512 }
1513 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1514
1515 for_each_pipe(pipe) {
1516 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1517 drm_handle_vblank(dev, pipe);
1518
1519 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
1520 intel_prepare_page_flip(dev, pipe);
1521 intel_finish_page_flip(dev, pipe);
1522 }
1523
1524 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1525 i9xx_pipe_crc_irq_handler(dev, pipe);
1526
1527 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
1528 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1529 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
1530 }
1531
1532 /* Consume port. Then clear IIR or we'll miss events */
1533 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
1534 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1535 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1536
1537 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1538
1539 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1540 dp_aux_irq_handler(dev);
1541
1542 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1543 I915_READ(PORT_HOTPLUG_STAT);
1544 }
1545
1546 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1547 gmbus_irq_handler(dev);
1548
1549 if (pm_iir)
1550 gen6_rps_irq_handler(dev_priv, pm_iir);
1551
1552 I915_WRITE(GTIIR, gt_iir);
1553 I915_WRITE(GEN6_PMIIR, pm_iir);
1554 I915_WRITE(VLV_IIR, iir);
1555 }
1556
1557 out:
1558 return ret;
1559 }
1560
1561 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1562 {
1563 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1564 int pipe;
1565 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1566
1567 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1568
1569 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1570 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1571 SDE_AUDIO_POWER_SHIFT);
1572 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1573 port_name(port));
1574 }
1575
1576 if (pch_iir & SDE_AUX_MASK)
1577 dp_aux_irq_handler(dev);
1578
1579 if (pch_iir & SDE_GMBUS)
1580 gmbus_irq_handler(dev);
1581
1582 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1583 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1584
1585 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1586 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1587
1588 if (pch_iir & SDE_POISON)
1589 DRM_ERROR("PCH poison interrupt\n");
1590
1591 if (pch_iir & SDE_FDI_MASK)
1592 for_each_pipe(pipe)
1593 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1594 pipe_name(pipe),
1595 I915_READ(FDI_RX_IIR(pipe)));
1596
1597 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1598 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1599
1600 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1601 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1602
1603 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1604 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1605 false))
1606 DRM_ERROR("PCH transcoder A FIFO underrun\n");
1607
1608 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1609 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1610 false))
1611 DRM_ERROR("PCH transcoder B FIFO underrun\n");
1612 }
1613
1614 static void ivb_err_int_handler(struct drm_device *dev)
1615 {
1616 struct drm_i915_private *dev_priv = dev->dev_private;
1617 u32 err_int = I915_READ(GEN7_ERR_INT);
1618 enum pipe pipe;
1619
1620 if (err_int & ERR_INT_POISON)
1621 DRM_ERROR("Poison interrupt\n");
1622
1623 for_each_pipe(pipe) {
1624 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
1625 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1626 false))
1627 DRM_ERROR("Pipe %c FIFO underrun\n",
1628 pipe_name(pipe));
1629 }
1630
1631 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1632 if (IS_IVYBRIDGE(dev))
1633 ivb_pipe_crc_irq_handler(dev, pipe);
1634 else
1635 hsw_pipe_crc_irq_handler(dev, pipe);
1636 }
1637 }
1638
1639 I915_WRITE(GEN7_ERR_INT, err_int);
1640 }
1641
1642 static void cpt_serr_int_handler(struct drm_device *dev)
1643 {
1644 struct drm_i915_private *dev_priv = dev->dev_private;
1645 u32 serr_int = I915_READ(SERR_INT);
1646
1647 if (serr_int & SERR_INT_POISON)
1648 DRM_ERROR("PCH poison interrupt\n");
1649
1650 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1651 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1652 false))
1653 DRM_ERROR("PCH transcoder A FIFO underrun\n");
1654
1655 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1656 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1657 false))
1658 DRM_ERROR("PCH transcoder B FIFO underrun\n");
1659
1660 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1661 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1662 false))
1663 DRM_ERROR("PCH transcoder C FIFO underrun\n");
1664
1665 I915_WRITE(SERR_INT, serr_int);
1666 }
1667
1668 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1669 {
1670 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1671 int pipe;
1672 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1673
1674 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1675
1676 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1677 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1678 SDE_AUDIO_POWER_SHIFT_CPT);
1679 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1680 port_name(port));
1681 }
1682
1683 if (pch_iir & SDE_AUX_MASK_CPT)
1684 dp_aux_irq_handler(dev);
1685
1686 if (pch_iir & SDE_GMBUS_CPT)
1687 gmbus_irq_handler(dev);
1688
1689 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1690 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1691
1692 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1693 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1694
1695 if (pch_iir & SDE_FDI_MASK_CPT)
1696 for_each_pipe(pipe)
1697 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1698 pipe_name(pipe),
1699 I915_READ(FDI_RX_IIR(pipe)));
1700
1701 if (pch_iir & SDE_ERROR_CPT)
1702 cpt_serr_int_handler(dev);
1703 }
1704
1705 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1706 {
1707 struct drm_i915_private *dev_priv = dev->dev_private;
1708 enum pipe pipe;
1709
1710 if (de_iir & DE_AUX_CHANNEL_A)
1711 dp_aux_irq_handler(dev);
1712
1713 if (de_iir & DE_GSE)
1714 intel_opregion_asle_intr(dev);
1715
1716 if (de_iir & DE_POISON)
1717 DRM_ERROR("Poison interrupt\n");
1718
1719 for_each_pipe(pipe) {
1720 if (de_iir & DE_PIPE_VBLANK(pipe))
1721 drm_handle_vblank(dev, pipe);
1722
1723 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
1724 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1725 DRM_ERROR("Pipe %c FIFO underrun\n",
1726 pipe_name(pipe));
1727
1728 if (de_iir & DE_PIPE_CRC_DONE(pipe))
1729 i9xx_pipe_crc_irq_handler(dev, pipe);
1730
1731 /* plane/pipes map 1:1 on ilk+ */
1732 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
1733 intel_prepare_page_flip(dev, pipe);
1734 intel_finish_page_flip_plane(dev, pipe);
1735 }
1736 }
1737
1738 /* check event from PCH */
1739 if (de_iir & DE_PCH_EVENT) {
1740 u32 pch_iir = I915_READ(SDEIIR);
1741
1742 if (HAS_PCH_CPT(dev))
1743 cpt_irq_handler(dev, pch_iir);
1744 else
1745 ibx_irq_handler(dev, pch_iir);
1746
1747 /* should clear PCH hotplug event before clear CPU irq */
1748 I915_WRITE(SDEIIR, pch_iir);
1749 }
1750
1751 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1752 ironlake_rps_change_irq_handler(dev);
1753 }
1754
1755 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
1756 {
1757 struct drm_i915_private *dev_priv = dev->dev_private;
1758 enum pipe i;
1759
1760 if (de_iir & DE_ERR_INT_IVB)
1761 ivb_err_int_handler(dev);
1762
1763 if (de_iir & DE_AUX_CHANNEL_A_IVB)
1764 dp_aux_irq_handler(dev);
1765
1766 if (de_iir & DE_GSE_IVB)
1767 intel_opregion_asle_intr(dev);
1768
1769 for_each_pipe(i) {
1770 if (de_iir & (DE_PIPE_VBLANK_IVB(i)))
1771 drm_handle_vblank(dev, i);
1772
1773 /* plane/pipes map 1:1 on ilk+ */
1774 if (de_iir & DE_PLANE_FLIP_DONE_IVB(i)) {
1775 intel_prepare_page_flip(dev, i);
1776 intel_finish_page_flip_plane(dev, i);
1777 }
1778 }
1779
1780 /* check event from PCH */
1781 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1782 u32 pch_iir = I915_READ(SDEIIR);
1783
1784 cpt_irq_handler(dev, pch_iir);
1785
1786 /* clear PCH hotplug event before clear CPU irq */
1787 I915_WRITE(SDEIIR, pch_iir);
1788 }
1789 }
1790
1791 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
1792 {
1793 struct drm_device *dev = (struct drm_device *) arg;
1794 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1795 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
1796 irqreturn_t ret = IRQ_NONE;
1797
1798 /* We get interrupts on unclaimed registers, so check for this before we
1799 * do any I915_{READ,WRITE}. */
1800 intel_uncore_check_errors(dev);
1801
1802 /* disable master interrupt before clearing iir */
1803 de_ier = I915_READ(DEIER);
1804 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
1805 POSTING_READ(DEIER);
1806
1807 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1808 * interrupts will will be stored on its back queue, and then we'll be
1809 * able to process them after we restore SDEIER (as soon as we restore
1810 * it, we'll get an interrupt if SDEIIR still has something to process
1811 * due to its back queue). */
1812 if (!HAS_PCH_NOP(dev)) {
1813 sde_ier = I915_READ(SDEIER);
1814 I915_WRITE(SDEIER, 0);
1815 POSTING_READ(SDEIER);
1816 }
1817
1818 gt_iir = I915_READ(GTIIR);
1819 if (gt_iir) {
1820 if (INTEL_INFO(dev)->gen >= 6)
1821 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1822 else
1823 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1824 I915_WRITE(GTIIR, gt_iir);
1825 ret = IRQ_HANDLED;
1826 }
1827
1828 de_iir = I915_READ(DEIIR);
1829 if (de_iir) {
1830 if (INTEL_INFO(dev)->gen >= 7)
1831 ivb_display_irq_handler(dev, de_iir);
1832 else
1833 ilk_display_irq_handler(dev, de_iir);
1834 I915_WRITE(DEIIR, de_iir);
1835 ret = IRQ_HANDLED;
1836 }
1837
1838 if (INTEL_INFO(dev)->gen >= 6) {
1839 u32 pm_iir = I915_READ(GEN6_PMIIR);
1840 if (pm_iir) {
1841 gen6_rps_irq_handler(dev_priv, pm_iir);
1842 I915_WRITE(GEN6_PMIIR, pm_iir);
1843 ret = IRQ_HANDLED;
1844 }
1845 }
1846
1847 I915_WRITE(DEIER, de_ier);
1848 POSTING_READ(DEIER);
1849 if (!HAS_PCH_NOP(dev)) {
1850 I915_WRITE(SDEIER, sde_ier);
1851 POSTING_READ(SDEIER);
1852 }
1853
1854 return ret;
1855 }
1856
1857 static irqreturn_t gen8_irq_handler(int irq, void *arg)
1858 {
1859 struct drm_device *dev = arg;
1860 struct drm_i915_private *dev_priv = dev->dev_private;
1861 u32 master_ctl;
1862 irqreturn_t ret = IRQ_NONE;
1863 uint32_t tmp = 0;
1864 enum pipe pipe;
1865
1866 master_ctl = I915_READ(GEN8_MASTER_IRQ);
1867 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
1868 if (!master_ctl)
1869 return IRQ_NONE;
1870
1871 I915_WRITE(GEN8_MASTER_IRQ, 0);
1872 POSTING_READ(GEN8_MASTER_IRQ);
1873
1874 ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
1875
1876 if (master_ctl & GEN8_DE_MISC_IRQ) {
1877 tmp = I915_READ(GEN8_DE_MISC_IIR);
1878 if (tmp & GEN8_DE_MISC_GSE)
1879 intel_opregion_asle_intr(dev);
1880 else if (tmp)
1881 DRM_ERROR("Unexpected DE Misc interrupt\n");
1882 else
1883 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
1884
1885 if (tmp) {
1886 I915_WRITE(GEN8_DE_MISC_IIR, tmp);
1887 ret = IRQ_HANDLED;
1888 }
1889 }
1890
1891 if (master_ctl & GEN8_DE_PORT_IRQ) {
1892 tmp = I915_READ(GEN8_DE_PORT_IIR);
1893 if (tmp & GEN8_AUX_CHANNEL_A)
1894 dp_aux_irq_handler(dev);
1895 else if (tmp)
1896 DRM_ERROR("Unexpected DE Port interrupt\n");
1897 else
1898 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
1899
1900 if (tmp) {
1901 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
1902 ret = IRQ_HANDLED;
1903 }
1904 }
1905
1906 for_each_pipe(pipe) {
1907 uint32_t pipe_iir;
1908
1909 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
1910 continue;
1911
1912 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
1913 if (pipe_iir & GEN8_PIPE_VBLANK)
1914 drm_handle_vblank(dev, pipe);
1915
1916 if (pipe_iir & GEN8_PIPE_FLIP_DONE) {
1917 intel_prepare_page_flip(dev, pipe);
1918 intel_finish_page_flip_plane(dev, pipe);
1919 }
1920
1921 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
1922 hsw_pipe_crc_irq_handler(dev, pipe);
1923
1924 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
1925 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1926 false))
1927 DRM_ERROR("Pipe %c FIFO underrun\n",
1928 pipe_name(pipe));
1929 }
1930
1931 if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
1932 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
1933 pipe_name(pipe),
1934 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
1935 }
1936
1937 if (pipe_iir) {
1938 ret = IRQ_HANDLED;
1939 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
1940 } else
1941 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
1942 }
1943
1944 if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
1945 /*
1946 * FIXME(BDW): Assume for now that the new interrupt handling
1947 * scheme also closed the SDE interrupt handling race we've seen
1948 * on older pch-split platforms. But this needs testing.
1949 */
1950 u32 pch_iir = I915_READ(SDEIIR);
1951
1952 cpt_irq_handler(dev, pch_iir);
1953
1954 if (pch_iir) {
1955 I915_WRITE(SDEIIR, pch_iir);
1956 ret = IRQ_HANDLED;
1957 }
1958 }
1959
1960 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
1961 POSTING_READ(GEN8_MASTER_IRQ);
1962
1963 return ret;
1964 }
1965
1966 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
1967 bool reset_completed)
1968 {
1969 struct intel_ring_buffer *ring;
1970 int i;
1971
1972 /*
1973 * Notify all waiters for GPU completion events that reset state has
1974 * been changed, and that they need to restart their wait after
1975 * checking for potential errors (and bail out to drop locks if there is
1976 * a gpu reset pending so that i915_error_work_func can acquire them).
1977 */
1978
1979 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
1980 for_each_ring(ring, dev_priv, i)
1981 wake_up_all(&ring->irq_queue);
1982
1983 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
1984 wake_up_all(&dev_priv->pending_flip_queue);
1985
1986 /*
1987 * Signal tasks blocked in i915_gem_wait_for_error that the pending
1988 * reset state is cleared.
1989 */
1990 if (reset_completed)
1991 wake_up_all(&dev_priv->gpu_error.reset_queue);
1992 }
1993
1994 /**
1995 * i915_error_work_func - do process context error handling work
1996 * @work: work struct
1997 *
1998 * Fire an error uevent so userspace can see that a hang or error
1999 * was detected.
2000 */
2001 static void i915_error_work_func(struct work_struct *work)
2002 {
2003 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
2004 work);
2005 drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
2006 gpu_error);
2007 struct drm_device *dev = dev_priv->dev;
2008 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2009 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2010 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2011 int ret;
2012
2013 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2014
2015 /*
2016 * Note that there's only one work item which does gpu resets, so we
2017 * need not worry about concurrent gpu resets potentially incrementing
2018 * error->reset_counter twice. We only need to take care of another
2019 * racing irq/hangcheck declaring the gpu dead for a second time. A
2020 * quick check for that is good enough: schedule_work ensures the
2021 * correct ordering between hang detection and this work item, and since
2022 * the reset in-progress bit is only ever set by code outside of this
2023 * work we don't need to worry about any other races.
2024 */
2025 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2026 DRM_DEBUG_DRIVER("resetting chip\n");
2027 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2028 reset_event);
2029
2030 /*
2031 * All state reset _must_ be completed before we update the
2032 * reset counter, for otherwise waiters might miss the reset
2033 * pending state and not properly drop locks, resulting in
2034 * deadlocks with the reset work.
2035 */
2036 ret = i915_reset(dev);
2037
2038 intel_display_handle_reset(dev);
2039
2040 if (ret == 0) {
2041 /*
2042 * After all the gem state is reset, increment the reset
2043 * counter and wake up everyone waiting for the reset to
2044 * complete.
2045 *
2046 * Since unlock operations are a one-sided barrier only,
2047 * we need to insert a barrier here to order any seqno
2048 * updates before
2049 * the counter increment.
2050 */
2051 smp_mb__before_atomic_inc();
2052 atomic_inc(&dev_priv->gpu_error.reset_counter);
2053
2054 kobject_uevent_env(&dev->primary->kdev->kobj,
2055 KOBJ_CHANGE, reset_done_event);
2056 } else {
2057 atomic_set_mask(I915_WEDGED, &error->reset_counter);
2058 }
2059
2060 /*
2061 * Note: The wake_up also serves as a memory barrier so that
2062 * waiters see the update value of the reset counter atomic_t.
2063 */
2064 i915_error_wake_up(dev_priv, true);
2065 }
2066 }
2067
2068 static void i915_report_and_clear_eir(struct drm_device *dev)
2069 {
2070 struct drm_i915_private *dev_priv = dev->dev_private;
2071 uint32_t instdone[I915_NUM_INSTDONE_REG];
2072 u32 eir = I915_READ(EIR);
2073 int pipe, i;
2074
2075 if (!eir)
2076 return;
2077
2078 pr_err("render error detected, EIR: 0x%08x\n", eir);
2079
2080 i915_get_extra_instdone(dev, instdone);
2081
2082 if (IS_G4X(dev)) {
2083 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2084 u32 ipeir = I915_READ(IPEIR_I965);
2085
2086 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2087 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2088 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2089 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2090 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2091 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2092 I915_WRITE(IPEIR_I965, ipeir);
2093 POSTING_READ(IPEIR_I965);
2094 }
2095 if (eir & GM45_ERROR_PAGE_TABLE) {
2096 u32 pgtbl_err = I915_READ(PGTBL_ER);
2097 pr_err("page table error\n");
2098 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2099 I915_WRITE(PGTBL_ER, pgtbl_err);
2100 POSTING_READ(PGTBL_ER);
2101 }
2102 }
2103
2104 if (!IS_GEN2(dev)) {
2105 if (eir & I915_ERROR_PAGE_TABLE) {
2106 u32 pgtbl_err = I915_READ(PGTBL_ER);
2107 pr_err("page table error\n");
2108 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2109 I915_WRITE(PGTBL_ER, pgtbl_err);
2110 POSTING_READ(PGTBL_ER);
2111 }
2112 }
2113
2114 if (eir & I915_ERROR_MEMORY_REFRESH) {
2115 pr_err("memory refresh error:\n");
2116 for_each_pipe(pipe)
2117 pr_err("pipe %c stat: 0x%08x\n",
2118 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2119 /* pipestat has already been acked */
2120 }
2121 if (eir & I915_ERROR_INSTRUCTION) {
2122 pr_err("instruction error\n");
2123 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
2124 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2125 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2126 if (INTEL_INFO(dev)->gen < 4) {
2127 u32 ipeir = I915_READ(IPEIR);
2128
2129 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2130 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
2131 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
2132 I915_WRITE(IPEIR, ipeir);
2133 POSTING_READ(IPEIR);
2134 } else {
2135 u32 ipeir = I915_READ(IPEIR_I965);
2136
2137 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2138 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2139 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2140 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2141 I915_WRITE(IPEIR_I965, ipeir);
2142 POSTING_READ(IPEIR_I965);
2143 }
2144 }
2145
2146 I915_WRITE(EIR, eir);
2147 POSTING_READ(EIR);
2148 eir = I915_READ(EIR);
2149 if (eir) {
2150 /*
2151 * some errors might have become stuck,
2152 * mask them.
2153 */
2154 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2155 I915_WRITE(EMR, I915_READ(EMR) | eir);
2156 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2157 }
2158 }
2159
2160 /**
2161 * i915_handle_error - handle an error interrupt
2162 * @dev: drm device
2163 *
2164 * Do some basic checking of regsiter state at error interrupt time and
2165 * dump it to the syslog. Also call i915_capture_error_state() to make
2166 * sure we get a record and make it available in debugfs. Fire a uevent
2167 * so userspace knows something bad happened (should trigger collection
2168 * of a ring dump etc.).
2169 */
2170 void i915_handle_error(struct drm_device *dev, bool wedged)
2171 {
2172 struct drm_i915_private *dev_priv = dev->dev_private;
2173
2174 i915_capture_error_state(dev);
2175 i915_report_and_clear_eir(dev);
2176
2177 if (wedged) {
2178 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2179 &dev_priv->gpu_error.reset_counter);
2180
2181 /*
2182 * Wakeup waiting processes so that the reset work function
2183 * i915_error_work_func doesn't deadlock trying to grab various
2184 * locks. By bumping the reset counter first, the woken
2185 * processes will see a reset in progress and back off,
2186 * releasing their locks and then wait for the reset completion.
2187 * We must do this for _all_ gpu waiters that might hold locks
2188 * that the reset work needs to acquire.
2189 *
2190 * Note: The wake_up serves as the required memory barrier to
2191 * ensure that the waiters see the updated value of the reset
2192 * counter atomic_t.
2193 */
2194 i915_error_wake_up(dev_priv, false);
2195 }
2196
2197 /*
2198 * Our reset work can grab modeset locks (since it needs to reset the
2199 * state of outstanding pagelips). Hence it must not be run on our own
2200 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2201 * code will deadlock.
2202 */
2203 schedule_work(&dev_priv->gpu_error.work);
2204 }
2205
2206 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
2207 {
2208 drm_i915_private_t *dev_priv = dev->dev_private;
2209 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2211 struct drm_i915_gem_object *obj;
2212 struct intel_unpin_work *work;
2213 unsigned long flags;
2214 bool stall_detected;
2215
2216 /* Ignore early vblank irqs */
2217 if (intel_crtc == NULL)
2218 return;
2219
2220 spin_lock_irqsave(&dev->event_lock, flags);
2221 work = intel_crtc->unpin_work;
2222
2223 if (work == NULL ||
2224 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2225 !work->enable_stall_check) {
2226 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2227 spin_unlock_irqrestore(&dev->event_lock, flags);
2228 return;
2229 }
2230
2231 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2232 obj = work->pending_flip_obj;
2233 if (INTEL_INFO(dev)->gen >= 4) {
2234 int dspsurf = DSPSURF(intel_crtc->plane);
2235 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
2236 i915_gem_obj_ggtt_offset(obj);
2237 } else {
2238 int dspaddr = DSPADDR(intel_crtc->plane);
2239 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
2240 crtc->y * crtc->fb->pitches[0] +
2241 crtc->x * crtc->fb->bits_per_pixel/8);
2242 }
2243
2244 spin_unlock_irqrestore(&dev->event_lock, flags);
2245
2246 if (stall_detected) {
2247 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2248 intel_prepare_page_flip(dev, intel_crtc->plane);
2249 }
2250 }
2251
2252 /* Called from drm generic code, passed 'crtc' which
2253 * we use as a pipe index
2254 */
2255 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2256 {
2257 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2258 unsigned long irqflags;
2259
2260 if (!i915_pipe_enabled(dev, pipe))
2261 return -EINVAL;
2262
2263 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2264 if (INTEL_INFO(dev)->gen >= 4)
2265 i915_enable_pipestat(dev_priv, pipe,
2266 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2267 else
2268 i915_enable_pipestat(dev_priv, pipe,
2269 PIPE_VBLANK_INTERRUPT_ENABLE);
2270
2271 /* maintain vblank delivery even in deep C-states */
2272 if (dev_priv->info->gen == 3)
2273 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
2274 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2275
2276 return 0;
2277 }
2278
2279 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2280 {
2281 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2282 unsigned long irqflags;
2283 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2284 DE_PIPE_VBLANK(pipe);
2285
2286 if (!i915_pipe_enabled(dev, pipe))
2287 return -EINVAL;
2288
2289 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2290 ironlake_enable_display_irq(dev_priv, bit);
2291 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2292
2293 return 0;
2294 }
2295
2296 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2297 {
2298 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2299 unsigned long irqflags;
2300 u32 imr;
2301
2302 if (!i915_pipe_enabled(dev, pipe))
2303 return -EINVAL;
2304
2305 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2306 imr = I915_READ(VLV_IMR);
2307 if (pipe == PIPE_A)
2308 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
2309 else
2310 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2311 I915_WRITE(VLV_IMR, imr);
2312 i915_enable_pipestat(dev_priv, pipe,
2313 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2314 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2315
2316 return 0;
2317 }
2318
2319 static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2320 {
2321 struct drm_i915_private *dev_priv = dev->dev_private;
2322 unsigned long irqflags;
2323
2324 if (!i915_pipe_enabled(dev, pipe))
2325 return -EINVAL;
2326
2327 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2328 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2329 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2330 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2331 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2332 return 0;
2333 }
2334
2335 /* Called from drm generic code, passed 'crtc' which
2336 * we use as a pipe index
2337 */
2338 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2339 {
2340 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2341 unsigned long irqflags;
2342
2343 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2344 if (dev_priv->info->gen == 3)
2345 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
2346
2347 i915_disable_pipestat(dev_priv, pipe,
2348 PIPE_VBLANK_INTERRUPT_ENABLE |
2349 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2350 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2351 }
2352
2353 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2354 {
2355 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2356 unsigned long irqflags;
2357 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2358 DE_PIPE_VBLANK(pipe);
2359
2360 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2361 ironlake_disable_display_irq(dev_priv, bit);
2362 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2363 }
2364
2365 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2366 {
2367 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2368 unsigned long irqflags;
2369 u32 imr;
2370
2371 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2372 i915_disable_pipestat(dev_priv, pipe,
2373 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2374 imr = I915_READ(VLV_IMR);
2375 if (pipe == PIPE_A)
2376 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
2377 else
2378 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2379 I915_WRITE(VLV_IMR, imr);
2380 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2381 }
2382
2383 static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2384 {
2385 struct drm_i915_private *dev_priv = dev->dev_private;
2386 unsigned long irqflags;
2387
2388 if (!i915_pipe_enabled(dev, pipe))
2389 return;
2390
2391 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2392 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2393 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2394 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2395 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2396 }
2397
2398 static u32
2399 ring_last_seqno(struct intel_ring_buffer *ring)
2400 {
2401 return list_entry(ring->request_list.prev,
2402 struct drm_i915_gem_request, list)->seqno;
2403 }
2404
2405 static bool
2406 ring_idle(struct intel_ring_buffer *ring, u32 seqno)
2407 {
2408 return (list_empty(&ring->request_list) ||
2409 i915_seqno_passed(seqno, ring_last_seqno(ring)));
2410 }
2411
2412 static struct intel_ring_buffer *
2413 semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
2414 {
2415 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2416 u32 cmd, ipehr, acthd, acthd_min;
2417
2418 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2419 if ((ipehr & ~(0x3 << 16)) !=
2420 (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
2421 return NULL;
2422
2423 /* ACTHD is likely pointing to the dword after the actual command,
2424 * so scan backwards until we find the MBOX.
2425 */
2426 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
2427 acthd_min = max((int)acthd - 3 * 4, 0);
2428 do {
2429 cmd = ioread32(ring->virtual_start + acthd);
2430 if (cmd == ipehr)
2431 break;
2432
2433 acthd -= 4;
2434 if (acthd < acthd_min)
2435 return NULL;
2436 } while (1);
2437
2438 *seqno = ioread32(ring->virtual_start+acthd+4)+1;
2439 return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
2440 }
2441
2442 static int semaphore_passed(struct intel_ring_buffer *ring)
2443 {
2444 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2445 struct intel_ring_buffer *signaller;
2446 u32 seqno, ctl;
2447
2448 ring->hangcheck.deadlock = true;
2449
2450 signaller = semaphore_waits_for(ring, &seqno);
2451 if (signaller == NULL || signaller->hangcheck.deadlock)
2452 return -1;
2453
2454 /* cursory check for an unkickable deadlock */
2455 ctl = I915_READ_CTL(signaller);
2456 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2457 return -1;
2458
2459 return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
2460 }
2461
2462 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2463 {
2464 struct intel_ring_buffer *ring;
2465 int i;
2466
2467 for_each_ring(ring, dev_priv, i)
2468 ring->hangcheck.deadlock = false;
2469 }
2470
2471 static enum intel_ring_hangcheck_action
2472 ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
2473 {
2474 struct drm_device *dev = ring->dev;
2475 struct drm_i915_private *dev_priv = dev->dev_private;
2476 u32 tmp;
2477
2478 if (ring->hangcheck.acthd != acthd)
2479 return HANGCHECK_ACTIVE;
2480
2481 if (IS_GEN2(dev))
2482 return HANGCHECK_HUNG;
2483
2484 /* Is the chip hanging on a WAIT_FOR_EVENT?
2485 * If so we can simply poke the RB_WAIT bit
2486 * and break the hang. This should work on
2487 * all but the second generation chipsets.
2488 */
2489 tmp = I915_READ_CTL(ring);
2490 if (tmp & RING_WAIT) {
2491 DRM_ERROR("Kicking stuck wait on %s\n",
2492 ring->name);
2493 i915_handle_error(dev, false);
2494 I915_WRITE_CTL(ring, tmp);
2495 return HANGCHECK_KICK;
2496 }
2497
2498 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2499 switch (semaphore_passed(ring)) {
2500 default:
2501 return HANGCHECK_HUNG;
2502 case 1:
2503 DRM_ERROR("Kicking stuck semaphore on %s\n",
2504 ring->name);
2505 i915_handle_error(dev, false);
2506 I915_WRITE_CTL(ring, tmp);
2507 return HANGCHECK_KICK;
2508 case 0:
2509 return HANGCHECK_WAIT;
2510 }
2511 }
2512
2513 return HANGCHECK_HUNG;
2514 }
2515
2516 /**
2517 * This is called when the chip hasn't reported back with completed
2518 * batchbuffers in a long time. We keep track per ring seqno progress and
2519 * if there are no progress, hangcheck score for that ring is increased.
2520 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2521 * we kick the ring. If we see no progress on three subsequent calls
2522 * we assume chip is wedged and try to fix it by resetting the chip.
2523 */
2524 static void i915_hangcheck_elapsed(unsigned long data)
2525 {
2526 struct drm_device *dev = (struct drm_device *)data;
2527 drm_i915_private_t *dev_priv = dev->dev_private;
2528 struct intel_ring_buffer *ring;
2529 int i;
2530 int busy_count = 0, rings_hung = 0;
2531 bool stuck[I915_NUM_RINGS] = { 0 };
2532 #define BUSY 1
2533 #define KICK 5
2534 #define HUNG 20
2535
2536 if (!i915.enable_hangcheck)
2537 return;
2538
2539 for_each_ring(ring, dev_priv, i) {
2540 u32 seqno, acthd;
2541 bool busy = true;
2542
2543 semaphore_clear_deadlocks(dev_priv);
2544
2545 seqno = ring->get_seqno(ring, false);
2546 acthd = intel_ring_get_active_head(ring);
2547
2548 if (ring->hangcheck.seqno == seqno) {
2549 if (ring_idle(ring, seqno)) {
2550 ring->hangcheck.action = HANGCHECK_IDLE;
2551
2552 if (waitqueue_active(&ring->irq_queue)) {
2553 /* Issue a wake-up to catch stuck h/w. */
2554 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2555 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2556 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2557 ring->name);
2558 else
2559 DRM_INFO("Fake missed irq on %s\n",
2560 ring->name);
2561 wake_up_all(&ring->irq_queue);
2562 }
2563 /* Safeguard against driver failure */
2564 ring->hangcheck.score += BUSY;
2565 } else
2566 busy = false;
2567 } else {
2568 /* We always increment the hangcheck score
2569 * if the ring is busy and still processing
2570 * the same request, so that no single request
2571 * can run indefinitely (such as a chain of
2572 * batches). The only time we do not increment
2573 * the hangcheck score on this ring, if this
2574 * ring is in a legitimate wait for another
2575 * ring. In that case the waiting ring is a
2576 * victim and we want to be sure we catch the
2577 * right culprit. Then every time we do kick
2578 * the ring, add a small increment to the
2579 * score so that we can catch a batch that is
2580 * being repeatedly kicked and so responsible
2581 * for stalling the machine.
2582 */
2583 ring->hangcheck.action = ring_stuck(ring,
2584 acthd);
2585
2586 switch (ring->hangcheck.action) {
2587 case HANGCHECK_IDLE:
2588 case HANGCHECK_WAIT:
2589 break;
2590 case HANGCHECK_ACTIVE:
2591 ring->hangcheck.score += BUSY;
2592 break;
2593 case HANGCHECK_KICK:
2594 ring->hangcheck.score += KICK;
2595 break;
2596 case HANGCHECK_HUNG:
2597 ring->hangcheck.score += HUNG;
2598 stuck[i] = true;
2599 break;
2600 }
2601 }
2602 } else {
2603 ring->hangcheck.action = HANGCHECK_ACTIVE;
2604
2605 /* Gradually reduce the count so that we catch DoS
2606 * attempts across multiple batches.
2607 */
2608 if (ring->hangcheck.score > 0)
2609 ring->hangcheck.score--;
2610 }
2611
2612 ring->hangcheck.seqno = seqno;
2613 ring->hangcheck.acthd = acthd;
2614 busy_count += busy;
2615 }
2616
2617 for_each_ring(ring, dev_priv, i) {
2618 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
2619 DRM_INFO("%s on %s\n",
2620 stuck[i] ? "stuck" : "no progress",
2621 ring->name);
2622 rings_hung++;
2623 }
2624 }
2625
2626 if (rings_hung)
2627 return i915_handle_error(dev, true);
2628
2629 if (busy_count)
2630 /* Reset timer case chip hangs without another request
2631 * being added */
2632 i915_queue_hangcheck(dev);
2633 }
2634
2635 void i915_queue_hangcheck(struct drm_device *dev)
2636 {
2637 struct drm_i915_private *dev_priv = dev->dev_private;
2638 if (!i915.enable_hangcheck)
2639 return;
2640
2641 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2642 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2643 }
2644
2645 static void ibx_irq_preinstall(struct drm_device *dev)
2646 {
2647 struct drm_i915_private *dev_priv = dev->dev_private;
2648
2649 if (HAS_PCH_NOP(dev))
2650 return;
2651
2652 /* south display irq */
2653 I915_WRITE(SDEIMR, 0xffffffff);
2654 /*
2655 * SDEIER is also touched by the interrupt handler to work around missed
2656 * PCH interrupts. Hence we can't update it after the interrupt handler
2657 * is enabled - instead we unconditionally enable all PCH interrupt
2658 * sources here, but then only unmask them as needed with SDEIMR.
2659 */
2660 I915_WRITE(SDEIER, 0xffffffff);
2661 POSTING_READ(SDEIER);
2662 }
2663
2664 static void gen5_gt_irq_preinstall(struct drm_device *dev)
2665 {
2666 struct drm_i915_private *dev_priv = dev->dev_private;
2667
2668 /* and GT */
2669 I915_WRITE(GTIMR, 0xffffffff);
2670 I915_WRITE(GTIER, 0x0);
2671 POSTING_READ(GTIER);
2672
2673 if (INTEL_INFO(dev)->gen >= 6) {
2674 /* and PM */
2675 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2676 I915_WRITE(GEN6_PMIER, 0x0);
2677 POSTING_READ(GEN6_PMIER);
2678 }
2679 }
2680
2681 /* drm_dma.h hooks
2682 */
2683 static void ironlake_irq_preinstall(struct drm_device *dev)
2684 {
2685 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2686
2687 I915_WRITE(HWSTAM, 0xeffe);
2688
2689 I915_WRITE(DEIMR, 0xffffffff);
2690 I915_WRITE(DEIER, 0x0);
2691 POSTING_READ(DEIER);
2692
2693 gen5_gt_irq_preinstall(dev);
2694
2695 ibx_irq_preinstall(dev);
2696 }
2697
2698 static void valleyview_irq_preinstall(struct drm_device *dev)
2699 {
2700 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2701 int pipe;
2702
2703 /* VLV magic */
2704 I915_WRITE(VLV_IMR, 0);
2705 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2706 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2707 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2708
2709 /* and GT */
2710 I915_WRITE(GTIIR, I915_READ(GTIIR));
2711 I915_WRITE(GTIIR, I915_READ(GTIIR));
2712
2713 gen5_gt_irq_preinstall(dev);
2714
2715 I915_WRITE(DPINVGTT, 0xff);
2716
2717 I915_WRITE(PORT_HOTPLUG_EN, 0);
2718 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2719 for_each_pipe(pipe)
2720 I915_WRITE(PIPESTAT(pipe), 0xffff);
2721 I915_WRITE(VLV_IIR, 0xffffffff);
2722 I915_WRITE(VLV_IMR, 0xffffffff);
2723 I915_WRITE(VLV_IER, 0x0);
2724 POSTING_READ(VLV_IER);
2725 }
2726
2727 static void gen8_irq_preinstall(struct drm_device *dev)
2728 {
2729 struct drm_i915_private *dev_priv = dev->dev_private;
2730 int pipe;
2731
2732 I915_WRITE(GEN8_MASTER_IRQ, 0);
2733 POSTING_READ(GEN8_MASTER_IRQ);
2734
2735 /* IIR can theoretically queue up two events. Be paranoid */
2736 #define GEN8_IRQ_INIT_NDX(type, which) do { \
2737 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
2738 POSTING_READ(GEN8_##type##_IMR(which)); \
2739 I915_WRITE(GEN8_##type##_IER(which), 0); \
2740 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
2741 POSTING_READ(GEN8_##type##_IIR(which)); \
2742 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
2743 } while (0)
2744
2745 #define GEN8_IRQ_INIT(type) do { \
2746 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
2747 POSTING_READ(GEN8_##type##_IMR); \
2748 I915_WRITE(GEN8_##type##_IER, 0); \
2749 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
2750 POSTING_READ(GEN8_##type##_IIR); \
2751 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
2752 } while (0)
2753
2754 GEN8_IRQ_INIT_NDX(GT, 0);
2755 GEN8_IRQ_INIT_NDX(GT, 1);
2756 GEN8_IRQ_INIT_NDX(GT, 2);
2757 GEN8_IRQ_INIT_NDX(GT, 3);
2758
2759 for_each_pipe(pipe) {
2760 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe);
2761 }
2762
2763 GEN8_IRQ_INIT(DE_PORT);
2764 GEN8_IRQ_INIT(DE_MISC);
2765 GEN8_IRQ_INIT(PCU);
2766 #undef GEN8_IRQ_INIT
2767 #undef GEN8_IRQ_INIT_NDX
2768
2769 POSTING_READ(GEN8_PCU_IIR);
2770
2771 ibx_irq_preinstall(dev);
2772 }
2773
2774 static void ibx_hpd_irq_setup(struct drm_device *dev)
2775 {
2776 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2777 struct drm_mode_config *mode_config = &dev->mode_config;
2778 struct intel_encoder *intel_encoder;
2779 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
2780
2781 if (HAS_PCH_IBX(dev)) {
2782 hotplug_irqs = SDE_HOTPLUG_MASK;
2783 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2784 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2785 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
2786 } else {
2787 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
2788 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2789 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2790 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
2791 }
2792
2793 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
2794
2795 /*
2796 * Enable digital hotplug on the PCH, and configure the DP short pulse
2797 * duration to 2ms (which is the minimum in the Display Port spec)
2798 *
2799 * This register is the same on all known PCH chips.
2800 */
2801 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2802 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2803 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2804 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2805 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2806 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2807 }
2808
2809 static void ibx_irq_postinstall(struct drm_device *dev)
2810 {
2811 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2812 u32 mask;
2813
2814 if (HAS_PCH_NOP(dev))
2815 return;
2816
2817 if (HAS_PCH_IBX(dev)) {
2818 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
2819 SDE_TRANSA_FIFO_UNDER | SDE_POISON;
2820 } else {
2821 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2822
2823 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2824 }
2825
2826 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2827 I915_WRITE(SDEIMR, ~mask);
2828 }
2829
2830 static void gen5_gt_irq_postinstall(struct drm_device *dev)
2831 {
2832 struct drm_i915_private *dev_priv = dev->dev_private;
2833 u32 pm_irqs, gt_irqs;
2834
2835 pm_irqs = gt_irqs = 0;
2836
2837 dev_priv->gt_irq_mask = ~0;
2838 if (HAS_L3_DPF(dev)) {
2839 /* L3 parity interrupt is always unmasked. */
2840 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
2841 gt_irqs |= GT_PARITY_ERROR(dev);
2842 }
2843
2844 gt_irqs |= GT_RENDER_USER_INTERRUPT;
2845 if (IS_GEN5(dev)) {
2846 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
2847 ILK_BSD_USER_INTERRUPT;
2848 } else {
2849 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
2850 }
2851
2852 I915_WRITE(GTIIR, I915_READ(GTIIR));
2853 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2854 I915_WRITE(GTIER, gt_irqs);
2855 POSTING_READ(GTIER);
2856
2857 if (INTEL_INFO(dev)->gen >= 6) {
2858 pm_irqs |= GEN6_PM_RPS_EVENTS;
2859
2860 if (HAS_VEBOX(dev))
2861 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
2862
2863 dev_priv->pm_irq_mask = 0xffffffff;
2864 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2865 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
2866 I915_WRITE(GEN6_PMIER, pm_irqs);
2867 POSTING_READ(GEN6_PMIER);
2868 }
2869 }
2870
2871 static int ironlake_irq_postinstall(struct drm_device *dev)
2872 {
2873 unsigned long irqflags;
2874 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2875 u32 display_mask, extra_mask;
2876
2877 if (INTEL_INFO(dev)->gen >= 7) {
2878 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
2879 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
2880 DE_PLANEB_FLIP_DONE_IVB |
2881 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB |
2882 DE_ERR_INT_IVB);
2883 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
2884 DE_PIPEA_VBLANK_IVB);
2885
2886 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2887 } else {
2888 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2889 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
2890 DE_AUX_CHANNEL_A |
2891 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
2892 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
2893 DE_POISON);
2894 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT;
2895 }
2896
2897 dev_priv->irq_mask = ~display_mask;
2898
2899 /* should always can generate irq */
2900 I915_WRITE(DEIIR, I915_READ(DEIIR));
2901 I915_WRITE(DEIMR, dev_priv->irq_mask);
2902 I915_WRITE(DEIER, display_mask | extra_mask);
2903 POSTING_READ(DEIER);
2904
2905 gen5_gt_irq_postinstall(dev);
2906
2907 ibx_irq_postinstall(dev);
2908
2909 if (IS_IRONLAKE_M(dev)) {
2910 /* Enable PCU event interrupts
2911 *
2912 * spinlocking not required here for correctness since interrupt
2913 * setup is guaranteed to run in single-threaded context. But we
2914 * need it to make the assert_spin_locked happy. */
2915 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2916 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2917 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2918 }
2919
2920 return 0;
2921 }
2922
2923 static int valleyview_irq_postinstall(struct drm_device *dev)
2924 {
2925 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2926 u32 enable_mask;
2927 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV |
2928 PIPE_CRC_DONE_ENABLE;
2929 unsigned long irqflags;
2930
2931 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
2932 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2933 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2934 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2935 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2936
2937 /*
2938 *Leave vblank interrupts masked initially. enable/disable will
2939 * toggle them based on usage.
2940 */
2941 dev_priv->irq_mask = (~enable_mask) |
2942 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2943 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2944
2945 I915_WRITE(PORT_HOTPLUG_EN, 0);
2946 POSTING_READ(PORT_HOTPLUG_EN);
2947
2948 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2949 I915_WRITE(VLV_IER, enable_mask);
2950 I915_WRITE(VLV_IIR, 0xffffffff);
2951 I915_WRITE(PIPESTAT(0), 0xffff);
2952 I915_WRITE(PIPESTAT(1), 0xffff);
2953 POSTING_READ(VLV_IER);
2954
2955 /* Interrupt setup is already guaranteed to be single-threaded, this is
2956 * just to make the assert_spin_locked check happy. */
2957 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2958 i915_enable_pipestat(dev_priv, PIPE_A, pipestat_enable);
2959 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE);
2960 i915_enable_pipestat(dev_priv, PIPE_B, pipestat_enable);
2961 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2962
2963 I915_WRITE(VLV_IIR, 0xffffffff);
2964 I915_WRITE(VLV_IIR, 0xffffffff);
2965
2966 gen5_gt_irq_postinstall(dev);
2967
2968 /* ack & enable invalid PTE error interrupts */
2969 #if 0 /* FIXME: add support to irq handler for checking these bits */
2970 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2971 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2972 #endif
2973
2974 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2975
2976 return 0;
2977 }
2978
2979 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
2980 {
2981 int i;
2982
2983 /* These are interrupts we'll toggle with the ring mask register */
2984 uint32_t gt_interrupts[] = {
2985 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
2986 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
2987 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
2988 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
2989 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
2990 0,
2991 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT
2992 };
2993
2994 for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) {
2995 u32 tmp = I915_READ(GEN8_GT_IIR(i));
2996 if (tmp)
2997 DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
2998 i, tmp);
2999 I915_WRITE(GEN8_GT_IMR(i), ~gt_interrupts[i]);
3000 I915_WRITE(GEN8_GT_IER(i), gt_interrupts[i]);
3001 }
3002 POSTING_READ(GEN8_GT_IER(0));
3003 }
3004
3005 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3006 {
3007 struct drm_device *dev = dev_priv->dev;
3008 uint32_t de_pipe_masked = GEN8_PIPE_FLIP_DONE |
3009 GEN8_PIPE_CDCLK_CRC_DONE |
3010 GEN8_PIPE_FIFO_UNDERRUN |
3011 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3012 uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK;
3013 int pipe;
3014 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3015 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3016 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3017
3018 for_each_pipe(pipe) {
3019 u32 tmp = I915_READ(GEN8_DE_PIPE_IIR(pipe));
3020 if (tmp)
3021 DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
3022 pipe, tmp);
3023 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
3024 I915_WRITE(GEN8_DE_PIPE_IER(pipe), de_pipe_enables);
3025 }
3026 POSTING_READ(GEN8_DE_PIPE_ISR(0));
3027
3028 I915_WRITE(GEN8_DE_PORT_IMR, ~GEN8_AUX_CHANNEL_A);
3029 I915_WRITE(GEN8_DE_PORT_IER, GEN8_AUX_CHANNEL_A);
3030 POSTING_READ(GEN8_DE_PORT_IER);
3031 }
3032
3033 static int gen8_irq_postinstall(struct drm_device *dev)
3034 {
3035 struct drm_i915_private *dev_priv = dev->dev_private;
3036
3037 gen8_gt_irq_postinstall(dev_priv);
3038 gen8_de_irq_postinstall(dev_priv);
3039
3040 ibx_irq_postinstall(dev);
3041
3042 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3043 POSTING_READ(GEN8_MASTER_IRQ);
3044
3045 return 0;
3046 }
3047
3048 static void gen8_irq_uninstall(struct drm_device *dev)
3049 {
3050 struct drm_i915_private *dev_priv = dev->dev_private;
3051 int pipe;
3052
3053 if (!dev_priv)
3054 return;
3055
3056 I915_WRITE(GEN8_MASTER_IRQ, 0);
3057
3058 #define GEN8_IRQ_FINI_NDX(type, which) do { \
3059 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
3060 I915_WRITE(GEN8_##type##_IER(which), 0); \
3061 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
3062 } while (0)
3063
3064 #define GEN8_IRQ_FINI(type) do { \
3065 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
3066 I915_WRITE(GEN8_##type##_IER, 0); \
3067 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
3068 } while (0)
3069
3070 GEN8_IRQ_FINI_NDX(GT, 0);
3071 GEN8_IRQ_FINI_NDX(GT, 1);
3072 GEN8_IRQ_FINI_NDX(GT, 2);
3073 GEN8_IRQ_FINI_NDX(GT, 3);
3074
3075 for_each_pipe(pipe) {
3076 GEN8_IRQ_FINI_NDX(DE_PIPE, pipe);
3077 }
3078
3079 GEN8_IRQ_FINI(DE_PORT);
3080 GEN8_IRQ_FINI(DE_MISC);
3081 GEN8_IRQ_FINI(PCU);
3082 #undef GEN8_IRQ_FINI
3083 #undef GEN8_IRQ_FINI_NDX
3084
3085 POSTING_READ(GEN8_PCU_IIR);
3086 }
3087
3088 static void valleyview_irq_uninstall(struct drm_device *dev)
3089 {
3090 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3091 int pipe;
3092
3093 if (!dev_priv)
3094 return;
3095
3096 intel_hpd_irq_uninstall(dev_priv);
3097
3098 for_each_pipe(pipe)
3099 I915_WRITE(PIPESTAT(pipe), 0xffff);
3100
3101 I915_WRITE(HWSTAM, 0xffffffff);
3102 I915_WRITE(PORT_HOTPLUG_EN, 0);
3103 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3104 for_each_pipe(pipe)
3105 I915_WRITE(PIPESTAT(pipe), 0xffff);
3106 I915_WRITE(VLV_IIR, 0xffffffff);
3107 I915_WRITE(VLV_IMR, 0xffffffff);
3108 I915_WRITE(VLV_IER, 0x0);
3109 POSTING_READ(VLV_IER);
3110 }
3111
3112 static void ironlake_irq_uninstall(struct drm_device *dev)
3113 {
3114 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3115
3116 if (!dev_priv)
3117 return;
3118
3119 intel_hpd_irq_uninstall(dev_priv);
3120
3121 I915_WRITE(HWSTAM, 0xffffffff);
3122
3123 I915_WRITE(DEIMR, 0xffffffff);
3124 I915_WRITE(DEIER, 0x0);
3125 I915_WRITE(DEIIR, I915_READ(DEIIR));
3126 if (IS_GEN7(dev))
3127 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
3128
3129 I915_WRITE(GTIMR, 0xffffffff);
3130 I915_WRITE(GTIER, 0x0);
3131 I915_WRITE(GTIIR, I915_READ(GTIIR));
3132
3133 if (HAS_PCH_NOP(dev))
3134 return;
3135
3136 I915_WRITE(SDEIMR, 0xffffffff);
3137 I915_WRITE(SDEIER, 0x0);
3138 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
3139 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3140 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
3141 }
3142
3143 static void i8xx_irq_preinstall(struct drm_device * dev)
3144 {
3145 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3146 int pipe;
3147
3148 for_each_pipe(pipe)
3149 I915_WRITE(PIPESTAT(pipe), 0);
3150 I915_WRITE16(IMR, 0xffff);
3151 I915_WRITE16(IER, 0x0);
3152 POSTING_READ16(IER);
3153 }
3154
3155 static int i8xx_irq_postinstall(struct drm_device *dev)
3156 {
3157 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3158 unsigned long irqflags;
3159
3160 I915_WRITE16(EMR,
3161 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3162
3163 /* Unmask the interrupts that we always want on. */
3164 dev_priv->irq_mask =
3165 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3166 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3167 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3168 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3169 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3170 I915_WRITE16(IMR, dev_priv->irq_mask);
3171
3172 I915_WRITE16(IER,
3173 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3174 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3175 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3176 I915_USER_INTERRUPT);
3177 POSTING_READ16(IER);
3178
3179 /* Interrupt setup is already guaranteed to be single-threaded, this is
3180 * just to make the assert_spin_locked check happy. */
3181 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3182 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
3183 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
3184 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3185
3186 return 0;
3187 }
3188
3189 /*
3190 * Returns true when a page flip has completed.
3191 */
3192 static bool i8xx_handle_vblank(struct drm_device *dev,
3193 int plane, int pipe, u32 iir)
3194 {
3195 drm_i915_private_t *dev_priv = dev->dev_private;
3196 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3197
3198 if (!drm_handle_vblank(dev, pipe))
3199 return false;
3200
3201 if ((iir & flip_pending) == 0)
3202 return false;
3203
3204 intel_prepare_page_flip(dev, plane);
3205
3206 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3207 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3208 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3209 * the flip is completed (no longer pending). Since this doesn't raise
3210 * an interrupt per se, we watch for the change at vblank.
3211 */
3212 if (I915_READ16(ISR) & flip_pending)
3213 return false;
3214
3215 intel_finish_page_flip(dev, pipe);
3216
3217 return true;
3218 }
3219
3220 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3221 {
3222 struct drm_device *dev = (struct drm_device *) arg;
3223 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3224 u16 iir, new_iir;
3225 u32 pipe_stats[2];
3226 unsigned long irqflags;
3227 int pipe;
3228 u16 flip_mask =
3229 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3230 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3231
3232 iir = I915_READ16(IIR);
3233 if (iir == 0)
3234 return IRQ_NONE;
3235
3236 while (iir & ~flip_mask) {
3237 /* Can't rely on pipestat interrupt bit in iir as it might
3238 * have been cleared after the pipestat interrupt was received.
3239 * It doesn't set the bit in iir again, but it still produces
3240 * interrupts (for non-MSI).
3241 */
3242 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3243 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3244 i915_handle_error(dev, false);
3245
3246 for_each_pipe(pipe) {
3247 int reg = PIPESTAT(pipe);
3248 pipe_stats[pipe] = I915_READ(reg);
3249
3250 /*
3251 * Clear the PIPE*STAT regs before the IIR
3252 */
3253 if (pipe_stats[pipe] & 0x8000ffff)
3254 I915_WRITE(reg, pipe_stats[pipe]);
3255 }
3256 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3257
3258 I915_WRITE16(IIR, iir & ~flip_mask);
3259 new_iir = I915_READ16(IIR); /* Flush posted writes */
3260
3261 i915_update_dri1_breadcrumb(dev);
3262
3263 if (iir & I915_USER_INTERRUPT)
3264 notify_ring(dev, &dev_priv->ring[RCS]);
3265
3266 for_each_pipe(pipe) {
3267 int plane = pipe;
3268 if (HAS_FBC(dev))
3269 plane = !plane;
3270
3271 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3272 i8xx_handle_vblank(dev, plane, pipe, iir))
3273 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3274
3275 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3276 i9xx_pipe_crc_irq_handler(dev, pipe);
3277
3278 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3279 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3280 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3281 }
3282
3283 iir = new_iir;
3284 }
3285
3286 return IRQ_HANDLED;
3287 }
3288
3289 static void i8xx_irq_uninstall(struct drm_device * dev)
3290 {
3291 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3292 int pipe;
3293
3294 for_each_pipe(pipe) {
3295 /* Clear enable bits; then clear status bits */
3296 I915_WRITE(PIPESTAT(pipe), 0);
3297 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3298 }
3299 I915_WRITE16(IMR, 0xffff);
3300 I915_WRITE16(IER, 0x0);
3301 I915_WRITE16(IIR, I915_READ16(IIR));
3302 }
3303
3304 static void i915_irq_preinstall(struct drm_device * dev)
3305 {
3306 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3307 int pipe;
3308
3309 if (I915_HAS_HOTPLUG(dev)) {
3310 I915_WRITE(PORT_HOTPLUG_EN, 0);
3311 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3312 }
3313
3314 I915_WRITE16(HWSTAM, 0xeffe);
3315 for_each_pipe(pipe)
3316 I915_WRITE(PIPESTAT(pipe), 0);
3317 I915_WRITE(IMR, 0xffffffff);
3318 I915_WRITE(IER, 0x0);
3319 POSTING_READ(IER);
3320 }
3321
3322 static int i915_irq_postinstall(struct drm_device *dev)
3323 {
3324 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3325 u32 enable_mask;
3326 unsigned long irqflags;
3327
3328 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3329
3330 /* Unmask the interrupts that we always want on. */
3331 dev_priv->irq_mask =
3332 ~(I915_ASLE_INTERRUPT |
3333 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3334 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3335 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3336 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3337 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3338
3339 enable_mask =
3340 I915_ASLE_INTERRUPT |
3341 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3342 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3343 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3344 I915_USER_INTERRUPT;
3345
3346 if (I915_HAS_HOTPLUG(dev)) {
3347 I915_WRITE(PORT_HOTPLUG_EN, 0);
3348 POSTING_READ(PORT_HOTPLUG_EN);
3349
3350 /* Enable in IER... */
3351 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3352 /* and unmask in IMR */
3353 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3354 }
3355
3356 I915_WRITE(IMR, dev_priv->irq_mask);
3357 I915_WRITE(IER, enable_mask);
3358 POSTING_READ(IER);
3359
3360 i915_enable_asle_pipestat(dev);
3361
3362 /* Interrupt setup is already guaranteed to be single-threaded, this is
3363 * just to make the assert_spin_locked check happy. */
3364 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3365 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
3366 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
3367 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3368
3369 return 0;
3370 }
3371
3372 /*
3373 * Returns true when a page flip has completed.
3374 */
3375 static bool i915_handle_vblank(struct drm_device *dev,
3376 int plane, int pipe, u32 iir)
3377 {
3378 drm_i915_private_t *dev_priv = dev->dev_private;
3379 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3380
3381 if (!drm_handle_vblank(dev, pipe))
3382 return false;
3383
3384 if ((iir & flip_pending) == 0)
3385 return false;
3386
3387 intel_prepare_page_flip(dev, plane);
3388
3389 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3390 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3391 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3392 * the flip is completed (no longer pending). Since this doesn't raise
3393 * an interrupt per se, we watch for the change at vblank.
3394 */
3395 if (I915_READ(ISR) & flip_pending)
3396 return false;
3397
3398 intel_finish_page_flip(dev, pipe);
3399
3400 return true;
3401 }
3402
3403 static irqreturn_t i915_irq_handler(int irq, void *arg)
3404 {
3405 struct drm_device *dev = (struct drm_device *) arg;
3406 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3407 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3408 unsigned long irqflags;
3409 u32 flip_mask =
3410 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3411 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3412 int pipe, ret = IRQ_NONE;
3413
3414 iir = I915_READ(IIR);
3415 do {
3416 bool irq_received = (iir & ~flip_mask) != 0;
3417 bool blc_event = false;
3418
3419 /* Can't rely on pipestat interrupt bit in iir as it might
3420 * have been cleared after the pipestat interrupt was received.
3421 * It doesn't set the bit in iir again, but it still produces
3422 * interrupts (for non-MSI).
3423 */
3424 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3425 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3426 i915_handle_error(dev, false);
3427
3428 for_each_pipe(pipe) {
3429 int reg = PIPESTAT(pipe);
3430 pipe_stats[pipe] = I915_READ(reg);
3431
3432 /* Clear the PIPE*STAT regs before the IIR */
3433 if (pipe_stats[pipe] & 0x8000ffff) {
3434 I915_WRITE(reg, pipe_stats[pipe]);
3435 irq_received = true;
3436 }
3437 }
3438 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3439
3440 if (!irq_received)
3441 break;
3442
3443 /* Consume port. Then clear IIR or we'll miss events */
3444 if ((I915_HAS_HOTPLUG(dev)) &&
3445 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
3446 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3447 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
3448
3449 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
3450
3451 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3452 POSTING_READ(PORT_HOTPLUG_STAT);
3453 }
3454
3455 I915_WRITE(IIR, iir & ~flip_mask);
3456 new_iir = I915_READ(IIR); /* Flush posted writes */
3457
3458 if (iir & I915_USER_INTERRUPT)
3459 notify_ring(dev, &dev_priv->ring[RCS]);
3460
3461 for_each_pipe(pipe) {
3462 int plane = pipe;
3463 if (HAS_FBC(dev))
3464 plane = !plane;
3465
3466 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3467 i915_handle_vblank(dev, plane, pipe, iir))
3468 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3469
3470 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3471 blc_event = true;
3472
3473 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3474 i9xx_pipe_crc_irq_handler(dev, pipe);
3475
3476 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3477 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3478 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3479 }
3480
3481 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3482 intel_opregion_asle_intr(dev);
3483
3484 /* With MSI, interrupts are only generated when iir
3485 * transitions from zero to nonzero. If another bit got
3486 * set while we were handling the existing iir bits, then
3487 * we would never get another interrupt.
3488 *
3489 * This is fine on non-MSI as well, as if we hit this path
3490 * we avoid exiting the interrupt handler only to generate
3491 * another one.
3492 *
3493 * Note that for MSI this could cause a stray interrupt report
3494 * if an interrupt landed in the time between writing IIR and
3495 * the posting read. This should be rare enough to never
3496 * trigger the 99% of 100,000 interrupts test for disabling
3497 * stray interrupts.
3498 */
3499 ret = IRQ_HANDLED;
3500 iir = new_iir;
3501 } while (iir & ~flip_mask);
3502
3503 i915_update_dri1_breadcrumb(dev);
3504
3505 return ret;
3506 }
3507
3508 static void i915_irq_uninstall(struct drm_device * dev)
3509 {
3510 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3511 int pipe;
3512
3513 intel_hpd_irq_uninstall(dev_priv);
3514
3515 if (I915_HAS_HOTPLUG(dev)) {
3516 I915_WRITE(PORT_HOTPLUG_EN, 0);
3517 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3518 }
3519
3520 I915_WRITE16(HWSTAM, 0xffff);
3521 for_each_pipe(pipe) {
3522 /* Clear enable bits; then clear status bits */
3523 I915_WRITE(PIPESTAT(pipe), 0);
3524 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3525 }
3526 I915_WRITE(IMR, 0xffffffff);
3527 I915_WRITE(IER, 0x0);
3528
3529 I915_WRITE(IIR, I915_READ(IIR));
3530 }
3531
3532 static void i965_irq_preinstall(struct drm_device * dev)
3533 {
3534 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3535 int pipe;
3536
3537 I915_WRITE(PORT_HOTPLUG_EN, 0);
3538 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3539
3540 I915_WRITE(HWSTAM, 0xeffe);
3541 for_each_pipe(pipe)
3542 I915_WRITE(PIPESTAT(pipe), 0);
3543 I915_WRITE(IMR, 0xffffffff);
3544 I915_WRITE(IER, 0x0);
3545 POSTING_READ(IER);
3546 }
3547
3548 static int i965_irq_postinstall(struct drm_device *dev)
3549 {
3550 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3551 u32 enable_mask;
3552 u32 error_mask;
3553 unsigned long irqflags;
3554
3555 /* Unmask the interrupts that we always want on. */
3556 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
3557 I915_DISPLAY_PORT_INTERRUPT |
3558 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3559 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3560 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3561 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3562 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3563
3564 enable_mask = ~dev_priv->irq_mask;
3565 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3566 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3567 enable_mask |= I915_USER_INTERRUPT;
3568
3569 if (IS_G4X(dev))
3570 enable_mask |= I915_BSD_USER_INTERRUPT;
3571
3572 /* Interrupt setup is already guaranteed to be single-threaded, this is
3573 * just to make the assert_spin_locked check happy. */
3574 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3575 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE);
3576 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
3577 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
3578 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3579
3580 /*
3581 * Enable some error detection, note the instruction error mask
3582 * bit is reserved, so we leave it masked.
3583 */
3584 if (IS_G4X(dev)) {
3585 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3586 GM45_ERROR_MEM_PRIV |
3587 GM45_ERROR_CP_PRIV |
3588 I915_ERROR_MEMORY_REFRESH);
3589 } else {
3590 error_mask = ~(I915_ERROR_PAGE_TABLE |
3591 I915_ERROR_MEMORY_REFRESH);
3592 }
3593 I915_WRITE(EMR, error_mask);
3594
3595 I915_WRITE(IMR, dev_priv->irq_mask);
3596 I915_WRITE(IER, enable_mask);
3597 POSTING_READ(IER);
3598
3599 I915_WRITE(PORT_HOTPLUG_EN, 0);
3600 POSTING_READ(PORT_HOTPLUG_EN);
3601
3602 i915_enable_asle_pipestat(dev);
3603
3604 return 0;
3605 }
3606
3607 static void i915_hpd_irq_setup(struct drm_device *dev)
3608 {
3609 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3610 struct drm_mode_config *mode_config = &dev->mode_config;
3611 struct intel_encoder *intel_encoder;
3612 u32 hotplug_en;
3613
3614 assert_spin_locked(&dev_priv->irq_lock);
3615
3616 if (I915_HAS_HOTPLUG(dev)) {
3617 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3618 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3619 /* Note HDMI and DP share hotplug bits */
3620 /* enable bits are the same for all generations */
3621 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3622 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3623 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
3624 /* Programming the CRT detection parameters tends
3625 to generate a spurious hotplug event about three
3626 seconds later. So just do it once.
3627 */
3628 if (IS_G4X(dev))
3629 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
3630 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
3631 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
3632
3633 /* Ignore TV since it's buggy */
3634 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3635 }
3636 }
3637
3638 static irqreturn_t i965_irq_handler(int irq, void *arg)
3639 {
3640 struct drm_device *dev = (struct drm_device *) arg;
3641 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3642 u32 iir, new_iir;
3643 u32 pipe_stats[I915_MAX_PIPES];
3644 unsigned long irqflags;
3645 int ret = IRQ_NONE, pipe;
3646 u32 flip_mask =
3647 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3648 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3649
3650 iir = I915_READ(IIR);
3651
3652 for (;;) {
3653 bool irq_received = (iir & ~flip_mask) != 0;
3654 bool blc_event = false;
3655
3656 /* Can't rely on pipestat interrupt bit in iir as it might
3657 * have been cleared after the pipestat interrupt was received.
3658 * It doesn't set the bit in iir again, but it still produces
3659 * interrupts (for non-MSI).
3660 */
3661 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3662 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3663 i915_handle_error(dev, false);
3664
3665 for_each_pipe(pipe) {
3666 int reg = PIPESTAT(pipe);
3667 pipe_stats[pipe] = I915_READ(reg);
3668
3669 /*
3670 * Clear the PIPE*STAT regs before the IIR
3671 */
3672 if (pipe_stats[pipe] & 0x8000ffff) {
3673 I915_WRITE(reg, pipe_stats[pipe]);
3674 irq_received = true;
3675 }
3676 }
3677 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3678
3679 if (!irq_received)
3680 break;
3681
3682 ret = IRQ_HANDLED;
3683
3684 /* Consume port. Then clear IIR or we'll miss events */
3685 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
3686 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3687 u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
3688 HOTPLUG_INT_STATUS_G4X :
3689 HOTPLUG_INT_STATUS_I915);
3690
3691 intel_hpd_irq_handler(dev, hotplug_trigger,
3692 IS_G4X(dev) ? hpd_status_g4x : hpd_status_i915);
3693
3694 if (IS_G4X(dev) &&
3695 (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X))
3696 dp_aux_irq_handler(dev);
3697
3698 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3699 I915_READ(PORT_HOTPLUG_STAT);
3700 }
3701
3702 I915_WRITE(IIR, iir & ~flip_mask);
3703 new_iir = I915_READ(IIR); /* Flush posted writes */
3704
3705 if (iir & I915_USER_INTERRUPT)
3706 notify_ring(dev, &dev_priv->ring[RCS]);
3707 if (iir & I915_BSD_USER_INTERRUPT)
3708 notify_ring(dev, &dev_priv->ring[VCS]);
3709
3710 for_each_pipe(pipe) {
3711 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
3712 i915_handle_vblank(dev, pipe, pipe, iir))
3713 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
3714
3715 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3716 blc_event = true;
3717
3718 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3719 i9xx_pipe_crc_irq_handler(dev, pipe);
3720
3721 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3722 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3723 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3724 }
3725
3726 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3727 intel_opregion_asle_intr(dev);
3728
3729 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3730 gmbus_irq_handler(dev);
3731
3732 /* With MSI, interrupts are only generated when iir
3733 * transitions from zero to nonzero. If another bit got
3734 * set while we were handling the existing iir bits, then
3735 * we would never get another interrupt.
3736 *
3737 * This is fine on non-MSI as well, as if we hit this path
3738 * we avoid exiting the interrupt handler only to generate
3739 * another one.
3740 *
3741 * Note that for MSI this could cause a stray interrupt report
3742 * if an interrupt landed in the time between writing IIR and
3743 * the posting read. This should be rare enough to never
3744 * trigger the 99% of 100,000 interrupts test for disabling
3745 * stray interrupts.
3746 */
3747 iir = new_iir;
3748 }
3749
3750 i915_update_dri1_breadcrumb(dev);
3751
3752 return ret;
3753 }
3754
3755 static void i965_irq_uninstall(struct drm_device * dev)
3756 {
3757 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3758 int pipe;
3759
3760 if (!dev_priv)
3761 return;
3762
3763 intel_hpd_irq_uninstall(dev_priv);
3764
3765 I915_WRITE(PORT_HOTPLUG_EN, 0);
3766 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3767
3768 I915_WRITE(HWSTAM, 0xffffffff);
3769 for_each_pipe(pipe)
3770 I915_WRITE(PIPESTAT(pipe), 0);
3771 I915_WRITE(IMR, 0xffffffff);
3772 I915_WRITE(IER, 0x0);
3773
3774 for_each_pipe(pipe)
3775 I915_WRITE(PIPESTAT(pipe),
3776 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3777 I915_WRITE(IIR, I915_READ(IIR));
3778 }
3779
3780 static void intel_hpd_irq_reenable(unsigned long data)
3781 {
3782 drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
3783 struct drm_device *dev = dev_priv->dev;
3784 struct drm_mode_config *mode_config = &dev->mode_config;
3785 unsigned long irqflags;
3786 int i;
3787
3788 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3789 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3790 struct drm_connector *connector;
3791
3792 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3793 continue;
3794
3795 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3796
3797 list_for_each_entry(connector, &mode_config->connector_list, head) {
3798 struct intel_connector *intel_connector = to_intel_connector(connector);
3799
3800 if (intel_connector->encoder->hpd_pin == i) {
3801 if (connector->polled != intel_connector->polled)
3802 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3803 drm_get_connector_name(connector));
3804 connector->polled = intel_connector->polled;
3805 if (!connector->polled)
3806 connector->polled = DRM_CONNECTOR_POLL_HPD;
3807 }
3808 }
3809 }
3810 if (dev_priv->display.hpd_irq_setup)
3811 dev_priv->display.hpd_irq_setup(dev);
3812 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3813 }
3814
3815 void intel_irq_init(struct drm_device *dev)
3816 {
3817 struct drm_i915_private *dev_priv = dev->dev_private;
3818
3819 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
3820 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
3821 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
3822 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
3823
3824 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3825 i915_hangcheck_elapsed,
3826 (unsigned long) dev);
3827 setup_timer(&dev_priv->hotplug_reenable_timer, intel_hpd_irq_reenable,
3828 (unsigned long) dev_priv);
3829
3830 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
3831
3832 if (IS_GEN2(dev)) {
3833 dev->max_vblank_count = 0;
3834 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
3835 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
3836 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3837 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
3838 } else {
3839 dev->driver->get_vblank_counter = i915_get_vblank_counter;
3840 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
3841 }
3842
3843 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
3844 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
3845 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3846 }
3847
3848 if (IS_VALLEYVIEW(dev)) {
3849 dev->driver->irq_handler = valleyview_irq_handler;
3850 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3851 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3852 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3853 dev->driver->enable_vblank = valleyview_enable_vblank;
3854 dev->driver->disable_vblank = valleyview_disable_vblank;
3855 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3856 } else if (IS_GEN8(dev)) {
3857 dev->driver->irq_handler = gen8_irq_handler;
3858 dev->driver->irq_preinstall = gen8_irq_preinstall;
3859 dev->driver->irq_postinstall = gen8_irq_postinstall;
3860 dev->driver->irq_uninstall = gen8_irq_uninstall;
3861 dev->driver->enable_vblank = gen8_enable_vblank;
3862 dev->driver->disable_vblank = gen8_disable_vblank;
3863 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3864 } else if (HAS_PCH_SPLIT(dev)) {
3865 dev->driver->irq_handler = ironlake_irq_handler;
3866 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3867 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3868 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3869 dev->driver->enable_vblank = ironlake_enable_vblank;
3870 dev->driver->disable_vblank = ironlake_disable_vblank;
3871 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3872 } else {
3873 if (INTEL_INFO(dev)->gen == 2) {
3874 dev->driver->irq_preinstall = i8xx_irq_preinstall;
3875 dev->driver->irq_postinstall = i8xx_irq_postinstall;
3876 dev->driver->irq_handler = i8xx_irq_handler;
3877 dev->driver->irq_uninstall = i8xx_irq_uninstall;
3878 } else if (INTEL_INFO(dev)->gen == 3) {
3879 dev->driver->irq_preinstall = i915_irq_preinstall;
3880 dev->driver->irq_postinstall = i915_irq_postinstall;
3881 dev->driver->irq_uninstall = i915_irq_uninstall;
3882 dev->driver->irq_handler = i915_irq_handler;
3883 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3884 } else {
3885 dev->driver->irq_preinstall = i965_irq_preinstall;
3886 dev->driver->irq_postinstall = i965_irq_postinstall;
3887 dev->driver->irq_uninstall = i965_irq_uninstall;
3888 dev->driver->irq_handler = i965_irq_handler;
3889 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3890 }
3891 dev->driver->enable_vblank = i915_enable_vblank;
3892 dev->driver->disable_vblank = i915_disable_vblank;
3893 }
3894 }
3895
3896 void intel_hpd_init(struct drm_device *dev)
3897 {
3898 struct drm_i915_private *dev_priv = dev->dev_private;
3899 struct drm_mode_config *mode_config = &dev->mode_config;
3900 struct drm_connector *connector;
3901 unsigned long irqflags;
3902 int i;
3903
3904 for (i = 1; i < HPD_NUM_PINS; i++) {
3905 dev_priv->hpd_stats[i].hpd_cnt = 0;
3906 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3907 }
3908 list_for_each_entry(connector, &mode_config->connector_list, head) {
3909 struct intel_connector *intel_connector = to_intel_connector(connector);
3910 connector->polled = intel_connector->polled;
3911 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3912 connector->polled = DRM_CONNECTOR_POLL_HPD;
3913 }
3914
3915 /* Interrupt setup is already guaranteed to be single-threaded, this is
3916 * just to make the assert_spin_locked checks happy. */
3917 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3918 if (dev_priv->display.hpd_irq_setup)
3919 dev_priv->display.hpd_irq_setup(dev);
3920 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3921 }
3922
3923 /* Disable interrupts so we can allow Package C8+. */
3924 void hsw_pc8_disable_interrupts(struct drm_device *dev)
3925 {
3926 struct drm_i915_private *dev_priv = dev->dev_private;
3927 unsigned long irqflags;
3928
3929 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3930
3931 dev_priv->pc8.regsave.deimr = I915_READ(DEIMR);
3932 dev_priv->pc8.regsave.sdeimr = I915_READ(SDEIMR);
3933 dev_priv->pc8.regsave.gtimr = I915_READ(GTIMR);
3934 dev_priv->pc8.regsave.gtier = I915_READ(GTIER);
3935 dev_priv->pc8.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR);
3936
3937 ironlake_disable_display_irq(dev_priv, 0xffffffff);
3938 ibx_disable_display_interrupt(dev_priv, 0xffffffff);
3939 ilk_disable_gt_irq(dev_priv, 0xffffffff);
3940 snb_disable_pm_irq(dev_priv, 0xffffffff);
3941
3942 dev_priv->pc8.irqs_disabled = true;
3943
3944 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3945 }
3946
3947 /* Restore interrupts so we can recover from Package C8+. */
3948 void hsw_pc8_restore_interrupts(struct drm_device *dev)
3949 {
3950 struct drm_i915_private *dev_priv = dev->dev_private;
3951 unsigned long irqflags;
3952 uint32_t val;
3953
3954 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3955
3956 val = I915_READ(DEIMR);
3957 WARN(val != 0xffffffff, "DEIMR is 0x%08x\n", val);
3958
3959 val = I915_READ(SDEIMR);
3960 WARN(val != 0xffffffff, "SDEIMR is 0x%08x\n", val);
3961
3962 val = I915_READ(GTIMR);
3963 WARN(val != 0xffffffff, "GTIMR is 0x%08x\n", val);
3964
3965 val = I915_READ(GEN6_PMIMR);
3966 WARN(val != 0xffffffff, "GEN6_PMIMR is 0x%08x\n", val);
3967
3968 dev_priv->pc8.irqs_disabled = false;
3969
3970 ironlake_enable_display_irq(dev_priv, ~dev_priv->pc8.regsave.deimr);
3971 ibx_enable_display_interrupt(dev_priv, ~dev_priv->pc8.regsave.sdeimr);
3972 ilk_enable_gt_irq(dev_priv, ~dev_priv->pc8.regsave.gtimr);
3973 snb_enable_pm_irq(dev_priv, ~dev_priv->pc8.regsave.gen6_pmimr);
3974 I915_WRITE(GTIER, dev_priv->pc8.regsave.gtier);
3975
3976 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3977 }
Linux kernel - Deliverables
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