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drm/i915: Only call mod_timer() if not already pending
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
34 #include <drm/drmP.h>
35 #include <drm/i915_drm.h>
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "intel_drv.h"
39
40 /**
41 * DOC: interrupt handling
42 *
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
46 */
47
48 static const u32 hpd_ibx[] = {
49 [HPD_CRT] = SDE_CRT_HOTPLUG,
50 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
51 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
52 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
53 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
54 };
55
56 static const u32 hpd_cpt[] = {
57 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
58 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
59 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
60 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
61 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
62 };
63
64 static const u32 hpd_mask_i915[] = {
65 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
66 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
67 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
68 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
69 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
70 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
71 };
72
73 static const u32 hpd_status_g4x[] = {
74 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
75 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
76 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
77 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
78 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
79 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
80 };
81
82 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
83 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
84 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
85 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
86 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
87 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
88 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
89 };
90
91 /* IIR can theoretically queue up two events. Be paranoid. */
92 #define GEN8_IRQ_RESET_NDX(type, which) do { \
93 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
94 POSTING_READ(GEN8_##type##_IMR(which)); \
95 I915_WRITE(GEN8_##type##_IER(which), 0); \
96 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
97 POSTING_READ(GEN8_##type##_IIR(which)); \
98 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
99 POSTING_READ(GEN8_##type##_IIR(which)); \
100 } while (0)
101
102 #define GEN5_IRQ_RESET(type) do { \
103 I915_WRITE(type##IMR, 0xffffffff); \
104 POSTING_READ(type##IMR); \
105 I915_WRITE(type##IER, 0); \
106 I915_WRITE(type##IIR, 0xffffffff); \
107 POSTING_READ(type##IIR); \
108 I915_WRITE(type##IIR, 0xffffffff); \
109 POSTING_READ(type##IIR); \
110 } while (0)
111
112 /*
113 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
114 */
115 #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
116 u32 val = I915_READ(reg); \
117 if (val) { \
118 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
119 (reg), val); \
120 I915_WRITE((reg), 0xffffffff); \
121 POSTING_READ(reg); \
122 I915_WRITE((reg), 0xffffffff); \
123 POSTING_READ(reg); \
124 } \
125 } while (0)
126
127 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
128 GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
129 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
130 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
131 POSTING_READ(GEN8_##type##_IMR(which)); \
132 } while (0)
133
134 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
135 GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
136 I915_WRITE(type##IER, (ier_val)); \
137 I915_WRITE(type##IMR, (imr_val)); \
138 POSTING_READ(type##IMR); \
139 } while (0)
140
141 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
142
143 /* For display hotplug interrupt */
144 void
145 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
146 {
147 assert_spin_locked(&dev_priv->irq_lock);
148
149 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
150 return;
151
152 if ((dev_priv->irq_mask & mask) != 0) {
153 dev_priv->irq_mask &= ~mask;
154 I915_WRITE(DEIMR, dev_priv->irq_mask);
155 POSTING_READ(DEIMR);
156 }
157 }
158
159 void
160 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
161 {
162 assert_spin_locked(&dev_priv->irq_lock);
163
164 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
165 return;
166
167 if ((dev_priv->irq_mask & mask) != mask) {
168 dev_priv->irq_mask |= mask;
169 I915_WRITE(DEIMR, dev_priv->irq_mask);
170 POSTING_READ(DEIMR);
171 }
172 }
173
174 /**
175 * ilk_update_gt_irq - update GTIMR
176 * @dev_priv: driver private
177 * @interrupt_mask: mask of interrupt bits to update
178 * @enabled_irq_mask: mask of interrupt bits to enable
179 */
180 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
181 uint32_t interrupt_mask,
182 uint32_t enabled_irq_mask)
183 {
184 assert_spin_locked(&dev_priv->irq_lock);
185
186 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
187 return;
188
189 dev_priv->gt_irq_mask &= ~interrupt_mask;
190 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
191 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
192 POSTING_READ(GTIMR);
193 }
194
195 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
196 {
197 ilk_update_gt_irq(dev_priv, mask, mask);
198 }
199
200 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
201 {
202 ilk_update_gt_irq(dev_priv, mask, 0);
203 }
204
205 static u32 gen6_pm_iir(struct drm_i915_private *dev_priv)
206 {
207 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
208 }
209
210 static u32 gen6_pm_imr(struct drm_i915_private *dev_priv)
211 {
212 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
213 }
214
215 static u32 gen6_pm_ier(struct drm_i915_private *dev_priv)
216 {
217 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
218 }
219
220 /**
221 * snb_update_pm_irq - update GEN6_PMIMR
222 * @dev_priv: driver private
223 * @interrupt_mask: mask of interrupt bits to update
224 * @enabled_irq_mask: mask of interrupt bits to enable
225 */
226 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
227 uint32_t interrupt_mask,
228 uint32_t enabled_irq_mask)
229 {
230 uint32_t new_val;
231
232 assert_spin_locked(&dev_priv->irq_lock);
233
234 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
235 return;
236
237 new_val = dev_priv->pm_irq_mask;
238 new_val &= ~interrupt_mask;
239 new_val |= (~enabled_irq_mask & interrupt_mask);
240
241 if (new_val != dev_priv->pm_irq_mask) {
242 dev_priv->pm_irq_mask = new_val;
243 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
244 POSTING_READ(gen6_pm_imr(dev_priv));
245 }
246 }
247
248 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
249 {
250 snb_update_pm_irq(dev_priv, mask, mask);
251 }
252
253 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
254 {
255 snb_update_pm_irq(dev_priv, mask, 0);
256 }
257
258 void gen6_reset_rps_interrupts(struct drm_device *dev)
259 {
260 struct drm_i915_private *dev_priv = dev->dev_private;
261 uint32_t reg = gen6_pm_iir(dev_priv);
262
263 spin_lock_irq(&dev_priv->irq_lock);
264 I915_WRITE(reg, dev_priv->pm_rps_events);
265 I915_WRITE(reg, dev_priv->pm_rps_events);
266 POSTING_READ(reg);
267 spin_unlock_irq(&dev_priv->irq_lock);
268 }
269
270 void gen6_enable_rps_interrupts(struct drm_device *dev)
271 {
272 struct drm_i915_private *dev_priv = dev->dev_private;
273
274 spin_lock_irq(&dev_priv->irq_lock);
275 WARN_ON(dev_priv->rps.pm_iir);
276 WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
277 dev_priv->rps.interrupts_enabled = true;
278 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
279 spin_unlock_irq(&dev_priv->irq_lock);
280 }
281
282 void gen6_disable_rps_interrupts(struct drm_device *dev)
283 {
284 struct drm_i915_private *dev_priv = dev->dev_private;
285
286 spin_lock_irq(&dev_priv->irq_lock);
287 dev_priv->rps.interrupts_enabled = false;
288 spin_unlock_irq(&dev_priv->irq_lock);
289
290 cancel_work_sync(&dev_priv->rps.work);
291
292 I915_WRITE(GEN6_PMINTRMSK, INTEL_INFO(dev_priv)->gen >= 8 ?
293 ~GEN8_PMINTR_REDIRECT_TO_NON_DISP : ~0);
294 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
295 ~dev_priv->pm_rps_events);
296
297 spin_lock_irq(&dev_priv->irq_lock);
298 dev_priv->rps.pm_iir = 0;
299 spin_unlock_irq(&dev_priv->irq_lock);
300
301 I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events);
302 }
303
304 /**
305 * ibx_display_interrupt_update - update SDEIMR
306 * @dev_priv: driver private
307 * @interrupt_mask: mask of interrupt bits to update
308 * @enabled_irq_mask: mask of interrupt bits to enable
309 */
310 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
311 uint32_t interrupt_mask,
312 uint32_t enabled_irq_mask)
313 {
314 uint32_t sdeimr = I915_READ(SDEIMR);
315 sdeimr &= ~interrupt_mask;
316 sdeimr |= (~enabled_irq_mask & interrupt_mask);
317
318 assert_spin_locked(&dev_priv->irq_lock);
319
320 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
321 return;
322
323 I915_WRITE(SDEIMR, sdeimr);
324 POSTING_READ(SDEIMR);
325 }
326
327 static void
328 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
329 u32 enable_mask, u32 status_mask)
330 {
331 u32 reg = PIPESTAT(pipe);
332 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
333
334 assert_spin_locked(&dev_priv->irq_lock);
335 WARN_ON(!intel_irqs_enabled(dev_priv));
336
337 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
338 status_mask & ~PIPESTAT_INT_STATUS_MASK,
339 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
340 pipe_name(pipe), enable_mask, status_mask))
341 return;
342
343 if ((pipestat & enable_mask) == enable_mask)
344 return;
345
346 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
347
348 /* Enable the interrupt, clear any pending status */
349 pipestat |= enable_mask | status_mask;
350 I915_WRITE(reg, pipestat);
351 POSTING_READ(reg);
352 }
353
354 static void
355 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
356 u32 enable_mask, u32 status_mask)
357 {
358 u32 reg = PIPESTAT(pipe);
359 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
360
361 assert_spin_locked(&dev_priv->irq_lock);
362 WARN_ON(!intel_irqs_enabled(dev_priv));
363
364 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
365 status_mask & ~PIPESTAT_INT_STATUS_MASK,
366 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
367 pipe_name(pipe), enable_mask, status_mask))
368 return;
369
370 if ((pipestat & enable_mask) == 0)
371 return;
372
373 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
374
375 pipestat &= ~enable_mask;
376 I915_WRITE(reg, pipestat);
377 POSTING_READ(reg);
378 }
379
380 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
381 {
382 u32 enable_mask = status_mask << 16;
383
384 /*
385 * On pipe A we don't support the PSR interrupt yet,
386 * on pipe B and C the same bit MBZ.
387 */
388 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
389 return 0;
390 /*
391 * On pipe B and C we don't support the PSR interrupt yet, on pipe
392 * A the same bit is for perf counters which we don't use either.
393 */
394 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
395 return 0;
396
397 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
398 SPRITE0_FLIP_DONE_INT_EN_VLV |
399 SPRITE1_FLIP_DONE_INT_EN_VLV);
400 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
401 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
402 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
403 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
404
405 return enable_mask;
406 }
407
408 void
409 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
410 u32 status_mask)
411 {
412 u32 enable_mask;
413
414 if (IS_VALLEYVIEW(dev_priv->dev))
415 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
416 status_mask);
417 else
418 enable_mask = status_mask << 16;
419 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
420 }
421
422 void
423 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
424 u32 status_mask)
425 {
426 u32 enable_mask;
427
428 if (IS_VALLEYVIEW(dev_priv->dev))
429 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
430 status_mask);
431 else
432 enable_mask = status_mask << 16;
433 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
434 }
435
436 /**
437 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
438 */
439 static void i915_enable_asle_pipestat(struct drm_device *dev)
440 {
441 struct drm_i915_private *dev_priv = dev->dev_private;
442
443 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
444 return;
445
446 spin_lock_irq(&dev_priv->irq_lock);
447
448 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
449 if (INTEL_INFO(dev)->gen >= 4)
450 i915_enable_pipestat(dev_priv, PIPE_A,
451 PIPE_LEGACY_BLC_EVENT_STATUS);
452
453 spin_unlock_irq(&dev_priv->irq_lock);
454 }
455
456 /**
457 * i915_pipe_enabled - check if a pipe is enabled
458 * @dev: DRM device
459 * @pipe: pipe to check
460 *
461 * Reading certain registers when the pipe is disabled can hang the chip.
462 * Use this routine to make sure the PLL is running and the pipe is active
463 * before reading such registers if unsure.
464 */
465 static int
466 i915_pipe_enabled(struct drm_device *dev, int pipe)
467 {
468 struct drm_i915_private *dev_priv = dev->dev_private;
469
470 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
471 /* Locking is horribly broken here, but whatever. */
472 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
473 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
474
475 return intel_crtc->active;
476 } else {
477 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
478 }
479 }
480
481 /*
482 * This timing diagram depicts the video signal in and
483 * around the vertical blanking period.
484 *
485 * Assumptions about the fictitious mode used in this example:
486 * vblank_start >= 3
487 * vsync_start = vblank_start + 1
488 * vsync_end = vblank_start + 2
489 * vtotal = vblank_start + 3
490 *
491 * start of vblank:
492 * latch double buffered registers
493 * increment frame counter (ctg+)
494 * generate start of vblank interrupt (gen4+)
495 * |
496 * | frame start:
497 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
498 * | may be shifted forward 1-3 extra lines via PIPECONF
499 * | |
500 * | | start of vsync:
501 * | | generate vsync interrupt
502 * | | |
503 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
504 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
505 * ----va---> <-----------------vb--------------------> <--------va-------------
506 * | | <----vs-----> |
507 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
508 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
509 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
510 * | | |
511 * last visible pixel first visible pixel
512 * | increment frame counter (gen3/4)
513 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
514 *
515 * x = horizontal active
516 * _ = horizontal blanking
517 * hs = horizontal sync
518 * va = vertical active
519 * vb = vertical blanking
520 * vs = vertical sync
521 * vbs = vblank_start (number)
522 *
523 * Summary:
524 * - most events happen at the start of horizontal sync
525 * - frame start happens at the start of horizontal blank, 1-4 lines
526 * (depending on PIPECONF settings) after the start of vblank
527 * - gen3/4 pixel and frame counter are synchronized with the start
528 * of horizontal active on the first line of vertical active
529 */
530
531 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
532 {
533 /* Gen2 doesn't have a hardware frame counter */
534 return 0;
535 }
536
537 /* Called from drm generic code, passed a 'crtc', which
538 * we use as a pipe index
539 */
540 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
541 {
542 struct drm_i915_private *dev_priv = dev->dev_private;
543 unsigned long high_frame;
544 unsigned long low_frame;
545 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
546
547 if (!i915_pipe_enabled(dev, pipe)) {
548 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
549 "pipe %c\n", pipe_name(pipe));
550 return 0;
551 }
552
553 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
554 struct intel_crtc *intel_crtc =
555 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
556 const struct drm_display_mode *mode =
557 &intel_crtc->config.adjusted_mode;
558
559 htotal = mode->crtc_htotal;
560 hsync_start = mode->crtc_hsync_start;
561 vbl_start = mode->crtc_vblank_start;
562 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
563 vbl_start = DIV_ROUND_UP(vbl_start, 2);
564 } else {
565 enum transcoder cpu_transcoder = (enum transcoder) pipe;
566
567 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
568 hsync_start = (I915_READ(HSYNC(cpu_transcoder)) & 0x1fff) + 1;
569 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
570 if ((I915_READ(PIPECONF(cpu_transcoder)) &
571 PIPECONF_INTERLACE_MASK) != PIPECONF_PROGRESSIVE)
572 vbl_start = DIV_ROUND_UP(vbl_start, 2);
573 }
574
575 /* Convert to pixel count */
576 vbl_start *= htotal;
577
578 /* Start of vblank event occurs at start of hsync */
579 vbl_start -= htotal - hsync_start;
580
581 high_frame = PIPEFRAME(pipe);
582 low_frame = PIPEFRAMEPIXEL(pipe);
583
584 /*
585 * High & low register fields aren't synchronized, so make sure
586 * we get a low value that's stable across two reads of the high
587 * register.
588 */
589 do {
590 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
591 low = I915_READ(low_frame);
592 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
593 } while (high1 != high2);
594
595 high1 >>= PIPE_FRAME_HIGH_SHIFT;
596 pixel = low & PIPE_PIXEL_MASK;
597 low >>= PIPE_FRAME_LOW_SHIFT;
598
599 /*
600 * The frame counter increments at beginning of active.
601 * Cook up a vblank counter by also checking the pixel
602 * counter against vblank start.
603 */
604 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
605 }
606
607 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
608 {
609 struct drm_i915_private *dev_priv = dev->dev_private;
610 int reg = PIPE_FRMCOUNT_GM45(pipe);
611
612 if (!i915_pipe_enabled(dev, pipe)) {
613 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
614 "pipe %c\n", pipe_name(pipe));
615 return 0;
616 }
617
618 return I915_READ(reg);
619 }
620
621 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
622 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
623
624 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
625 {
626 struct drm_device *dev = crtc->base.dev;
627 struct drm_i915_private *dev_priv = dev->dev_private;
628 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
629 enum pipe pipe = crtc->pipe;
630 int position, vtotal;
631
632 vtotal = mode->crtc_vtotal;
633 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
634 vtotal /= 2;
635
636 if (IS_GEN2(dev))
637 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
638 else
639 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
640
641 /*
642 * See update_scanline_offset() for the details on the
643 * scanline_offset adjustment.
644 */
645 return (position + crtc->scanline_offset) % vtotal;
646 }
647
648 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
649 unsigned int flags, int *vpos, int *hpos,
650 ktime_t *stime, ktime_t *etime)
651 {
652 struct drm_i915_private *dev_priv = dev->dev_private;
653 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
655 const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
656 int position;
657 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
658 bool in_vbl = true;
659 int ret = 0;
660 unsigned long irqflags;
661
662 if (!intel_crtc->active) {
663 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
664 "pipe %c\n", pipe_name(pipe));
665 return 0;
666 }
667
668 htotal = mode->crtc_htotal;
669 hsync_start = mode->crtc_hsync_start;
670 vtotal = mode->crtc_vtotal;
671 vbl_start = mode->crtc_vblank_start;
672 vbl_end = mode->crtc_vblank_end;
673
674 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
675 vbl_start = DIV_ROUND_UP(vbl_start, 2);
676 vbl_end /= 2;
677 vtotal /= 2;
678 }
679
680 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
681
682 /*
683 * Lock uncore.lock, as we will do multiple timing critical raw
684 * register reads, potentially with preemption disabled, so the
685 * following code must not block on uncore.lock.
686 */
687 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
688
689 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
690
691 /* Get optional system timestamp before query. */
692 if (stime)
693 *stime = ktime_get();
694
695 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
696 /* No obvious pixelcount register. Only query vertical
697 * scanout position from Display scan line register.
698 */
699 position = __intel_get_crtc_scanline(intel_crtc);
700 } else {
701 /* Have access to pixelcount since start of frame.
702 * We can split this into vertical and horizontal
703 * scanout position.
704 */
705 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
706
707 /* convert to pixel counts */
708 vbl_start *= htotal;
709 vbl_end *= htotal;
710 vtotal *= htotal;
711
712 /*
713 * In interlaced modes, the pixel counter counts all pixels,
714 * so one field will have htotal more pixels. In order to avoid
715 * the reported position from jumping backwards when the pixel
716 * counter is beyond the length of the shorter field, just
717 * clamp the position the length of the shorter field. This
718 * matches how the scanline counter based position works since
719 * the scanline counter doesn't count the two half lines.
720 */
721 if (position >= vtotal)
722 position = vtotal - 1;
723
724 /*
725 * Start of vblank interrupt is triggered at start of hsync,
726 * just prior to the first active line of vblank. However we
727 * consider lines to start at the leading edge of horizontal
728 * active. So, should we get here before we've crossed into
729 * the horizontal active of the first line in vblank, we would
730 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
731 * always add htotal-hsync_start to the current pixel position.
732 */
733 position = (position + htotal - hsync_start) % vtotal;
734 }
735
736 /* Get optional system timestamp after query. */
737 if (etime)
738 *etime = ktime_get();
739
740 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
741
742 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
743
744 in_vbl = position >= vbl_start && position < vbl_end;
745
746 /*
747 * While in vblank, position will be negative
748 * counting up towards 0 at vbl_end. And outside
749 * vblank, position will be positive counting
750 * up since vbl_end.
751 */
752 if (position >= vbl_start)
753 position -= vbl_end;
754 else
755 position += vtotal - vbl_end;
756
757 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
758 *vpos = position;
759 *hpos = 0;
760 } else {
761 *vpos = position / htotal;
762 *hpos = position - (*vpos * htotal);
763 }
764
765 /* In vblank? */
766 if (in_vbl)
767 ret |= DRM_SCANOUTPOS_IN_VBLANK;
768
769 return ret;
770 }
771
772 int intel_get_crtc_scanline(struct intel_crtc *crtc)
773 {
774 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
775 unsigned long irqflags;
776 int position;
777
778 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
779 position = __intel_get_crtc_scanline(crtc);
780 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
781
782 return position;
783 }
784
785 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
786 int *max_error,
787 struct timeval *vblank_time,
788 unsigned flags)
789 {
790 struct drm_crtc *crtc;
791
792 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
793 DRM_ERROR("Invalid crtc %d\n", pipe);
794 return -EINVAL;
795 }
796
797 /* Get drm_crtc to timestamp: */
798 crtc = intel_get_crtc_for_pipe(dev, pipe);
799 if (crtc == NULL) {
800 DRM_ERROR("Invalid crtc %d\n", pipe);
801 return -EINVAL;
802 }
803
804 if (!crtc->enabled) {
805 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
806 return -EBUSY;
807 }
808
809 /* Helper routine in DRM core does all the work: */
810 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
811 vblank_time, flags,
812 crtc,
813 &to_intel_crtc(crtc)->config.adjusted_mode);
814 }
815
816 static bool intel_hpd_irq_event(struct drm_device *dev,
817 struct drm_connector *connector)
818 {
819 enum drm_connector_status old_status;
820
821 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
822 old_status = connector->status;
823
824 connector->status = connector->funcs->detect(connector, false);
825 if (old_status == connector->status)
826 return false;
827
828 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
829 connector->base.id,
830 connector->name,
831 drm_get_connector_status_name(old_status),
832 drm_get_connector_status_name(connector->status));
833
834 return true;
835 }
836
837 static void i915_digport_work_func(struct work_struct *work)
838 {
839 struct drm_i915_private *dev_priv =
840 container_of(work, struct drm_i915_private, dig_port_work);
841 u32 long_port_mask, short_port_mask;
842 struct intel_digital_port *intel_dig_port;
843 int i, ret;
844 u32 old_bits = 0;
845
846 spin_lock_irq(&dev_priv->irq_lock);
847 long_port_mask = dev_priv->long_hpd_port_mask;
848 dev_priv->long_hpd_port_mask = 0;
849 short_port_mask = dev_priv->short_hpd_port_mask;
850 dev_priv->short_hpd_port_mask = 0;
851 spin_unlock_irq(&dev_priv->irq_lock);
852
853 for (i = 0; i < I915_MAX_PORTS; i++) {
854 bool valid = false;
855 bool long_hpd = false;
856 intel_dig_port = dev_priv->hpd_irq_port[i];
857 if (!intel_dig_port || !intel_dig_port->hpd_pulse)
858 continue;
859
860 if (long_port_mask & (1 << i)) {
861 valid = true;
862 long_hpd = true;
863 } else if (short_port_mask & (1 << i))
864 valid = true;
865
866 if (valid) {
867 ret = intel_dig_port->hpd_pulse(intel_dig_port, long_hpd);
868 if (ret == true) {
869 /* if we get true fallback to old school hpd */
870 old_bits |= (1 << intel_dig_port->base.hpd_pin);
871 }
872 }
873 }
874
875 if (old_bits) {
876 spin_lock_irq(&dev_priv->irq_lock);
877 dev_priv->hpd_event_bits |= old_bits;
878 spin_unlock_irq(&dev_priv->irq_lock);
879 schedule_work(&dev_priv->hotplug_work);
880 }
881 }
882
883 /*
884 * Handle hotplug events outside the interrupt handler proper.
885 */
886 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
887
888 static void i915_hotplug_work_func(struct work_struct *work)
889 {
890 struct drm_i915_private *dev_priv =
891 container_of(work, struct drm_i915_private, hotplug_work);
892 struct drm_device *dev = dev_priv->dev;
893 struct drm_mode_config *mode_config = &dev->mode_config;
894 struct intel_connector *intel_connector;
895 struct intel_encoder *intel_encoder;
896 struct drm_connector *connector;
897 bool hpd_disabled = false;
898 bool changed = false;
899 u32 hpd_event_bits;
900
901 mutex_lock(&mode_config->mutex);
902 DRM_DEBUG_KMS("running encoder hotplug functions\n");
903
904 spin_lock_irq(&dev_priv->irq_lock);
905
906 hpd_event_bits = dev_priv->hpd_event_bits;
907 dev_priv->hpd_event_bits = 0;
908 list_for_each_entry(connector, &mode_config->connector_list, head) {
909 intel_connector = to_intel_connector(connector);
910 if (!intel_connector->encoder)
911 continue;
912 intel_encoder = intel_connector->encoder;
913 if (intel_encoder->hpd_pin > HPD_NONE &&
914 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
915 connector->polled == DRM_CONNECTOR_POLL_HPD) {
916 DRM_INFO("HPD interrupt storm detected on connector %s: "
917 "switching from hotplug detection to polling\n",
918 connector->name);
919 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
920 connector->polled = DRM_CONNECTOR_POLL_CONNECT
921 | DRM_CONNECTOR_POLL_DISCONNECT;
922 hpd_disabled = true;
923 }
924 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
925 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
926 connector->name, intel_encoder->hpd_pin);
927 }
928 }
929 /* if there were no outputs to poll, poll was disabled,
930 * therefore make sure it's enabled when disabling HPD on
931 * some connectors */
932 if (hpd_disabled) {
933 drm_kms_helper_poll_enable(dev);
934 mod_delayed_work(system_wq, &dev_priv->hotplug_reenable_work,
935 msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
936 }
937
938 spin_unlock_irq(&dev_priv->irq_lock);
939
940 list_for_each_entry(connector, &mode_config->connector_list, head) {
941 intel_connector = to_intel_connector(connector);
942 if (!intel_connector->encoder)
943 continue;
944 intel_encoder = intel_connector->encoder;
945 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
946 if (intel_encoder->hot_plug)
947 intel_encoder->hot_plug(intel_encoder);
948 if (intel_hpd_irq_event(dev, connector))
949 changed = true;
950 }
951 }
952 mutex_unlock(&mode_config->mutex);
953
954 if (changed)
955 drm_kms_helper_hotplug_event(dev);
956 }
957
958 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
959 {
960 struct drm_i915_private *dev_priv = dev->dev_private;
961 u32 busy_up, busy_down, max_avg, min_avg;
962 u8 new_delay;
963
964 spin_lock(&mchdev_lock);
965
966 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
967
968 new_delay = dev_priv->ips.cur_delay;
969
970 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
971 busy_up = I915_READ(RCPREVBSYTUPAVG);
972 busy_down = I915_READ(RCPREVBSYTDNAVG);
973 max_avg = I915_READ(RCBMAXAVG);
974 min_avg = I915_READ(RCBMINAVG);
975
976 /* Handle RCS change request from hw */
977 if (busy_up > max_avg) {
978 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
979 new_delay = dev_priv->ips.cur_delay - 1;
980 if (new_delay < dev_priv->ips.max_delay)
981 new_delay = dev_priv->ips.max_delay;
982 } else if (busy_down < min_avg) {
983 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
984 new_delay = dev_priv->ips.cur_delay + 1;
985 if (new_delay > dev_priv->ips.min_delay)
986 new_delay = dev_priv->ips.min_delay;
987 }
988
989 if (ironlake_set_drps(dev, new_delay))
990 dev_priv->ips.cur_delay = new_delay;
991
992 spin_unlock(&mchdev_lock);
993
994 return;
995 }
996
997 static void notify_ring(struct drm_device *dev,
998 struct intel_engine_cs *ring)
999 {
1000 if (!intel_ring_initialized(ring))
1001 return;
1002
1003 trace_i915_gem_request_complete(ring);
1004
1005 wake_up_all(&ring->irq_queue);
1006 }
1007
1008 static u32 vlv_c0_residency(struct drm_i915_private *dev_priv,
1009 struct intel_rps_ei *rps_ei)
1010 {
1011 u32 cz_ts, cz_freq_khz;
1012 u32 render_count, media_count;
1013 u32 elapsed_render, elapsed_media, elapsed_time;
1014 u32 residency = 0;
1015
1016 cz_ts = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
1017 cz_freq_khz = DIV_ROUND_CLOSEST(dev_priv->mem_freq * 1000, 4);
1018
1019 render_count = I915_READ(VLV_RENDER_C0_COUNT_REG);
1020 media_count = I915_READ(VLV_MEDIA_C0_COUNT_REG);
1021
1022 if (rps_ei->cz_clock == 0) {
1023 rps_ei->cz_clock = cz_ts;
1024 rps_ei->render_c0 = render_count;
1025 rps_ei->media_c0 = media_count;
1026
1027 return dev_priv->rps.cur_freq;
1028 }
1029
1030 elapsed_time = cz_ts - rps_ei->cz_clock;
1031 rps_ei->cz_clock = cz_ts;
1032
1033 elapsed_render = render_count - rps_ei->render_c0;
1034 rps_ei->render_c0 = render_count;
1035
1036 elapsed_media = media_count - rps_ei->media_c0;
1037 rps_ei->media_c0 = media_count;
1038
1039 /* Convert all the counters into common unit of milli sec */
1040 elapsed_time /= VLV_CZ_CLOCK_TO_MILLI_SEC;
1041 elapsed_render /= cz_freq_khz;
1042 elapsed_media /= cz_freq_khz;
1043
1044 /*
1045 * Calculate overall C0 residency percentage
1046 * only if elapsed time is non zero
1047 */
1048 if (elapsed_time) {
1049 residency =
1050 ((max(elapsed_render, elapsed_media) * 100)
1051 / elapsed_time);
1052 }
1053
1054 return residency;
1055 }
1056
1057 /**
1058 * vlv_calc_delay_from_C0_counters - Increase/Decrease freq based on GPU
1059 * busy-ness calculated from C0 counters of render & media power wells
1060 * @dev_priv: DRM device private
1061 *
1062 */
1063 static int vlv_calc_delay_from_C0_counters(struct drm_i915_private *dev_priv)
1064 {
1065 u32 residency_C0_up = 0, residency_C0_down = 0;
1066 int new_delay, adj;
1067
1068 dev_priv->rps.ei_interrupt_count++;
1069
1070 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
1071
1072
1073 if (dev_priv->rps.up_ei.cz_clock == 0) {
1074 vlv_c0_residency(dev_priv, &dev_priv->rps.up_ei);
1075 vlv_c0_residency(dev_priv, &dev_priv->rps.down_ei);
1076 return dev_priv->rps.cur_freq;
1077 }
1078
1079
1080 /*
1081 * To down throttle, C0 residency should be less than down threshold
1082 * for continous EI intervals. So calculate down EI counters
1083 * once in VLV_INT_COUNT_FOR_DOWN_EI
1084 */
1085 if (dev_priv->rps.ei_interrupt_count == VLV_INT_COUNT_FOR_DOWN_EI) {
1086
1087 dev_priv->rps.ei_interrupt_count = 0;
1088
1089 residency_C0_down = vlv_c0_residency(dev_priv,
1090 &dev_priv->rps.down_ei);
1091 } else {
1092 residency_C0_up = vlv_c0_residency(dev_priv,
1093 &dev_priv->rps.up_ei);
1094 }
1095
1096 new_delay = dev_priv->rps.cur_freq;
1097
1098 adj = dev_priv->rps.last_adj;
1099 /* C0 residency is greater than UP threshold. Increase Frequency */
1100 if (residency_C0_up >= VLV_RP_UP_EI_THRESHOLD) {
1101 if (adj > 0)
1102 adj *= 2;
1103 else
1104 adj = 1;
1105
1106 if (dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit)
1107 new_delay = dev_priv->rps.cur_freq + adj;
1108
1109 /*
1110 * For better performance, jump directly
1111 * to RPe if we're below it.
1112 */
1113 if (new_delay < dev_priv->rps.efficient_freq)
1114 new_delay = dev_priv->rps.efficient_freq;
1115
1116 } else if (!dev_priv->rps.ei_interrupt_count &&
1117 (residency_C0_down < VLV_RP_DOWN_EI_THRESHOLD)) {
1118 if (adj < 0)
1119 adj *= 2;
1120 else
1121 adj = -1;
1122 /*
1123 * This means, C0 residency is less than down threshold over
1124 * a period of VLV_INT_COUNT_FOR_DOWN_EI. So, reduce the freq
1125 */
1126 if (dev_priv->rps.cur_freq > dev_priv->rps.min_freq_softlimit)
1127 new_delay = dev_priv->rps.cur_freq + adj;
1128 }
1129
1130 return new_delay;
1131 }
1132
1133 static void gen6_pm_rps_work(struct work_struct *work)
1134 {
1135 struct drm_i915_private *dev_priv =
1136 container_of(work, struct drm_i915_private, rps.work);
1137 u32 pm_iir;
1138 int new_delay, adj;
1139
1140 spin_lock_irq(&dev_priv->irq_lock);
1141 /* Speed up work cancelation during disabling rps interrupts. */
1142 if (!dev_priv->rps.interrupts_enabled) {
1143 spin_unlock_irq(&dev_priv->irq_lock);
1144 return;
1145 }
1146 pm_iir = dev_priv->rps.pm_iir;
1147 dev_priv->rps.pm_iir = 0;
1148 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1149 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1150 spin_unlock_irq(&dev_priv->irq_lock);
1151
1152 /* Make sure we didn't queue anything we're not going to process. */
1153 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1154
1155 if ((pm_iir & dev_priv->pm_rps_events) == 0)
1156 return;
1157
1158 mutex_lock(&dev_priv->rps.hw_lock);
1159
1160 adj = dev_priv->rps.last_adj;
1161 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1162 if (adj > 0)
1163 adj *= 2;
1164 else {
1165 /* CHV needs even encode values */
1166 adj = IS_CHERRYVIEW(dev_priv->dev) ? 2 : 1;
1167 }
1168 new_delay = dev_priv->rps.cur_freq + adj;
1169
1170 /*
1171 * For better performance, jump directly
1172 * to RPe if we're below it.
1173 */
1174 if (new_delay < dev_priv->rps.efficient_freq)
1175 new_delay = dev_priv->rps.efficient_freq;
1176 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1177 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1178 new_delay = dev_priv->rps.efficient_freq;
1179 else
1180 new_delay = dev_priv->rps.min_freq_softlimit;
1181 adj = 0;
1182 } else if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1183 new_delay = vlv_calc_delay_from_C0_counters(dev_priv);
1184 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1185 if (adj < 0)
1186 adj *= 2;
1187 else {
1188 /* CHV needs even encode values */
1189 adj = IS_CHERRYVIEW(dev_priv->dev) ? -2 : -1;
1190 }
1191 new_delay = dev_priv->rps.cur_freq + adj;
1192 } else { /* unknown event */
1193 new_delay = dev_priv->rps.cur_freq;
1194 }
1195
1196 /* sysfs frequency interfaces may have snuck in while servicing the
1197 * interrupt
1198 */
1199 new_delay = clamp_t(int, new_delay,
1200 dev_priv->rps.min_freq_softlimit,
1201 dev_priv->rps.max_freq_softlimit);
1202
1203 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq;
1204
1205 if (IS_VALLEYVIEW(dev_priv->dev))
1206 valleyview_set_rps(dev_priv->dev, new_delay);
1207 else
1208 gen6_set_rps(dev_priv->dev, new_delay);
1209
1210 mutex_unlock(&dev_priv->rps.hw_lock);
1211 }
1212
1213
1214 /**
1215 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1216 * occurred.
1217 * @work: workqueue struct
1218 *
1219 * Doesn't actually do anything except notify userspace. As a consequence of
1220 * this event, userspace should try to remap the bad rows since statistically
1221 * it is likely the same row is more likely to go bad again.
1222 */
1223 static void ivybridge_parity_work(struct work_struct *work)
1224 {
1225 struct drm_i915_private *dev_priv =
1226 container_of(work, struct drm_i915_private, l3_parity.error_work);
1227 u32 error_status, row, bank, subbank;
1228 char *parity_event[6];
1229 uint32_t misccpctl;
1230 uint8_t slice = 0;
1231
1232 /* We must turn off DOP level clock gating to access the L3 registers.
1233 * In order to prevent a get/put style interface, acquire struct mutex
1234 * any time we access those registers.
1235 */
1236 mutex_lock(&dev_priv->dev->struct_mutex);
1237
1238 /* If we've screwed up tracking, just let the interrupt fire again */
1239 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1240 goto out;
1241
1242 misccpctl = I915_READ(GEN7_MISCCPCTL);
1243 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1244 POSTING_READ(GEN7_MISCCPCTL);
1245
1246 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1247 u32 reg;
1248
1249 slice--;
1250 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1251 break;
1252
1253 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1254
1255 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1256
1257 error_status = I915_READ(reg);
1258 row = GEN7_PARITY_ERROR_ROW(error_status);
1259 bank = GEN7_PARITY_ERROR_BANK(error_status);
1260 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1261
1262 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1263 POSTING_READ(reg);
1264
1265 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1266 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1267 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1268 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1269 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1270 parity_event[5] = NULL;
1271
1272 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1273 KOBJ_CHANGE, parity_event);
1274
1275 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1276 slice, row, bank, subbank);
1277
1278 kfree(parity_event[4]);
1279 kfree(parity_event[3]);
1280 kfree(parity_event[2]);
1281 kfree(parity_event[1]);
1282 }
1283
1284 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1285
1286 out:
1287 WARN_ON(dev_priv->l3_parity.which_slice);
1288 spin_lock_irq(&dev_priv->irq_lock);
1289 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1290 spin_unlock_irq(&dev_priv->irq_lock);
1291
1292 mutex_unlock(&dev_priv->dev->struct_mutex);
1293 }
1294
1295 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1296 {
1297 struct drm_i915_private *dev_priv = dev->dev_private;
1298
1299 if (!HAS_L3_DPF(dev))
1300 return;
1301
1302 spin_lock(&dev_priv->irq_lock);
1303 gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1304 spin_unlock(&dev_priv->irq_lock);
1305
1306 iir &= GT_PARITY_ERROR(dev);
1307 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1308 dev_priv->l3_parity.which_slice |= 1 << 1;
1309
1310 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1311 dev_priv->l3_parity.which_slice |= 1 << 0;
1312
1313 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1314 }
1315
1316 static void ilk_gt_irq_handler(struct drm_device *dev,
1317 struct drm_i915_private *dev_priv,
1318 u32 gt_iir)
1319 {
1320 if (gt_iir &
1321 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1322 notify_ring(dev, &dev_priv->ring[RCS]);
1323 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1324 notify_ring(dev, &dev_priv->ring[VCS]);
1325 }
1326
1327 static void snb_gt_irq_handler(struct drm_device *dev,
1328 struct drm_i915_private *dev_priv,
1329 u32 gt_iir)
1330 {
1331
1332 if (gt_iir &
1333 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1334 notify_ring(dev, &dev_priv->ring[RCS]);
1335 if (gt_iir & GT_BSD_USER_INTERRUPT)
1336 notify_ring(dev, &dev_priv->ring[VCS]);
1337 if (gt_iir & GT_BLT_USER_INTERRUPT)
1338 notify_ring(dev, &dev_priv->ring[BCS]);
1339
1340 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1341 GT_BSD_CS_ERROR_INTERRUPT |
1342 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
1343 i915_handle_error(dev, false, "GT error interrupt 0x%08x",
1344 gt_iir);
1345 }
1346
1347 if (gt_iir & GT_PARITY_ERROR(dev))
1348 ivybridge_parity_error_irq_handler(dev, gt_iir);
1349 }
1350
1351 static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1352 struct drm_i915_private *dev_priv,
1353 u32 master_ctl)
1354 {
1355 struct intel_engine_cs *ring;
1356 u32 rcs, bcs, vcs;
1357 uint32_t tmp = 0;
1358 irqreturn_t ret = IRQ_NONE;
1359
1360 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1361 tmp = I915_READ(GEN8_GT_IIR(0));
1362 if (tmp) {
1363 I915_WRITE(GEN8_GT_IIR(0), tmp);
1364 ret = IRQ_HANDLED;
1365
1366 rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1367 ring = &dev_priv->ring[RCS];
1368 if (rcs & GT_RENDER_USER_INTERRUPT)
1369 notify_ring(dev, ring);
1370 if (rcs & GT_CONTEXT_SWITCH_INTERRUPT)
1371 intel_execlists_handle_ctx_events(ring);
1372
1373 bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1374 ring = &dev_priv->ring[BCS];
1375 if (bcs & GT_RENDER_USER_INTERRUPT)
1376 notify_ring(dev, ring);
1377 if (bcs & GT_CONTEXT_SWITCH_INTERRUPT)
1378 intel_execlists_handle_ctx_events(ring);
1379 } else
1380 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1381 }
1382
1383 if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1384 tmp = I915_READ(GEN8_GT_IIR(1));
1385 if (tmp) {
1386 I915_WRITE(GEN8_GT_IIR(1), tmp);
1387 ret = IRQ_HANDLED;
1388
1389 vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1390 ring = &dev_priv->ring[VCS];
1391 if (vcs & GT_RENDER_USER_INTERRUPT)
1392 notify_ring(dev, ring);
1393 if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1394 intel_execlists_handle_ctx_events(ring);
1395
1396 vcs = tmp >> GEN8_VCS2_IRQ_SHIFT;
1397 ring = &dev_priv->ring[VCS2];
1398 if (vcs & GT_RENDER_USER_INTERRUPT)
1399 notify_ring(dev, ring);
1400 if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1401 intel_execlists_handle_ctx_events(ring);
1402 } else
1403 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1404 }
1405
1406 if (master_ctl & GEN8_GT_PM_IRQ) {
1407 tmp = I915_READ(GEN8_GT_IIR(2));
1408 if (tmp & dev_priv->pm_rps_events) {
1409 I915_WRITE(GEN8_GT_IIR(2),
1410 tmp & dev_priv->pm_rps_events);
1411 ret = IRQ_HANDLED;
1412 gen6_rps_irq_handler(dev_priv, tmp);
1413 } else
1414 DRM_ERROR("The master control interrupt lied (PM)!\n");
1415 }
1416
1417 if (master_ctl & GEN8_GT_VECS_IRQ) {
1418 tmp = I915_READ(GEN8_GT_IIR(3));
1419 if (tmp) {
1420 I915_WRITE(GEN8_GT_IIR(3), tmp);
1421 ret = IRQ_HANDLED;
1422
1423 vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1424 ring = &dev_priv->ring[VECS];
1425 if (vcs & GT_RENDER_USER_INTERRUPT)
1426 notify_ring(dev, ring);
1427 if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1428 intel_execlists_handle_ctx_events(ring);
1429 } else
1430 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1431 }
1432
1433 return ret;
1434 }
1435
1436 #define HPD_STORM_DETECT_PERIOD 1000
1437 #define HPD_STORM_THRESHOLD 5
1438
1439 static int pch_port_to_hotplug_shift(enum port port)
1440 {
1441 switch (port) {
1442 case PORT_A:
1443 case PORT_E:
1444 default:
1445 return -1;
1446 case PORT_B:
1447 return 0;
1448 case PORT_C:
1449 return 8;
1450 case PORT_D:
1451 return 16;
1452 }
1453 }
1454
1455 static int i915_port_to_hotplug_shift(enum port port)
1456 {
1457 switch (port) {
1458 case PORT_A:
1459 case PORT_E:
1460 default:
1461 return -1;
1462 case PORT_B:
1463 return 17;
1464 case PORT_C:
1465 return 19;
1466 case PORT_D:
1467 return 21;
1468 }
1469 }
1470
1471 static inline enum port get_port_from_pin(enum hpd_pin pin)
1472 {
1473 switch (pin) {
1474 case HPD_PORT_B:
1475 return PORT_B;
1476 case HPD_PORT_C:
1477 return PORT_C;
1478 case HPD_PORT_D:
1479 return PORT_D;
1480 default:
1481 return PORT_A; /* no hpd */
1482 }
1483 }
1484
1485 static inline void intel_hpd_irq_handler(struct drm_device *dev,
1486 u32 hotplug_trigger,
1487 u32 dig_hotplug_reg,
1488 const u32 *hpd)
1489 {
1490 struct drm_i915_private *dev_priv = dev->dev_private;
1491 int i;
1492 enum port port;
1493 bool storm_detected = false;
1494 bool queue_dig = false, queue_hp = false;
1495 u32 dig_shift;
1496 u32 dig_port_mask = 0;
1497
1498 if (!hotplug_trigger)
1499 return;
1500
1501 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x\n",
1502 hotplug_trigger, dig_hotplug_reg);
1503
1504 spin_lock(&dev_priv->irq_lock);
1505 for (i = 1; i < HPD_NUM_PINS; i++) {
1506 if (!(hpd[i] & hotplug_trigger))
1507 continue;
1508
1509 port = get_port_from_pin(i);
1510 if (port && dev_priv->hpd_irq_port[port]) {
1511 bool long_hpd;
1512
1513 if (HAS_PCH_SPLIT(dev)) {
1514 dig_shift = pch_port_to_hotplug_shift(port);
1515 long_hpd = (dig_hotplug_reg >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
1516 } else {
1517 dig_shift = i915_port_to_hotplug_shift(port);
1518 long_hpd = (hotplug_trigger >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
1519 }
1520
1521 DRM_DEBUG_DRIVER("digital hpd port %c - %s\n",
1522 port_name(port),
1523 long_hpd ? "long" : "short");
1524 /* for long HPD pulses we want to have the digital queue happen,
1525 but we still want HPD storm detection to function. */
1526 if (long_hpd) {
1527 dev_priv->long_hpd_port_mask |= (1 << port);
1528 dig_port_mask |= hpd[i];
1529 } else {
1530 /* for short HPD just trigger the digital queue */
1531 dev_priv->short_hpd_port_mask |= (1 << port);
1532 hotplug_trigger &= ~hpd[i];
1533 }
1534 queue_dig = true;
1535 }
1536 }
1537
1538 for (i = 1; i < HPD_NUM_PINS; i++) {
1539 if (hpd[i] & hotplug_trigger &&
1540 dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) {
1541 /*
1542 * On GMCH platforms the interrupt mask bits only
1543 * prevent irq generation, not the setting of the
1544 * hotplug bits itself. So only WARN about unexpected
1545 * interrupts on saner platforms.
1546 */
1547 WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
1548 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1549 hotplug_trigger, i, hpd[i]);
1550
1551 continue;
1552 }
1553
1554 if (!(hpd[i] & hotplug_trigger) ||
1555 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1556 continue;
1557
1558 if (!(dig_port_mask & hpd[i])) {
1559 dev_priv->hpd_event_bits |= (1 << i);
1560 queue_hp = true;
1561 }
1562
1563 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1564 dev_priv->hpd_stats[i].hpd_last_jiffies
1565 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1566 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1567 dev_priv->hpd_stats[i].hpd_cnt = 0;
1568 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1569 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1570 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1571 dev_priv->hpd_event_bits &= ~(1 << i);
1572 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1573 storm_detected = true;
1574 } else {
1575 dev_priv->hpd_stats[i].hpd_cnt++;
1576 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1577 dev_priv->hpd_stats[i].hpd_cnt);
1578 }
1579 }
1580
1581 if (storm_detected)
1582 dev_priv->display.hpd_irq_setup(dev);
1583 spin_unlock(&dev_priv->irq_lock);
1584
1585 /*
1586 * Our hotplug handler can grab modeset locks (by calling down into the
1587 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1588 * queue for otherwise the flush_work in the pageflip code will
1589 * deadlock.
1590 */
1591 if (queue_dig)
1592 queue_work(dev_priv->dp_wq, &dev_priv->dig_port_work);
1593 if (queue_hp)
1594 schedule_work(&dev_priv->hotplug_work);
1595 }
1596
1597 static void gmbus_irq_handler(struct drm_device *dev)
1598 {
1599 struct drm_i915_private *dev_priv = dev->dev_private;
1600
1601 wake_up_all(&dev_priv->gmbus_wait_queue);
1602 }
1603
1604 static void dp_aux_irq_handler(struct drm_device *dev)
1605 {
1606 struct drm_i915_private *dev_priv = dev->dev_private;
1607
1608 wake_up_all(&dev_priv->gmbus_wait_queue);
1609 }
1610
1611 #if defined(CONFIG_DEBUG_FS)
1612 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1613 uint32_t crc0, uint32_t crc1,
1614 uint32_t crc2, uint32_t crc3,
1615 uint32_t crc4)
1616 {
1617 struct drm_i915_private *dev_priv = dev->dev_private;
1618 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1619 struct intel_pipe_crc_entry *entry;
1620 int head, tail;
1621
1622 spin_lock(&pipe_crc->lock);
1623
1624 if (!pipe_crc->entries) {
1625 spin_unlock(&pipe_crc->lock);
1626 DRM_ERROR("spurious interrupt\n");
1627 return;
1628 }
1629
1630 head = pipe_crc->head;
1631 tail = pipe_crc->tail;
1632
1633 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1634 spin_unlock(&pipe_crc->lock);
1635 DRM_ERROR("CRC buffer overflowing\n");
1636 return;
1637 }
1638
1639 entry = &pipe_crc->entries[head];
1640
1641 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1642 entry->crc[0] = crc0;
1643 entry->crc[1] = crc1;
1644 entry->crc[2] = crc2;
1645 entry->crc[3] = crc3;
1646 entry->crc[4] = crc4;
1647
1648 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1649 pipe_crc->head = head;
1650
1651 spin_unlock(&pipe_crc->lock);
1652
1653 wake_up_interruptible(&pipe_crc->wq);
1654 }
1655 #else
1656 static inline void
1657 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1658 uint32_t crc0, uint32_t crc1,
1659 uint32_t crc2, uint32_t crc3,
1660 uint32_t crc4) {}
1661 #endif
1662
1663
1664 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1665 {
1666 struct drm_i915_private *dev_priv = dev->dev_private;
1667
1668 display_pipe_crc_irq_handler(dev, pipe,
1669 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1670 0, 0, 0, 0);
1671 }
1672
1673 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1674 {
1675 struct drm_i915_private *dev_priv = dev->dev_private;
1676
1677 display_pipe_crc_irq_handler(dev, pipe,
1678 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1679 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1680 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1681 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1682 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1683 }
1684
1685 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1686 {
1687 struct drm_i915_private *dev_priv = dev->dev_private;
1688 uint32_t res1, res2;
1689
1690 if (INTEL_INFO(dev)->gen >= 3)
1691 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1692 else
1693 res1 = 0;
1694
1695 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1696 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1697 else
1698 res2 = 0;
1699
1700 display_pipe_crc_irq_handler(dev, pipe,
1701 I915_READ(PIPE_CRC_RES_RED(pipe)),
1702 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1703 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1704 res1, res2);
1705 }
1706
1707 /* The RPS events need forcewake, so we add them to a work queue and mask their
1708 * IMR bits until the work is done. Other interrupts can be processed without
1709 * the work queue. */
1710 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1711 {
1712 /* TODO: RPS on GEN9+ is not supported yet. */
1713 if (WARN_ONCE(INTEL_INFO(dev_priv)->gen >= 9,
1714 "GEN9+: unexpected RPS IRQ\n"))
1715 return;
1716
1717 if (pm_iir & dev_priv->pm_rps_events) {
1718 spin_lock(&dev_priv->irq_lock);
1719 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1720 if (dev_priv->rps.interrupts_enabled) {
1721 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1722 queue_work(dev_priv->wq, &dev_priv->rps.work);
1723 }
1724 spin_unlock(&dev_priv->irq_lock);
1725 }
1726
1727 if (INTEL_INFO(dev_priv)->gen >= 8)
1728 return;
1729
1730 if (HAS_VEBOX(dev_priv->dev)) {
1731 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1732 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1733
1734 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1735 i915_handle_error(dev_priv->dev, false,
1736 "VEBOX CS error interrupt 0x%08x",
1737 pm_iir);
1738 }
1739 }
1740 }
1741
1742 static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
1743 {
1744 if (!drm_handle_vblank(dev, pipe))
1745 return false;
1746
1747 return true;
1748 }
1749
1750 static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1751 {
1752 struct drm_i915_private *dev_priv = dev->dev_private;
1753 u32 pipe_stats[I915_MAX_PIPES] = { };
1754 int pipe;
1755
1756 spin_lock(&dev_priv->irq_lock);
1757 for_each_pipe(dev_priv, pipe) {
1758 int reg;
1759 u32 mask, iir_bit = 0;
1760
1761 /*
1762 * PIPESTAT bits get signalled even when the interrupt is
1763 * disabled with the mask bits, and some of the status bits do
1764 * not generate interrupts at all (like the underrun bit). Hence
1765 * we need to be careful that we only handle what we want to
1766 * handle.
1767 */
1768
1769 /* fifo underruns are filterered in the underrun handler. */
1770 mask = PIPE_FIFO_UNDERRUN_STATUS;
1771
1772 switch (pipe) {
1773 case PIPE_A:
1774 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1775 break;
1776 case PIPE_B:
1777 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1778 break;
1779 case PIPE_C:
1780 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1781 break;
1782 }
1783 if (iir & iir_bit)
1784 mask |= dev_priv->pipestat_irq_mask[pipe];
1785
1786 if (!mask)
1787 continue;
1788
1789 reg = PIPESTAT(pipe);
1790 mask |= PIPESTAT_INT_ENABLE_MASK;
1791 pipe_stats[pipe] = I915_READ(reg) & mask;
1792
1793 /*
1794 * Clear the PIPE*STAT regs before the IIR
1795 */
1796 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1797 PIPESTAT_INT_STATUS_MASK))
1798 I915_WRITE(reg, pipe_stats[pipe]);
1799 }
1800 spin_unlock(&dev_priv->irq_lock);
1801
1802 for_each_pipe(dev_priv, pipe) {
1803 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1804 intel_pipe_handle_vblank(dev, pipe))
1805 intel_check_page_flip(dev, pipe);
1806
1807 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
1808 intel_prepare_page_flip(dev, pipe);
1809 intel_finish_page_flip(dev, pipe);
1810 }
1811
1812 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1813 i9xx_pipe_crc_irq_handler(dev, pipe);
1814
1815 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1816 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1817 }
1818
1819 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1820 gmbus_irq_handler(dev);
1821 }
1822
1823 static void i9xx_hpd_irq_handler(struct drm_device *dev)
1824 {
1825 struct drm_i915_private *dev_priv = dev->dev_private;
1826 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1827
1828 if (hotplug_status) {
1829 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1830 /*
1831 * Make sure hotplug status is cleared before we clear IIR, or else we
1832 * may miss hotplug events.
1833 */
1834 POSTING_READ(PORT_HOTPLUG_STAT);
1835
1836 if (IS_G4X(dev)) {
1837 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1838
1839 intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_g4x);
1840 } else {
1841 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1842
1843 intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_i915);
1844 }
1845
1846 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) &&
1847 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1848 dp_aux_irq_handler(dev);
1849 }
1850 }
1851
1852 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1853 {
1854 struct drm_device *dev = arg;
1855 struct drm_i915_private *dev_priv = dev->dev_private;
1856 u32 iir, gt_iir, pm_iir;
1857 irqreturn_t ret = IRQ_NONE;
1858
1859 while (true) {
1860 /* Find, clear, then process each source of interrupt */
1861
1862 gt_iir = I915_READ(GTIIR);
1863 if (gt_iir)
1864 I915_WRITE(GTIIR, gt_iir);
1865
1866 pm_iir = I915_READ(GEN6_PMIIR);
1867 if (pm_iir)
1868 I915_WRITE(GEN6_PMIIR, pm_iir);
1869
1870 iir = I915_READ(VLV_IIR);
1871 if (iir) {
1872 /* Consume port before clearing IIR or we'll miss events */
1873 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1874 i9xx_hpd_irq_handler(dev);
1875 I915_WRITE(VLV_IIR, iir);
1876 }
1877
1878 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1879 goto out;
1880
1881 ret = IRQ_HANDLED;
1882
1883 if (gt_iir)
1884 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1885 if (pm_iir)
1886 gen6_rps_irq_handler(dev_priv, pm_iir);
1887 /* Call regardless, as some status bits might not be
1888 * signalled in iir */
1889 valleyview_pipestat_irq_handler(dev, iir);
1890 }
1891
1892 out:
1893 return ret;
1894 }
1895
1896 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1897 {
1898 struct drm_device *dev = arg;
1899 struct drm_i915_private *dev_priv = dev->dev_private;
1900 u32 master_ctl, iir;
1901 irqreturn_t ret = IRQ_NONE;
1902
1903 for (;;) {
1904 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1905 iir = I915_READ(VLV_IIR);
1906
1907 if (master_ctl == 0 && iir == 0)
1908 break;
1909
1910 ret = IRQ_HANDLED;
1911
1912 I915_WRITE(GEN8_MASTER_IRQ, 0);
1913
1914 /* Find, clear, then process each source of interrupt */
1915
1916 if (iir) {
1917 /* Consume port before clearing IIR or we'll miss events */
1918 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1919 i9xx_hpd_irq_handler(dev);
1920 I915_WRITE(VLV_IIR, iir);
1921 }
1922
1923 gen8_gt_irq_handler(dev, dev_priv, master_ctl);
1924
1925 /* Call regardless, as some status bits might not be
1926 * signalled in iir */
1927 valleyview_pipestat_irq_handler(dev, iir);
1928
1929 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
1930 POSTING_READ(GEN8_MASTER_IRQ);
1931 }
1932
1933 return ret;
1934 }
1935
1936 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1937 {
1938 struct drm_i915_private *dev_priv = dev->dev_private;
1939 int pipe;
1940 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1941 u32 dig_hotplug_reg;
1942
1943 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1944 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1945
1946 intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_ibx);
1947
1948 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1949 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1950 SDE_AUDIO_POWER_SHIFT);
1951 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1952 port_name(port));
1953 }
1954
1955 if (pch_iir & SDE_AUX_MASK)
1956 dp_aux_irq_handler(dev);
1957
1958 if (pch_iir & SDE_GMBUS)
1959 gmbus_irq_handler(dev);
1960
1961 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1962 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1963
1964 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1965 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1966
1967 if (pch_iir & SDE_POISON)
1968 DRM_ERROR("PCH poison interrupt\n");
1969
1970 if (pch_iir & SDE_FDI_MASK)
1971 for_each_pipe(dev_priv, pipe)
1972 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1973 pipe_name(pipe),
1974 I915_READ(FDI_RX_IIR(pipe)));
1975
1976 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1977 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1978
1979 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1980 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1981
1982 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1983 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1984
1985 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1986 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
1987 }
1988
1989 static void ivb_err_int_handler(struct drm_device *dev)
1990 {
1991 struct drm_i915_private *dev_priv = dev->dev_private;
1992 u32 err_int = I915_READ(GEN7_ERR_INT);
1993 enum pipe pipe;
1994
1995 if (err_int & ERR_INT_POISON)
1996 DRM_ERROR("Poison interrupt\n");
1997
1998 for_each_pipe(dev_priv, pipe) {
1999 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
2000 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2001
2002 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
2003 if (IS_IVYBRIDGE(dev))
2004 ivb_pipe_crc_irq_handler(dev, pipe);
2005 else
2006 hsw_pipe_crc_irq_handler(dev, pipe);
2007 }
2008 }
2009
2010 I915_WRITE(GEN7_ERR_INT, err_int);
2011 }
2012
2013 static void cpt_serr_int_handler(struct drm_device *dev)
2014 {
2015 struct drm_i915_private *dev_priv = dev->dev_private;
2016 u32 serr_int = I915_READ(SERR_INT);
2017
2018 if (serr_int & SERR_INT_POISON)
2019 DRM_ERROR("PCH poison interrupt\n");
2020
2021 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2022 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2023
2024 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2025 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2026
2027 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2028 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
2029
2030 I915_WRITE(SERR_INT, serr_int);
2031 }
2032
2033 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
2034 {
2035 struct drm_i915_private *dev_priv = dev->dev_private;
2036 int pipe;
2037 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2038 u32 dig_hotplug_reg;
2039
2040 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2041 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2042
2043 intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_cpt);
2044
2045 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2046 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2047 SDE_AUDIO_POWER_SHIFT_CPT);
2048 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2049 port_name(port));
2050 }
2051
2052 if (pch_iir & SDE_AUX_MASK_CPT)
2053 dp_aux_irq_handler(dev);
2054
2055 if (pch_iir & SDE_GMBUS_CPT)
2056 gmbus_irq_handler(dev);
2057
2058 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2059 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2060
2061 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2062 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2063
2064 if (pch_iir & SDE_FDI_MASK_CPT)
2065 for_each_pipe(dev_priv, pipe)
2066 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2067 pipe_name(pipe),
2068 I915_READ(FDI_RX_IIR(pipe)));
2069
2070 if (pch_iir & SDE_ERROR_CPT)
2071 cpt_serr_int_handler(dev);
2072 }
2073
2074 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
2075 {
2076 struct drm_i915_private *dev_priv = dev->dev_private;
2077 enum pipe pipe;
2078
2079 if (de_iir & DE_AUX_CHANNEL_A)
2080 dp_aux_irq_handler(dev);
2081
2082 if (de_iir & DE_GSE)
2083 intel_opregion_asle_intr(dev);
2084
2085 if (de_iir & DE_POISON)
2086 DRM_ERROR("Poison interrupt\n");
2087
2088 for_each_pipe(dev_priv, pipe) {
2089 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2090 intel_pipe_handle_vblank(dev, pipe))
2091 intel_check_page_flip(dev, pipe);
2092
2093 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2094 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2095
2096 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2097 i9xx_pipe_crc_irq_handler(dev, pipe);
2098
2099 /* plane/pipes map 1:1 on ilk+ */
2100 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
2101 intel_prepare_page_flip(dev, pipe);
2102 intel_finish_page_flip_plane(dev, pipe);
2103 }
2104 }
2105
2106 /* check event from PCH */
2107 if (de_iir & DE_PCH_EVENT) {
2108 u32 pch_iir = I915_READ(SDEIIR);
2109
2110 if (HAS_PCH_CPT(dev))
2111 cpt_irq_handler(dev, pch_iir);
2112 else
2113 ibx_irq_handler(dev, pch_iir);
2114
2115 /* should clear PCH hotplug event before clear CPU irq */
2116 I915_WRITE(SDEIIR, pch_iir);
2117 }
2118
2119 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
2120 ironlake_rps_change_irq_handler(dev);
2121 }
2122
2123 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
2124 {
2125 struct drm_i915_private *dev_priv = dev->dev_private;
2126 enum pipe pipe;
2127
2128 if (de_iir & DE_ERR_INT_IVB)
2129 ivb_err_int_handler(dev);
2130
2131 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2132 dp_aux_irq_handler(dev);
2133
2134 if (de_iir & DE_GSE_IVB)
2135 intel_opregion_asle_intr(dev);
2136
2137 for_each_pipe(dev_priv, pipe) {
2138 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2139 intel_pipe_handle_vblank(dev, pipe))
2140 intel_check_page_flip(dev, pipe);
2141
2142 /* plane/pipes map 1:1 on ilk+ */
2143 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
2144 intel_prepare_page_flip(dev, pipe);
2145 intel_finish_page_flip_plane(dev, pipe);
2146 }
2147 }
2148
2149 /* check event from PCH */
2150 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
2151 u32 pch_iir = I915_READ(SDEIIR);
2152
2153 cpt_irq_handler(dev, pch_iir);
2154
2155 /* clear PCH hotplug event before clear CPU irq */
2156 I915_WRITE(SDEIIR, pch_iir);
2157 }
2158 }
2159
2160 /*
2161 * To handle irqs with the minimum potential races with fresh interrupts, we:
2162 * 1 - Disable Master Interrupt Control.
2163 * 2 - Find the source(s) of the interrupt.
2164 * 3 - Clear the Interrupt Identity bits (IIR).
2165 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2166 * 5 - Re-enable Master Interrupt Control.
2167 */
2168 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2169 {
2170 struct drm_device *dev = arg;
2171 struct drm_i915_private *dev_priv = dev->dev_private;
2172 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2173 irqreturn_t ret = IRQ_NONE;
2174
2175 /* We get interrupts on unclaimed registers, so check for this before we
2176 * do any I915_{READ,WRITE}. */
2177 intel_uncore_check_errors(dev);
2178
2179 /* disable master interrupt before clearing iir */
2180 de_ier = I915_READ(DEIER);
2181 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2182 POSTING_READ(DEIER);
2183
2184 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2185 * interrupts will will be stored on its back queue, and then we'll be
2186 * able to process them after we restore SDEIER (as soon as we restore
2187 * it, we'll get an interrupt if SDEIIR still has something to process
2188 * due to its back queue). */
2189 if (!HAS_PCH_NOP(dev)) {
2190 sde_ier = I915_READ(SDEIER);
2191 I915_WRITE(SDEIER, 0);
2192 POSTING_READ(SDEIER);
2193 }
2194
2195 /* Find, clear, then process each source of interrupt */
2196
2197 gt_iir = I915_READ(GTIIR);
2198 if (gt_iir) {
2199 I915_WRITE(GTIIR, gt_iir);
2200 ret = IRQ_HANDLED;
2201 if (INTEL_INFO(dev)->gen >= 6)
2202 snb_gt_irq_handler(dev, dev_priv, gt_iir);
2203 else
2204 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
2205 }
2206
2207 de_iir = I915_READ(DEIIR);
2208 if (de_iir) {
2209 I915_WRITE(DEIIR, de_iir);
2210 ret = IRQ_HANDLED;
2211 if (INTEL_INFO(dev)->gen >= 7)
2212 ivb_display_irq_handler(dev, de_iir);
2213 else
2214 ilk_display_irq_handler(dev, de_iir);
2215 }
2216
2217 if (INTEL_INFO(dev)->gen >= 6) {
2218 u32 pm_iir = I915_READ(GEN6_PMIIR);
2219 if (pm_iir) {
2220 I915_WRITE(GEN6_PMIIR, pm_iir);
2221 ret = IRQ_HANDLED;
2222 gen6_rps_irq_handler(dev_priv, pm_iir);
2223 }
2224 }
2225
2226 I915_WRITE(DEIER, de_ier);
2227 POSTING_READ(DEIER);
2228 if (!HAS_PCH_NOP(dev)) {
2229 I915_WRITE(SDEIER, sde_ier);
2230 POSTING_READ(SDEIER);
2231 }
2232
2233 return ret;
2234 }
2235
2236 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2237 {
2238 struct drm_device *dev = arg;
2239 struct drm_i915_private *dev_priv = dev->dev_private;
2240 u32 master_ctl;
2241 irqreturn_t ret = IRQ_NONE;
2242 uint32_t tmp = 0;
2243 enum pipe pipe;
2244 u32 aux_mask = GEN8_AUX_CHANNEL_A;
2245
2246 if (IS_GEN9(dev))
2247 aux_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
2248 GEN9_AUX_CHANNEL_D;
2249
2250 master_ctl = I915_READ(GEN8_MASTER_IRQ);
2251 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2252 if (!master_ctl)
2253 return IRQ_NONE;
2254
2255 I915_WRITE(GEN8_MASTER_IRQ, 0);
2256 POSTING_READ(GEN8_MASTER_IRQ);
2257
2258 /* Find, clear, then process each source of interrupt */
2259
2260 ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
2261
2262 if (master_ctl & GEN8_DE_MISC_IRQ) {
2263 tmp = I915_READ(GEN8_DE_MISC_IIR);
2264 if (tmp) {
2265 I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2266 ret = IRQ_HANDLED;
2267 if (tmp & GEN8_DE_MISC_GSE)
2268 intel_opregion_asle_intr(dev);
2269 else
2270 DRM_ERROR("Unexpected DE Misc interrupt\n");
2271 }
2272 else
2273 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2274 }
2275
2276 if (master_ctl & GEN8_DE_PORT_IRQ) {
2277 tmp = I915_READ(GEN8_DE_PORT_IIR);
2278 if (tmp) {
2279 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2280 ret = IRQ_HANDLED;
2281
2282 if (tmp & aux_mask)
2283 dp_aux_irq_handler(dev);
2284 else
2285 DRM_ERROR("Unexpected DE Port interrupt\n");
2286 }
2287 else
2288 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2289 }
2290
2291 for_each_pipe(dev_priv, pipe) {
2292 uint32_t pipe_iir, flip_done = 0, fault_errors = 0;
2293
2294 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2295 continue;
2296
2297 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2298 if (pipe_iir) {
2299 ret = IRQ_HANDLED;
2300 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2301
2302 if (pipe_iir & GEN8_PIPE_VBLANK &&
2303 intel_pipe_handle_vblank(dev, pipe))
2304 intel_check_page_flip(dev, pipe);
2305
2306 if (IS_GEN9(dev))
2307 flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE;
2308 else
2309 flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE;
2310
2311 if (flip_done) {
2312 intel_prepare_page_flip(dev, pipe);
2313 intel_finish_page_flip_plane(dev, pipe);
2314 }
2315
2316 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2317 hsw_pipe_crc_irq_handler(dev, pipe);
2318
2319 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN)
2320 intel_cpu_fifo_underrun_irq_handler(dev_priv,
2321 pipe);
2322
2323
2324 if (IS_GEN9(dev))
2325 fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2326 else
2327 fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2328
2329 if (fault_errors)
2330 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2331 pipe_name(pipe),
2332 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2333 } else
2334 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2335 }
2336
2337 if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
2338 /*
2339 * FIXME(BDW): Assume for now that the new interrupt handling
2340 * scheme also closed the SDE interrupt handling race we've seen
2341 * on older pch-split platforms. But this needs testing.
2342 */
2343 u32 pch_iir = I915_READ(SDEIIR);
2344 if (pch_iir) {
2345 I915_WRITE(SDEIIR, pch_iir);
2346 ret = IRQ_HANDLED;
2347 cpt_irq_handler(dev, pch_iir);
2348 } else
2349 DRM_ERROR("The master control interrupt lied (SDE)!\n");
2350
2351 }
2352
2353 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2354 POSTING_READ(GEN8_MASTER_IRQ);
2355
2356 return ret;
2357 }
2358
2359 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2360 bool reset_completed)
2361 {
2362 struct intel_engine_cs *ring;
2363 int i;
2364
2365 /*
2366 * Notify all waiters for GPU completion events that reset state has
2367 * been changed, and that they need to restart their wait after
2368 * checking for potential errors (and bail out to drop locks if there is
2369 * a gpu reset pending so that i915_error_work_func can acquire them).
2370 */
2371
2372 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2373 for_each_ring(ring, dev_priv, i)
2374 wake_up_all(&ring->irq_queue);
2375
2376 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2377 wake_up_all(&dev_priv->pending_flip_queue);
2378
2379 /*
2380 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2381 * reset state is cleared.
2382 */
2383 if (reset_completed)
2384 wake_up_all(&dev_priv->gpu_error.reset_queue);
2385 }
2386
2387 /**
2388 * i915_error_work_func - do process context error handling work
2389 * @work: work struct
2390 *
2391 * Fire an error uevent so userspace can see that a hang or error
2392 * was detected.
2393 */
2394 static void i915_error_work_func(struct work_struct *work)
2395 {
2396 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
2397 work);
2398 struct drm_i915_private *dev_priv =
2399 container_of(error, struct drm_i915_private, gpu_error);
2400 struct drm_device *dev = dev_priv->dev;
2401 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2402 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2403 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2404 int ret;
2405
2406 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2407
2408 /*
2409 * Note that there's only one work item which does gpu resets, so we
2410 * need not worry about concurrent gpu resets potentially incrementing
2411 * error->reset_counter twice. We only need to take care of another
2412 * racing irq/hangcheck declaring the gpu dead for a second time. A
2413 * quick check for that is good enough: schedule_work ensures the
2414 * correct ordering between hang detection and this work item, and since
2415 * the reset in-progress bit is only ever set by code outside of this
2416 * work we don't need to worry about any other races.
2417 */
2418 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2419 DRM_DEBUG_DRIVER("resetting chip\n");
2420 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2421 reset_event);
2422
2423 /*
2424 * In most cases it's guaranteed that we get here with an RPM
2425 * reference held, for example because there is a pending GPU
2426 * request that won't finish until the reset is done. This
2427 * isn't the case at least when we get here by doing a
2428 * simulated reset via debugs, so get an RPM reference.
2429 */
2430 intel_runtime_pm_get(dev_priv);
2431 /*
2432 * All state reset _must_ be completed before we update the
2433 * reset counter, for otherwise waiters might miss the reset
2434 * pending state and not properly drop locks, resulting in
2435 * deadlocks with the reset work.
2436 */
2437 ret = i915_reset(dev);
2438
2439 intel_display_handle_reset(dev);
2440
2441 intel_runtime_pm_put(dev_priv);
2442
2443 if (ret == 0) {
2444 /*
2445 * After all the gem state is reset, increment the reset
2446 * counter and wake up everyone waiting for the reset to
2447 * complete.
2448 *
2449 * Since unlock operations are a one-sided barrier only,
2450 * we need to insert a barrier here to order any seqno
2451 * updates before
2452 * the counter increment.
2453 */
2454 smp_mb__before_atomic();
2455 atomic_inc(&dev_priv->gpu_error.reset_counter);
2456
2457 kobject_uevent_env(&dev->primary->kdev->kobj,
2458 KOBJ_CHANGE, reset_done_event);
2459 } else {
2460 atomic_set_mask(I915_WEDGED, &error->reset_counter);
2461 }
2462
2463 /*
2464 * Note: The wake_up also serves as a memory barrier so that
2465 * waiters see the update value of the reset counter atomic_t.
2466 */
2467 i915_error_wake_up(dev_priv, true);
2468 }
2469 }
2470
2471 static void i915_report_and_clear_eir(struct drm_device *dev)
2472 {
2473 struct drm_i915_private *dev_priv = dev->dev_private;
2474 uint32_t instdone[I915_NUM_INSTDONE_REG];
2475 u32 eir = I915_READ(EIR);
2476 int pipe, i;
2477
2478 if (!eir)
2479 return;
2480
2481 pr_err("render error detected, EIR: 0x%08x\n", eir);
2482
2483 i915_get_extra_instdone(dev, instdone);
2484
2485 if (IS_G4X(dev)) {
2486 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2487 u32 ipeir = I915_READ(IPEIR_I965);
2488
2489 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2490 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2491 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2492 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2493 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2494 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2495 I915_WRITE(IPEIR_I965, ipeir);
2496 POSTING_READ(IPEIR_I965);
2497 }
2498 if (eir & GM45_ERROR_PAGE_TABLE) {
2499 u32 pgtbl_err = I915_READ(PGTBL_ER);
2500 pr_err("page table error\n");
2501 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2502 I915_WRITE(PGTBL_ER, pgtbl_err);
2503 POSTING_READ(PGTBL_ER);
2504 }
2505 }
2506
2507 if (!IS_GEN2(dev)) {
2508 if (eir & I915_ERROR_PAGE_TABLE) {
2509 u32 pgtbl_err = I915_READ(PGTBL_ER);
2510 pr_err("page table error\n");
2511 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2512 I915_WRITE(PGTBL_ER, pgtbl_err);
2513 POSTING_READ(PGTBL_ER);
2514 }
2515 }
2516
2517 if (eir & I915_ERROR_MEMORY_REFRESH) {
2518 pr_err("memory refresh error:\n");
2519 for_each_pipe(dev_priv, pipe)
2520 pr_err("pipe %c stat: 0x%08x\n",
2521 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2522 /* pipestat has already been acked */
2523 }
2524 if (eir & I915_ERROR_INSTRUCTION) {
2525 pr_err("instruction error\n");
2526 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
2527 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2528 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2529 if (INTEL_INFO(dev)->gen < 4) {
2530 u32 ipeir = I915_READ(IPEIR);
2531
2532 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2533 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
2534 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
2535 I915_WRITE(IPEIR, ipeir);
2536 POSTING_READ(IPEIR);
2537 } else {
2538 u32 ipeir = I915_READ(IPEIR_I965);
2539
2540 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2541 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2542 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2543 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2544 I915_WRITE(IPEIR_I965, ipeir);
2545 POSTING_READ(IPEIR_I965);
2546 }
2547 }
2548
2549 I915_WRITE(EIR, eir);
2550 POSTING_READ(EIR);
2551 eir = I915_READ(EIR);
2552 if (eir) {
2553 /*
2554 * some errors might have become stuck,
2555 * mask them.
2556 */
2557 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2558 I915_WRITE(EMR, I915_READ(EMR) | eir);
2559 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2560 }
2561 }
2562
2563 /**
2564 * i915_handle_error - handle an error interrupt
2565 * @dev: drm device
2566 *
2567 * Do some basic checking of regsiter state at error interrupt time and
2568 * dump it to the syslog. Also call i915_capture_error_state() to make
2569 * sure we get a record and make it available in debugfs. Fire a uevent
2570 * so userspace knows something bad happened (should trigger collection
2571 * of a ring dump etc.).
2572 */
2573 void i915_handle_error(struct drm_device *dev, bool wedged,
2574 const char *fmt, ...)
2575 {
2576 struct drm_i915_private *dev_priv = dev->dev_private;
2577 va_list args;
2578 char error_msg[80];
2579
2580 va_start(args, fmt);
2581 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2582 va_end(args);
2583
2584 i915_capture_error_state(dev, wedged, error_msg);
2585 i915_report_and_clear_eir(dev);
2586
2587 if (wedged) {
2588 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2589 &dev_priv->gpu_error.reset_counter);
2590
2591 /*
2592 * Wakeup waiting processes so that the reset work function
2593 * i915_error_work_func doesn't deadlock trying to grab various
2594 * locks. By bumping the reset counter first, the woken
2595 * processes will see a reset in progress and back off,
2596 * releasing their locks and then wait for the reset completion.
2597 * We must do this for _all_ gpu waiters that might hold locks
2598 * that the reset work needs to acquire.
2599 *
2600 * Note: The wake_up serves as the required memory barrier to
2601 * ensure that the waiters see the updated value of the reset
2602 * counter atomic_t.
2603 */
2604 i915_error_wake_up(dev_priv, false);
2605 }
2606
2607 /*
2608 * Our reset work can grab modeset locks (since it needs to reset the
2609 * state of outstanding pagelips). Hence it must not be run on our own
2610 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2611 * code will deadlock.
2612 */
2613 schedule_work(&dev_priv->gpu_error.work);
2614 }
2615
2616 /* Called from drm generic code, passed 'crtc' which
2617 * we use as a pipe index
2618 */
2619 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2620 {
2621 struct drm_i915_private *dev_priv = dev->dev_private;
2622 unsigned long irqflags;
2623
2624 if (!i915_pipe_enabled(dev, pipe))
2625 return -EINVAL;
2626
2627 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2628 if (INTEL_INFO(dev)->gen >= 4)
2629 i915_enable_pipestat(dev_priv, pipe,
2630 PIPE_START_VBLANK_INTERRUPT_STATUS);
2631 else
2632 i915_enable_pipestat(dev_priv, pipe,
2633 PIPE_VBLANK_INTERRUPT_STATUS);
2634 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2635
2636 return 0;
2637 }
2638
2639 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2640 {
2641 struct drm_i915_private *dev_priv = dev->dev_private;
2642 unsigned long irqflags;
2643 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2644 DE_PIPE_VBLANK(pipe);
2645
2646 if (!i915_pipe_enabled(dev, pipe))
2647 return -EINVAL;
2648
2649 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2650 ironlake_enable_display_irq(dev_priv, bit);
2651 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2652
2653 return 0;
2654 }
2655
2656 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2657 {
2658 struct drm_i915_private *dev_priv = dev->dev_private;
2659 unsigned long irqflags;
2660
2661 if (!i915_pipe_enabled(dev, pipe))
2662 return -EINVAL;
2663
2664 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2665 i915_enable_pipestat(dev_priv, pipe,
2666 PIPE_START_VBLANK_INTERRUPT_STATUS);
2667 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2668
2669 return 0;
2670 }
2671
2672 static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2673 {
2674 struct drm_i915_private *dev_priv = dev->dev_private;
2675 unsigned long irqflags;
2676
2677 if (!i915_pipe_enabled(dev, pipe))
2678 return -EINVAL;
2679
2680 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2681 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2682 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2683 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2684 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2685 return 0;
2686 }
2687
2688 /* Called from drm generic code, passed 'crtc' which
2689 * we use as a pipe index
2690 */
2691 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2692 {
2693 struct drm_i915_private *dev_priv = dev->dev_private;
2694 unsigned long irqflags;
2695
2696 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2697 i915_disable_pipestat(dev_priv, pipe,
2698 PIPE_VBLANK_INTERRUPT_STATUS |
2699 PIPE_START_VBLANK_INTERRUPT_STATUS);
2700 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2701 }
2702
2703 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2704 {
2705 struct drm_i915_private *dev_priv = dev->dev_private;
2706 unsigned long irqflags;
2707 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2708 DE_PIPE_VBLANK(pipe);
2709
2710 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2711 ironlake_disable_display_irq(dev_priv, bit);
2712 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2713 }
2714
2715 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2716 {
2717 struct drm_i915_private *dev_priv = dev->dev_private;
2718 unsigned long irqflags;
2719
2720 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2721 i915_disable_pipestat(dev_priv, pipe,
2722 PIPE_START_VBLANK_INTERRUPT_STATUS);
2723 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2724 }
2725
2726 static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2727 {
2728 struct drm_i915_private *dev_priv = dev->dev_private;
2729 unsigned long irqflags;
2730
2731 if (!i915_pipe_enabled(dev, pipe))
2732 return;
2733
2734 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2735 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2736 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2737 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2738 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2739 }
2740
2741 static u32
2742 ring_last_seqno(struct intel_engine_cs *ring)
2743 {
2744 return list_entry(ring->request_list.prev,
2745 struct drm_i915_gem_request, list)->seqno;
2746 }
2747
2748 static bool
2749 ring_idle(struct intel_engine_cs *ring, u32 seqno)
2750 {
2751 return (list_empty(&ring->request_list) ||
2752 i915_seqno_passed(seqno, ring_last_seqno(ring)));
2753 }
2754
2755 static bool
2756 ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
2757 {
2758 if (INTEL_INFO(dev)->gen >= 8) {
2759 return (ipehr >> 23) == 0x1c;
2760 } else {
2761 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2762 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2763 MI_SEMAPHORE_REGISTER);
2764 }
2765 }
2766
2767 static struct intel_engine_cs *
2768 semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset)
2769 {
2770 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2771 struct intel_engine_cs *signaller;
2772 int i;
2773
2774 if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
2775 for_each_ring(signaller, dev_priv, i) {
2776 if (ring == signaller)
2777 continue;
2778
2779 if (offset == signaller->semaphore.signal_ggtt[ring->id])
2780 return signaller;
2781 }
2782 } else {
2783 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2784
2785 for_each_ring(signaller, dev_priv, i) {
2786 if(ring == signaller)
2787 continue;
2788
2789 if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
2790 return signaller;
2791 }
2792 }
2793
2794 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2795 ring->id, ipehr, offset);
2796
2797 return NULL;
2798 }
2799
2800 static struct intel_engine_cs *
2801 semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
2802 {
2803 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2804 u32 cmd, ipehr, head;
2805 u64 offset = 0;
2806 int i, backwards;
2807
2808 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2809 if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
2810 return NULL;
2811
2812 /*
2813 * HEAD is likely pointing to the dword after the actual command,
2814 * so scan backwards until we find the MBOX. But limit it to just 3
2815 * or 4 dwords depending on the semaphore wait command size.
2816 * Note that we don't care about ACTHD here since that might
2817 * point at at batch, and semaphores are always emitted into the
2818 * ringbuffer itself.
2819 */
2820 head = I915_READ_HEAD(ring) & HEAD_ADDR;
2821 backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4;
2822
2823 for (i = backwards; i; --i) {
2824 /*
2825 * Be paranoid and presume the hw has gone off into the wild -
2826 * our ring is smaller than what the hardware (and hence
2827 * HEAD_ADDR) allows. Also handles wrap-around.
2828 */
2829 head &= ring->buffer->size - 1;
2830
2831 /* This here seems to blow up */
2832 cmd = ioread32(ring->buffer->virtual_start + head);
2833 if (cmd == ipehr)
2834 break;
2835
2836 head -= 4;
2837 }
2838
2839 if (!i)
2840 return NULL;
2841
2842 *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
2843 if (INTEL_INFO(ring->dev)->gen >= 8) {
2844 offset = ioread32(ring->buffer->virtual_start + head + 12);
2845 offset <<= 32;
2846 offset = ioread32(ring->buffer->virtual_start + head + 8);
2847 }
2848 return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
2849 }
2850
2851 static int semaphore_passed(struct intel_engine_cs *ring)
2852 {
2853 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2854 struct intel_engine_cs *signaller;
2855 u32 seqno;
2856
2857 ring->hangcheck.deadlock++;
2858
2859 signaller = semaphore_waits_for(ring, &seqno);
2860 if (signaller == NULL)
2861 return -1;
2862
2863 /* Prevent pathological recursion due to driver bugs */
2864 if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
2865 return -1;
2866
2867 if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
2868 return 1;
2869
2870 /* cursory check for an unkickable deadlock */
2871 if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
2872 semaphore_passed(signaller) < 0)
2873 return -1;
2874
2875 return 0;
2876 }
2877
2878 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2879 {
2880 struct intel_engine_cs *ring;
2881 int i;
2882
2883 for_each_ring(ring, dev_priv, i)
2884 ring->hangcheck.deadlock = 0;
2885 }
2886
2887 static enum intel_ring_hangcheck_action
2888 ring_stuck(struct intel_engine_cs *ring, u64 acthd)
2889 {
2890 struct drm_device *dev = ring->dev;
2891 struct drm_i915_private *dev_priv = dev->dev_private;
2892 u32 tmp;
2893
2894 if (acthd != ring->hangcheck.acthd) {
2895 if (acthd > ring->hangcheck.max_acthd) {
2896 ring->hangcheck.max_acthd = acthd;
2897 return HANGCHECK_ACTIVE;
2898 }
2899
2900 return HANGCHECK_ACTIVE_LOOP;
2901 }
2902
2903 if (IS_GEN2(dev))
2904 return HANGCHECK_HUNG;
2905
2906 /* Is the chip hanging on a WAIT_FOR_EVENT?
2907 * If so we can simply poke the RB_WAIT bit
2908 * and break the hang. This should work on
2909 * all but the second generation chipsets.
2910 */
2911 tmp = I915_READ_CTL(ring);
2912 if (tmp & RING_WAIT) {
2913 i915_handle_error(dev, false,
2914 "Kicking stuck wait on %s",
2915 ring->name);
2916 I915_WRITE_CTL(ring, tmp);
2917 return HANGCHECK_KICK;
2918 }
2919
2920 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2921 switch (semaphore_passed(ring)) {
2922 default:
2923 return HANGCHECK_HUNG;
2924 case 1:
2925 i915_handle_error(dev, false,
2926 "Kicking stuck semaphore on %s",
2927 ring->name);
2928 I915_WRITE_CTL(ring, tmp);
2929 return HANGCHECK_KICK;
2930 case 0:
2931 return HANGCHECK_WAIT;
2932 }
2933 }
2934
2935 return HANGCHECK_HUNG;
2936 }
2937
2938 /**
2939 * This is called when the chip hasn't reported back with completed
2940 * batchbuffers in a long time. We keep track per ring seqno progress and
2941 * if there are no progress, hangcheck score for that ring is increased.
2942 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2943 * we kick the ring. If we see no progress on three subsequent calls
2944 * we assume chip is wedged and try to fix it by resetting the chip.
2945 */
2946 static void i915_hangcheck_elapsed(unsigned long data)
2947 {
2948 struct drm_device *dev = (struct drm_device *)data;
2949 struct drm_i915_private *dev_priv = dev->dev_private;
2950 struct intel_engine_cs *ring;
2951 int i;
2952 int busy_count = 0, rings_hung = 0;
2953 bool stuck[I915_NUM_RINGS] = { 0 };
2954 #define BUSY 1
2955 #define KICK 5
2956 #define HUNG 20
2957
2958 if (!i915.enable_hangcheck)
2959 return;
2960
2961 for_each_ring(ring, dev_priv, i) {
2962 u64 acthd;
2963 u32 seqno;
2964 bool busy = true;
2965
2966 semaphore_clear_deadlocks(dev_priv);
2967
2968 seqno = ring->get_seqno(ring, false);
2969 acthd = intel_ring_get_active_head(ring);
2970
2971 if (ring->hangcheck.seqno == seqno) {
2972 if (ring_idle(ring, seqno)) {
2973 ring->hangcheck.action = HANGCHECK_IDLE;
2974
2975 if (waitqueue_active(&ring->irq_queue)) {
2976 /* Issue a wake-up to catch stuck h/w. */
2977 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2978 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2979 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2980 ring->name);
2981 else
2982 DRM_INFO("Fake missed irq on %s\n",
2983 ring->name);
2984 wake_up_all(&ring->irq_queue);
2985 }
2986 /* Safeguard against driver failure */
2987 ring->hangcheck.score += BUSY;
2988 } else
2989 busy = false;
2990 } else {
2991 /* We always increment the hangcheck score
2992 * if the ring is busy and still processing
2993 * the same request, so that no single request
2994 * can run indefinitely (such as a chain of
2995 * batches). The only time we do not increment
2996 * the hangcheck score on this ring, if this
2997 * ring is in a legitimate wait for another
2998 * ring. In that case the waiting ring is a
2999 * victim and we want to be sure we catch the
3000 * right culprit. Then every time we do kick
3001 * the ring, add a small increment to the
3002 * score so that we can catch a batch that is
3003 * being repeatedly kicked and so responsible
3004 * for stalling the machine.
3005 */
3006 ring->hangcheck.action = ring_stuck(ring,
3007 acthd);
3008
3009 switch (ring->hangcheck.action) {
3010 case HANGCHECK_IDLE:
3011 case HANGCHECK_WAIT:
3012 case HANGCHECK_ACTIVE:
3013 break;
3014 case HANGCHECK_ACTIVE_LOOP:
3015 ring->hangcheck.score += BUSY;
3016 break;
3017 case HANGCHECK_KICK:
3018 ring->hangcheck.score += KICK;
3019 break;
3020 case HANGCHECK_HUNG:
3021 ring->hangcheck.score += HUNG;
3022 stuck[i] = true;
3023 break;
3024 }
3025 }
3026 } else {
3027 ring->hangcheck.action = HANGCHECK_ACTIVE;
3028
3029 /* Gradually reduce the count so that we catch DoS
3030 * attempts across multiple batches.
3031 */
3032 if (ring->hangcheck.score > 0)
3033 ring->hangcheck.score--;
3034
3035 ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0;
3036 }
3037
3038 ring->hangcheck.seqno = seqno;
3039 ring->hangcheck.acthd = acthd;
3040 busy_count += busy;
3041 }
3042
3043 for_each_ring(ring, dev_priv, i) {
3044 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3045 DRM_INFO("%s on %s\n",
3046 stuck[i] ? "stuck" : "no progress",
3047 ring->name);
3048 rings_hung++;
3049 }
3050 }
3051
3052 if (rings_hung)
3053 return i915_handle_error(dev, true, "Ring hung");
3054
3055 if (busy_count)
3056 /* Reset timer case chip hangs without another request
3057 * being added */
3058 i915_queue_hangcheck(dev);
3059 }
3060
3061 void i915_queue_hangcheck(struct drm_device *dev)
3062 {
3063 struct drm_i915_private *dev_priv = dev->dev_private;
3064 struct timer_list *timer = &dev_priv->gpu_error.hangcheck_timer;
3065
3066 if (!i915.enable_hangcheck)
3067 return;
3068
3069 /* Don't continually defer the hangcheck, but make sure it is active */
3070 if (timer_pending(timer))
3071 return;
3072 mod_timer(timer,
3073 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
3074 }
3075
3076 static void ibx_irq_reset(struct drm_device *dev)
3077 {
3078 struct drm_i915_private *dev_priv = dev->dev_private;
3079
3080 if (HAS_PCH_NOP(dev))
3081 return;
3082
3083 GEN5_IRQ_RESET(SDE);
3084
3085 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3086 I915_WRITE(SERR_INT, 0xffffffff);
3087 }
3088
3089 /*
3090 * SDEIER is also touched by the interrupt handler to work around missed PCH
3091 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3092 * instead we unconditionally enable all PCH interrupt sources here, but then
3093 * only unmask them as needed with SDEIMR.
3094 *
3095 * This function needs to be called before interrupts are enabled.
3096 */
3097 static void ibx_irq_pre_postinstall(struct drm_device *dev)
3098 {
3099 struct drm_i915_private *dev_priv = dev->dev_private;
3100
3101 if (HAS_PCH_NOP(dev))
3102 return;
3103
3104 WARN_ON(I915_READ(SDEIER) != 0);
3105 I915_WRITE(SDEIER, 0xffffffff);
3106 POSTING_READ(SDEIER);
3107 }
3108
3109 static void gen5_gt_irq_reset(struct drm_device *dev)
3110 {
3111 struct drm_i915_private *dev_priv = dev->dev_private;
3112
3113 GEN5_IRQ_RESET(GT);
3114 if (INTEL_INFO(dev)->gen >= 6)
3115 GEN5_IRQ_RESET(GEN6_PM);
3116 }
3117
3118 /* drm_dma.h hooks
3119 */
3120 static void ironlake_irq_reset(struct drm_device *dev)
3121 {
3122 struct drm_i915_private *dev_priv = dev->dev_private;
3123
3124 I915_WRITE(HWSTAM, 0xffffffff);
3125
3126 GEN5_IRQ_RESET(DE);
3127 if (IS_GEN7(dev))
3128 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3129
3130 gen5_gt_irq_reset(dev);
3131
3132 ibx_irq_reset(dev);
3133 }
3134
3135 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3136 {
3137 enum pipe pipe;
3138
3139 I915_WRITE(PORT_HOTPLUG_EN, 0);
3140 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3141
3142 for_each_pipe(dev_priv, pipe)
3143 I915_WRITE(PIPESTAT(pipe), 0xffff);
3144
3145 GEN5_IRQ_RESET(VLV_);
3146 }
3147
3148 static void valleyview_irq_preinstall(struct drm_device *dev)
3149 {
3150 struct drm_i915_private *dev_priv = dev->dev_private;
3151
3152 /* VLV magic */
3153 I915_WRITE(VLV_IMR, 0);
3154 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
3155 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
3156 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
3157
3158 gen5_gt_irq_reset(dev);
3159
3160 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3161
3162 vlv_display_irq_reset(dev_priv);
3163 }
3164
3165 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3166 {
3167 GEN8_IRQ_RESET_NDX(GT, 0);
3168 GEN8_IRQ_RESET_NDX(GT, 1);
3169 GEN8_IRQ_RESET_NDX(GT, 2);
3170 GEN8_IRQ_RESET_NDX(GT, 3);
3171 }
3172
3173 static void gen8_irq_reset(struct drm_device *dev)
3174 {
3175 struct drm_i915_private *dev_priv = dev->dev_private;
3176 int pipe;
3177
3178 I915_WRITE(GEN8_MASTER_IRQ, 0);
3179 POSTING_READ(GEN8_MASTER_IRQ);
3180
3181 gen8_gt_irq_reset(dev_priv);
3182
3183 for_each_pipe(dev_priv, pipe)
3184 if (intel_display_power_is_enabled(dev_priv,
3185 POWER_DOMAIN_PIPE(pipe)))
3186 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3187
3188 GEN5_IRQ_RESET(GEN8_DE_PORT_);
3189 GEN5_IRQ_RESET(GEN8_DE_MISC_);
3190 GEN5_IRQ_RESET(GEN8_PCU_);
3191
3192 ibx_irq_reset(dev);
3193 }
3194
3195 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv)
3196 {
3197 uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3198
3199 spin_lock_irq(&dev_priv->irq_lock);
3200 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B],
3201 ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
3202 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C],
3203 ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
3204 spin_unlock_irq(&dev_priv->irq_lock);
3205 }
3206
3207 static void cherryview_irq_preinstall(struct drm_device *dev)
3208 {
3209 struct drm_i915_private *dev_priv = dev->dev_private;
3210
3211 I915_WRITE(GEN8_MASTER_IRQ, 0);
3212 POSTING_READ(GEN8_MASTER_IRQ);
3213
3214 gen8_gt_irq_reset(dev_priv);
3215
3216 GEN5_IRQ_RESET(GEN8_PCU_);
3217
3218 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3219
3220 vlv_display_irq_reset(dev_priv);
3221 }
3222
3223 static void ibx_hpd_irq_setup(struct drm_device *dev)
3224 {
3225 struct drm_i915_private *dev_priv = dev->dev_private;
3226 struct intel_encoder *intel_encoder;
3227 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
3228
3229 if (HAS_PCH_IBX(dev)) {
3230 hotplug_irqs = SDE_HOTPLUG_MASK;
3231 for_each_intel_encoder(dev, intel_encoder)
3232 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3233 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
3234 } else {
3235 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3236 for_each_intel_encoder(dev, intel_encoder)
3237 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3238 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
3239 }
3240
3241 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3242
3243 /*
3244 * Enable digital hotplug on the PCH, and configure the DP short pulse
3245 * duration to 2ms (which is the minimum in the Display Port spec)
3246 *
3247 * This register is the same on all known PCH chips.
3248 */
3249 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3250 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3251 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3252 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3253 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3254 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3255 }
3256
3257 static void ibx_irq_postinstall(struct drm_device *dev)
3258 {
3259 struct drm_i915_private *dev_priv = dev->dev_private;
3260 u32 mask;
3261
3262 if (HAS_PCH_NOP(dev))
3263 return;
3264
3265 if (HAS_PCH_IBX(dev))
3266 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3267 else
3268 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3269
3270 GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
3271 I915_WRITE(SDEIMR, ~mask);
3272 }
3273
3274 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3275 {
3276 struct drm_i915_private *dev_priv = dev->dev_private;
3277 u32 pm_irqs, gt_irqs;
3278
3279 pm_irqs = gt_irqs = 0;
3280
3281 dev_priv->gt_irq_mask = ~0;
3282 if (HAS_L3_DPF(dev)) {
3283 /* L3 parity interrupt is always unmasked. */
3284 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3285 gt_irqs |= GT_PARITY_ERROR(dev);
3286 }
3287
3288 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3289 if (IS_GEN5(dev)) {
3290 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3291 ILK_BSD_USER_INTERRUPT;
3292 } else {
3293 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3294 }
3295
3296 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3297
3298 if (INTEL_INFO(dev)->gen >= 6) {
3299 pm_irqs |= dev_priv->pm_rps_events;
3300
3301 if (HAS_VEBOX(dev))
3302 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3303
3304 dev_priv->pm_irq_mask = 0xffffffff;
3305 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3306 }
3307 }
3308
3309 static int ironlake_irq_postinstall(struct drm_device *dev)
3310 {
3311 struct drm_i915_private *dev_priv = dev->dev_private;
3312 u32 display_mask, extra_mask;
3313
3314 if (INTEL_INFO(dev)->gen >= 7) {
3315 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3316 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3317 DE_PLANEB_FLIP_DONE_IVB |
3318 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3319 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3320 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
3321 } else {
3322 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3323 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3324 DE_AUX_CHANNEL_A |
3325 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3326 DE_POISON);
3327 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3328 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
3329 }
3330
3331 dev_priv->irq_mask = ~display_mask;
3332
3333 I915_WRITE(HWSTAM, 0xeffe);
3334
3335 ibx_irq_pre_postinstall(dev);
3336
3337 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3338
3339 gen5_gt_irq_postinstall(dev);
3340
3341 ibx_irq_postinstall(dev);
3342
3343 if (IS_IRONLAKE_M(dev)) {
3344 /* Enable PCU event interrupts
3345 *
3346 * spinlocking not required here for correctness since interrupt
3347 * setup is guaranteed to run in single-threaded context. But we
3348 * need it to make the assert_spin_locked happy. */
3349 spin_lock_irq(&dev_priv->irq_lock);
3350 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
3351 spin_unlock_irq(&dev_priv->irq_lock);
3352 }
3353
3354 return 0;
3355 }
3356
3357 static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3358 {
3359 u32 pipestat_mask;
3360 u32 iir_mask;
3361 enum pipe pipe;
3362
3363 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3364 PIPE_FIFO_UNDERRUN_STATUS;
3365
3366 for_each_pipe(dev_priv, pipe)
3367 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3368 POSTING_READ(PIPESTAT(PIPE_A));
3369
3370 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3371 PIPE_CRC_DONE_INTERRUPT_STATUS;
3372
3373 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3374 for_each_pipe(dev_priv, pipe)
3375 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3376
3377 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3378 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3379 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3380 if (IS_CHERRYVIEW(dev_priv))
3381 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3382 dev_priv->irq_mask &= ~iir_mask;
3383
3384 I915_WRITE(VLV_IIR, iir_mask);
3385 I915_WRITE(VLV_IIR, iir_mask);
3386 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3387 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3388 POSTING_READ(VLV_IMR);
3389 }
3390
3391 static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3392 {
3393 u32 pipestat_mask;
3394 u32 iir_mask;
3395 enum pipe pipe;
3396
3397 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3398 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3399 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3400 if (IS_CHERRYVIEW(dev_priv))
3401 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3402
3403 dev_priv->irq_mask |= iir_mask;
3404 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3405 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3406 I915_WRITE(VLV_IIR, iir_mask);
3407 I915_WRITE(VLV_IIR, iir_mask);
3408 POSTING_READ(VLV_IIR);
3409
3410 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3411 PIPE_CRC_DONE_INTERRUPT_STATUS;
3412
3413 i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3414 for_each_pipe(dev_priv, pipe)
3415 i915_disable_pipestat(dev_priv, pipe, pipestat_mask);
3416
3417 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3418 PIPE_FIFO_UNDERRUN_STATUS;
3419
3420 for_each_pipe(dev_priv, pipe)
3421 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3422 POSTING_READ(PIPESTAT(PIPE_A));
3423 }
3424
3425 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3426 {
3427 assert_spin_locked(&dev_priv->irq_lock);
3428
3429 if (dev_priv->display_irqs_enabled)
3430 return;
3431
3432 dev_priv->display_irqs_enabled = true;
3433
3434 if (intel_irqs_enabled(dev_priv))
3435 valleyview_display_irqs_install(dev_priv);
3436 }
3437
3438 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3439 {
3440 assert_spin_locked(&dev_priv->irq_lock);
3441
3442 if (!dev_priv->display_irqs_enabled)
3443 return;
3444
3445 dev_priv->display_irqs_enabled = false;
3446
3447 if (intel_irqs_enabled(dev_priv))
3448 valleyview_display_irqs_uninstall(dev_priv);
3449 }
3450
3451 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3452 {
3453 dev_priv->irq_mask = ~0;
3454
3455 I915_WRITE(PORT_HOTPLUG_EN, 0);
3456 POSTING_READ(PORT_HOTPLUG_EN);
3457
3458 I915_WRITE(VLV_IIR, 0xffffffff);
3459 I915_WRITE(VLV_IIR, 0xffffffff);
3460 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3461 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3462 POSTING_READ(VLV_IMR);
3463
3464 /* Interrupt setup is already guaranteed to be single-threaded, this is
3465 * just to make the assert_spin_locked check happy. */
3466 spin_lock_irq(&dev_priv->irq_lock);
3467 if (dev_priv->display_irqs_enabled)
3468 valleyview_display_irqs_install(dev_priv);
3469 spin_unlock_irq(&dev_priv->irq_lock);
3470 }
3471
3472 static int valleyview_irq_postinstall(struct drm_device *dev)
3473 {
3474 struct drm_i915_private *dev_priv = dev->dev_private;
3475
3476 vlv_display_irq_postinstall(dev_priv);
3477
3478 gen5_gt_irq_postinstall(dev);
3479
3480 /* ack & enable invalid PTE error interrupts */
3481 #if 0 /* FIXME: add support to irq handler for checking these bits */
3482 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3483 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3484 #endif
3485
3486 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3487
3488 return 0;
3489 }
3490
3491 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3492 {
3493 /* These are interrupts we'll toggle with the ring mask register */
3494 uint32_t gt_interrupts[] = {
3495 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3496 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3497 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3498 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3499 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3500 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3501 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3502 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3503 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3504 0,
3505 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3506 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3507 };
3508
3509 dev_priv->pm_irq_mask = 0xffffffff;
3510 GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3511 GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3512 GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, dev_priv->pm_rps_events);
3513 GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3514 }
3515
3516 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3517 {
3518 uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3519 uint32_t de_pipe_enables;
3520 int pipe;
3521 u32 aux_en = GEN8_AUX_CHANNEL_A;
3522
3523 if (IS_GEN9(dev_priv)) {
3524 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3525 GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3526 aux_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3527 GEN9_AUX_CHANNEL_D;
3528 } else
3529 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3530 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3531
3532 de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3533 GEN8_PIPE_FIFO_UNDERRUN;
3534
3535 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3536 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3537 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3538
3539 for_each_pipe(dev_priv, pipe)
3540 if (intel_display_power_is_enabled(dev_priv,
3541 POWER_DOMAIN_PIPE(pipe)))
3542 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3543 dev_priv->de_irq_mask[pipe],
3544 de_pipe_enables);
3545
3546 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~aux_en, aux_en);
3547 }
3548
3549 static int gen8_irq_postinstall(struct drm_device *dev)
3550 {
3551 struct drm_i915_private *dev_priv = dev->dev_private;
3552
3553 ibx_irq_pre_postinstall(dev);
3554
3555 gen8_gt_irq_postinstall(dev_priv);
3556 gen8_de_irq_postinstall(dev_priv);
3557
3558 ibx_irq_postinstall(dev);
3559
3560 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3561 POSTING_READ(GEN8_MASTER_IRQ);
3562
3563 return 0;
3564 }
3565
3566 static int cherryview_irq_postinstall(struct drm_device *dev)
3567 {
3568 struct drm_i915_private *dev_priv = dev->dev_private;
3569
3570 vlv_display_irq_postinstall(dev_priv);
3571
3572 gen8_gt_irq_postinstall(dev_priv);
3573
3574 I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
3575 POSTING_READ(GEN8_MASTER_IRQ);
3576
3577 return 0;
3578 }
3579
3580 static void gen8_irq_uninstall(struct drm_device *dev)
3581 {
3582 struct drm_i915_private *dev_priv = dev->dev_private;
3583
3584 if (!dev_priv)
3585 return;
3586
3587 gen8_irq_reset(dev);
3588 }
3589
3590 static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv)
3591 {
3592 /* Interrupt setup is already guaranteed to be single-threaded, this is
3593 * just to make the assert_spin_locked check happy. */
3594 spin_lock_irq(&dev_priv->irq_lock);
3595 if (dev_priv->display_irqs_enabled)
3596 valleyview_display_irqs_uninstall(dev_priv);
3597 spin_unlock_irq(&dev_priv->irq_lock);
3598
3599 vlv_display_irq_reset(dev_priv);
3600
3601 dev_priv->irq_mask = 0;
3602 }
3603
3604 static void valleyview_irq_uninstall(struct drm_device *dev)
3605 {
3606 struct drm_i915_private *dev_priv = dev->dev_private;
3607
3608 if (!dev_priv)
3609 return;
3610
3611 I915_WRITE(VLV_MASTER_IER, 0);
3612
3613 gen5_gt_irq_reset(dev);
3614
3615 I915_WRITE(HWSTAM, 0xffffffff);
3616
3617 vlv_display_irq_uninstall(dev_priv);
3618 }
3619
3620 static void cherryview_irq_uninstall(struct drm_device *dev)
3621 {
3622 struct drm_i915_private *dev_priv = dev->dev_private;
3623
3624 if (!dev_priv)
3625 return;
3626
3627 I915_WRITE(GEN8_MASTER_IRQ, 0);
3628 POSTING_READ(GEN8_MASTER_IRQ);
3629
3630 gen8_gt_irq_reset(dev_priv);
3631
3632 GEN5_IRQ_RESET(GEN8_PCU_);
3633
3634 vlv_display_irq_uninstall(dev_priv);
3635 }
3636
3637 static void ironlake_irq_uninstall(struct drm_device *dev)
3638 {
3639 struct drm_i915_private *dev_priv = dev->dev_private;
3640
3641 if (!dev_priv)
3642 return;
3643
3644 ironlake_irq_reset(dev);
3645 }
3646
3647 static void i8xx_irq_preinstall(struct drm_device * dev)
3648 {
3649 struct drm_i915_private *dev_priv = dev->dev_private;
3650 int pipe;
3651
3652 for_each_pipe(dev_priv, pipe)
3653 I915_WRITE(PIPESTAT(pipe), 0);
3654 I915_WRITE16(IMR, 0xffff);
3655 I915_WRITE16(IER, 0x0);
3656 POSTING_READ16(IER);
3657 }
3658
3659 static int i8xx_irq_postinstall(struct drm_device *dev)
3660 {
3661 struct drm_i915_private *dev_priv = dev->dev_private;
3662
3663 I915_WRITE16(EMR,
3664 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3665
3666 /* Unmask the interrupts that we always want on. */
3667 dev_priv->irq_mask =
3668 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3669 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3670 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3671 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3672 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3673 I915_WRITE16(IMR, dev_priv->irq_mask);
3674
3675 I915_WRITE16(IER,
3676 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3677 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3678 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3679 I915_USER_INTERRUPT);
3680 POSTING_READ16(IER);
3681
3682 /* Interrupt setup is already guaranteed to be single-threaded, this is
3683 * just to make the assert_spin_locked check happy. */
3684 spin_lock_irq(&dev_priv->irq_lock);
3685 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3686 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3687 spin_unlock_irq(&dev_priv->irq_lock);
3688
3689 return 0;
3690 }
3691
3692 /*
3693 * Returns true when a page flip has completed.
3694 */
3695 static bool i8xx_handle_vblank(struct drm_device *dev,
3696 int plane, int pipe, u32 iir)
3697 {
3698 struct drm_i915_private *dev_priv = dev->dev_private;
3699 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3700
3701 if (!intel_pipe_handle_vblank(dev, pipe))
3702 return false;
3703
3704 if ((iir & flip_pending) == 0)
3705 goto check_page_flip;
3706
3707 intel_prepare_page_flip(dev, plane);
3708
3709 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3710 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3711 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3712 * the flip is completed (no longer pending). Since this doesn't raise
3713 * an interrupt per se, we watch for the change at vblank.
3714 */
3715 if (I915_READ16(ISR) & flip_pending)
3716 goto check_page_flip;
3717
3718 intel_finish_page_flip(dev, pipe);
3719 return true;
3720
3721 check_page_flip:
3722 intel_check_page_flip(dev, pipe);
3723 return false;
3724 }
3725
3726 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3727 {
3728 struct drm_device *dev = arg;
3729 struct drm_i915_private *dev_priv = dev->dev_private;
3730 u16 iir, new_iir;
3731 u32 pipe_stats[2];
3732 int pipe;
3733 u16 flip_mask =
3734 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3735 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3736
3737 iir = I915_READ16(IIR);
3738 if (iir == 0)
3739 return IRQ_NONE;
3740
3741 while (iir & ~flip_mask) {
3742 /* Can't rely on pipestat interrupt bit in iir as it might
3743 * have been cleared after the pipestat interrupt was received.
3744 * It doesn't set the bit in iir again, but it still produces
3745 * interrupts (for non-MSI).
3746 */
3747 spin_lock(&dev_priv->irq_lock);
3748 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3749 i915_handle_error(dev, false,
3750 "Command parser error, iir 0x%08x",
3751 iir);
3752
3753 for_each_pipe(dev_priv, pipe) {
3754 int reg = PIPESTAT(pipe);
3755 pipe_stats[pipe] = I915_READ(reg);
3756
3757 /*
3758 * Clear the PIPE*STAT regs before the IIR
3759 */
3760 if (pipe_stats[pipe] & 0x8000ffff)
3761 I915_WRITE(reg, pipe_stats[pipe]);
3762 }
3763 spin_unlock(&dev_priv->irq_lock);
3764
3765 I915_WRITE16(IIR, iir & ~flip_mask);
3766 new_iir = I915_READ16(IIR); /* Flush posted writes */
3767
3768 if (iir & I915_USER_INTERRUPT)
3769 notify_ring(dev, &dev_priv->ring[RCS]);
3770
3771 for_each_pipe(dev_priv, pipe) {
3772 int plane = pipe;
3773 if (HAS_FBC(dev))
3774 plane = !plane;
3775
3776 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3777 i8xx_handle_vblank(dev, plane, pipe, iir))
3778 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3779
3780 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3781 i9xx_pipe_crc_irq_handler(dev, pipe);
3782
3783 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3784 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3785 pipe);
3786 }
3787
3788 iir = new_iir;
3789 }
3790
3791 return IRQ_HANDLED;
3792 }
3793
3794 static void i8xx_irq_uninstall(struct drm_device * dev)
3795 {
3796 struct drm_i915_private *dev_priv = dev->dev_private;
3797 int pipe;
3798
3799 for_each_pipe(dev_priv, pipe) {
3800 /* Clear enable bits; then clear status bits */
3801 I915_WRITE(PIPESTAT(pipe), 0);
3802 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3803 }
3804 I915_WRITE16(IMR, 0xffff);
3805 I915_WRITE16(IER, 0x0);
3806 I915_WRITE16(IIR, I915_READ16(IIR));
3807 }
3808
3809 static void i915_irq_preinstall(struct drm_device * dev)
3810 {
3811 struct drm_i915_private *dev_priv = dev->dev_private;
3812 int pipe;
3813
3814 if (I915_HAS_HOTPLUG(dev)) {
3815 I915_WRITE(PORT_HOTPLUG_EN, 0);
3816 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3817 }
3818
3819 I915_WRITE16(HWSTAM, 0xeffe);
3820 for_each_pipe(dev_priv, pipe)
3821 I915_WRITE(PIPESTAT(pipe), 0);
3822 I915_WRITE(IMR, 0xffffffff);
3823 I915_WRITE(IER, 0x0);
3824 POSTING_READ(IER);
3825 }
3826
3827 static int i915_irq_postinstall(struct drm_device *dev)
3828 {
3829 struct drm_i915_private *dev_priv = dev->dev_private;
3830 u32 enable_mask;
3831
3832 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3833
3834 /* Unmask the interrupts that we always want on. */
3835 dev_priv->irq_mask =
3836 ~(I915_ASLE_INTERRUPT |
3837 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3838 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3839 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3840 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3841 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3842
3843 enable_mask =
3844 I915_ASLE_INTERRUPT |
3845 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3846 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3847 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3848 I915_USER_INTERRUPT;
3849
3850 if (I915_HAS_HOTPLUG(dev)) {
3851 I915_WRITE(PORT_HOTPLUG_EN, 0);
3852 POSTING_READ(PORT_HOTPLUG_EN);
3853
3854 /* Enable in IER... */
3855 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3856 /* and unmask in IMR */
3857 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3858 }
3859
3860 I915_WRITE(IMR, dev_priv->irq_mask);
3861 I915_WRITE(IER, enable_mask);
3862 POSTING_READ(IER);
3863
3864 i915_enable_asle_pipestat(dev);
3865
3866 /* Interrupt setup is already guaranteed to be single-threaded, this is
3867 * just to make the assert_spin_locked check happy. */
3868 spin_lock_irq(&dev_priv->irq_lock);
3869 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3870 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3871 spin_unlock_irq(&dev_priv->irq_lock);
3872
3873 return 0;
3874 }
3875
3876 /*
3877 * Returns true when a page flip has completed.
3878 */
3879 static bool i915_handle_vblank(struct drm_device *dev,
3880 int plane, int pipe, u32 iir)
3881 {
3882 struct drm_i915_private *dev_priv = dev->dev_private;
3883 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3884
3885 if (!intel_pipe_handle_vblank(dev, pipe))
3886 return false;
3887
3888 if ((iir & flip_pending) == 0)
3889 goto check_page_flip;
3890
3891 intel_prepare_page_flip(dev, plane);
3892
3893 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3894 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3895 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3896 * the flip is completed (no longer pending). Since this doesn't raise
3897 * an interrupt per se, we watch for the change at vblank.
3898 */
3899 if (I915_READ(ISR) & flip_pending)
3900 goto check_page_flip;
3901
3902 intel_finish_page_flip(dev, pipe);
3903 return true;
3904
3905 check_page_flip:
3906 intel_check_page_flip(dev, pipe);
3907 return false;
3908 }
3909
3910 static irqreturn_t i915_irq_handler(int irq, void *arg)
3911 {
3912 struct drm_device *dev = arg;
3913 struct drm_i915_private *dev_priv = dev->dev_private;
3914 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3915 u32 flip_mask =
3916 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3917 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3918 int pipe, ret = IRQ_NONE;
3919
3920 iir = I915_READ(IIR);
3921 do {
3922 bool irq_received = (iir & ~flip_mask) != 0;
3923 bool blc_event = false;
3924
3925 /* Can't rely on pipestat interrupt bit in iir as it might
3926 * have been cleared after the pipestat interrupt was received.
3927 * It doesn't set the bit in iir again, but it still produces
3928 * interrupts (for non-MSI).
3929 */
3930 spin_lock(&dev_priv->irq_lock);
3931 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3932 i915_handle_error(dev, false,
3933 "Command parser error, iir 0x%08x",
3934 iir);
3935
3936 for_each_pipe(dev_priv, pipe) {
3937 int reg = PIPESTAT(pipe);
3938 pipe_stats[pipe] = I915_READ(reg);
3939
3940 /* Clear the PIPE*STAT regs before the IIR */
3941 if (pipe_stats[pipe] & 0x8000ffff) {
3942 I915_WRITE(reg, pipe_stats[pipe]);
3943 irq_received = true;
3944 }
3945 }
3946 spin_unlock(&dev_priv->irq_lock);
3947
3948 if (!irq_received)
3949 break;
3950
3951 /* Consume port. Then clear IIR or we'll miss events */
3952 if (I915_HAS_HOTPLUG(dev) &&
3953 iir & I915_DISPLAY_PORT_INTERRUPT)
3954 i9xx_hpd_irq_handler(dev);
3955
3956 I915_WRITE(IIR, iir & ~flip_mask);
3957 new_iir = I915_READ(IIR); /* Flush posted writes */
3958
3959 if (iir & I915_USER_INTERRUPT)
3960 notify_ring(dev, &dev_priv->ring[RCS]);
3961
3962 for_each_pipe(dev_priv, pipe) {
3963 int plane = pipe;
3964 if (HAS_FBC(dev))
3965 plane = !plane;
3966
3967 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3968 i915_handle_vblank(dev, plane, pipe, iir))
3969 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3970
3971 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3972 blc_event = true;
3973
3974 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3975 i9xx_pipe_crc_irq_handler(dev, pipe);
3976
3977 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3978 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3979 pipe);
3980 }
3981
3982 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3983 intel_opregion_asle_intr(dev);
3984
3985 /* With MSI, interrupts are only generated when iir
3986 * transitions from zero to nonzero. If another bit got
3987 * set while we were handling the existing iir bits, then
3988 * we would never get another interrupt.
3989 *
3990 * This is fine on non-MSI as well, as if we hit this path
3991 * we avoid exiting the interrupt handler only to generate
3992 * another one.
3993 *
3994 * Note that for MSI this could cause a stray interrupt report
3995 * if an interrupt landed in the time between writing IIR and
3996 * the posting read. This should be rare enough to never
3997 * trigger the 99% of 100,000 interrupts test for disabling
3998 * stray interrupts.
3999 */
4000 ret = IRQ_HANDLED;
4001 iir = new_iir;
4002 } while (iir & ~flip_mask);
4003
4004 return ret;
4005 }
4006
4007 static void i915_irq_uninstall(struct drm_device * dev)
4008 {
4009 struct drm_i915_private *dev_priv = dev->dev_private;
4010 int pipe;
4011
4012 if (I915_HAS_HOTPLUG(dev)) {
4013 I915_WRITE(PORT_HOTPLUG_EN, 0);
4014 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4015 }
4016
4017 I915_WRITE16(HWSTAM, 0xffff);
4018 for_each_pipe(dev_priv, pipe) {
4019 /* Clear enable bits; then clear status bits */
4020 I915_WRITE(PIPESTAT(pipe), 0);
4021 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4022 }
4023 I915_WRITE(IMR, 0xffffffff);
4024 I915_WRITE(IER, 0x0);
4025
4026 I915_WRITE(IIR, I915_READ(IIR));
4027 }
4028
4029 static void i965_irq_preinstall(struct drm_device * dev)
4030 {
4031 struct drm_i915_private *dev_priv = dev->dev_private;
4032 int pipe;
4033
4034 I915_WRITE(PORT_HOTPLUG_EN, 0);
4035 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4036
4037 I915_WRITE(HWSTAM, 0xeffe);
4038 for_each_pipe(dev_priv, pipe)
4039 I915_WRITE(PIPESTAT(pipe), 0);
4040 I915_WRITE(IMR, 0xffffffff);
4041 I915_WRITE(IER, 0x0);
4042 POSTING_READ(IER);
4043 }
4044
4045 static int i965_irq_postinstall(struct drm_device *dev)
4046 {
4047 struct drm_i915_private *dev_priv = dev->dev_private;
4048 u32 enable_mask;
4049 u32 error_mask;
4050
4051 /* Unmask the interrupts that we always want on. */
4052 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4053 I915_DISPLAY_PORT_INTERRUPT |
4054 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4055 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4056 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4057 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4058 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4059
4060 enable_mask = ~dev_priv->irq_mask;
4061 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4062 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4063 enable_mask |= I915_USER_INTERRUPT;
4064
4065 if (IS_G4X(dev))
4066 enable_mask |= I915_BSD_USER_INTERRUPT;
4067
4068 /* Interrupt setup is already guaranteed to be single-threaded, this is
4069 * just to make the assert_spin_locked check happy. */
4070 spin_lock_irq(&dev_priv->irq_lock);
4071 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4072 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4073 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4074 spin_unlock_irq(&dev_priv->irq_lock);
4075
4076 /*
4077 * Enable some error detection, note the instruction error mask
4078 * bit is reserved, so we leave it masked.
4079 */
4080 if (IS_G4X(dev)) {
4081 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4082 GM45_ERROR_MEM_PRIV |
4083 GM45_ERROR_CP_PRIV |
4084 I915_ERROR_MEMORY_REFRESH);
4085 } else {
4086 error_mask = ~(I915_ERROR_PAGE_TABLE |
4087 I915_ERROR_MEMORY_REFRESH);
4088 }
4089 I915_WRITE(EMR, error_mask);
4090
4091 I915_WRITE(IMR, dev_priv->irq_mask);
4092 I915_WRITE(IER, enable_mask);
4093 POSTING_READ(IER);
4094
4095 I915_WRITE(PORT_HOTPLUG_EN, 0);
4096 POSTING_READ(PORT_HOTPLUG_EN);
4097
4098 i915_enable_asle_pipestat(dev);
4099
4100 return 0;
4101 }
4102
4103 static void i915_hpd_irq_setup(struct drm_device *dev)
4104 {
4105 struct drm_i915_private *dev_priv = dev->dev_private;
4106 struct intel_encoder *intel_encoder;
4107 u32 hotplug_en;
4108
4109 assert_spin_locked(&dev_priv->irq_lock);
4110
4111 if (I915_HAS_HOTPLUG(dev)) {
4112 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
4113 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
4114 /* Note HDMI and DP share hotplug bits */
4115 /* enable bits are the same for all generations */
4116 for_each_intel_encoder(dev, intel_encoder)
4117 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
4118 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
4119 /* Programming the CRT detection parameters tends
4120 to generate a spurious hotplug event about three
4121 seconds later. So just do it once.
4122 */
4123 if (IS_G4X(dev))
4124 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4125 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
4126 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4127
4128 /* Ignore TV since it's buggy */
4129 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
4130 }
4131 }
4132
4133 static irqreturn_t i965_irq_handler(int irq, void *arg)
4134 {
4135 struct drm_device *dev = arg;
4136 struct drm_i915_private *dev_priv = dev->dev_private;
4137 u32 iir, new_iir;
4138 u32 pipe_stats[I915_MAX_PIPES];
4139 int ret = IRQ_NONE, pipe;
4140 u32 flip_mask =
4141 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4142 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4143
4144 iir = I915_READ(IIR);
4145
4146 for (;;) {
4147 bool irq_received = (iir & ~flip_mask) != 0;
4148 bool blc_event = false;
4149
4150 /* Can't rely on pipestat interrupt bit in iir as it might
4151 * have been cleared after the pipestat interrupt was received.
4152 * It doesn't set the bit in iir again, but it still produces
4153 * interrupts (for non-MSI).
4154 */
4155 spin_lock(&dev_priv->irq_lock);
4156 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4157 i915_handle_error(dev, false,
4158 "Command parser error, iir 0x%08x",
4159 iir);
4160
4161 for_each_pipe(dev_priv, pipe) {
4162 int reg = PIPESTAT(pipe);
4163 pipe_stats[pipe] = I915_READ(reg);
4164
4165 /*
4166 * Clear the PIPE*STAT regs before the IIR
4167 */
4168 if (pipe_stats[pipe] & 0x8000ffff) {
4169 I915_WRITE(reg, pipe_stats[pipe]);
4170 irq_received = true;
4171 }
4172 }
4173 spin_unlock(&dev_priv->irq_lock);
4174
4175 if (!irq_received)
4176 break;
4177
4178 ret = IRQ_HANDLED;
4179
4180 /* Consume port. Then clear IIR or we'll miss events */
4181 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4182 i9xx_hpd_irq_handler(dev);
4183
4184 I915_WRITE(IIR, iir & ~flip_mask);
4185 new_iir = I915_READ(IIR); /* Flush posted writes */
4186
4187 if (iir & I915_USER_INTERRUPT)
4188 notify_ring(dev, &dev_priv->ring[RCS]);
4189 if (iir & I915_BSD_USER_INTERRUPT)
4190 notify_ring(dev, &dev_priv->ring[VCS]);
4191
4192 for_each_pipe(dev_priv, pipe) {
4193 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4194 i915_handle_vblank(dev, pipe, pipe, iir))
4195 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4196
4197 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4198 blc_event = true;
4199
4200 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4201 i9xx_pipe_crc_irq_handler(dev, pipe);
4202
4203 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4204 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4205 }
4206
4207 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4208 intel_opregion_asle_intr(dev);
4209
4210 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4211 gmbus_irq_handler(dev);
4212
4213 /* With MSI, interrupts are only generated when iir
4214 * transitions from zero to nonzero. If another bit got
4215 * set while we were handling the existing iir bits, then
4216 * we would never get another interrupt.
4217 *
4218 * This is fine on non-MSI as well, as if we hit this path
4219 * we avoid exiting the interrupt handler only to generate
4220 * another one.
4221 *
4222 * Note that for MSI this could cause a stray interrupt report
4223 * if an interrupt landed in the time between writing IIR and
4224 * the posting read. This should be rare enough to never
4225 * trigger the 99% of 100,000 interrupts test for disabling
4226 * stray interrupts.
4227 */
4228 iir = new_iir;
4229 }
4230
4231 return ret;
4232 }
4233
4234 static void i965_irq_uninstall(struct drm_device * dev)
4235 {
4236 struct drm_i915_private *dev_priv = dev->dev_private;
4237 int pipe;
4238
4239 if (!dev_priv)
4240 return;
4241
4242 I915_WRITE(PORT_HOTPLUG_EN, 0);
4243 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4244
4245 I915_WRITE(HWSTAM, 0xffffffff);
4246 for_each_pipe(dev_priv, pipe)
4247 I915_WRITE(PIPESTAT(pipe), 0);
4248 I915_WRITE(IMR, 0xffffffff);
4249 I915_WRITE(IER, 0x0);
4250
4251 for_each_pipe(dev_priv, pipe)
4252 I915_WRITE(PIPESTAT(pipe),
4253 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4254 I915_WRITE(IIR, I915_READ(IIR));
4255 }
4256
4257 static void intel_hpd_irq_reenable_work(struct work_struct *work)
4258 {
4259 struct drm_i915_private *dev_priv =
4260 container_of(work, typeof(*dev_priv),
4261 hotplug_reenable_work.work);
4262 struct drm_device *dev = dev_priv->dev;
4263 struct drm_mode_config *mode_config = &dev->mode_config;
4264 int i;
4265
4266 intel_runtime_pm_get(dev_priv);
4267
4268 spin_lock_irq(&dev_priv->irq_lock);
4269 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
4270 struct drm_connector *connector;
4271
4272 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
4273 continue;
4274
4275 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4276
4277 list_for_each_entry(connector, &mode_config->connector_list, head) {
4278 struct intel_connector *intel_connector = to_intel_connector(connector);
4279
4280 if (intel_connector->encoder->hpd_pin == i) {
4281 if (connector->polled != intel_connector->polled)
4282 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
4283 connector->name);
4284 connector->polled = intel_connector->polled;
4285 if (!connector->polled)
4286 connector->polled = DRM_CONNECTOR_POLL_HPD;
4287 }
4288 }
4289 }
4290 if (dev_priv->display.hpd_irq_setup)
4291 dev_priv->display.hpd_irq_setup(dev);
4292 spin_unlock_irq(&dev_priv->irq_lock);
4293
4294 intel_runtime_pm_put(dev_priv);
4295 }
4296
4297 /**
4298 * intel_irq_init - initializes irq support
4299 * @dev_priv: i915 device instance
4300 *
4301 * This function initializes all the irq support including work items, timers
4302 * and all the vtables. It does not setup the interrupt itself though.
4303 */
4304 void intel_irq_init(struct drm_i915_private *dev_priv)
4305 {
4306 struct drm_device *dev = dev_priv->dev;
4307
4308 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
4309 INIT_WORK(&dev_priv->dig_port_work, i915_digport_work_func);
4310 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
4311 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4312 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4313
4314 /* Let's track the enabled rps events */
4315 if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
4316 /* WaGsvRC0ResidencyMethod:vlv */
4317 dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
4318 else
4319 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4320
4321 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
4322 i915_hangcheck_elapsed,
4323 (unsigned long) dev);
4324 INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work,
4325 intel_hpd_irq_reenable_work);
4326
4327 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4328
4329 if (IS_GEN2(dev_priv)) {
4330 dev->max_vblank_count = 0;
4331 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4332 } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4333 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4334 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
4335 } else {
4336 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4337 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4338 }
4339
4340 /*
4341 * Opt out of the vblank disable timer on everything except gen2.
4342 * Gen2 doesn't have a hardware frame counter and so depends on
4343 * vblank interrupts to produce sane vblank seuquence numbers.
4344 */
4345 if (!IS_GEN2(dev_priv))
4346 dev->vblank_disable_immediate = true;
4347
4348 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
4349 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4350 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4351 }
4352
4353 if (IS_CHERRYVIEW(dev_priv)) {
4354 dev->driver->irq_handler = cherryview_irq_handler;
4355 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4356 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4357 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4358 dev->driver->enable_vblank = valleyview_enable_vblank;
4359 dev->driver->disable_vblank = valleyview_disable_vblank;
4360 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4361 } else if (IS_VALLEYVIEW(dev_priv)) {
4362 dev->driver->irq_handler = valleyview_irq_handler;
4363 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4364 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4365 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4366 dev->driver->enable_vblank = valleyview_enable_vblank;
4367 dev->driver->disable_vblank = valleyview_disable_vblank;
4368 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4369 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
4370 dev->driver->irq_handler = gen8_irq_handler;
4371 dev->driver->irq_preinstall = gen8_irq_reset;
4372 dev->driver->irq_postinstall = gen8_irq_postinstall;
4373 dev->driver->irq_uninstall = gen8_irq_uninstall;
4374 dev->driver->enable_vblank = gen8_enable_vblank;
4375 dev->driver->disable_vblank = gen8_disable_vblank;
4376 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4377 } else if (HAS_PCH_SPLIT(dev)) {
4378 dev->driver->irq_handler = ironlake_irq_handler;
4379 dev->driver->irq_preinstall = ironlake_irq_reset;
4380 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4381 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4382 dev->driver->enable_vblank = ironlake_enable_vblank;
4383 dev->driver->disable_vblank = ironlake_disable_vblank;
4384 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4385 } else {
4386 if (INTEL_INFO(dev_priv)->gen == 2) {
4387 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4388 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4389 dev->driver->irq_handler = i8xx_irq_handler;
4390 dev->driver->irq_uninstall = i8xx_irq_uninstall;
4391 } else if (INTEL_INFO(dev_priv)->gen == 3) {
4392 dev->driver->irq_preinstall = i915_irq_preinstall;
4393 dev->driver->irq_postinstall = i915_irq_postinstall;
4394 dev->driver->irq_uninstall = i915_irq_uninstall;
4395 dev->driver->irq_handler = i915_irq_handler;
4396 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4397 } else {
4398 dev->driver->irq_preinstall = i965_irq_preinstall;
4399 dev->driver->irq_postinstall = i965_irq_postinstall;
4400 dev->driver->irq_uninstall = i965_irq_uninstall;
4401 dev->driver->irq_handler = i965_irq_handler;
4402 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4403 }
4404 dev->driver->enable_vblank = i915_enable_vblank;
4405 dev->driver->disable_vblank = i915_disable_vblank;
4406 }
4407 }
4408
4409 /**
4410 * intel_hpd_init - initializes and enables hpd support
4411 * @dev_priv: i915 device instance
4412 *
4413 * This function enables the hotplug support. It requires that interrupts have
4414 * already been enabled with intel_irq_init_hw(). From this point on hotplug and
4415 * poll request can run concurrently to other code, so locking rules must be
4416 * obeyed.
4417 *
4418 * This is a separate step from interrupt enabling to simplify the locking rules
4419 * in the driver load and resume code.
4420 */
4421 void intel_hpd_init(struct drm_i915_private *dev_priv)
4422 {
4423 struct drm_device *dev = dev_priv->dev;
4424 struct drm_mode_config *mode_config = &dev->mode_config;
4425 struct drm_connector *connector;
4426 int i;
4427
4428 for (i = 1; i < HPD_NUM_PINS; i++) {
4429 dev_priv->hpd_stats[i].hpd_cnt = 0;
4430 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4431 }
4432 list_for_each_entry(connector, &mode_config->connector_list, head) {
4433 struct intel_connector *intel_connector = to_intel_connector(connector);
4434 connector->polled = intel_connector->polled;
4435 if (connector->encoder && !connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
4436 connector->polled = DRM_CONNECTOR_POLL_HPD;
4437 if (intel_connector->mst_port)
4438 connector->polled = DRM_CONNECTOR_POLL_HPD;
4439 }
4440
4441 /* Interrupt setup is already guaranteed to be single-threaded, this is
4442 * just to make the assert_spin_locked checks happy. */
4443 spin_lock_irq(&dev_priv->irq_lock);
4444 if (dev_priv->display.hpd_irq_setup)
4445 dev_priv->display.hpd_irq_setup(dev);
4446 spin_unlock_irq(&dev_priv->irq_lock);
4447 }
4448
4449 /**
4450 * intel_irq_install - enables the hardware interrupt
4451 * @dev_priv: i915 device instance
4452 *
4453 * This function enables the hardware interrupt handling, but leaves the hotplug
4454 * handling still disabled. It is called after intel_irq_init().
4455 *
4456 * In the driver load and resume code we need working interrupts in a few places
4457 * but don't want to deal with the hassle of concurrent probe and hotplug
4458 * workers. Hence the split into this two-stage approach.
4459 */
4460 int intel_irq_install(struct drm_i915_private *dev_priv)
4461 {
4462 /*
4463 * We enable some interrupt sources in our postinstall hooks, so mark
4464 * interrupts as enabled _before_ actually enabling them to avoid
4465 * special cases in our ordering checks.
4466 */
4467 dev_priv->pm.irqs_enabled = true;
4468
4469 return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
4470 }
4471
4472 /**
4473 * intel_irq_uninstall - finilizes all irq handling
4474 * @dev_priv: i915 device instance
4475 *
4476 * This stops interrupt and hotplug handling and unregisters and frees all
4477 * resources acquired in the init functions.
4478 */
4479 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4480 {
4481 drm_irq_uninstall(dev_priv->dev);
4482 intel_hpd_cancel_work(dev_priv);
4483 dev_priv->pm.irqs_enabled = false;
4484 }
4485
4486 /**
4487 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4488 * @dev_priv: i915 device instance
4489 *
4490 * This function is used to disable interrupts at runtime, both in the runtime
4491 * pm and the system suspend/resume code.
4492 */
4493 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4494 {
4495 dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
4496 dev_priv->pm.irqs_enabled = false;
4497 }
4498
4499 /**
4500 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4501 * @dev_priv: i915 device instance
4502 *
4503 * This function is used to enable interrupts at runtime, both in the runtime
4504 * pm and the system suspend/resume code.
4505 */
4506 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4507 {
4508 dev_priv->pm.irqs_enabled = true;
4509 dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
4510 dev_priv->dev->driver->irq_postinstall(dev_priv->dev);
4511 }
Linux kernel - Deliverables
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