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drm/i915: move gen6 rps handling to workqueue
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #include <linux/sysrq.h>
30 #include <linux/slab.h>
31 #include "drmP.h"
32 #include "drm.h"
33 #include "i915_drm.h"
34 #include "i915_drv.h"
35 #include "i915_trace.h"
36 #include "intel_drv.h"
37
38 #define MAX_NOPID ((u32)~0)
39
40 /**
41 * Interrupts that are always left unmasked.
42 *
43 * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
44 * we leave them always unmasked in IMR and then control enabling them through
45 * PIPESTAT alone.
46 */
47 #define I915_INTERRUPT_ENABLE_FIX \
48 (I915_ASLE_INTERRUPT | \
49 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
50 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
51 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \
52 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \
53 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
54
55 /** Interrupts that we mask and unmask at runtime. */
56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
57
58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
59 PIPE_VBLANK_INTERRUPT_STATUS)
60
61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
62 PIPE_VBLANK_INTERRUPT_ENABLE)
63
64 #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
65 DRM_I915_VBLANK_PIPE_B)
66
67 /* For display hotplug interrupt */
68 static void
69 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
70 {
71 if ((dev_priv->irq_mask & mask) != 0) {
72 dev_priv->irq_mask &= ~mask;
73 I915_WRITE(DEIMR, dev_priv->irq_mask);
74 POSTING_READ(DEIMR);
75 }
76 }
77
78 static inline void
79 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
80 {
81 if ((dev_priv->irq_mask & mask) != mask) {
82 dev_priv->irq_mask |= mask;
83 I915_WRITE(DEIMR, dev_priv->irq_mask);
84 POSTING_READ(DEIMR);
85 }
86 }
87
88 void
89 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
90 {
91 if ((dev_priv->pipestat[pipe] & mask) != mask) {
92 u32 reg = PIPESTAT(pipe);
93
94 dev_priv->pipestat[pipe] |= mask;
95 /* Enable the interrupt, clear any pending status */
96 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
97 POSTING_READ(reg);
98 }
99 }
100
101 void
102 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
103 {
104 if ((dev_priv->pipestat[pipe] & mask) != 0) {
105 u32 reg = PIPESTAT(pipe);
106
107 dev_priv->pipestat[pipe] &= ~mask;
108 I915_WRITE(reg, dev_priv->pipestat[pipe]);
109 POSTING_READ(reg);
110 }
111 }
112
113 /**
114 * intel_enable_asle - enable ASLE interrupt for OpRegion
115 */
116 void intel_enable_asle(struct drm_device *dev)
117 {
118 drm_i915_private_t *dev_priv = dev->dev_private;
119 unsigned long irqflags;
120
121 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
122
123 if (HAS_PCH_SPLIT(dev))
124 ironlake_enable_display_irq(dev_priv, DE_GSE);
125 else {
126 i915_enable_pipestat(dev_priv, 1,
127 PIPE_LEGACY_BLC_EVENT_ENABLE);
128 if (INTEL_INFO(dev)->gen >= 4)
129 i915_enable_pipestat(dev_priv, 0,
130 PIPE_LEGACY_BLC_EVENT_ENABLE);
131 }
132
133 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
134 }
135
136 /**
137 * i915_pipe_enabled - check if a pipe is enabled
138 * @dev: DRM device
139 * @pipe: pipe to check
140 *
141 * Reading certain registers when the pipe is disabled can hang the chip.
142 * Use this routine to make sure the PLL is running and the pipe is active
143 * before reading such registers if unsure.
144 */
145 static int
146 i915_pipe_enabled(struct drm_device *dev, int pipe)
147 {
148 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
149 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
150 }
151
152 /* Called from drm generic code, passed a 'crtc', which
153 * we use as a pipe index
154 */
155 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
156 {
157 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
158 unsigned long high_frame;
159 unsigned long low_frame;
160 u32 high1, high2, low;
161
162 if (!i915_pipe_enabled(dev, pipe)) {
163 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
164 "pipe %c\n", pipe_name(pipe));
165 return 0;
166 }
167
168 high_frame = PIPEFRAME(pipe);
169 low_frame = PIPEFRAMEPIXEL(pipe);
170
171 /*
172 * High & low register fields aren't synchronized, so make sure
173 * we get a low value that's stable across two reads of the high
174 * register.
175 */
176 do {
177 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
178 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
179 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
180 } while (high1 != high2);
181
182 high1 >>= PIPE_FRAME_HIGH_SHIFT;
183 low >>= PIPE_FRAME_LOW_SHIFT;
184 return (high1 << 8) | low;
185 }
186
187 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
188 {
189 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
190 int reg = PIPE_FRMCOUNT_GM45(pipe);
191
192 if (!i915_pipe_enabled(dev, pipe)) {
193 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
194 "pipe %c\n", pipe_name(pipe));
195 return 0;
196 }
197
198 return I915_READ(reg);
199 }
200
201 int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
202 int *vpos, int *hpos)
203 {
204 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
205 u32 vbl = 0, position = 0;
206 int vbl_start, vbl_end, htotal, vtotal;
207 bool in_vbl = true;
208 int ret = 0;
209
210 if (!i915_pipe_enabled(dev, pipe)) {
211 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
212 "pipe %c\n", pipe_name(pipe));
213 return 0;
214 }
215
216 /* Get vtotal. */
217 vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
218
219 if (INTEL_INFO(dev)->gen >= 4) {
220 /* No obvious pixelcount register. Only query vertical
221 * scanout position from Display scan line register.
222 */
223 position = I915_READ(PIPEDSL(pipe));
224
225 /* Decode into vertical scanout position. Don't have
226 * horizontal scanout position.
227 */
228 *vpos = position & 0x1fff;
229 *hpos = 0;
230 } else {
231 /* Have access to pixelcount since start of frame.
232 * We can split this into vertical and horizontal
233 * scanout position.
234 */
235 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
236
237 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
238 *vpos = position / htotal;
239 *hpos = position - (*vpos * htotal);
240 }
241
242 /* Query vblank area. */
243 vbl = I915_READ(VBLANK(pipe));
244
245 /* Test position against vblank region. */
246 vbl_start = vbl & 0x1fff;
247 vbl_end = (vbl >> 16) & 0x1fff;
248
249 if ((*vpos < vbl_start) || (*vpos > vbl_end))
250 in_vbl = false;
251
252 /* Inside "upper part" of vblank area? Apply corrective offset: */
253 if (in_vbl && (*vpos >= vbl_start))
254 *vpos = *vpos - vtotal;
255
256 /* Readouts valid? */
257 if (vbl > 0)
258 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
259
260 /* In vblank? */
261 if (in_vbl)
262 ret |= DRM_SCANOUTPOS_INVBL;
263
264 return ret;
265 }
266
267 int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
268 int *max_error,
269 struct timeval *vblank_time,
270 unsigned flags)
271 {
272 struct drm_i915_private *dev_priv = dev->dev_private;
273 struct drm_crtc *crtc;
274
275 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
276 DRM_ERROR("Invalid crtc %d\n", pipe);
277 return -EINVAL;
278 }
279
280 /* Get drm_crtc to timestamp: */
281 crtc = intel_get_crtc_for_pipe(dev, pipe);
282 if (crtc == NULL) {
283 DRM_ERROR("Invalid crtc %d\n", pipe);
284 return -EINVAL;
285 }
286
287 if (!crtc->enabled) {
288 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
289 return -EBUSY;
290 }
291
292 /* Helper routine in DRM core does all the work: */
293 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
294 vblank_time, flags,
295 crtc);
296 }
297
298 /*
299 * Handle hotplug events outside the interrupt handler proper.
300 */
301 static void i915_hotplug_work_func(struct work_struct *work)
302 {
303 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
304 hotplug_work);
305 struct drm_device *dev = dev_priv->dev;
306 struct drm_mode_config *mode_config = &dev->mode_config;
307 struct intel_encoder *encoder;
308
309 DRM_DEBUG_KMS("running encoder hotplug functions\n");
310
311 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
312 if (encoder->hot_plug)
313 encoder->hot_plug(encoder);
314
315 /* Just fire off a uevent and let userspace tell us what to do */
316 drm_helper_hpd_irq_event(dev);
317 }
318
319 static void i915_handle_rps_change(struct drm_device *dev)
320 {
321 drm_i915_private_t *dev_priv = dev->dev_private;
322 u32 busy_up, busy_down, max_avg, min_avg;
323 u8 new_delay = dev_priv->cur_delay;
324
325 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
326 busy_up = I915_READ(RCPREVBSYTUPAVG);
327 busy_down = I915_READ(RCPREVBSYTDNAVG);
328 max_avg = I915_READ(RCBMAXAVG);
329 min_avg = I915_READ(RCBMINAVG);
330
331 /* Handle RCS change request from hw */
332 if (busy_up > max_avg) {
333 if (dev_priv->cur_delay != dev_priv->max_delay)
334 new_delay = dev_priv->cur_delay - 1;
335 if (new_delay < dev_priv->max_delay)
336 new_delay = dev_priv->max_delay;
337 } else if (busy_down < min_avg) {
338 if (dev_priv->cur_delay != dev_priv->min_delay)
339 new_delay = dev_priv->cur_delay + 1;
340 if (new_delay > dev_priv->min_delay)
341 new_delay = dev_priv->min_delay;
342 }
343
344 if (ironlake_set_drps(dev, new_delay))
345 dev_priv->cur_delay = new_delay;
346
347 return;
348 }
349
350 static void notify_ring(struct drm_device *dev,
351 struct intel_ring_buffer *ring)
352 {
353 struct drm_i915_private *dev_priv = dev->dev_private;
354 u32 seqno;
355
356 if (ring->obj == NULL)
357 return;
358
359 seqno = ring->get_seqno(ring);
360 trace_i915_gem_request_complete(ring, seqno);
361
362 ring->irq_seqno = seqno;
363 wake_up_all(&ring->irq_queue);
364
365 dev_priv->hangcheck_count = 0;
366 mod_timer(&dev_priv->hangcheck_timer,
367 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
368 }
369
370 static void gen6_pm_rps_work(struct work_struct *work)
371 {
372 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
373 rps_work);
374 u8 new_delay = dev_priv->cur_delay;
375 u32 pm_iir, pm_imr;
376
377 spin_lock_irq(&dev_priv->rps_lock);
378 pm_iir = dev_priv->pm_iir;
379 dev_priv->pm_iir = 0;
380 pm_imr = I915_READ(GEN6_PMIMR);
381 spin_unlock_irq(&dev_priv->rps_lock);
382
383 if (!pm_iir)
384 return;
385
386 mutex_lock(&dev_priv->dev->struct_mutex);
387 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
388 if (dev_priv->cur_delay != dev_priv->max_delay)
389 new_delay = dev_priv->cur_delay + 1;
390 if (new_delay > dev_priv->max_delay)
391 new_delay = dev_priv->max_delay;
392 } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
393 gen6_gt_force_wake_get(dev_priv);
394 if (dev_priv->cur_delay != dev_priv->min_delay)
395 new_delay = dev_priv->cur_delay - 1;
396 if (new_delay < dev_priv->min_delay) {
397 new_delay = dev_priv->min_delay;
398 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
399 I915_READ(GEN6_RP_INTERRUPT_LIMITS) |
400 ((new_delay << 16) & 0x3f0000));
401 } else {
402 /* Make sure we continue to get down interrupts
403 * until we hit the minimum frequency */
404 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
405 I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
406 }
407 gen6_gt_force_wake_put(dev_priv);
408 }
409
410 gen6_set_rps(dev_priv->dev, new_delay);
411 dev_priv->cur_delay = new_delay;
412
413 /*
414 * rps_lock not held here because clearing is non-destructive. There is
415 * an *extremely* unlikely race with gen6_rps_enable() that is prevented
416 * by holding struct_mutex for the duration of the write.
417 */
418 I915_WRITE(GEN6_PMIMR, pm_imr & ~pm_iir);
419 mutex_unlock(&dev_priv->dev->struct_mutex);
420 }
421
422 static void pch_irq_handler(struct drm_device *dev)
423 {
424 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
425 u32 pch_iir;
426 int pipe;
427
428 pch_iir = I915_READ(SDEIIR);
429
430 if (pch_iir & SDE_AUDIO_POWER_MASK)
431 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
432 (pch_iir & SDE_AUDIO_POWER_MASK) >>
433 SDE_AUDIO_POWER_SHIFT);
434
435 if (pch_iir & SDE_GMBUS)
436 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
437
438 if (pch_iir & SDE_AUDIO_HDCP_MASK)
439 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
440
441 if (pch_iir & SDE_AUDIO_TRANS_MASK)
442 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
443
444 if (pch_iir & SDE_POISON)
445 DRM_ERROR("PCH poison interrupt\n");
446
447 if (pch_iir & SDE_FDI_MASK)
448 for_each_pipe(pipe)
449 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
450 pipe_name(pipe),
451 I915_READ(FDI_RX_IIR(pipe)));
452
453 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
454 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
455
456 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
457 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
458
459 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
460 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
461 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
462 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
463 }
464
465 static irqreturn_t ironlake_irq_handler(struct drm_device *dev)
466 {
467 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
468 int ret = IRQ_NONE;
469 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
470 u32 hotplug_mask;
471 struct drm_i915_master_private *master_priv;
472 u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
473
474 if (IS_GEN6(dev))
475 bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
476
477 /* disable master interrupt before clearing iir */
478 de_ier = I915_READ(DEIER);
479 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
480 POSTING_READ(DEIER);
481
482 de_iir = I915_READ(DEIIR);
483 gt_iir = I915_READ(GTIIR);
484 pch_iir = I915_READ(SDEIIR);
485 pm_iir = I915_READ(GEN6_PMIIR);
486
487 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
488 (!IS_GEN6(dev) || pm_iir == 0))
489 goto done;
490
491 if (HAS_PCH_CPT(dev))
492 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
493 else
494 hotplug_mask = SDE_HOTPLUG_MASK;
495
496 ret = IRQ_HANDLED;
497
498 if (dev->primary->master) {
499 master_priv = dev->primary->master->driver_priv;
500 if (master_priv->sarea_priv)
501 master_priv->sarea_priv->last_dispatch =
502 READ_BREADCRUMB(dev_priv);
503 }
504
505 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
506 notify_ring(dev, &dev_priv->ring[RCS]);
507 if (gt_iir & bsd_usr_interrupt)
508 notify_ring(dev, &dev_priv->ring[VCS]);
509 if (gt_iir & GT_BLT_USER_INTERRUPT)
510 notify_ring(dev, &dev_priv->ring[BCS]);
511
512 if (de_iir & DE_GSE)
513 intel_opregion_gse_intr(dev);
514
515 if (de_iir & DE_PLANEA_FLIP_DONE) {
516 intel_prepare_page_flip(dev, 0);
517 intel_finish_page_flip_plane(dev, 0);
518 }
519
520 if (de_iir & DE_PLANEB_FLIP_DONE) {
521 intel_prepare_page_flip(dev, 1);
522 intel_finish_page_flip_plane(dev, 1);
523 }
524
525 if (de_iir & DE_PIPEA_VBLANK)
526 drm_handle_vblank(dev, 0);
527
528 if (de_iir & DE_PIPEB_VBLANK)
529 drm_handle_vblank(dev, 1);
530
531 /* check event from PCH */
532 if (de_iir & DE_PCH_EVENT) {
533 if (pch_iir & hotplug_mask)
534 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
535 pch_irq_handler(dev);
536 }
537
538 if (de_iir & DE_PCU_EVENT) {
539 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
540 i915_handle_rps_change(dev);
541 }
542
543 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS) {
544 /*
545 * IIR bits should never already be set because IMR should
546 * prevent an interrupt from being shown in IIR. The warning
547 * displays a case where we've unsafely cleared
548 * dev_priv->pm_iir. Although missing an interrupt of the same
549 * type is not a problem, it displays a problem in the logic.
550 *
551 * The mask bit in IMR is cleared by rps_work.
552 */
553 unsigned long flags;
554 spin_lock_irqsave(&dev_priv->rps_lock, flags);
555 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
556 I915_WRITE(GEN6_PMIMR, pm_iir);
557 dev_priv->pm_iir |= pm_iir;
558 spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
559 queue_work(dev_priv->wq, &dev_priv->rps_work);
560 }
561
562 /* should clear PCH hotplug event before clear CPU irq */
563 I915_WRITE(SDEIIR, pch_iir);
564 I915_WRITE(GTIIR, gt_iir);
565 I915_WRITE(DEIIR, de_iir);
566 I915_WRITE(GEN6_PMIIR, pm_iir);
567
568 done:
569 I915_WRITE(DEIER, de_ier);
570 POSTING_READ(DEIER);
571
572 return ret;
573 }
574
575 /**
576 * i915_error_work_func - do process context error handling work
577 * @work: work struct
578 *
579 * Fire an error uevent so userspace can see that a hang or error
580 * was detected.
581 */
582 static void i915_error_work_func(struct work_struct *work)
583 {
584 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
585 error_work);
586 struct drm_device *dev = dev_priv->dev;
587 char *error_event[] = { "ERROR=1", NULL };
588 char *reset_event[] = { "RESET=1", NULL };
589 char *reset_done_event[] = { "ERROR=0", NULL };
590
591 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
592
593 if (atomic_read(&dev_priv->mm.wedged)) {
594 DRM_DEBUG_DRIVER("resetting chip\n");
595 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
596 if (!i915_reset(dev, GRDOM_RENDER)) {
597 atomic_set(&dev_priv->mm.wedged, 0);
598 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
599 }
600 complete_all(&dev_priv->error_completion);
601 }
602 }
603
604 #ifdef CONFIG_DEBUG_FS
605 static struct drm_i915_error_object *
606 i915_error_object_create(struct drm_i915_private *dev_priv,
607 struct drm_i915_gem_object *src)
608 {
609 struct drm_i915_error_object *dst;
610 int page, page_count;
611 u32 reloc_offset;
612
613 if (src == NULL || src->pages == NULL)
614 return NULL;
615
616 page_count = src->base.size / PAGE_SIZE;
617
618 dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
619 if (dst == NULL)
620 return NULL;
621
622 reloc_offset = src->gtt_offset;
623 for (page = 0; page < page_count; page++) {
624 unsigned long flags;
625 void __iomem *s;
626 void *d;
627
628 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
629 if (d == NULL)
630 goto unwind;
631
632 local_irq_save(flags);
633 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
634 reloc_offset);
635 memcpy_fromio(d, s, PAGE_SIZE);
636 io_mapping_unmap_atomic(s);
637 local_irq_restore(flags);
638
639 dst->pages[page] = d;
640
641 reloc_offset += PAGE_SIZE;
642 }
643 dst->page_count = page_count;
644 dst->gtt_offset = src->gtt_offset;
645
646 return dst;
647
648 unwind:
649 while (page--)
650 kfree(dst->pages[page]);
651 kfree(dst);
652 return NULL;
653 }
654
655 static void
656 i915_error_object_free(struct drm_i915_error_object *obj)
657 {
658 int page;
659
660 if (obj == NULL)
661 return;
662
663 for (page = 0; page < obj->page_count; page++)
664 kfree(obj->pages[page]);
665
666 kfree(obj);
667 }
668
669 static void
670 i915_error_state_free(struct drm_device *dev,
671 struct drm_i915_error_state *error)
672 {
673 int i;
674
675 for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++)
676 i915_error_object_free(error->batchbuffer[i]);
677
678 for (i = 0; i < ARRAY_SIZE(error->ringbuffer); i++)
679 i915_error_object_free(error->ringbuffer[i]);
680
681 kfree(error->active_bo);
682 kfree(error->overlay);
683 kfree(error);
684 }
685
686 static u32 capture_bo_list(struct drm_i915_error_buffer *err,
687 int count,
688 struct list_head *head)
689 {
690 struct drm_i915_gem_object *obj;
691 int i = 0;
692
693 list_for_each_entry(obj, head, mm_list) {
694 err->size = obj->base.size;
695 err->name = obj->base.name;
696 err->seqno = obj->last_rendering_seqno;
697 err->gtt_offset = obj->gtt_offset;
698 err->read_domains = obj->base.read_domains;
699 err->write_domain = obj->base.write_domain;
700 err->fence_reg = obj->fence_reg;
701 err->pinned = 0;
702 if (obj->pin_count > 0)
703 err->pinned = 1;
704 if (obj->user_pin_count > 0)
705 err->pinned = -1;
706 err->tiling = obj->tiling_mode;
707 err->dirty = obj->dirty;
708 err->purgeable = obj->madv != I915_MADV_WILLNEED;
709 err->ring = obj->ring ? obj->ring->id : 0;
710 err->cache_level = obj->cache_level;
711
712 if (++i == count)
713 break;
714
715 err++;
716 }
717
718 return i;
719 }
720
721 static void i915_gem_record_fences(struct drm_device *dev,
722 struct drm_i915_error_state *error)
723 {
724 struct drm_i915_private *dev_priv = dev->dev_private;
725 int i;
726
727 /* Fences */
728 switch (INTEL_INFO(dev)->gen) {
729 case 6:
730 for (i = 0; i < 16; i++)
731 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
732 break;
733 case 5:
734 case 4:
735 for (i = 0; i < 16; i++)
736 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
737 break;
738 case 3:
739 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
740 for (i = 0; i < 8; i++)
741 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
742 case 2:
743 for (i = 0; i < 8; i++)
744 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
745 break;
746
747 }
748 }
749
750 static struct drm_i915_error_object *
751 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
752 struct intel_ring_buffer *ring)
753 {
754 struct drm_i915_gem_object *obj;
755 u32 seqno;
756
757 if (!ring->get_seqno)
758 return NULL;
759
760 seqno = ring->get_seqno(ring);
761 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
762 if (obj->ring != ring)
763 continue;
764
765 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
766 continue;
767
768 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
769 continue;
770
771 /* We need to copy these to an anonymous buffer as the simplest
772 * method to avoid being overwritten by userspace.
773 */
774 return i915_error_object_create(dev_priv, obj);
775 }
776
777 return NULL;
778 }
779
780 /**
781 * i915_capture_error_state - capture an error record for later analysis
782 * @dev: drm device
783 *
784 * Should be called when an error is detected (either a hang or an error
785 * interrupt) to capture error state from the time of the error. Fills
786 * out a structure which becomes available in debugfs for user level tools
787 * to pick up.
788 */
789 static void i915_capture_error_state(struct drm_device *dev)
790 {
791 struct drm_i915_private *dev_priv = dev->dev_private;
792 struct drm_i915_gem_object *obj;
793 struct drm_i915_error_state *error;
794 unsigned long flags;
795 int i, pipe;
796
797 spin_lock_irqsave(&dev_priv->error_lock, flags);
798 error = dev_priv->first_error;
799 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
800 if (error)
801 return;
802
803 /* Account for pipe specific data like PIPE*STAT */
804 error = kmalloc(sizeof(*error), GFP_ATOMIC);
805 if (!error) {
806 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
807 return;
808 }
809
810 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
811 dev->primary->index);
812
813 error->seqno = dev_priv->ring[RCS].get_seqno(&dev_priv->ring[RCS]);
814 error->eir = I915_READ(EIR);
815 error->pgtbl_er = I915_READ(PGTBL_ER);
816 for_each_pipe(pipe)
817 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
818 error->instpm = I915_READ(INSTPM);
819 error->error = 0;
820 if (INTEL_INFO(dev)->gen >= 6) {
821 error->error = I915_READ(ERROR_GEN6);
822
823 error->bcs_acthd = I915_READ(BCS_ACTHD);
824 error->bcs_ipehr = I915_READ(BCS_IPEHR);
825 error->bcs_ipeir = I915_READ(BCS_IPEIR);
826 error->bcs_instdone = I915_READ(BCS_INSTDONE);
827 error->bcs_seqno = 0;
828 if (dev_priv->ring[BCS].get_seqno)
829 error->bcs_seqno = dev_priv->ring[BCS].get_seqno(&dev_priv->ring[BCS]);
830
831 error->vcs_acthd = I915_READ(VCS_ACTHD);
832 error->vcs_ipehr = I915_READ(VCS_IPEHR);
833 error->vcs_ipeir = I915_READ(VCS_IPEIR);
834 error->vcs_instdone = I915_READ(VCS_INSTDONE);
835 error->vcs_seqno = 0;
836 if (dev_priv->ring[VCS].get_seqno)
837 error->vcs_seqno = dev_priv->ring[VCS].get_seqno(&dev_priv->ring[VCS]);
838 }
839 if (INTEL_INFO(dev)->gen >= 4) {
840 error->ipeir = I915_READ(IPEIR_I965);
841 error->ipehr = I915_READ(IPEHR_I965);
842 error->instdone = I915_READ(INSTDONE_I965);
843 error->instps = I915_READ(INSTPS);
844 error->instdone1 = I915_READ(INSTDONE1);
845 error->acthd = I915_READ(ACTHD_I965);
846 error->bbaddr = I915_READ64(BB_ADDR);
847 } else {
848 error->ipeir = I915_READ(IPEIR);
849 error->ipehr = I915_READ(IPEHR);
850 error->instdone = I915_READ(INSTDONE);
851 error->acthd = I915_READ(ACTHD);
852 error->bbaddr = 0;
853 }
854 i915_gem_record_fences(dev, error);
855
856 /* Record the active batch and ring buffers */
857 for (i = 0; i < I915_NUM_RINGS; i++) {
858 error->batchbuffer[i] =
859 i915_error_first_batchbuffer(dev_priv,
860 &dev_priv->ring[i]);
861
862 error->ringbuffer[i] =
863 i915_error_object_create(dev_priv,
864 dev_priv->ring[i].obj);
865 }
866
867 /* Record buffers on the active and pinned lists. */
868 error->active_bo = NULL;
869 error->pinned_bo = NULL;
870
871 i = 0;
872 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
873 i++;
874 error->active_bo_count = i;
875 list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
876 i++;
877 error->pinned_bo_count = i - error->active_bo_count;
878
879 error->active_bo = NULL;
880 error->pinned_bo = NULL;
881 if (i) {
882 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
883 GFP_ATOMIC);
884 if (error->active_bo)
885 error->pinned_bo =
886 error->active_bo + error->active_bo_count;
887 }
888
889 if (error->active_bo)
890 error->active_bo_count =
891 capture_bo_list(error->active_bo,
892 error->active_bo_count,
893 &dev_priv->mm.active_list);
894
895 if (error->pinned_bo)
896 error->pinned_bo_count =
897 capture_bo_list(error->pinned_bo,
898 error->pinned_bo_count,
899 &dev_priv->mm.pinned_list);
900
901 do_gettimeofday(&error->time);
902
903 error->overlay = intel_overlay_capture_error_state(dev);
904 error->display = intel_display_capture_error_state(dev);
905
906 spin_lock_irqsave(&dev_priv->error_lock, flags);
907 if (dev_priv->first_error == NULL) {
908 dev_priv->first_error = error;
909 error = NULL;
910 }
911 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
912
913 if (error)
914 i915_error_state_free(dev, error);
915 }
916
917 void i915_destroy_error_state(struct drm_device *dev)
918 {
919 struct drm_i915_private *dev_priv = dev->dev_private;
920 struct drm_i915_error_state *error;
921
922 spin_lock(&dev_priv->error_lock);
923 error = dev_priv->first_error;
924 dev_priv->first_error = NULL;
925 spin_unlock(&dev_priv->error_lock);
926
927 if (error)
928 i915_error_state_free(dev, error);
929 }
930 #else
931 #define i915_capture_error_state(x)
932 #endif
933
934 static void i915_report_and_clear_eir(struct drm_device *dev)
935 {
936 struct drm_i915_private *dev_priv = dev->dev_private;
937 u32 eir = I915_READ(EIR);
938 int pipe;
939
940 if (!eir)
941 return;
942
943 printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
944 eir);
945
946 if (IS_G4X(dev)) {
947 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
948 u32 ipeir = I915_READ(IPEIR_I965);
949
950 printk(KERN_ERR " IPEIR: 0x%08x\n",
951 I915_READ(IPEIR_I965));
952 printk(KERN_ERR " IPEHR: 0x%08x\n",
953 I915_READ(IPEHR_I965));
954 printk(KERN_ERR " INSTDONE: 0x%08x\n",
955 I915_READ(INSTDONE_I965));
956 printk(KERN_ERR " INSTPS: 0x%08x\n",
957 I915_READ(INSTPS));
958 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
959 I915_READ(INSTDONE1));
960 printk(KERN_ERR " ACTHD: 0x%08x\n",
961 I915_READ(ACTHD_I965));
962 I915_WRITE(IPEIR_I965, ipeir);
963 POSTING_READ(IPEIR_I965);
964 }
965 if (eir & GM45_ERROR_PAGE_TABLE) {
966 u32 pgtbl_err = I915_READ(PGTBL_ER);
967 printk(KERN_ERR "page table error\n");
968 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
969 pgtbl_err);
970 I915_WRITE(PGTBL_ER, pgtbl_err);
971 POSTING_READ(PGTBL_ER);
972 }
973 }
974
975 if (!IS_GEN2(dev)) {
976 if (eir & I915_ERROR_PAGE_TABLE) {
977 u32 pgtbl_err = I915_READ(PGTBL_ER);
978 printk(KERN_ERR "page table error\n");
979 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
980 pgtbl_err);
981 I915_WRITE(PGTBL_ER, pgtbl_err);
982 POSTING_READ(PGTBL_ER);
983 }
984 }
985
986 if (eir & I915_ERROR_MEMORY_REFRESH) {
987 printk(KERN_ERR "memory refresh error:\n");
988 for_each_pipe(pipe)
989 printk(KERN_ERR "pipe %c stat: 0x%08x\n",
990 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
991 /* pipestat has already been acked */
992 }
993 if (eir & I915_ERROR_INSTRUCTION) {
994 printk(KERN_ERR "instruction error\n");
995 printk(KERN_ERR " INSTPM: 0x%08x\n",
996 I915_READ(INSTPM));
997 if (INTEL_INFO(dev)->gen < 4) {
998 u32 ipeir = I915_READ(IPEIR);
999
1000 printk(KERN_ERR " IPEIR: 0x%08x\n",
1001 I915_READ(IPEIR));
1002 printk(KERN_ERR " IPEHR: 0x%08x\n",
1003 I915_READ(IPEHR));
1004 printk(KERN_ERR " INSTDONE: 0x%08x\n",
1005 I915_READ(INSTDONE));
1006 printk(KERN_ERR " ACTHD: 0x%08x\n",
1007 I915_READ(ACTHD));
1008 I915_WRITE(IPEIR, ipeir);
1009 POSTING_READ(IPEIR);
1010 } else {
1011 u32 ipeir = I915_READ(IPEIR_I965);
1012
1013 printk(KERN_ERR " IPEIR: 0x%08x\n",
1014 I915_READ(IPEIR_I965));
1015 printk(KERN_ERR " IPEHR: 0x%08x\n",
1016 I915_READ(IPEHR_I965));
1017 printk(KERN_ERR " INSTDONE: 0x%08x\n",
1018 I915_READ(INSTDONE_I965));
1019 printk(KERN_ERR " INSTPS: 0x%08x\n",
1020 I915_READ(INSTPS));
1021 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
1022 I915_READ(INSTDONE1));
1023 printk(KERN_ERR " ACTHD: 0x%08x\n",
1024 I915_READ(ACTHD_I965));
1025 I915_WRITE(IPEIR_I965, ipeir);
1026 POSTING_READ(IPEIR_I965);
1027 }
1028 }
1029
1030 I915_WRITE(EIR, eir);
1031 POSTING_READ(EIR);
1032 eir = I915_READ(EIR);
1033 if (eir) {
1034 /*
1035 * some errors might have become stuck,
1036 * mask them.
1037 */
1038 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1039 I915_WRITE(EMR, I915_READ(EMR) | eir);
1040 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1041 }
1042 }
1043
1044 /**
1045 * i915_handle_error - handle an error interrupt
1046 * @dev: drm device
1047 *
1048 * Do some basic checking of regsiter state at error interrupt time and
1049 * dump it to the syslog. Also call i915_capture_error_state() to make
1050 * sure we get a record and make it available in debugfs. Fire a uevent
1051 * so userspace knows something bad happened (should trigger collection
1052 * of a ring dump etc.).
1053 */
1054 void i915_handle_error(struct drm_device *dev, bool wedged)
1055 {
1056 struct drm_i915_private *dev_priv = dev->dev_private;
1057
1058 i915_capture_error_state(dev);
1059 i915_report_and_clear_eir(dev);
1060
1061 if (wedged) {
1062 INIT_COMPLETION(dev_priv->error_completion);
1063 atomic_set(&dev_priv->mm.wedged, 1);
1064
1065 /*
1066 * Wakeup waiting processes so they don't hang
1067 */
1068 wake_up_all(&dev_priv->ring[RCS].irq_queue);
1069 if (HAS_BSD(dev))
1070 wake_up_all(&dev_priv->ring[VCS].irq_queue);
1071 if (HAS_BLT(dev))
1072 wake_up_all(&dev_priv->ring[BCS].irq_queue);
1073 }
1074
1075 queue_work(dev_priv->wq, &dev_priv->error_work);
1076 }
1077
1078 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1079 {
1080 drm_i915_private_t *dev_priv = dev->dev_private;
1081 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1083 struct drm_i915_gem_object *obj;
1084 struct intel_unpin_work *work;
1085 unsigned long flags;
1086 bool stall_detected;
1087
1088 /* Ignore early vblank irqs */
1089 if (intel_crtc == NULL)
1090 return;
1091
1092 spin_lock_irqsave(&dev->event_lock, flags);
1093 work = intel_crtc->unpin_work;
1094
1095 if (work == NULL || work->pending || !work->enable_stall_check) {
1096 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1097 spin_unlock_irqrestore(&dev->event_lock, flags);
1098 return;
1099 }
1100
1101 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1102 obj = work->pending_flip_obj;
1103 if (INTEL_INFO(dev)->gen >= 4) {
1104 int dspsurf = DSPSURF(intel_crtc->plane);
1105 stall_detected = I915_READ(dspsurf) == obj->gtt_offset;
1106 } else {
1107 int dspaddr = DSPADDR(intel_crtc->plane);
1108 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1109 crtc->y * crtc->fb->pitch +
1110 crtc->x * crtc->fb->bits_per_pixel/8);
1111 }
1112
1113 spin_unlock_irqrestore(&dev->event_lock, flags);
1114
1115 if (stall_detected) {
1116 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1117 intel_prepare_page_flip(dev, intel_crtc->plane);
1118 }
1119 }
1120
1121 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
1122 {
1123 struct drm_device *dev = (struct drm_device *) arg;
1124 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1125 struct drm_i915_master_private *master_priv;
1126 u32 iir, new_iir;
1127 u32 pipe_stats[I915_MAX_PIPES];
1128 u32 vblank_status;
1129 int vblank = 0;
1130 unsigned long irqflags;
1131 int irq_received;
1132 int ret = IRQ_NONE, pipe;
1133 bool blc_event = false;
1134
1135 atomic_inc(&dev_priv->irq_received);
1136
1137 if (HAS_PCH_SPLIT(dev))
1138 return ironlake_irq_handler(dev);
1139
1140 iir = I915_READ(IIR);
1141
1142 if (INTEL_INFO(dev)->gen >= 4)
1143 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
1144 else
1145 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
1146
1147 for (;;) {
1148 irq_received = iir != 0;
1149
1150 /* Can't rely on pipestat interrupt bit in iir as it might
1151 * have been cleared after the pipestat interrupt was received.
1152 * It doesn't set the bit in iir again, but it still produces
1153 * interrupts (for non-MSI).
1154 */
1155 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1156 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
1157 i915_handle_error(dev, false);
1158
1159 for_each_pipe(pipe) {
1160 int reg = PIPESTAT(pipe);
1161 pipe_stats[pipe] = I915_READ(reg);
1162
1163 /*
1164 * Clear the PIPE*STAT regs before the IIR
1165 */
1166 if (pipe_stats[pipe] & 0x8000ffff) {
1167 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1168 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1169 pipe_name(pipe));
1170 I915_WRITE(reg, pipe_stats[pipe]);
1171 irq_received = 1;
1172 }
1173 }
1174 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1175
1176 if (!irq_received)
1177 break;
1178
1179 ret = IRQ_HANDLED;
1180
1181 /* Consume port. Then clear IIR or we'll miss events */
1182 if ((I915_HAS_HOTPLUG(dev)) &&
1183 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
1184 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1185
1186 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1187 hotplug_status);
1188 if (hotplug_status & dev_priv->hotplug_supported_mask)
1189 queue_work(dev_priv->wq,
1190 &dev_priv->hotplug_work);
1191
1192 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1193 I915_READ(PORT_HOTPLUG_STAT);
1194 }
1195
1196 I915_WRITE(IIR, iir);
1197 new_iir = I915_READ(IIR); /* Flush posted writes */
1198
1199 if (dev->primary->master) {
1200 master_priv = dev->primary->master->driver_priv;
1201 if (master_priv->sarea_priv)
1202 master_priv->sarea_priv->last_dispatch =
1203 READ_BREADCRUMB(dev_priv);
1204 }
1205
1206 if (iir & I915_USER_INTERRUPT)
1207 notify_ring(dev, &dev_priv->ring[RCS]);
1208 if (iir & I915_BSD_USER_INTERRUPT)
1209 notify_ring(dev, &dev_priv->ring[VCS]);
1210
1211 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
1212 intel_prepare_page_flip(dev, 0);
1213 if (dev_priv->flip_pending_is_done)
1214 intel_finish_page_flip_plane(dev, 0);
1215 }
1216
1217 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
1218 intel_prepare_page_flip(dev, 1);
1219 if (dev_priv->flip_pending_is_done)
1220 intel_finish_page_flip_plane(dev, 1);
1221 }
1222
1223 for_each_pipe(pipe) {
1224 if (pipe_stats[pipe] & vblank_status &&
1225 drm_handle_vblank(dev, pipe)) {
1226 vblank++;
1227 if (!dev_priv->flip_pending_is_done) {
1228 i915_pageflip_stall_check(dev, pipe);
1229 intel_finish_page_flip(dev, pipe);
1230 }
1231 }
1232
1233 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1234 blc_event = true;
1235 }
1236
1237
1238 if (blc_event || (iir & I915_ASLE_INTERRUPT))
1239 intel_opregion_asle_intr(dev);
1240
1241 /* With MSI, interrupts are only generated when iir
1242 * transitions from zero to nonzero. If another bit got
1243 * set while we were handling the existing iir bits, then
1244 * we would never get another interrupt.
1245 *
1246 * This is fine on non-MSI as well, as if we hit this path
1247 * we avoid exiting the interrupt handler only to generate
1248 * another one.
1249 *
1250 * Note that for MSI this could cause a stray interrupt report
1251 * if an interrupt landed in the time between writing IIR and
1252 * the posting read. This should be rare enough to never
1253 * trigger the 99% of 100,000 interrupts test for disabling
1254 * stray interrupts.
1255 */
1256 iir = new_iir;
1257 }
1258
1259 return ret;
1260 }
1261
1262 static int i915_emit_irq(struct drm_device * dev)
1263 {
1264 drm_i915_private_t *dev_priv = dev->dev_private;
1265 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1266
1267 i915_kernel_lost_context(dev);
1268
1269 DRM_DEBUG_DRIVER("\n");
1270
1271 dev_priv->counter++;
1272 if (dev_priv->counter > 0x7FFFFFFFUL)
1273 dev_priv->counter = 1;
1274 if (master_priv->sarea_priv)
1275 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1276
1277 if (BEGIN_LP_RING(4) == 0) {
1278 OUT_RING(MI_STORE_DWORD_INDEX);
1279 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1280 OUT_RING(dev_priv->counter);
1281 OUT_RING(MI_USER_INTERRUPT);
1282 ADVANCE_LP_RING();
1283 }
1284
1285 return dev_priv->counter;
1286 }
1287
1288 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1289 {
1290 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1291 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1292 int ret = 0;
1293 struct intel_ring_buffer *ring = LP_RING(dev_priv);
1294
1295 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1296 READ_BREADCRUMB(dev_priv));
1297
1298 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1299 if (master_priv->sarea_priv)
1300 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1301 return 0;
1302 }
1303
1304 if (master_priv->sarea_priv)
1305 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1306
1307 if (ring->irq_get(ring)) {
1308 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
1309 READ_BREADCRUMB(dev_priv) >= irq_nr);
1310 ring->irq_put(ring);
1311 } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
1312 ret = -EBUSY;
1313
1314 if (ret == -EBUSY) {
1315 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1316 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1317 }
1318
1319 return ret;
1320 }
1321
1322 /* Needs the lock as it touches the ring.
1323 */
1324 int i915_irq_emit(struct drm_device *dev, void *data,
1325 struct drm_file *file_priv)
1326 {
1327 drm_i915_private_t *dev_priv = dev->dev_private;
1328 drm_i915_irq_emit_t *emit = data;
1329 int result;
1330
1331 if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
1332 DRM_ERROR("called with no initialization\n");
1333 return -EINVAL;
1334 }
1335
1336 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1337
1338 mutex_lock(&dev->struct_mutex);
1339 result = i915_emit_irq(dev);
1340 mutex_unlock(&dev->struct_mutex);
1341
1342 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1343 DRM_ERROR("copy_to_user\n");
1344 return -EFAULT;
1345 }
1346
1347 return 0;
1348 }
1349
1350 /* Doesn't need the hardware lock.
1351 */
1352 int i915_irq_wait(struct drm_device *dev, void *data,
1353 struct drm_file *file_priv)
1354 {
1355 drm_i915_private_t *dev_priv = dev->dev_private;
1356 drm_i915_irq_wait_t *irqwait = data;
1357
1358 if (!dev_priv) {
1359 DRM_ERROR("called with no initialization\n");
1360 return -EINVAL;
1361 }
1362
1363 return i915_wait_irq(dev, irqwait->irq_seq);
1364 }
1365
1366 /* Called from drm generic code, passed 'crtc' which
1367 * we use as a pipe index
1368 */
1369 int i915_enable_vblank(struct drm_device *dev, int pipe)
1370 {
1371 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1372 unsigned long irqflags;
1373
1374 if (!i915_pipe_enabled(dev, pipe))
1375 return -EINVAL;
1376
1377 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1378 if (HAS_PCH_SPLIT(dev))
1379 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1380 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1381 else if (INTEL_INFO(dev)->gen >= 4)
1382 i915_enable_pipestat(dev_priv, pipe,
1383 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1384 else
1385 i915_enable_pipestat(dev_priv, pipe,
1386 PIPE_VBLANK_INTERRUPT_ENABLE);
1387
1388 /* maintain vblank delivery even in deep C-states */
1389 if (dev_priv->info->gen == 3)
1390 I915_WRITE(INSTPM, INSTPM_AGPBUSY_DIS << 16);
1391 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1392
1393 return 0;
1394 }
1395
1396 /* Called from drm generic code, passed 'crtc' which
1397 * we use as a pipe index
1398 */
1399 void i915_disable_vblank(struct drm_device *dev, int pipe)
1400 {
1401 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1402 unsigned long irqflags;
1403
1404 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1405 if (dev_priv->info->gen == 3)
1406 I915_WRITE(INSTPM,
1407 INSTPM_AGPBUSY_DIS << 16 | INSTPM_AGPBUSY_DIS);
1408
1409 if (HAS_PCH_SPLIT(dev))
1410 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1411 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1412 else
1413 i915_disable_pipestat(dev_priv, pipe,
1414 PIPE_VBLANK_INTERRUPT_ENABLE |
1415 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1416 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1417 }
1418
1419 /* Set the vblank monitor pipe
1420 */
1421 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1422 struct drm_file *file_priv)
1423 {
1424 drm_i915_private_t *dev_priv = dev->dev_private;
1425
1426 if (!dev_priv) {
1427 DRM_ERROR("called with no initialization\n");
1428 return -EINVAL;
1429 }
1430
1431 return 0;
1432 }
1433
1434 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1435 struct drm_file *file_priv)
1436 {
1437 drm_i915_private_t *dev_priv = dev->dev_private;
1438 drm_i915_vblank_pipe_t *pipe = data;
1439
1440 if (!dev_priv) {
1441 DRM_ERROR("called with no initialization\n");
1442 return -EINVAL;
1443 }
1444
1445 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1446
1447 return 0;
1448 }
1449
1450 /**
1451 * Schedule buffer swap at given vertical blank.
1452 */
1453 int i915_vblank_swap(struct drm_device *dev, void *data,
1454 struct drm_file *file_priv)
1455 {
1456 /* The delayed swap mechanism was fundamentally racy, and has been
1457 * removed. The model was that the client requested a delayed flip/swap
1458 * from the kernel, then waited for vblank before continuing to perform
1459 * rendering. The problem was that the kernel might wake the client
1460 * up before it dispatched the vblank swap (since the lock has to be
1461 * held while touching the ringbuffer), in which case the client would
1462 * clear and start the next frame before the swap occurred, and
1463 * flicker would occur in addition to likely missing the vblank.
1464 *
1465 * In the absence of this ioctl, userland falls back to a correct path
1466 * of waiting for a vblank, then dispatching the swap on its own.
1467 * Context switching to userland and back is plenty fast enough for
1468 * meeting the requirements of vblank swapping.
1469 */
1470 return -EINVAL;
1471 }
1472
1473 static u32
1474 ring_last_seqno(struct intel_ring_buffer *ring)
1475 {
1476 return list_entry(ring->request_list.prev,
1477 struct drm_i915_gem_request, list)->seqno;
1478 }
1479
1480 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1481 {
1482 if (list_empty(&ring->request_list) ||
1483 i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1484 /* Issue a wake-up to catch stuck h/w. */
1485 if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) {
1486 DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n",
1487 ring->name,
1488 ring->waiting_seqno,
1489 ring->get_seqno(ring));
1490 wake_up_all(&ring->irq_queue);
1491 *err = true;
1492 }
1493 return true;
1494 }
1495 return false;
1496 }
1497
1498 static bool kick_ring(struct intel_ring_buffer *ring)
1499 {
1500 struct drm_device *dev = ring->dev;
1501 struct drm_i915_private *dev_priv = dev->dev_private;
1502 u32 tmp = I915_READ_CTL(ring);
1503 if (tmp & RING_WAIT) {
1504 DRM_ERROR("Kicking stuck wait on %s\n",
1505 ring->name);
1506 I915_WRITE_CTL(ring, tmp);
1507 return true;
1508 }
1509 if (IS_GEN6(dev) &&
1510 (tmp & RING_WAIT_SEMAPHORE)) {
1511 DRM_ERROR("Kicking stuck semaphore on %s\n",
1512 ring->name);
1513 I915_WRITE_CTL(ring, tmp);
1514 return true;
1515 }
1516 return false;
1517 }
1518
1519 /**
1520 * This is called when the chip hasn't reported back with completed
1521 * batchbuffers in a long time. The first time this is called we simply record
1522 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1523 * again, we assume the chip is wedged and try to fix it.
1524 */
1525 void i915_hangcheck_elapsed(unsigned long data)
1526 {
1527 struct drm_device *dev = (struct drm_device *)data;
1528 drm_i915_private_t *dev_priv = dev->dev_private;
1529 uint32_t acthd, instdone, instdone1;
1530 bool err = false;
1531
1532 /* If all work is done then ACTHD clearly hasn't advanced. */
1533 if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) &&
1534 i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) &&
1535 i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) {
1536 dev_priv->hangcheck_count = 0;
1537 if (err)
1538 goto repeat;
1539 return;
1540 }
1541
1542 if (INTEL_INFO(dev)->gen < 4) {
1543 acthd = I915_READ(ACTHD);
1544 instdone = I915_READ(INSTDONE);
1545 instdone1 = 0;
1546 } else {
1547 acthd = I915_READ(ACTHD_I965);
1548 instdone = I915_READ(INSTDONE_I965);
1549 instdone1 = I915_READ(INSTDONE1);
1550 }
1551
1552 if (dev_priv->last_acthd == acthd &&
1553 dev_priv->last_instdone == instdone &&
1554 dev_priv->last_instdone1 == instdone1) {
1555 if (dev_priv->hangcheck_count++ > 1) {
1556 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1557
1558 if (!IS_GEN2(dev)) {
1559 /* Is the chip hanging on a WAIT_FOR_EVENT?
1560 * If so we can simply poke the RB_WAIT bit
1561 * and break the hang. This should work on
1562 * all but the second generation chipsets.
1563 */
1564
1565 if (kick_ring(&dev_priv->ring[RCS]))
1566 goto repeat;
1567
1568 if (HAS_BSD(dev) &&
1569 kick_ring(&dev_priv->ring[VCS]))
1570 goto repeat;
1571
1572 if (HAS_BLT(dev) &&
1573 kick_ring(&dev_priv->ring[BCS]))
1574 goto repeat;
1575 }
1576
1577 i915_handle_error(dev, true);
1578 return;
1579 }
1580 } else {
1581 dev_priv->hangcheck_count = 0;
1582
1583 dev_priv->last_acthd = acthd;
1584 dev_priv->last_instdone = instdone;
1585 dev_priv->last_instdone1 = instdone1;
1586 }
1587
1588 repeat:
1589 /* Reset timer case chip hangs without another request being added */
1590 mod_timer(&dev_priv->hangcheck_timer,
1591 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1592 }
1593
1594 /* drm_dma.h hooks
1595 */
1596 static void ironlake_irq_preinstall(struct drm_device *dev)
1597 {
1598 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1599
1600 I915_WRITE(HWSTAM, 0xeffe);
1601
1602 /* XXX hotplug from PCH */
1603
1604 I915_WRITE(DEIMR, 0xffffffff);
1605 I915_WRITE(DEIER, 0x0);
1606 POSTING_READ(DEIER);
1607
1608 /* and GT */
1609 I915_WRITE(GTIMR, 0xffffffff);
1610 I915_WRITE(GTIER, 0x0);
1611 POSTING_READ(GTIER);
1612
1613 /* south display irq */
1614 I915_WRITE(SDEIMR, 0xffffffff);
1615 I915_WRITE(SDEIER, 0x0);
1616 POSTING_READ(SDEIER);
1617 }
1618
1619 static int ironlake_irq_postinstall(struct drm_device *dev)
1620 {
1621 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1622 /* enable kind of interrupts always enabled */
1623 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1624 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1625 u32 render_irqs;
1626 u32 hotplug_mask;
1627
1628 dev_priv->irq_mask = ~display_mask;
1629
1630 /* should always can generate irq */
1631 I915_WRITE(DEIIR, I915_READ(DEIIR));
1632 I915_WRITE(DEIMR, dev_priv->irq_mask);
1633 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
1634 POSTING_READ(DEIER);
1635
1636 dev_priv->gt_irq_mask = ~0;
1637
1638 I915_WRITE(GTIIR, I915_READ(GTIIR));
1639 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1640
1641 if (IS_GEN6(dev))
1642 render_irqs =
1643 GT_USER_INTERRUPT |
1644 GT_GEN6_BSD_USER_INTERRUPT |
1645 GT_BLT_USER_INTERRUPT;
1646 else
1647 render_irqs =
1648 GT_USER_INTERRUPT |
1649 GT_PIPE_NOTIFY |
1650 GT_BSD_USER_INTERRUPT;
1651 I915_WRITE(GTIER, render_irqs);
1652 POSTING_READ(GTIER);
1653
1654 if (HAS_PCH_CPT(dev)) {
1655 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1656 SDE_PORTB_HOTPLUG_CPT |
1657 SDE_PORTC_HOTPLUG_CPT |
1658 SDE_PORTD_HOTPLUG_CPT);
1659 } else {
1660 hotplug_mask = (SDE_CRT_HOTPLUG |
1661 SDE_PORTB_HOTPLUG |
1662 SDE_PORTC_HOTPLUG |
1663 SDE_PORTD_HOTPLUG |
1664 SDE_AUX_MASK);
1665 }
1666
1667 dev_priv->pch_irq_mask = ~hotplug_mask;
1668
1669 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1670 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1671 I915_WRITE(SDEIER, hotplug_mask);
1672 POSTING_READ(SDEIER);
1673
1674 if (IS_IRONLAKE_M(dev)) {
1675 /* Clear & enable PCU event interrupts */
1676 I915_WRITE(DEIIR, DE_PCU_EVENT);
1677 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1678 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1679 }
1680
1681 return 0;
1682 }
1683
1684 void i915_driver_irq_preinstall(struct drm_device * dev)
1685 {
1686 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1687 int pipe;
1688
1689 atomic_set(&dev_priv->irq_received, 0);
1690
1691 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1692 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1693 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
1694
1695 if (HAS_PCH_SPLIT(dev)) {
1696 ironlake_irq_preinstall(dev);
1697 return;
1698 }
1699
1700 if (I915_HAS_HOTPLUG(dev)) {
1701 I915_WRITE(PORT_HOTPLUG_EN, 0);
1702 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1703 }
1704
1705 I915_WRITE(HWSTAM, 0xeffe);
1706 for_each_pipe(pipe)
1707 I915_WRITE(PIPESTAT(pipe), 0);
1708 I915_WRITE(IMR, 0xffffffff);
1709 I915_WRITE(IER, 0x0);
1710 POSTING_READ(IER);
1711 }
1712
1713 /*
1714 * Must be called after intel_modeset_init or hotplug interrupts won't be
1715 * enabled correctly.
1716 */
1717 int i915_driver_irq_postinstall(struct drm_device *dev)
1718 {
1719 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1720 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1721 u32 error_mask;
1722
1723 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1724
1725 if (HAS_PCH_SPLIT(dev))
1726 return ironlake_irq_postinstall(dev);
1727
1728 /* Unmask the interrupts that we always want on. */
1729 dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX;
1730
1731 dev_priv->pipestat[0] = 0;
1732 dev_priv->pipestat[1] = 0;
1733
1734 if (I915_HAS_HOTPLUG(dev)) {
1735 /* Enable in IER... */
1736 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1737 /* and unmask in IMR */
1738 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
1739 }
1740
1741 /*
1742 * Enable some error detection, note the instruction error mask
1743 * bit is reserved, so we leave it masked.
1744 */
1745 if (IS_G4X(dev)) {
1746 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1747 GM45_ERROR_MEM_PRIV |
1748 GM45_ERROR_CP_PRIV |
1749 I915_ERROR_MEMORY_REFRESH);
1750 } else {
1751 error_mask = ~(I915_ERROR_PAGE_TABLE |
1752 I915_ERROR_MEMORY_REFRESH);
1753 }
1754 I915_WRITE(EMR, error_mask);
1755
1756 I915_WRITE(IMR, dev_priv->irq_mask);
1757 I915_WRITE(IER, enable_mask);
1758 POSTING_READ(IER);
1759
1760 if (I915_HAS_HOTPLUG(dev)) {
1761 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1762
1763 /* Note HDMI and DP share bits */
1764 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1765 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1766 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1767 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1768 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1769 hotplug_en |= HDMID_HOTPLUG_INT_EN;
1770 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1771 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1772 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1773 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1774 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1775 hotplug_en |= CRT_HOTPLUG_INT_EN;
1776
1777 /* Programming the CRT detection parameters tends
1778 to generate a spurious hotplug event about three
1779 seconds later. So just do it once.
1780 */
1781 if (IS_G4X(dev))
1782 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
1783 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1784 }
1785
1786 /* Ignore TV since it's buggy */
1787
1788 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1789 }
1790
1791 intel_opregion_enable_asle(dev);
1792
1793 return 0;
1794 }
1795
1796 static void ironlake_irq_uninstall(struct drm_device *dev)
1797 {
1798 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1799 I915_WRITE(HWSTAM, 0xffffffff);
1800
1801 I915_WRITE(DEIMR, 0xffffffff);
1802 I915_WRITE(DEIER, 0x0);
1803 I915_WRITE(DEIIR, I915_READ(DEIIR));
1804
1805 I915_WRITE(GTIMR, 0xffffffff);
1806 I915_WRITE(GTIER, 0x0);
1807 I915_WRITE(GTIIR, I915_READ(GTIIR));
1808 }
1809
1810 void i915_driver_irq_uninstall(struct drm_device * dev)
1811 {
1812 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1813 int pipe;
1814
1815 if (!dev_priv)
1816 return;
1817
1818 dev_priv->vblank_pipe = 0;
1819
1820 if (HAS_PCH_SPLIT(dev)) {
1821 ironlake_irq_uninstall(dev);
1822 return;
1823 }
1824
1825 if (I915_HAS_HOTPLUG(dev)) {
1826 I915_WRITE(PORT_HOTPLUG_EN, 0);
1827 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1828 }
1829
1830 I915_WRITE(HWSTAM, 0xffffffff);
1831 for_each_pipe(pipe)
1832 I915_WRITE(PIPESTAT(pipe), 0);
1833 I915_WRITE(IMR, 0xffffffff);
1834 I915_WRITE(IER, 0x0);
1835
1836 for_each_pipe(pipe)
1837 I915_WRITE(PIPESTAT(pipe),
1838 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
1839 I915_WRITE(IIR, I915_READ(IIR));
1840 }
Linux kernel - Deliverables
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