1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
34 #include <drm/i915_drm.h>
36 #include "i915_trace.h"
37 #include "intel_drv.h"
39 static const u32 hpd_ibx
[] = {
40 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
41 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
42 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
43 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
44 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
47 static const u32 hpd_cpt
[] = {
48 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
49 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG_CPT
,
50 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
51 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
52 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
55 static const u32 hpd_mask_i915
[] = {
56 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
57 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
58 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
59 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
60 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
61 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
64 static const u32 hpd_status_gen4
[] = {
65 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
66 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
67 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
68 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
69 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
70 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
73 static const u32 hpd_status_i915
[] = { /* i915 and valleyview are the same */
74 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
75 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
76 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
77 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
78 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
79 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
82 /* For display hotplug interrupt */
84 ironlake_enable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
86 assert_spin_locked(&dev_priv
->irq_lock
);
88 if ((dev_priv
->irq_mask
& mask
) != 0) {
89 dev_priv
->irq_mask
&= ~mask
;
90 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
96 ironlake_disable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
98 assert_spin_locked(&dev_priv
->irq_lock
);
100 if ((dev_priv
->irq_mask
& mask
) != mask
) {
101 dev_priv
->irq_mask
|= mask
;
102 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
108 * ilk_update_gt_irq - update GTIMR
109 * @dev_priv: driver private
110 * @interrupt_mask: mask of interrupt bits to update
111 * @enabled_irq_mask: mask of interrupt bits to enable
113 static void ilk_update_gt_irq(struct drm_i915_private
*dev_priv
,
114 uint32_t interrupt_mask
,
115 uint32_t enabled_irq_mask
)
117 assert_spin_locked(&dev_priv
->irq_lock
);
119 dev_priv
->gt_irq_mask
&= ~interrupt_mask
;
120 dev_priv
->gt_irq_mask
|= (~enabled_irq_mask
& interrupt_mask
);
121 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
125 void ilk_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
127 ilk_update_gt_irq(dev_priv
, mask
, mask
);
130 void ilk_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
132 ilk_update_gt_irq(dev_priv
, mask
, 0);
135 static bool ivb_can_enable_err_int(struct drm_device
*dev
)
137 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
138 struct intel_crtc
*crtc
;
141 assert_spin_locked(&dev_priv
->irq_lock
);
143 for_each_pipe(pipe
) {
144 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
146 if (crtc
->cpu_fifo_underrun_disabled
)
153 static bool cpt_can_enable_serr_int(struct drm_device
*dev
)
155 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
157 struct intel_crtc
*crtc
;
159 assert_spin_locked(&dev_priv
->irq_lock
);
161 for_each_pipe(pipe
) {
162 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
164 if (crtc
->pch_fifo_underrun_disabled
)
171 static void ironlake_set_fifo_underrun_reporting(struct drm_device
*dev
,
172 enum pipe pipe
, bool enable
)
174 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
175 uint32_t bit
= (pipe
== PIPE_A
) ? DE_PIPEA_FIFO_UNDERRUN
:
176 DE_PIPEB_FIFO_UNDERRUN
;
179 ironlake_enable_display_irq(dev_priv
, bit
);
181 ironlake_disable_display_irq(dev_priv
, bit
);
184 static void ivybridge_set_fifo_underrun_reporting(struct drm_device
*dev
,
185 enum pipe pipe
, bool enable
)
187 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
189 I915_WRITE(GEN7_ERR_INT
, ERR_INT_FIFO_UNDERRUN(pipe
));
191 if (!ivb_can_enable_err_int(dev
))
194 ironlake_enable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
196 bool was_enabled
= !(I915_READ(DEIMR
) & DE_ERR_INT_IVB
);
198 /* Change the state _after_ we've read out the current one. */
199 ironlake_disable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
202 (I915_READ(GEN7_ERR_INT
) & ERR_INT_FIFO_UNDERRUN(pipe
))) {
203 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
210 * ibx_display_interrupt_update - update SDEIMR
211 * @dev_priv: driver private
212 * @interrupt_mask: mask of interrupt bits to update
213 * @enabled_irq_mask: mask of interrupt bits to enable
215 static void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
216 uint32_t interrupt_mask
,
217 uint32_t enabled_irq_mask
)
219 uint32_t sdeimr
= I915_READ(SDEIMR
);
220 sdeimr
&= ~interrupt_mask
;
221 sdeimr
|= (~enabled_irq_mask
& interrupt_mask
);
223 assert_spin_locked(&dev_priv
->irq_lock
);
225 I915_WRITE(SDEIMR
, sdeimr
);
226 POSTING_READ(SDEIMR
);
228 #define ibx_enable_display_interrupt(dev_priv, bits) \
229 ibx_display_interrupt_update((dev_priv), (bits), (bits))
230 #define ibx_disable_display_interrupt(dev_priv, bits) \
231 ibx_display_interrupt_update((dev_priv), (bits), 0)
233 static void ibx_set_fifo_underrun_reporting(struct drm_device
*dev
,
234 enum transcoder pch_transcoder
,
237 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
238 uint32_t bit
= (pch_transcoder
== TRANSCODER_A
) ?
239 SDE_TRANSA_FIFO_UNDER
: SDE_TRANSB_FIFO_UNDER
;
242 ibx_enable_display_interrupt(dev_priv
, bit
);
244 ibx_disable_display_interrupt(dev_priv
, bit
);
247 static void cpt_set_fifo_underrun_reporting(struct drm_device
*dev
,
248 enum transcoder pch_transcoder
,
251 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
255 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
));
257 if (!cpt_can_enable_serr_int(dev
))
260 ibx_enable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
262 uint32_t tmp
= I915_READ(SERR_INT
);
263 bool was_enabled
= !(I915_READ(SDEIMR
) & SDE_ERROR_CPT
);
265 /* Change the state _after_ we've read out the current one. */
266 ibx_disable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
269 (tmp
& SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
))) {
270 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
271 transcoder_name(pch_transcoder
));
277 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
280 * @enable: true if we want to report FIFO underrun errors, false otherwise
282 * This function makes us disable or enable CPU fifo underruns for a specific
283 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
284 * reporting for one pipe may also disable all the other CPU error interruts for
285 * the other pipes, due to the fact that there's just one interrupt mask/enable
286 * bit for all the pipes.
288 * Returns the previous state of underrun reporting.
290 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device
*dev
,
291 enum pipe pipe
, bool enable
)
293 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
294 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
295 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
299 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
301 ret
= !intel_crtc
->cpu_fifo_underrun_disabled
;
306 intel_crtc
->cpu_fifo_underrun_disabled
= !enable
;
308 if (IS_GEN5(dev
) || IS_GEN6(dev
))
309 ironlake_set_fifo_underrun_reporting(dev
, pipe
, enable
);
310 else if (IS_GEN7(dev
))
311 ivybridge_set_fifo_underrun_reporting(dev
, pipe
, enable
);
314 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
319 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
321 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
322 * @enable: true if we want to report FIFO underrun errors, false otherwise
324 * This function makes us disable or enable PCH fifo underruns for a specific
325 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
326 * underrun reporting for one transcoder may also disable all the other PCH
327 * error interruts for the other transcoders, due to the fact that there's just
328 * one interrupt mask/enable bit for all the transcoders.
330 * Returns the previous state of underrun reporting.
332 bool intel_set_pch_fifo_underrun_reporting(struct drm_device
*dev
,
333 enum transcoder pch_transcoder
,
336 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
337 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pch_transcoder
];
338 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
343 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
344 * has only one pch transcoder A that all pipes can use. To avoid racy
345 * pch transcoder -> pipe lookups from interrupt code simply store the
346 * underrun statistics in crtc A. Since we never expose this anywhere
347 * nor use it outside of the fifo underrun code here using the "wrong"
348 * crtc on LPT won't cause issues.
351 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
353 ret
= !intel_crtc
->pch_fifo_underrun_disabled
;
358 intel_crtc
->pch_fifo_underrun_disabled
= !enable
;
360 if (HAS_PCH_IBX(dev
))
361 ibx_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
363 cpt_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
366 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
372 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
374 u32 reg
= PIPESTAT(pipe
);
375 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
377 assert_spin_locked(&dev_priv
->irq_lock
);
379 if ((pipestat
& mask
) == mask
)
382 /* Enable the interrupt, clear any pending status */
383 pipestat
|= mask
| (mask
>> 16);
384 I915_WRITE(reg
, pipestat
);
389 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
391 u32 reg
= PIPESTAT(pipe
);
392 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
394 assert_spin_locked(&dev_priv
->irq_lock
);
396 if ((pipestat
& mask
) == 0)
400 I915_WRITE(reg
, pipestat
);
405 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
407 static void i915_enable_asle_pipestat(struct drm_device
*dev
)
409 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
410 unsigned long irqflags
;
412 if (!dev_priv
->opregion
.asle
|| !IS_MOBILE(dev
))
415 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
417 i915_enable_pipestat(dev_priv
, 1, PIPE_LEGACY_BLC_EVENT_ENABLE
);
418 if (INTEL_INFO(dev
)->gen
>= 4)
419 i915_enable_pipestat(dev_priv
, 0, PIPE_LEGACY_BLC_EVENT_ENABLE
);
421 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
425 * i915_pipe_enabled - check if a pipe is enabled
427 * @pipe: pipe to check
429 * Reading certain registers when the pipe is disabled can hang the chip.
430 * Use this routine to make sure the PLL is running and the pipe is active
431 * before reading such registers if unsure.
434 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
436 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
438 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
439 /* Locking is horribly broken here, but whatever. */
440 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
441 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
443 return intel_crtc
->active
;
445 return I915_READ(PIPECONF(pipe
)) & PIPECONF_ENABLE
;
449 /* Called from drm generic code, passed a 'crtc', which
450 * we use as a pipe index
452 static u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
454 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
455 unsigned long high_frame
;
456 unsigned long low_frame
;
457 u32 high1
, high2
, low
;
459 if (!i915_pipe_enabled(dev
, pipe
)) {
460 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
461 "pipe %c\n", pipe_name(pipe
));
465 high_frame
= PIPEFRAME(pipe
);
466 low_frame
= PIPEFRAMEPIXEL(pipe
);
469 * High & low register fields aren't synchronized, so make sure
470 * we get a low value that's stable across two reads of the high
474 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
475 low
= I915_READ(low_frame
) & PIPE_FRAME_LOW_MASK
;
476 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
477 } while (high1
!= high2
);
479 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
480 low
>>= PIPE_FRAME_LOW_SHIFT
;
481 return (high1
<< 8) | low
;
484 static u32
gm45_get_vblank_counter(struct drm_device
*dev
, int pipe
)
486 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
487 int reg
= PIPE_FRMCOUNT_GM45(pipe
);
489 if (!i915_pipe_enabled(dev
, pipe
)) {
490 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
491 "pipe %c\n", pipe_name(pipe
));
495 return I915_READ(reg
);
498 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, int pipe
,
499 int *vpos
, int *hpos
)
501 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
502 u32 vbl
= 0, position
= 0;
503 int vbl_start
, vbl_end
, htotal
, vtotal
;
506 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
509 if (!i915_pipe_enabled(dev
, pipe
)) {
510 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
511 "pipe %c\n", pipe_name(pipe
));
516 vtotal
= 1 + ((I915_READ(VTOTAL(cpu_transcoder
)) >> 16) & 0x1fff);
518 if (INTEL_INFO(dev
)->gen
>= 4) {
519 /* No obvious pixelcount register. Only query vertical
520 * scanout position from Display scan line register.
522 position
= I915_READ(PIPEDSL(pipe
));
524 /* Decode into vertical scanout position. Don't have
525 * horizontal scanout position.
527 *vpos
= position
& 0x1fff;
530 /* Have access to pixelcount since start of frame.
531 * We can split this into vertical and horizontal
534 position
= (I915_READ(PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
536 htotal
= 1 + ((I915_READ(HTOTAL(cpu_transcoder
)) >> 16) & 0x1fff);
537 *vpos
= position
/ htotal
;
538 *hpos
= position
- (*vpos
* htotal
);
541 /* Query vblank area. */
542 vbl
= I915_READ(VBLANK(cpu_transcoder
));
544 /* Test position against vblank region. */
545 vbl_start
= vbl
& 0x1fff;
546 vbl_end
= (vbl
>> 16) & 0x1fff;
548 if ((*vpos
< vbl_start
) || (*vpos
> vbl_end
))
551 /* Inside "upper part" of vblank area? Apply corrective offset: */
552 if (in_vbl
&& (*vpos
>= vbl_start
))
553 *vpos
= *vpos
- vtotal
;
555 /* Readouts valid? */
557 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
561 ret
|= DRM_SCANOUTPOS_INVBL
;
566 static int i915_get_vblank_timestamp(struct drm_device
*dev
, int pipe
,
568 struct timeval
*vblank_time
,
571 struct drm_crtc
*crtc
;
573 if (pipe
< 0 || pipe
>= INTEL_INFO(dev
)->num_pipes
) {
574 DRM_ERROR("Invalid crtc %d\n", pipe
);
578 /* Get drm_crtc to timestamp: */
579 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
581 DRM_ERROR("Invalid crtc %d\n", pipe
);
585 if (!crtc
->enabled
) {
586 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
590 /* Helper routine in DRM core does all the work: */
591 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
596 static int intel_hpd_irq_event(struct drm_device
*dev
, struct drm_connector
*connector
)
598 enum drm_connector_status old_status
;
600 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
601 old_status
= connector
->status
;
603 connector
->status
= connector
->funcs
->detect(connector
, false);
604 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
606 drm_get_connector_name(connector
),
607 old_status
, connector
->status
);
608 return (old_status
!= connector
->status
);
612 * Handle hotplug events outside the interrupt handler proper.
614 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
616 static void i915_hotplug_work_func(struct work_struct
*work
)
618 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
620 struct drm_device
*dev
= dev_priv
->dev
;
621 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
622 struct intel_connector
*intel_connector
;
623 struct intel_encoder
*intel_encoder
;
624 struct drm_connector
*connector
;
625 unsigned long irqflags
;
626 bool hpd_disabled
= false;
627 bool changed
= false;
630 /* HPD irq before everything is fully set up. */
631 if (!dev_priv
->enable_hotplug_processing
)
634 mutex_lock(&mode_config
->mutex
);
635 DRM_DEBUG_KMS("running encoder hotplug functions\n");
637 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
639 hpd_event_bits
= dev_priv
->hpd_event_bits
;
640 dev_priv
->hpd_event_bits
= 0;
641 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
642 intel_connector
= to_intel_connector(connector
);
643 intel_encoder
= intel_connector
->encoder
;
644 if (intel_encoder
->hpd_pin
> HPD_NONE
&&
645 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_MARK_DISABLED
&&
646 connector
->polled
== DRM_CONNECTOR_POLL_HPD
) {
647 DRM_INFO("HPD interrupt storm detected on connector %s: "
648 "switching from hotplug detection to polling\n",
649 drm_get_connector_name(connector
));
650 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
= HPD_DISABLED
;
651 connector
->polled
= DRM_CONNECTOR_POLL_CONNECT
652 | DRM_CONNECTOR_POLL_DISCONNECT
;
655 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
656 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
657 drm_get_connector_name(connector
), intel_encoder
->hpd_pin
);
660 /* if there were no outputs to poll, poll was disabled,
661 * therefore make sure it's enabled when disabling HPD on
664 drm_kms_helper_poll_enable(dev
);
665 mod_timer(&dev_priv
->hotplug_reenable_timer
,
666 jiffies
+ msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY
));
669 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
671 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
672 intel_connector
= to_intel_connector(connector
);
673 intel_encoder
= intel_connector
->encoder
;
674 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
675 if (intel_encoder
->hot_plug
)
676 intel_encoder
->hot_plug(intel_encoder
);
677 if (intel_hpd_irq_event(dev
, connector
))
681 mutex_unlock(&mode_config
->mutex
);
684 drm_kms_helper_hotplug_event(dev
);
687 static void ironlake_rps_change_irq_handler(struct drm_device
*dev
)
689 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
690 u32 busy_up
, busy_down
, max_avg
, min_avg
;
693 spin_lock(&mchdev_lock
);
695 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
697 new_delay
= dev_priv
->ips
.cur_delay
;
699 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
700 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
701 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
702 max_avg
= I915_READ(RCBMAXAVG
);
703 min_avg
= I915_READ(RCBMINAVG
);
705 /* Handle RCS change request from hw */
706 if (busy_up
> max_avg
) {
707 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
708 new_delay
= dev_priv
->ips
.cur_delay
- 1;
709 if (new_delay
< dev_priv
->ips
.max_delay
)
710 new_delay
= dev_priv
->ips
.max_delay
;
711 } else if (busy_down
< min_avg
) {
712 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
713 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
714 if (new_delay
> dev_priv
->ips
.min_delay
)
715 new_delay
= dev_priv
->ips
.min_delay
;
718 if (ironlake_set_drps(dev
, new_delay
))
719 dev_priv
->ips
.cur_delay
= new_delay
;
721 spin_unlock(&mchdev_lock
);
726 static void notify_ring(struct drm_device
*dev
,
727 struct intel_ring_buffer
*ring
)
729 if (ring
->obj
== NULL
)
732 trace_i915_gem_request_complete(ring
, ring
->get_seqno(ring
, false));
734 wake_up_all(&ring
->irq_queue
);
735 i915_queue_hangcheck(dev
);
738 static void gen6_pm_rps_work(struct work_struct
*work
)
740 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
745 spin_lock_irq(&dev_priv
->irq_lock
);
746 pm_iir
= dev_priv
->rps
.pm_iir
;
747 dev_priv
->rps
.pm_iir
= 0;
748 pm_imr
= I915_READ(GEN6_PMIMR
);
749 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
750 I915_WRITE(GEN6_PMIMR
, pm_imr
& ~GEN6_PM_RPS_EVENTS
);
751 spin_unlock_irq(&dev_priv
->irq_lock
);
753 if ((pm_iir
& GEN6_PM_RPS_EVENTS
) == 0)
756 mutex_lock(&dev_priv
->rps
.hw_lock
);
758 if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
) {
759 new_delay
= dev_priv
->rps
.cur_delay
+ 1;
762 * For better performance, jump directly
763 * to RPe if we're below it.
765 if (IS_VALLEYVIEW(dev_priv
->dev
) &&
766 dev_priv
->rps
.cur_delay
< dev_priv
->rps
.rpe_delay
)
767 new_delay
= dev_priv
->rps
.rpe_delay
;
769 new_delay
= dev_priv
->rps
.cur_delay
- 1;
771 /* sysfs frequency interfaces may have snuck in while servicing the
774 if (new_delay
>= dev_priv
->rps
.min_delay
&&
775 new_delay
<= dev_priv
->rps
.max_delay
) {
776 if (IS_VALLEYVIEW(dev_priv
->dev
))
777 valleyview_set_rps(dev_priv
->dev
, new_delay
);
779 gen6_set_rps(dev_priv
->dev
, new_delay
);
782 if (IS_VALLEYVIEW(dev_priv
->dev
)) {
784 * On VLV, when we enter RC6 we may not be at the minimum
785 * voltage level, so arm a timer to check. It should only
786 * fire when there's activity or once after we've entered
787 * RC6, and then won't be re-armed until the next RPS interrupt.
789 mod_delayed_work(dev_priv
->wq
, &dev_priv
->rps
.vlv_work
,
790 msecs_to_jiffies(100));
793 mutex_unlock(&dev_priv
->rps
.hw_lock
);
798 * ivybridge_parity_work - Workqueue called when a parity error interrupt
800 * @work: workqueue struct
802 * Doesn't actually do anything except notify userspace. As a consequence of
803 * this event, userspace should try to remap the bad rows since statistically
804 * it is likely the same row is more likely to go bad again.
806 static void ivybridge_parity_work(struct work_struct
*work
)
808 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
809 l3_parity
.error_work
);
810 u32 error_status
, row
, bank
, subbank
;
811 char *parity_event
[5];
815 /* We must turn off DOP level clock gating to access the L3 registers.
816 * In order to prevent a get/put style interface, acquire struct mutex
817 * any time we access those registers.
819 mutex_lock(&dev_priv
->dev
->struct_mutex
);
821 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
822 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
823 POSTING_READ(GEN7_MISCCPCTL
);
825 error_status
= I915_READ(GEN7_L3CDERRST1
);
826 row
= GEN7_PARITY_ERROR_ROW(error_status
);
827 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
828 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
830 I915_WRITE(GEN7_L3CDERRST1
, GEN7_PARITY_ERROR_VALID
|
831 GEN7_L3CDERRST1_ENABLE
);
832 POSTING_READ(GEN7_L3CDERRST1
);
834 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
836 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
837 ilk_enable_gt_irq(dev_priv
, GT_RENDER_L3_PARITY_ERROR_INTERRUPT
);
838 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
840 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
842 parity_event
[0] = I915_L3_PARITY_UEVENT
"=1";
843 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
844 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
845 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
846 parity_event
[4] = NULL
;
848 kobject_uevent_env(&dev_priv
->dev
->primary
->kdev
.kobj
,
849 KOBJ_CHANGE
, parity_event
);
851 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
854 kfree(parity_event
[3]);
855 kfree(parity_event
[2]);
856 kfree(parity_event
[1]);
859 static void ivybridge_parity_error_irq_handler(struct drm_device
*dev
)
861 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
863 if (!HAS_L3_GPU_CACHE(dev
))
866 spin_lock(&dev_priv
->irq_lock
);
867 ilk_disable_gt_irq(dev_priv
, GT_RENDER_L3_PARITY_ERROR_INTERRUPT
);
868 spin_unlock(&dev_priv
->irq_lock
);
870 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
873 static void ilk_gt_irq_handler(struct drm_device
*dev
,
874 struct drm_i915_private
*dev_priv
,
878 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
879 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
880 if (gt_iir
& ILK_BSD_USER_INTERRUPT
)
881 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
884 static void snb_gt_irq_handler(struct drm_device
*dev
,
885 struct drm_i915_private
*dev_priv
,
890 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
891 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
892 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
893 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
894 if (gt_iir
& GT_BLT_USER_INTERRUPT
)
895 notify_ring(dev
, &dev_priv
->ring
[BCS
]);
897 if (gt_iir
& (GT_BLT_CS_ERROR_INTERRUPT
|
898 GT_BSD_CS_ERROR_INTERRUPT
|
899 GT_RENDER_CS_MASTER_ERROR_INTERRUPT
)) {
900 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir
);
901 i915_handle_error(dev
, false);
904 if (gt_iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT
)
905 ivybridge_parity_error_irq_handler(dev
);
908 /* Legacy way of handling PM interrupts */
909 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
,
913 * IIR bits should never already be set because IMR should
914 * prevent an interrupt from being shown in IIR. The warning
915 * displays a case where we've unsafely cleared
916 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
917 * type is not a problem, it displays a problem in the logic.
919 * The mask bit in IMR is cleared by dev_priv->rps.work.
922 spin_lock(&dev_priv
->irq_lock
);
923 dev_priv
->rps
.pm_iir
|= pm_iir
;
924 I915_WRITE(GEN6_PMIMR
, dev_priv
->rps
.pm_iir
);
925 POSTING_READ(GEN6_PMIMR
);
926 spin_unlock(&dev_priv
->irq_lock
);
928 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
931 #define HPD_STORM_DETECT_PERIOD 1000
932 #define HPD_STORM_THRESHOLD 5
934 static inline void intel_hpd_irq_handler(struct drm_device
*dev
,
938 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
940 bool storm_detected
= false;
942 if (!hotplug_trigger
)
945 spin_lock(&dev_priv
->irq_lock
);
946 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
948 WARN(((hpd
[i
] & hotplug_trigger
) &&
949 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
),
950 "Received HPD interrupt although disabled\n");
952 if (!(hpd
[i
] & hotplug_trigger
) ||
953 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
)
956 dev_priv
->hpd_event_bits
|= (1 << i
);
957 if (!time_in_range(jiffies
, dev_priv
->hpd_stats
[i
].hpd_last_jiffies
,
958 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
959 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD
))) {
960 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
= jiffies
;
961 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
962 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i
);
963 } else if (dev_priv
->hpd_stats
[i
].hpd_cnt
> HPD_STORM_THRESHOLD
) {
964 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_MARK_DISABLED
;
965 dev_priv
->hpd_event_bits
&= ~(1 << i
);
966 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i
);
967 storm_detected
= true;
969 dev_priv
->hpd_stats
[i
].hpd_cnt
++;
970 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i
,
971 dev_priv
->hpd_stats
[i
].hpd_cnt
);
976 dev_priv
->display
.hpd_irq_setup(dev
);
977 spin_unlock(&dev_priv
->irq_lock
);
979 queue_work(dev_priv
->wq
,
980 &dev_priv
->hotplug_work
);
983 static void gmbus_irq_handler(struct drm_device
*dev
)
985 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
987 wake_up_all(&dev_priv
->gmbus_wait_queue
);
990 static void dp_aux_irq_handler(struct drm_device
*dev
)
992 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
994 wake_up_all(&dev_priv
->gmbus_wait_queue
);
997 /* Unlike gen6_rps_irq_handler() from which this function is originally derived,
998 * we must be able to deal with other PM interrupts. This is complicated because
999 * of the way in which we use the masks to defer the RPS work (which for
1000 * posterity is necessary because of forcewake).
1002 static void hsw_pm_irq_handler(struct drm_i915_private
*dev_priv
,
1005 if (pm_iir
& GEN6_PM_RPS_EVENTS
) {
1006 spin_lock(&dev_priv
->irq_lock
);
1007 dev_priv
->rps
.pm_iir
|= pm_iir
& GEN6_PM_RPS_EVENTS
;
1008 I915_WRITE(GEN6_PMIMR
, dev_priv
->rps
.pm_iir
);
1009 /* never want to mask useful interrupts. (also posting read) */
1010 WARN_ON(I915_READ_NOTRACE(GEN6_PMIMR
) & ~GEN6_PM_RPS_EVENTS
);
1011 spin_unlock(&dev_priv
->irq_lock
);
1013 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
1016 if (pm_iir
& PM_VEBOX_USER_INTERRUPT
)
1017 notify_ring(dev_priv
->dev
, &dev_priv
->ring
[VECS
]);
1019 if (pm_iir
& PM_VEBOX_CS_ERROR_INTERRUPT
) {
1020 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir
);
1021 i915_handle_error(dev_priv
->dev
, false);
1025 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
1027 struct drm_device
*dev
= (struct drm_device
*) arg
;
1028 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1029 u32 iir
, gt_iir
, pm_iir
;
1030 irqreturn_t ret
= IRQ_NONE
;
1031 unsigned long irqflags
;
1033 u32 pipe_stats
[I915_MAX_PIPES
];
1035 atomic_inc(&dev_priv
->irq_received
);
1038 iir
= I915_READ(VLV_IIR
);
1039 gt_iir
= I915_READ(GTIIR
);
1040 pm_iir
= I915_READ(GEN6_PMIIR
);
1042 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
1047 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1049 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1050 for_each_pipe(pipe
) {
1051 int reg
= PIPESTAT(pipe
);
1052 pipe_stats
[pipe
] = I915_READ(reg
);
1055 * Clear the PIPE*STAT regs before the IIR
1057 if (pipe_stats
[pipe
] & 0x8000ffff) {
1058 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
1059 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1061 I915_WRITE(reg
, pipe_stats
[pipe
]);
1064 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1066 for_each_pipe(pipe
) {
1067 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
)
1068 drm_handle_vblank(dev
, pipe
);
1070 if (pipe_stats
[pipe
] & PLANE_FLIPDONE_INT_STATUS_VLV
) {
1071 intel_prepare_page_flip(dev
, pipe
);
1072 intel_finish_page_flip(dev
, pipe
);
1076 /* Consume port. Then clear IIR or we'll miss events */
1077 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
1078 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1079 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
1081 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1084 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
1086 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1087 I915_READ(PORT_HOTPLUG_STAT
);
1090 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1091 gmbus_irq_handler(dev
);
1093 if (pm_iir
& GEN6_PM_RPS_EVENTS
)
1094 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1096 I915_WRITE(GTIIR
, gt_iir
);
1097 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1098 I915_WRITE(VLV_IIR
, iir
);
1105 static void ibx_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1107 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1109 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK
;
1111 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_ibx
);
1113 if (pch_iir
& SDE_AUDIO_POWER_MASK
) {
1114 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK
) >>
1115 SDE_AUDIO_POWER_SHIFT
);
1116 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1120 if (pch_iir
& SDE_AUX_MASK
)
1121 dp_aux_irq_handler(dev
);
1123 if (pch_iir
& SDE_GMBUS
)
1124 gmbus_irq_handler(dev
);
1126 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
1127 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1129 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
1130 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1132 if (pch_iir
& SDE_POISON
)
1133 DRM_ERROR("PCH poison interrupt\n");
1135 if (pch_iir
& SDE_FDI_MASK
)
1137 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1139 I915_READ(FDI_RX_IIR(pipe
)));
1141 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
1142 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1144 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
1145 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1147 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
1148 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1150 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1152 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
1153 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1155 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1158 static void ivb_err_int_handler(struct drm_device
*dev
)
1160 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1161 u32 err_int
= I915_READ(GEN7_ERR_INT
);
1163 if (err_int
& ERR_INT_POISON
)
1164 DRM_ERROR("Poison interrupt\n");
1166 if (err_int
& ERR_INT_FIFO_UNDERRUN_A
)
1167 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_A
, false))
1168 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1170 if (err_int
& ERR_INT_FIFO_UNDERRUN_B
)
1171 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_B
, false))
1172 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1174 if (err_int
& ERR_INT_FIFO_UNDERRUN_C
)
1175 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_C
, false))
1176 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1178 I915_WRITE(GEN7_ERR_INT
, err_int
);
1181 static void cpt_serr_int_handler(struct drm_device
*dev
)
1183 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1184 u32 serr_int
= I915_READ(SERR_INT
);
1186 if (serr_int
& SERR_INT_POISON
)
1187 DRM_ERROR("PCH poison interrupt\n");
1189 if (serr_int
& SERR_INT_TRANS_A_FIFO_UNDERRUN
)
1190 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1192 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1194 if (serr_int
& SERR_INT_TRANS_B_FIFO_UNDERRUN
)
1195 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1197 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1199 if (serr_int
& SERR_INT_TRANS_C_FIFO_UNDERRUN
)
1200 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_C
,
1202 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1204 I915_WRITE(SERR_INT
, serr_int
);
1207 static void cpt_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1209 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1211 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_CPT
;
1213 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_cpt
);
1215 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) {
1216 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
1217 SDE_AUDIO_POWER_SHIFT_CPT
);
1218 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1222 if (pch_iir
& SDE_AUX_MASK_CPT
)
1223 dp_aux_irq_handler(dev
);
1225 if (pch_iir
& SDE_GMBUS_CPT
)
1226 gmbus_irq_handler(dev
);
1228 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
1229 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1231 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
1232 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1234 if (pch_iir
& SDE_FDI_MASK_CPT
)
1236 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1238 I915_READ(FDI_RX_IIR(pipe
)));
1240 if (pch_iir
& SDE_ERROR_CPT
)
1241 cpt_serr_int_handler(dev
);
1244 static void ilk_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
1246 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1248 if (de_iir
& DE_AUX_CHANNEL_A
)
1249 dp_aux_irq_handler(dev
);
1251 if (de_iir
& DE_GSE
)
1252 intel_opregion_asle_intr(dev
);
1254 if (de_iir
& DE_PIPEA_VBLANK
)
1255 drm_handle_vblank(dev
, 0);
1257 if (de_iir
& DE_PIPEB_VBLANK
)
1258 drm_handle_vblank(dev
, 1);
1260 if (de_iir
& DE_POISON
)
1261 DRM_ERROR("Poison interrupt\n");
1263 if (de_iir
& DE_PIPEA_FIFO_UNDERRUN
)
1264 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_A
, false))
1265 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1267 if (de_iir
& DE_PIPEB_FIFO_UNDERRUN
)
1268 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_B
, false))
1269 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1271 if (de_iir
& DE_PLANEA_FLIP_DONE
) {
1272 intel_prepare_page_flip(dev
, 0);
1273 intel_finish_page_flip_plane(dev
, 0);
1276 if (de_iir
& DE_PLANEB_FLIP_DONE
) {
1277 intel_prepare_page_flip(dev
, 1);
1278 intel_finish_page_flip_plane(dev
, 1);
1281 /* check event from PCH */
1282 if (de_iir
& DE_PCH_EVENT
) {
1283 u32 pch_iir
= I915_READ(SDEIIR
);
1285 if (HAS_PCH_CPT(dev
))
1286 cpt_irq_handler(dev
, pch_iir
);
1288 ibx_irq_handler(dev
, pch_iir
);
1290 /* should clear PCH hotplug event before clear CPU irq */
1291 I915_WRITE(SDEIIR
, pch_iir
);
1294 if (IS_GEN5(dev
) && de_iir
& DE_PCU_EVENT
)
1295 ironlake_rps_change_irq_handler(dev
);
1298 static void ivb_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
1300 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1303 if (de_iir
& DE_ERR_INT_IVB
)
1304 ivb_err_int_handler(dev
);
1306 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
1307 dp_aux_irq_handler(dev
);
1309 if (de_iir
& DE_GSE_IVB
)
1310 intel_opregion_asle_intr(dev
);
1312 for (i
= 0; i
< 3; i
++) {
1313 if (de_iir
& (DE_PIPEA_VBLANK_IVB
<< (5 * i
)))
1314 drm_handle_vblank(dev
, i
);
1315 if (de_iir
& (DE_PLANEA_FLIP_DONE_IVB
<< (5 * i
))) {
1316 intel_prepare_page_flip(dev
, i
);
1317 intel_finish_page_flip_plane(dev
, i
);
1321 /* check event from PCH */
1322 if (!HAS_PCH_NOP(dev
) && (de_iir
& DE_PCH_EVENT_IVB
)) {
1323 u32 pch_iir
= I915_READ(SDEIIR
);
1325 cpt_irq_handler(dev
, pch_iir
);
1327 /* clear PCH hotplug event before clear CPU irq */
1328 I915_WRITE(SDEIIR
, pch_iir
);
1332 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
1334 struct drm_device
*dev
= (struct drm_device
*) arg
;
1335 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1336 u32 de_iir
, gt_iir
, de_ier
, sde_ier
= 0;
1337 irqreturn_t ret
= IRQ_NONE
;
1339 atomic_inc(&dev_priv
->irq_received
);
1341 /* We get interrupts on unclaimed registers, so check for this before we
1342 * do any I915_{READ,WRITE}. */
1343 intel_uncore_check_errors(dev
);
1345 /* disable master interrupt before clearing iir */
1346 de_ier
= I915_READ(DEIER
);
1347 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
1348 POSTING_READ(DEIER
);
1350 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1351 * interrupts will will be stored on its back queue, and then we'll be
1352 * able to process them after we restore SDEIER (as soon as we restore
1353 * it, we'll get an interrupt if SDEIIR still has something to process
1354 * due to its back queue). */
1355 if (!HAS_PCH_NOP(dev
)) {
1356 sde_ier
= I915_READ(SDEIER
);
1357 I915_WRITE(SDEIER
, 0);
1358 POSTING_READ(SDEIER
);
1361 /* On Haswell, also mask ERR_INT because we don't want to risk
1362 * generating "unclaimed register" interrupts from inside the interrupt
1364 if (IS_HASWELL(dev
)) {
1365 spin_lock(&dev_priv
->irq_lock
);
1366 ironlake_disable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
1367 spin_unlock(&dev_priv
->irq_lock
);
1370 gt_iir
= I915_READ(GTIIR
);
1372 if (INTEL_INFO(dev
)->gen
>= 6)
1373 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1375 ilk_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1376 I915_WRITE(GTIIR
, gt_iir
);
1380 de_iir
= I915_READ(DEIIR
);
1382 if (INTEL_INFO(dev
)->gen
>= 7)
1383 ivb_display_irq_handler(dev
, de_iir
);
1385 ilk_display_irq_handler(dev
, de_iir
);
1386 I915_WRITE(DEIIR
, de_iir
);
1390 if (INTEL_INFO(dev
)->gen
>= 6) {
1391 u32 pm_iir
= I915_READ(GEN6_PMIIR
);
1393 if (IS_HASWELL(dev
))
1394 hsw_pm_irq_handler(dev_priv
, pm_iir
);
1395 else if (pm_iir
& GEN6_PM_RPS_EVENTS
)
1396 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1397 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1402 if (IS_HASWELL(dev
)) {
1403 spin_lock(&dev_priv
->irq_lock
);
1404 if (ivb_can_enable_err_int(dev
))
1405 ironlake_enable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
1406 spin_unlock(&dev_priv
->irq_lock
);
1409 I915_WRITE(DEIER
, de_ier
);
1410 POSTING_READ(DEIER
);
1411 if (!HAS_PCH_NOP(dev
)) {
1412 I915_WRITE(SDEIER
, sde_ier
);
1413 POSTING_READ(SDEIER
);
1420 * i915_error_work_func - do process context error handling work
1421 * @work: work struct
1423 * Fire an error uevent so userspace can see that a hang or error
1426 static void i915_error_work_func(struct work_struct
*work
)
1428 struct i915_gpu_error
*error
= container_of(work
, struct i915_gpu_error
,
1430 drm_i915_private_t
*dev_priv
= container_of(error
, drm_i915_private_t
,
1432 struct drm_device
*dev
= dev_priv
->dev
;
1433 struct intel_ring_buffer
*ring
;
1434 char *error_event
[] = { I915_ERROR_UEVENT
"=1", NULL
};
1435 char *reset_event
[] = { I915_RESET_UEVENT
"=1", NULL
};
1436 char *reset_done_event
[] = { I915_ERROR_UEVENT
"=0", NULL
};
1439 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
, error_event
);
1442 * Note that there's only one work item which does gpu resets, so we
1443 * need not worry about concurrent gpu resets potentially incrementing
1444 * error->reset_counter twice. We only need to take care of another
1445 * racing irq/hangcheck declaring the gpu dead for a second time. A
1446 * quick check for that is good enough: schedule_work ensures the
1447 * correct ordering between hang detection and this work item, and since
1448 * the reset in-progress bit is only ever set by code outside of this
1449 * work we don't need to worry about any other races.
1451 if (i915_reset_in_progress(error
) && !i915_terminally_wedged(error
)) {
1452 DRM_DEBUG_DRIVER("resetting chip\n");
1453 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
,
1456 ret
= i915_reset(dev
);
1460 * After all the gem state is reset, increment the reset
1461 * counter and wake up everyone waiting for the reset to
1464 * Since unlock operations are a one-sided barrier only,
1465 * we need to insert a barrier here to order any seqno
1467 * the counter increment.
1469 smp_mb__before_atomic_inc();
1470 atomic_inc(&dev_priv
->gpu_error
.reset_counter
);
1472 kobject_uevent_env(&dev
->primary
->kdev
.kobj
,
1473 KOBJ_CHANGE
, reset_done_event
);
1475 atomic_set(&error
->reset_counter
, I915_WEDGED
);
1478 for_each_ring(ring
, dev_priv
, i
)
1479 wake_up_all(&ring
->irq_queue
);
1481 intel_display_handle_reset(dev
);
1483 wake_up_all(&dev_priv
->gpu_error
.reset_queue
);
1487 static void i915_report_and_clear_eir(struct drm_device
*dev
)
1489 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1490 uint32_t instdone
[I915_NUM_INSTDONE_REG
];
1491 u32 eir
= I915_READ(EIR
);
1497 pr_err("render error detected, EIR: 0x%08x\n", eir
);
1499 i915_get_extra_instdone(dev
, instdone
);
1502 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
1503 u32 ipeir
= I915_READ(IPEIR_I965
);
1505 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1506 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1507 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
1508 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
1509 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1510 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1511 I915_WRITE(IPEIR_I965
, ipeir
);
1512 POSTING_READ(IPEIR_I965
);
1514 if (eir
& GM45_ERROR_PAGE_TABLE
) {
1515 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1516 pr_err("page table error\n");
1517 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1518 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1519 POSTING_READ(PGTBL_ER
);
1523 if (!IS_GEN2(dev
)) {
1524 if (eir
& I915_ERROR_PAGE_TABLE
) {
1525 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1526 pr_err("page table error\n");
1527 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1528 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1529 POSTING_READ(PGTBL_ER
);
1533 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
1534 pr_err("memory refresh error:\n");
1536 pr_err("pipe %c stat: 0x%08x\n",
1537 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
1538 /* pipestat has already been acked */
1540 if (eir
& I915_ERROR_INSTRUCTION
) {
1541 pr_err("instruction error\n");
1542 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
1543 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
1544 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
1545 if (INTEL_INFO(dev
)->gen
< 4) {
1546 u32 ipeir
= I915_READ(IPEIR
);
1548 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
1549 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
1550 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
1551 I915_WRITE(IPEIR
, ipeir
);
1552 POSTING_READ(IPEIR
);
1554 u32 ipeir
= I915_READ(IPEIR_I965
);
1556 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1557 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1558 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1559 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1560 I915_WRITE(IPEIR_I965
, ipeir
);
1561 POSTING_READ(IPEIR_I965
);
1565 I915_WRITE(EIR
, eir
);
1567 eir
= I915_READ(EIR
);
1570 * some errors might have become stuck,
1573 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
1574 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
1575 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
1580 * i915_handle_error - handle an error interrupt
1583 * Do some basic checking of regsiter state at error interrupt time and
1584 * dump it to the syslog. Also call i915_capture_error_state() to make
1585 * sure we get a record and make it available in debugfs. Fire a uevent
1586 * so userspace knows something bad happened (should trigger collection
1587 * of a ring dump etc.).
1589 void i915_handle_error(struct drm_device
*dev
, bool wedged
)
1591 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1592 struct intel_ring_buffer
*ring
;
1595 i915_capture_error_state(dev
);
1596 i915_report_and_clear_eir(dev
);
1599 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG
,
1600 &dev_priv
->gpu_error
.reset_counter
);
1603 * Wakeup waiting processes so that the reset work item
1604 * doesn't deadlock trying to grab various locks.
1606 for_each_ring(ring
, dev_priv
, i
)
1607 wake_up_all(&ring
->irq_queue
);
1610 queue_work(dev_priv
->wq
, &dev_priv
->gpu_error
.work
);
1613 static void __always_unused
i915_pageflip_stall_check(struct drm_device
*dev
, int pipe
)
1615 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1616 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1617 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1618 struct drm_i915_gem_object
*obj
;
1619 struct intel_unpin_work
*work
;
1620 unsigned long flags
;
1621 bool stall_detected
;
1623 /* Ignore early vblank irqs */
1624 if (intel_crtc
== NULL
)
1627 spin_lock_irqsave(&dev
->event_lock
, flags
);
1628 work
= intel_crtc
->unpin_work
;
1631 atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
||
1632 !work
->enable_stall_check
) {
1633 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1634 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1638 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1639 obj
= work
->pending_flip_obj
;
1640 if (INTEL_INFO(dev
)->gen
>= 4) {
1641 int dspsurf
= DSPSURF(intel_crtc
->plane
);
1642 stall_detected
= I915_HI_DISPBASE(I915_READ(dspsurf
)) ==
1643 i915_gem_obj_ggtt_offset(obj
);
1645 int dspaddr
= DSPADDR(intel_crtc
->plane
);
1646 stall_detected
= I915_READ(dspaddr
) == (i915_gem_obj_ggtt_offset(obj
) +
1647 crtc
->y
* crtc
->fb
->pitches
[0] +
1648 crtc
->x
* crtc
->fb
->bits_per_pixel
/8);
1651 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1653 if (stall_detected
) {
1654 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1655 intel_prepare_page_flip(dev
, intel_crtc
->plane
);
1659 /* Called from drm generic code, passed 'crtc' which
1660 * we use as a pipe index
1662 static int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
1664 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1665 unsigned long irqflags
;
1667 if (!i915_pipe_enabled(dev
, pipe
))
1670 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1671 if (INTEL_INFO(dev
)->gen
>= 4)
1672 i915_enable_pipestat(dev_priv
, pipe
,
1673 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1675 i915_enable_pipestat(dev_priv
, pipe
,
1676 PIPE_VBLANK_INTERRUPT_ENABLE
);
1678 /* maintain vblank delivery even in deep C-states */
1679 if (dev_priv
->info
->gen
== 3)
1680 I915_WRITE(INSTPM
, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS
));
1681 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1686 static int ironlake_enable_vblank(struct drm_device
*dev
, int pipe
)
1688 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1689 unsigned long irqflags
;
1690 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
1691 DE_PIPE_VBLANK_ILK(pipe
);
1693 if (!i915_pipe_enabled(dev
, pipe
))
1696 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1697 ironlake_enable_display_irq(dev_priv
, bit
);
1698 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1703 static int valleyview_enable_vblank(struct drm_device
*dev
, int pipe
)
1705 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1706 unsigned long irqflags
;
1709 if (!i915_pipe_enabled(dev
, pipe
))
1712 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1713 imr
= I915_READ(VLV_IMR
);
1715 imr
&= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
1717 imr
&= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1718 I915_WRITE(VLV_IMR
, imr
);
1719 i915_enable_pipestat(dev_priv
, pipe
,
1720 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1721 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1726 /* Called from drm generic code, passed 'crtc' which
1727 * we use as a pipe index
1729 static void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
1731 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1732 unsigned long irqflags
;
1734 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1735 if (dev_priv
->info
->gen
== 3)
1736 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS
));
1738 i915_disable_pipestat(dev_priv
, pipe
,
1739 PIPE_VBLANK_INTERRUPT_ENABLE
|
1740 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1741 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1744 static void ironlake_disable_vblank(struct drm_device
*dev
, int pipe
)
1746 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1747 unsigned long irqflags
;
1748 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
1749 DE_PIPE_VBLANK_ILK(pipe
);
1751 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1752 ironlake_disable_display_irq(dev_priv
, bit
);
1753 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1756 static void valleyview_disable_vblank(struct drm_device
*dev
, int pipe
)
1758 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1759 unsigned long irqflags
;
1762 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1763 i915_disable_pipestat(dev_priv
, pipe
,
1764 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1765 imr
= I915_READ(VLV_IMR
);
1767 imr
|= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
1769 imr
|= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1770 I915_WRITE(VLV_IMR
, imr
);
1771 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1775 ring_last_seqno(struct intel_ring_buffer
*ring
)
1777 return list_entry(ring
->request_list
.prev
,
1778 struct drm_i915_gem_request
, list
)->seqno
;
1782 ring_idle(struct intel_ring_buffer
*ring
, u32 seqno
)
1784 return (list_empty(&ring
->request_list
) ||
1785 i915_seqno_passed(seqno
, ring_last_seqno(ring
)));
1788 static struct intel_ring_buffer
*
1789 semaphore_waits_for(struct intel_ring_buffer
*ring
, u32
*seqno
)
1791 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1792 u32 cmd
, ipehr
, acthd
, acthd_min
;
1794 ipehr
= I915_READ(RING_IPEHR(ring
->mmio_base
));
1795 if ((ipehr
& ~(0x3 << 16)) !=
1796 (MI_SEMAPHORE_MBOX
| MI_SEMAPHORE_COMPARE
| MI_SEMAPHORE_REGISTER
))
1799 /* ACTHD is likely pointing to the dword after the actual command,
1800 * so scan backwards until we find the MBOX.
1802 acthd
= intel_ring_get_active_head(ring
) & HEAD_ADDR
;
1803 acthd_min
= max((int)acthd
- 3 * 4, 0);
1805 cmd
= ioread32(ring
->virtual_start
+ acthd
);
1810 if (acthd
< acthd_min
)
1814 *seqno
= ioread32(ring
->virtual_start
+acthd
+4)+1;
1815 return &dev_priv
->ring
[(ring
->id
+ (((ipehr
>> 17) & 1) + 1)) % 3];
1818 static int semaphore_passed(struct intel_ring_buffer
*ring
)
1820 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1821 struct intel_ring_buffer
*signaller
;
1824 ring
->hangcheck
.deadlock
= true;
1826 signaller
= semaphore_waits_for(ring
, &seqno
);
1827 if (signaller
== NULL
|| signaller
->hangcheck
.deadlock
)
1830 /* cursory check for an unkickable deadlock */
1831 ctl
= I915_READ_CTL(signaller
);
1832 if (ctl
& RING_WAIT_SEMAPHORE
&& semaphore_passed(signaller
) < 0)
1835 return i915_seqno_passed(signaller
->get_seqno(signaller
, false), seqno
);
1838 static void semaphore_clear_deadlocks(struct drm_i915_private
*dev_priv
)
1840 struct intel_ring_buffer
*ring
;
1843 for_each_ring(ring
, dev_priv
, i
)
1844 ring
->hangcheck
.deadlock
= false;
1847 static enum intel_ring_hangcheck_action
1848 ring_stuck(struct intel_ring_buffer
*ring
, u32 acthd
)
1850 struct drm_device
*dev
= ring
->dev
;
1851 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1854 if (ring
->hangcheck
.acthd
!= acthd
)
1855 return HANGCHECK_ACTIVE
;
1858 return HANGCHECK_HUNG
;
1860 /* Is the chip hanging on a WAIT_FOR_EVENT?
1861 * If so we can simply poke the RB_WAIT bit
1862 * and break the hang. This should work on
1863 * all but the second generation chipsets.
1865 tmp
= I915_READ_CTL(ring
);
1866 if (tmp
& RING_WAIT
) {
1867 DRM_ERROR("Kicking stuck wait on %s\n",
1869 I915_WRITE_CTL(ring
, tmp
);
1870 return HANGCHECK_KICK
;
1873 if (INTEL_INFO(dev
)->gen
>= 6 && tmp
& RING_WAIT_SEMAPHORE
) {
1874 switch (semaphore_passed(ring
)) {
1876 return HANGCHECK_HUNG
;
1878 DRM_ERROR("Kicking stuck semaphore on %s\n",
1880 I915_WRITE_CTL(ring
, tmp
);
1881 return HANGCHECK_KICK
;
1883 return HANGCHECK_WAIT
;
1887 return HANGCHECK_HUNG
;
1891 * This is called when the chip hasn't reported back with completed
1892 * batchbuffers in a long time. We keep track per ring seqno progress and
1893 * if there are no progress, hangcheck score for that ring is increased.
1894 * Further, acthd is inspected to see if the ring is stuck. On stuck case
1895 * we kick the ring. If we see no progress on three subsequent calls
1896 * we assume chip is wedged and try to fix it by resetting the chip.
1898 static void i915_hangcheck_elapsed(unsigned long data
)
1900 struct drm_device
*dev
= (struct drm_device
*)data
;
1901 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1902 struct intel_ring_buffer
*ring
;
1904 int busy_count
= 0, rings_hung
= 0;
1905 bool stuck
[I915_NUM_RINGS
] = { 0 };
1911 if (!i915_enable_hangcheck
)
1914 for_each_ring(ring
, dev_priv
, i
) {
1918 semaphore_clear_deadlocks(dev_priv
);
1920 seqno
= ring
->get_seqno(ring
, false);
1921 acthd
= intel_ring_get_active_head(ring
);
1923 if (ring
->hangcheck
.seqno
== seqno
) {
1924 if (ring_idle(ring
, seqno
)) {
1925 if (waitqueue_active(&ring
->irq_queue
)) {
1926 /* Issue a wake-up to catch stuck h/w. */
1927 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1929 wake_up_all(&ring
->irq_queue
);
1930 ring
->hangcheck
.score
+= HUNG
;
1934 /* We always increment the hangcheck score
1935 * if the ring is busy and still processing
1936 * the same request, so that no single request
1937 * can run indefinitely (such as a chain of
1938 * batches). The only time we do not increment
1939 * the hangcheck score on this ring, if this
1940 * ring is in a legitimate wait for another
1941 * ring. In that case the waiting ring is a
1942 * victim and we want to be sure we catch the
1943 * right culprit. Then every time we do kick
1944 * the ring, add a small increment to the
1945 * score so that we can catch a batch that is
1946 * being repeatedly kicked and so responsible
1947 * for stalling the machine.
1949 ring
->hangcheck
.action
= ring_stuck(ring
,
1952 switch (ring
->hangcheck
.action
) {
1953 case HANGCHECK_WAIT
:
1955 case HANGCHECK_ACTIVE
:
1956 ring
->hangcheck
.score
+= BUSY
;
1958 case HANGCHECK_KICK
:
1959 ring
->hangcheck
.score
+= KICK
;
1961 case HANGCHECK_HUNG
:
1962 ring
->hangcheck
.score
+= HUNG
;
1968 /* Gradually reduce the count so that we catch DoS
1969 * attempts across multiple batches.
1971 if (ring
->hangcheck
.score
> 0)
1972 ring
->hangcheck
.score
--;
1975 ring
->hangcheck
.seqno
= seqno
;
1976 ring
->hangcheck
.acthd
= acthd
;
1980 for_each_ring(ring
, dev_priv
, i
) {
1981 if (ring
->hangcheck
.score
> FIRE
) {
1982 DRM_ERROR("%s on %s\n",
1983 stuck
[i
] ? "stuck" : "no progress",
1990 return i915_handle_error(dev
, true);
1993 /* Reset timer case chip hangs without another request
1995 i915_queue_hangcheck(dev
);
1998 void i915_queue_hangcheck(struct drm_device
*dev
)
2000 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2001 if (!i915_enable_hangcheck
)
2004 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
2005 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
2008 static void ibx_irq_preinstall(struct drm_device
*dev
)
2010 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2012 if (HAS_PCH_NOP(dev
))
2015 /* south display irq */
2016 I915_WRITE(SDEIMR
, 0xffffffff);
2018 * SDEIER is also touched by the interrupt handler to work around missed
2019 * PCH interrupts. Hence we can't update it after the interrupt handler
2020 * is enabled - instead we unconditionally enable all PCH interrupt
2021 * sources here, but then only unmask them as needed with SDEIMR.
2023 I915_WRITE(SDEIER
, 0xffffffff);
2024 POSTING_READ(SDEIER
);
2027 static void gen5_gt_irq_preinstall(struct drm_device
*dev
)
2029 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2032 I915_WRITE(GTIMR
, 0xffffffff);
2033 I915_WRITE(GTIER
, 0x0);
2034 POSTING_READ(GTIER
);
2036 if (INTEL_INFO(dev
)->gen
>= 6) {
2038 I915_WRITE(GEN6_PMIMR
, 0xffffffff);
2039 I915_WRITE(GEN6_PMIER
, 0x0);
2040 POSTING_READ(GEN6_PMIER
);
2046 static void ironlake_irq_preinstall(struct drm_device
*dev
)
2048 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2050 atomic_set(&dev_priv
->irq_received
, 0);
2052 I915_WRITE(HWSTAM
, 0xeffe);
2054 I915_WRITE(DEIMR
, 0xffffffff);
2055 I915_WRITE(DEIER
, 0x0);
2056 POSTING_READ(DEIER
);
2058 gen5_gt_irq_preinstall(dev
);
2060 ibx_irq_preinstall(dev
);
2063 static void valleyview_irq_preinstall(struct drm_device
*dev
)
2065 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2068 atomic_set(&dev_priv
->irq_received
, 0);
2071 I915_WRITE(VLV_IMR
, 0);
2072 I915_WRITE(RING_IMR(RENDER_RING_BASE
), 0);
2073 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE
), 0);
2074 I915_WRITE(RING_IMR(BLT_RING_BASE
), 0);
2077 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2078 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2080 gen5_gt_irq_preinstall(dev
);
2082 I915_WRITE(DPINVGTT
, 0xff);
2084 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2085 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2087 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2088 I915_WRITE(VLV_IIR
, 0xffffffff);
2089 I915_WRITE(VLV_IMR
, 0xffffffff);
2090 I915_WRITE(VLV_IER
, 0x0);
2091 POSTING_READ(VLV_IER
);
2094 static void ibx_hpd_irq_setup(struct drm_device
*dev
)
2096 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2097 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2098 struct intel_encoder
*intel_encoder
;
2099 u32 hotplug_irqs
, hotplug
, enabled_irqs
= 0;
2101 if (HAS_PCH_IBX(dev
)) {
2102 hotplug_irqs
= SDE_HOTPLUG_MASK
;
2103 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2104 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2105 enabled_irqs
|= hpd_ibx
[intel_encoder
->hpd_pin
];
2107 hotplug_irqs
= SDE_HOTPLUG_MASK_CPT
;
2108 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2109 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2110 enabled_irqs
|= hpd_cpt
[intel_encoder
->hpd_pin
];
2113 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
2116 * Enable digital hotplug on the PCH, and configure the DP short pulse
2117 * duration to 2ms (which is the minimum in the Display Port spec)
2119 * This register is the same on all known PCH chips.
2121 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
2122 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
2123 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
2124 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
2125 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
2126 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
2129 static void ibx_irq_postinstall(struct drm_device
*dev
)
2131 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2134 if (HAS_PCH_NOP(dev
))
2137 if (HAS_PCH_IBX(dev
)) {
2138 mask
= SDE_GMBUS
| SDE_AUX_MASK
| SDE_TRANSB_FIFO_UNDER
|
2139 SDE_TRANSA_FIFO_UNDER
| SDE_POISON
;
2141 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
| SDE_ERROR_CPT
;
2143 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2146 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2147 I915_WRITE(SDEIMR
, ~mask
);
2150 static void gen5_gt_irq_postinstall(struct drm_device
*dev
)
2152 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2153 u32 pm_irqs
, gt_irqs
;
2155 pm_irqs
= gt_irqs
= 0;
2157 dev_priv
->gt_irq_mask
= ~0;
2158 if (HAS_L3_GPU_CACHE(dev
)) {
2159 /* L3 parity interrupt is always unmasked. */
2160 dev_priv
->gt_irq_mask
= ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
2161 gt_irqs
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
2164 gt_irqs
|= GT_RENDER_USER_INTERRUPT
;
2166 gt_irqs
|= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
|
2167 ILK_BSD_USER_INTERRUPT
;
2169 gt_irqs
|= GT_BLT_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
;
2172 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2173 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
2174 I915_WRITE(GTIER
, gt_irqs
);
2175 POSTING_READ(GTIER
);
2177 if (INTEL_INFO(dev
)->gen
>= 6) {
2178 pm_irqs
|= GEN6_PM_RPS_EVENTS
;
2181 pm_irqs
|= PM_VEBOX_USER_INTERRUPT
;
2183 I915_WRITE(GEN6_PMIIR
, I915_READ(GEN6_PMIIR
));
2184 I915_WRITE(GEN6_PMIMR
, 0xffffffff);
2185 I915_WRITE(GEN6_PMIER
, pm_irqs
);
2186 POSTING_READ(GEN6_PMIER
);
2190 static int ironlake_irq_postinstall(struct drm_device
*dev
)
2192 unsigned long irqflags
;
2193 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2194 u32 display_mask
, extra_mask
;
2196 if (INTEL_INFO(dev
)->gen
>= 7) {
2197 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
|
2198 DE_PCH_EVENT_IVB
| DE_PLANEC_FLIP_DONE_IVB
|
2199 DE_PLANEB_FLIP_DONE_IVB
|
2200 DE_PLANEA_FLIP_DONE_IVB
| DE_AUX_CHANNEL_A_IVB
|
2202 extra_mask
= (DE_PIPEC_VBLANK_IVB
| DE_PIPEB_VBLANK_IVB
|
2203 DE_PIPEA_VBLANK_IVB
);
2205 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2207 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
2208 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
|
2209 DE_AUX_CHANNEL_A
| DE_PIPEB_FIFO_UNDERRUN
|
2210 DE_PIPEA_FIFO_UNDERRUN
| DE_POISON
);
2211 extra_mask
= DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
| DE_PCU_EVENT
;
2214 dev_priv
->irq_mask
= ~display_mask
;
2216 /* should always can generate irq */
2217 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2218 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
2219 I915_WRITE(DEIER
, display_mask
| extra_mask
);
2220 POSTING_READ(DEIER
);
2222 gen5_gt_irq_postinstall(dev
);
2224 ibx_irq_postinstall(dev
);
2226 if (IS_IRONLAKE_M(dev
)) {
2227 /* Enable PCU event interrupts
2229 * spinlocking not required here for correctness since interrupt
2230 * setup is guaranteed to run in single-threaded context. But we
2231 * need it to make the assert_spin_locked happy. */
2232 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2233 ironlake_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
2234 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2240 static int valleyview_irq_postinstall(struct drm_device
*dev
)
2242 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2244 u32 pipestat_enable
= PLANE_FLIP_DONE_INT_EN_VLV
;
2245 unsigned long irqflags
;
2247 enable_mask
= I915_DISPLAY_PORT_INTERRUPT
;
2248 enable_mask
|= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2249 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2250 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2251 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2254 *Leave vblank interrupts masked initially. enable/disable will
2255 * toggle them based on usage.
2257 dev_priv
->irq_mask
= (~enable_mask
) |
2258 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2259 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2261 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2262 POSTING_READ(PORT_HOTPLUG_EN
);
2264 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
2265 I915_WRITE(VLV_IER
, enable_mask
);
2266 I915_WRITE(VLV_IIR
, 0xffffffff);
2267 I915_WRITE(PIPESTAT(0), 0xffff);
2268 I915_WRITE(PIPESTAT(1), 0xffff);
2269 POSTING_READ(VLV_IER
);
2271 /* Interrupt setup is already guaranteed to be single-threaded, this is
2272 * just to make the assert_spin_locked check happy. */
2273 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2274 i915_enable_pipestat(dev_priv
, 0, pipestat_enable
);
2275 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
2276 i915_enable_pipestat(dev_priv
, 1, pipestat_enable
);
2277 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2279 I915_WRITE(VLV_IIR
, 0xffffffff);
2280 I915_WRITE(VLV_IIR
, 0xffffffff);
2282 gen5_gt_irq_postinstall(dev
);
2284 /* ack & enable invalid PTE error interrupts */
2285 #if 0 /* FIXME: add support to irq handler for checking these bits */
2286 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
2287 I915_WRITE(DPINVGTT
, DPINVGTT_EN_MASK
);
2290 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
2295 static void valleyview_irq_uninstall(struct drm_device
*dev
)
2297 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2303 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2306 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2308 I915_WRITE(HWSTAM
, 0xffffffff);
2309 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2310 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2312 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2313 I915_WRITE(VLV_IIR
, 0xffffffff);
2314 I915_WRITE(VLV_IMR
, 0xffffffff);
2315 I915_WRITE(VLV_IER
, 0x0);
2316 POSTING_READ(VLV_IER
);
2319 static void ironlake_irq_uninstall(struct drm_device
*dev
)
2321 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2326 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2328 I915_WRITE(HWSTAM
, 0xffffffff);
2330 I915_WRITE(DEIMR
, 0xffffffff);
2331 I915_WRITE(DEIER
, 0x0);
2332 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2334 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2336 I915_WRITE(GTIMR
, 0xffffffff);
2337 I915_WRITE(GTIER
, 0x0);
2338 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2340 if (HAS_PCH_NOP(dev
))
2343 I915_WRITE(SDEIMR
, 0xffffffff);
2344 I915_WRITE(SDEIER
, 0x0);
2345 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2346 if (HAS_PCH_CPT(dev
) || HAS_PCH_LPT(dev
))
2347 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2350 static void i8xx_irq_preinstall(struct drm_device
* dev
)
2352 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2355 atomic_set(&dev_priv
->irq_received
, 0);
2358 I915_WRITE(PIPESTAT(pipe
), 0);
2359 I915_WRITE16(IMR
, 0xffff);
2360 I915_WRITE16(IER
, 0x0);
2361 POSTING_READ16(IER
);
2364 static int i8xx_irq_postinstall(struct drm_device
*dev
)
2366 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2369 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2371 /* Unmask the interrupts that we always want on. */
2372 dev_priv
->irq_mask
=
2373 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2374 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2375 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2376 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2377 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2378 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
2381 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2382 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2383 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2384 I915_USER_INTERRUPT
);
2385 POSTING_READ16(IER
);
2391 * Returns true when a page flip has completed.
2393 static bool i8xx_handle_vblank(struct drm_device
*dev
,
2396 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2397 u16 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(pipe
);
2399 if (!drm_handle_vblank(dev
, pipe
))
2402 if ((iir
& flip_pending
) == 0)
2405 intel_prepare_page_flip(dev
, pipe
);
2407 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2408 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2409 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2410 * the flip is completed (no longer pending). Since this doesn't raise
2411 * an interrupt per se, we watch for the change at vblank.
2413 if (I915_READ16(ISR
) & flip_pending
)
2416 intel_finish_page_flip(dev
, pipe
);
2421 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
2423 struct drm_device
*dev
= (struct drm_device
*) arg
;
2424 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2427 unsigned long irqflags
;
2430 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2431 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2433 atomic_inc(&dev_priv
->irq_received
);
2435 iir
= I915_READ16(IIR
);
2439 while (iir
& ~flip_mask
) {
2440 /* Can't rely on pipestat interrupt bit in iir as it might
2441 * have been cleared after the pipestat interrupt was received.
2442 * It doesn't set the bit in iir again, but it still produces
2443 * interrupts (for non-MSI).
2445 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2446 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2447 i915_handle_error(dev
, false);
2449 for_each_pipe(pipe
) {
2450 int reg
= PIPESTAT(pipe
);
2451 pipe_stats
[pipe
] = I915_READ(reg
);
2454 * Clear the PIPE*STAT regs before the IIR
2456 if (pipe_stats
[pipe
] & 0x8000ffff) {
2457 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2458 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2460 I915_WRITE(reg
, pipe_stats
[pipe
]);
2463 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2465 I915_WRITE16(IIR
, iir
& ~flip_mask
);
2466 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
2468 i915_update_dri1_breadcrumb(dev
);
2470 if (iir
& I915_USER_INTERRUPT
)
2471 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2473 if (pipe_stats
[0] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2474 i8xx_handle_vblank(dev
, 0, iir
))
2475 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(0);
2477 if (pipe_stats
[1] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2478 i8xx_handle_vblank(dev
, 1, iir
))
2479 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(1);
2487 static void i8xx_irq_uninstall(struct drm_device
* dev
)
2489 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2492 for_each_pipe(pipe
) {
2493 /* Clear enable bits; then clear status bits */
2494 I915_WRITE(PIPESTAT(pipe
), 0);
2495 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
2497 I915_WRITE16(IMR
, 0xffff);
2498 I915_WRITE16(IER
, 0x0);
2499 I915_WRITE16(IIR
, I915_READ16(IIR
));
2502 static void i915_irq_preinstall(struct drm_device
* dev
)
2504 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2507 atomic_set(&dev_priv
->irq_received
, 0);
2509 if (I915_HAS_HOTPLUG(dev
)) {
2510 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2511 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2514 I915_WRITE16(HWSTAM
, 0xeffe);
2516 I915_WRITE(PIPESTAT(pipe
), 0);
2517 I915_WRITE(IMR
, 0xffffffff);
2518 I915_WRITE(IER
, 0x0);
2522 static int i915_irq_postinstall(struct drm_device
*dev
)
2524 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2527 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2529 /* Unmask the interrupts that we always want on. */
2530 dev_priv
->irq_mask
=
2531 ~(I915_ASLE_INTERRUPT
|
2532 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2533 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2534 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2535 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2536 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2539 I915_ASLE_INTERRUPT
|
2540 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2541 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2542 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2543 I915_USER_INTERRUPT
;
2545 if (I915_HAS_HOTPLUG(dev
)) {
2546 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2547 POSTING_READ(PORT_HOTPLUG_EN
);
2549 /* Enable in IER... */
2550 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
2551 /* and unmask in IMR */
2552 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
2555 I915_WRITE(IMR
, dev_priv
->irq_mask
);
2556 I915_WRITE(IER
, enable_mask
);
2559 i915_enable_asle_pipestat(dev
);
2565 * Returns true when a page flip has completed.
2567 static bool i915_handle_vblank(struct drm_device
*dev
,
2568 int plane
, int pipe
, u32 iir
)
2570 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2571 u32 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
2573 if (!drm_handle_vblank(dev
, pipe
))
2576 if ((iir
& flip_pending
) == 0)
2579 intel_prepare_page_flip(dev
, plane
);
2581 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2582 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2583 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2584 * the flip is completed (no longer pending). Since this doesn't raise
2585 * an interrupt per se, we watch for the change at vblank.
2587 if (I915_READ(ISR
) & flip_pending
)
2590 intel_finish_page_flip(dev
, pipe
);
2595 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
2597 struct drm_device
*dev
= (struct drm_device
*) arg
;
2598 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2599 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
2600 unsigned long irqflags
;
2602 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2603 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2604 int pipe
, ret
= IRQ_NONE
;
2606 atomic_inc(&dev_priv
->irq_received
);
2608 iir
= I915_READ(IIR
);
2610 bool irq_received
= (iir
& ~flip_mask
) != 0;
2611 bool blc_event
= false;
2613 /* Can't rely on pipestat interrupt bit in iir as it might
2614 * have been cleared after the pipestat interrupt was received.
2615 * It doesn't set the bit in iir again, but it still produces
2616 * interrupts (for non-MSI).
2618 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2619 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2620 i915_handle_error(dev
, false);
2622 for_each_pipe(pipe
) {
2623 int reg
= PIPESTAT(pipe
);
2624 pipe_stats
[pipe
] = I915_READ(reg
);
2626 /* Clear the PIPE*STAT regs before the IIR */
2627 if (pipe_stats
[pipe
] & 0x8000ffff) {
2628 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2629 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2631 I915_WRITE(reg
, pipe_stats
[pipe
]);
2632 irq_received
= true;
2635 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2640 /* Consume port. Then clear IIR or we'll miss events */
2641 if ((I915_HAS_HOTPLUG(dev
)) &&
2642 (iir
& I915_DISPLAY_PORT_INTERRUPT
)) {
2643 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
2644 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
2646 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2649 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
2651 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
2652 POSTING_READ(PORT_HOTPLUG_STAT
);
2655 I915_WRITE(IIR
, iir
& ~flip_mask
);
2656 new_iir
= I915_READ(IIR
); /* Flush posted writes */
2658 if (iir
& I915_USER_INTERRUPT
)
2659 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2661 for_each_pipe(pipe
) {
2666 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2667 i915_handle_vblank(dev
, plane
, pipe
, iir
))
2668 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
2670 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
2674 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
2675 intel_opregion_asle_intr(dev
);
2677 /* With MSI, interrupts are only generated when iir
2678 * transitions from zero to nonzero. If another bit got
2679 * set while we were handling the existing iir bits, then
2680 * we would never get another interrupt.
2682 * This is fine on non-MSI as well, as if we hit this path
2683 * we avoid exiting the interrupt handler only to generate
2686 * Note that for MSI this could cause a stray interrupt report
2687 * if an interrupt landed in the time between writing IIR and
2688 * the posting read. This should be rare enough to never
2689 * trigger the 99% of 100,000 interrupts test for disabling
2694 } while (iir
& ~flip_mask
);
2696 i915_update_dri1_breadcrumb(dev
);
2701 static void i915_irq_uninstall(struct drm_device
* dev
)
2703 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2706 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2708 if (I915_HAS_HOTPLUG(dev
)) {
2709 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2710 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2713 I915_WRITE16(HWSTAM
, 0xffff);
2714 for_each_pipe(pipe
) {
2715 /* Clear enable bits; then clear status bits */
2716 I915_WRITE(PIPESTAT(pipe
), 0);
2717 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
2719 I915_WRITE(IMR
, 0xffffffff);
2720 I915_WRITE(IER
, 0x0);
2722 I915_WRITE(IIR
, I915_READ(IIR
));
2725 static void i965_irq_preinstall(struct drm_device
* dev
)
2727 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2730 atomic_set(&dev_priv
->irq_received
, 0);
2732 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2733 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2735 I915_WRITE(HWSTAM
, 0xeffe);
2737 I915_WRITE(PIPESTAT(pipe
), 0);
2738 I915_WRITE(IMR
, 0xffffffff);
2739 I915_WRITE(IER
, 0x0);
2743 static int i965_irq_postinstall(struct drm_device
*dev
)
2745 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2748 unsigned long irqflags
;
2750 /* Unmask the interrupts that we always want on. */
2751 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
2752 I915_DISPLAY_PORT_INTERRUPT
|
2753 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2754 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2755 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2756 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2757 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2759 enable_mask
= ~dev_priv
->irq_mask
;
2760 enable_mask
&= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2761 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
2762 enable_mask
|= I915_USER_INTERRUPT
;
2765 enable_mask
|= I915_BSD_USER_INTERRUPT
;
2767 /* Interrupt setup is already guaranteed to be single-threaded, this is
2768 * just to make the assert_spin_locked check happy. */
2769 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2770 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
2771 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2774 * Enable some error detection, note the instruction error mask
2775 * bit is reserved, so we leave it masked.
2778 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
2779 GM45_ERROR_MEM_PRIV
|
2780 GM45_ERROR_CP_PRIV
|
2781 I915_ERROR_MEMORY_REFRESH
);
2783 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
2784 I915_ERROR_MEMORY_REFRESH
);
2786 I915_WRITE(EMR
, error_mask
);
2788 I915_WRITE(IMR
, dev_priv
->irq_mask
);
2789 I915_WRITE(IER
, enable_mask
);
2792 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2793 POSTING_READ(PORT_HOTPLUG_EN
);
2795 i915_enable_asle_pipestat(dev
);
2800 static void i915_hpd_irq_setup(struct drm_device
*dev
)
2802 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2803 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2804 struct intel_encoder
*intel_encoder
;
2807 assert_spin_locked(&dev_priv
->irq_lock
);
2809 if (I915_HAS_HOTPLUG(dev
)) {
2810 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
2811 hotplug_en
&= ~HOTPLUG_INT_EN_MASK
;
2812 /* Note HDMI and DP share hotplug bits */
2813 /* enable bits are the same for all generations */
2814 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2815 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2816 hotplug_en
|= hpd_mask_i915
[intel_encoder
->hpd_pin
];
2817 /* Programming the CRT detection parameters tends
2818 to generate a spurious hotplug event about three
2819 seconds later. So just do it once.
2822 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
2823 hotplug_en
&= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK
;
2824 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
2826 /* Ignore TV since it's buggy */
2827 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
2831 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
2833 struct drm_device
*dev
= (struct drm_device
*) arg
;
2834 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2836 u32 pipe_stats
[I915_MAX_PIPES
];
2837 unsigned long irqflags
;
2839 int ret
= IRQ_NONE
, pipe
;
2841 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2842 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2844 atomic_inc(&dev_priv
->irq_received
);
2846 iir
= I915_READ(IIR
);
2849 bool blc_event
= false;
2851 irq_received
= (iir
& ~flip_mask
) != 0;
2853 /* Can't rely on pipestat interrupt bit in iir as it might
2854 * have been cleared after the pipestat interrupt was received.
2855 * It doesn't set the bit in iir again, but it still produces
2856 * interrupts (for non-MSI).
2858 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2859 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2860 i915_handle_error(dev
, false);
2862 for_each_pipe(pipe
) {
2863 int reg
= PIPESTAT(pipe
);
2864 pipe_stats
[pipe
] = I915_READ(reg
);
2867 * Clear the PIPE*STAT regs before the IIR
2869 if (pipe_stats
[pipe
] & 0x8000ffff) {
2870 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2871 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2873 I915_WRITE(reg
, pipe_stats
[pipe
]);
2877 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2884 /* Consume port. Then clear IIR or we'll miss events */
2885 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
2886 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
2887 u32 hotplug_trigger
= hotplug_status
& (IS_G4X(dev
) ?
2888 HOTPLUG_INT_STATUS_G4X
:
2889 HOTPLUG_INT_STATUS_I915
);
2891 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2894 intel_hpd_irq_handler(dev
, hotplug_trigger
,
2895 IS_G4X(dev
) ? hpd_status_gen4
: hpd_status_i915
);
2897 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
2898 I915_READ(PORT_HOTPLUG_STAT
);
2901 I915_WRITE(IIR
, iir
& ~flip_mask
);
2902 new_iir
= I915_READ(IIR
); /* Flush posted writes */
2904 if (iir
& I915_USER_INTERRUPT
)
2905 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2906 if (iir
& I915_BSD_USER_INTERRUPT
)
2907 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
2909 for_each_pipe(pipe
) {
2910 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
2911 i915_handle_vblank(dev
, pipe
, pipe
, iir
))
2912 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
2914 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
2919 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
2920 intel_opregion_asle_intr(dev
);
2922 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
2923 gmbus_irq_handler(dev
);
2925 /* With MSI, interrupts are only generated when iir
2926 * transitions from zero to nonzero. If another bit got
2927 * set while we were handling the existing iir bits, then
2928 * we would never get another interrupt.
2930 * This is fine on non-MSI as well, as if we hit this path
2931 * we avoid exiting the interrupt handler only to generate
2934 * Note that for MSI this could cause a stray interrupt report
2935 * if an interrupt landed in the time between writing IIR and
2936 * the posting read. This should be rare enough to never
2937 * trigger the 99% of 100,000 interrupts test for disabling
2943 i915_update_dri1_breadcrumb(dev
);
2948 static void i965_irq_uninstall(struct drm_device
* dev
)
2950 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2956 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2958 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2959 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2961 I915_WRITE(HWSTAM
, 0xffffffff);
2963 I915_WRITE(PIPESTAT(pipe
), 0);
2964 I915_WRITE(IMR
, 0xffffffff);
2965 I915_WRITE(IER
, 0x0);
2968 I915_WRITE(PIPESTAT(pipe
),
2969 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
2970 I915_WRITE(IIR
, I915_READ(IIR
));
2973 static void i915_reenable_hotplug_timer_func(unsigned long data
)
2975 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*)data
;
2976 struct drm_device
*dev
= dev_priv
->dev
;
2977 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2978 unsigned long irqflags
;
2981 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2982 for (i
= (HPD_NONE
+ 1); i
< HPD_NUM_PINS
; i
++) {
2983 struct drm_connector
*connector
;
2985 if (dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_DISABLED
)
2988 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
2990 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
2991 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2993 if (intel_connector
->encoder
->hpd_pin
== i
) {
2994 if (connector
->polled
!= intel_connector
->polled
)
2995 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
2996 drm_get_connector_name(connector
));
2997 connector
->polled
= intel_connector
->polled
;
2998 if (!connector
->polled
)
2999 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3003 if (dev_priv
->display
.hpd_irq_setup
)
3004 dev_priv
->display
.hpd_irq_setup(dev
);
3005 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3008 void intel_irq_init(struct drm_device
*dev
)
3010 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3012 INIT_WORK(&dev_priv
->hotplug_work
, i915_hotplug_work_func
);
3013 INIT_WORK(&dev_priv
->gpu_error
.work
, i915_error_work_func
);
3014 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
3015 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
3017 setup_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
3018 i915_hangcheck_elapsed
,
3019 (unsigned long) dev
);
3020 setup_timer(&dev_priv
->hotplug_reenable_timer
, i915_reenable_hotplug_timer_func
,
3021 (unsigned long) dev_priv
);
3023 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
, PM_QOS_DEFAULT_VALUE
);
3025 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
3026 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
3027 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
3028 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
3029 dev
->driver
->get_vblank_counter
= gm45_get_vblank_counter
;
3032 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3033 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
3035 dev
->driver
->get_vblank_timestamp
= NULL
;
3036 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
3038 if (IS_VALLEYVIEW(dev
)) {
3039 dev
->driver
->irq_handler
= valleyview_irq_handler
;
3040 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
3041 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
3042 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
3043 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
3044 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
3045 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3046 } else if (HAS_PCH_SPLIT(dev
)) {
3047 dev
->driver
->irq_handler
= ironlake_irq_handler
;
3048 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
3049 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
3050 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
3051 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
3052 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
3053 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
3055 if (INTEL_INFO(dev
)->gen
== 2) {
3056 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
3057 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
3058 dev
->driver
->irq_handler
= i8xx_irq_handler
;
3059 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
3060 } else if (INTEL_INFO(dev
)->gen
== 3) {
3061 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
3062 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
3063 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
3064 dev
->driver
->irq_handler
= i915_irq_handler
;
3065 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3067 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
3068 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
3069 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
3070 dev
->driver
->irq_handler
= i965_irq_handler
;
3071 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3073 dev
->driver
->enable_vblank
= i915_enable_vblank
;
3074 dev
->driver
->disable_vblank
= i915_disable_vblank
;
3078 void intel_hpd_init(struct drm_device
*dev
)
3080 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3081 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3082 struct drm_connector
*connector
;
3083 unsigned long irqflags
;
3086 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
3087 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
3088 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3090 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3091 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3092 connector
->polled
= intel_connector
->polled
;
3093 if (!connector
->polled
&& I915_HAS_HOTPLUG(dev
) && intel_connector
->encoder
->hpd_pin
> HPD_NONE
)
3094 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3097 /* Interrupt setup is already guaranteed to be single-threaded, this is
3098 * just to make the assert_spin_locked checks happy. */
3099 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3100 if (dev_priv
->display
.hpd_irq_setup
)
3101 dev_priv
->display
.hpd_irq_setup(dev
);
3102 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);