1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
35 #include <drm/i915_drm.h>
37 #include "i915_trace.h"
38 #include "intel_drv.h"
40 static const u32 hpd_ibx
[] = {
41 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
42 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
43 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
44 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
45 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
48 static const u32 hpd_cpt
[] = {
49 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
50 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG_CPT
,
51 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
52 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
53 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
56 static const u32 hpd_mask_i915
[] = {
57 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
58 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
59 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
60 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
61 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
62 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
65 static const u32 hpd_status_gen4
[] = {
66 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
67 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
68 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
69 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
70 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
71 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
74 static const u32 hpd_status_i915
[] = { /* i915 and valleyview are the same */
75 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
76 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
77 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
78 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
79 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
80 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
83 /* For display hotplug interrupt */
85 ironlake_enable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
87 assert_spin_locked(&dev_priv
->irq_lock
);
89 if (dev_priv
->pc8
.irqs_disabled
) {
90 WARN(1, "IRQs disabled\n");
91 dev_priv
->pc8
.regsave
.deimr
&= ~mask
;
95 if ((dev_priv
->irq_mask
& mask
) != 0) {
96 dev_priv
->irq_mask
&= ~mask
;
97 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
103 ironlake_disable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
105 assert_spin_locked(&dev_priv
->irq_lock
);
107 if (dev_priv
->pc8
.irqs_disabled
) {
108 WARN(1, "IRQs disabled\n");
109 dev_priv
->pc8
.regsave
.deimr
|= mask
;
113 if ((dev_priv
->irq_mask
& mask
) != mask
) {
114 dev_priv
->irq_mask
|= mask
;
115 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
121 * ilk_update_gt_irq - update GTIMR
122 * @dev_priv: driver private
123 * @interrupt_mask: mask of interrupt bits to update
124 * @enabled_irq_mask: mask of interrupt bits to enable
126 static void ilk_update_gt_irq(struct drm_i915_private
*dev_priv
,
127 uint32_t interrupt_mask
,
128 uint32_t enabled_irq_mask
)
130 assert_spin_locked(&dev_priv
->irq_lock
);
132 if (dev_priv
->pc8
.irqs_disabled
) {
133 WARN(1, "IRQs disabled\n");
134 dev_priv
->pc8
.regsave
.gtimr
&= ~interrupt_mask
;
135 dev_priv
->pc8
.regsave
.gtimr
|= (~enabled_irq_mask
&
140 dev_priv
->gt_irq_mask
&= ~interrupt_mask
;
141 dev_priv
->gt_irq_mask
|= (~enabled_irq_mask
& interrupt_mask
);
142 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
146 void ilk_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
148 ilk_update_gt_irq(dev_priv
, mask
, mask
);
151 void ilk_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
153 ilk_update_gt_irq(dev_priv
, mask
, 0);
157 * snb_update_pm_irq - update GEN6_PMIMR
158 * @dev_priv: driver private
159 * @interrupt_mask: mask of interrupt bits to update
160 * @enabled_irq_mask: mask of interrupt bits to enable
162 static void snb_update_pm_irq(struct drm_i915_private
*dev_priv
,
163 uint32_t interrupt_mask
,
164 uint32_t enabled_irq_mask
)
168 assert_spin_locked(&dev_priv
->irq_lock
);
170 if (dev_priv
->pc8
.irqs_disabled
) {
171 WARN(1, "IRQs disabled\n");
172 dev_priv
->pc8
.regsave
.gen6_pmimr
&= ~interrupt_mask
;
173 dev_priv
->pc8
.regsave
.gen6_pmimr
|= (~enabled_irq_mask
&
178 new_val
= dev_priv
->pm_irq_mask
;
179 new_val
&= ~interrupt_mask
;
180 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
182 if (new_val
!= dev_priv
->pm_irq_mask
) {
183 dev_priv
->pm_irq_mask
= new_val
;
184 I915_WRITE(GEN6_PMIMR
, dev_priv
->pm_irq_mask
);
185 POSTING_READ(GEN6_PMIMR
);
189 void snb_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
191 snb_update_pm_irq(dev_priv
, mask
, mask
);
194 void snb_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
196 snb_update_pm_irq(dev_priv
, mask
, 0);
199 static bool ivb_can_enable_err_int(struct drm_device
*dev
)
201 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
202 struct intel_crtc
*crtc
;
205 assert_spin_locked(&dev_priv
->irq_lock
);
207 for_each_pipe(pipe
) {
208 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
210 if (crtc
->cpu_fifo_underrun_disabled
)
217 static bool cpt_can_enable_serr_int(struct drm_device
*dev
)
219 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
221 struct intel_crtc
*crtc
;
223 assert_spin_locked(&dev_priv
->irq_lock
);
225 for_each_pipe(pipe
) {
226 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
228 if (crtc
->pch_fifo_underrun_disabled
)
235 static void ironlake_set_fifo_underrun_reporting(struct drm_device
*dev
,
236 enum pipe pipe
, bool enable
)
238 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
239 uint32_t bit
= (pipe
== PIPE_A
) ? DE_PIPEA_FIFO_UNDERRUN
:
240 DE_PIPEB_FIFO_UNDERRUN
;
243 ironlake_enable_display_irq(dev_priv
, bit
);
245 ironlake_disable_display_irq(dev_priv
, bit
);
248 static void ivybridge_set_fifo_underrun_reporting(struct drm_device
*dev
,
249 enum pipe pipe
, bool enable
)
251 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
253 I915_WRITE(GEN7_ERR_INT
, ERR_INT_FIFO_UNDERRUN(pipe
));
255 if (!ivb_can_enable_err_int(dev
))
258 ironlake_enable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
260 bool was_enabled
= !(I915_READ(DEIMR
) & DE_ERR_INT_IVB
);
262 /* Change the state _after_ we've read out the current one. */
263 ironlake_disable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
266 (I915_READ(GEN7_ERR_INT
) & ERR_INT_FIFO_UNDERRUN(pipe
))) {
267 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
274 * ibx_display_interrupt_update - update SDEIMR
275 * @dev_priv: driver private
276 * @interrupt_mask: mask of interrupt bits to update
277 * @enabled_irq_mask: mask of interrupt bits to enable
279 static void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
280 uint32_t interrupt_mask
,
281 uint32_t enabled_irq_mask
)
283 uint32_t sdeimr
= I915_READ(SDEIMR
);
284 sdeimr
&= ~interrupt_mask
;
285 sdeimr
|= (~enabled_irq_mask
& interrupt_mask
);
287 assert_spin_locked(&dev_priv
->irq_lock
);
289 if (dev_priv
->pc8
.irqs_disabled
&&
290 (interrupt_mask
& SDE_HOTPLUG_MASK_CPT
)) {
291 WARN(1, "IRQs disabled\n");
292 dev_priv
->pc8
.regsave
.sdeimr
&= ~interrupt_mask
;
293 dev_priv
->pc8
.regsave
.sdeimr
|= (~enabled_irq_mask
&
298 I915_WRITE(SDEIMR
, sdeimr
);
299 POSTING_READ(SDEIMR
);
301 #define ibx_enable_display_interrupt(dev_priv, bits) \
302 ibx_display_interrupt_update((dev_priv), (bits), (bits))
303 #define ibx_disable_display_interrupt(dev_priv, bits) \
304 ibx_display_interrupt_update((dev_priv), (bits), 0)
306 static void ibx_set_fifo_underrun_reporting(struct drm_device
*dev
,
307 enum transcoder pch_transcoder
,
310 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
311 uint32_t bit
= (pch_transcoder
== TRANSCODER_A
) ?
312 SDE_TRANSA_FIFO_UNDER
: SDE_TRANSB_FIFO_UNDER
;
315 ibx_enable_display_interrupt(dev_priv
, bit
);
317 ibx_disable_display_interrupt(dev_priv
, bit
);
320 static void cpt_set_fifo_underrun_reporting(struct drm_device
*dev
,
321 enum transcoder pch_transcoder
,
324 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
328 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
));
330 if (!cpt_can_enable_serr_int(dev
))
333 ibx_enable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
335 uint32_t tmp
= I915_READ(SERR_INT
);
336 bool was_enabled
= !(I915_READ(SDEIMR
) & SDE_ERROR_CPT
);
338 /* Change the state _after_ we've read out the current one. */
339 ibx_disable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
342 (tmp
& SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
))) {
343 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
344 transcoder_name(pch_transcoder
));
350 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
353 * @enable: true if we want to report FIFO underrun errors, false otherwise
355 * This function makes us disable or enable CPU fifo underruns for a specific
356 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
357 * reporting for one pipe may also disable all the other CPU error interruts for
358 * the other pipes, due to the fact that there's just one interrupt mask/enable
359 * bit for all the pipes.
361 * Returns the previous state of underrun reporting.
363 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device
*dev
,
364 enum pipe pipe
, bool enable
)
366 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
367 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
368 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
372 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
374 ret
= !intel_crtc
->cpu_fifo_underrun_disabled
;
379 intel_crtc
->cpu_fifo_underrun_disabled
= !enable
;
381 if (IS_GEN5(dev
) || IS_GEN6(dev
))
382 ironlake_set_fifo_underrun_reporting(dev
, pipe
, enable
);
383 else if (IS_GEN7(dev
))
384 ivybridge_set_fifo_underrun_reporting(dev
, pipe
, enable
);
387 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
392 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
394 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
395 * @enable: true if we want to report FIFO underrun errors, false otherwise
397 * This function makes us disable or enable PCH fifo underruns for a specific
398 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
399 * underrun reporting for one transcoder may also disable all the other PCH
400 * error interruts for the other transcoders, due to the fact that there's just
401 * one interrupt mask/enable bit for all the transcoders.
403 * Returns the previous state of underrun reporting.
405 bool intel_set_pch_fifo_underrun_reporting(struct drm_device
*dev
,
406 enum transcoder pch_transcoder
,
409 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
410 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pch_transcoder
];
411 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
416 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
417 * has only one pch transcoder A that all pipes can use. To avoid racy
418 * pch transcoder -> pipe lookups from interrupt code simply store the
419 * underrun statistics in crtc A. Since we never expose this anywhere
420 * nor use it outside of the fifo underrun code here using the "wrong"
421 * crtc on LPT won't cause issues.
424 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
426 ret
= !intel_crtc
->pch_fifo_underrun_disabled
;
431 intel_crtc
->pch_fifo_underrun_disabled
= !enable
;
433 if (HAS_PCH_IBX(dev
))
434 ibx_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
436 cpt_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
439 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
445 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
447 u32 reg
= PIPESTAT(pipe
);
448 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
450 assert_spin_locked(&dev_priv
->irq_lock
);
452 if ((pipestat
& mask
) == mask
)
455 /* Enable the interrupt, clear any pending status */
456 pipestat
|= mask
| (mask
>> 16);
457 I915_WRITE(reg
, pipestat
);
462 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
464 u32 reg
= PIPESTAT(pipe
);
465 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
467 assert_spin_locked(&dev_priv
->irq_lock
);
469 if ((pipestat
& mask
) == 0)
473 I915_WRITE(reg
, pipestat
);
478 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
480 static void i915_enable_asle_pipestat(struct drm_device
*dev
)
482 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
483 unsigned long irqflags
;
485 if (!dev_priv
->opregion
.asle
|| !IS_MOBILE(dev
))
488 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
490 i915_enable_pipestat(dev_priv
, 1, PIPE_LEGACY_BLC_EVENT_ENABLE
);
491 if (INTEL_INFO(dev
)->gen
>= 4)
492 i915_enable_pipestat(dev_priv
, 0, PIPE_LEGACY_BLC_EVENT_ENABLE
);
494 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
498 * i915_pipe_enabled - check if a pipe is enabled
500 * @pipe: pipe to check
502 * Reading certain registers when the pipe is disabled can hang the chip.
503 * Use this routine to make sure the PLL is running and the pipe is active
504 * before reading such registers if unsure.
507 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
509 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
511 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
512 /* Locking is horribly broken here, but whatever. */
513 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
514 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
516 return intel_crtc
->active
;
518 return I915_READ(PIPECONF(pipe
)) & PIPECONF_ENABLE
;
522 static u32
i8xx_get_vblank_counter(struct drm_device
*dev
, int pipe
)
524 /* Gen2 doesn't have a hardware frame counter */
528 /* Called from drm generic code, passed a 'crtc', which
529 * we use as a pipe index
531 static u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
533 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
534 unsigned long high_frame
;
535 unsigned long low_frame
;
536 u32 high1
, high2
, low
, pixel
, vbl_start
;
538 if (!i915_pipe_enabled(dev
, pipe
)) {
539 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
540 "pipe %c\n", pipe_name(pipe
));
544 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
545 struct intel_crtc
*intel_crtc
=
546 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
547 const struct drm_display_mode
*mode
=
548 &intel_crtc
->config
.adjusted_mode
;
550 vbl_start
= mode
->crtc_vblank_start
* mode
->crtc_htotal
;
552 enum transcoder cpu_transcoder
=
553 intel_pipe_to_cpu_transcoder(dev_priv
, pipe
);
556 htotal
= ((I915_READ(HTOTAL(cpu_transcoder
)) >> 16) & 0x1fff) + 1;
557 vbl_start
= (I915_READ(VBLANK(cpu_transcoder
)) & 0x1fff) + 1;
562 high_frame
= PIPEFRAME(pipe
);
563 low_frame
= PIPEFRAMEPIXEL(pipe
);
566 * High & low register fields aren't synchronized, so make sure
567 * we get a low value that's stable across two reads of the high
571 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
572 low
= I915_READ(low_frame
);
573 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
574 } while (high1
!= high2
);
576 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
577 pixel
= low
& PIPE_PIXEL_MASK
;
578 low
>>= PIPE_FRAME_LOW_SHIFT
;
581 * The frame counter increments at beginning of active.
582 * Cook up a vblank counter by also checking the pixel
583 * counter against vblank start.
585 return ((high1
<< 8) | low
) + (pixel
>= vbl_start
);
588 static u32
gm45_get_vblank_counter(struct drm_device
*dev
, int pipe
)
590 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
591 int reg
= PIPE_FRMCOUNT_GM45(pipe
);
593 if (!i915_pipe_enabled(dev
, pipe
)) {
594 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
595 "pipe %c\n", pipe_name(pipe
));
599 return I915_READ(reg
);
602 static bool intel_pipe_in_vblank(struct drm_device
*dev
, enum pipe pipe
)
604 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
607 if (IS_VALLEYVIEW(dev
)) {
608 status
= pipe
== PIPE_A
?
609 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
:
610 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
612 return I915_READ(VLV_ISR
) & status
;
613 } else if (IS_GEN2(dev
)) {
614 status
= pipe
== PIPE_A
?
615 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
:
616 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
618 return I915_READ16(ISR
) & status
;
619 } else if (INTEL_INFO(dev
)->gen
< 5) {
620 status
= pipe
== PIPE_A
?
621 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
:
622 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
624 return I915_READ(ISR
) & status
;
625 } else if (INTEL_INFO(dev
)->gen
< 7) {
626 status
= pipe
== PIPE_A
?
630 return I915_READ(DEISR
) & status
;
635 status
= DE_PIPEA_VBLANK_IVB
;
638 status
= DE_PIPEB_VBLANK_IVB
;
641 status
= DE_PIPEC_VBLANK_IVB
;
645 return I915_READ(DEISR
) & status
;
649 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, int pipe
,
650 int *vpos
, int *hpos
)
652 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
653 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
654 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
655 const struct drm_display_mode
*mode
= &intel_crtc
->config
.adjusted_mode
;
657 int vbl_start
, vbl_end
, htotal
, vtotal
;
661 if (!intel_crtc
->active
) {
662 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
663 "pipe %c\n", pipe_name(pipe
));
667 htotal
= mode
->crtc_htotal
;
668 vtotal
= mode
->crtc_vtotal
;
669 vbl_start
= mode
->crtc_vblank_start
;
670 vbl_end
= mode
->crtc_vblank_end
;
672 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
674 if (IS_GEN2(dev
) || IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
675 /* No obvious pixelcount register. Only query vertical
676 * scanout position from Display scan line register.
679 position
= I915_READ(PIPEDSL(pipe
)) & DSL_LINEMASK_GEN2
;
681 position
= I915_READ(PIPEDSL(pipe
)) & DSL_LINEMASK_GEN3
;
684 * The scanline counter increments at the leading edge
685 * of hsync, ie. it completely misses the active portion
686 * of the line. Fix up the counter at both edges of vblank
687 * to get a more accurate picture whether we're in vblank
690 in_vbl
= intel_pipe_in_vblank(dev
, pipe
);
691 if ((in_vbl
&& position
== vbl_start
- 1) ||
692 (!in_vbl
&& position
== vbl_end
- 1))
693 position
= (position
+ 1) % vtotal
;
695 /* Have access to pixelcount since start of frame.
696 * We can split this into vertical and horizontal
699 position
= (I915_READ(PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
701 /* convert to pixel counts */
707 in_vbl
= position
>= vbl_start
&& position
< vbl_end
;
710 * While in vblank, position will be negative
711 * counting up towards 0 at vbl_end. And outside
712 * vblank, position will be positive counting
715 if (position
>= vbl_start
)
718 position
+= vtotal
- vbl_end
;
720 if (IS_GEN2(dev
) || IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
724 *vpos
= position
/ htotal
;
725 *hpos
= position
- (*vpos
* htotal
);
730 ret
|= DRM_SCANOUTPOS_INVBL
;
735 static int i915_get_vblank_timestamp(struct drm_device
*dev
, int pipe
,
737 struct timeval
*vblank_time
,
740 struct drm_crtc
*crtc
;
742 if (pipe
< 0 || pipe
>= INTEL_INFO(dev
)->num_pipes
) {
743 DRM_ERROR("Invalid crtc %d\n", pipe
);
747 /* Get drm_crtc to timestamp: */
748 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
750 DRM_ERROR("Invalid crtc %d\n", pipe
);
754 if (!crtc
->enabled
) {
755 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
759 /* Helper routine in DRM core does all the work: */
760 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
765 static bool intel_hpd_irq_event(struct drm_device
*dev
,
766 struct drm_connector
*connector
)
768 enum drm_connector_status old_status
;
770 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
771 old_status
= connector
->status
;
773 connector
->status
= connector
->funcs
->detect(connector
, false);
774 if (old_status
== connector
->status
)
777 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
779 drm_get_connector_name(connector
),
780 drm_get_connector_status_name(old_status
),
781 drm_get_connector_status_name(connector
->status
));
787 * Handle hotplug events outside the interrupt handler proper.
789 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
791 static void i915_hotplug_work_func(struct work_struct
*work
)
793 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
795 struct drm_device
*dev
= dev_priv
->dev
;
796 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
797 struct intel_connector
*intel_connector
;
798 struct intel_encoder
*intel_encoder
;
799 struct drm_connector
*connector
;
800 unsigned long irqflags
;
801 bool hpd_disabled
= false;
802 bool changed
= false;
805 /* HPD irq before everything is fully set up. */
806 if (!dev_priv
->enable_hotplug_processing
)
809 mutex_lock(&mode_config
->mutex
);
810 DRM_DEBUG_KMS("running encoder hotplug functions\n");
812 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
814 hpd_event_bits
= dev_priv
->hpd_event_bits
;
815 dev_priv
->hpd_event_bits
= 0;
816 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
817 intel_connector
= to_intel_connector(connector
);
818 intel_encoder
= intel_connector
->encoder
;
819 if (intel_encoder
->hpd_pin
> HPD_NONE
&&
820 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_MARK_DISABLED
&&
821 connector
->polled
== DRM_CONNECTOR_POLL_HPD
) {
822 DRM_INFO("HPD interrupt storm detected on connector %s: "
823 "switching from hotplug detection to polling\n",
824 drm_get_connector_name(connector
));
825 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
= HPD_DISABLED
;
826 connector
->polled
= DRM_CONNECTOR_POLL_CONNECT
827 | DRM_CONNECTOR_POLL_DISCONNECT
;
830 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
831 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
832 drm_get_connector_name(connector
), intel_encoder
->hpd_pin
);
835 /* if there were no outputs to poll, poll was disabled,
836 * therefore make sure it's enabled when disabling HPD on
839 drm_kms_helper_poll_enable(dev
);
840 mod_timer(&dev_priv
->hotplug_reenable_timer
,
841 jiffies
+ msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY
));
844 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
846 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
847 intel_connector
= to_intel_connector(connector
);
848 intel_encoder
= intel_connector
->encoder
;
849 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
850 if (intel_encoder
->hot_plug
)
851 intel_encoder
->hot_plug(intel_encoder
);
852 if (intel_hpd_irq_event(dev
, connector
))
856 mutex_unlock(&mode_config
->mutex
);
859 drm_kms_helper_hotplug_event(dev
);
862 static void ironlake_rps_change_irq_handler(struct drm_device
*dev
)
864 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
865 u32 busy_up
, busy_down
, max_avg
, min_avg
;
868 spin_lock(&mchdev_lock
);
870 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
872 new_delay
= dev_priv
->ips
.cur_delay
;
874 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
875 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
876 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
877 max_avg
= I915_READ(RCBMAXAVG
);
878 min_avg
= I915_READ(RCBMINAVG
);
880 /* Handle RCS change request from hw */
881 if (busy_up
> max_avg
) {
882 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
883 new_delay
= dev_priv
->ips
.cur_delay
- 1;
884 if (new_delay
< dev_priv
->ips
.max_delay
)
885 new_delay
= dev_priv
->ips
.max_delay
;
886 } else if (busy_down
< min_avg
) {
887 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
888 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
889 if (new_delay
> dev_priv
->ips
.min_delay
)
890 new_delay
= dev_priv
->ips
.min_delay
;
893 if (ironlake_set_drps(dev
, new_delay
))
894 dev_priv
->ips
.cur_delay
= new_delay
;
896 spin_unlock(&mchdev_lock
);
901 static void notify_ring(struct drm_device
*dev
,
902 struct intel_ring_buffer
*ring
)
904 if (ring
->obj
== NULL
)
907 trace_i915_gem_request_complete(ring
);
909 wake_up_all(&ring
->irq_queue
);
910 i915_queue_hangcheck(dev
);
913 static void gen6_pm_rps_work(struct work_struct
*work
)
915 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
920 spin_lock_irq(&dev_priv
->irq_lock
);
921 pm_iir
= dev_priv
->rps
.pm_iir
;
922 dev_priv
->rps
.pm_iir
= 0;
923 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
924 snb_enable_pm_irq(dev_priv
, GEN6_PM_RPS_EVENTS
);
925 spin_unlock_irq(&dev_priv
->irq_lock
);
927 /* Make sure we didn't queue anything we're not going to process. */
928 WARN_ON(pm_iir
& ~GEN6_PM_RPS_EVENTS
);
930 if ((pm_iir
& GEN6_PM_RPS_EVENTS
) == 0)
933 mutex_lock(&dev_priv
->rps
.hw_lock
);
935 adj
= dev_priv
->rps
.last_adj
;
936 if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
) {
941 new_delay
= dev_priv
->rps
.cur_delay
+ adj
;
944 * For better performance, jump directly
945 * to RPe if we're below it.
947 if (new_delay
< dev_priv
->rps
.rpe_delay
)
948 new_delay
= dev_priv
->rps
.rpe_delay
;
949 } else if (pm_iir
& GEN6_PM_RP_DOWN_TIMEOUT
) {
950 if (dev_priv
->rps
.cur_delay
> dev_priv
->rps
.rpe_delay
)
951 new_delay
= dev_priv
->rps
.rpe_delay
;
953 new_delay
= dev_priv
->rps
.min_delay
;
955 } else if (pm_iir
& GEN6_PM_RP_DOWN_THRESHOLD
) {
960 new_delay
= dev_priv
->rps
.cur_delay
+ adj
;
961 } else { /* unknown event */
962 new_delay
= dev_priv
->rps
.cur_delay
;
965 /* sysfs frequency interfaces may have snuck in while servicing the
968 if (new_delay
< (int)dev_priv
->rps
.min_delay
)
969 new_delay
= dev_priv
->rps
.min_delay
;
970 if (new_delay
> (int)dev_priv
->rps
.max_delay
)
971 new_delay
= dev_priv
->rps
.max_delay
;
972 dev_priv
->rps
.last_adj
= new_delay
- dev_priv
->rps
.cur_delay
;
974 if (IS_VALLEYVIEW(dev_priv
->dev
))
975 valleyview_set_rps(dev_priv
->dev
, new_delay
);
977 gen6_set_rps(dev_priv
->dev
, new_delay
);
979 mutex_unlock(&dev_priv
->rps
.hw_lock
);
984 * ivybridge_parity_work - Workqueue called when a parity error interrupt
986 * @work: workqueue struct
988 * Doesn't actually do anything except notify userspace. As a consequence of
989 * this event, userspace should try to remap the bad rows since statistically
990 * it is likely the same row is more likely to go bad again.
992 static void ivybridge_parity_work(struct work_struct
*work
)
994 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
995 l3_parity
.error_work
);
996 u32 error_status
, row
, bank
, subbank
;
997 char *parity_event
[6];
1002 /* We must turn off DOP level clock gating to access the L3 registers.
1003 * In order to prevent a get/put style interface, acquire struct mutex
1004 * any time we access those registers.
1006 mutex_lock(&dev_priv
->dev
->struct_mutex
);
1008 /* If we've screwed up tracking, just let the interrupt fire again */
1009 if (WARN_ON(!dev_priv
->l3_parity
.which_slice
))
1012 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
1013 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
1014 POSTING_READ(GEN7_MISCCPCTL
);
1016 while ((slice
= ffs(dev_priv
->l3_parity
.which_slice
)) != 0) {
1020 if (WARN_ON_ONCE(slice
>= NUM_L3_SLICES(dev_priv
->dev
)))
1023 dev_priv
->l3_parity
.which_slice
&= ~(1<<slice
);
1025 reg
= GEN7_L3CDERRST1
+ (slice
* 0x200);
1027 error_status
= I915_READ(reg
);
1028 row
= GEN7_PARITY_ERROR_ROW(error_status
);
1029 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
1030 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
1032 I915_WRITE(reg
, GEN7_PARITY_ERROR_VALID
| GEN7_L3CDERRST1_ENABLE
);
1035 parity_event
[0] = I915_L3_PARITY_UEVENT
"=1";
1036 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
1037 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
1038 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
1039 parity_event
[4] = kasprintf(GFP_KERNEL
, "SLICE=%d", slice
);
1040 parity_event
[5] = NULL
;
1042 kobject_uevent_env(&dev_priv
->dev
->primary
->kdev
.kobj
,
1043 KOBJ_CHANGE
, parity_event
);
1045 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1046 slice
, row
, bank
, subbank
);
1048 kfree(parity_event
[4]);
1049 kfree(parity_event
[3]);
1050 kfree(parity_event
[2]);
1051 kfree(parity_event
[1]);
1054 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
1057 WARN_ON(dev_priv
->l3_parity
.which_slice
);
1058 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1059 ilk_enable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev_priv
->dev
));
1060 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1062 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
1065 static void ivybridge_parity_error_irq_handler(struct drm_device
*dev
, u32 iir
)
1067 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1069 if (!HAS_L3_DPF(dev
))
1072 spin_lock(&dev_priv
->irq_lock
);
1073 ilk_disable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev
));
1074 spin_unlock(&dev_priv
->irq_lock
);
1076 iir
&= GT_PARITY_ERROR(dev
);
1077 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1
)
1078 dev_priv
->l3_parity
.which_slice
|= 1 << 1;
1080 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT
)
1081 dev_priv
->l3_parity
.which_slice
|= 1 << 0;
1083 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
1086 static void ilk_gt_irq_handler(struct drm_device
*dev
,
1087 struct drm_i915_private
*dev_priv
,
1091 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1092 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
1093 if (gt_iir
& ILK_BSD_USER_INTERRUPT
)
1094 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1097 static void snb_gt_irq_handler(struct drm_device
*dev
,
1098 struct drm_i915_private
*dev_priv
,
1103 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1104 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
1105 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
1106 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1107 if (gt_iir
& GT_BLT_USER_INTERRUPT
)
1108 notify_ring(dev
, &dev_priv
->ring
[BCS
]);
1110 if (gt_iir
& (GT_BLT_CS_ERROR_INTERRUPT
|
1111 GT_BSD_CS_ERROR_INTERRUPT
|
1112 GT_RENDER_CS_MASTER_ERROR_INTERRUPT
)) {
1113 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir
);
1114 i915_handle_error(dev
, false);
1117 if (gt_iir
& GT_PARITY_ERROR(dev
))
1118 ivybridge_parity_error_irq_handler(dev
, gt_iir
);
1121 #define HPD_STORM_DETECT_PERIOD 1000
1122 #define HPD_STORM_THRESHOLD 5
1124 static inline void intel_hpd_irq_handler(struct drm_device
*dev
,
1125 u32 hotplug_trigger
,
1128 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1130 bool storm_detected
= false;
1132 if (!hotplug_trigger
)
1135 spin_lock(&dev_priv
->irq_lock
);
1136 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
1138 WARN(((hpd
[i
] & hotplug_trigger
) &&
1139 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
),
1140 "Received HPD interrupt although disabled\n");
1142 if (!(hpd
[i
] & hotplug_trigger
) ||
1143 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
)
1146 dev_priv
->hpd_event_bits
|= (1 << i
);
1147 if (!time_in_range(jiffies
, dev_priv
->hpd_stats
[i
].hpd_last_jiffies
,
1148 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
1149 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD
))) {
1150 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
= jiffies
;
1151 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
1152 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i
);
1153 } else if (dev_priv
->hpd_stats
[i
].hpd_cnt
> HPD_STORM_THRESHOLD
) {
1154 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_MARK_DISABLED
;
1155 dev_priv
->hpd_event_bits
&= ~(1 << i
);
1156 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i
);
1157 storm_detected
= true;
1159 dev_priv
->hpd_stats
[i
].hpd_cnt
++;
1160 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i
,
1161 dev_priv
->hpd_stats
[i
].hpd_cnt
);
1166 dev_priv
->display
.hpd_irq_setup(dev
);
1167 spin_unlock(&dev_priv
->irq_lock
);
1170 * Our hotplug handler can grab modeset locks (by calling down into the
1171 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1172 * queue for otherwise the flush_work in the pageflip code will
1175 schedule_work(&dev_priv
->hotplug_work
);
1178 static void gmbus_irq_handler(struct drm_device
*dev
)
1180 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1182 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1185 static void dp_aux_irq_handler(struct drm_device
*dev
)
1187 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1189 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1192 #if defined(CONFIG_DEBUG_FS)
1193 static void ivb_pipe_crc_update(struct drm_device
*dev
, enum pipe pipe
)
1195 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1196 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
1197 struct intel_pipe_crc_entry
*entry
;
1201 head
= atomic_read(&pipe_crc
->head
);
1202 tail
= atomic_read(&pipe_crc
->tail
);
1204 if (CIRC_SPACE(head
, tail
, INTEL_PIPE_CRC_ENTRIES_NR
) < 1) {
1205 DRM_ERROR("CRC buffer overflowing\n");
1209 entry
= &pipe_crc
->entries
[head
];
1212 ts
= ktime_to_us(now
);
1214 entry
->timestamp
= ts
;
1215 entry
->crc
[0] = I915_READ(PIPE_CRC_RES_1_IVB(pipe
));
1216 entry
->crc
[1] = I915_READ(PIPE_CRC_RES_2_IVB(pipe
));
1217 entry
->crc
[2] = I915_READ(PIPE_CRC_RES_3_IVB(pipe
));
1218 entry
->crc
[3] = I915_READ(PIPE_CRC_RES_4_IVB(pipe
));
1219 entry
->crc
[4] = I915_READ(PIPE_CRC_RES_5_IVB(pipe
));
1221 head
= (head
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
1222 atomic_set(&pipe_crc
->head
, head
);
1225 static void ivb_pipe_crc_update(struct drm_device
*dev
, int pipe
) {}
1228 /* The RPS events need forcewake, so we add them to a work queue and mask their
1229 * IMR bits until the work is done. Other interrupts can be processed without
1230 * the work queue. */
1231 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1233 if (pm_iir
& GEN6_PM_RPS_EVENTS
) {
1234 spin_lock(&dev_priv
->irq_lock
);
1235 dev_priv
->rps
.pm_iir
|= pm_iir
& GEN6_PM_RPS_EVENTS
;
1236 snb_disable_pm_irq(dev_priv
, pm_iir
& GEN6_PM_RPS_EVENTS
);
1237 spin_unlock(&dev_priv
->irq_lock
);
1239 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
1242 if (HAS_VEBOX(dev_priv
->dev
)) {
1243 if (pm_iir
& PM_VEBOX_USER_INTERRUPT
)
1244 notify_ring(dev_priv
->dev
, &dev_priv
->ring
[VECS
]);
1246 if (pm_iir
& PM_VEBOX_CS_ERROR_INTERRUPT
) {
1247 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir
);
1248 i915_handle_error(dev_priv
->dev
, false);
1253 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
1255 struct drm_device
*dev
= (struct drm_device
*) arg
;
1256 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1257 u32 iir
, gt_iir
, pm_iir
;
1258 irqreturn_t ret
= IRQ_NONE
;
1259 unsigned long irqflags
;
1261 u32 pipe_stats
[I915_MAX_PIPES
];
1263 atomic_inc(&dev_priv
->irq_received
);
1266 iir
= I915_READ(VLV_IIR
);
1267 gt_iir
= I915_READ(GTIIR
);
1268 pm_iir
= I915_READ(GEN6_PMIIR
);
1270 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
1275 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1277 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1278 for_each_pipe(pipe
) {
1279 int reg
= PIPESTAT(pipe
);
1280 pipe_stats
[pipe
] = I915_READ(reg
);
1283 * Clear the PIPE*STAT regs before the IIR
1285 if (pipe_stats
[pipe
] & 0x8000ffff) {
1286 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
1287 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1289 I915_WRITE(reg
, pipe_stats
[pipe
]);
1292 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1294 for_each_pipe(pipe
) {
1295 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
)
1296 drm_handle_vblank(dev
, pipe
);
1298 if (pipe_stats
[pipe
] & PLANE_FLIPDONE_INT_STATUS_VLV
) {
1299 intel_prepare_page_flip(dev
, pipe
);
1300 intel_finish_page_flip(dev
, pipe
);
1304 /* Consume port. Then clear IIR or we'll miss events */
1305 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
1306 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1307 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
1309 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1312 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
1314 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1315 I915_READ(PORT_HOTPLUG_STAT
);
1318 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1319 gmbus_irq_handler(dev
);
1322 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1324 I915_WRITE(GTIIR
, gt_iir
);
1325 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1326 I915_WRITE(VLV_IIR
, iir
);
1333 static void ibx_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1335 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1337 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK
;
1339 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_ibx
);
1341 if (pch_iir
& SDE_AUDIO_POWER_MASK
) {
1342 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK
) >>
1343 SDE_AUDIO_POWER_SHIFT
);
1344 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1348 if (pch_iir
& SDE_AUX_MASK
)
1349 dp_aux_irq_handler(dev
);
1351 if (pch_iir
& SDE_GMBUS
)
1352 gmbus_irq_handler(dev
);
1354 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
1355 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1357 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
1358 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1360 if (pch_iir
& SDE_POISON
)
1361 DRM_ERROR("PCH poison interrupt\n");
1363 if (pch_iir
& SDE_FDI_MASK
)
1365 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1367 I915_READ(FDI_RX_IIR(pipe
)));
1369 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
1370 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1372 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
1373 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1375 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
1376 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1378 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1380 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
1381 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1383 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1386 static void ivb_err_int_handler(struct drm_device
*dev
)
1388 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1389 u32 err_int
= I915_READ(GEN7_ERR_INT
);
1391 if (err_int
& ERR_INT_POISON
)
1392 DRM_ERROR("Poison interrupt\n");
1394 if (err_int
& ERR_INT_FIFO_UNDERRUN_A
)
1395 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_A
, false))
1396 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1398 if (err_int
& ERR_INT_FIFO_UNDERRUN_B
)
1399 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_B
, false))
1400 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1402 if (err_int
& ERR_INT_FIFO_UNDERRUN_C
)
1403 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_C
, false))
1404 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1406 if (err_int
& ERR_INT_PIPE_CRC_DONE_A
)
1407 ivb_pipe_crc_update(dev
, PIPE_A
);
1409 if (err_int
& ERR_INT_PIPE_CRC_DONE_B
)
1410 ivb_pipe_crc_update(dev
, PIPE_B
);
1412 if (err_int
& ERR_INT_PIPE_CRC_DONE_C
)
1413 ivb_pipe_crc_update(dev
, PIPE_C
);
1415 I915_WRITE(GEN7_ERR_INT
, err_int
);
1418 static void cpt_serr_int_handler(struct drm_device
*dev
)
1420 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1421 u32 serr_int
= I915_READ(SERR_INT
);
1423 if (serr_int
& SERR_INT_POISON
)
1424 DRM_ERROR("PCH poison interrupt\n");
1426 if (serr_int
& SERR_INT_TRANS_A_FIFO_UNDERRUN
)
1427 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1429 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1431 if (serr_int
& SERR_INT_TRANS_B_FIFO_UNDERRUN
)
1432 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1434 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1436 if (serr_int
& SERR_INT_TRANS_C_FIFO_UNDERRUN
)
1437 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_C
,
1439 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1441 I915_WRITE(SERR_INT
, serr_int
);
1444 static void cpt_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1446 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1448 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_CPT
;
1450 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_cpt
);
1452 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) {
1453 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
1454 SDE_AUDIO_POWER_SHIFT_CPT
);
1455 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1459 if (pch_iir
& SDE_AUX_MASK_CPT
)
1460 dp_aux_irq_handler(dev
);
1462 if (pch_iir
& SDE_GMBUS_CPT
)
1463 gmbus_irq_handler(dev
);
1465 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
1466 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1468 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
1469 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1471 if (pch_iir
& SDE_FDI_MASK_CPT
)
1473 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1475 I915_READ(FDI_RX_IIR(pipe
)));
1477 if (pch_iir
& SDE_ERROR_CPT
)
1478 cpt_serr_int_handler(dev
);
1481 static void ilk_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
1483 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1485 if (de_iir
& DE_AUX_CHANNEL_A
)
1486 dp_aux_irq_handler(dev
);
1488 if (de_iir
& DE_GSE
)
1489 intel_opregion_asle_intr(dev
);
1491 if (de_iir
& DE_PIPEA_VBLANK
)
1492 drm_handle_vblank(dev
, 0);
1494 if (de_iir
& DE_PIPEB_VBLANK
)
1495 drm_handle_vblank(dev
, 1);
1497 if (de_iir
& DE_POISON
)
1498 DRM_ERROR("Poison interrupt\n");
1500 if (de_iir
& DE_PIPEA_FIFO_UNDERRUN
)
1501 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_A
, false))
1502 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1504 if (de_iir
& DE_PIPEB_FIFO_UNDERRUN
)
1505 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_B
, false))
1506 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1508 if (de_iir
& DE_PLANEA_FLIP_DONE
) {
1509 intel_prepare_page_flip(dev
, 0);
1510 intel_finish_page_flip_plane(dev
, 0);
1513 if (de_iir
& DE_PLANEB_FLIP_DONE
) {
1514 intel_prepare_page_flip(dev
, 1);
1515 intel_finish_page_flip_plane(dev
, 1);
1518 /* check event from PCH */
1519 if (de_iir
& DE_PCH_EVENT
) {
1520 u32 pch_iir
= I915_READ(SDEIIR
);
1522 if (HAS_PCH_CPT(dev
))
1523 cpt_irq_handler(dev
, pch_iir
);
1525 ibx_irq_handler(dev
, pch_iir
);
1527 /* should clear PCH hotplug event before clear CPU irq */
1528 I915_WRITE(SDEIIR
, pch_iir
);
1531 if (IS_GEN5(dev
) && de_iir
& DE_PCU_EVENT
)
1532 ironlake_rps_change_irq_handler(dev
);
1535 static void ivb_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
1537 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1540 if (de_iir
& DE_ERR_INT_IVB
)
1541 ivb_err_int_handler(dev
);
1543 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
1544 dp_aux_irq_handler(dev
);
1546 if (de_iir
& DE_GSE_IVB
)
1547 intel_opregion_asle_intr(dev
);
1549 for (i
= 0; i
< 3; i
++) {
1550 if (de_iir
& (DE_PIPEA_VBLANK_IVB
<< (5 * i
)))
1551 drm_handle_vblank(dev
, i
);
1552 if (de_iir
& (DE_PLANEA_FLIP_DONE_IVB
<< (5 * i
))) {
1553 intel_prepare_page_flip(dev
, i
);
1554 intel_finish_page_flip_plane(dev
, i
);
1558 /* check event from PCH */
1559 if (!HAS_PCH_NOP(dev
) && (de_iir
& DE_PCH_EVENT_IVB
)) {
1560 u32 pch_iir
= I915_READ(SDEIIR
);
1562 cpt_irq_handler(dev
, pch_iir
);
1564 /* clear PCH hotplug event before clear CPU irq */
1565 I915_WRITE(SDEIIR
, pch_iir
);
1569 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
1571 struct drm_device
*dev
= (struct drm_device
*) arg
;
1572 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1573 u32 de_iir
, gt_iir
, de_ier
, sde_ier
= 0;
1574 irqreturn_t ret
= IRQ_NONE
;
1576 atomic_inc(&dev_priv
->irq_received
);
1578 /* We get interrupts on unclaimed registers, so check for this before we
1579 * do any I915_{READ,WRITE}. */
1580 intel_uncore_check_errors(dev
);
1582 /* disable master interrupt before clearing iir */
1583 de_ier
= I915_READ(DEIER
);
1584 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
1585 POSTING_READ(DEIER
);
1587 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1588 * interrupts will will be stored on its back queue, and then we'll be
1589 * able to process them after we restore SDEIER (as soon as we restore
1590 * it, we'll get an interrupt if SDEIIR still has something to process
1591 * due to its back queue). */
1592 if (!HAS_PCH_NOP(dev
)) {
1593 sde_ier
= I915_READ(SDEIER
);
1594 I915_WRITE(SDEIER
, 0);
1595 POSTING_READ(SDEIER
);
1598 gt_iir
= I915_READ(GTIIR
);
1600 if (INTEL_INFO(dev
)->gen
>= 6)
1601 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1603 ilk_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1604 I915_WRITE(GTIIR
, gt_iir
);
1608 de_iir
= I915_READ(DEIIR
);
1610 if (INTEL_INFO(dev
)->gen
>= 7)
1611 ivb_display_irq_handler(dev
, de_iir
);
1613 ilk_display_irq_handler(dev
, de_iir
);
1614 I915_WRITE(DEIIR
, de_iir
);
1618 if (INTEL_INFO(dev
)->gen
>= 6) {
1619 u32 pm_iir
= I915_READ(GEN6_PMIIR
);
1621 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1622 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1627 I915_WRITE(DEIER
, de_ier
);
1628 POSTING_READ(DEIER
);
1629 if (!HAS_PCH_NOP(dev
)) {
1630 I915_WRITE(SDEIER
, sde_ier
);
1631 POSTING_READ(SDEIER
);
1637 static void i915_error_wake_up(struct drm_i915_private
*dev_priv
,
1638 bool reset_completed
)
1640 struct intel_ring_buffer
*ring
;
1644 * Notify all waiters for GPU completion events that reset state has
1645 * been changed, and that they need to restart their wait after
1646 * checking for potential errors (and bail out to drop locks if there is
1647 * a gpu reset pending so that i915_error_work_func can acquire them).
1650 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
1651 for_each_ring(ring
, dev_priv
, i
)
1652 wake_up_all(&ring
->irq_queue
);
1654 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
1655 wake_up_all(&dev_priv
->pending_flip_queue
);
1658 * Signal tasks blocked in i915_gem_wait_for_error that the pending
1659 * reset state is cleared.
1661 if (reset_completed
)
1662 wake_up_all(&dev_priv
->gpu_error
.reset_queue
);
1666 * i915_error_work_func - do process context error handling work
1667 * @work: work struct
1669 * Fire an error uevent so userspace can see that a hang or error
1672 static void i915_error_work_func(struct work_struct
*work
)
1674 struct i915_gpu_error
*error
= container_of(work
, struct i915_gpu_error
,
1676 drm_i915_private_t
*dev_priv
= container_of(error
, drm_i915_private_t
,
1678 struct drm_device
*dev
= dev_priv
->dev
;
1679 char *error_event
[] = { I915_ERROR_UEVENT
"=1", NULL
};
1680 char *reset_event
[] = { I915_RESET_UEVENT
"=1", NULL
};
1681 char *reset_done_event
[] = { I915_ERROR_UEVENT
"=0", NULL
};
1684 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
, error_event
);
1687 * Note that there's only one work item which does gpu resets, so we
1688 * need not worry about concurrent gpu resets potentially incrementing
1689 * error->reset_counter twice. We only need to take care of another
1690 * racing irq/hangcheck declaring the gpu dead for a second time. A
1691 * quick check for that is good enough: schedule_work ensures the
1692 * correct ordering between hang detection and this work item, and since
1693 * the reset in-progress bit is only ever set by code outside of this
1694 * work we don't need to worry about any other races.
1696 if (i915_reset_in_progress(error
) && !i915_terminally_wedged(error
)) {
1697 DRM_DEBUG_DRIVER("resetting chip\n");
1698 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
,
1702 * All state reset _must_ be completed before we update the
1703 * reset counter, for otherwise waiters might miss the reset
1704 * pending state and not properly drop locks, resulting in
1705 * deadlocks with the reset work.
1707 ret
= i915_reset(dev
);
1709 intel_display_handle_reset(dev
);
1713 * After all the gem state is reset, increment the reset
1714 * counter and wake up everyone waiting for the reset to
1717 * Since unlock operations are a one-sided barrier only,
1718 * we need to insert a barrier here to order any seqno
1720 * the counter increment.
1722 smp_mb__before_atomic_inc();
1723 atomic_inc(&dev_priv
->gpu_error
.reset_counter
);
1725 kobject_uevent_env(&dev
->primary
->kdev
.kobj
,
1726 KOBJ_CHANGE
, reset_done_event
);
1728 atomic_set(&error
->reset_counter
, I915_WEDGED
);
1732 * Note: The wake_up also serves as a memory barrier so that
1733 * waiters see the update value of the reset counter atomic_t.
1735 i915_error_wake_up(dev_priv
, true);
1739 static void i915_report_and_clear_eir(struct drm_device
*dev
)
1741 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1742 uint32_t instdone
[I915_NUM_INSTDONE_REG
];
1743 u32 eir
= I915_READ(EIR
);
1749 pr_err("render error detected, EIR: 0x%08x\n", eir
);
1751 i915_get_extra_instdone(dev
, instdone
);
1754 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
1755 u32 ipeir
= I915_READ(IPEIR_I965
);
1757 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1758 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1759 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
1760 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
1761 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1762 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1763 I915_WRITE(IPEIR_I965
, ipeir
);
1764 POSTING_READ(IPEIR_I965
);
1766 if (eir
& GM45_ERROR_PAGE_TABLE
) {
1767 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1768 pr_err("page table error\n");
1769 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1770 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1771 POSTING_READ(PGTBL_ER
);
1775 if (!IS_GEN2(dev
)) {
1776 if (eir
& I915_ERROR_PAGE_TABLE
) {
1777 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1778 pr_err("page table error\n");
1779 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1780 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1781 POSTING_READ(PGTBL_ER
);
1785 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
1786 pr_err("memory refresh error:\n");
1788 pr_err("pipe %c stat: 0x%08x\n",
1789 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
1790 /* pipestat has already been acked */
1792 if (eir
& I915_ERROR_INSTRUCTION
) {
1793 pr_err("instruction error\n");
1794 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
1795 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
1796 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
1797 if (INTEL_INFO(dev
)->gen
< 4) {
1798 u32 ipeir
= I915_READ(IPEIR
);
1800 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
1801 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
1802 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
1803 I915_WRITE(IPEIR
, ipeir
);
1804 POSTING_READ(IPEIR
);
1806 u32 ipeir
= I915_READ(IPEIR_I965
);
1808 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1809 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1810 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1811 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1812 I915_WRITE(IPEIR_I965
, ipeir
);
1813 POSTING_READ(IPEIR_I965
);
1817 I915_WRITE(EIR
, eir
);
1819 eir
= I915_READ(EIR
);
1822 * some errors might have become stuck,
1825 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
1826 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
1827 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
1832 * i915_handle_error - handle an error interrupt
1835 * Do some basic checking of regsiter state at error interrupt time and
1836 * dump it to the syslog. Also call i915_capture_error_state() to make
1837 * sure we get a record and make it available in debugfs. Fire a uevent
1838 * so userspace knows something bad happened (should trigger collection
1839 * of a ring dump etc.).
1841 void i915_handle_error(struct drm_device
*dev
, bool wedged
)
1843 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1845 i915_capture_error_state(dev
);
1846 i915_report_and_clear_eir(dev
);
1849 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG
,
1850 &dev_priv
->gpu_error
.reset_counter
);
1853 * Wakeup waiting processes so that the reset work function
1854 * i915_error_work_func doesn't deadlock trying to grab various
1855 * locks. By bumping the reset counter first, the woken
1856 * processes will see a reset in progress and back off,
1857 * releasing their locks and then wait for the reset completion.
1858 * We must do this for _all_ gpu waiters that might hold locks
1859 * that the reset work needs to acquire.
1861 * Note: The wake_up serves as the required memory barrier to
1862 * ensure that the waiters see the updated value of the reset
1865 i915_error_wake_up(dev_priv
, false);
1869 * Our reset work can grab modeset locks (since it needs to reset the
1870 * state of outstanding pagelips). Hence it must not be run on our own
1871 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
1872 * code will deadlock.
1874 schedule_work(&dev_priv
->gpu_error
.work
);
1877 static void __always_unused
i915_pageflip_stall_check(struct drm_device
*dev
, int pipe
)
1879 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1880 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1881 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1882 struct drm_i915_gem_object
*obj
;
1883 struct intel_unpin_work
*work
;
1884 unsigned long flags
;
1885 bool stall_detected
;
1887 /* Ignore early vblank irqs */
1888 if (intel_crtc
== NULL
)
1891 spin_lock_irqsave(&dev
->event_lock
, flags
);
1892 work
= intel_crtc
->unpin_work
;
1895 atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
||
1896 !work
->enable_stall_check
) {
1897 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1898 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1902 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1903 obj
= work
->pending_flip_obj
;
1904 if (INTEL_INFO(dev
)->gen
>= 4) {
1905 int dspsurf
= DSPSURF(intel_crtc
->plane
);
1906 stall_detected
= I915_HI_DISPBASE(I915_READ(dspsurf
)) ==
1907 i915_gem_obj_ggtt_offset(obj
);
1909 int dspaddr
= DSPADDR(intel_crtc
->plane
);
1910 stall_detected
= I915_READ(dspaddr
) == (i915_gem_obj_ggtt_offset(obj
) +
1911 crtc
->y
* crtc
->fb
->pitches
[0] +
1912 crtc
->x
* crtc
->fb
->bits_per_pixel
/8);
1915 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1917 if (stall_detected
) {
1918 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1919 intel_prepare_page_flip(dev
, intel_crtc
->plane
);
1923 /* Called from drm generic code, passed 'crtc' which
1924 * we use as a pipe index
1926 static int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
1928 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1929 unsigned long irqflags
;
1931 if (!i915_pipe_enabled(dev
, pipe
))
1934 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1935 if (INTEL_INFO(dev
)->gen
>= 4)
1936 i915_enable_pipestat(dev_priv
, pipe
,
1937 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1939 i915_enable_pipestat(dev_priv
, pipe
,
1940 PIPE_VBLANK_INTERRUPT_ENABLE
);
1942 /* maintain vblank delivery even in deep C-states */
1943 if (dev_priv
->info
->gen
== 3)
1944 I915_WRITE(INSTPM
, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS
));
1945 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1950 static int ironlake_enable_vblank(struct drm_device
*dev
, int pipe
)
1952 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1953 unsigned long irqflags
;
1954 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
1955 DE_PIPE_VBLANK_ILK(pipe
);
1957 if (!i915_pipe_enabled(dev
, pipe
))
1960 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1961 ironlake_enable_display_irq(dev_priv
, bit
);
1962 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1967 static int valleyview_enable_vblank(struct drm_device
*dev
, int pipe
)
1969 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1970 unsigned long irqflags
;
1973 if (!i915_pipe_enabled(dev
, pipe
))
1976 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1977 imr
= I915_READ(VLV_IMR
);
1979 imr
&= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
1981 imr
&= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1982 I915_WRITE(VLV_IMR
, imr
);
1983 i915_enable_pipestat(dev_priv
, pipe
,
1984 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1985 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1990 /* Called from drm generic code, passed 'crtc' which
1991 * we use as a pipe index
1993 static void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
1995 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1996 unsigned long irqflags
;
1998 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1999 if (dev_priv
->info
->gen
== 3)
2000 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS
));
2002 i915_disable_pipestat(dev_priv
, pipe
,
2003 PIPE_VBLANK_INTERRUPT_ENABLE
|
2004 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
2005 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2008 static void ironlake_disable_vblank(struct drm_device
*dev
, int pipe
)
2010 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2011 unsigned long irqflags
;
2012 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
2013 DE_PIPE_VBLANK_ILK(pipe
);
2015 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2016 ironlake_disable_display_irq(dev_priv
, bit
);
2017 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2020 static void valleyview_disable_vblank(struct drm_device
*dev
, int pipe
)
2022 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2023 unsigned long irqflags
;
2026 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2027 i915_disable_pipestat(dev_priv
, pipe
,
2028 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
2029 imr
= I915_READ(VLV_IMR
);
2031 imr
|= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
2033 imr
|= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2034 I915_WRITE(VLV_IMR
, imr
);
2035 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2039 ring_last_seqno(struct intel_ring_buffer
*ring
)
2041 return list_entry(ring
->request_list
.prev
,
2042 struct drm_i915_gem_request
, list
)->seqno
;
2046 ring_idle(struct intel_ring_buffer
*ring
, u32 seqno
)
2048 return (list_empty(&ring
->request_list
) ||
2049 i915_seqno_passed(seqno
, ring_last_seqno(ring
)));
2052 static struct intel_ring_buffer
*
2053 semaphore_waits_for(struct intel_ring_buffer
*ring
, u32
*seqno
)
2055 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2056 u32 cmd
, ipehr
, acthd
, acthd_min
;
2058 ipehr
= I915_READ(RING_IPEHR(ring
->mmio_base
));
2059 if ((ipehr
& ~(0x3 << 16)) !=
2060 (MI_SEMAPHORE_MBOX
| MI_SEMAPHORE_COMPARE
| MI_SEMAPHORE_REGISTER
))
2063 /* ACTHD is likely pointing to the dword after the actual command,
2064 * so scan backwards until we find the MBOX.
2066 acthd
= intel_ring_get_active_head(ring
) & HEAD_ADDR
;
2067 acthd_min
= max((int)acthd
- 3 * 4, 0);
2069 cmd
= ioread32(ring
->virtual_start
+ acthd
);
2074 if (acthd
< acthd_min
)
2078 *seqno
= ioread32(ring
->virtual_start
+acthd
+4)+1;
2079 return &dev_priv
->ring
[(ring
->id
+ (((ipehr
>> 17) & 1) + 1)) % 3];
2082 static int semaphore_passed(struct intel_ring_buffer
*ring
)
2084 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2085 struct intel_ring_buffer
*signaller
;
2088 ring
->hangcheck
.deadlock
= true;
2090 signaller
= semaphore_waits_for(ring
, &seqno
);
2091 if (signaller
== NULL
|| signaller
->hangcheck
.deadlock
)
2094 /* cursory check for an unkickable deadlock */
2095 ctl
= I915_READ_CTL(signaller
);
2096 if (ctl
& RING_WAIT_SEMAPHORE
&& semaphore_passed(signaller
) < 0)
2099 return i915_seqno_passed(signaller
->get_seqno(signaller
, false), seqno
);
2102 static void semaphore_clear_deadlocks(struct drm_i915_private
*dev_priv
)
2104 struct intel_ring_buffer
*ring
;
2107 for_each_ring(ring
, dev_priv
, i
)
2108 ring
->hangcheck
.deadlock
= false;
2111 static enum intel_ring_hangcheck_action
2112 ring_stuck(struct intel_ring_buffer
*ring
, u32 acthd
)
2114 struct drm_device
*dev
= ring
->dev
;
2115 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2118 if (ring
->hangcheck
.acthd
!= acthd
)
2119 return HANGCHECK_ACTIVE
;
2122 return HANGCHECK_HUNG
;
2124 /* Is the chip hanging on a WAIT_FOR_EVENT?
2125 * If so we can simply poke the RB_WAIT bit
2126 * and break the hang. This should work on
2127 * all but the second generation chipsets.
2129 tmp
= I915_READ_CTL(ring
);
2130 if (tmp
& RING_WAIT
) {
2131 DRM_ERROR("Kicking stuck wait on %s\n",
2133 i915_handle_error(dev
, false);
2134 I915_WRITE_CTL(ring
, tmp
);
2135 return HANGCHECK_KICK
;
2138 if (INTEL_INFO(dev
)->gen
>= 6 && tmp
& RING_WAIT_SEMAPHORE
) {
2139 switch (semaphore_passed(ring
)) {
2141 return HANGCHECK_HUNG
;
2143 DRM_ERROR("Kicking stuck semaphore on %s\n",
2145 i915_handle_error(dev
, false);
2146 I915_WRITE_CTL(ring
, tmp
);
2147 return HANGCHECK_KICK
;
2149 return HANGCHECK_WAIT
;
2153 return HANGCHECK_HUNG
;
2157 * This is called when the chip hasn't reported back with completed
2158 * batchbuffers in a long time. We keep track per ring seqno progress and
2159 * if there are no progress, hangcheck score for that ring is increased.
2160 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2161 * we kick the ring. If we see no progress on three subsequent calls
2162 * we assume chip is wedged and try to fix it by resetting the chip.
2164 static void i915_hangcheck_elapsed(unsigned long data
)
2166 struct drm_device
*dev
= (struct drm_device
*)data
;
2167 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2168 struct intel_ring_buffer
*ring
;
2170 int busy_count
= 0, rings_hung
= 0;
2171 bool stuck
[I915_NUM_RINGS
] = { 0 };
2177 if (!i915_enable_hangcheck
)
2180 for_each_ring(ring
, dev_priv
, i
) {
2184 semaphore_clear_deadlocks(dev_priv
);
2186 seqno
= ring
->get_seqno(ring
, false);
2187 acthd
= intel_ring_get_active_head(ring
);
2189 if (ring
->hangcheck
.seqno
== seqno
) {
2190 if (ring_idle(ring
, seqno
)) {
2191 ring
->hangcheck
.action
= HANGCHECK_IDLE
;
2193 if (waitqueue_active(&ring
->irq_queue
)) {
2194 /* Issue a wake-up to catch stuck h/w. */
2195 if (!test_and_set_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
)) {
2196 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2198 wake_up_all(&ring
->irq_queue
);
2200 /* Safeguard against driver failure */
2201 ring
->hangcheck
.score
+= BUSY
;
2205 /* We always increment the hangcheck score
2206 * if the ring is busy and still processing
2207 * the same request, so that no single request
2208 * can run indefinitely (such as a chain of
2209 * batches). The only time we do not increment
2210 * the hangcheck score on this ring, if this
2211 * ring is in a legitimate wait for another
2212 * ring. In that case the waiting ring is a
2213 * victim and we want to be sure we catch the
2214 * right culprit. Then every time we do kick
2215 * the ring, add a small increment to the
2216 * score so that we can catch a batch that is
2217 * being repeatedly kicked and so responsible
2218 * for stalling the machine.
2220 ring
->hangcheck
.action
= ring_stuck(ring
,
2223 switch (ring
->hangcheck
.action
) {
2224 case HANGCHECK_IDLE
:
2225 case HANGCHECK_WAIT
:
2227 case HANGCHECK_ACTIVE
:
2228 ring
->hangcheck
.score
+= BUSY
;
2230 case HANGCHECK_KICK
:
2231 ring
->hangcheck
.score
+= KICK
;
2233 case HANGCHECK_HUNG
:
2234 ring
->hangcheck
.score
+= HUNG
;
2240 ring
->hangcheck
.action
= HANGCHECK_ACTIVE
;
2242 /* Gradually reduce the count so that we catch DoS
2243 * attempts across multiple batches.
2245 if (ring
->hangcheck
.score
> 0)
2246 ring
->hangcheck
.score
--;
2249 ring
->hangcheck
.seqno
= seqno
;
2250 ring
->hangcheck
.acthd
= acthd
;
2254 for_each_ring(ring
, dev_priv
, i
) {
2255 if (ring
->hangcheck
.score
> FIRE
) {
2256 DRM_INFO("%s on %s\n",
2257 stuck
[i
] ? "stuck" : "no progress",
2264 return i915_handle_error(dev
, true);
2267 /* Reset timer case chip hangs without another request
2269 i915_queue_hangcheck(dev
);
2272 void i915_queue_hangcheck(struct drm_device
*dev
)
2274 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2275 if (!i915_enable_hangcheck
)
2278 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
2279 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
2282 static void ibx_irq_preinstall(struct drm_device
*dev
)
2284 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2286 if (HAS_PCH_NOP(dev
))
2289 /* south display irq */
2290 I915_WRITE(SDEIMR
, 0xffffffff);
2292 * SDEIER is also touched by the interrupt handler to work around missed
2293 * PCH interrupts. Hence we can't update it after the interrupt handler
2294 * is enabled - instead we unconditionally enable all PCH interrupt
2295 * sources here, but then only unmask them as needed with SDEIMR.
2297 I915_WRITE(SDEIER
, 0xffffffff);
2298 POSTING_READ(SDEIER
);
2301 static void gen5_gt_irq_preinstall(struct drm_device
*dev
)
2303 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2306 I915_WRITE(GTIMR
, 0xffffffff);
2307 I915_WRITE(GTIER
, 0x0);
2308 POSTING_READ(GTIER
);
2310 if (INTEL_INFO(dev
)->gen
>= 6) {
2312 I915_WRITE(GEN6_PMIMR
, 0xffffffff);
2313 I915_WRITE(GEN6_PMIER
, 0x0);
2314 POSTING_READ(GEN6_PMIER
);
2320 static void ironlake_irq_preinstall(struct drm_device
*dev
)
2322 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2324 atomic_set(&dev_priv
->irq_received
, 0);
2326 I915_WRITE(HWSTAM
, 0xeffe);
2328 I915_WRITE(DEIMR
, 0xffffffff);
2329 I915_WRITE(DEIER
, 0x0);
2330 POSTING_READ(DEIER
);
2332 gen5_gt_irq_preinstall(dev
);
2334 ibx_irq_preinstall(dev
);
2337 static void valleyview_irq_preinstall(struct drm_device
*dev
)
2339 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2342 atomic_set(&dev_priv
->irq_received
, 0);
2345 I915_WRITE(VLV_IMR
, 0);
2346 I915_WRITE(RING_IMR(RENDER_RING_BASE
), 0);
2347 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE
), 0);
2348 I915_WRITE(RING_IMR(BLT_RING_BASE
), 0);
2351 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2352 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2354 gen5_gt_irq_preinstall(dev
);
2356 I915_WRITE(DPINVGTT
, 0xff);
2358 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2359 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2361 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2362 I915_WRITE(VLV_IIR
, 0xffffffff);
2363 I915_WRITE(VLV_IMR
, 0xffffffff);
2364 I915_WRITE(VLV_IER
, 0x0);
2365 POSTING_READ(VLV_IER
);
2368 static void ibx_hpd_irq_setup(struct drm_device
*dev
)
2370 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2371 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2372 struct intel_encoder
*intel_encoder
;
2373 u32 hotplug_irqs
, hotplug
, enabled_irqs
= 0;
2375 if (HAS_PCH_IBX(dev
)) {
2376 hotplug_irqs
= SDE_HOTPLUG_MASK
;
2377 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2378 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2379 enabled_irqs
|= hpd_ibx
[intel_encoder
->hpd_pin
];
2381 hotplug_irqs
= SDE_HOTPLUG_MASK_CPT
;
2382 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2383 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2384 enabled_irqs
|= hpd_cpt
[intel_encoder
->hpd_pin
];
2387 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
2390 * Enable digital hotplug on the PCH, and configure the DP short pulse
2391 * duration to 2ms (which is the minimum in the Display Port spec)
2393 * This register is the same on all known PCH chips.
2395 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
2396 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
2397 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
2398 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
2399 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
2400 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
2403 static void ibx_irq_postinstall(struct drm_device
*dev
)
2405 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2408 if (HAS_PCH_NOP(dev
))
2411 if (HAS_PCH_IBX(dev
)) {
2412 mask
= SDE_GMBUS
| SDE_AUX_MASK
| SDE_TRANSB_FIFO_UNDER
|
2413 SDE_TRANSA_FIFO_UNDER
| SDE_POISON
;
2415 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
| SDE_ERROR_CPT
;
2417 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2420 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2421 I915_WRITE(SDEIMR
, ~mask
);
2424 static void gen5_gt_irq_postinstall(struct drm_device
*dev
)
2426 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2427 u32 pm_irqs
, gt_irqs
;
2429 pm_irqs
= gt_irqs
= 0;
2431 dev_priv
->gt_irq_mask
= ~0;
2432 if (HAS_L3_DPF(dev
)) {
2433 /* L3 parity interrupt is always unmasked. */
2434 dev_priv
->gt_irq_mask
= ~GT_PARITY_ERROR(dev
);
2435 gt_irqs
|= GT_PARITY_ERROR(dev
);
2438 gt_irqs
|= GT_RENDER_USER_INTERRUPT
;
2440 gt_irqs
|= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
|
2441 ILK_BSD_USER_INTERRUPT
;
2443 gt_irqs
|= GT_BLT_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
;
2446 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2447 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
2448 I915_WRITE(GTIER
, gt_irqs
);
2449 POSTING_READ(GTIER
);
2451 if (INTEL_INFO(dev
)->gen
>= 6) {
2452 pm_irqs
|= GEN6_PM_RPS_EVENTS
;
2455 pm_irqs
|= PM_VEBOX_USER_INTERRUPT
;
2457 dev_priv
->pm_irq_mask
= 0xffffffff;
2458 I915_WRITE(GEN6_PMIIR
, I915_READ(GEN6_PMIIR
));
2459 I915_WRITE(GEN6_PMIMR
, dev_priv
->pm_irq_mask
);
2460 I915_WRITE(GEN6_PMIER
, pm_irqs
);
2461 POSTING_READ(GEN6_PMIER
);
2465 static int ironlake_irq_postinstall(struct drm_device
*dev
)
2467 unsigned long irqflags
;
2468 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2469 u32 display_mask
, extra_mask
;
2471 if (INTEL_INFO(dev
)->gen
>= 7) {
2472 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
|
2473 DE_PCH_EVENT_IVB
| DE_PLANEC_FLIP_DONE_IVB
|
2474 DE_PLANEB_FLIP_DONE_IVB
|
2475 DE_PLANEA_FLIP_DONE_IVB
| DE_AUX_CHANNEL_A_IVB
|
2477 extra_mask
= (DE_PIPEC_VBLANK_IVB
| DE_PIPEB_VBLANK_IVB
|
2478 DE_PIPEA_VBLANK_IVB
);
2480 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2482 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
2483 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
|
2484 DE_AUX_CHANNEL_A
| DE_PIPEB_FIFO_UNDERRUN
|
2485 DE_PIPEA_FIFO_UNDERRUN
| DE_POISON
);
2486 extra_mask
= DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
| DE_PCU_EVENT
;
2489 dev_priv
->irq_mask
= ~display_mask
;
2491 /* should always can generate irq */
2492 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2493 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
2494 I915_WRITE(DEIER
, display_mask
| extra_mask
);
2495 POSTING_READ(DEIER
);
2497 gen5_gt_irq_postinstall(dev
);
2499 ibx_irq_postinstall(dev
);
2501 if (IS_IRONLAKE_M(dev
)) {
2502 /* Enable PCU event interrupts
2504 * spinlocking not required here for correctness since interrupt
2505 * setup is guaranteed to run in single-threaded context. But we
2506 * need it to make the assert_spin_locked happy. */
2507 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2508 ironlake_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
2509 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2515 static int valleyview_irq_postinstall(struct drm_device
*dev
)
2517 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2519 u32 pipestat_enable
= PLANE_FLIP_DONE_INT_EN_VLV
;
2520 unsigned long irqflags
;
2522 enable_mask
= I915_DISPLAY_PORT_INTERRUPT
;
2523 enable_mask
|= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2524 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2525 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2526 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2529 *Leave vblank interrupts masked initially. enable/disable will
2530 * toggle them based on usage.
2532 dev_priv
->irq_mask
= (~enable_mask
) |
2533 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2534 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2536 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2537 POSTING_READ(PORT_HOTPLUG_EN
);
2539 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
2540 I915_WRITE(VLV_IER
, enable_mask
);
2541 I915_WRITE(VLV_IIR
, 0xffffffff);
2542 I915_WRITE(PIPESTAT(0), 0xffff);
2543 I915_WRITE(PIPESTAT(1), 0xffff);
2544 POSTING_READ(VLV_IER
);
2546 /* Interrupt setup is already guaranteed to be single-threaded, this is
2547 * just to make the assert_spin_locked check happy. */
2548 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2549 i915_enable_pipestat(dev_priv
, 0, pipestat_enable
);
2550 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
2551 i915_enable_pipestat(dev_priv
, 1, pipestat_enable
);
2552 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2554 I915_WRITE(VLV_IIR
, 0xffffffff);
2555 I915_WRITE(VLV_IIR
, 0xffffffff);
2557 gen5_gt_irq_postinstall(dev
);
2559 /* ack & enable invalid PTE error interrupts */
2560 #if 0 /* FIXME: add support to irq handler for checking these bits */
2561 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
2562 I915_WRITE(DPINVGTT
, DPINVGTT_EN_MASK
);
2565 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
2570 static void valleyview_irq_uninstall(struct drm_device
*dev
)
2572 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2578 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2581 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2583 I915_WRITE(HWSTAM
, 0xffffffff);
2584 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2585 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2587 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2588 I915_WRITE(VLV_IIR
, 0xffffffff);
2589 I915_WRITE(VLV_IMR
, 0xffffffff);
2590 I915_WRITE(VLV_IER
, 0x0);
2591 POSTING_READ(VLV_IER
);
2594 static void ironlake_irq_uninstall(struct drm_device
*dev
)
2596 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2601 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2603 I915_WRITE(HWSTAM
, 0xffffffff);
2605 I915_WRITE(DEIMR
, 0xffffffff);
2606 I915_WRITE(DEIER
, 0x0);
2607 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2609 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2611 I915_WRITE(GTIMR
, 0xffffffff);
2612 I915_WRITE(GTIER
, 0x0);
2613 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2615 if (HAS_PCH_NOP(dev
))
2618 I915_WRITE(SDEIMR
, 0xffffffff);
2619 I915_WRITE(SDEIER
, 0x0);
2620 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2621 if (HAS_PCH_CPT(dev
) || HAS_PCH_LPT(dev
))
2622 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2625 static void i8xx_irq_preinstall(struct drm_device
* dev
)
2627 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2630 atomic_set(&dev_priv
->irq_received
, 0);
2633 I915_WRITE(PIPESTAT(pipe
), 0);
2634 I915_WRITE16(IMR
, 0xffff);
2635 I915_WRITE16(IER
, 0x0);
2636 POSTING_READ16(IER
);
2639 static int i8xx_irq_postinstall(struct drm_device
*dev
)
2641 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2644 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2646 /* Unmask the interrupts that we always want on. */
2647 dev_priv
->irq_mask
=
2648 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2649 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2650 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2651 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2652 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2653 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
2656 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2657 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2658 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2659 I915_USER_INTERRUPT
);
2660 POSTING_READ16(IER
);
2666 * Returns true when a page flip has completed.
2668 static bool i8xx_handle_vblank(struct drm_device
*dev
,
2671 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2672 u16 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(pipe
);
2674 if (!drm_handle_vblank(dev
, pipe
))
2677 if ((iir
& flip_pending
) == 0)
2680 intel_prepare_page_flip(dev
, pipe
);
2682 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2683 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2684 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2685 * the flip is completed (no longer pending). Since this doesn't raise
2686 * an interrupt per se, we watch for the change at vblank.
2688 if (I915_READ16(ISR
) & flip_pending
)
2691 intel_finish_page_flip(dev
, pipe
);
2696 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
2698 struct drm_device
*dev
= (struct drm_device
*) arg
;
2699 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2702 unsigned long irqflags
;
2705 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2706 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2708 atomic_inc(&dev_priv
->irq_received
);
2710 iir
= I915_READ16(IIR
);
2714 while (iir
& ~flip_mask
) {
2715 /* Can't rely on pipestat interrupt bit in iir as it might
2716 * have been cleared after the pipestat interrupt was received.
2717 * It doesn't set the bit in iir again, but it still produces
2718 * interrupts (for non-MSI).
2720 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2721 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2722 i915_handle_error(dev
, false);
2724 for_each_pipe(pipe
) {
2725 int reg
= PIPESTAT(pipe
);
2726 pipe_stats
[pipe
] = I915_READ(reg
);
2729 * Clear the PIPE*STAT regs before the IIR
2731 if (pipe_stats
[pipe
] & 0x8000ffff) {
2732 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2733 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2735 I915_WRITE(reg
, pipe_stats
[pipe
]);
2738 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2740 I915_WRITE16(IIR
, iir
& ~flip_mask
);
2741 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
2743 i915_update_dri1_breadcrumb(dev
);
2745 if (iir
& I915_USER_INTERRUPT
)
2746 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2748 if (pipe_stats
[0] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2749 i8xx_handle_vblank(dev
, 0, iir
))
2750 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(0);
2752 if (pipe_stats
[1] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2753 i8xx_handle_vblank(dev
, 1, iir
))
2754 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(1);
2762 static void i8xx_irq_uninstall(struct drm_device
* dev
)
2764 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2767 for_each_pipe(pipe
) {
2768 /* Clear enable bits; then clear status bits */
2769 I915_WRITE(PIPESTAT(pipe
), 0);
2770 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
2772 I915_WRITE16(IMR
, 0xffff);
2773 I915_WRITE16(IER
, 0x0);
2774 I915_WRITE16(IIR
, I915_READ16(IIR
));
2777 static void i915_irq_preinstall(struct drm_device
* dev
)
2779 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2782 atomic_set(&dev_priv
->irq_received
, 0);
2784 if (I915_HAS_HOTPLUG(dev
)) {
2785 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2786 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2789 I915_WRITE16(HWSTAM
, 0xeffe);
2791 I915_WRITE(PIPESTAT(pipe
), 0);
2792 I915_WRITE(IMR
, 0xffffffff);
2793 I915_WRITE(IER
, 0x0);
2797 static int i915_irq_postinstall(struct drm_device
*dev
)
2799 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2802 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2804 /* Unmask the interrupts that we always want on. */
2805 dev_priv
->irq_mask
=
2806 ~(I915_ASLE_INTERRUPT
|
2807 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2808 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2809 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2810 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2811 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2814 I915_ASLE_INTERRUPT
|
2815 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2816 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2817 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2818 I915_USER_INTERRUPT
;
2820 if (I915_HAS_HOTPLUG(dev
)) {
2821 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2822 POSTING_READ(PORT_HOTPLUG_EN
);
2824 /* Enable in IER... */
2825 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
2826 /* and unmask in IMR */
2827 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
2830 I915_WRITE(IMR
, dev_priv
->irq_mask
);
2831 I915_WRITE(IER
, enable_mask
);
2834 i915_enable_asle_pipestat(dev
);
2840 * Returns true when a page flip has completed.
2842 static bool i915_handle_vblank(struct drm_device
*dev
,
2843 int plane
, int pipe
, u32 iir
)
2845 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2846 u32 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
2848 if (!drm_handle_vblank(dev
, pipe
))
2851 if ((iir
& flip_pending
) == 0)
2854 intel_prepare_page_flip(dev
, plane
);
2856 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2857 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2858 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2859 * the flip is completed (no longer pending). Since this doesn't raise
2860 * an interrupt per se, we watch for the change at vblank.
2862 if (I915_READ(ISR
) & flip_pending
)
2865 intel_finish_page_flip(dev
, pipe
);
2870 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
2872 struct drm_device
*dev
= (struct drm_device
*) arg
;
2873 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2874 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
2875 unsigned long irqflags
;
2877 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2878 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2879 int pipe
, ret
= IRQ_NONE
;
2881 atomic_inc(&dev_priv
->irq_received
);
2883 iir
= I915_READ(IIR
);
2885 bool irq_received
= (iir
& ~flip_mask
) != 0;
2886 bool blc_event
= false;
2888 /* Can't rely on pipestat interrupt bit in iir as it might
2889 * have been cleared after the pipestat interrupt was received.
2890 * It doesn't set the bit in iir again, but it still produces
2891 * interrupts (for non-MSI).
2893 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2894 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2895 i915_handle_error(dev
, false);
2897 for_each_pipe(pipe
) {
2898 int reg
= PIPESTAT(pipe
);
2899 pipe_stats
[pipe
] = I915_READ(reg
);
2901 /* Clear the PIPE*STAT regs before the IIR */
2902 if (pipe_stats
[pipe
] & 0x8000ffff) {
2903 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2904 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2906 I915_WRITE(reg
, pipe_stats
[pipe
]);
2907 irq_received
= true;
2910 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2915 /* Consume port. Then clear IIR or we'll miss events */
2916 if ((I915_HAS_HOTPLUG(dev
)) &&
2917 (iir
& I915_DISPLAY_PORT_INTERRUPT
)) {
2918 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
2919 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
2921 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2924 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
2926 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
2927 POSTING_READ(PORT_HOTPLUG_STAT
);
2930 I915_WRITE(IIR
, iir
& ~flip_mask
);
2931 new_iir
= I915_READ(IIR
); /* Flush posted writes */
2933 if (iir
& I915_USER_INTERRUPT
)
2934 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2936 for_each_pipe(pipe
) {
2941 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2942 i915_handle_vblank(dev
, plane
, pipe
, iir
))
2943 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
2945 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
2949 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
2950 intel_opregion_asle_intr(dev
);
2952 /* With MSI, interrupts are only generated when iir
2953 * transitions from zero to nonzero. If another bit got
2954 * set while we were handling the existing iir bits, then
2955 * we would never get another interrupt.
2957 * This is fine on non-MSI as well, as if we hit this path
2958 * we avoid exiting the interrupt handler only to generate
2961 * Note that for MSI this could cause a stray interrupt report
2962 * if an interrupt landed in the time between writing IIR and
2963 * the posting read. This should be rare enough to never
2964 * trigger the 99% of 100,000 interrupts test for disabling
2969 } while (iir
& ~flip_mask
);
2971 i915_update_dri1_breadcrumb(dev
);
2976 static void i915_irq_uninstall(struct drm_device
* dev
)
2978 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2981 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2983 if (I915_HAS_HOTPLUG(dev
)) {
2984 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2985 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2988 I915_WRITE16(HWSTAM
, 0xffff);
2989 for_each_pipe(pipe
) {
2990 /* Clear enable bits; then clear status bits */
2991 I915_WRITE(PIPESTAT(pipe
), 0);
2992 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
2994 I915_WRITE(IMR
, 0xffffffff);
2995 I915_WRITE(IER
, 0x0);
2997 I915_WRITE(IIR
, I915_READ(IIR
));
3000 static void i965_irq_preinstall(struct drm_device
* dev
)
3002 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3005 atomic_set(&dev_priv
->irq_received
, 0);
3007 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3008 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3010 I915_WRITE(HWSTAM
, 0xeffe);
3012 I915_WRITE(PIPESTAT(pipe
), 0);
3013 I915_WRITE(IMR
, 0xffffffff);
3014 I915_WRITE(IER
, 0x0);
3018 static int i965_irq_postinstall(struct drm_device
*dev
)
3020 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3023 unsigned long irqflags
;
3025 /* Unmask the interrupts that we always want on. */
3026 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
3027 I915_DISPLAY_PORT_INTERRUPT
|
3028 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3029 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3030 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3031 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
3032 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
3034 enable_mask
= ~dev_priv
->irq_mask
;
3035 enable_mask
&= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3036 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
3037 enable_mask
|= I915_USER_INTERRUPT
;
3040 enable_mask
|= I915_BSD_USER_INTERRUPT
;
3042 /* Interrupt setup is already guaranteed to be single-threaded, this is
3043 * just to make the assert_spin_locked check happy. */
3044 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3045 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
3046 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3049 * Enable some error detection, note the instruction error mask
3050 * bit is reserved, so we leave it masked.
3053 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
3054 GM45_ERROR_MEM_PRIV
|
3055 GM45_ERROR_CP_PRIV
|
3056 I915_ERROR_MEMORY_REFRESH
);
3058 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
3059 I915_ERROR_MEMORY_REFRESH
);
3061 I915_WRITE(EMR
, error_mask
);
3063 I915_WRITE(IMR
, dev_priv
->irq_mask
);
3064 I915_WRITE(IER
, enable_mask
);
3067 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3068 POSTING_READ(PORT_HOTPLUG_EN
);
3070 i915_enable_asle_pipestat(dev
);
3075 static void i915_hpd_irq_setup(struct drm_device
*dev
)
3077 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3078 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3079 struct intel_encoder
*intel_encoder
;
3082 assert_spin_locked(&dev_priv
->irq_lock
);
3084 if (I915_HAS_HOTPLUG(dev
)) {
3085 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
3086 hotplug_en
&= ~HOTPLUG_INT_EN_MASK
;
3087 /* Note HDMI and DP share hotplug bits */
3088 /* enable bits are the same for all generations */
3089 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
3090 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
3091 hotplug_en
|= hpd_mask_i915
[intel_encoder
->hpd_pin
];
3092 /* Programming the CRT detection parameters tends
3093 to generate a spurious hotplug event about three
3094 seconds later. So just do it once.
3097 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
3098 hotplug_en
&= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK
;
3099 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
3101 /* Ignore TV since it's buggy */
3102 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
3106 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
3108 struct drm_device
*dev
= (struct drm_device
*) arg
;
3109 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3111 u32 pipe_stats
[I915_MAX_PIPES
];
3112 unsigned long irqflags
;
3114 int ret
= IRQ_NONE
, pipe
;
3116 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3117 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3119 atomic_inc(&dev_priv
->irq_received
);
3121 iir
= I915_READ(IIR
);
3124 bool blc_event
= false;
3126 irq_received
= (iir
& ~flip_mask
) != 0;
3128 /* Can't rely on pipestat interrupt bit in iir as it might
3129 * have been cleared after the pipestat interrupt was received.
3130 * It doesn't set the bit in iir again, but it still produces
3131 * interrupts (for non-MSI).
3133 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3134 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3135 i915_handle_error(dev
, false);
3137 for_each_pipe(pipe
) {
3138 int reg
= PIPESTAT(pipe
);
3139 pipe_stats
[pipe
] = I915_READ(reg
);
3142 * Clear the PIPE*STAT regs before the IIR
3144 if (pipe_stats
[pipe
] & 0x8000ffff) {
3145 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
3146 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3148 I915_WRITE(reg
, pipe_stats
[pipe
]);
3152 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3159 /* Consume port. Then clear IIR or we'll miss events */
3160 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
3161 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
3162 u32 hotplug_trigger
= hotplug_status
& (IS_G4X(dev
) ?
3163 HOTPLUG_INT_STATUS_G4X
:
3164 HOTPLUG_INT_STATUS_I915
);
3166 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3169 intel_hpd_irq_handler(dev
, hotplug_trigger
,
3170 IS_G4X(dev
) ? hpd_status_gen4
: hpd_status_i915
);
3172 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
3173 I915_READ(PORT_HOTPLUG_STAT
);
3176 I915_WRITE(IIR
, iir
& ~flip_mask
);
3177 new_iir
= I915_READ(IIR
); /* Flush posted writes */
3179 if (iir
& I915_USER_INTERRUPT
)
3180 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
3181 if (iir
& I915_BSD_USER_INTERRUPT
)
3182 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
3184 for_each_pipe(pipe
) {
3185 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
3186 i915_handle_vblank(dev
, pipe
, pipe
, iir
))
3187 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
3189 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
3194 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
3195 intel_opregion_asle_intr(dev
);
3197 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
3198 gmbus_irq_handler(dev
);
3200 /* With MSI, interrupts are only generated when iir
3201 * transitions from zero to nonzero. If another bit got
3202 * set while we were handling the existing iir bits, then
3203 * we would never get another interrupt.
3205 * This is fine on non-MSI as well, as if we hit this path
3206 * we avoid exiting the interrupt handler only to generate
3209 * Note that for MSI this could cause a stray interrupt report
3210 * if an interrupt landed in the time between writing IIR and
3211 * the posting read. This should be rare enough to never
3212 * trigger the 99% of 100,000 interrupts test for disabling
3218 i915_update_dri1_breadcrumb(dev
);
3223 static void i965_irq_uninstall(struct drm_device
* dev
)
3225 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3231 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
3233 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3234 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3236 I915_WRITE(HWSTAM
, 0xffffffff);
3238 I915_WRITE(PIPESTAT(pipe
), 0);
3239 I915_WRITE(IMR
, 0xffffffff);
3240 I915_WRITE(IER
, 0x0);
3243 I915_WRITE(PIPESTAT(pipe
),
3244 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
3245 I915_WRITE(IIR
, I915_READ(IIR
));
3248 static void i915_reenable_hotplug_timer_func(unsigned long data
)
3250 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*)data
;
3251 struct drm_device
*dev
= dev_priv
->dev
;
3252 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3253 unsigned long irqflags
;
3256 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3257 for (i
= (HPD_NONE
+ 1); i
< HPD_NUM_PINS
; i
++) {
3258 struct drm_connector
*connector
;
3260 if (dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_DISABLED
)
3263 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3265 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3266 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3268 if (intel_connector
->encoder
->hpd_pin
== i
) {
3269 if (connector
->polled
!= intel_connector
->polled
)
3270 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3271 drm_get_connector_name(connector
));
3272 connector
->polled
= intel_connector
->polled
;
3273 if (!connector
->polled
)
3274 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3278 if (dev_priv
->display
.hpd_irq_setup
)
3279 dev_priv
->display
.hpd_irq_setup(dev
);
3280 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3283 void intel_irq_init(struct drm_device
*dev
)
3285 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3287 INIT_WORK(&dev_priv
->hotplug_work
, i915_hotplug_work_func
);
3288 INIT_WORK(&dev_priv
->gpu_error
.work
, i915_error_work_func
);
3289 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
3290 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
3292 setup_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
3293 i915_hangcheck_elapsed
,
3294 (unsigned long) dev
);
3295 setup_timer(&dev_priv
->hotplug_reenable_timer
, i915_reenable_hotplug_timer_func
,
3296 (unsigned long) dev_priv
);
3298 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
, PM_QOS_DEFAULT_VALUE
);
3301 dev
->max_vblank_count
= 0;
3302 dev
->driver
->get_vblank_counter
= i8xx_get_vblank_counter
;
3303 } else if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
3304 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
3305 dev
->driver
->get_vblank_counter
= gm45_get_vblank_counter
;
3307 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
3308 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
3311 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
3312 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
3313 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
3316 if (IS_VALLEYVIEW(dev
)) {
3317 dev
->driver
->irq_handler
= valleyview_irq_handler
;
3318 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
3319 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
3320 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
3321 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
3322 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
3323 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3324 } else if (HAS_PCH_SPLIT(dev
)) {
3325 dev
->driver
->irq_handler
= ironlake_irq_handler
;
3326 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
3327 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
3328 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
3329 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
3330 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
3331 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
3333 if (INTEL_INFO(dev
)->gen
== 2) {
3334 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
3335 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
3336 dev
->driver
->irq_handler
= i8xx_irq_handler
;
3337 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
3338 } else if (INTEL_INFO(dev
)->gen
== 3) {
3339 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
3340 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
3341 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
3342 dev
->driver
->irq_handler
= i915_irq_handler
;
3343 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3345 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
3346 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
3347 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
3348 dev
->driver
->irq_handler
= i965_irq_handler
;
3349 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3351 dev
->driver
->enable_vblank
= i915_enable_vblank
;
3352 dev
->driver
->disable_vblank
= i915_disable_vblank
;
3356 void intel_hpd_init(struct drm_device
*dev
)
3358 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3359 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3360 struct drm_connector
*connector
;
3361 unsigned long irqflags
;
3364 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
3365 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
3366 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3368 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3369 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3370 connector
->polled
= intel_connector
->polled
;
3371 if (!connector
->polled
&& I915_HAS_HOTPLUG(dev
) && intel_connector
->encoder
->hpd_pin
> HPD_NONE
)
3372 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3375 /* Interrupt setup is already guaranteed to be single-threaded, this is
3376 * just to make the assert_spin_locked checks happy. */
3377 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3378 if (dev_priv
->display
.hpd_irq_setup
)
3379 dev_priv
->display
.hpd_irq_setup(dev
);
3380 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3383 /* Disable interrupts so we can allow Package C8+. */
3384 void hsw_pc8_disable_interrupts(struct drm_device
*dev
)
3386 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3387 unsigned long irqflags
;
3389 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3391 dev_priv
->pc8
.regsave
.deimr
= I915_READ(DEIMR
);
3392 dev_priv
->pc8
.regsave
.sdeimr
= I915_READ(SDEIMR
);
3393 dev_priv
->pc8
.regsave
.gtimr
= I915_READ(GTIMR
);
3394 dev_priv
->pc8
.regsave
.gtier
= I915_READ(GTIER
);
3395 dev_priv
->pc8
.regsave
.gen6_pmimr
= I915_READ(GEN6_PMIMR
);
3397 ironlake_disable_display_irq(dev_priv
, ~DE_PCH_EVENT_IVB
);
3398 ibx_disable_display_interrupt(dev_priv
, ~SDE_HOTPLUG_MASK_CPT
);
3399 ilk_disable_gt_irq(dev_priv
, 0xffffffff);
3400 snb_disable_pm_irq(dev_priv
, 0xffffffff);
3402 dev_priv
->pc8
.irqs_disabled
= true;
3404 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3407 /* Restore interrupts so we can recover from Package C8+. */
3408 void hsw_pc8_restore_interrupts(struct drm_device
*dev
)
3410 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3411 unsigned long irqflags
;
3412 uint32_t val
, expected
;
3414 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3416 val
= I915_READ(DEIMR
);
3417 expected
= ~DE_PCH_EVENT_IVB
;
3418 WARN(val
!= expected
, "DEIMR is 0x%08x, not 0x%08x\n", val
, expected
);
3420 val
= I915_READ(SDEIMR
) & ~SDE_HOTPLUG_MASK_CPT
;
3421 expected
= ~SDE_HOTPLUG_MASK_CPT
;
3422 WARN(val
!= expected
, "SDEIMR non-HPD bits are 0x%08x, not 0x%08x\n",
3425 val
= I915_READ(GTIMR
);
3426 expected
= 0xffffffff;
3427 WARN(val
!= expected
, "GTIMR is 0x%08x, not 0x%08x\n", val
, expected
);
3429 val
= I915_READ(GEN6_PMIMR
);
3430 expected
= 0xffffffff;
3431 WARN(val
!= expected
, "GEN6_PMIMR is 0x%08x, not 0x%08x\n", val
,
3434 dev_priv
->pc8
.irqs_disabled
= false;
3436 ironlake_enable_display_irq(dev_priv
, ~dev_priv
->pc8
.regsave
.deimr
);
3437 ibx_enable_display_interrupt(dev_priv
,
3438 ~dev_priv
->pc8
.regsave
.sdeimr
&
3439 ~SDE_HOTPLUG_MASK_CPT
);
3440 ilk_enable_gt_irq(dev_priv
, ~dev_priv
->pc8
.regsave
.gtimr
);
3441 snb_enable_pm_irq(dev_priv
, ~dev_priv
->pc8
.regsave
.gen6_pmimr
);
3442 I915_WRITE(GTIER
, dev_priv
->pc8
.regsave
.gtier
);
3444 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);