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drm/i915: improve GEN7_ERR_INT clearing for fifo underrun reporting
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <drm/drmP.h>
34 #include <drm/i915_drm.h>
35 #include "i915_drv.h"
36 #include "i915_trace.h"
37 #include "intel_drv.h"
38
39 static const u32 hpd_ibx[] = {
40 [HPD_CRT] = SDE_CRT_HOTPLUG,
41 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
42 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
43 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
44 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
45 };
46
47 static const u32 hpd_cpt[] = {
48 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
49 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
50 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
51 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
52 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
53 };
54
55 static const u32 hpd_mask_i915[] = {
56 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
57 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
58 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
59 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
60 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
61 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
62 };
63
64 static const u32 hpd_status_gen4[] = {
65 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
66 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
67 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
68 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
69 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
70 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
71 };
72
73 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
74 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
75 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
76 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
77 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
78 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
79 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
80 };
81
82 /* For display hotplug interrupt */
83 static void
84 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
85 {
86 assert_spin_locked(&dev_priv->irq_lock);
87
88 if ((dev_priv->irq_mask & mask) != 0) {
89 dev_priv->irq_mask &= ~mask;
90 I915_WRITE(DEIMR, dev_priv->irq_mask);
91 POSTING_READ(DEIMR);
92 }
93 }
94
95 static void
96 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
97 {
98 assert_spin_locked(&dev_priv->irq_lock);
99
100 if ((dev_priv->irq_mask & mask) != mask) {
101 dev_priv->irq_mask |= mask;
102 I915_WRITE(DEIMR, dev_priv->irq_mask);
103 POSTING_READ(DEIMR);
104 }
105 }
106
107 static bool ivb_can_enable_err_int(struct drm_device *dev)
108 {
109 struct drm_i915_private *dev_priv = dev->dev_private;
110 struct intel_crtc *crtc;
111 enum pipe pipe;
112
113 assert_spin_locked(&dev_priv->irq_lock);
114
115 for_each_pipe(pipe) {
116 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
117
118 if (crtc->cpu_fifo_underrun_disabled)
119 return false;
120 }
121
122 return true;
123 }
124
125 static bool cpt_can_enable_serr_int(struct drm_device *dev)
126 {
127 struct drm_i915_private *dev_priv = dev->dev_private;
128 enum pipe pipe;
129 struct intel_crtc *crtc;
130
131 assert_spin_locked(&dev_priv->irq_lock);
132
133 for_each_pipe(pipe) {
134 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
135
136 if (crtc->pch_fifo_underrun_disabled)
137 return false;
138 }
139
140 return true;
141 }
142
143 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
144 enum pipe pipe, bool enable)
145 {
146 struct drm_i915_private *dev_priv = dev->dev_private;
147 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
148 DE_PIPEB_FIFO_UNDERRUN;
149
150 if (enable)
151 ironlake_enable_display_irq(dev_priv, bit);
152 else
153 ironlake_disable_display_irq(dev_priv, bit);
154 }
155
156 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
157 enum pipe pipe, bool enable)
158 {
159 struct drm_i915_private *dev_priv = dev->dev_private;
160 if (enable) {
161 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
162
163 if (!ivb_can_enable_err_int(dev))
164 return;
165
166 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
167 } else {
168 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
169
170 /* Change the state _after_ we've read out the current one. */
171 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
172
173 if (!was_enabled &&
174 (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
175 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
176 pipe_name(pipe));
177 }
178 }
179 }
180
181 /**
182 * ibx_display_interrupt_update - update SDEIMR
183 * @dev_priv: driver private
184 * @interrupt_mask: mask of interrupt bits to update
185 * @enabled_irq_mask: mask of interrupt bits to enable
186 */
187 static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
188 uint32_t interrupt_mask,
189 uint32_t enabled_irq_mask)
190 {
191 uint32_t sdeimr = I915_READ(SDEIMR);
192 sdeimr &= ~interrupt_mask;
193 sdeimr |= (~enabled_irq_mask & interrupt_mask);
194
195 assert_spin_locked(&dev_priv->irq_lock);
196
197 I915_WRITE(SDEIMR, sdeimr);
198 POSTING_READ(SDEIMR);
199 }
200 #define ibx_enable_display_interrupt(dev_priv, bits) \
201 ibx_display_interrupt_update((dev_priv), (bits), (bits))
202 #define ibx_disable_display_interrupt(dev_priv, bits) \
203 ibx_display_interrupt_update((dev_priv), (bits), 0)
204
205 static void ibx_set_fifo_underrun_reporting(struct intel_crtc *crtc,
206 bool enable)
207 {
208 struct drm_device *dev = crtc->base.dev;
209 struct drm_i915_private *dev_priv = dev->dev_private;
210 uint32_t bit = (crtc->pipe == PIPE_A) ? SDE_TRANSA_FIFO_UNDER :
211 SDE_TRANSB_FIFO_UNDER;
212
213 if (enable)
214 ibx_enable_display_interrupt(dev_priv, bit);
215 else
216 ibx_disable_display_interrupt(dev_priv, bit);
217 }
218
219 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
220 enum transcoder pch_transcoder,
221 bool enable)
222 {
223 struct drm_i915_private *dev_priv = dev->dev_private;
224
225 if (enable) {
226 I915_WRITE(SERR_INT,
227 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
228
229 if (!cpt_can_enable_serr_int(dev))
230 return;
231
232 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
233 } else {
234 uint32_t tmp = I915_READ(SERR_INT);
235 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
236
237 /* Change the state _after_ we've read out the current one. */
238 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
239
240 if (!was_enabled &&
241 (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
242 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
243 transcoder_name(pch_transcoder));
244 }
245 }
246 }
247
248 /**
249 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
250 * @dev: drm device
251 * @pipe: pipe
252 * @enable: true if we want to report FIFO underrun errors, false otherwise
253 *
254 * This function makes us disable or enable CPU fifo underruns for a specific
255 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
256 * reporting for one pipe may also disable all the other CPU error interruts for
257 * the other pipes, due to the fact that there's just one interrupt mask/enable
258 * bit for all the pipes.
259 *
260 * Returns the previous state of underrun reporting.
261 */
262 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
263 enum pipe pipe, bool enable)
264 {
265 struct drm_i915_private *dev_priv = dev->dev_private;
266 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
268 unsigned long flags;
269 bool ret;
270
271 spin_lock_irqsave(&dev_priv->irq_lock, flags);
272
273 ret = !intel_crtc->cpu_fifo_underrun_disabled;
274
275 if (enable == ret)
276 goto done;
277
278 intel_crtc->cpu_fifo_underrun_disabled = !enable;
279
280 if (IS_GEN5(dev) || IS_GEN6(dev))
281 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
282 else if (IS_GEN7(dev))
283 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
284
285 done:
286 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
287 return ret;
288 }
289
290 /**
291 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
292 * @dev: drm device
293 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
294 * @enable: true if we want to report FIFO underrun errors, false otherwise
295 *
296 * This function makes us disable or enable PCH fifo underruns for a specific
297 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
298 * underrun reporting for one transcoder may also disable all the other PCH
299 * error interruts for the other transcoders, due to the fact that there's just
300 * one interrupt mask/enable bit for all the transcoders.
301 *
302 * Returns the previous state of underrun reporting.
303 */
304 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
305 enum transcoder pch_transcoder,
306 bool enable)
307 {
308 struct drm_i915_private *dev_priv = dev->dev_private;
309 enum pipe p;
310 struct drm_crtc *crtc;
311 struct intel_crtc *intel_crtc;
312 unsigned long flags;
313 bool ret;
314
315 if (HAS_PCH_LPT(dev)) {
316 crtc = NULL;
317 for_each_pipe(p) {
318 struct drm_crtc *c = dev_priv->pipe_to_crtc_mapping[p];
319 if (intel_pipe_has_type(c, INTEL_OUTPUT_ANALOG)) {
320 crtc = c;
321 break;
322 }
323 }
324 if (!crtc) {
325 DRM_ERROR("PCH FIFO underrun, but no CRTC using the PCH found\n");
326 return false;
327 }
328 } else {
329 crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
330 }
331 intel_crtc = to_intel_crtc(crtc);
332
333 spin_lock_irqsave(&dev_priv->irq_lock, flags);
334
335 ret = !intel_crtc->pch_fifo_underrun_disabled;
336
337 if (enable == ret)
338 goto done;
339
340 intel_crtc->pch_fifo_underrun_disabled = !enable;
341
342 if (HAS_PCH_IBX(dev))
343 ibx_set_fifo_underrun_reporting(intel_crtc, enable);
344 else
345 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
346
347 done:
348 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
349 return ret;
350 }
351
352
353 void
354 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
355 {
356 u32 reg = PIPESTAT(pipe);
357 u32 pipestat = I915_READ(reg) & 0x7fff0000;
358
359 assert_spin_locked(&dev_priv->irq_lock);
360
361 if ((pipestat & mask) == mask)
362 return;
363
364 /* Enable the interrupt, clear any pending status */
365 pipestat |= mask | (mask >> 16);
366 I915_WRITE(reg, pipestat);
367 POSTING_READ(reg);
368 }
369
370 void
371 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
372 {
373 u32 reg = PIPESTAT(pipe);
374 u32 pipestat = I915_READ(reg) & 0x7fff0000;
375
376 assert_spin_locked(&dev_priv->irq_lock);
377
378 if ((pipestat & mask) == 0)
379 return;
380
381 pipestat &= ~mask;
382 I915_WRITE(reg, pipestat);
383 POSTING_READ(reg);
384 }
385
386 /**
387 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
388 */
389 static void i915_enable_asle_pipestat(struct drm_device *dev)
390 {
391 drm_i915_private_t *dev_priv = dev->dev_private;
392 unsigned long irqflags;
393
394 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
395 return;
396
397 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
398
399 i915_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE);
400 if (INTEL_INFO(dev)->gen >= 4)
401 i915_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE);
402
403 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
404 }
405
406 /**
407 * i915_pipe_enabled - check if a pipe is enabled
408 * @dev: DRM device
409 * @pipe: pipe to check
410 *
411 * Reading certain registers when the pipe is disabled can hang the chip.
412 * Use this routine to make sure the PLL is running and the pipe is active
413 * before reading such registers if unsure.
414 */
415 static int
416 i915_pipe_enabled(struct drm_device *dev, int pipe)
417 {
418 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
419
420 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
421 /* Locking is horribly broken here, but whatever. */
422 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
423 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
424
425 return intel_crtc->active;
426 } else {
427 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
428 }
429 }
430
431 /* Called from drm generic code, passed a 'crtc', which
432 * we use as a pipe index
433 */
434 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
435 {
436 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
437 unsigned long high_frame;
438 unsigned long low_frame;
439 u32 high1, high2, low;
440
441 if (!i915_pipe_enabled(dev, pipe)) {
442 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
443 "pipe %c\n", pipe_name(pipe));
444 return 0;
445 }
446
447 high_frame = PIPEFRAME(pipe);
448 low_frame = PIPEFRAMEPIXEL(pipe);
449
450 /*
451 * High & low register fields aren't synchronized, so make sure
452 * we get a low value that's stable across two reads of the high
453 * register.
454 */
455 do {
456 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
457 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
458 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
459 } while (high1 != high2);
460
461 high1 >>= PIPE_FRAME_HIGH_SHIFT;
462 low >>= PIPE_FRAME_LOW_SHIFT;
463 return (high1 << 8) | low;
464 }
465
466 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
467 {
468 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
469 int reg = PIPE_FRMCOUNT_GM45(pipe);
470
471 if (!i915_pipe_enabled(dev, pipe)) {
472 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
473 "pipe %c\n", pipe_name(pipe));
474 return 0;
475 }
476
477 return I915_READ(reg);
478 }
479
480 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
481 int *vpos, int *hpos)
482 {
483 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
484 u32 vbl = 0, position = 0;
485 int vbl_start, vbl_end, htotal, vtotal;
486 bool in_vbl = true;
487 int ret = 0;
488 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
489 pipe);
490
491 if (!i915_pipe_enabled(dev, pipe)) {
492 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
493 "pipe %c\n", pipe_name(pipe));
494 return 0;
495 }
496
497 /* Get vtotal. */
498 vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
499
500 if (INTEL_INFO(dev)->gen >= 4) {
501 /* No obvious pixelcount register. Only query vertical
502 * scanout position from Display scan line register.
503 */
504 position = I915_READ(PIPEDSL(pipe));
505
506 /* Decode into vertical scanout position. Don't have
507 * horizontal scanout position.
508 */
509 *vpos = position & 0x1fff;
510 *hpos = 0;
511 } else {
512 /* Have access to pixelcount since start of frame.
513 * We can split this into vertical and horizontal
514 * scanout position.
515 */
516 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
517
518 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
519 *vpos = position / htotal;
520 *hpos = position - (*vpos * htotal);
521 }
522
523 /* Query vblank area. */
524 vbl = I915_READ(VBLANK(cpu_transcoder));
525
526 /* Test position against vblank region. */
527 vbl_start = vbl & 0x1fff;
528 vbl_end = (vbl >> 16) & 0x1fff;
529
530 if ((*vpos < vbl_start) || (*vpos > vbl_end))
531 in_vbl = false;
532
533 /* Inside "upper part" of vblank area? Apply corrective offset: */
534 if (in_vbl && (*vpos >= vbl_start))
535 *vpos = *vpos - vtotal;
536
537 /* Readouts valid? */
538 if (vbl > 0)
539 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
540
541 /* In vblank? */
542 if (in_vbl)
543 ret |= DRM_SCANOUTPOS_INVBL;
544
545 return ret;
546 }
547
548 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
549 int *max_error,
550 struct timeval *vblank_time,
551 unsigned flags)
552 {
553 struct drm_crtc *crtc;
554
555 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
556 DRM_ERROR("Invalid crtc %d\n", pipe);
557 return -EINVAL;
558 }
559
560 /* Get drm_crtc to timestamp: */
561 crtc = intel_get_crtc_for_pipe(dev, pipe);
562 if (crtc == NULL) {
563 DRM_ERROR("Invalid crtc %d\n", pipe);
564 return -EINVAL;
565 }
566
567 if (!crtc->enabled) {
568 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
569 return -EBUSY;
570 }
571
572 /* Helper routine in DRM core does all the work: */
573 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
574 vblank_time, flags,
575 crtc);
576 }
577
578 static int intel_hpd_irq_event(struct drm_device *dev, struct drm_connector *connector)
579 {
580 enum drm_connector_status old_status;
581
582 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
583 old_status = connector->status;
584
585 connector->status = connector->funcs->detect(connector, false);
586 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
587 connector->base.id,
588 drm_get_connector_name(connector),
589 old_status, connector->status);
590 return (old_status != connector->status);
591 }
592
593 /*
594 * Handle hotplug events outside the interrupt handler proper.
595 */
596 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
597
598 static void i915_hotplug_work_func(struct work_struct *work)
599 {
600 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
601 hotplug_work);
602 struct drm_device *dev = dev_priv->dev;
603 struct drm_mode_config *mode_config = &dev->mode_config;
604 struct intel_connector *intel_connector;
605 struct intel_encoder *intel_encoder;
606 struct drm_connector *connector;
607 unsigned long irqflags;
608 bool hpd_disabled = false;
609 bool changed = false;
610 u32 hpd_event_bits;
611
612 /* HPD irq before everything is fully set up. */
613 if (!dev_priv->enable_hotplug_processing)
614 return;
615
616 mutex_lock(&mode_config->mutex);
617 DRM_DEBUG_KMS("running encoder hotplug functions\n");
618
619 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
620
621 hpd_event_bits = dev_priv->hpd_event_bits;
622 dev_priv->hpd_event_bits = 0;
623 list_for_each_entry(connector, &mode_config->connector_list, head) {
624 intel_connector = to_intel_connector(connector);
625 intel_encoder = intel_connector->encoder;
626 if (intel_encoder->hpd_pin > HPD_NONE &&
627 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
628 connector->polled == DRM_CONNECTOR_POLL_HPD) {
629 DRM_INFO("HPD interrupt storm detected on connector %s: "
630 "switching from hotplug detection to polling\n",
631 drm_get_connector_name(connector));
632 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
633 connector->polled = DRM_CONNECTOR_POLL_CONNECT
634 | DRM_CONNECTOR_POLL_DISCONNECT;
635 hpd_disabled = true;
636 }
637 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
638 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
639 drm_get_connector_name(connector), intel_encoder->hpd_pin);
640 }
641 }
642 /* if there were no outputs to poll, poll was disabled,
643 * therefore make sure it's enabled when disabling HPD on
644 * some connectors */
645 if (hpd_disabled) {
646 drm_kms_helper_poll_enable(dev);
647 mod_timer(&dev_priv->hotplug_reenable_timer,
648 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
649 }
650
651 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
652
653 list_for_each_entry(connector, &mode_config->connector_list, head) {
654 intel_connector = to_intel_connector(connector);
655 intel_encoder = intel_connector->encoder;
656 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
657 if (intel_encoder->hot_plug)
658 intel_encoder->hot_plug(intel_encoder);
659 if (intel_hpd_irq_event(dev, connector))
660 changed = true;
661 }
662 }
663 mutex_unlock(&mode_config->mutex);
664
665 if (changed)
666 drm_kms_helper_hotplug_event(dev);
667 }
668
669 static void ironlake_handle_rps_change(struct drm_device *dev)
670 {
671 drm_i915_private_t *dev_priv = dev->dev_private;
672 u32 busy_up, busy_down, max_avg, min_avg;
673 u8 new_delay;
674 unsigned long flags;
675
676 spin_lock_irqsave(&mchdev_lock, flags);
677
678 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
679
680 new_delay = dev_priv->ips.cur_delay;
681
682 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
683 busy_up = I915_READ(RCPREVBSYTUPAVG);
684 busy_down = I915_READ(RCPREVBSYTDNAVG);
685 max_avg = I915_READ(RCBMAXAVG);
686 min_avg = I915_READ(RCBMINAVG);
687
688 /* Handle RCS change request from hw */
689 if (busy_up > max_avg) {
690 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
691 new_delay = dev_priv->ips.cur_delay - 1;
692 if (new_delay < dev_priv->ips.max_delay)
693 new_delay = dev_priv->ips.max_delay;
694 } else if (busy_down < min_avg) {
695 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
696 new_delay = dev_priv->ips.cur_delay + 1;
697 if (new_delay > dev_priv->ips.min_delay)
698 new_delay = dev_priv->ips.min_delay;
699 }
700
701 if (ironlake_set_drps(dev, new_delay))
702 dev_priv->ips.cur_delay = new_delay;
703
704 spin_unlock_irqrestore(&mchdev_lock, flags);
705
706 return;
707 }
708
709 static void notify_ring(struct drm_device *dev,
710 struct intel_ring_buffer *ring)
711 {
712 struct drm_i915_private *dev_priv = dev->dev_private;
713
714 if (ring->obj == NULL)
715 return;
716
717 trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
718
719 wake_up_all(&ring->irq_queue);
720 if (i915_enable_hangcheck) {
721 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
722 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
723 }
724 }
725
726 static void gen6_pm_rps_work(struct work_struct *work)
727 {
728 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
729 rps.work);
730 u32 pm_iir, pm_imr;
731 u8 new_delay;
732
733 spin_lock_irq(&dev_priv->rps.lock);
734 pm_iir = dev_priv->rps.pm_iir;
735 dev_priv->rps.pm_iir = 0;
736 pm_imr = I915_READ(GEN6_PMIMR);
737 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
738 I915_WRITE(GEN6_PMIMR, pm_imr & ~GEN6_PM_RPS_EVENTS);
739 spin_unlock_irq(&dev_priv->rps.lock);
740
741 if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
742 return;
743
744 mutex_lock(&dev_priv->rps.hw_lock);
745
746 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
747 new_delay = dev_priv->rps.cur_delay + 1;
748
749 /*
750 * For better performance, jump directly
751 * to RPe if we're below it.
752 */
753 if (IS_VALLEYVIEW(dev_priv->dev) &&
754 dev_priv->rps.cur_delay < dev_priv->rps.rpe_delay)
755 new_delay = dev_priv->rps.rpe_delay;
756 } else
757 new_delay = dev_priv->rps.cur_delay - 1;
758
759 /* sysfs frequency interfaces may have snuck in while servicing the
760 * interrupt
761 */
762 if (new_delay >= dev_priv->rps.min_delay &&
763 new_delay <= dev_priv->rps.max_delay) {
764 if (IS_VALLEYVIEW(dev_priv->dev))
765 valleyview_set_rps(dev_priv->dev, new_delay);
766 else
767 gen6_set_rps(dev_priv->dev, new_delay);
768 }
769
770 if (IS_VALLEYVIEW(dev_priv->dev)) {
771 /*
772 * On VLV, when we enter RC6 we may not be at the minimum
773 * voltage level, so arm a timer to check. It should only
774 * fire when there's activity or once after we've entered
775 * RC6, and then won't be re-armed until the next RPS interrupt.
776 */
777 mod_delayed_work(dev_priv->wq, &dev_priv->rps.vlv_work,
778 msecs_to_jiffies(100));
779 }
780
781 mutex_unlock(&dev_priv->rps.hw_lock);
782 }
783
784
785 /**
786 * ivybridge_parity_work - Workqueue called when a parity error interrupt
787 * occurred.
788 * @work: workqueue struct
789 *
790 * Doesn't actually do anything except notify userspace. As a consequence of
791 * this event, userspace should try to remap the bad rows since statistically
792 * it is likely the same row is more likely to go bad again.
793 */
794 static void ivybridge_parity_work(struct work_struct *work)
795 {
796 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
797 l3_parity.error_work);
798 u32 error_status, row, bank, subbank;
799 char *parity_event[5];
800 uint32_t misccpctl;
801 unsigned long flags;
802
803 /* We must turn off DOP level clock gating to access the L3 registers.
804 * In order to prevent a get/put style interface, acquire struct mutex
805 * any time we access those registers.
806 */
807 mutex_lock(&dev_priv->dev->struct_mutex);
808
809 misccpctl = I915_READ(GEN7_MISCCPCTL);
810 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
811 POSTING_READ(GEN7_MISCCPCTL);
812
813 error_status = I915_READ(GEN7_L3CDERRST1);
814 row = GEN7_PARITY_ERROR_ROW(error_status);
815 bank = GEN7_PARITY_ERROR_BANK(error_status);
816 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
817
818 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
819 GEN7_L3CDERRST1_ENABLE);
820 POSTING_READ(GEN7_L3CDERRST1);
821
822 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
823
824 spin_lock_irqsave(&dev_priv->irq_lock, flags);
825 dev_priv->gt_irq_mask &= ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
826 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
827 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
828
829 mutex_unlock(&dev_priv->dev->struct_mutex);
830
831 parity_event[0] = "L3_PARITY_ERROR=1";
832 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
833 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
834 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
835 parity_event[4] = NULL;
836
837 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
838 KOBJ_CHANGE, parity_event);
839
840 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
841 row, bank, subbank);
842
843 kfree(parity_event[3]);
844 kfree(parity_event[2]);
845 kfree(parity_event[1]);
846 }
847
848 static void ivybridge_handle_parity_error(struct drm_device *dev)
849 {
850 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
851 unsigned long flags;
852
853 if (!HAS_L3_GPU_CACHE(dev))
854 return;
855
856 spin_lock_irqsave(&dev_priv->irq_lock, flags);
857 dev_priv->gt_irq_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
858 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
859 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
860
861 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
862 }
863
864 static void snb_gt_irq_handler(struct drm_device *dev,
865 struct drm_i915_private *dev_priv,
866 u32 gt_iir)
867 {
868
869 if (gt_iir &
870 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
871 notify_ring(dev, &dev_priv->ring[RCS]);
872 if (gt_iir & GT_BSD_USER_INTERRUPT)
873 notify_ring(dev, &dev_priv->ring[VCS]);
874 if (gt_iir & GT_BLT_USER_INTERRUPT)
875 notify_ring(dev, &dev_priv->ring[BCS]);
876
877 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
878 GT_BSD_CS_ERROR_INTERRUPT |
879 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
880 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
881 i915_handle_error(dev, false);
882 }
883
884 if (gt_iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
885 ivybridge_handle_parity_error(dev);
886 }
887
888 /* Legacy way of handling PM interrupts */
889 static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
890 u32 pm_iir)
891 {
892 unsigned long flags;
893
894 /*
895 * IIR bits should never already be set because IMR should
896 * prevent an interrupt from being shown in IIR. The warning
897 * displays a case where we've unsafely cleared
898 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
899 * type is not a problem, it displays a problem in the logic.
900 *
901 * The mask bit in IMR is cleared by dev_priv->rps.work.
902 */
903
904 spin_lock_irqsave(&dev_priv->rps.lock, flags);
905 dev_priv->rps.pm_iir |= pm_iir;
906 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
907 POSTING_READ(GEN6_PMIMR);
908 spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
909
910 queue_work(dev_priv->wq, &dev_priv->rps.work);
911 }
912
913 #define HPD_STORM_DETECT_PERIOD 1000
914 #define HPD_STORM_THRESHOLD 5
915
916 static inline void intel_hpd_irq_handler(struct drm_device *dev,
917 u32 hotplug_trigger,
918 const u32 *hpd)
919 {
920 drm_i915_private_t *dev_priv = dev->dev_private;
921 int i;
922 bool storm_detected = false;
923
924 if (!hotplug_trigger)
925 return;
926
927 spin_lock(&dev_priv->irq_lock);
928 for (i = 1; i < HPD_NUM_PINS; i++) {
929
930 if (!(hpd[i] & hotplug_trigger) ||
931 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
932 continue;
933
934 dev_priv->hpd_event_bits |= (1 << i);
935 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
936 dev_priv->hpd_stats[i].hpd_last_jiffies
937 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
938 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
939 dev_priv->hpd_stats[i].hpd_cnt = 0;
940 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
941 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
942 dev_priv->hpd_event_bits &= ~(1 << i);
943 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
944 storm_detected = true;
945 } else {
946 dev_priv->hpd_stats[i].hpd_cnt++;
947 }
948 }
949
950 if (storm_detected)
951 dev_priv->display.hpd_irq_setup(dev);
952 spin_unlock(&dev_priv->irq_lock);
953
954 queue_work(dev_priv->wq,
955 &dev_priv->hotplug_work);
956 }
957
958 static void gmbus_irq_handler(struct drm_device *dev)
959 {
960 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
961
962 wake_up_all(&dev_priv->gmbus_wait_queue);
963 }
964
965 static void dp_aux_irq_handler(struct drm_device *dev)
966 {
967 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
968
969 wake_up_all(&dev_priv->gmbus_wait_queue);
970 }
971
972 /* Unlike gen6_queue_rps_work() from which this function is originally derived,
973 * we must be able to deal with other PM interrupts. This is complicated because
974 * of the way in which we use the masks to defer the RPS work (which for
975 * posterity is necessary because of forcewake).
976 */
977 static void hsw_pm_irq_handler(struct drm_i915_private *dev_priv,
978 u32 pm_iir)
979 {
980 unsigned long flags;
981
982 spin_lock_irqsave(&dev_priv->rps.lock, flags);
983 dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
984 if (dev_priv->rps.pm_iir) {
985 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
986 /* never want to mask useful interrupts. (also posting read) */
987 WARN_ON(I915_READ_NOTRACE(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS);
988 /* TODO: if queue_work is slow, move it out of the spinlock */
989 queue_work(dev_priv->wq, &dev_priv->rps.work);
990 }
991 spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
992
993 if (pm_iir & ~GEN6_PM_RPS_EVENTS) {
994 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
995 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
996
997 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
998 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
999 i915_handle_error(dev_priv->dev, false);
1000 }
1001 }
1002 }
1003
1004 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1005 {
1006 struct drm_device *dev = (struct drm_device *) arg;
1007 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1008 u32 iir, gt_iir, pm_iir;
1009 irqreturn_t ret = IRQ_NONE;
1010 unsigned long irqflags;
1011 int pipe;
1012 u32 pipe_stats[I915_MAX_PIPES];
1013
1014 atomic_inc(&dev_priv->irq_received);
1015
1016 while (true) {
1017 iir = I915_READ(VLV_IIR);
1018 gt_iir = I915_READ(GTIIR);
1019 pm_iir = I915_READ(GEN6_PMIIR);
1020
1021 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1022 goto out;
1023
1024 ret = IRQ_HANDLED;
1025
1026 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1027
1028 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1029 for_each_pipe(pipe) {
1030 int reg = PIPESTAT(pipe);
1031 pipe_stats[pipe] = I915_READ(reg);
1032
1033 /*
1034 * Clear the PIPE*STAT regs before the IIR
1035 */
1036 if (pipe_stats[pipe] & 0x8000ffff) {
1037 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1038 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1039 pipe_name(pipe));
1040 I915_WRITE(reg, pipe_stats[pipe]);
1041 }
1042 }
1043 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1044
1045 for_each_pipe(pipe) {
1046 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1047 drm_handle_vblank(dev, pipe);
1048
1049 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
1050 intel_prepare_page_flip(dev, pipe);
1051 intel_finish_page_flip(dev, pipe);
1052 }
1053 }
1054
1055 /* Consume port. Then clear IIR or we'll miss events */
1056 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
1057 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1058 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1059
1060 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1061 hotplug_status);
1062
1063 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1064
1065 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1066 I915_READ(PORT_HOTPLUG_STAT);
1067 }
1068
1069 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1070 gmbus_irq_handler(dev);
1071
1072 if (pm_iir & GEN6_PM_RPS_EVENTS)
1073 gen6_queue_rps_work(dev_priv, pm_iir);
1074
1075 I915_WRITE(GTIIR, gt_iir);
1076 I915_WRITE(GEN6_PMIIR, pm_iir);
1077 I915_WRITE(VLV_IIR, iir);
1078 }
1079
1080 out:
1081 return ret;
1082 }
1083
1084 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1085 {
1086 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1087 int pipe;
1088 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1089
1090 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1091
1092 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1093 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1094 SDE_AUDIO_POWER_SHIFT);
1095 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1096 port_name(port));
1097 }
1098
1099 if (pch_iir & SDE_AUX_MASK)
1100 dp_aux_irq_handler(dev);
1101
1102 if (pch_iir & SDE_GMBUS)
1103 gmbus_irq_handler(dev);
1104
1105 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1106 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1107
1108 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1109 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1110
1111 if (pch_iir & SDE_POISON)
1112 DRM_ERROR("PCH poison interrupt\n");
1113
1114 if (pch_iir & SDE_FDI_MASK)
1115 for_each_pipe(pipe)
1116 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1117 pipe_name(pipe),
1118 I915_READ(FDI_RX_IIR(pipe)));
1119
1120 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1121 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1122
1123 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1124 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1125
1126 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1127 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1128 false))
1129 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1130
1131 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1132 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1133 false))
1134 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1135 }
1136
1137 static void ivb_err_int_handler(struct drm_device *dev)
1138 {
1139 struct drm_i915_private *dev_priv = dev->dev_private;
1140 u32 err_int = I915_READ(GEN7_ERR_INT);
1141
1142 if (err_int & ERR_INT_POISON)
1143 DRM_ERROR("Poison interrupt\n");
1144
1145 if (err_int & ERR_INT_FIFO_UNDERRUN_A)
1146 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1147 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1148
1149 if (err_int & ERR_INT_FIFO_UNDERRUN_B)
1150 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1151 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1152
1153 if (err_int & ERR_INT_FIFO_UNDERRUN_C)
1154 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false))
1155 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1156
1157 I915_WRITE(GEN7_ERR_INT, err_int);
1158 }
1159
1160 static void cpt_serr_int_handler(struct drm_device *dev)
1161 {
1162 struct drm_i915_private *dev_priv = dev->dev_private;
1163 u32 serr_int = I915_READ(SERR_INT);
1164
1165 if (serr_int & SERR_INT_POISON)
1166 DRM_ERROR("PCH poison interrupt\n");
1167
1168 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1169 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1170 false))
1171 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1172
1173 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1174 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1175 false))
1176 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1177
1178 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1179 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1180 false))
1181 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1182
1183 I915_WRITE(SERR_INT, serr_int);
1184 }
1185
1186 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1187 {
1188 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1189 int pipe;
1190 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1191
1192 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1193
1194 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1195 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1196 SDE_AUDIO_POWER_SHIFT_CPT);
1197 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1198 port_name(port));
1199 }
1200
1201 if (pch_iir & SDE_AUX_MASK_CPT)
1202 dp_aux_irq_handler(dev);
1203
1204 if (pch_iir & SDE_GMBUS_CPT)
1205 gmbus_irq_handler(dev);
1206
1207 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1208 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1209
1210 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1211 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1212
1213 if (pch_iir & SDE_FDI_MASK_CPT)
1214 for_each_pipe(pipe)
1215 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1216 pipe_name(pipe),
1217 I915_READ(FDI_RX_IIR(pipe)));
1218
1219 if (pch_iir & SDE_ERROR_CPT)
1220 cpt_serr_int_handler(dev);
1221 }
1222
1223 static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
1224 {
1225 struct drm_device *dev = (struct drm_device *) arg;
1226 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1227 u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier = 0;
1228 irqreturn_t ret = IRQ_NONE;
1229 int i;
1230
1231 atomic_inc(&dev_priv->irq_received);
1232
1233 /* We get interrupts on unclaimed registers, so check for this before we
1234 * do any I915_{READ,WRITE}. */
1235 if (IS_HASWELL(dev) &&
1236 (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1237 DRM_ERROR("Unclaimed register before interrupt\n");
1238 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1239 }
1240
1241 /* disable master interrupt before clearing iir */
1242 de_ier = I915_READ(DEIER);
1243 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
1244
1245 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1246 * interrupts will will be stored on its back queue, and then we'll be
1247 * able to process them after we restore SDEIER (as soon as we restore
1248 * it, we'll get an interrupt if SDEIIR still has something to process
1249 * due to its back queue). */
1250 if (!HAS_PCH_NOP(dev)) {
1251 sde_ier = I915_READ(SDEIER);
1252 I915_WRITE(SDEIER, 0);
1253 POSTING_READ(SDEIER);
1254 }
1255
1256 /* On Haswell, also mask ERR_INT because we don't want to risk
1257 * generating "unclaimed register" interrupts from inside the interrupt
1258 * handler. */
1259 if (IS_HASWELL(dev)) {
1260 spin_lock(&dev_priv->irq_lock);
1261 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
1262 spin_unlock(&dev_priv->irq_lock);
1263 }
1264
1265 gt_iir = I915_READ(GTIIR);
1266 if (gt_iir) {
1267 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1268 I915_WRITE(GTIIR, gt_iir);
1269 ret = IRQ_HANDLED;
1270 }
1271
1272 de_iir = I915_READ(DEIIR);
1273 if (de_iir) {
1274 if (de_iir & DE_ERR_INT_IVB)
1275 ivb_err_int_handler(dev);
1276
1277 if (de_iir & DE_AUX_CHANNEL_A_IVB)
1278 dp_aux_irq_handler(dev);
1279
1280 if (de_iir & DE_GSE_IVB)
1281 intel_opregion_asle_intr(dev);
1282
1283 for (i = 0; i < 3; i++) {
1284 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
1285 drm_handle_vblank(dev, i);
1286 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
1287 intel_prepare_page_flip(dev, i);
1288 intel_finish_page_flip_plane(dev, i);
1289 }
1290 }
1291
1292 /* check event from PCH */
1293 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1294 u32 pch_iir = I915_READ(SDEIIR);
1295
1296 cpt_irq_handler(dev, pch_iir);
1297
1298 /* clear PCH hotplug event before clear CPU irq */
1299 I915_WRITE(SDEIIR, pch_iir);
1300 }
1301
1302 I915_WRITE(DEIIR, de_iir);
1303 ret = IRQ_HANDLED;
1304 }
1305
1306 pm_iir = I915_READ(GEN6_PMIIR);
1307 if (pm_iir) {
1308 if (IS_HASWELL(dev))
1309 hsw_pm_irq_handler(dev_priv, pm_iir);
1310 else if (pm_iir & GEN6_PM_RPS_EVENTS)
1311 gen6_queue_rps_work(dev_priv, pm_iir);
1312 I915_WRITE(GEN6_PMIIR, pm_iir);
1313 ret = IRQ_HANDLED;
1314 }
1315
1316 if (IS_HASWELL(dev)) {
1317 spin_lock(&dev_priv->irq_lock);
1318 if (ivb_can_enable_err_int(dev))
1319 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
1320 spin_unlock(&dev_priv->irq_lock);
1321 }
1322
1323 I915_WRITE(DEIER, de_ier);
1324 POSTING_READ(DEIER);
1325 if (!HAS_PCH_NOP(dev)) {
1326 I915_WRITE(SDEIER, sde_ier);
1327 POSTING_READ(SDEIER);
1328 }
1329
1330 return ret;
1331 }
1332
1333 static void ilk_gt_irq_handler(struct drm_device *dev,
1334 struct drm_i915_private *dev_priv,
1335 u32 gt_iir)
1336 {
1337 if (gt_iir &
1338 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1339 notify_ring(dev, &dev_priv->ring[RCS]);
1340 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1341 notify_ring(dev, &dev_priv->ring[VCS]);
1342 }
1343
1344 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
1345 {
1346 struct drm_device *dev = (struct drm_device *) arg;
1347 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1348 int ret = IRQ_NONE;
1349 u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
1350
1351 atomic_inc(&dev_priv->irq_received);
1352
1353 /* disable master interrupt before clearing iir */
1354 de_ier = I915_READ(DEIER);
1355 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
1356 POSTING_READ(DEIER);
1357
1358 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1359 * interrupts will will be stored on its back queue, and then we'll be
1360 * able to process them after we restore SDEIER (as soon as we restore
1361 * it, we'll get an interrupt if SDEIIR still has something to process
1362 * due to its back queue). */
1363 sde_ier = I915_READ(SDEIER);
1364 I915_WRITE(SDEIER, 0);
1365 POSTING_READ(SDEIER);
1366
1367 de_iir = I915_READ(DEIIR);
1368 gt_iir = I915_READ(GTIIR);
1369 pm_iir = I915_READ(GEN6_PMIIR);
1370
1371 if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
1372 goto done;
1373
1374 ret = IRQ_HANDLED;
1375
1376 if (IS_GEN5(dev))
1377 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1378 else
1379 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1380
1381 if (de_iir & DE_AUX_CHANNEL_A)
1382 dp_aux_irq_handler(dev);
1383
1384 if (de_iir & DE_GSE)
1385 intel_opregion_asle_intr(dev);
1386
1387 if (de_iir & DE_PIPEA_VBLANK)
1388 drm_handle_vblank(dev, 0);
1389
1390 if (de_iir & DE_PIPEB_VBLANK)
1391 drm_handle_vblank(dev, 1);
1392
1393 if (de_iir & DE_POISON)
1394 DRM_ERROR("Poison interrupt\n");
1395
1396 if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
1397 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1398 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1399
1400 if (de_iir & DE_PIPEB_FIFO_UNDERRUN)
1401 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1402 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1403
1404 if (de_iir & DE_PLANEA_FLIP_DONE) {
1405 intel_prepare_page_flip(dev, 0);
1406 intel_finish_page_flip_plane(dev, 0);
1407 }
1408
1409 if (de_iir & DE_PLANEB_FLIP_DONE) {
1410 intel_prepare_page_flip(dev, 1);
1411 intel_finish_page_flip_plane(dev, 1);
1412 }
1413
1414 /* check event from PCH */
1415 if (de_iir & DE_PCH_EVENT) {
1416 u32 pch_iir = I915_READ(SDEIIR);
1417
1418 if (HAS_PCH_CPT(dev))
1419 cpt_irq_handler(dev, pch_iir);
1420 else
1421 ibx_irq_handler(dev, pch_iir);
1422
1423 /* should clear PCH hotplug event before clear CPU irq */
1424 I915_WRITE(SDEIIR, pch_iir);
1425 }
1426
1427 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1428 ironlake_handle_rps_change(dev);
1429
1430 if (IS_GEN6(dev) && pm_iir & GEN6_PM_RPS_EVENTS)
1431 gen6_queue_rps_work(dev_priv, pm_iir);
1432
1433 I915_WRITE(GTIIR, gt_iir);
1434 I915_WRITE(DEIIR, de_iir);
1435 I915_WRITE(GEN6_PMIIR, pm_iir);
1436
1437 done:
1438 I915_WRITE(DEIER, de_ier);
1439 POSTING_READ(DEIER);
1440 I915_WRITE(SDEIER, sde_ier);
1441 POSTING_READ(SDEIER);
1442
1443 return ret;
1444 }
1445
1446 /**
1447 * i915_error_work_func - do process context error handling work
1448 * @work: work struct
1449 *
1450 * Fire an error uevent so userspace can see that a hang or error
1451 * was detected.
1452 */
1453 static void i915_error_work_func(struct work_struct *work)
1454 {
1455 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
1456 work);
1457 drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
1458 gpu_error);
1459 struct drm_device *dev = dev_priv->dev;
1460 struct intel_ring_buffer *ring;
1461 char *error_event[] = { "ERROR=1", NULL };
1462 char *reset_event[] = { "RESET=1", NULL };
1463 char *reset_done_event[] = { "ERROR=0", NULL };
1464 int i, ret;
1465
1466 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
1467
1468 /*
1469 * Note that there's only one work item which does gpu resets, so we
1470 * need not worry about concurrent gpu resets potentially incrementing
1471 * error->reset_counter twice. We only need to take care of another
1472 * racing irq/hangcheck declaring the gpu dead for a second time. A
1473 * quick check for that is good enough: schedule_work ensures the
1474 * correct ordering between hang detection and this work item, and since
1475 * the reset in-progress bit is only ever set by code outside of this
1476 * work we don't need to worry about any other races.
1477 */
1478 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
1479 DRM_DEBUG_DRIVER("resetting chip\n");
1480 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
1481 reset_event);
1482
1483 ret = i915_reset(dev);
1484
1485 if (ret == 0) {
1486 /*
1487 * After all the gem state is reset, increment the reset
1488 * counter and wake up everyone waiting for the reset to
1489 * complete.
1490 *
1491 * Since unlock operations are a one-sided barrier only,
1492 * we need to insert a barrier here to order any seqno
1493 * updates before
1494 * the counter increment.
1495 */
1496 smp_mb__before_atomic_inc();
1497 atomic_inc(&dev_priv->gpu_error.reset_counter);
1498
1499 kobject_uevent_env(&dev->primary->kdev.kobj,
1500 KOBJ_CHANGE, reset_done_event);
1501 } else {
1502 atomic_set(&error->reset_counter, I915_WEDGED);
1503 }
1504
1505 for_each_ring(ring, dev_priv, i)
1506 wake_up_all(&ring->irq_queue);
1507
1508 intel_display_handle_reset(dev);
1509
1510 wake_up_all(&dev_priv->gpu_error.reset_queue);
1511 }
1512 }
1513
1514 /* NB: please notice the memset */
1515 static void i915_get_extra_instdone(struct drm_device *dev,
1516 uint32_t *instdone)
1517 {
1518 struct drm_i915_private *dev_priv = dev->dev_private;
1519 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1520
1521 switch(INTEL_INFO(dev)->gen) {
1522 case 2:
1523 case 3:
1524 instdone[0] = I915_READ(INSTDONE);
1525 break;
1526 case 4:
1527 case 5:
1528 case 6:
1529 instdone[0] = I915_READ(INSTDONE_I965);
1530 instdone[1] = I915_READ(INSTDONE1);
1531 break;
1532 default:
1533 WARN_ONCE(1, "Unsupported platform\n");
1534 case 7:
1535 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1536 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1537 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1538 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1539 break;
1540 }
1541 }
1542
1543 #ifdef CONFIG_DEBUG_FS
1544 static struct drm_i915_error_object *
1545 i915_error_object_create_sized(struct drm_i915_private *dev_priv,
1546 struct drm_i915_gem_object *src,
1547 const int num_pages)
1548 {
1549 struct drm_i915_error_object *dst;
1550 int i;
1551 u32 reloc_offset;
1552
1553 if (src == NULL || src->pages == NULL)
1554 return NULL;
1555
1556 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
1557 if (dst == NULL)
1558 return NULL;
1559
1560 reloc_offset = dst->gtt_offset = i915_gem_obj_ggtt_offset(src);
1561 for (i = 0; i < num_pages; i++) {
1562 unsigned long flags;
1563 void *d;
1564
1565 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
1566 if (d == NULL)
1567 goto unwind;
1568
1569 local_irq_save(flags);
1570 if (reloc_offset < dev_priv->gtt.mappable_end &&
1571 src->has_global_gtt_mapping) {
1572 void __iomem *s;
1573
1574 /* Simply ignore tiling or any overlapping fence.
1575 * It's part of the error state, and this hopefully
1576 * captures what the GPU read.
1577 */
1578
1579 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
1580 reloc_offset);
1581 memcpy_fromio(d, s, PAGE_SIZE);
1582 io_mapping_unmap_atomic(s);
1583 } else if (src->stolen) {
1584 unsigned long offset;
1585
1586 offset = dev_priv->mm.stolen_base;
1587 offset += src->stolen->start;
1588 offset += i << PAGE_SHIFT;
1589
1590 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
1591 } else {
1592 struct page *page;
1593 void *s;
1594
1595 page = i915_gem_object_get_page(src, i);
1596
1597 drm_clflush_pages(&page, 1);
1598
1599 s = kmap_atomic(page);
1600 memcpy(d, s, PAGE_SIZE);
1601 kunmap_atomic(s);
1602
1603 drm_clflush_pages(&page, 1);
1604 }
1605 local_irq_restore(flags);
1606
1607 dst->pages[i] = d;
1608
1609 reloc_offset += PAGE_SIZE;
1610 }
1611 dst->page_count = num_pages;
1612
1613 return dst;
1614
1615 unwind:
1616 while (i--)
1617 kfree(dst->pages[i]);
1618 kfree(dst);
1619 return NULL;
1620 }
1621 #define i915_error_object_create(dev_priv, src) \
1622 i915_error_object_create_sized((dev_priv), (src), \
1623 (src)->base.size>>PAGE_SHIFT)
1624
1625 static void
1626 i915_error_object_free(struct drm_i915_error_object *obj)
1627 {
1628 int page;
1629
1630 if (obj == NULL)
1631 return;
1632
1633 for (page = 0; page < obj->page_count; page++)
1634 kfree(obj->pages[page]);
1635
1636 kfree(obj);
1637 }
1638
1639 void
1640 i915_error_state_free(struct kref *error_ref)
1641 {
1642 struct drm_i915_error_state *error = container_of(error_ref,
1643 typeof(*error), ref);
1644 int i;
1645
1646 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
1647 i915_error_object_free(error->ring[i].batchbuffer);
1648 i915_error_object_free(error->ring[i].ringbuffer);
1649 i915_error_object_free(error->ring[i].ctx);
1650 kfree(error->ring[i].requests);
1651 }
1652
1653 kfree(error->active_bo);
1654 kfree(error->overlay);
1655 kfree(error->display);
1656 kfree(error);
1657 }
1658 static void capture_bo(struct drm_i915_error_buffer *err,
1659 struct drm_i915_gem_object *obj)
1660 {
1661 err->size = obj->base.size;
1662 err->name = obj->base.name;
1663 err->rseqno = obj->last_read_seqno;
1664 err->wseqno = obj->last_write_seqno;
1665 err->gtt_offset = i915_gem_obj_ggtt_offset(obj);
1666 err->read_domains = obj->base.read_domains;
1667 err->write_domain = obj->base.write_domain;
1668 err->fence_reg = obj->fence_reg;
1669 err->pinned = 0;
1670 if (obj->pin_count > 0)
1671 err->pinned = 1;
1672 if (obj->user_pin_count > 0)
1673 err->pinned = -1;
1674 err->tiling = obj->tiling_mode;
1675 err->dirty = obj->dirty;
1676 err->purgeable = obj->madv != I915_MADV_WILLNEED;
1677 err->ring = obj->ring ? obj->ring->id : -1;
1678 err->cache_level = obj->cache_level;
1679 }
1680
1681 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1682 int count, struct list_head *head)
1683 {
1684 struct drm_i915_gem_object *obj;
1685 int i = 0;
1686
1687 list_for_each_entry(obj, head, mm_list) {
1688 capture_bo(err++, obj);
1689 if (++i == count)
1690 break;
1691 }
1692
1693 return i;
1694 }
1695
1696 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1697 int count, struct list_head *head)
1698 {
1699 struct drm_i915_gem_object *obj;
1700 int i = 0;
1701
1702 list_for_each_entry(obj, head, global_list) {
1703 if (obj->pin_count == 0)
1704 continue;
1705
1706 capture_bo(err++, obj);
1707 if (++i == count)
1708 break;
1709 }
1710
1711 return i;
1712 }
1713
1714 static void i915_gem_record_fences(struct drm_device *dev,
1715 struct drm_i915_error_state *error)
1716 {
1717 struct drm_i915_private *dev_priv = dev->dev_private;
1718 int i;
1719
1720 /* Fences */
1721 switch (INTEL_INFO(dev)->gen) {
1722 case 7:
1723 case 6:
1724 for (i = 0; i < dev_priv->num_fence_regs; i++)
1725 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1726 break;
1727 case 5:
1728 case 4:
1729 for (i = 0; i < 16; i++)
1730 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1731 break;
1732 case 3:
1733 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1734 for (i = 0; i < 8; i++)
1735 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1736 case 2:
1737 for (i = 0; i < 8; i++)
1738 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1739 break;
1740
1741 default:
1742 BUG();
1743 }
1744 }
1745
1746 static struct drm_i915_error_object *
1747 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1748 struct intel_ring_buffer *ring)
1749 {
1750 struct drm_i915_gem_object *obj;
1751 u32 seqno;
1752
1753 if (!ring->get_seqno)
1754 return NULL;
1755
1756 if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
1757 u32 acthd = I915_READ(ACTHD);
1758
1759 if (WARN_ON(ring->id != RCS))
1760 return NULL;
1761
1762 obj = ring->private;
1763 if (acthd >= i915_gem_obj_ggtt_offset(obj) &&
1764 acthd < i915_gem_obj_ggtt_offset(obj) + obj->base.size)
1765 return i915_error_object_create(dev_priv, obj);
1766 }
1767
1768 seqno = ring->get_seqno(ring, false);
1769 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1770 if (obj->ring != ring)
1771 continue;
1772
1773 if (i915_seqno_passed(seqno, obj->last_read_seqno))
1774 continue;
1775
1776 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1777 continue;
1778
1779 /* We need to copy these to an anonymous buffer as the simplest
1780 * method to avoid being overwritten by userspace.
1781 */
1782 return i915_error_object_create(dev_priv, obj);
1783 }
1784
1785 return NULL;
1786 }
1787
1788 static void i915_record_ring_state(struct drm_device *dev,
1789 struct drm_i915_error_state *error,
1790 struct intel_ring_buffer *ring)
1791 {
1792 struct drm_i915_private *dev_priv = dev->dev_private;
1793
1794 if (INTEL_INFO(dev)->gen >= 6) {
1795 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
1796 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
1797 error->semaphore_mboxes[ring->id][0]
1798 = I915_READ(RING_SYNC_0(ring->mmio_base));
1799 error->semaphore_mboxes[ring->id][1]
1800 = I915_READ(RING_SYNC_1(ring->mmio_base));
1801 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
1802 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
1803 }
1804
1805 if (INTEL_INFO(dev)->gen >= 4) {
1806 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
1807 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1808 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1809 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
1810 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
1811 if (ring->id == RCS)
1812 error->bbaddr = I915_READ64(BB_ADDR);
1813 } else {
1814 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
1815 error->ipeir[ring->id] = I915_READ(IPEIR);
1816 error->ipehr[ring->id] = I915_READ(IPEHR);
1817 error->instdone[ring->id] = I915_READ(INSTDONE);
1818 }
1819
1820 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
1821 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
1822 error->seqno[ring->id] = ring->get_seqno(ring, false);
1823 error->acthd[ring->id] = intel_ring_get_active_head(ring);
1824 error->head[ring->id] = I915_READ_HEAD(ring);
1825 error->tail[ring->id] = I915_READ_TAIL(ring);
1826 error->ctl[ring->id] = I915_READ_CTL(ring);
1827
1828 error->cpu_ring_head[ring->id] = ring->head;
1829 error->cpu_ring_tail[ring->id] = ring->tail;
1830 }
1831
1832
1833 static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
1834 struct drm_i915_error_state *error,
1835 struct drm_i915_error_ring *ering)
1836 {
1837 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1838 struct drm_i915_gem_object *obj;
1839
1840 /* Currently render ring is the only HW context user */
1841 if (ring->id != RCS || !error->ccid)
1842 return;
1843
1844 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1845 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
1846 ering->ctx = i915_error_object_create_sized(dev_priv,
1847 obj, 1);
1848 break;
1849 }
1850 }
1851 }
1852
1853 static void i915_gem_record_rings(struct drm_device *dev,
1854 struct drm_i915_error_state *error)
1855 {
1856 struct drm_i915_private *dev_priv = dev->dev_private;
1857 struct intel_ring_buffer *ring;
1858 struct drm_i915_gem_request *request;
1859 int i, count;
1860
1861 for_each_ring(ring, dev_priv, i) {
1862 i915_record_ring_state(dev, error, ring);
1863
1864 error->ring[i].batchbuffer =
1865 i915_error_first_batchbuffer(dev_priv, ring);
1866
1867 error->ring[i].ringbuffer =
1868 i915_error_object_create(dev_priv, ring->obj);
1869
1870
1871 i915_gem_record_active_context(ring, error, &error->ring[i]);
1872
1873 count = 0;
1874 list_for_each_entry(request, &ring->request_list, list)
1875 count++;
1876
1877 error->ring[i].num_requests = count;
1878 error->ring[i].requests =
1879 kmalloc(count*sizeof(struct drm_i915_error_request),
1880 GFP_ATOMIC);
1881 if (error->ring[i].requests == NULL) {
1882 error->ring[i].num_requests = 0;
1883 continue;
1884 }
1885
1886 count = 0;
1887 list_for_each_entry(request, &ring->request_list, list) {
1888 struct drm_i915_error_request *erq;
1889
1890 erq = &error->ring[i].requests[count++];
1891 erq->seqno = request->seqno;
1892 erq->jiffies = request->emitted_jiffies;
1893 erq->tail = request->tail;
1894 }
1895 }
1896 }
1897
1898 static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
1899 struct drm_i915_error_state *error)
1900 {
1901 struct drm_i915_gem_object *obj;
1902 int i;
1903
1904 i = 0;
1905 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1906 i++;
1907 error->active_bo_count = i;
1908 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1909 if (obj->pin_count)
1910 i++;
1911 error->pinned_bo_count = i - error->active_bo_count;
1912
1913 if (i) {
1914 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
1915 GFP_ATOMIC);
1916 if (error->active_bo)
1917 error->pinned_bo =
1918 error->active_bo + error->active_bo_count;
1919 }
1920
1921 if (error->active_bo)
1922 error->active_bo_count =
1923 capture_active_bo(error->active_bo,
1924 error->active_bo_count,
1925 &dev_priv->mm.active_list);
1926
1927 if (error->pinned_bo)
1928 error->pinned_bo_count =
1929 capture_pinned_bo(error->pinned_bo,
1930 error->pinned_bo_count,
1931 &dev_priv->mm.bound_list);
1932 }
1933
1934 /**
1935 * i915_capture_error_state - capture an error record for later analysis
1936 * @dev: drm device
1937 *
1938 * Should be called when an error is detected (either a hang or an error
1939 * interrupt) to capture error state from the time of the error. Fills
1940 * out a structure which becomes available in debugfs for user level tools
1941 * to pick up.
1942 */
1943 static void i915_capture_error_state(struct drm_device *dev)
1944 {
1945 struct drm_i915_private *dev_priv = dev->dev_private;
1946 struct drm_i915_error_state *error;
1947 unsigned long flags;
1948 int pipe;
1949
1950 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1951 error = dev_priv->gpu_error.first_error;
1952 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1953 if (error)
1954 return;
1955
1956 /* Account for pipe specific data like PIPE*STAT */
1957 error = kzalloc(sizeof(*error), GFP_ATOMIC);
1958 if (!error) {
1959 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1960 return;
1961 }
1962
1963 DRM_INFO("capturing error event; look for more information in "
1964 "/sys/class/drm/card%d/error\n", dev->primary->index);
1965
1966 kref_init(&error->ref);
1967 error->eir = I915_READ(EIR);
1968 error->pgtbl_er = I915_READ(PGTBL_ER);
1969 if (HAS_HW_CONTEXTS(dev))
1970 error->ccid = I915_READ(CCID);
1971
1972 if (HAS_PCH_SPLIT(dev))
1973 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1974 else if (IS_VALLEYVIEW(dev))
1975 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1976 else if (IS_GEN2(dev))
1977 error->ier = I915_READ16(IER);
1978 else
1979 error->ier = I915_READ(IER);
1980
1981 if (INTEL_INFO(dev)->gen >= 6)
1982 error->derrmr = I915_READ(DERRMR);
1983
1984 if (IS_VALLEYVIEW(dev))
1985 error->forcewake = I915_READ(FORCEWAKE_VLV);
1986 else if (INTEL_INFO(dev)->gen >= 7)
1987 error->forcewake = I915_READ(FORCEWAKE_MT);
1988 else if (INTEL_INFO(dev)->gen == 6)
1989 error->forcewake = I915_READ(FORCEWAKE);
1990
1991 if (!HAS_PCH_SPLIT(dev))
1992 for_each_pipe(pipe)
1993 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1994
1995 if (INTEL_INFO(dev)->gen >= 6) {
1996 error->error = I915_READ(ERROR_GEN6);
1997 error->done_reg = I915_READ(DONE_REG);
1998 }
1999
2000 if (INTEL_INFO(dev)->gen == 7)
2001 error->err_int = I915_READ(GEN7_ERR_INT);
2002
2003 i915_get_extra_instdone(dev, error->extra_instdone);
2004
2005 i915_gem_capture_buffers(dev_priv, error);
2006 i915_gem_record_fences(dev, error);
2007 i915_gem_record_rings(dev, error);
2008
2009 do_gettimeofday(&error->time);
2010
2011 error->overlay = intel_overlay_capture_error_state(dev);
2012 error->display = intel_display_capture_error_state(dev);
2013
2014 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
2015 if (dev_priv->gpu_error.first_error == NULL) {
2016 dev_priv->gpu_error.first_error = error;
2017 error = NULL;
2018 }
2019 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
2020
2021 if (error)
2022 i915_error_state_free(&error->ref);
2023 }
2024
2025 void i915_destroy_error_state(struct drm_device *dev)
2026 {
2027 struct drm_i915_private *dev_priv = dev->dev_private;
2028 struct drm_i915_error_state *error;
2029 unsigned long flags;
2030
2031 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
2032 error = dev_priv->gpu_error.first_error;
2033 dev_priv->gpu_error.first_error = NULL;
2034 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
2035
2036 if (error)
2037 kref_put(&error->ref, i915_error_state_free);
2038 }
2039 #else
2040 #define i915_capture_error_state(x)
2041 #endif
2042
2043 static void i915_report_and_clear_eir(struct drm_device *dev)
2044 {
2045 struct drm_i915_private *dev_priv = dev->dev_private;
2046 uint32_t instdone[I915_NUM_INSTDONE_REG];
2047 u32 eir = I915_READ(EIR);
2048 int pipe, i;
2049
2050 if (!eir)
2051 return;
2052
2053 pr_err("render error detected, EIR: 0x%08x\n", eir);
2054
2055 i915_get_extra_instdone(dev, instdone);
2056
2057 if (IS_G4X(dev)) {
2058 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2059 u32 ipeir = I915_READ(IPEIR_I965);
2060
2061 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2062 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2063 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2064 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2065 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2066 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2067 I915_WRITE(IPEIR_I965, ipeir);
2068 POSTING_READ(IPEIR_I965);
2069 }
2070 if (eir & GM45_ERROR_PAGE_TABLE) {
2071 u32 pgtbl_err = I915_READ(PGTBL_ER);
2072 pr_err("page table error\n");
2073 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2074 I915_WRITE(PGTBL_ER, pgtbl_err);
2075 POSTING_READ(PGTBL_ER);
2076 }
2077 }
2078
2079 if (!IS_GEN2(dev)) {
2080 if (eir & I915_ERROR_PAGE_TABLE) {
2081 u32 pgtbl_err = I915_READ(PGTBL_ER);
2082 pr_err("page table error\n");
2083 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2084 I915_WRITE(PGTBL_ER, pgtbl_err);
2085 POSTING_READ(PGTBL_ER);
2086 }
2087 }
2088
2089 if (eir & I915_ERROR_MEMORY_REFRESH) {
2090 pr_err("memory refresh error:\n");
2091 for_each_pipe(pipe)
2092 pr_err("pipe %c stat: 0x%08x\n",
2093 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2094 /* pipestat has already been acked */
2095 }
2096 if (eir & I915_ERROR_INSTRUCTION) {
2097 pr_err("instruction error\n");
2098 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
2099 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2100 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2101 if (INTEL_INFO(dev)->gen < 4) {
2102 u32 ipeir = I915_READ(IPEIR);
2103
2104 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2105 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
2106 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
2107 I915_WRITE(IPEIR, ipeir);
2108 POSTING_READ(IPEIR);
2109 } else {
2110 u32 ipeir = I915_READ(IPEIR_I965);
2111
2112 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2113 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2114 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2115 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2116 I915_WRITE(IPEIR_I965, ipeir);
2117 POSTING_READ(IPEIR_I965);
2118 }
2119 }
2120
2121 I915_WRITE(EIR, eir);
2122 POSTING_READ(EIR);
2123 eir = I915_READ(EIR);
2124 if (eir) {
2125 /*
2126 * some errors might have become stuck,
2127 * mask them.
2128 */
2129 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2130 I915_WRITE(EMR, I915_READ(EMR) | eir);
2131 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2132 }
2133 }
2134
2135 /**
2136 * i915_handle_error - handle an error interrupt
2137 * @dev: drm device
2138 *
2139 * Do some basic checking of regsiter state at error interrupt time and
2140 * dump it to the syslog. Also call i915_capture_error_state() to make
2141 * sure we get a record and make it available in debugfs. Fire a uevent
2142 * so userspace knows something bad happened (should trigger collection
2143 * of a ring dump etc.).
2144 */
2145 void i915_handle_error(struct drm_device *dev, bool wedged)
2146 {
2147 struct drm_i915_private *dev_priv = dev->dev_private;
2148 struct intel_ring_buffer *ring;
2149 int i;
2150
2151 i915_capture_error_state(dev);
2152 i915_report_and_clear_eir(dev);
2153
2154 if (wedged) {
2155 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2156 &dev_priv->gpu_error.reset_counter);
2157
2158 /*
2159 * Wakeup waiting processes so that the reset work item
2160 * doesn't deadlock trying to grab various locks.
2161 */
2162 for_each_ring(ring, dev_priv, i)
2163 wake_up_all(&ring->irq_queue);
2164 }
2165
2166 queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
2167 }
2168
2169 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
2170 {
2171 drm_i915_private_t *dev_priv = dev->dev_private;
2172 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2173 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2174 struct drm_i915_gem_object *obj;
2175 struct intel_unpin_work *work;
2176 unsigned long flags;
2177 bool stall_detected;
2178
2179 /* Ignore early vblank irqs */
2180 if (intel_crtc == NULL)
2181 return;
2182
2183 spin_lock_irqsave(&dev->event_lock, flags);
2184 work = intel_crtc->unpin_work;
2185
2186 if (work == NULL ||
2187 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2188 !work->enable_stall_check) {
2189 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2190 spin_unlock_irqrestore(&dev->event_lock, flags);
2191 return;
2192 }
2193
2194 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2195 obj = work->pending_flip_obj;
2196 if (INTEL_INFO(dev)->gen >= 4) {
2197 int dspsurf = DSPSURF(intel_crtc->plane);
2198 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
2199 i915_gem_obj_ggtt_offset(obj);
2200 } else {
2201 int dspaddr = DSPADDR(intel_crtc->plane);
2202 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
2203 crtc->y * crtc->fb->pitches[0] +
2204 crtc->x * crtc->fb->bits_per_pixel/8);
2205 }
2206
2207 spin_unlock_irqrestore(&dev->event_lock, flags);
2208
2209 if (stall_detected) {
2210 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2211 intel_prepare_page_flip(dev, intel_crtc->plane);
2212 }
2213 }
2214
2215 /* Called from drm generic code, passed 'crtc' which
2216 * we use as a pipe index
2217 */
2218 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2219 {
2220 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2221 unsigned long irqflags;
2222
2223 if (!i915_pipe_enabled(dev, pipe))
2224 return -EINVAL;
2225
2226 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2227 if (INTEL_INFO(dev)->gen >= 4)
2228 i915_enable_pipestat(dev_priv, pipe,
2229 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2230 else
2231 i915_enable_pipestat(dev_priv, pipe,
2232 PIPE_VBLANK_INTERRUPT_ENABLE);
2233
2234 /* maintain vblank delivery even in deep C-states */
2235 if (dev_priv->info->gen == 3)
2236 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
2237 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2238
2239 return 0;
2240 }
2241
2242 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2243 {
2244 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2245 unsigned long irqflags;
2246
2247 if (!i915_pipe_enabled(dev, pipe))
2248 return -EINVAL;
2249
2250 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2251 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
2252 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
2253 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2254
2255 return 0;
2256 }
2257
2258 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
2259 {
2260 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2261 unsigned long irqflags;
2262
2263 if (!i915_pipe_enabled(dev, pipe))
2264 return -EINVAL;
2265
2266 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2267 ironlake_enable_display_irq(dev_priv,
2268 DE_PIPEA_VBLANK_IVB << (5 * pipe));
2269 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2270
2271 return 0;
2272 }
2273
2274 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2275 {
2276 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2277 unsigned long irqflags;
2278 u32 imr;
2279
2280 if (!i915_pipe_enabled(dev, pipe))
2281 return -EINVAL;
2282
2283 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2284 imr = I915_READ(VLV_IMR);
2285 if (pipe == 0)
2286 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
2287 else
2288 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2289 I915_WRITE(VLV_IMR, imr);
2290 i915_enable_pipestat(dev_priv, pipe,
2291 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2292 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2293
2294 return 0;
2295 }
2296
2297 /* Called from drm generic code, passed 'crtc' which
2298 * we use as a pipe index
2299 */
2300 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2301 {
2302 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2303 unsigned long irqflags;
2304
2305 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2306 if (dev_priv->info->gen == 3)
2307 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
2308
2309 i915_disable_pipestat(dev_priv, pipe,
2310 PIPE_VBLANK_INTERRUPT_ENABLE |
2311 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2312 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2313 }
2314
2315 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2316 {
2317 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2318 unsigned long irqflags;
2319
2320 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2321 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
2322 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
2323 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2324 }
2325
2326 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
2327 {
2328 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2329 unsigned long irqflags;
2330
2331 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2332 ironlake_disable_display_irq(dev_priv,
2333 DE_PIPEA_VBLANK_IVB << (pipe * 5));
2334 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2335 }
2336
2337 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2338 {
2339 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2340 unsigned long irqflags;
2341 u32 imr;
2342
2343 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2344 i915_disable_pipestat(dev_priv, pipe,
2345 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2346 imr = I915_READ(VLV_IMR);
2347 if (pipe == 0)
2348 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
2349 else
2350 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2351 I915_WRITE(VLV_IMR, imr);
2352 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2353 }
2354
2355 static u32
2356 ring_last_seqno(struct intel_ring_buffer *ring)
2357 {
2358 return list_entry(ring->request_list.prev,
2359 struct drm_i915_gem_request, list)->seqno;
2360 }
2361
2362 static bool
2363 ring_idle(struct intel_ring_buffer *ring, u32 seqno)
2364 {
2365 return (list_empty(&ring->request_list) ||
2366 i915_seqno_passed(seqno, ring_last_seqno(ring)));
2367 }
2368
2369 static struct intel_ring_buffer *
2370 semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
2371 {
2372 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2373 u32 cmd, ipehr, acthd, acthd_min;
2374
2375 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2376 if ((ipehr & ~(0x3 << 16)) !=
2377 (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
2378 return NULL;
2379
2380 /* ACTHD is likely pointing to the dword after the actual command,
2381 * so scan backwards until we find the MBOX.
2382 */
2383 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
2384 acthd_min = max((int)acthd - 3 * 4, 0);
2385 do {
2386 cmd = ioread32(ring->virtual_start + acthd);
2387 if (cmd == ipehr)
2388 break;
2389
2390 acthd -= 4;
2391 if (acthd < acthd_min)
2392 return NULL;
2393 } while (1);
2394
2395 *seqno = ioread32(ring->virtual_start+acthd+4)+1;
2396 return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
2397 }
2398
2399 static int semaphore_passed(struct intel_ring_buffer *ring)
2400 {
2401 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2402 struct intel_ring_buffer *signaller;
2403 u32 seqno, ctl;
2404
2405 ring->hangcheck.deadlock = true;
2406
2407 signaller = semaphore_waits_for(ring, &seqno);
2408 if (signaller == NULL || signaller->hangcheck.deadlock)
2409 return -1;
2410
2411 /* cursory check for an unkickable deadlock */
2412 ctl = I915_READ_CTL(signaller);
2413 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2414 return -1;
2415
2416 return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
2417 }
2418
2419 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2420 {
2421 struct intel_ring_buffer *ring;
2422 int i;
2423
2424 for_each_ring(ring, dev_priv, i)
2425 ring->hangcheck.deadlock = false;
2426 }
2427
2428 static enum intel_ring_hangcheck_action
2429 ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
2430 {
2431 struct drm_device *dev = ring->dev;
2432 struct drm_i915_private *dev_priv = dev->dev_private;
2433 u32 tmp;
2434
2435 if (ring->hangcheck.acthd != acthd)
2436 return active;
2437
2438 if (IS_GEN2(dev))
2439 return hung;
2440
2441 /* Is the chip hanging on a WAIT_FOR_EVENT?
2442 * If so we can simply poke the RB_WAIT bit
2443 * and break the hang. This should work on
2444 * all but the second generation chipsets.
2445 */
2446 tmp = I915_READ_CTL(ring);
2447 if (tmp & RING_WAIT) {
2448 DRM_ERROR("Kicking stuck wait on %s\n",
2449 ring->name);
2450 I915_WRITE_CTL(ring, tmp);
2451 return kick;
2452 }
2453
2454 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2455 switch (semaphore_passed(ring)) {
2456 default:
2457 return hung;
2458 case 1:
2459 DRM_ERROR("Kicking stuck semaphore on %s\n",
2460 ring->name);
2461 I915_WRITE_CTL(ring, tmp);
2462 return kick;
2463 case 0:
2464 return wait;
2465 }
2466 }
2467
2468 return hung;
2469 }
2470
2471 /**
2472 * This is called when the chip hasn't reported back with completed
2473 * batchbuffers in a long time. We keep track per ring seqno progress and
2474 * if there are no progress, hangcheck score for that ring is increased.
2475 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2476 * we kick the ring. If we see no progress on three subsequent calls
2477 * we assume chip is wedged and try to fix it by resetting the chip.
2478 */
2479 void i915_hangcheck_elapsed(unsigned long data)
2480 {
2481 struct drm_device *dev = (struct drm_device *)data;
2482 drm_i915_private_t *dev_priv = dev->dev_private;
2483 struct intel_ring_buffer *ring;
2484 int i;
2485 int busy_count = 0, rings_hung = 0;
2486 bool stuck[I915_NUM_RINGS] = { 0 };
2487 #define BUSY 1
2488 #define KICK 5
2489 #define HUNG 20
2490 #define FIRE 30
2491
2492 if (!i915_enable_hangcheck)
2493 return;
2494
2495 for_each_ring(ring, dev_priv, i) {
2496 u32 seqno, acthd;
2497 bool busy = true;
2498
2499 semaphore_clear_deadlocks(dev_priv);
2500
2501 seqno = ring->get_seqno(ring, false);
2502 acthd = intel_ring_get_active_head(ring);
2503
2504 if (ring->hangcheck.seqno == seqno) {
2505 if (ring_idle(ring, seqno)) {
2506 if (waitqueue_active(&ring->irq_queue)) {
2507 /* Issue a wake-up to catch stuck h/w. */
2508 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2509 ring->name);
2510 wake_up_all(&ring->irq_queue);
2511 ring->hangcheck.score += HUNG;
2512 } else
2513 busy = false;
2514 } else {
2515 int score;
2516
2517 /* We always increment the hangcheck score
2518 * if the ring is busy and still processing
2519 * the same request, so that no single request
2520 * can run indefinitely (such as a chain of
2521 * batches). The only time we do not increment
2522 * the hangcheck score on this ring, if this
2523 * ring is in a legitimate wait for another
2524 * ring. In that case the waiting ring is a
2525 * victim and we want to be sure we catch the
2526 * right culprit. Then every time we do kick
2527 * the ring, add a small increment to the
2528 * score so that we can catch a batch that is
2529 * being repeatedly kicked and so responsible
2530 * for stalling the machine.
2531 */
2532 ring->hangcheck.action = ring_stuck(ring,
2533 acthd);
2534
2535 switch (ring->hangcheck.action) {
2536 case wait:
2537 score = 0;
2538 break;
2539 case active:
2540 score = BUSY;
2541 break;
2542 case kick:
2543 score = KICK;
2544 break;
2545 case hung:
2546 score = HUNG;
2547 stuck[i] = true;
2548 break;
2549 }
2550 ring->hangcheck.score += score;
2551 }
2552 } else {
2553 /* Gradually reduce the count so that we catch DoS
2554 * attempts across multiple batches.
2555 */
2556 if (ring->hangcheck.score > 0)
2557 ring->hangcheck.score--;
2558 }
2559
2560 ring->hangcheck.seqno = seqno;
2561 ring->hangcheck.acthd = acthd;
2562 busy_count += busy;
2563 }
2564
2565 for_each_ring(ring, dev_priv, i) {
2566 if (ring->hangcheck.score > FIRE) {
2567 DRM_ERROR("%s on %s\n",
2568 stuck[i] ? "stuck" : "no progress",
2569 ring->name);
2570 rings_hung++;
2571 }
2572 }
2573
2574 if (rings_hung)
2575 return i915_handle_error(dev, true);
2576
2577 if (busy_count)
2578 /* Reset timer case chip hangs without another request
2579 * being added */
2580 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2581 round_jiffies_up(jiffies +
2582 DRM_I915_HANGCHECK_JIFFIES));
2583 }
2584
2585 static void ibx_irq_preinstall(struct drm_device *dev)
2586 {
2587 struct drm_i915_private *dev_priv = dev->dev_private;
2588
2589 if (HAS_PCH_NOP(dev))
2590 return;
2591
2592 /* south display irq */
2593 I915_WRITE(SDEIMR, 0xffffffff);
2594 /*
2595 * SDEIER is also touched by the interrupt handler to work around missed
2596 * PCH interrupts. Hence we can't update it after the interrupt handler
2597 * is enabled - instead we unconditionally enable all PCH interrupt
2598 * sources here, but then only unmask them as needed with SDEIMR.
2599 */
2600 I915_WRITE(SDEIER, 0xffffffff);
2601 POSTING_READ(SDEIER);
2602 }
2603
2604 /* drm_dma.h hooks
2605 */
2606 static void ironlake_irq_preinstall(struct drm_device *dev)
2607 {
2608 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2609
2610 atomic_set(&dev_priv->irq_received, 0);
2611
2612 I915_WRITE(HWSTAM, 0xeffe);
2613
2614 /* XXX hotplug from PCH */
2615
2616 I915_WRITE(DEIMR, 0xffffffff);
2617 I915_WRITE(DEIER, 0x0);
2618 POSTING_READ(DEIER);
2619
2620 /* and GT */
2621 I915_WRITE(GTIMR, 0xffffffff);
2622 I915_WRITE(GTIER, 0x0);
2623 POSTING_READ(GTIER);
2624
2625 ibx_irq_preinstall(dev);
2626 }
2627
2628 static void ivybridge_irq_preinstall(struct drm_device *dev)
2629 {
2630 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2631
2632 atomic_set(&dev_priv->irq_received, 0);
2633
2634 I915_WRITE(HWSTAM, 0xeffe);
2635
2636 /* XXX hotplug from PCH */
2637
2638 I915_WRITE(DEIMR, 0xffffffff);
2639 I915_WRITE(DEIER, 0x0);
2640 POSTING_READ(DEIER);
2641
2642 /* and GT */
2643 I915_WRITE(GTIMR, 0xffffffff);
2644 I915_WRITE(GTIER, 0x0);
2645 POSTING_READ(GTIER);
2646
2647 /* Power management */
2648 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2649 I915_WRITE(GEN6_PMIER, 0x0);
2650 POSTING_READ(GEN6_PMIER);
2651
2652 ibx_irq_preinstall(dev);
2653 }
2654
2655 static void valleyview_irq_preinstall(struct drm_device *dev)
2656 {
2657 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2658 int pipe;
2659
2660 atomic_set(&dev_priv->irq_received, 0);
2661
2662 /* VLV magic */
2663 I915_WRITE(VLV_IMR, 0);
2664 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2665 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2666 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2667
2668 /* and GT */
2669 I915_WRITE(GTIIR, I915_READ(GTIIR));
2670 I915_WRITE(GTIIR, I915_READ(GTIIR));
2671 I915_WRITE(GTIMR, 0xffffffff);
2672 I915_WRITE(GTIER, 0x0);
2673 POSTING_READ(GTIER);
2674
2675 I915_WRITE(DPINVGTT, 0xff);
2676
2677 I915_WRITE(PORT_HOTPLUG_EN, 0);
2678 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2679 for_each_pipe(pipe)
2680 I915_WRITE(PIPESTAT(pipe), 0xffff);
2681 I915_WRITE(VLV_IIR, 0xffffffff);
2682 I915_WRITE(VLV_IMR, 0xffffffff);
2683 I915_WRITE(VLV_IER, 0x0);
2684 POSTING_READ(VLV_IER);
2685 }
2686
2687 static void ibx_hpd_irq_setup(struct drm_device *dev)
2688 {
2689 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2690 struct drm_mode_config *mode_config = &dev->mode_config;
2691 struct intel_encoder *intel_encoder;
2692 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
2693
2694 if (HAS_PCH_IBX(dev)) {
2695 hotplug_irqs = SDE_HOTPLUG_MASK;
2696 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2697 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2698 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
2699 } else {
2700 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
2701 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2702 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2703 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
2704 }
2705
2706 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
2707
2708 /*
2709 * Enable digital hotplug on the PCH, and configure the DP short pulse
2710 * duration to 2ms (which is the minimum in the Display Port spec)
2711 *
2712 * This register is the same on all known PCH chips.
2713 */
2714 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2715 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2716 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2717 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2718 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2719 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2720 }
2721
2722 static void ibx_irq_postinstall(struct drm_device *dev)
2723 {
2724 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2725 u32 mask;
2726
2727 if (HAS_PCH_NOP(dev))
2728 return;
2729
2730 if (HAS_PCH_IBX(dev)) {
2731 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
2732 SDE_TRANSA_FIFO_UNDER | SDE_POISON;
2733 } else {
2734 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2735
2736 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2737 }
2738
2739 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2740 I915_WRITE(SDEIMR, ~mask);
2741 }
2742
2743 static int ironlake_irq_postinstall(struct drm_device *dev)
2744 {
2745 unsigned long irqflags;
2746
2747 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2748 /* enable kind of interrupts always enabled */
2749 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2750 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
2751 DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
2752 DE_PIPEA_FIFO_UNDERRUN | DE_POISON;
2753 u32 gt_irqs;
2754
2755 dev_priv->irq_mask = ~display_mask;
2756
2757 /* should always can generate irq */
2758 I915_WRITE(DEIIR, I915_READ(DEIIR));
2759 I915_WRITE(DEIMR, dev_priv->irq_mask);
2760 I915_WRITE(DEIER, display_mask |
2761 DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT);
2762 POSTING_READ(DEIER);
2763
2764 dev_priv->gt_irq_mask = ~0;
2765
2766 I915_WRITE(GTIIR, I915_READ(GTIIR));
2767 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2768
2769 gt_irqs = GT_RENDER_USER_INTERRUPT;
2770
2771 if (IS_GEN6(dev))
2772 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
2773 else
2774 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
2775 ILK_BSD_USER_INTERRUPT;
2776
2777 I915_WRITE(GTIER, gt_irqs);
2778 POSTING_READ(GTIER);
2779
2780 ibx_irq_postinstall(dev);
2781
2782 if (IS_IRONLAKE_M(dev)) {
2783 /* Enable PCU event interrupts
2784 *
2785 * spinlocking not required here for correctness since interrupt
2786 * setup is guaranteed to run in single-threaded context. But we
2787 * need it to make the assert_spin_locked happy. */
2788 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2789 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2790 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2791 }
2792
2793 return 0;
2794 }
2795
2796 static int ivybridge_irq_postinstall(struct drm_device *dev)
2797 {
2798 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2799 /* enable kind of interrupts always enabled */
2800 u32 display_mask =
2801 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
2802 DE_PLANEC_FLIP_DONE_IVB |
2803 DE_PLANEB_FLIP_DONE_IVB |
2804 DE_PLANEA_FLIP_DONE_IVB |
2805 DE_AUX_CHANNEL_A_IVB |
2806 DE_ERR_INT_IVB;
2807 u32 pm_irqs = GEN6_PM_RPS_EVENTS;
2808 u32 gt_irqs;
2809
2810 dev_priv->irq_mask = ~display_mask;
2811
2812 /* should always can generate irq */
2813 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2814 I915_WRITE(DEIIR, I915_READ(DEIIR));
2815 I915_WRITE(DEIMR, dev_priv->irq_mask);
2816 I915_WRITE(DEIER,
2817 display_mask |
2818 DE_PIPEC_VBLANK_IVB |
2819 DE_PIPEB_VBLANK_IVB |
2820 DE_PIPEA_VBLANK_IVB);
2821 POSTING_READ(DEIER);
2822
2823 dev_priv->gt_irq_mask = ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2824
2825 I915_WRITE(GTIIR, I915_READ(GTIIR));
2826 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2827
2828 gt_irqs = GT_RENDER_USER_INTERRUPT | GT_BSD_USER_INTERRUPT |
2829 GT_BLT_USER_INTERRUPT | GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2830 I915_WRITE(GTIER, gt_irqs);
2831 POSTING_READ(GTIER);
2832
2833 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2834 if (HAS_VEBOX(dev))
2835 pm_irqs |= PM_VEBOX_USER_INTERRUPT |
2836 PM_VEBOX_CS_ERROR_INTERRUPT;
2837
2838 /* Our enable/disable rps functions may touch these registers so
2839 * make sure to set a known state for only the non-RPS bits.
2840 * The RMW is extra paranoia since this should be called after being set
2841 * to a known state in preinstall.
2842 * */
2843 I915_WRITE(GEN6_PMIMR,
2844 (I915_READ(GEN6_PMIMR) | ~GEN6_PM_RPS_EVENTS) & ~pm_irqs);
2845 I915_WRITE(GEN6_PMIER,
2846 (I915_READ(GEN6_PMIER) & GEN6_PM_RPS_EVENTS) | pm_irqs);
2847 POSTING_READ(GEN6_PMIER);
2848
2849 ibx_irq_postinstall(dev);
2850
2851 return 0;
2852 }
2853
2854 static int valleyview_irq_postinstall(struct drm_device *dev)
2855 {
2856 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2857 u32 gt_irqs;
2858 u32 enable_mask;
2859 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
2860 unsigned long irqflags;
2861
2862 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
2863 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2864 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2865 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2866 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2867
2868 /*
2869 *Leave vblank interrupts masked initially. enable/disable will
2870 * toggle them based on usage.
2871 */
2872 dev_priv->irq_mask = (~enable_mask) |
2873 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2874 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2875
2876 I915_WRITE(PORT_HOTPLUG_EN, 0);
2877 POSTING_READ(PORT_HOTPLUG_EN);
2878
2879 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2880 I915_WRITE(VLV_IER, enable_mask);
2881 I915_WRITE(VLV_IIR, 0xffffffff);
2882 I915_WRITE(PIPESTAT(0), 0xffff);
2883 I915_WRITE(PIPESTAT(1), 0xffff);
2884 POSTING_READ(VLV_IER);
2885
2886 /* Interrupt setup is already guaranteed to be single-threaded, this is
2887 * just to make the assert_spin_locked check happy. */
2888 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2889 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
2890 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
2891 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
2892 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2893
2894 I915_WRITE(VLV_IIR, 0xffffffff);
2895 I915_WRITE(VLV_IIR, 0xffffffff);
2896
2897 I915_WRITE(GTIIR, I915_READ(GTIIR));
2898 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2899
2900 gt_irqs = GT_RENDER_USER_INTERRUPT | GT_BSD_USER_INTERRUPT |
2901 GT_BLT_USER_INTERRUPT;
2902 I915_WRITE(GTIER, gt_irqs);
2903 POSTING_READ(GTIER);
2904
2905 /* ack & enable invalid PTE error interrupts */
2906 #if 0 /* FIXME: add support to irq handler for checking these bits */
2907 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2908 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2909 #endif
2910
2911 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2912
2913 return 0;
2914 }
2915
2916 static void valleyview_irq_uninstall(struct drm_device *dev)
2917 {
2918 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2919 int pipe;
2920
2921 if (!dev_priv)
2922 return;
2923
2924 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2925
2926 for_each_pipe(pipe)
2927 I915_WRITE(PIPESTAT(pipe), 0xffff);
2928
2929 I915_WRITE(HWSTAM, 0xffffffff);
2930 I915_WRITE(PORT_HOTPLUG_EN, 0);
2931 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2932 for_each_pipe(pipe)
2933 I915_WRITE(PIPESTAT(pipe), 0xffff);
2934 I915_WRITE(VLV_IIR, 0xffffffff);
2935 I915_WRITE(VLV_IMR, 0xffffffff);
2936 I915_WRITE(VLV_IER, 0x0);
2937 POSTING_READ(VLV_IER);
2938 }
2939
2940 static void ironlake_irq_uninstall(struct drm_device *dev)
2941 {
2942 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2943
2944 if (!dev_priv)
2945 return;
2946
2947 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2948
2949 I915_WRITE(HWSTAM, 0xffffffff);
2950
2951 I915_WRITE(DEIMR, 0xffffffff);
2952 I915_WRITE(DEIER, 0x0);
2953 I915_WRITE(DEIIR, I915_READ(DEIIR));
2954 if (IS_GEN7(dev))
2955 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2956
2957 I915_WRITE(GTIMR, 0xffffffff);
2958 I915_WRITE(GTIER, 0x0);
2959 I915_WRITE(GTIIR, I915_READ(GTIIR));
2960
2961 if (HAS_PCH_NOP(dev))
2962 return;
2963
2964 I915_WRITE(SDEIMR, 0xffffffff);
2965 I915_WRITE(SDEIER, 0x0);
2966 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2967 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
2968 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2969 }
2970
2971 static void i8xx_irq_preinstall(struct drm_device * dev)
2972 {
2973 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2974 int pipe;
2975
2976 atomic_set(&dev_priv->irq_received, 0);
2977
2978 for_each_pipe(pipe)
2979 I915_WRITE(PIPESTAT(pipe), 0);
2980 I915_WRITE16(IMR, 0xffff);
2981 I915_WRITE16(IER, 0x0);
2982 POSTING_READ16(IER);
2983 }
2984
2985 static int i8xx_irq_postinstall(struct drm_device *dev)
2986 {
2987 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2988
2989 I915_WRITE16(EMR,
2990 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2991
2992 /* Unmask the interrupts that we always want on. */
2993 dev_priv->irq_mask =
2994 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2995 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2996 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2997 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2998 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2999 I915_WRITE16(IMR, dev_priv->irq_mask);
3000
3001 I915_WRITE16(IER,
3002 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3003 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3004 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3005 I915_USER_INTERRUPT);
3006 POSTING_READ16(IER);
3007
3008 return 0;
3009 }
3010
3011 /*
3012 * Returns true when a page flip has completed.
3013 */
3014 static bool i8xx_handle_vblank(struct drm_device *dev,
3015 int pipe, u16 iir)
3016 {
3017 drm_i915_private_t *dev_priv = dev->dev_private;
3018 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
3019
3020 if (!drm_handle_vblank(dev, pipe))
3021 return false;
3022
3023 if ((iir & flip_pending) == 0)
3024 return false;
3025
3026 intel_prepare_page_flip(dev, pipe);
3027
3028 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3029 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3030 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3031 * the flip is completed (no longer pending). Since this doesn't raise
3032 * an interrupt per se, we watch for the change at vblank.
3033 */
3034 if (I915_READ16(ISR) & flip_pending)
3035 return false;
3036
3037 intel_finish_page_flip(dev, pipe);
3038
3039 return true;
3040 }
3041
3042 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3043 {
3044 struct drm_device *dev = (struct drm_device *) arg;
3045 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3046 u16 iir, new_iir;
3047 u32 pipe_stats[2];
3048 unsigned long irqflags;
3049 int irq_received;
3050 int pipe;
3051 u16 flip_mask =
3052 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3053 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3054
3055 atomic_inc(&dev_priv->irq_received);
3056
3057 iir = I915_READ16(IIR);
3058 if (iir == 0)
3059 return IRQ_NONE;
3060
3061 while (iir & ~flip_mask) {
3062 /* Can't rely on pipestat interrupt bit in iir as it might
3063 * have been cleared after the pipestat interrupt was received.
3064 * It doesn't set the bit in iir again, but it still produces
3065 * interrupts (for non-MSI).
3066 */
3067 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3068 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3069 i915_handle_error(dev, false);
3070
3071 for_each_pipe(pipe) {
3072 int reg = PIPESTAT(pipe);
3073 pipe_stats[pipe] = I915_READ(reg);
3074
3075 /*
3076 * Clear the PIPE*STAT regs before the IIR
3077 */
3078 if (pipe_stats[pipe] & 0x8000ffff) {
3079 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3080 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3081 pipe_name(pipe));
3082 I915_WRITE(reg, pipe_stats[pipe]);
3083 irq_received = 1;
3084 }
3085 }
3086 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3087
3088 I915_WRITE16(IIR, iir & ~flip_mask);
3089 new_iir = I915_READ16(IIR); /* Flush posted writes */
3090
3091 i915_update_dri1_breadcrumb(dev);
3092
3093 if (iir & I915_USER_INTERRUPT)
3094 notify_ring(dev, &dev_priv->ring[RCS]);
3095
3096 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
3097 i8xx_handle_vblank(dev, 0, iir))
3098 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
3099
3100 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
3101 i8xx_handle_vblank(dev, 1, iir))
3102 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
3103
3104 iir = new_iir;
3105 }
3106
3107 return IRQ_HANDLED;
3108 }
3109
3110 static void i8xx_irq_uninstall(struct drm_device * dev)
3111 {
3112 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3113 int pipe;
3114
3115 for_each_pipe(pipe) {
3116 /* Clear enable bits; then clear status bits */
3117 I915_WRITE(PIPESTAT(pipe), 0);
3118 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3119 }
3120 I915_WRITE16(IMR, 0xffff);
3121 I915_WRITE16(IER, 0x0);
3122 I915_WRITE16(IIR, I915_READ16(IIR));
3123 }
3124
3125 static void i915_irq_preinstall(struct drm_device * dev)
3126 {
3127 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3128 int pipe;
3129
3130 atomic_set(&dev_priv->irq_received, 0);
3131
3132 if (I915_HAS_HOTPLUG(dev)) {
3133 I915_WRITE(PORT_HOTPLUG_EN, 0);
3134 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3135 }
3136
3137 I915_WRITE16(HWSTAM, 0xeffe);
3138 for_each_pipe(pipe)
3139 I915_WRITE(PIPESTAT(pipe), 0);
3140 I915_WRITE(IMR, 0xffffffff);
3141 I915_WRITE(IER, 0x0);
3142 POSTING_READ(IER);
3143 }
3144
3145 static int i915_irq_postinstall(struct drm_device *dev)
3146 {
3147 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3148 u32 enable_mask;
3149
3150 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3151
3152 /* Unmask the interrupts that we always want on. */
3153 dev_priv->irq_mask =
3154 ~(I915_ASLE_INTERRUPT |
3155 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3156 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3157 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3158 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3159 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3160
3161 enable_mask =
3162 I915_ASLE_INTERRUPT |
3163 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3164 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3165 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3166 I915_USER_INTERRUPT;
3167
3168 if (I915_HAS_HOTPLUG(dev)) {
3169 I915_WRITE(PORT_HOTPLUG_EN, 0);
3170 POSTING_READ(PORT_HOTPLUG_EN);
3171
3172 /* Enable in IER... */
3173 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3174 /* and unmask in IMR */
3175 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3176 }
3177
3178 I915_WRITE(IMR, dev_priv->irq_mask);
3179 I915_WRITE(IER, enable_mask);
3180 POSTING_READ(IER);
3181
3182 i915_enable_asle_pipestat(dev);
3183
3184 return 0;
3185 }
3186
3187 /*
3188 * Returns true when a page flip has completed.
3189 */
3190 static bool i915_handle_vblank(struct drm_device *dev,
3191 int plane, int pipe, u32 iir)
3192 {
3193 drm_i915_private_t *dev_priv = dev->dev_private;
3194 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3195
3196 if (!drm_handle_vblank(dev, pipe))
3197 return false;
3198
3199 if ((iir & flip_pending) == 0)
3200 return false;
3201
3202 intel_prepare_page_flip(dev, plane);
3203
3204 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3205 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3206 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3207 * the flip is completed (no longer pending). Since this doesn't raise
3208 * an interrupt per se, we watch for the change at vblank.
3209 */
3210 if (I915_READ(ISR) & flip_pending)
3211 return false;
3212
3213 intel_finish_page_flip(dev, pipe);
3214
3215 return true;
3216 }
3217
3218 static irqreturn_t i915_irq_handler(int irq, void *arg)
3219 {
3220 struct drm_device *dev = (struct drm_device *) arg;
3221 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3222 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3223 unsigned long irqflags;
3224 u32 flip_mask =
3225 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3226 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3227 int pipe, ret = IRQ_NONE;
3228
3229 atomic_inc(&dev_priv->irq_received);
3230
3231 iir = I915_READ(IIR);
3232 do {
3233 bool irq_received = (iir & ~flip_mask) != 0;
3234 bool blc_event = false;
3235
3236 /* Can't rely on pipestat interrupt bit in iir as it might
3237 * have been cleared after the pipestat interrupt was received.
3238 * It doesn't set the bit in iir again, but it still produces
3239 * interrupts (for non-MSI).
3240 */
3241 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3242 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3243 i915_handle_error(dev, false);
3244
3245 for_each_pipe(pipe) {
3246 int reg = PIPESTAT(pipe);
3247 pipe_stats[pipe] = I915_READ(reg);
3248
3249 /* Clear the PIPE*STAT regs before the IIR */
3250 if (pipe_stats[pipe] & 0x8000ffff) {
3251 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3252 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3253 pipe_name(pipe));
3254 I915_WRITE(reg, pipe_stats[pipe]);
3255 irq_received = true;
3256 }
3257 }
3258 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3259
3260 if (!irq_received)
3261 break;
3262
3263 /* Consume port. Then clear IIR or we'll miss events */
3264 if ((I915_HAS_HOTPLUG(dev)) &&
3265 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
3266 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3267 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
3268
3269 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3270 hotplug_status);
3271
3272 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
3273
3274 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3275 POSTING_READ(PORT_HOTPLUG_STAT);
3276 }
3277
3278 I915_WRITE(IIR, iir & ~flip_mask);
3279 new_iir = I915_READ(IIR); /* Flush posted writes */
3280
3281 if (iir & I915_USER_INTERRUPT)
3282 notify_ring(dev, &dev_priv->ring[RCS]);
3283
3284 for_each_pipe(pipe) {
3285 int plane = pipe;
3286 if (IS_MOBILE(dev))
3287 plane = !plane;
3288
3289 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3290 i915_handle_vblank(dev, plane, pipe, iir))
3291 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3292
3293 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3294 blc_event = true;
3295 }
3296
3297 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3298 intel_opregion_asle_intr(dev);
3299
3300 /* With MSI, interrupts are only generated when iir
3301 * transitions from zero to nonzero. If another bit got
3302 * set while we were handling the existing iir bits, then
3303 * we would never get another interrupt.
3304 *
3305 * This is fine on non-MSI as well, as if we hit this path
3306 * we avoid exiting the interrupt handler only to generate
3307 * another one.
3308 *
3309 * Note that for MSI this could cause a stray interrupt report
3310 * if an interrupt landed in the time between writing IIR and
3311 * the posting read. This should be rare enough to never
3312 * trigger the 99% of 100,000 interrupts test for disabling
3313 * stray interrupts.
3314 */
3315 ret = IRQ_HANDLED;
3316 iir = new_iir;
3317 } while (iir & ~flip_mask);
3318
3319 i915_update_dri1_breadcrumb(dev);
3320
3321 return ret;
3322 }
3323
3324 static void i915_irq_uninstall(struct drm_device * dev)
3325 {
3326 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3327 int pipe;
3328
3329 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3330
3331 if (I915_HAS_HOTPLUG(dev)) {
3332 I915_WRITE(PORT_HOTPLUG_EN, 0);
3333 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3334 }
3335
3336 I915_WRITE16(HWSTAM, 0xffff);
3337 for_each_pipe(pipe) {
3338 /* Clear enable bits; then clear status bits */
3339 I915_WRITE(PIPESTAT(pipe), 0);
3340 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3341 }
3342 I915_WRITE(IMR, 0xffffffff);
3343 I915_WRITE(IER, 0x0);
3344
3345 I915_WRITE(IIR, I915_READ(IIR));
3346 }
3347
3348 static void i965_irq_preinstall(struct drm_device * dev)
3349 {
3350 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3351 int pipe;
3352
3353 atomic_set(&dev_priv->irq_received, 0);
3354
3355 I915_WRITE(PORT_HOTPLUG_EN, 0);
3356 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3357
3358 I915_WRITE(HWSTAM, 0xeffe);
3359 for_each_pipe(pipe)
3360 I915_WRITE(PIPESTAT(pipe), 0);
3361 I915_WRITE(IMR, 0xffffffff);
3362 I915_WRITE(IER, 0x0);
3363 POSTING_READ(IER);
3364 }
3365
3366 static int i965_irq_postinstall(struct drm_device *dev)
3367 {
3368 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3369 u32 enable_mask;
3370 u32 error_mask;
3371 unsigned long irqflags;
3372
3373 /* Unmask the interrupts that we always want on. */
3374 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
3375 I915_DISPLAY_PORT_INTERRUPT |
3376 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3377 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3378 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3379 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3380 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3381
3382 enable_mask = ~dev_priv->irq_mask;
3383 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3384 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3385 enable_mask |= I915_USER_INTERRUPT;
3386
3387 if (IS_G4X(dev))
3388 enable_mask |= I915_BSD_USER_INTERRUPT;
3389
3390 /* Interrupt setup is already guaranteed to be single-threaded, this is
3391 * just to make the assert_spin_locked check happy. */
3392 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3393 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
3394 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3395
3396 /*
3397 * Enable some error detection, note the instruction error mask
3398 * bit is reserved, so we leave it masked.
3399 */
3400 if (IS_G4X(dev)) {
3401 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3402 GM45_ERROR_MEM_PRIV |
3403 GM45_ERROR_CP_PRIV |
3404 I915_ERROR_MEMORY_REFRESH);
3405 } else {
3406 error_mask = ~(I915_ERROR_PAGE_TABLE |
3407 I915_ERROR_MEMORY_REFRESH);
3408 }
3409 I915_WRITE(EMR, error_mask);
3410
3411 I915_WRITE(IMR, dev_priv->irq_mask);
3412 I915_WRITE(IER, enable_mask);
3413 POSTING_READ(IER);
3414
3415 I915_WRITE(PORT_HOTPLUG_EN, 0);
3416 POSTING_READ(PORT_HOTPLUG_EN);
3417
3418 i915_enable_asle_pipestat(dev);
3419
3420 return 0;
3421 }
3422
3423 static void i915_hpd_irq_setup(struct drm_device *dev)
3424 {
3425 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3426 struct drm_mode_config *mode_config = &dev->mode_config;
3427 struct intel_encoder *intel_encoder;
3428 u32 hotplug_en;
3429
3430 assert_spin_locked(&dev_priv->irq_lock);
3431
3432 if (I915_HAS_HOTPLUG(dev)) {
3433 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3434 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3435 /* Note HDMI and DP share hotplug bits */
3436 /* enable bits are the same for all generations */
3437 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3438 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3439 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
3440 /* Programming the CRT detection parameters tends
3441 to generate a spurious hotplug event about three
3442 seconds later. So just do it once.
3443 */
3444 if (IS_G4X(dev))
3445 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
3446 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
3447 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
3448
3449 /* Ignore TV since it's buggy */
3450 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3451 }
3452 }
3453
3454 static irqreturn_t i965_irq_handler(int irq, void *arg)
3455 {
3456 struct drm_device *dev = (struct drm_device *) arg;
3457 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3458 u32 iir, new_iir;
3459 u32 pipe_stats[I915_MAX_PIPES];
3460 unsigned long irqflags;
3461 int irq_received;
3462 int ret = IRQ_NONE, pipe;
3463 u32 flip_mask =
3464 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3465 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3466
3467 atomic_inc(&dev_priv->irq_received);
3468
3469 iir = I915_READ(IIR);
3470
3471 for (;;) {
3472 bool blc_event = false;
3473
3474 irq_received = (iir & ~flip_mask) != 0;
3475
3476 /* Can't rely on pipestat interrupt bit in iir as it might
3477 * have been cleared after the pipestat interrupt was received.
3478 * It doesn't set the bit in iir again, but it still produces
3479 * interrupts (for non-MSI).
3480 */
3481 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3482 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3483 i915_handle_error(dev, false);
3484
3485 for_each_pipe(pipe) {
3486 int reg = PIPESTAT(pipe);
3487 pipe_stats[pipe] = I915_READ(reg);
3488
3489 /*
3490 * Clear the PIPE*STAT regs before the IIR
3491 */
3492 if (pipe_stats[pipe] & 0x8000ffff) {
3493 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3494 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3495 pipe_name(pipe));
3496 I915_WRITE(reg, pipe_stats[pipe]);
3497 irq_received = 1;
3498 }
3499 }
3500 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3501
3502 if (!irq_received)
3503 break;
3504
3505 ret = IRQ_HANDLED;
3506
3507 /* Consume port. Then clear IIR or we'll miss events */
3508 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
3509 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3510 u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
3511 HOTPLUG_INT_STATUS_G4X :
3512 HOTPLUG_INT_STATUS_I915);
3513
3514 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3515 hotplug_status);
3516
3517 intel_hpd_irq_handler(dev, hotplug_trigger,
3518 IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915);
3519
3520 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3521 I915_READ(PORT_HOTPLUG_STAT);
3522 }
3523
3524 I915_WRITE(IIR, iir & ~flip_mask);
3525 new_iir = I915_READ(IIR); /* Flush posted writes */
3526
3527 if (iir & I915_USER_INTERRUPT)
3528 notify_ring(dev, &dev_priv->ring[RCS]);
3529 if (iir & I915_BSD_USER_INTERRUPT)
3530 notify_ring(dev, &dev_priv->ring[VCS]);
3531
3532 for_each_pipe(pipe) {
3533 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
3534 i915_handle_vblank(dev, pipe, pipe, iir))
3535 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
3536
3537 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3538 blc_event = true;
3539 }
3540
3541
3542 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3543 intel_opregion_asle_intr(dev);
3544
3545 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3546 gmbus_irq_handler(dev);
3547
3548 /* With MSI, interrupts are only generated when iir
3549 * transitions from zero to nonzero. If another bit got
3550 * set while we were handling the existing iir bits, then
3551 * we would never get another interrupt.
3552 *
3553 * This is fine on non-MSI as well, as if we hit this path
3554 * we avoid exiting the interrupt handler only to generate
3555 * another one.
3556 *
3557 * Note that for MSI this could cause a stray interrupt report
3558 * if an interrupt landed in the time between writing IIR and
3559 * the posting read. This should be rare enough to never
3560 * trigger the 99% of 100,000 interrupts test for disabling
3561 * stray interrupts.
3562 */
3563 iir = new_iir;
3564 }
3565
3566 i915_update_dri1_breadcrumb(dev);
3567
3568 return ret;
3569 }
3570
3571 static void i965_irq_uninstall(struct drm_device * dev)
3572 {
3573 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3574 int pipe;
3575
3576 if (!dev_priv)
3577 return;
3578
3579 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3580
3581 I915_WRITE(PORT_HOTPLUG_EN, 0);
3582 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3583
3584 I915_WRITE(HWSTAM, 0xffffffff);
3585 for_each_pipe(pipe)
3586 I915_WRITE(PIPESTAT(pipe), 0);
3587 I915_WRITE(IMR, 0xffffffff);
3588 I915_WRITE(IER, 0x0);
3589
3590 for_each_pipe(pipe)
3591 I915_WRITE(PIPESTAT(pipe),
3592 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3593 I915_WRITE(IIR, I915_READ(IIR));
3594 }
3595
3596 static void i915_reenable_hotplug_timer_func(unsigned long data)
3597 {
3598 drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
3599 struct drm_device *dev = dev_priv->dev;
3600 struct drm_mode_config *mode_config = &dev->mode_config;
3601 unsigned long irqflags;
3602 int i;
3603
3604 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3605 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3606 struct drm_connector *connector;
3607
3608 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3609 continue;
3610
3611 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3612
3613 list_for_each_entry(connector, &mode_config->connector_list, head) {
3614 struct intel_connector *intel_connector = to_intel_connector(connector);
3615
3616 if (intel_connector->encoder->hpd_pin == i) {
3617 if (connector->polled != intel_connector->polled)
3618 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3619 drm_get_connector_name(connector));
3620 connector->polled = intel_connector->polled;
3621 if (!connector->polled)
3622 connector->polled = DRM_CONNECTOR_POLL_HPD;
3623 }
3624 }
3625 }
3626 if (dev_priv->display.hpd_irq_setup)
3627 dev_priv->display.hpd_irq_setup(dev);
3628 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3629 }
3630
3631 void intel_irq_init(struct drm_device *dev)
3632 {
3633 struct drm_i915_private *dev_priv = dev->dev_private;
3634
3635 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
3636 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
3637 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
3638 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
3639
3640 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3641 i915_hangcheck_elapsed,
3642 (unsigned long) dev);
3643 setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
3644 (unsigned long) dev_priv);
3645
3646 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
3647
3648 dev->driver->get_vblank_counter = i915_get_vblank_counter;
3649 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
3650 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
3651 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3652 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
3653 }
3654
3655 if (drm_core_check_feature(dev, DRIVER_MODESET))
3656 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
3657 else
3658 dev->driver->get_vblank_timestamp = NULL;
3659 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3660
3661 if (IS_VALLEYVIEW(dev)) {
3662 dev->driver->irq_handler = valleyview_irq_handler;
3663 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3664 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3665 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3666 dev->driver->enable_vblank = valleyview_enable_vblank;
3667 dev->driver->disable_vblank = valleyview_disable_vblank;
3668 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3669 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
3670 /* Share uninstall handlers with ILK/SNB */
3671 dev->driver->irq_handler = ivybridge_irq_handler;
3672 dev->driver->irq_preinstall = ivybridge_irq_preinstall;
3673 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
3674 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3675 dev->driver->enable_vblank = ivybridge_enable_vblank;
3676 dev->driver->disable_vblank = ivybridge_disable_vblank;
3677 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3678 } else if (HAS_PCH_SPLIT(dev)) {
3679 dev->driver->irq_handler = ironlake_irq_handler;
3680 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3681 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3682 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3683 dev->driver->enable_vblank = ironlake_enable_vblank;
3684 dev->driver->disable_vblank = ironlake_disable_vblank;
3685 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3686 } else {
3687 if (INTEL_INFO(dev)->gen == 2) {
3688 dev->driver->irq_preinstall = i8xx_irq_preinstall;
3689 dev->driver->irq_postinstall = i8xx_irq_postinstall;
3690 dev->driver->irq_handler = i8xx_irq_handler;
3691 dev->driver->irq_uninstall = i8xx_irq_uninstall;
3692 } else if (INTEL_INFO(dev)->gen == 3) {
3693 dev->driver->irq_preinstall = i915_irq_preinstall;
3694 dev->driver->irq_postinstall = i915_irq_postinstall;
3695 dev->driver->irq_uninstall = i915_irq_uninstall;
3696 dev->driver->irq_handler = i915_irq_handler;
3697 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3698 } else {
3699 dev->driver->irq_preinstall = i965_irq_preinstall;
3700 dev->driver->irq_postinstall = i965_irq_postinstall;
3701 dev->driver->irq_uninstall = i965_irq_uninstall;
3702 dev->driver->irq_handler = i965_irq_handler;
3703 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3704 }
3705 dev->driver->enable_vblank = i915_enable_vblank;
3706 dev->driver->disable_vblank = i915_disable_vblank;
3707 }
3708 }
3709
3710 void intel_hpd_init(struct drm_device *dev)
3711 {
3712 struct drm_i915_private *dev_priv = dev->dev_private;
3713 struct drm_mode_config *mode_config = &dev->mode_config;
3714 struct drm_connector *connector;
3715 unsigned long irqflags;
3716 int i;
3717
3718 for (i = 1; i < HPD_NUM_PINS; i++) {
3719 dev_priv->hpd_stats[i].hpd_cnt = 0;
3720 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3721 }
3722 list_for_each_entry(connector, &mode_config->connector_list, head) {
3723 struct intel_connector *intel_connector = to_intel_connector(connector);
3724 connector->polled = intel_connector->polled;
3725 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3726 connector->polled = DRM_CONNECTOR_POLL_HPD;
3727 }
3728
3729 /* Interrupt setup is already guaranteed to be single-threaded, this is
3730 * just to make the assert_spin_locked checks happy. */
3731 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3732 if (dev_priv->display.hpd_irq_setup)
3733 dev_priv->display.hpd_irq_setup(dev);
3734 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3735 }
Linux kernel - Deliverables
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