1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
34 #include <drm/i915_drm.h>
36 #include "i915_trace.h"
37 #include "intel_drv.h"
39 static const u32 hpd_ibx
[] = {
40 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
41 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
42 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
43 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
44 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
47 static const u32 hpd_cpt
[] = {
48 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
49 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG_CPT
,
50 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
51 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
52 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
55 static const u32 hpd_mask_i915
[] = {
56 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
57 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
58 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
59 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
60 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
61 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
64 static const u32 hpd_status_gen4
[] = {
65 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
66 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
67 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
68 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
69 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
70 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
73 static const u32 hpd_status_i915
[] = { /* i915 and valleyview are the same */
74 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
75 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
76 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
77 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
78 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
79 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
82 /* For display hotplug interrupt */
84 ironlake_enable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
86 assert_spin_locked(&dev_priv
->irq_lock
);
88 if ((dev_priv
->irq_mask
& mask
) != 0) {
89 dev_priv
->irq_mask
&= ~mask
;
90 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
96 ironlake_disable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
98 assert_spin_locked(&dev_priv
->irq_lock
);
100 if ((dev_priv
->irq_mask
& mask
) != mask
) {
101 dev_priv
->irq_mask
|= mask
;
102 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
107 static bool ivb_can_enable_err_int(struct drm_device
*dev
)
109 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
110 struct intel_crtc
*crtc
;
113 assert_spin_locked(&dev_priv
->irq_lock
);
115 for_each_pipe(pipe
) {
116 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
118 if (crtc
->cpu_fifo_underrun_disabled
)
125 static bool cpt_can_enable_serr_int(struct drm_device
*dev
)
127 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
129 struct intel_crtc
*crtc
;
131 assert_spin_locked(&dev_priv
->irq_lock
);
133 for_each_pipe(pipe
) {
134 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
136 if (crtc
->pch_fifo_underrun_disabled
)
143 static void ironlake_set_fifo_underrun_reporting(struct drm_device
*dev
,
144 enum pipe pipe
, bool enable
)
146 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
147 uint32_t bit
= (pipe
== PIPE_A
) ? DE_PIPEA_FIFO_UNDERRUN
:
148 DE_PIPEB_FIFO_UNDERRUN
;
151 ironlake_enable_display_irq(dev_priv
, bit
);
153 ironlake_disable_display_irq(dev_priv
, bit
);
156 static void ivybridge_set_fifo_underrun_reporting(struct drm_device
*dev
,
157 enum pipe pipe
, bool enable
)
159 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
161 I915_WRITE(GEN7_ERR_INT
, ERR_INT_FIFO_UNDERRUN(pipe
));
163 if (!ivb_can_enable_err_int(dev
))
166 ironlake_enable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
168 bool was_enabled
= !(I915_READ(DEIMR
) & DE_ERR_INT_IVB
);
170 /* Change the state _after_ we've read out the current one. */
171 ironlake_disable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
174 (I915_READ(GEN7_ERR_INT
) & ERR_INT_FIFO_UNDERRUN(pipe
))) {
175 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
182 * ibx_display_interrupt_update - update SDEIMR
183 * @dev_priv: driver private
184 * @interrupt_mask: mask of interrupt bits to update
185 * @enabled_irq_mask: mask of interrupt bits to enable
187 static void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
188 uint32_t interrupt_mask
,
189 uint32_t enabled_irq_mask
)
191 uint32_t sdeimr
= I915_READ(SDEIMR
);
192 sdeimr
&= ~interrupt_mask
;
193 sdeimr
|= (~enabled_irq_mask
& interrupt_mask
);
195 assert_spin_locked(&dev_priv
->irq_lock
);
197 I915_WRITE(SDEIMR
, sdeimr
);
198 POSTING_READ(SDEIMR
);
200 #define ibx_enable_display_interrupt(dev_priv, bits) \
201 ibx_display_interrupt_update((dev_priv), (bits), (bits))
202 #define ibx_disable_display_interrupt(dev_priv, bits) \
203 ibx_display_interrupt_update((dev_priv), (bits), 0)
205 static void ibx_set_fifo_underrun_reporting(struct drm_device
*dev
,
206 enum transcoder pch_transcoder
,
209 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
210 uint32_t bit
= (pch_transcoder
== TRANSCODER_A
) ?
211 SDE_TRANSA_FIFO_UNDER
: SDE_TRANSB_FIFO_UNDER
;
214 ibx_enable_display_interrupt(dev_priv
, bit
);
216 ibx_disable_display_interrupt(dev_priv
, bit
);
219 static void cpt_set_fifo_underrun_reporting(struct drm_device
*dev
,
220 enum transcoder pch_transcoder
,
223 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
227 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
));
229 if (!cpt_can_enable_serr_int(dev
))
232 ibx_enable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
234 uint32_t tmp
= I915_READ(SERR_INT
);
235 bool was_enabled
= !(I915_READ(SDEIMR
) & SDE_ERROR_CPT
);
237 /* Change the state _after_ we've read out the current one. */
238 ibx_disable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
241 (tmp
& SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
))) {
242 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
243 transcoder_name(pch_transcoder
));
249 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
252 * @enable: true if we want to report FIFO underrun errors, false otherwise
254 * This function makes us disable or enable CPU fifo underruns for a specific
255 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
256 * reporting for one pipe may also disable all the other CPU error interruts for
257 * the other pipes, due to the fact that there's just one interrupt mask/enable
258 * bit for all the pipes.
260 * Returns the previous state of underrun reporting.
262 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device
*dev
,
263 enum pipe pipe
, bool enable
)
265 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
266 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
267 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
271 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
273 ret
= !intel_crtc
->cpu_fifo_underrun_disabled
;
278 intel_crtc
->cpu_fifo_underrun_disabled
= !enable
;
280 if (IS_GEN5(dev
) || IS_GEN6(dev
))
281 ironlake_set_fifo_underrun_reporting(dev
, pipe
, enable
);
282 else if (IS_GEN7(dev
))
283 ivybridge_set_fifo_underrun_reporting(dev
, pipe
, enable
);
286 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
291 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
293 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
294 * @enable: true if we want to report FIFO underrun errors, false otherwise
296 * This function makes us disable or enable PCH fifo underruns for a specific
297 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
298 * underrun reporting for one transcoder may also disable all the other PCH
299 * error interruts for the other transcoders, due to the fact that there's just
300 * one interrupt mask/enable bit for all the transcoders.
302 * Returns the previous state of underrun reporting.
304 bool intel_set_pch_fifo_underrun_reporting(struct drm_device
*dev
,
305 enum transcoder pch_transcoder
,
308 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
309 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pch_transcoder
];
310 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
315 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
316 * has only one pch transcoder A that all pipes can use. To avoid racy
317 * pch transcoder -> pipe lookups from interrupt code simply store the
318 * underrun statistics in crtc A. Since we never expose this anywhere
319 * nor use it outside of the fifo underrun code here using the "wrong"
320 * crtc on LPT won't cause issues.
323 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
325 ret
= !intel_crtc
->pch_fifo_underrun_disabled
;
330 intel_crtc
->pch_fifo_underrun_disabled
= !enable
;
332 if (HAS_PCH_IBX(dev
))
333 ibx_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
335 cpt_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
338 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
344 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
346 u32 reg
= PIPESTAT(pipe
);
347 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
349 assert_spin_locked(&dev_priv
->irq_lock
);
351 if ((pipestat
& mask
) == mask
)
354 /* Enable the interrupt, clear any pending status */
355 pipestat
|= mask
| (mask
>> 16);
356 I915_WRITE(reg
, pipestat
);
361 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
363 u32 reg
= PIPESTAT(pipe
);
364 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
366 assert_spin_locked(&dev_priv
->irq_lock
);
368 if ((pipestat
& mask
) == 0)
372 I915_WRITE(reg
, pipestat
);
377 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
379 static void i915_enable_asle_pipestat(struct drm_device
*dev
)
381 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
382 unsigned long irqflags
;
384 if (!dev_priv
->opregion
.asle
|| !IS_MOBILE(dev
))
387 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
389 i915_enable_pipestat(dev_priv
, 1, PIPE_LEGACY_BLC_EVENT_ENABLE
);
390 if (INTEL_INFO(dev
)->gen
>= 4)
391 i915_enable_pipestat(dev_priv
, 0, PIPE_LEGACY_BLC_EVENT_ENABLE
);
393 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
397 * i915_pipe_enabled - check if a pipe is enabled
399 * @pipe: pipe to check
401 * Reading certain registers when the pipe is disabled can hang the chip.
402 * Use this routine to make sure the PLL is running and the pipe is active
403 * before reading such registers if unsure.
406 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
408 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
410 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
411 /* Locking is horribly broken here, but whatever. */
412 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
413 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
415 return intel_crtc
->active
;
417 return I915_READ(PIPECONF(pipe
)) & PIPECONF_ENABLE
;
421 /* Called from drm generic code, passed a 'crtc', which
422 * we use as a pipe index
424 static u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
426 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
427 unsigned long high_frame
;
428 unsigned long low_frame
;
429 u32 high1
, high2
, low
;
431 if (!i915_pipe_enabled(dev
, pipe
)) {
432 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
433 "pipe %c\n", pipe_name(pipe
));
437 high_frame
= PIPEFRAME(pipe
);
438 low_frame
= PIPEFRAMEPIXEL(pipe
);
441 * High & low register fields aren't synchronized, so make sure
442 * we get a low value that's stable across two reads of the high
446 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
447 low
= I915_READ(low_frame
) & PIPE_FRAME_LOW_MASK
;
448 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
449 } while (high1
!= high2
);
451 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
452 low
>>= PIPE_FRAME_LOW_SHIFT
;
453 return (high1
<< 8) | low
;
456 static u32
gm45_get_vblank_counter(struct drm_device
*dev
, int pipe
)
458 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
459 int reg
= PIPE_FRMCOUNT_GM45(pipe
);
461 if (!i915_pipe_enabled(dev
, pipe
)) {
462 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
463 "pipe %c\n", pipe_name(pipe
));
467 return I915_READ(reg
);
470 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, int pipe
,
471 int *vpos
, int *hpos
)
473 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
474 u32 vbl
= 0, position
= 0;
475 int vbl_start
, vbl_end
, htotal
, vtotal
;
478 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
481 if (!i915_pipe_enabled(dev
, pipe
)) {
482 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
483 "pipe %c\n", pipe_name(pipe
));
488 vtotal
= 1 + ((I915_READ(VTOTAL(cpu_transcoder
)) >> 16) & 0x1fff);
490 if (INTEL_INFO(dev
)->gen
>= 4) {
491 /* No obvious pixelcount register. Only query vertical
492 * scanout position from Display scan line register.
494 position
= I915_READ(PIPEDSL(pipe
));
496 /* Decode into vertical scanout position. Don't have
497 * horizontal scanout position.
499 *vpos
= position
& 0x1fff;
502 /* Have access to pixelcount since start of frame.
503 * We can split this into vertical and horizontal
506 position
= (I915_READ(PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
508 htotal
= 1 + ((I915_READ(HTOTAL(cpu_transcoder
)) >> 16) & 0x1fff);
509 *vpos
= position
/ htotal
;
510 *hpos
= position
- (*vpos
* htotal
);
513 /* Query vblank area. */
514 vbl
= I915_READ(VBLANK(cpu_transcoder
));
516 /* Test position against vblank region. */
517 vbl_start
= vbl
& 0x1fff;
518 vbl_end
= (vbl
>> 16) & 0x1fff;
520 if ((*vpos
< vbl_start
) || (*vpos
> vbl_end
))
523 /* Inside "upper part" of vblank area? Apply corrective offset: */
524 if (in_vbl
&& (*vpos
>= vbl_start
))
525 *vpos
= *vpos
- vtotal
;
527 /* Readouts valid? */
529 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
533 ret
|= DRM_SCANOUTPOS_INVBL
;
538 static int i915_get_vblank_timestamp(struct drm_device
*dev
, int pipe
,
540 struct timeval
*vblank_time
,
543 struct drm_crtc
*crtc
;
545 if (pipe
< 0 || pipe
>= INTEL_INFO(dev
)->num_pipes
) {
546 DRM_ERROR("Invalid crtc %d\n", pipe
);
550 /* Get drm_crtc to timestamp: */
551 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
553 DRM_ERROR("Invalid crtc %d\n", pipe
);
557 if (!crtc
->enabled
) {
558 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
562 /* Helper routine in DRM core does all the work: */
563 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
568 static int intel_hpd_irq_event(struct drm_device
*dev
, struct drm_connector
*connector
)
570 enum drm_connector_status old_status
;
572 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
573 old_status
= connector
->status
;
575 connector
->status
= connector
->funcs
->detect(connector
, false);
576 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
578 drm_get_connector_name(connector
),
579 old_status
, connector
->status
);
580 return (old_status
!= connector
->status
);
584 * Handle hotplug events outside the interrupt handler proper.
586 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
588 static void i915_hotplug_work_func(struct work_struct
*work
)
590 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
592 struct drm_device
*dev
= dev_priv
->dev
;
593 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
594 struct intel_connector
*intel_connector
;
595 struct intel_encoder
*intel_encoder
;
596 struct drm_connector
*connector
;
597 unsigned long irqflags
;
598 bool hpd_disabled
= false;
599 bool changed
= false;
602 /* HPD irq before everything is fully set up. */
603 if (!dev_priv
->enable_hotplug_processing
)
606 mutex_lock(&mode_config
->mutex
);
607 DRM_DEBUG_KMS("running encoder hotplug functions\n");
609 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
611 hpd_event_bits
= dev_priv
->hpd_event_bits
;
612 dev_priv
->hpd_event_bits
= 0;
613 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
614 intel_connector
= to_intel_connector(connector
);
615 intel_encoder
= intel_connector
->encoder
;
616 if (intel_encoder
->hpd_pin
> HPD_NONE
&&
617 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_MARK_DISABLED
&&
618 connector
->polled
== DRM_CONNECTOR_POLL_HPD
) {
619 DRM_INFO("HPD interrupt storm detected on connector %s: "
620 "switching from hotplug detection to polling\n",
621 drm_get_connector_name(connector
));
622 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
= HPD_DISABLED
;
623 connector
->polled
= DRM_CONNECTOR_POLL_CONNECT
624 | DRM_CONNECTOR_POLL_DISCONNECT
;
627 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
628 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
629 drm_get_connector_name(connector
), intel_encoder
->hpd_pin
);
632 /* if there were no outputs to poll, poll was disabled,
633 * therefore make sure it's enabled when disabling HPD on
636 drm_kms_helper_poll_enable(dev
);
637 mod_timer(&dev_priv
->hotplug_reenable_timer
,
638 jiffies
+ msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY
));
641 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
643 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
644 intel_connector
= to_intel_connector(connector
);
645 intel_encoder
= intel_connector
->encoder
;
646 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
647 if (intel_encoder
->hot_plug
)
648 intel_encoder
->hot_plug(intel_encoder
);
649 if (intel_hpd_irq_event(dev
, connector
))
653 mutex_unlock(&mode_config
->mutex
);
656 drm_kms_helper_hotplug_event(dev
);
659 static void ironlake_rps_change_irq_handler(struct drm_device
*dev
)
661 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
662 u32 busy_up
, busy_down
, max_avg
, min_avg
;
665 spin_lock(&mchdev_lock
);
667 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
669 new_delay
= dev_priv
->ips
.cur_delay
;
671 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
672 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
673 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
674 max_avg
= I915_READ(RCBMAXAVG
);
675 min_avg
= I915_READ(RCBMINAVG
);
677 /* Handle RCS change request from hw */
678 if (busy_up
> max_avg
) {
679 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
680 new_delay
= dev_priv
->ips
.cur_delay
- 1;
681 if (new_delay
< dev_priv
->ips
.max_delay
)
682 new_delay
= dev_priv
->ips
.max_delay
;
683 } else if (busy_down
< min_avg
) {
684 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
685 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
686 if (new_delay
> dev_priv
->ips
.min_delay
)
687 new_delay
= dev_priv
->ips
.min_delay
;
690 if (ironlake_set_drps(dev
, new_delay
))
691 dev_priv
->ips
.cur_delay
= new_delay
;
693 spin_unlock(&mchdev_lock
);
698 static void notify_ring(struct drm_device
*dev
,
699 struct intel_ring_buffer
*ring
)
701 if (ring
->obj
== NULL
)
704 trace_i915_gem_request_complete(ring
, ring
->get_seqno(ring
, false));
706 wake_up_all(&ring
->irq_queue
);
707 i915_queue_hangcheck(dev
);
710 static void gen6_pm_rps_work(struct work_struct
*work
)
712 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
717 spin_lock_irq(&dev_priv
->irq_lock
);
718 pm_iir
= dev_priv
->rps
.pm_iir
;
719 dev_priv
->rps
.pm_iir
= 0;
720 pm_imr
= I915_READ(GEN6_PMIMR
);
721 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
722 I915_WRITE(GEN6_PMIMR
, pm_imr
& ~GEN6_PM_RPS_EVENTS
);
723 spin_unlock_irq(&dev_priv
->irq_lock
);
725 if ((pm_iir
& GEN6_PM_RPS_EVENTS
) == 0)
728 mutex_lock(&dev_priv
->rps
.hw_lock
);
730 if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
) {
731 new_delay
= dev_priv
->rps
.cur_delay
+ 1;
734 * For better performance, jump directly
735 * to RPe if we're below it.
737 if (IS_VALLEYVIEW(dev_priv
->dev
) &&
738 dev_priv
->rps
.cur_delay
< dev_priv
->rps
.rpe_delay
)
739 new_delay
= dev_priv
->rps
.rpe_delay
;
741 new_delay
= dev_priv
->rps
.cur_delay
- 1;
743 /* sysfs frequency interfaces may have snuck in while servicing the
746 if (new_delay
>= dev_priv
->rps
.min_delay
&&
747 new_delay
<= dev_priv
->rps
.max_delay
) {
748 if (IS_VALLEYVIEW(dev_priv
->dev
))
749 valleyview_set_rps(dev_priv
->dev
, new_delay
);
751 gen6_set_rps(dev_priv
->dev
, new_delay
);
754 if (IS_VALLEYVIEW(dev_priv
->dev
)) {
756 * On VLV, when we enter RC6 we may not be at the minimum
757 * voltage level, so arm a timer to check. It should only
758 * fire when there's activity or once after we've entered
759 * RC6, and then won't be re-armed until the next RPS interrupt.
761 mod_delayed_work(dev_priv
->wq
, &dev_priv
->rps
.vlv_work
,
762 msecs_to_jiffies(100));
765 mutex_unlock(&dev_priv
->rps
.hw_lock
);
770 * ivybridge_parity_work - Workqueue called when a parity error interrupt
772 * @work: workqueue struct
774 * Doesn't actually do anything except notify userspace. As a consequence of
775 * this event, userspace should try to remap the bad rows since statistically
776 * it is likely the same row is more likely to go bad again.
778 static void ivybridge_parity_work(struct work_struct
*work
)
780 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
781 l3_parity
.error_work
);
782 u32 error_status
, row
, bank
, subbank
;
783 char *parity_event
[5];
787 /* We must turn off DOP level clock gating to access the L3 registers.
788 * In order to prevent a get/put style interface, acquire struct mutex
789 * any time we access those registers.
791 mutex_lock(&dev_priv
->dev
->struct_mutex
);
793 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
794 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
795 POSTING_READ(GEN7_MISCCPCTL
);
797 error_status
= I915_READ(GEN7_L3CDERRST1
);
798 row
= GEN7_PARITY_ERROR_ROW(error_status
);
799 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
800 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
802 I915_WRITE(GEN7_L3CDERRST1
, GEN7_PARITY_ERROR_VALID
|
803 GEN7_L3CDERRST1_ENABLE
);
804 POSTING_READ(GEN7_L3CDERRST1
);
806 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
808 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
809 dev_priv
->gt_irq_mask
&= ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
810 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
811 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
813 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
815 parity_event
[0] = "L3_PARITY_ERROR=1";
816 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
817 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
818 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
819 parity_event
[4] = NULL
;
821 kobject_uevent_env(&dev_priv
->dev
->primary
->kdev
.kobj
,
822 KOBJ_CHANGE
, parity_event
);
824 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
827 kfree(parity_event
[3]);
828 kfree(parity_event
[2]);
829 kfree(parity_event
[1]);
832 static void ivybridge_parity_error_irq_handler(struct drm_device
*dev
)
834 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
836 if (!HAS_L3_GPU_CACHE(dev
))
839 spin_lock(&dev_priv
->irq_lock
);
840 dev_priv
->gt_irq_mask
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
841 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
842 spin_unlock(&dev_priv
->irq_lock
);
844 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
847 static void ilk_gt_irq_handler(struct drm_device
*dev
,
848 struct drm_i915_private
*dev_priv
,
852 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
853 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
854 if (gt_iir
& ILK_BSD_USER_INTERRUPT
)
855 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
858 static void snb_gt_irq_handler(struct drm_device
*dev
,
859 struct drm_i915_private
*dev_priv
,
864 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
865 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
866 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
867 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
868 if (gt_iir
& GT_BLT_USER_INTERRUPT
)
869 notify_ring(dev
, &dev_priv
->ring
[BCS
]);
871 if (gt_iir
& (GT_BLT_CS_ERROR_INTERRUPT
|
872 GT_BSD_CS_ERROR_INTERRUPT
|
873 GT_RENDER_CS_MASTER_ERROR_INTERRUPT
)) {
874 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir
);
875 i915_handle_error(dev
, false);
878 if (gt_iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT
)
879 ivybridge_parity_error_irq_handler(dev
);
882 /* Legacy way of handling PM interrupts */
883 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
,
887 * IIR bits should never already be set because IMR should
888 * prevent an interrupt from being shown in IIR. The warning
889 * displays a case where we've unsafely cleared
890 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
891 * type is not a problem, it displays a problem in the logic.
893 * The mask bit in IMR is cleared by dev_priv->rps.work.
896 spin_lock(&dev_priv
->irq_lock
);
897 dev_priv
->rps
.pm_iir
|= pm_iir
;
898 I915_WRITE(GEN6_PMIMR
, dev_priv
->rps
.pm_iir
);
899 POSTING_READ(GEN6_PMIMR
);
900 spin_unlock(&dev_priv
->irq_lock
);
902 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
905 #define HPD_STORM_DETECT_PERIOD 1000
906 #define HPD_STORM_THRESHOLD 5
908 static inline void intel_hpd_irq_handler(struct drm_device
*dev
,
912 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
914 bool storm_detected
= false;
916 if (!hotplug_trigger
)
919 spin_lock(&dev_priv
->irq_lock
);
920 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
922 if (!(hpd
[i
] & hotplug_trigger
) ||
923 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
)
926 dev_priv
->hpd_event_bits
|= (1 << i
);
927 if (!time_in_range(jiffies
, dev_priv
->hpd_stats
[i
].hpd_last_jiffies
,
928 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
929 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD
))) {
930 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
= jiffies
;
931 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
932 } else if (dev_priv
->hpd_stats
[i
].hpd_cnt
> HPD_STORM_THRESHOLD
) {
933 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_MARK_DISABLED
;
934 dev_priv
->hpd_event_bits
&= ~(1 << i
);
935 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i
);
936 storm_detected
= true;
938 dev_priv
->hpd_stats
[i
].hpd_cnt
++;
943 dev_priv
->display
.hpd_irq_setup(dev
);
944 spin_unlock(&dev_priv
->irq_lock
);
946 queue_work(dev_priv
->wq
,
947 &dev_priv
->hotplug_work
);
950 static void gmbus_irq_handler(struct drm_device
*dev
)
952 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
954 wake_up_all(&dev_priv
->gmbus_wait_queue
);
957 static void dp_aux_irq_handler(struct drm_device
*dev
)
959 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
961 wake_up_all(&dev_priv
->gmbus_wait_queue
);
964 /* Unlike gen6_rps_irq_handler() from which this function is originally derived,
965 * we must be able to deal with other PM interrupts. This is complicated because
966 * of the way in which we use the masks to defer the RPS work (which for
967 * posterity is necessary because of forcewake).
969 static void hsw_pm_irq_handler(struct drm_i915_private
*dev_priv
,
972 if (pm_iir
& GEN6_PM_RPS_EVENTS
) {
973 spin_lock(&dev_priv
->irq_lock
);
974 dev_priv
->rps
.pm_iir
|= pm_iir
& GEN6_PM_RPS_EVENTS
;
975 I915_WRITE(GEN6_PMIMR
, dev_priv
->rps
.pm_iir
);
976 /* never want to mask useful interrupts. (also posting read) */
977 WARN_ON(I915_READ_NOTRACE(GEN6_PMIMR
) & ~GEN6_PM_RPS_EVENTS
);
978 spin_unlock(&dev_priv
->irq_lock
);
980 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
983 if (pm_iir
& PM_VEBOX_USER_INTERRUPT
)
984 notify_ring(dev_priv
->dev
, &dev_priv
->ring
[VECS
]);
986 if (pm_iir
& PM_VEBOX_CS_ERROR_INTERRUPT
) {
987 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir
);
988 i915_handle_error(dev_priv
->dev
, false);
992 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
994 struct drm_device
*dev
= (struct drm_device
*) arg
;
995 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
996 u32 iir
, gt_iir
, pm_iir
;
997 irqreturn_t ret
= IRQ_NONE
;
998 unsigned long irqflags
;
1000 u32 pipe_stats
[I915_MAX_PIPES
];
1002 atomic_inc(&dev_priv
->irq_received
);
1005 iir
= I915_READ(VLV_IIR
);
1006 gt_iir
= I915_READ(GTIIR
);
1007 pm_iir
= I915_READ(GEN6_PMIIR
);
1009 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
1014 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1016 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1017 for_each_pipe(pipe
) {
1018 int reg
= PIPESTAT(pipe
);
1019 pipe_stats
[pipe
] = I915_READ(reg
);
1022 * Clear the PIPE*STAT regs before the IIR
1024 if (pipe_stats
[pipe
] & 0x8000ffff) {
1025 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
1026 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1028 I915_WRITE(reg
, pipe_stats
[pipe
]);
1031 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1033 for_each_pipe(pipe
) {
1034 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
)
1035 drm_handle_vblank(dev
, pipe
);
1037 if (pipe_stats
[pipe
] & PLANE_FLIPDONE_INT_STATUS_VLV
) {
1038 intel_prepare_page_flip(dev
, pipe
);
1039 intel_finish_page_flip(dev
, pipe
);
1043 /* Consume port. Then clear IIR or we'll miss events */
1044 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
1045 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1046 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
1048 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1051 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
1053 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1054 I915_READ(PORT_HOTPLUG_STAT
);
1057 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1058 gmbus_irq_handler(dev
);
1060 if (pm_iir
& GEN6_PM_RPS_EVENTS
)
1061 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1063 I915_WRITE(GTIIR
, gt_iir
);
1064 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1065 I915_WRITE(VLV_IIR
, iir
);
1072 static void ibx_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1074 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1076 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK
;
1078 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_ibx
);
1080 if (pch_iir
& SDE_AUDIO_POWER_MASK
) {
1081 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK
) >>
1082 SDE_AUDIO_POWER_SHIFT
);
1083 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1087 if (pch_iir
& SDE_AUX_MASK
)
1088 dp_aux_irq_handler(dev
);
1090 if (pch_iir
& SDE_GMBUS
)
1091 gmbus_irq_handler(dev
);
1093 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
1094 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1096 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
1097 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1099 if (pch_iir
& SDE_POISON
)
1100 DRM_ERROR("PCH poison interrupt\n");
1102 if (pch_iir
& SDE_FDI_MASK
)
1104 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1106 I915_READ(FDI_RX_IIR(pipe
)));
1108 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
1109 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1111 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
1112 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1114 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
1115 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1117 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1119 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
1120 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1122 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1125 static void ivb_err_int_handler(struct drm_device
*dev
)
1127 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1128 u32 err_int
= I915_READ(GEN7_ERR_INT
);
1130 if (err_int
& ERR_INT_POISON
)
1131 DRM_ERROR("Poison interrupt\n");
1133 if (err_int
& ERR_INT_FIFO_UNDERRUN_A
)
1134 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_A
, false))
1135 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1137 if (err_int
& ERR_INT_FIFO_UNDERRUN_B
)
1138 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_B
, false))
1139 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1141 if (err_int
& ERR_INT_FIFO_UNDERRUN_C
)
1142 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_C
, false))
1143 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1145 I915_WRITE(GEN7_ERR_INT
, err_int
);
1148 static void cpt_serr_int_handler(struct drm_device
*dev
)
1150 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1151 u32 serr_int
= I915_READ(SERR_INT
);
1153 if (serr_int
& SERR_INT_POISON
)
1154 DRM_ERROR("PCH poison interrupt\n");
1156 if (serr_int
& SERR_INT_TRANS_A_FIFO_UNDERRUN
)
1157 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1159 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1161 if (serr_int
& SERR_INT_TRANS_B_FIFO_UNDERRUN
)
1162 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1164 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1166 if (serr_int
& SERR_INT_TRANS_C_FIFO_UNDERRUN
)
1167 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_C
,
1169 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1171 I915_WRITE(SERR_INT
, serr_int
);
1174 static void cpt_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1176 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1178 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_CPT
;
1180 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_cpt
);
1182 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) {
1183 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
1184 SDE_AUDIO_POWER_SHIFT_CPT
);
1185 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1189 if (pch_iir
& SDE_AUX_MASK_CPT
)
1190 dp_aux_irq_handler(dev
);
1192 if (pch_iir
& SDE_GMBUS_CPT
)
1193 gmbus_irq_handler(dev
);
1195 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
1196 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1198 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
1199 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1201 if (pch_iir
& SDE_FDI_MASK_CPT
)
1203 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1205 I915_READ(FDI_RX_IIR(pipe
)));
1207 if (pch_iir
& SDE_ERROR_CPT
)
1208 cpt_serr_int_handler(dev
);
1211 static void ilk_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
1213 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1215 if (de_iir
& DE_AUX_CHANNEL_A
)
1216 dp_aux_irq_handler(dev
);
1218 if (de_iir
& DE_GSE
)
1219 intel_opregion_asle_intr(dev
);
1221 if (de_iir
& DE_PIPEA_VBLANK
)
1222 drm_handle_vblank(dev
, 0);
1224 if (de_iir
& DE_PIPEB_VBLANK
)
1225 drm_handle_vblank(dev
, 1);
1227 if (de_iir
& DE_POISON
)
1228 DRM_ERROR("Poison interrupt\n");
1230 if (de_iir
& DE_PIPEA_FIFO_UNDERRUN
)
1231 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_A
, false))
1232 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1234 if (de_iir
& DE_PIPEB_FIFO_UNDERRUN
)
1235 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_B
, false))
1236 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1238 if (de_iir
& DE_PLANEA_FLIP_DONE
) {
1239 intel_prepare_page_flip(dev
, 0);
1240 intel_finish_page_flip_plane(dev
, 0);
1243 if (de_iir
& DE_PLANEB_FLIP_DONE
) {
1244 intel_prepare_page_flip(dev
, 1);
1245 intel_finish_page_flip_plane(dev
, 1);
1248 /* check event from PCH */
1249 if (de_iir
& DE_PCH_EVENT
) {
1250 u32 pch_iir
= I915_READ(SDEIIR
);
1252 if (HAS_PCH_CPT(dev
))
1253 cpt_irq_handler(dev
, pch_iir
);
1255 ibx_irq_handler(dev
, pch_iir
);
1257 /* should clear PCH hotplug event before clear CPU irq */
1258 I915_WRITE(SDEIIR
, pch_iir
);
1261 if (IS_GEN5(dev
) && de_iir
& DE_PCU_EVENT
)
1262 ironlake_rps_change_irq_handler(dev
);
1265 static void ivb_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
1267 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1270 if (de_iir
& DE_ERR_INT_IVB
)
1271 ivb_err_int_handler(dev
);
1273 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
1274 dp_aux_irq_handler(dev
);
1276 if (de_iir
& DE_GSE_IVB
)
1277 intel_opregion_asle_intr(dev
);
1279 for (i
= 0; i
< 3; i
++) {
1280 if (de_iir
& (DE_PIPEA_VBLANK_IVB
<< (5 * i
)))
1281 drm_handle_vblank(dev
, i
);
1282 if (de_iir
& (DE_PLANEA_FLIP_DONE_IVB
<< (5 * i
))) {
1283 intel_prepare_page_flip(dev
, i
);
1284 intel_finish_page_flip_plane(dev
, i
);
1288 /* check event from PCH */
1289 if (!HAS_PCH_NOP(dev
) && (de_iir
& DE_PCH_EVENT_IVB
)) {
1290 u32 pch_iir
= I915_READ(SDEIIR
);
1292 cpt_irq_handler(dev
, pch_iir
);
1294 /* clear PCH hotplug event before clear CPU irq */
1295 I915_WRITE(SDEIIR
, pch_iir
);
1299 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
1301 struct drm_device
*dev
= (struct drm_device
*) arg
;
1302 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1303 u32 de_iir
, gt_iir
, de_ier
, sde_ier
= 0;
1304 irqreturn_t ret
= IRQ_NONE
;
1306 atomic_inc(&dev_priv
->irq_received
);
1308 /* We get interrupts on unclaimed registers, so check for this before we
1309 * do any I915_{READ,WRITE}. */
1310 if (IS_HASWELL(dev
) &&
1311 (I915_READ_NOTRACE(FPGA_DBG
) & FPGA_DBG_RM_NOCLAIM
)) {
1312 DRM_ERROR("Unclaimed register before interrupt\n");
1313 I915_WRITE_NOTRACE(FPGA_DBG
, FPGA_DBG_RM_NOCLAIM
);
1316 /* disable master interrupt before clearing iir */
1317 de_ier
= I915_READ(DEIER
);
1318 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
1319 POSTING_READ(DEIER
);
1321 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1322 * interrupts will will be stored on its back queue, and then we'll be
1323 * able to process them after we restore SDEIER (as soon as we restore
1324 * it, we'll get an interrupt if SDEIIR still has something to process
1325 * due to its back queue). */
1326 if (!HAS_PCH_NOP(dev
)) {
1327 sde_ier
= I915_READ(SDEIER
);
1328 I915_WRITE(SDEIER
, 0);
1329 POSTING_READ(SDEIER
);
1332 /* On Haswell, also mask ERR_INT because we don't want to risk
1333 * generating "unclaimed register" interrupts from inside the interrupt
1335 if (IS_HASWELL(dev
)) {
1336 spin_lock(&dev_priv
->irq_lock
);
1337 ironlake_disable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
1338 spin_unlock(&dev_priv
->irq_lock
);
1341 gt_iir
= I915_READ(GTIIR
);
1344 ilk_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1346 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1347 I915_WRITE(GTIIR
, gt_iir
);
1351 de_iir
= I915_READ(DEIIR
);
1353 if (INTEL_INFO(dev
)->gen
>= 7)
1354 ivb_display_irq_handler(dev
, de_iir
);
1356 ilk_display_irq_handler(dev
, de_iir
);
1357 I915_WRITE(DEIIR
, de_iir
);
1361 if (INTEL_INFO(dev
)->gen
>= 6) {
1362 u32 pm_iir
= I915_READ(GEN6_PMIIR
);
1364 if (IS_HASWELL(dev
))
1365 hsw_pm_irq_handler(dev_priv
, pm_iir
);
1366 else if (pm_iir
& GEN6_PM_RPS_EVENTS
)
1367 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1368 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1373 if (IS_HASWELL(dev
)) {
1374 spin_lock(&dev_priv
->irq_lock
);
1375 if (ivb_can_enable_err_int(dev
))
1376 ironlake_enable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
1377 spin_unlock(&dev_priv
->irq_lock
);
1380 I915_WRITE(DEIER
, de_ier
);
1381 POSTING_READ(DEIER
);
1382 if (!HAS_PCH_NOP(dev
)) {
1383 I915_WRITE(SDEIER
, sde_ier
);
1384 POSTING_READ(SDEIER
);
1391 * i915_error_work_func - do process context error handling work
1392 * @work: work struct
1394 * Fire an error uevent so userspace can see that a hang or error
1397 static void i915_error_work_func(struct work_struct
*work
)
1399 struct i915_gpu_error
*error
= container_of(work
, struct i915_gpu_error
,
1401 drm_i915_private_t
*dev_priv
= container_of(error
, drm_i915_private_t
,
1403 struct drm_device
*dev
= dev_priv
->dev
;
1404 struct intel_ring_buffer
*ring
;
1405 char *error_event
[] = { "ERROR=1", NULL
};
1406 char *reset_event
[] = { "RESET=1", NULL
};
1407 char *reset_done_event
[] = { "ERROR=0", NULL
};
1410 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
, error_event
);
1413 * Note that there's only one work item which does gpu resets, so we
1414 * need not worry about concurrent gpu resets potentially incrementing
1415 * error->reset_counter twice. We only need to take care of another
1416 * racing irq/hangcheck declaring the gpu dead for a second time. A
1417 * quick check for that is good enough: schedule_work ensures the
1418 * correct ordering between hang detection and this work item, and since
1419 * the reset in-progress bit is only ever set by code outside of this
1420 * work we don't need to worry about any other races.
1422 if (i915_reset_in_progress(error
) && !i915_terminally_wedged(error
)) {
1423 DRM_DEBUG_DRIVER("resetting chip\n");
1424 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
,
1427 ret
= i915_reset(dev
);
1431 * After all the gem state is reset, increment the reset
1432 * counter and wake up everyone waiting for the reset to
1435 * Since unlock operations are a one-sided barrier only,
1436 * we need to insert a barrier here to order any seqno
1438 * the counter increment.
1440 smp_mb__before_atomic_inc();
1441 atomic_inc(&dev_priv
->gpu_error
.reset_counter
);
1443 kobject_uevent_env(&dev
->primary
->kdev
.kobj
,
1444 KOBJ_CHANGE
, reset_done_event
);
1446 atomic_set(&error
->reset_counter
, I915_WEDGED
);
1449 for_each_ring(ring
, dev_priv
, i
)
1450 wake_up_all(&ring
->irq_queue
);
1452 intel_display_handle_reset(dev
);
1454 wake_up_all(&dev_priv
->gpu_error
.reset_queue
);
1458 static void i915_report_and_clear_eir(struct drm_device
*dev
)
1460 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1461 uint32_t instdone
[I915_NUM_INSTDONE_REG
];
1462 u32 eir
= I915_READ(EIR
);
1468 pr_err("render error detected, EIR: 0x%08x\n", eir
);
1470 i915_get_extra_instdone(dev
, instdone
);
1473 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
1474 u32 ipeir
= I915_READ(IPEIR_I965
);
1476 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1477 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1478 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
1479 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
1480 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1481 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1482 I915_WRITE(IPEIR_I965
, ipeir
);
1483 POSTING_READ(IPEIR_I965
);
1485 if (eir
& GM45_ERROR_PAGE_TABLE
) {
1486 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1487 pr_err("page table error\n");
1488 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1489 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1490 POSTING_READ(PGTBL_ER
);
1494 if (!IS_GEN2(dev
)) {
1495 if (eir
& I915_ERROR_PAGE_TABLE
) {
1496 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1497 pr_err("page table error\n");
1498 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1499 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1500 POSTING_READ(PGTBL_ER
);
1504 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
1505 pr_err("memory refresh error:\n");
1507 pr_err("pipe %c stat: 0x%08x\n",
1508 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
1509 /* pipestat has already been acked */
1511 if (eir
& I915_ERROR_INSTRUCTION
) {
1512 pr_err("instruction error\n");
1513 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
1514 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
1515 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
1516 if (INTEL_INFO(dev
)->gen
< 4) {
1517 u32 ipeir
= I915_READ(IPEIR
);
1519 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
1520 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
1521 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
1522 I915_WRITE(IPEIR
, ipeir
);
1523 POSTING_READ(IPEIR
);
1525 u32 ipeir
= I915_READ(IPEIR_I965
);
1527 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1528 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1529 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1530 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1531 I915_WRITE(IPEIR_I965
, ipeir
);
1532 POSTING_READ(IPEIR_I965
);
1536 I915_WRITE(EIR
, eir
);
1538 eir
= I915_READ(EIR
);
1541 * some errors might have become stuck,
1544 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
1545 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
1546 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
1551 * i915_handle_error - handle an error interrupt
1554 * Do some basic checking of regsiter state at error interrupt time and
1555 * dump it to the syslog. Also call i915_capture_error_state() to make
1556 * sure we get a record and make it available in debugfs. Fire a uevent
1557 * so userspace knows something bad happened (should trigger collection
1558 * of a ring dump etc.).
1560 void i915_handle_error(struct drm_device
*dev
, bool wedged
)
1562 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1563 struct intel_ring_buffer
*ring
;
1566 i915_capture_error_state(dev
);
1567 i915_report_and_clear_eir(dev
);
1570 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG
,
1571 &dev_priv
->gpu_error
.reset_counter
);
1574 * Wakeup waiting processes so that the reset work item
1575 * doesn't deadlock trying to grab various locks.
1577 for_each_ring(ring
, dev_priv
, i
)
1578 wake_up_all(&ring
->irq_queue
);
1581 queue_work(dev_priv
->wq
, &dev_priv
->gpu_error
.work
);
1584 static void __always_unused
i915_pageflip_stall_check(struct drm_device
*dev
, int pipe
)
1586 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1587 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1588 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1589 struct drm_i915_gem_object
*obj
;
1590 struct intel_unpin_work
*work
;
1591 unsigned long flags
;
1592 bool stall_detected
;
1594 /* Ignore early vblank irqs */
1595 if (intel_crtc
== NULL
)
1598 spin_lock_irqsave(&dev
->event_lock
, flags
);
1599 work
= intel_crtc
->unpin_work
;
1602 atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
||
1603 !work
->enable_stall_check
) {
1604 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1605 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1609 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1610 obj
= work
->pending_flip_obj
;
1611 if (INTEL_INFO(dev
)->gen
>= 4) {
1612 int dspsurf
= DSPSURF(intel_crtc
->plane
);
1613 stall_detected
= I915_HI_DISPBASE(I915_READ(dspsurf
)) ==
1614 i915_gem_obj_ggtt_offset(obj
);
1616 int dspaddr
= DSPADDR(intel_crtc
->plane
);
1617 stall_detected
= I915_READ(dspaddr
) == (i915_gem_obj_ggtt_offset(obj
) +
1618 crtc
->y
* crtc
->fb
->pitches
[0] +
1619 crtc
->x
* crtc
->fb
->bits_per_pixel
/8);
1622 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1624 if (stall_detected
) {
1625 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1626 intel_prepare_page_flip(dev
, intel_crtc
->plane
);
1630 /* Called from drm generic code, passed 'crtc' which
1631 * we use as a pipe index
1633 static int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
1635 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1636 unsigned long irqflags
;
1638 if (!i915_pipe_enabled(dev
, pipe
))
1641 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1642 if (INTEL_INFO(dev
)->gen
>= 4)
1643 i915_enable_pipestat(dev_priv
, pipe
,
1644 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1646 i915_enable_pipestat(dev_priv
, pipe
,
1647 PIPE_VBLANK_INTERRUPT_ENABLE
);
1649 /* maintain vblank delivery even in deep C-states */
1650 if (dev_priv
->info
->gen
== 3)
1651 I915_WRITE(INSTPM
, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS
));
1652 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1657 static int ironlake_enable_vblank(struct drm_device
*dev
, int pipe
)
1659 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1660 unsigned long irqflags
;
1662 if (!i915_pipe_enabled(dev
, pipe
))
1665 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1666 ironlake_enable_display_irq(dev_priv
, (pipe
== 0) ?
1667 DE_PIPEA_VBLANK
: DE_PIPEB_VBLANK
);
1668 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1673 static int ivybridge_enable_vblank(struct drm_device
*dev
, int pipe
)
1675 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1676 unsigned long irqflags
;
1678 if (!i915_pipe_enabled(dev
, pipe
))
1681 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1682 ironlake_enable_display_irq(dev_priv
,
1683 DE_PIPEA_VBLANK_IVB
<< (5 * pipe
));
1684 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1689 static int valleyview_enable_vblank(struct drm_device
*dev
, int pipe
)
1691 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1692 unsigned long irqflags
;
1695 if (!i915_pipe_enabled(dev
, pipe
))
1698 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1699 imr
= I915_READ(VLV_IMR
);
1701 imr
&= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
1703 imr
&= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1704 I915_WRITE(VLV_IMR
, imr
);
1705 i915_enable_pipestat(dev_priv
, pipe
,
1706 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1707 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1712 /* Called from drm generic code, passed 'crtc' which
1713 * we use as a pipe index
1715 static void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
1717 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1718 unsigned long irqflags
;
1720 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1721 if (dev_priv
->info
->gen
== 3)
1722 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS
));
1724 i915_disable_pipestat(dev_priv
, pipe
,
1725 PIPE_VBLANK_INTERRUPT_ENABLE
|
1726 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1727 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1730 static void ironlake_disable_vblank(struct drm_device
*dev
, int pipe
)
1732 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1733 unsigned long irqflags
;
1735 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1736 ironlake_disable_display_irq(dev_priv
, (pipe
== 0) ?
1737 DE_PIPEA_VBLANK
: DE_PIPEB_VBLANK
);
1738 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1741 static void ivybridge_disable_vblank(struct drm_device
*dev
, int pipe
)
1743 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1744 unsigned long irqflags
;
1746 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1747 ironlake_disable_display_irq(dev_priv
,
1748 DE_PIPEA_VBLANK_IVB
<< (pipe
* 5));
1749 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1752 static void valleyview_disable_vblank(struct drm_device
*dev
, int pipe
)
1754 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1755 unsigned long irqflags
;
1758 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1759 i915_disable_pipestat(dev_priv
, pipe
,
1760 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1761 imr
= I915_READ(VLV_IMR
);
1763 imr
|= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
1765 imr
|= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1766 I915_WRITE(VLV_IMR
, imr
);
1767 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1771 ring_last_seqno(struct intel_ring_buffer
*ring
)
1773 return list_entry(ring
->request_list
.prev
,
1774 struct drm_i915_gem_request
, list
)->seqno
;
1778 ring_idle(struct intel_ring_buffer
*ring
, u32 seqno
)
1780 return (list_empty(&ring
->request_list
) ||
1781 i915_seqno_passed(seqno
, ring_last_seqno(ring
)));
1784 static struct intel_ring_buffer
*
1785 semaphore_waits_for(struct intel_ring_buffer
*ring
, u32
*seqno
)
1787 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1788 u32 cmd
, ipehr
, acthd
, acthd_min
;
1790 ipehr
= I915_READ(RING_IPEHR(ring
->mmio_base
));
1791 if ((ipehr
& ~(0x3 << 16)) !=
1792 (MI_SEMAPHORE_MBOX
| MI_SEMAPHORE_COMPARE
| MI_SEMAPHORE_REGISTER
))
1795 /* ACTHD is likely pointing to the dword after the actual command,
1796 * so scan backwards until we find the MBOX.
1798 acthd
= intel_ring_get_active_head(ring
) & HEAD_ADDR
;
1799 acthd_min
= max((int)acthd
- 3 * 4, 0);
1801 cmd
= ioread32(ring
->virtual_start
+ acthd
);
1806 if (acthd
< acthd_min
)
1810 *seqno
= ioread32(ring
->virtual_start
+acthd
+4)+1;
1811 return &dev_priv
->ring
[(ring
->id
+ (((ipehr
>> 17) & 1) + 1)) % 3];
1814 static int semaphore_passed(struct intel_ring_buffer
*ring
)
1816 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1817 struct intel_ring_buffer
*signaller
;
1820 ring
->hangcheck
.deadlock
= true;
1822 signaller
= semaphore_waits_for(ring
, &seqno
);
1823 if (signaller
== NULL
|| signaller
->hangcheck
.deadlock
)
1826 /* cursory check for an unkickable deadlock */
1827 ctl
= I915_READ_CTL(signaller
);
1828 if (ctl
& RING_WAIT_SEMAPHORE
&& semaphore_passed(signaller
) < 0)
1831 return i915_seqno_passed(signaller
->get_seqno(signaller
, false), seqno
);
1834 static void semaphore_clear_deadlocks(struct drm_i915_private
*dev_priv
)
1836 struct intel_ring_buffer
*ring
;
1839 for_each_ring(ring
, dev_priv
, i
)
1840 ring
->hangcheck
.deadlock
= false;
1843 static enum intel_ring_hangcheck_action
1844 ring_stuck(struct intel_ring_buffer
*ring
, u32 acthd
)
1846 struct drm_device
*dev
= ring
->dev
;
1847 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1850 if (ring
->hangcheck
.acthd
!= acthd
)
1856 /* Is the chip hanging on a WAIT_FOR_EVENT?
1857 * If so we can simply poke the RB_WAIT bit
1858 * and break the hang. This should work on
1859 * all but the second generation chipsets.
1861 tmp
= I915_READ_CTL(ring
);
1862 if (tmp
& RING_WAIT
) {
1863 DRM_ERROR("Kicking stuck wait on %s\n",
1865 I915_WRITE_CTL(ring
, tmp
);
1869 if (INTEL_INFO(dev
)->gen
>= 6 && tmp
& RING_WAIT_SEMAPHORE
) {
1870 switch (semaphore_passed(ring
)) {
1874 DRM_ERROR("Kicking stuck semaphore on %s\n",
1876 I915_WRITE_CTL(ring
, tmp
);
1887 * This is called when the chip hasn't reported back with completed
1888 * batchbuffers in a long time. We keep track per ring seqno progress and
1889 * if there are no progress, hangcheck score for that ring is increased.
1890 * Further, acthd is inspected to see if the ring is stuck. On stuck case
1891 * we kick the ring. If we see no progress on three subsequent calls
1892 * we assume chip is wedged and try to fix it by resetting the chip.
1894 void i915_hangcheck_elapsed(unsigned long data
)
1896 struct drm_device
*dev
= (struct drm_device
*)data
;
1897 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1898 struct intel_ring_buffer
*ring
;
1900 int busy_count
= 0, rings_hung
= 0;
1901 bool stuck
[I915_NUM_RINGS
] = { 0 };
1907 if (!i915_enable_hangcheck
)
1910 for_each_ring(ring
, dev_priv
, i
) {
1914 semaphore_clear_deadlocks(dev_priv
);
1916 seqno
= ring
->get_seqno(ring
, false);
1917 acthd
= intel_ring_get_active_head(ring
);
1919 if (ring
->hangcheck
.seqno
== seqno
) {
1920 if (ring_idle(ring
, seqno
)) {
1921 if (waitqueue_active(&ring
->irq_queue
)) {
1922 /* Issue a wake-up to catch stuck h/w. */
1923 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1925 wake_up_all(&ring
->irq_queue
);
1926 ring
->hangcheck
.score
+= HUNG
;
1932 /* We always increment the hangcheck score
1933 * if the ring is busy and still processing
1934 * the same request, so that no single request
1935 * can run indefinitely (such as a chain of
1936 * batches). The only time we do not increment
1937 * the hangcheck score on this ring, if this
1938 * ring is in a legitimate wait for another
1939 * ring. In that case the waiting ring is a
1940 * victim and we want to be sure we catch the
1941 * right culprit. Then every time we do kick
1942 * the ring, add a small increment to the
1943 * score so that we can catch a batch that is
1944 * being repeatedly kicked and so responsible
1945 * for stalling the machine.
1947 ring
->hangcheck
.action
= ring_stuck(ring
,
1950 switch (ring
->hangcheck
.action
) {
1965 ring
->hangcheck
.score
+= score
;
1968 /* Gradually reduce the count so that we catch DoS
1969 * attempts across multiple batches.
1971 if (ring
->hangcheck
.score
> 0)
1972 ring
->hangcheck
.score
--;
1975 ring
->hangcheck
.seqno
= seqno
;
1976 ring
->hangcheck
.acthd
= acthd
;
1980 for_each_ring(ring
, dev_priv
, i
) {
1981 if (ring
->hangcheck
.score
> FIRE
) {
1982 DRM_ERROR("%s on %s\n",
1983 stuck
[i
] ? "stuck" : "no progress",
1990 return i915_handle_error(dev
, true);
1993 /* Reset timer case chip hangs without another request
1995 i915_queue_hangcheck(dev
);
1998 void i915_queue_hangcheck(struct drm_device
*dev
)
2000 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2001 if (!i915_enable_hangcheck
)
2004 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
2005 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
2008 static void ibx_irq_preinstall(struct drm_device
*dev
)
2010 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2012 if (HAS_PCH_NOP(dev
))
2015 /* south display irq */
2016 I915_WRITE(SDEIMR
, 0xffffffff);
2018 * SDEIER is also touched by the interrupt handler to work around missed
2019 * PCH interrupts. Hence we can't update it after the interrupt handler
2020 * is enabled - instead we unconditionally enable all PCH interrupt
2021 * sources here, but then only unmask them as needed with SDEIMR.
2023 I915_WRITE(SDEIER
, 0xffffffff);
2024 POSTING_READ(SDEIER
);
2027 static void gen5_gt_irq_preinstall(struct drm_device
*dev
)
2029 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2032 I915_WRITE(GTIMR
, 0xffffffff);
2033 I915_WRITE(GTIER
, 0x0);
2034 POSTING_READ(GTIER
);
2036 if (INTEL_INFO(dev
)->gen
>= 6) {
2038 I915_WRITE(GEN6_PMIMR
, 0xffffffff);
2039 I915_WRITE(GEN6_PMIER
, 0x0);
2040 POSTING_READ(GEN6_PMIER
);
2046 static void ironlake_irq_preinstall(struct drm_device
*dev
)
2048 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2050 atomic_set(&dev_priv
->irq_received
, 0);
2052 I915_WRITE(HWSTAM
, 0xeffe);
2054 I915_WRITE(DEIMR
, 0xffffffff);
2055 I915_WRITE(DEIER
, 0x0);
2056 POSTING_READ(DEIER
);
2058 gen5_gt_irq_preinstall(dev
);
2060 ibx_irq_preinstall(dev
);
2063 static void valleyview_irq_preinstall(struct drm_device
*dev
)
2065 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2068 atomic_set(&dev_priv
->irq_received
, 0);
2071 I915_WRITE(VLV_IMR
, 0);
2072 I915_WRITE(RING_IMR(RENDER_RING_BASE
), 0);
2073 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE
), 0);
2074 I915_WRITE(RING_IMR(BLT_RING_BASE
), 0);
2077 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2078 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2080 gen5_gt_irq_preinstall(dev
);
2082 I915_WRITE(DPINVGTT
, 0xff);
2084 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2085 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2087 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2088 I915_WRITE(VLV_IIR
, 0xffffffff);
2089 I915_WRITE(VLV_IMR
, 0xffffffff);
2090 I915_WRITE(VLV_IER
, 0x0);
2091 POSTING_READ(VLV_IER
);
2094 static void ibx_hpd_irq_setup(struct drm_device
*dev
)
2096 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2097 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2098 struct intel_encoder
*intel_encoder
;
2099 u32 hotplug_irqs
, hotplug
, enabled_irqs
= 0;
2101 if (HAS_PCH_IBX(dev
)) {
2102 hotplug_irqs
= SDE_HOTPLUG_MASK
;
2103 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2104 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2105 enabled_irqs
|= hpd_ibx
[intel_encoder
->hpd_pin
];
2107 hotplug_irqs
= SDE_HOTPLUG_MASK_CPT
;
2108 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2109 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2110 enabled_irqs
|= hpd_cpt
[intel_encoder
->hpd_pin
];
2113 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
2116 * Enable digital hotplug on the PCH, and configure the DP short pulse
2117 * duration to 2ms (which is the minimum in the Display Port spec)
2119 * This register is the same on all known PCH chips.
2121 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
2122 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
2123 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
2124 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
2125 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
2126 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
2129 static void ibx_irq_postinstall(struct drm_device
*dev
)
2131 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2134 if (HAS_PCH_NOP(dev
))
2137 if (HAS_PCH_IBX(dev
)) {
2138 mask
= SDE_GMBUS
| SDE_AUX_MASK
| SDE_TRANSB_FIFO_UNDER
|
2139 SDE_TRANSA_FIFO_UNDER
| SDE_POISON
;
2141 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
| SDE_ERROR_CPT
;
2143 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2146 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2147 I915_WRITE(SDEIMR
, ~mask
);
2150 static void gen5_gt_irq_postinstall(struct drm_device
*dev
)
2152 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2153 u32 pm_irqs
, gt_irqs
;
2155 pm_irqs
= gt_irqs
= 0;
2157 dev_priv
->gt_irq_mask
= ~0;
2158 if (HAS_L3_GPU_CACHE(dev
)) {
2159 /* L3 parity interrupt is always unmasked. */
2160 dev_priv
->gt_irq_mask
= ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
2161 gt_irqs
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
2164 gt_irqs
|= GT_RENDER_USER_INTERRUPT
;
2166 gt_irqs
|= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
|
2167 ILK_BSD_USER_INTERRUPT
;
2169 gt_irqs
|= GT_BLT_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
;
2172 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2173 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
2174 I915_WRITE(GTIER
, gt_irqs
);
2175 POSTING_READ(GTIER
);
2177 if (INTEL_INFO(dev
)->gen
>= 6) {
2178 pm_irqs
|= GEN6_PM_RPS_EVENTS
;
2181 pm_irqs
|= PM_VEBOX_USER_INTERRUPT
;
2183 I915_WRITE(GEN6_PMIIR
, I915_READ(GEN6_PMIIR
));
2184 I915_WRITE(GEN6_PMIMR
, 0xffffffff);
2185 I915_WRITE(GEN6_PMIER
, pm_irqs
);
2186 POSTING_READ(GEN6_PMIER
);
2190 static int ironlake_irq_postinstall(struct drm_device
*dev
)
2192 unsigned long irqflags
;
2194 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2195 /* enable kind of interrupts always enabled */
2196 u32 display_mask
= DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
2197 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
|
2198 DE_AUX_CHANNEL_A
| DE_PIPEB_FIFO_UNDERRUN
|
2199 DE_PIPEA_FIFO_UNDERRUN
| DE_POISON
;
2201 dev_priv
->irq_mask
= ~display_mask
;
2203 /* should always can generate irq */
2204 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2205 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
2206 I915_WRITE(DEIER
, display_mask
|
2207 DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
| DE_PCU_EVENT
);
2208 POSTING_READ(DEIER
);
2210 gen5_gt_irq_postinstall(dev
);
2212 ibx_irq_postinstall(dev
);
2214 if (IS_IRONLAKE_M(dev
)) {
2215 /* Enable PCU event interrupts
2217 * spinlocking not required here for correctness since interrupt
2218 * setup is guaranteed to run in single-threaded context. But we
2219 * need it to make the assert_spin_locked happy. */
2220 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2221 ironlake_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
2222 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2228 static int ivybridge_irq_postinstall(struct drm_device
*dev
)
2230 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2231 /* enable kind of interrupts always enabled */
2233 DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
| DE_PCH_EVENT_IVB
|
2234 DE_PLANEC_FLIP_DONE_IVB
|
2235 DE_PLANEB_FLIP_DONE_IVB
|
2236 DE_PLANEA_FLIP_DONE_IVB
|
2237 DE_AUX_CHANNEL_A_IVB
|
2240 dev_priv
->irq_mask
= ~display_mask
;
2242 /* should always can generate irq */
2243 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2244 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2245 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
2248 DE_PIPEC_VBLANK_IVB
|
2249 DE_PIPEB_VBLANK_IVB
|
2250 DE_PIPEA_VBLANK_IVB
);
2251 POSTING_READ(DEIER
);
2253 gen5_gt_irq_postinstall(dev
);
2255 ibx_irq_postinstall(dev
);
2260 static int valleyview_irq_postinstall(struct drm_device
*dev
)
2262 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2264 u32 pipestat_enable
= PLANE_FLIP_DONE_INT_EN_VLV
;
2265 unsigned long irqflags
;
2267 enable_mask
= I915_DISPLAY_PORT_INTERRUPT
;
2268 enable_mask
|= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2269 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2270 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2271 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2274 *Leave vblank interrupts masked initially. enable/disable will
2275 * toggle them based on usage.
2277 dev_priv
->irq_mask
= (~enable_mask
) |
2278 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2279 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2281 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2282 POSTING_READ(PORT_HOTPLUG_EN
);
2284 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
2285 I915_WRITE(VLV_IER
, enable_mask
);
2286 I915_WRITE(VLV_IIR
, 0xffffffff);
2287 I915_WRITE(PIPESTAT(0), 0xffff);
2288 I915_WRITE(PIPESTAT(1), 0xffff);
2289 POSTING_READ(VLV_IER
);
2291 /* Interrupt setup is already guaranteed to be single-threaded, this is
2292 * just to make the assert_spin_locked check happy. */
2293 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2294 i915_enable_pipestat(dev_priv
, 0, pipestat_enable
);
2295 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
2296 i915_enable_pipestat(dev_priv
, 1, pipestat_enable
);
2297 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2299 I915_WRITE(VLV_IIR
, 0xffffffff);
2300 I915_WRITE(VLV_IIR
, 0xffffffff);
2302 gen5_gt_irq_postinstall(dev
);
2304 /* ack & enable invalid PTE error interrupts */
2305 #if 0 /* FIXME: add support to irq handler for checking these bits */
2306 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
2307 I915_WRITE(DPINVGTT
, DPINVGTT_EN_MASK
);
2310 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
2315 static void valleyview_irq_uninstall(struct drm_device
*dev
)
2317 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2323 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2326 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2328 I915_WRITE(HWSTAM
, 0xffffffff);
2329 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2330 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2332 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2333 I915_WRITE(VLV_IIR
, 0xffffffff);
2334 I915_WRITE(VLV_IMR
, 0xffffffff);
2335 I915_WRITE(VLV_IER
, 0x0);
2336 POSTING_READ(VLV_IER
);
2339 static void ironlake_irq_uninstall(struct drm_device
*dev
)
2341 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2346 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2348 I915_WRITE(HWSTAM
, 0xffffffff);
2350 I915_WRITE(DEIMR
, 0xffffffff);
2351 I915_WRITE(DEIER
, 0x0);
2352 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2354 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2356 I915_WRITE(GTIMR
, 0xffffffff);
2357 I915_WRITE(GTIER
, 0x0);
2358 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2360 if (HAS_PCH_NOP(dev
))
2363 I915_WRITE(SDEIMR
, 0xffffffff);
2364 I915_WRITE(SDEIER
, 0x0);
2365 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2366 if (HAS_PCH_CPT(dev
) || HAS_PCH_LPT(dev
))
2367 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2370 static void i8xx_irq_preinstall(struct drm_device
* dev
)
2372 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2375 atomic_set(&dev_priv
->irq_received
, 0);
2378 I915_WRITE(PIPESTAT(pipe
), 0);
2379 I915_WRITE16(IMR
, 0xffff);
2380 I915_WRITE16(IER
, 0x0);
2381 POSTING_READ16(IER
);
2384 static int i8xx_irq_postinstall(struct drm_device
*dev
)
2386 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2389 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2391 /* Unmask the interrupts that we always want on. */
2392 dev_priv
->irq_mask
=
2393 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2394 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2395 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2396 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2397 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2398 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
2401 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2402 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2403 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2404 I915_USER_INTERRUPT
);
2405 POSTING_READ16(IER
);
2411 * Returns true when a page flip has completed.
2413 static bool i8xx_handle_vblank(struct drm_device
*dev
,
2416 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2417 u16 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(pipe
);
2419 if (!drm_handle_vblank(dev
, pipe
))
2422 if ((iir
& flip_pending
) == 0)
2425 intel_prepare_page_flip(dev
, pipe
);
2427 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2428 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2429 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2430 * the flip is completed (no longer pending). Since this doesn't raise
2431 * an interrupt per se, we watch for the change at vblank.
2433 if (I915_READ16(ISR
) & flip_pending
)
2436 intel_finish_page_flip(dev
, pipe
);
2441 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
2443 struct drm_device
*dev
= (struct drm_device
*) arg
;
2444 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2447 unsigned long irqflags
;
2451 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2452 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2454 atomic_inc(&dev_priv
->irq_received
);
2456 iir
= I915_READ16(IIR
);
2460 while (iir
& ~flip_mask
) {
2461 /* Can't rely on pipestat interrupt bit in iir as it might
2462 * have been cleared after the pipestat interrupt was received.
2463 * It doesn't set the bit in iir again, but it still produces
2464 * interrupts (for non-MSI).
2466 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2467 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2468 i915_handle_error(dev
, false);
2470 for_each_pipe(pipe
) {
2471 int reg
= PIPESTAT(pipe
);
2472 pipe_stats
[pipe
] = I915_READ(reg
);
2475 * Clear the PIPE*STAT regs before the IIR
2477 if (pipe_stats
[pipe
] & 0x8000ffff) {
2478 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2479 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2481 I915_WRITE(reg
, pipe_stats
[pipe
]);
2485 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2487 I915_WRITE16(IIR
, iir
& ~flip_mask
);
2488 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
2490 i915_update_dri1_breadcrumb(dev
);
2492 if (iir
& I915_USER_INTERRUPT
)
2493 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2495 if (pipe_stats
[0] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2496 i8xx_handle_vblank(dev
, 0, iir
))
2497 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(0);
2499 if (pipe_stats
[1] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2500 i8xx_handle_vblank(dev
, 1, iir
))
2501 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(1);
2509 static void i8xx_irq_uninstall(struct drm_device
* dev
)
2511 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2514 for_each_pipe(pipe
) {
2515 /* Clear enable bits; then clear status bits */
2516 I915_WRITE(PIPESTAT(pipe
), 0);
2517 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
2519 I915_WRITE16(IMR
, 0xffff);
2520 I915_WRITE16(IER
, 0x0);
2521 I915_WRITE16(IIR
, I915_READ16(IIR
));
2524 static void i915_irq_preinstall(struct drm_device
* dev
)
2526 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2529 atomic_set(&dev_priv
->irq_received
, 0);
2531 if (I915_HAS_HOTPLUG(dev
)) {
2532 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2533 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2536 I915_WRITE16(HWSTAM
, 0xeffe);
2538 I915_WRITE(PIPESTAT(pipe
), 0);
2539 I915_WRITE(IMR
, 0xffffffff);
2540 I915_WRITE(IER
, 0x0);
2544 static int i915_irq_postinstall(struct drm_device
*dev
)
2546 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2549 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2551 /* Unmask the interrupts that we always want on. */
2552 dev_priv
->irq_mask
=
2553 ~(I915_ASLE_INTERRUPT
|
2554 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2555 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2556 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2557 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2558 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2561 I915_ASLE_INTERRUPT
|
2562 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2563 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2564 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2565 I915_USER_INTERRUPT
;
2567 if (I915_HAS_HOTPLUG(dev
)) {
2568 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2569 POSTING_READ(PORT_HOTPLUG_EN
);
2571 /* Enable in IER... */
2572 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
2573 /* and unmask in IMR */
2574 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
2577 I915_WRITE(IMR
, dev_priv
->irq_mask
);
2578 I915_WRITE(IER
, enable_mask
);
2581 i915_enable_asle_pipestat(dev
);
2587 * Returns true when a page flip has completed.
2589 static bool i915_handle_vblank(struct drm_device
*dev
,
2590 int plane
, int pipe
, u32 iir
)
2592 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2593 u32 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
2595 if (!drm_handle_vblank(dev
, pipe
))
2598 if ((iir
& flip_pending
) == 0)
2601 intel_prepare_page_flip(dev
, plane
);
2603 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2604 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2605 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2606 * the flip is completed (no longer pending). Since this doesn't raise
2607 * an interrupt per se, we watch for the change at vblank.
2609 if (I915_READ(ISR
) & flip_pending
)
2612 intel_finish_page_flip(dev
, pipe
);
2617 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
2619 struct drm_device
*dev
= (struct drm_device
*) arg
;
2620 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2621 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
2622 unsigned long irqflags
;
2624 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2625 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2626 int pipe
, ret
= IRQ_NONE
;
2628 atomic_inc(&dev_priv
->irq_received
);
2630 iir
= I915_READ(IIR
);
2632 bool irq_received
= (iir
& ~flip_mask
) != 0;
2633 bool blc_event
= false;
2635 /* Can't rely on pipestat interrupt bit in iir as it might
2636 * have been cleared after the pipestat interrupt was received.
2637 * It doesn't set the bit in iir again, but it still produces
2638 * interrupts (for non-MSI).
2640 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2641 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2642 i915_handle_error(dev
, false);
2644 for_each_pipe(pipe
) {
2645 int reg
= PIPESTAT(pipe
);
2646 pipe_stats
[pipe
] = I915_READ(reg
);
2648 /* Clear the PIPE*STAT regs before the IIR */
2649 if (pipe_stats
[pipe
] & 0x8000ffff) {
2650 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2651 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2653 I915_WRITE(reg
, pipe_stats
[pipe
]);
2654 irq_received
= true;
2657 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2662 /* Consume port. Then clear IIR or we'll miss events */
2663 if ((I915_HAS_HOTPLUG(dev
)) &&
2664 (iir
& I915_DISPLAY_PORT_INTERRUPT
)) {
2665 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
2666 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
2668 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2671 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
2673 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
2674 POSTING_READ(PORT_HOTPLUG_STAT
);
2677 I915_WRITE(IIR
, iir
& ~flip_mask
);
2678 new_iir
= I915_READ(IIR
); /* Flush posted writes */
2680 if (iir
& I915_USER_INTERRUPT
)
2681 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2683 for_each_pipe(pipe
) {
2688 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2689 i915_handle_vblank(dev
, plane
, pipe
, iir
))
2690 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
2692 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
2696 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
2697 intel_opregion_asle_intr(dev
);
2699 /* With MSI, interrupts are only generated when iir
2700 * transitions from zero to nonzero. If another bit got
2701 * set while we were handling the existing iir bits, then
2702 * we would never get another interrupt.
2704 * This is fine on non-MSI as well, as if we hit this path
2705 * we avoid exiting the interrupt handler only to generate
2708 * Note that for MSI this could cause a stray interrupt report
2709 * if an interrupt landed in the time between writing IIR and
2710 * the posting read. This should be rare enough to never
2711 * trigger the 99% of 100,000 interrupts test for disabling
2716 } while (iir
& ~flip_mask
);
2718 i915_update_dri1_breadcrumb(dev
);
2723 static void i915_irq_uninstall(struct drm_device
* dev
)
2725 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2728 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2730 if (I915_HAS_HOTPLUG(dev
)) {
2731 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2732 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2735 I915_WRITE16(HWSTAM
, 0xffff);
2736 for_each_pipe(pipe
) {
2737 /* Clear enable bits; then clear status bits */
2738 I915_WRITE(PIPESTAT(pipe
), 0);
2739 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
2741 I915_WRITE(IMR
, 0xffffffff);
2742 I915_WRITE(IER
, 0x0);
2744 I915_WRITE(IIR
, I915_READ(IIR
));
2747 static void i965_irq_preinstall(struct drm_device
* dev
)
2749 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2752 atomic_set(&dev_priv
->irq_received
, 0);
2754 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2755 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2757 I915_WRITE(HWSTAM
, 0xeffe);
2759 I915_WRITE(PIPESTAT(pipe
), 0);
2760 I915_WRITE(IMR
, 0xffffffff);
2761 I915_WRITE(IER
, 0x0);
2765 static int i965_irq_postinstall(struct drm_device
*dev
)
2767 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2770 unsigned long irqflags
;
2772 /* Unmask the interrupts that we always want on. */
2773 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
2774 I915_DISPLAY_PORT_INTERRUPT
|
2775 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2776 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2777 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2778 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2779 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2781 enable_mask
= ~dev_priv
->irq_mask
;
2782 enable_mask
&= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2783 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
2784 enable_mask
|= I915_USER_INTERRUPT
;
2787 enable_mask
|= I915_BSD_USER_INTERRUPT
;
2789 /* Interrupt setup is already guaranteed to be single-threaded, this is
2790 * just to make the assert_spin_locked check happy. */
2791 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2792 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
2793 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2796 * Enable some error detection, note the instruction error mask
2797 * bit is reserved, so we leave it masked.
2800 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
2801 GM45_ERROR_MEM_PRIV
|
2802 GM45_ERROR_CP_PRIV
|
2803 I915_ERROR_MEMORY_REFRESH
);
2805 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
2806 I915_ERROR_MEMORY_REFRESH
);
2808 I915_WRITE(EMR
, error_mask
);
2810 I915_WRITE(IMR
, dev_priv
->irq_mask
);
2811 I915_WRITE(IER
, enable_mask
);
2814 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2815 POSTING_READ(PORT_HOTPLUG_EN
);
2817 i915_enable_asle_pipestat(dev
);
2822 static void i915_hpd_irq_setup(struct drm_device
*dev
)
2824 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2825 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2826 struct intel_encoder
*intel_encoder
;
2829 assert_spin_locked(&dev_priv
->irq_lock
);
2831 if (I915_HAS_HOTPLUG(dev
)) {
2832 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
2833 hotplug_en
&= ~HOTPLUG_INT_EN_MASK
;
2834 /* Note HDMI and DP share hotplug bits */
2835 /* enable bits are the same for all generations */
2836 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2837 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2838 hotplug_en
|= hpd_mask_i915
[intel_encoder
->hpd_pin
];
2839 /* Programming the CRT detection parameters tends
2840 to generate a spurious hotplug event about three
2841 seconds later. So just do it once.
2844 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
2845 hotplug_en
&= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK
;
2846 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
2848 /* Ignore TV since it's buggy */
2849 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
2853 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
2855 struct drm_device
*dev
= (struct drm_device
*) arg
;
2856 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2858 u32 pipe_stats
[I915_MAX_PIPES
];
2859 unsigned long irqflags
;
2861 int ret
= IRQ_NONE
, pipe
;
2863 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2864 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2866 atomic_inc(&dev_priv
->irq_received
);
2868 iir
= I915_READ(IIR
);
2871 bool blc_event
= false;
2873 irq_received
= (iir
& ~flip_mask
) != 0;
2875 /* Can't rely on pipestat interrupt bit in iir as it might
2876 * have been cleared after the pipestat interrupt was received.
2877 * It doesn't set the bit in iir again, but it still produces
2878 * interrupts (for non-MSI).
2880 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2881 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2882 i915_handle_error(dev
, false);
2884 for_each_pipe(pipe
) {
2885 int reg
= PIPESTAT(pipe
);
2886 pipe_stats
[pipe
] = I915_READ(reg
);
2889 * Clear the PIPE*STAT regs before the IIR
2891 if (pipe_stats
[pipe
] & 0x8000ffff) {
2892 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2893 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2895 I915_WRITE(reg
, pipe_stats
[pipe
]);
2899 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2906 /* Consume port. Then clear IIR or we'll miss events */
2907 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
2908 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
2909 u32 hotplug_trigger
= hotplug_status
& (IS_G4X(dev
) ?
2910 HOTPLUG_INT_STATUS_G4X
:
2911 HOTPLUG_INT_STATUS_I915
);
2913 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2916 intel_hpd_irq_handler(dev
, hotplug_trigger
,
2917 IS_G4X(dev
) ? hpd_status_gen4
: hpd_status_i915
);
2919 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
2920 I915_READ(PORT_HOTPLUG_STAT
);
2923 I915_WRITE(IIR
, iir
& ~flip_mask
);
2924 new_iir
= I915_READ(IIR
); /* Flush posted writes */
2926 if (iir
& I915_USER_INTERRUPT
)
2927 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2928 if (iir
& I915_BSD_USER_INTERRUPT
)
2929 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
2931 for_each_pipe(pipe
) {
2932 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
2933 i915_handle_vblank(dev
, pipe
, pipe
, iir
))
2934 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
2936 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
2941 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
2942 intel_opregion_asle_intr(dev
);
2944 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
2945 gmbus_irq_handler(dev
);
2947 /* With MSI, interrupts are only generated when iir
2948 * transitions from zero to nonzero. If another bit got
2949 * set while we were handling the existing iir bits, then
2950 * we would never get another interrupt.
2952 * This is fine on non-MSI as well, as if we hit this path
2953 * we avoid exiting the interrupt handler only to generate
2956 * Note that for MSI this could cause a stray interrupt report
2957 * if an interrupt landed in the time between writing IIR and
2958 * the posting read. This should be rare enough to never
2959 * trigger the 99% of 100,000 interrupts test for disabling
2965 i915_update_dri1_breadcrumb(dev
);
2970 static void i965_irq_uninstall(struct drm_device
* dev
)
2972 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2978 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2980 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2981 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2983 I915_WRITE(HWSTAM
, 0xffffffff);
2985 I915_WRITE(PIPESTAT(pipe
), 0);
2986 I915_WRITE(IMR
, 0xffffffff);
2987 I915_WRITE(IER
, 0x0);
2990 I915_WRITE(PIPESTAT(pipe
),
2991 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
2992 I915_WRITE(IIR
, I915_READ(IIR
));
2995 static void i915_reenable_hotplug_timer_func(unsigned long data
)
2997 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*)data
;
2998 struct drm_device
*dev
= dev_priv
->dev
;
2999 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3000 unsigned long irqflags
;
3003 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3004 for (i
= (HPD_NONE
+ 1); i
< HPD_NUM_PINS
; i
++) {
3005 struct drm_connector
*connector
;
3007 if (dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_DISABLED
)
3010 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3012 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3013 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3015 if (intel_connector
->encoder
->hpd_pin
== i
) {
3016 if (connector
->polled
!= intel_connector
->polled
)
3017 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3018 drm_get_connector_name(connector
));
3019 connector
->polled
= intel_connector
->polled
;
3020 if (!connector
->polled
)
3021 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3025 if (dev_priv
->display
.hpd_irq_setup
)
3026 dev_priv
->display
.hpd_irq_setup(dev
);
3027 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3030 void intel_irq_init(struct drm_device
*dev
)
3032 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3034 INIT_WORK(&dev_priv
->hotplug_work
, i915_hotplug_work_func
);
3035 INIT_WORK(&dev_priv
->gpu_error
.work
, i915_error_work_func
);
3036 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
3037 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
3039 setup_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
3040 i915_hangcheck_elapsed
,
3041 (unsigned long) dev
);
3042 setup_timer(&dev_priv
->hotplug_reenable_timer
, i915_reenable_hotplug_timer_func
,
3043 (unsigned long) dev_priv
);
3045 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
, PM_QOS_DEFAULT_VALUE
);
3047 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
3048 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
3049 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
3050 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
3051 dev
->driver
->get_vblank_counter
= gm45_get_vblank_counter
;
3054 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3055 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
3057 dev
->driver
->get_vblank_timestamp
= NULL
;
3058 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
3060 if (IS_VALLEYVIEW(dev
)) {
3061 dev
->driver
->irq_handler
= valleyview_irq_handler
;
3062 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
3063 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
3064 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
3065 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
3066 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
3067 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3068 } else if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
3069 /* Share uninstall handlers with ILK/SNB */
3070 dev
->driver
->irq_handler
= ironlake_irq_handler
;
3071 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
3072 dev
->driver
->irq_postinstall
= ivybridge_irq_postinstall
;
3073 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
3074 dev
->driver
->enable_vblank
= ivybridge_enable_vblank
;
3075 dev
->driver
->disable_vblank
= ivybridge_disable_vblank
;
3076 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
3077 } else if (HAS_PCH_SPLIT(dev
)) {
3078 dev
->driver
->irq_handler
= ironlake_irq_handler
;
3079 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
3080 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
3081 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
3082 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
3083 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
3084 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
3086 if (INTEL_INFO(dev
)->gen
== 2) {
3087 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
3088 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
3089 dev
->driver
->irq_handler
= i8xx_irq_handler
;
3090 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
3091 } else if (INTEL_INFO(dev
)->gen
== 3) {
3092 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
3093 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
3094 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
3095 dev
->driver
->irq_handler
= i915_irq_handler
;
3096 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3098 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
3099 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
3100 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
3101 dev
->driver
->irq_handler
= i965_irq_handler
;
3102 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3104 dev
->driver
->enable_vblank
= i915_enable_vblank
;
3105 dev
->driver
->disable_vblank
= i915_disable_vblank
;
3109 void intel_hpd_init(struct drm_device
*dev
)
3111 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3112 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3113 struct drm_connector
*connector
;
3114 unsigned long irqflags
;
3117 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
3118 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
3119 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3121 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3122 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3123 connector
->polled
= intel_connector
->polled
;
3124 if (!connector
->polled
&& I915_HAS_HOTPLUG(dev
) && intel_connector
->encoder
->hpd_pin
> HPD_NONE
)
3125 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3128 /* Interrupt setup is already guaranteed to be single-threaded, this is
3129 * just to make the assert_spin_locked checks happy. */
3130 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3131 if (dev_priv
->display
.hpd_irq_setup
)
3132 dev_priv
->display
.hpd_irq_setup(dev
);
3133 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);