1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #define MAX_NOPID ((u32)~0)
36 /** These are the interrupts used by the driver */
37 #define I915_INTERRUPT_ENABLE_MASK (I915_USER_INTERRUPT | \
38 I915_ASLE_INTERRUPT | \
39 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
40 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
43 i915_enable_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
45 if ((dev_priv
->irq_mask_reg
& mask
) != 0) {
46 dev_priv
->irq_mask_reg
&= ~mask
;
47 I915_WRITE(IMR
, dev_priv
->irq_mask_reg
);
48 (void) I915_READ(IMR
);
53 i915_disable_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
55 if ((dev_priv
->irq_mask_reg
& mask
) != mask
) {
56 dev_priv
->irq_mask_reg
|= mask
;
57 I915_WRITE(IMR
, dev_priv
->irq_mask_reg
);
58 (void) I915_READ(IMR
);
63 * i915_pipe_enabled - check if a pipe is enabled
65 * @pipe: pipe to check
67 * Reading certain registers when the pipe is disabled can hang the chip.
68 * Use this routine to make sure the PLL is running and the pipe is active
69 * before reading such registers if unsure.
72 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
74 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
75 unsigned long pipeconf
= pipe
? PIPEBCONF
: PIPEACONF
;
77 if (I915_READ(pipeconf
) & PIPEACONF_ENABLE
)
83 /* Called from drm generic code, passed a 'crtc', which
84 * we use as a pipe index
86 u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
88 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
89 unsigned long high_frame
;
90 unsigned long low_frame
;
91 u32 high1
, high2
, low
, count
;
93 high_frame
= pipe
? PIPEBFRAMEHIGH
: PIPEAFRAMEHIGH
;
94 low_frame
= pipe
? PIPEBFRAMEPIXEL
: PIPEAFRAMEPIXEL
;
96 if (!i915_pipe_enabled(dev
, pipe
)) {
97 DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe
);
102 * High & low register fields aren't synchronized, so make sure
103 * we get a low value that's stable across two reads of the high
107 high1
= ((I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
) >>
108 PIPE_FRAME_HIGH_SHIFT
);
109 low
= ((I915_READ(low_frame
) & PIPE_FRAME_LOW_MASK
) >>
110 PIPE_FRAME_LOW_SHIFT
);
111 high2
= ((I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
) >>
112 PIPE_FRAME_HIGH_SHIFT
);
113 } while (high1
!= high2
);
115 count
= (high1
<< 8) | low
;
120 irqreturn_t
i915_driver_irq_handler(DRM_IRQ_ARGS
)
122 struct drm_device
*dev
= (struct drm_device
*) arg
;
123 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
125 u32 pipea_stats
, pipeb_stats
;
128 atomic_inc(&dev_priv
->irq_received
);
130 if (dev
->pdev
->msi_enabled
)
132 iir
= I915_READ(IIR
);
135 if (dev
->pdev
->msi_enabled
) {
136 I915_WRITE(IMR
, dev_priv
->irq_mask_reg
);
137 (void) I915_READ(IMR
);
143 * Clear the PIPE(A|B)STAT regs before the IIR otherwise
144 * we may get extra interrupts.
146 if (iir
& I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
) {
147 pipea_stats
= I915_READ(PIPEASTAT
);
148 if (!(dev_priv
->vblank_pipe
& DRM_I915_VBLANK_PIPE_A
))
149 pipea_stats
&= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE
|
150 PIPE_VBLANK_INTERRUPT_ENABLE
);
151 else if (pipea_stats
& (PIPE_START_VBLANK_INTERRUPT_STATUS
|
152 PIPE_VBLANK_INTERRUPT_STATUS
)) {
154 drm_handle_vblank(dev
, 0);
157 I915_WRITE(PIPEASTAT
, pipea_stats
);
159 if (iir
& I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
) {
160 pipeb_stats
= I915_READ(PIPEBSTAT
);
162 I915_WRITE(PIPEBSTAT
, pipeb_stats
);
164 /* The vblank interrupt gets enabled even if we didn't ask for
165 it, so make sure it's shut down again */
166 if (!(dev_priv
->vblank_pipe
& DRM_I915_VBLANK_PIPE_B
))
167 pipeb_stats
&= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE
|
168 PIPE_VBLANK_INTERRUPT_ENABLE
);
169 else if (pipeb_stats
& (PIPE_START_VBLANK_INTERRUPT_STATUS
|
170 PIPE_VBLANK_INTERRUPT_STATUS
)) {
172 drm_handle_vblank(dev
, 1);
175 if (pipeb_stats
& I915_LEGACY_BLC_EVENT_STATUS
)
176 opregion_asle_intr(dev
);
177 I915_WRITE(PIPEBSTAT
, pipeb_stats
);
180 I915_WRITE(IIR
, iir
);
181 if (dev
->pdev
->msi_enabled
)
182 I915_WRITE(IMR
, dev_priv
->irq_mask_reg
);
183 (void) I915_READ(IIR
); /* Flush posted writes */
185 if (dev_priv
->sarea_priv
)
186 dev_priv
->sarea_priv
->last_dispatch
=
187 READ_BREADCRUMB(dev_priv
);
189 if (iir
& I915_USER_INTERRUPT
) {
190 dev_priv
->mm
.irq_gem_seqno
= i915_get_gem_seqno(dev
);
191 DRM_WAKEUP(&dev_priv
->irq_queue
);
194 if (iir
& I915_ASLE_INTERRUPT
)
195 opregion_asle_intr(dev
);
200 static int i915_emit_irq(struct drm_device
* dev
)
202 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
205 i915_kernel_lost_context(dev
);
210 if (dev_priv
->counter
> 0x7FFFFFFFUL
)
211 dev_priv
->counter
= 1;
212 if (dev_priv
->sarea_priv
)
213 dev_priv
->sarea_priv
->last_enqueue
= dev_priv
->counter
;
216 OUT_RING(MI_STORE_DWORD_INDEX
);
217 OUT_RING(I915_BREADCRUMB_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
218 OUT_RING(dev_priv
->counter
);
219 OUT_RING(MI_USER_INTERRUPT
);
222 return dev_priv
->counter
;
225 void i915_user_irq_get(struct drm_device
*dev
)
227 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
228 unsigned long irqflags
;
230 spin_lock_irqsave(&dev_priv
->user_irq_lock
, irqflags
);
231 if (dev
->irq_enabled
&& (++dev_priv
->user_irq_refcount
== 1))
232 i915_enable_irq(dev_priv
, I915_USER_INTERRUPT
);
233 spin_unlock_irqrestore(&dev_priv
->user_irq_lock
, irqflags
);
236 void i915_user_irq_put(struct drm_device
*dev
)
238 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
239 unsigned long irqflags
;
241 spin_lock_irqsave(&dev_priv
->user_irq_lock
, irqflags
);
242 BUG_ON(dev
->irq_enabled
&& dev_priv
->user_irq_refcount
<= 0);
243 if (dev
->irq_enabled
&& (--dev_priv
->user_irq_refcount
== 0))
244 i915_disable_irq(dev_priv
, I915_USER_INTERRUPT
);
245 spin_unlock_irqrestore(&dev_priv
->user_irq_lock
, irqflags
);
248 static int i915_wait_irq(struct drm_device
* dev
, int irq_nr
)
250 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
253 DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr
,
254 READ_BREADCRUMB(dev_priv
));
256 if (READ_BREADCRUMB(dev_priv
) >= irq_nr
) {
257 if (dev_priv
->sarea_priv
) {
258 dev_priv
->sarea_priv
->last_dispatch
=
259 READ_BREADCRUMB(dev_priv
);
264 if (dev_priv
->sarea_priv
)
265 dev_priv
->sarea_priv
->perf_boxes
|= I915_BOX_WAIT
;
267 i915_user_irq_get(dev
);
268 DRM_WAIT_ON(ret
, dev_priv
->irq_queue
, 3 * DRM_HZ
,
269 READ_BREADCRUMB(dev_priv
) >= irq_nr
);
270 i915_user_irq_put(dev
);
273 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
274 READ_BREADCRUMB(dev_priv
), (int)dev_priv
->counter
);
277 if (dev_priv
->sarea_priv
)
278 dev_priv
->sarea_priv
->last_dispatch
=
279 READ_BREADCRUMB(dev_priv
);
284 /* Needs the lock as it touches the ring.
286 int i915_irq_emit(struct drm_device
*dev
, void *data
,
287 struct drm_file
*file_priv
)
289 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
290 drm_i915_irq_emit_t
*emit
= data
;
293 RING_LOCK_TEST_WITH_RETURN(dev
, file_priv
);
296 DRM_ERROR("called with no initialization\n");
299 mutex_lock(&dev
->struct_mutex
);
300 result
= i915_emit_irq(dev
);
301 mutex_unlock(&dev
->struct_mutex
);
303 if (DRM_COPY_TO_USER(emit
->irq_seq
, &result
, sizeof(int))) {
304 DRM_ERROR("copy_to_user\n");
311 /* Doesn't need the hardware lock.
313 int i915_irq_wait(struct drm_device
*dev
, void *data
,
314 struct drm_file
*file_priv
)
316 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
317 drm_i915_irq_wait_t
*irqwait
= data
;
320 DRM_ERROR("called with no initialization\n");
324 return i915_wait_irq(dev
, irqwait
->irq_seq
);
327 /* Called from drm generic code, passed 'crtc' which
328 * we use as a pipe index
330 int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
332 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
333 u32 pipestat_reg
= 0;
336 unsigned long irqflags
;
340 pipestat_reg
= PIPEASTAT
;
341 interrupt
= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
;
344 pipestat_reg
= PIPEBSTAT
;
345 interrupt
= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
348 DRM_ERROR("tried to enable vblank on non-existent pipe %d\n",
353 spin_lock_irqsave(&dev_priv
->user_irq_lock
, irqflags
);
354 /* Enabling vblank events in IMR comes before PIPESTAT write, or
355 * there's a race where the PIPESTAT vblank bit gets set to 1, so
356 * the OR of enabled PIPESTAT bits goes to 1, so the PIPExEVENT in
357 * ISR flashes to 1, but the IIR bit doesn't get set to 1 because
358 * IMR masks it. It doesn't ever get set after we clear the masking
359 * in IMR because the ISR bit is edge, not level-triggered, on the
360 * OR of PIPESTAT bits.
362 i915_enable_irq(dev_priv
, interrupt
);
363 pipestat
= I915_READ(pipestat_reg
);
365 pipestat
|= PIPE_START_VBLANK_INTERRUPT_ENABLE
;
367 pipestat
|= PIPE_VBLANK_INTERRUPT_ENABLE
;
368 /* Clear any stale interrupt status */
369 pipestat
|= (PIPE_START_VBLANK_INTERRUPT_STATUS
|
370 PIPE_VBLANK_INTERRUPT_STATUS
);
371 I915_WRITE(pipestat_reg
, pipestat
);
372 (void) I915_READ(pipestat_reg
); /* Posting read */
373 spin_unlock_irqrestore(&dev_priv
->user_irq_lock
, irqflags
);
378 /* Called from drm generic code, passed 'crtc' which
379 * we use as a pipe index
381 void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
383 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
384 u32 pipestat_reg
= 0;
387 unsigned long irqflags
;
391 pipestat_reg
= PIPEASTAT
;
392 interrupt
= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
;
395 pipestat_reg
= PIPEBSTAT
;
396 interrupt
= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
399 DRM_ERROR("tried to disable vblank on non-existent pipe %d\n",
405 spin_lock_irqsave(&dev_priv
->user_irq_lock
, irqflags
);
406 i915_disable_irq(dev_priv
, interrupt
);
407 pipestat
= I915_READ(pipestat_reg
);
408 pipestat
&= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE
|
409 PIPE_VBLANK_INTERRUPT_ENABLE
);
410 /* Clear any stale interrupt status */
411 pipestat
|= (PIPE_START_VBLANK_INTERRUPT_STATUS
|
412 PIPE_VBLANK_INTERRUPT_STATUS
);
413 I915_WRITE(pipestat_reg
, pipestat
);
414 (void) I915_READ(pipestat_reg
); /* Posting read */
415 spin_unlock_irqrestore(&dev_priv
->user_irq_lock
, irqflags
);
418 /* Set the vblank monitor pipe
420 int i915_vblank_pipe_set(struct drm_device
*dev
, void *data
,
421 struct drm_file
*file_priv
)
423 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
426 DRM_ERROR("called with no initialization\n");
433 int i915_vblank_pipe_get(struct drm_device
*dev
, void *data
,
434 struct drm_file
*file_priv
)
436 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
437 drm_i915_vblank_pipe_t
*pipe
= data
;
440 DRM_ERROR("called with no initialization\n");
444 pipe
->pipe
= DRM_I915_VBLANK_PIPE_A
| DRM_I915_VBLANK_PIPE_B
;
450 * Schedule buffer swap at given vertical blank.
452 int i915_vblank_swap(struct drm_device
*dev
, void *data
,
453 struct drm_file
*file_priv
)
455 /* The delayed swap mechanism was fundamentally racy, and has been
456 * removed. The model was that the client requested a delayed flip/swap
457 * from the kernel, then waited for vblank before continuing to perform
458 * rendering. The problem was that the kernel might wake the client
459 * up before it dispatched the vblank swap (since the lock has to be
460 * held while touching the ringbuffer), in which case the client would
461 * clear and start the next frame before the swap occurred, and
462 * flicker would occur in addition to likely missing the vblank.
464 * In the absence of this ioctl, userland falls back to a correct path
465 * of waiting for a vblank, then dispatching the swap on its own.
466 * Context switching to userland and back is plenty fast enough for
467 * meeting the requirements of vblank swapping.
474 void i915_driver_irq_preinstall(struct drm_device
* dev
)
476 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
478 I915_WRITE(HWSTAM
, 0xeffe);
479 I915_WRITE(IMR
, 0xffffffff);
480 I915_WRITE(IER
, 0x0);
483 int i915_driver_irq_postinstall(struct drm_device
*dev
)
485 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
486 int ret
, num_pipes
= 2;
488 /* Set initial unmasked IRQs to just the selected vblank pipes. */
489 dev_priv
->irq_mask_reg
= ~0;
491 ret
= drm_vblank_init(dev
, num_pipes
);
495 dev_priv
->vblank_pipe
= DRM_I915_VBLANK_PIPE_A
| DRM_I915_VBLANK_PIPE_B
;
496 dev_priv
->irq_mask_reg
&= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
497 dev_priv
->irq_mask_reg
&= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
499 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
501 dev_priv
->irq_mask_reg
&= I915_INTERRUPT_ENABLE_MASK
;
503 I915_WRITE(IMR
, dev_priv
->irq_mask_reg
);
504 I915_WRITE(IER
, I915_INTERRUPT_ENABLE_MASK
);
505 (void) I915_READ(IER
);
507 opregion_enable_asle(dev
);
508 DRM_INIT_WAITQUEUE(&dev_priv
->irq_queue
);
513 void i915_driver_irq_uninstall(struct drm_device
* dev
)
515 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
521 dev_priv
->vblank_pipe
= 0;
523 I915_WRITE(HWSTAM
, 0xffffffff);
524 I915_WRITE(IMR
, 0xffffffff);
525 I915_WRITE(IER
, 0x0);
527 temp
= I915_READ(PIPEASTAT
);
528 I915_WRITE(PIPEASTAT
, temp
);
529 temp
= I915_READ(PIPEBSTAT
);
530 I915_WRITE(PIPEBSTAT
, temp
);
531 temp
= I915_READ(IIR
);
532 I915_WRITE(IIR
, temp
);