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[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
34 #include <drm/drmP.h>
35 #include <drm/i915_drm.h>
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "intel_drv.h"
39
40 /**
41 * DOC: interrupt handling
42 *
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
46 */
47
48 static const u32 hpd_ibx[HPD_NUM_PINS] = {
49 [HPD_CRT] = SDE_CRT_HOTPLUG,
50 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
51 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
52 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
53 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
54 };
55
56 static const u32 hpd_cpt[HPD_NUM_PINS] = {
57 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
58 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
59 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
60 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
61 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
62 };
63
64 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
65 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
66 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
67 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
68 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
69 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
70 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
71 };
72
73 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
74 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
75 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
76 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
77 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
78 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
79 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
80 };
81
82 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
83 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
84 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
85 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
86 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
87 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
88 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
89 };
90
91 /* BXT hpd list */
92 static const u32 hpd_bxt[HPD_NUM_PINS] = {
93 [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
94 [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
95 };
96
97 /* IIR can theoretically queue up two events. Be paranoid. */
98 #define GEN8_IRQ_RESET_NDX(type, which) do { \
99 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
100 POSTING_READ(GEN8_##type##_IMR(which)); \
101 I915_WRITE(GEN8_##type##_IER(which), 0); \
102 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
103 POSTING_READ(GEN8_##type##_IIR(which)); \
104 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
105 POSTING_READ(GEN8_##type##_IIR(which)); \
106 } while (0)
107
108 #define GEN5_IRQ_RESET(type) do { \
109 I915_WRITE(type##IMR, 0xffffffff); \
110 POSTING_READ(type##IMR); \
111 I915_WRITE(type##IER, 0); \
112 I915_WRITE(type##IIR, 0xffffffff); \
113 POSTING_READ(type##IIR); \
114 I915_WRITE(type##IIR, 0xffffffff); \
115 POSTING_READ(type##IIR); \
116 } while (0)
117
118 /*
119 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
120 */
121 #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
122 u32 val = I915_READ(reg); \
123 if (val) { \
124 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
125 (reg), val); \
126 I915_WRITE((reg), 0xffffffff); \
127 POSTING_READ(reg); \
128 I915_WRITE((reg), 0xffffffff); \
129 POSTING_READ(reg); \
130 } \
131 } while (0)
132
133 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
134 GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
135 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
136 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
137 POSTING_READ(GEN8_##type##_IMR(which)); \
138 } while (0)
139
140 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
141 GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
142 I915_WRITE(type##IER, (ier_val)); \
143 I915_WRITE(type##IMR, (imr_val)); \
144 POSTING_READ(type##IMR); \
145 } while (0)
146
147 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
148
149 /* For display hotplug interrupt */
150 void
151 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
152 {
153 assert_spin_locked(&dev_priv->irq_lock);
154
155 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
156 return;
157
158 if ((dev_priv->irq_mask & mask) != 0) {
159 dev_priv->irq_mask &= ~mask;
160 I915_WRITE(DEIMR, dev_priv->irq_mask);
161 POSTING_READ(DEIMR);
162 }
163 }
164
165 void
166 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
167 {
168 assert_spin_locked(&dev_priv->irq_lock);
169
170 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
171 return;
172
173 if ((dev_priv->irq_mask & mask) != mask) {
174 dev_priv->irq_mask |= mask;
175 I915_WRITE(DEIMR, dev_priv->irq_mask);
176 POSTING_READ(DEIMR);
177 }
178 }
179
180 /**
181 * ilk_update_gt_irq - update GTIMR
182 * @dev_priv: driver private
183 * @interrupt_mask: mask of interrupt bits to update
184 * @enabled_irq_mask: mask of interrupt bits to enable
185 */
186 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
187 uint32_t interrupt_mask,
188 uint32_t enabled_irq_mask)
189 {
190 assert_spin_locked(&dev_priv->irq_lock);
191
192 WARN_ON(enabled_irq_mask & ~interrupt_mask);
193
194 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
195 return;
196
197 dev_priv->gt_irq_mask &= ~interrupt_mask;
198 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
199 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
200 POSTING_READ(GTIMR);
201 }
202
203 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
204 {
205 ilk_update_gt_irq(dev_priv, mask, mask);
206 }
207
208 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
209 {
210 ilk_update_gt_irq(dev_priv, mask, 0);
211 }
212
213 static u32 gen6_pm_iir(struct drm_i915_private *dev_priv)
214 {
215 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
216 }
217
218 static u32 gen6_pm_imr(struct drm_i915_private *dev_priv)
219 {
220 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
221 }
222
223 static u32 gen6_pm_ier(struct drm_i915_private *dev_priv)
224 {
225 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
226 }
227
228 /**
229 * snb_update_pm_irq - update GEN6_PMIMR
230 * @dev_priv: driver private
231 * @interrupt_mask: mask of interrupt bits to update
232 * @enabled_irq_mask: mask of interrupt bits to enable
233 */
234 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
235 uint32_t interrupt_mask,
236 uint32_t enabled_irq_mask)
237 {
238 uint32_t new_val;
239
240 WARN_ON(enabled_irq_mask & ~interrupt_mask);
241
242 assert_spin_locked(&dev_priv->irq_lock);
243
244 new_val = dev_priv->pm_irq_mask;
245 new_val &= ~interrupt_mask;
246 new_val |= (~enabled_irq_mask & interrupt_mask);
247
248 if (new_val != dev_priv->pm_irq_mask) {
249 dev_priv->pm_irq_mask = new_val;
250 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
251 POSTING_READ(gen6_pm_imr(dev_priv));
252 }
253 }
254
255 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
256 {
257 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
258 return;
259
260 snb_update_pm_irq(dev_priv, mask, mask);
261 }
262
263 static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
264 uint32_t mask)
265 {
266 snb_update_pm_irq(dev_priv, mask, 0);
267 }
268
269 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
270 {
271 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
272 return;
273
274 __gen6_disable_pm_irq(dev_priv, mask);
275 }
276
277 void gen6_reset_rps_interrupts(struct drm_device *dev)
278 {
279 struct drm_i915_private *dev_priv = dev->dev_private;
280 uint32_t reg = gen6_pm_iir(dev_priv);
281
282 spin_lock_irq(&dev_priv->irq_lock);
283 I915_WRITE(reg, dev_priv->pm_rps_events);
284 I915_WRITE(reg, dev_priv->pm_rps_events);
285 POSTING_READ(reg);
286 dev_priv->rps.pm_iir = 0;
287 spin_unlock_irq(&dev_priv->irq_lock);
288 }
289
290 void gen6_enable_rps_interrupts(struct drm_device *dev)
291 {
292 struct drm_i915_private *dev_priv = dev->dev_private;
293
294 spin_lock_irq(&dev_priv->irq_lock);
295
296 WARN_ON(dev_priv->rps.pm_iir);
297 WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
298 dev_priv->rps.interrupts_enabled = true;
299 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
300 dev_priv->pm_rps_events);
301 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
302
303 spin_unlock_irq(&dev_priv->irq_lock);
304 }
305
306 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
307 {
308 /*
309 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
310 * if GEN6_PM_UP_EI_EXPIRED is masked.
311 *
312 * TODO: verify if this can be reproduced on VLV,CHV.
313 */
314 if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
315 mask &= ~GEN6_PM_RP_UP_EI_EXPIRED;
316
317 if (INTEL_INFO(dev_priv)->gen >= 8)
318 mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
319
320 return mask;
321 }
322
323 void gen6_disable_rps_interrupts(struct drm_device *dev)
324 {
325 struct drm_i915_private *dev_priv = dev->dev_private;
326
327 spin_lock_irq(&dev_priv->irq_lock);
328 dev_priv->rps.interrupts_enabled = false;
329 spin_unlock_irq(&dev_priv->irq_lock);
330
331 cancel_work_sync(&dev_priv->rps.work);
332
333 spin_lock_irq(&dev_priv->irq_lock);
334
335 I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
336
337 __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
338 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
339 ~dev_priv->pm_rps_events);
340
341 spin_unlock_irq(&dev_priv->irq_lock);
342
343 synchronize_irq(dev->irq);
344 }
345
346 /**
347 * ibx_display_interrupt_update - update SDEIMR
348 * @dev_priv: driver private
349 * @interrupt_mask: mask of interrupt bits to update
350 * @enabled_irq_mask: mask of interrupt bits to enable
351 */
352 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
353 uint32_t interrupt_mask,
354 uint32_t enabled_irq_mask)
355 {
356 uint32_t sdeimr = I915_READ(SDEIMR);
357 sdeimr &= ~interrupt_mask;
358 sdeimr |= (~enabled_irq_mask & interrupt_mask);
359
360 WARN_ON(enabled_irq_mask & ~interrupt_mask);
361
362 assert_spin_locked(&dev_priv->irq_lock);
363
364 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
365 return;
366
367 I915_WRITE(SDEIMR, sdeimr);
368 POSTING_READ(SDEIMR);
369 }
370
371 static void
372 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
373 u32 enable_mask, u32 status_mask)
374 {
375 u32 reg = PIPESTAT(pipe);
376 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
377
378 assert_spin_locked(&dev_priv->irq_lock);
379 WARN_ON(!intel_irqs_enabled(dev_priv));
380
381 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
382 status_mask & ~PIPESTAT_INT_STATUS_MASK,
383 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
384 pipe_name(pipe), enable_mask, status_mask))
385 return;
386
387 if ((pipestat & enable_mask) == enable_mask)
388 return;
389
390 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
391
392 /* Enable the interrupt, clear any pending status */
393 pipestat |= enable_mask | status_mask;
394 I915_WRITE(reg, pipestat);
395 POSTING_READ(reg);
396 }
397
398 static void
399 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
400 u32 enable_mask, u32 status_mask)
401 {
402 u32 reg = PIPESTAT(pipe);
403 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
404
405 assert_spin_locked(&dev_priv->irq_lock);
406 WARN_ON(!intel_irqs_enabled(dev_priv));
407
408 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
409 status_mask & ~PIPESTAT_INT_STATUS_MASK,
410 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
411 pipe_name(pipe), enable_mask, status_mask))
412 return;
413
414 if ((pipestat & enable_mask) == 0)
415 return;
416
417 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
418
419 pipestat &= ~enable_mask;
420 I915_WRITE(reg, pipestat);
421 POSTING_READ(reg);
422 }
423
424 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
425 {
426 u32 enable_mask = status_mask << 16;
427
428 /*
429 * On pipe A we don't support the PSR interrupt yet,
430 * on pipe B and C the same bit MBZ.
431 */
432 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
433 return 0;
434 /*
435 * On pipe B and C we don't support the PSR interrupt yet, on pipe
436 * A the same bit is for perf counters which we don't use either.
437 */
438 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
439 return 0;
440
441 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
442 SPRITE0_FLIP_DONE_INT_EN_VLV |
443 SPRITE1_FLIP_DONE_INT_EN_VLV);
444 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
445 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
446 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
447 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
448
449 return enable_mask;
450 }
451
452 void
453 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
454 u32 status_mask)
455 {
456 u32 enable_mask;
457
458 if (IS_VALLEYVIEW(dev_priv->dev))
459 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
460 status_mask);
461 else
462 enable_mask = status_mask << 16;
463 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
464 }
465
466 void
467 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
468 u32 status_mask)
469 {
470 u32 enable_mask;
471
472 if (IS_VALLEYVIEW(dev_priv->dev))
473 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
474 status_mask);
475 else
476 enable_mask = status_mask << 16;
477 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
478 }
479
480 /**
481 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
482 */
483 static void i915_enable_asle_pipestat(struct drm_device *dev)
484 {
485 struct drm_i915_private *dev_priv = dev->dev_private;
486
487 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
488 return;
489
490 spin_lock_irq(&dev_priv->irq_lock);
491
492 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
493 if (INTEL_INFO(dev)->gen >= 4)
494 i915_enable_pipestat(dev_priv, PIPE_A,
495 PIPE_LEGACY_BLC_EVENT_STATUS);
496
497 spin_unlock_irq(&dev_priv->irq_lock);
498 }
499
500 /*
501 * This timing diagram depicts the video signal in and
502 * around the vertical blanking period.
503 *
504 * Assumptions about the fictitious mode used in this example:
505 * vblank_start >= 3
506 * vsync_start = vblank_start + 1
507 * vsync_end = vblank_start + 2
508 * vtotal = vblank_start + 3
509 *
510 * start of vblank:
511 * latch double buffered registers
512 * increment frame counter (ctg+)
513 * generate start of vblank interrupt (gen4+)
514 * |
515 * | frame start:
516 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
517 * | may be shifted forward 1-3 extra lines via PIPECONF
518 * | |
519 * | | start of vsync:
520 * | | generate vsync interrupt
521 * | | |
522 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
523 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
524 * ----va---> <-----------------vb--------------------> <--------va-------------
525 * | | <----vs-----> |
526 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
527 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
528 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
529 * | | |
530 * last visible pixel first visible pixel
531 * | increment frame counter (gen3/4)
532 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
533 *
534 * x = horizontal active
535 * _ = horizontal blanking
536 * hs = horizontal sync
537 * va = vertical active
538 * vb = vertical blanking
539 * vs = vertical sync
540 * vbs = vblank_start (number)
541 *
542 * Summary:
543 * - most events happen at the start of horizontal sync
544 * - frame start happens at the start of horizontal blank, 1-4 lines
545 * (depending on PIPECONF settings) after the start of vblank
546 * - gen3/4 pixel and frame counter are synchronized with the start
547 * of horizontal active on the first line of vertical active
548 */
549
550 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
551 {
552 /* Gen2 doesn't have a hardware frame counter */
553 return 0;
554 }
555
556 /* Called from drm generic code, passed a 'crtc', which
557 * we use as a pipe index
558 */
559 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
560 {
561 struct drm_i915_private *dev_priv = dev->dev_private;
562 unsigned long high_frame;
563 unsigned long low_frame;
564 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
565 struct intel_crtc *intel_crtc =
566 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
567 const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
568
569 htotal = mode->crtc_htotal;
570 hsync_start = mode->crtc_hsync_start;
571 vbl_start = mode->crtc_vblank_start;
572 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
573 vbl_start = DIV_ROUND_UP(vbl_start, 2);
574
575 /* Convert to pixel count */
576 vbl_start *= htotal;
577
578 /* Start of vblank event occurs at start of hsync */
579 vbl_start -= htotal - hsync_start;
580
581 high_frame = PIPEFRAME(pipe);
582 low_frame = PIPEFRAMEPIXEL(pipe);
583
584 /*
585 * High & low register fields aren't synchronized, so make sure
586 * we get a low value that's stable across two reads of the high
587 * register.
588 */
589 do {
590 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
591 low = I915_READ(low_frame);
592 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
593 } while (high1 != high2);
594
595 high1 >>= PIPE_FRAME_HIGH_SHIFT;
596 pixel = low & PIPE_PIXEL_MASK;
597 low >>= PIPE_FRAME_LOW_SHIFT;
598
599 /*
600 * The frame counter increments at beginning of active.
601 * Cook up a vblank counter by also checking the pixel
602 * counter against vblank start.
603 */
604 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
605 }
606
607 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
608 {
609 struct drm_i915_private *dev_priv = dev->dev_private;
610 int reg = PIPE_FRMCOUNT_GM45(pipe);
611
612 return I915_READ(reg);
613 }
614
615 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
616 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
617
618 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
619 {
620 struct drm_device *dev = crtc->base.dev;
621 struct drm_i915_private *dev_priv = dev->dev_private;
622 const struct drm_display_mode *mode = &crtc->base.hwmode;
623 enum pipe pipe = crtc->pipe;
624 int position, vtotal;
625
626 vtotal = mode->crtc_vtotal;
627 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
628 vtotal /= 2;
629
630 if (IS_GEN2(dev))
631 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
632 else
633 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
634
635 /*
636 * See update_scanline_offset() for the details on the
637 * scanline_offset adjustment.
638 */
639 return (position + crtc->scanline_offset) % vtotal;
640 }
641
642 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
643 unsigned int flags, int *vpos, int *hpos,
644 ktime_t *stime, ktime_t *etime)
645 {
646 struct drm_i915_private *dev_priv = dev->dev_private;
647 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
649 const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
650 int position;
651 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
652 bool in_vbl = true;
653 int ret = 0;
654 unsigned long irqflags;
655
656 if (WARN_ON(!mode->crtc_clock)) {
657 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
658 "pipe %c\n", pipe_name(pipe));
659 return 0;
660 }
661
662 htotal = mode->crtc_htotal;
663 hsync_start = mode->crtc_hsync_start;
664 vtotal = mode->crtc_vtotal;
665 vbl_start = mode->crtc_vblank_start;
666 vbl_end = mode->crtc_vblank_end;
667
668 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
669 vbl_start = DIV_ROUND_UP(vbl_start, 2);
670 vbl_end /= 2;
671 vtotal /= 2;
672 }
673
674 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
675
676 /*
677 * Lock uncore.lock, as we will do multiple timing critical raw
678 * register reads, potentially with preemption disabled, so the
679 * following code must not block on uncore.lock.
680 */
681 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
682
683 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
684
685 /* Get optional system timestamp before query. */
686 if (stime)
687 *stime = ktime_get();
688
689 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
690 /* No obvious pixelcount register. Only query vertical
691 * scanout position from Display scan line register.
692 */
693 position = __intel_get_crtc_scanline(intel_crtc);
694 } else {
695 /* Have access to pixelcount since start of frame.
696 * We can split this into vertical and horizontal
697 * scanout position.
698 */
699 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
700
701 /* convert to pixel counts */
702 vbl_start *= htotal;
703 vbl_end *= htotal;
704 vtotal *= htotal;
705
706 /*
707 * In interlaced modes, the pixel counter counts all pixels,
708 * so one field will have htotal more pixels. In order to avoid
709 * the reported position from jumping backwards when the pixel
710 * counter is beyond the length of the shorter field, just
711 * clamp the position the length of the shorter field. This
712 * matches how the scanline counter based position works since
713 * the scanline counter doesn't count the two half lines.
714 */
715 if (position >= vtotal)
716 position = vtotal - 1;
717
718 /*
719 * Start of vblank interrupt is triggered at start of hsync,
720 * just prior to the first active line of vblank. However we
721 * consider lines to start at the leading edge of horizontal
722 * active. So, should we get here before we've crossed into
723 * the horizontal active of the first line in vblank, we would
724 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
725 * always add htotal-hsync_start to the current pixel position.
726 */
727 position = (position + htotal - hsync_start) % vtotal;
728 }
729
730 /* Get optional system timestamp after query. */
731 if (etime)
732 *etime = ktime_get();
733
734 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
735
736 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
737
738 in_vbl = position >= vbl_start && position < vbl_end;
739
740 /*
741 * While in vblank, position will be negative
742 * counting up towards 0 at vbl_end. And outside
743 * vblank, position will be positive counting
744 * up since vbl_end.
745 */
746 if (position >= vbl_start)
747 position -= vbl_end;
748 else
749 position += vtotal - vbl_end;
750
751 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
752 *vpos = position;
753 *hpos = 0;
754 } else {
755 *vpos = position / htotal;
756 *hpos = position - (*vpos * htotal);
757 }
758
759 /* In vblank? */
760 if (in_vbl)
761 ret |= DRM_SCANOUTPOS_IN_VBLANK;
762
763 return ret;
764 }
765
766 int intel_get_crtc_scanline(struct intel_crtc *crtc)
767 {
768 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
769 unsigned long irqflags;
770 int position;
771
772 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
773 position = __intel_get_crtc_scanline(crtc);
774 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
775
776 return position;
777 }
778
779 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
780 int *max_error,
781 struct timeval *vblank_time,
782 unsigned flags)
783 {
784 struct drm_crtc *crtc;
785
786 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
787 DRM_ERROR("Invalid crtc %d\n", pipe);
788 return -EINVAL;
789 }
790
791 /* Get drm_crtc to timestamp: */
792 crtc = intel_get_crtc_for_pipe(dev, pipe);
793 if (crtc == NULL) {
794 DRM_ERROR("Invalid crtc %d\n", pipe);
795 return -EINVAL;
796 }
797
798 if (!crtc->hwmode.crtc_clock) {
799 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
800 return -EBUSY;
801 }
802
803 /* Helper routine in DRM core does all the work: */
804 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
805 vblank_time, flags,
806 crtc,
807 &crtc->hwmode);
808 }
809
810 static bool intel_hpd_irq_event(struct drm_device *dev,
811 struct drm_connector *connector)
812 {
813 enum drm_connector_status old_status;
814
815 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
816 old_status = connector->status;
817
818 connector->status = connector->funcs->detect(connector, false);
819 if (old_status == connector->status)
820 return false;
821
822 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
823 connector->base.id,
824 connector->name,
825 drm_get_connector_status_name(old_status),
826 drm_get_connector_status_name(connector->status));
827
828 return true;
829 }
830
831 static void i915_digport_work_func(struct work_struct *work)
832 {
833 struct drm_i915_private *dev_priv =
834 container_of(work, struct drm_i915_private, hotplug.dig_port_work);
835 u32 long_port_mask, short_port_mask;
836 struct intel_digital_port *intel_dig_port;
837 int i;
838 u32 old_bits = 0;
839
840 spin_lock_irq(&dev_priv->irq_lock);
841 long_port_mask = dev_priv->hotplug.long_port_mask;
842 dev_priv->hotplug.long_port_mask = 0;
843 short_port_mask = dev_priv->hotplug.short_port_mask;
844 dev_priv->hotplug.short_port_mask = 0;
845 spin_unlock_irq(&dev_priv->irq_lock);
846
847 for (i = 0; i < I915_MAX_PORTS; i++) {
848 bool valid = false;
849 bool long_hpd = false;
850 intel_dig_port = dev_priv->hotplug.irq_port[i];
851 if (!intel_dig_port || !intel_dig_port->hpd_pulse)
852 continue;
853
854 if (long_port_mask & (1 << i)) {
855 valid = true;
856 long_hpd = true;
857 } else if (short_port_mask & (1 << i))
858 valid = true;
859
860 if (valid) {
861 enum irqreturn ret;
862
863 ret = intel_dig_port->hpd_pulse(intel_dig_port, long_hpd);
864 if (ret == IRQ_NONE) {
865 /* fall back to old school hpd */
866 old_bits |= (1 << intel_dig_port->base.hpd_pin);
867 }
868 }
869 }
870
871 if (old_bits) {
872 spin_lock_irq(&dev_priv->irq_lock);
873 dev_priv->hotplug.event_bits |= old_bits;
874 spin_unlock_irq(&dev_priv->irq_lock);
875 schedule_work(&dev_priv->hotplug.hotplug_work);
876 }
877 }
878
879 /*
880 * Handle hotplug events outside the interrupt handler proper.
881 */
882 static void intel_hpd_irq_storm_disable(struct drm_i915_private *dev_priv);
883
884 static void i915_hotplug_work_func(struct work_struct *work)
885 {
886 struct drm_i915_private *dev_priv =
887 container_of(work, struct drm_i915_private, hotplug.hotplug_work);
888 struct drm_device *dev = dev_priv->dev;
889 struct drm_mode_config *mode_config = &dev->mode_config;
890 struct intel_connector *intel_connector;
891 struct intel_encoder *intel_encoder;
892 struct drm_connector *connector;
893 bool changed = false;
894 u32 hpd_event_bits;
895
896 mutex_lock(&mode_config->mutex);
897 DRM_DEBUG_KMS("running encoder hotplug functions\n");
898
899 spin_lock_irq(&dev_priv->irq_lock);
900
901 hpd_event_bits = dev_priv->hotplug.event_bits;
902 dev_priv->hotplug.event_bits = 0;
903
904 /* Disable hotplug on connectors that hit an irq storm. */
905 intel_hpd_irq_storm_disable(dev_priv);
906
907 spin_unlock_irq(&dev_priv->irq_lock);
908
909 list_for_each_entry(connector, &mode_config->connector_list, head) {
910 intel_connector = to_intel_connector(connector);
911 if (!intel_connector->encoder)
912 continue;
913 intel_encoder = intel_connector->encoder;
914 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
915 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
916 connector->name, intel_encoder->hpd_pin);
917 if (intel_encoder->hot_plug)
918 intel_encoder->hot_plug(intel_encoder);
919 if (intel_hpd_irq_event(dev, connector))
920 changed = true;
921 }
922 }
923 mutex_unlock(&mode_config->mutex);
924
925 if (changed)
926 drm_kms_helper_hotplug_event(dev);
927 }
928
929 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
930 {
931 struct drm_i915_private *dev_priv = dev->dev_private;
932 u32 busy_up, busy_down, max_avg, min_avg;
933 u8 new_delay;
934
935 spin_lock(&mchdev_lock);
936
937 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
938
939 new_delay = dev_priv->ips.cur_delay;
940
941 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
942 busy_up = I915_READ(RCPREVBSYTUPAVG);
943 busy_down = I915_READ(RCPREVBSYTDNAVG);
944 max_avg = I915_READ(RCBMAXAVG);
945 min_avg = I915_READ(RCBMINAVG);
946
947 /* Handle RCS change request from hw */
948 if (busy_up > max_avg) {
949 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
950 new_delay = dev_priv->ips.cur_delay - 1;
951 if (new_delay < dev_priv->ips.max_delay)
952 new_delay = dev_priv->ips.max_delay;
953 } else if (busy_down < min_avg) {
954 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
955 new_delay = dev_priv->ips.cur_delay + 1;
956 if (new_delay > dev_priv->ips.min_delay)
957 new_delay = dev_priv->ips.min_delay;
958 }
959
960 if (ironlake_set_drps(dev, new_delay))
961 dev_priv->ips.cur_delay = new_delay;
962
963 spin_unlock(&mchdev_lock);
964
965 return;
966 }
967
968 static void notify_ring(struct intel_engine_cs *ring)
969 {
970 if (!intel_ring_initialized(ring))
971 return;
972
973 trace_i915_gem_request_notify(ring);
974
975 wake_up_all(&ring->irq_queue);
976 }
977
978 static void vlv_c0_read(struct drm_i915_private *dev_priv,
979 struct intel_rps_ei *ei)
980 {
981 ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
982 ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
983 ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
984 }
985
986 static bool vlv_c0_above(struct drm_i915_private *dev_priv,
987 const struct intel_rps_ei *old,
988 const struct intel_rps_ei *now,
989 int threshold)
990 {
991 u64 time, c0;
992
993 if (old->cz_clock == 0)
994 return false;
995
996 time = now->cz_clock - old->cz_clock;
997 time *= threshold * dev_priv->mem_freq;
998
999 /* Workload can be split between render + media, e.g. SwapBuffers
1000 * being blitted in X after being rendered in mesa. To account for
1001 * this we need to combine both engines into our activity counter.
1002 */
1003 c0 = now->render_c0 - old->render_c0;
1004 c0 += now->media_c0 - old->media_c0;
1005 c0 *= 100 * VLV_CZ_CLOCK_TO_MILLI_SEC * 4 / 1000;
1006
1007 return c0 >= time;
1008 }
1009
1010 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1011 {
1012 vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);
1013 dev_priv->rps.up_ei = dev_priv->rps.down_ei;
1014 }
1015
1016 static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1017 {
1018 struct intel_rps_ei now;
1019 u32 events = 0;
1020
1021 if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0)
1022 return 0;
1023
1024 vlv_c0_read(dev_priv, &now);
1025 if (now.cz_clock == 0)
1026 return 0;
1027
1028 if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
1029 if (!vlv_c0_above(dev_priv,
1030 &dev_priv->rps.down_ei, &now,
1031 dev_priv->rps.down_threshold))
1032 events |= GEN6_PM_RP_DOWN_THRESHOLD;
1033 dev_priv->rps.down_ei = now;
1034 }
1035
1036 if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1037 if (vlv_c0_above(dev_priv,
1038 &dev_priv->rps.up_ei, &now,
1039 dev_priv->rps.up_threshold))
1040 events |= GEN6_PM_RP_UP_THRESHOLD;
1041 dev_priv->rps.up_ei = now;
1042 }
1043
1044 return events;
1045 }
1046
1047 static bool any_waiters(struct drm_i915_private *dev_priv)
1048 {
1049 struct intel_engine_cs *ring;
1050 int i;
1051
1052 for_each_ring(ring, dev_priv, i)
1053 if (ring->irq_refcount)
1054 return true;
1055
1056 return false;
1057 }
1058
1059 static void gen6_pm_rps_work(struct work_struct *work)
1060 {
1061 struct drm_i915_private *dev_priv =
1062 container_of(work, struct drm_i915_private, rps.work);
1063 bool client_boost;
1064 int new_delay, adj, min, max;
1065 u32 pm_iir;
1066
1067 spin_lock_irq(&dev_priv->irq_lock);
1068 /* Speed up work cancelation during disabling rps interrupts. */
1069 if (!dev_priv->rps.interrupts_enabled) {
1070 spin_unlock_irq(&dev_priv->irq_lock);
1071 return;
1072 }
1073 pm_iir = dev_priv->rps.pm_iir;
1074 dev_priv->rps.pm_iir = 0;
1075 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1076 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1077 client_boost = dev_priv->rps.client_boost;
1078 dev_priv->rps.client_boost = false;
1079 spin_unlock_irq(&dev_priv->irq_lock);
1080
1081 /* Make sure we didn't queue anything we're not going to process. */
1082 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1083
1084 if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1085 return;
1086
1087 mutex_lock(&dev_priv->rps.hw_lock);
1088
1089 pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1090
1091 adj = dev_priv->rps.last_adj;
1092 new_delay = dev_priv->rps.cur_freq;
1093 min = dev_priv->rps.min_freq_softlimit;
1094 max = dev_priv->rps.max_freq_softlimit;
1095
1096 if (client_boost) {
1097 new_delay = dev_priv->rps.max_freq_softlimit;
1098 adj = 0;
1099 } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1100 if (adj > 0)
1101 adj *= 2;
1102 else /* CHV needs even encode values */
1103 adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1104 /*
1105 * For better performance, jump directly
1106 * to RPe if we're below it.
1107 */
1108 if (new_delay < dev_priv->rps.efficient_freq - adj) {
1109 new_delay = dev_priv->rps.efficient_freq;
1110 adj = 0;
1111 }
1112 } else if (any_waiters(dev_priv)) {
1113 adj = 0;
1114 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1115 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1116 new_delay = dev_priv->rps.efficient_freq;
1117 else
1118 new_delay = dev_priv->rps.min_freq_softlimit;
1119 adj = 0;
1120 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1121 if (adj < 0)
1122 adj *= 2;
1123 else /* CHV needs even encode values */
1124 adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1125 } else { /* unknown event */
1126 adj = 0;
1127 }
1128
1129 dev_priv->rps.last_adj = adj;
1130
1131 /* sysfs frequency interfaces may have snuck in while servicing the
1132 * interrupt
1133 */
1134 new_delay += adj;
1135 new_delay = clamp_t(int, new_delay, min, max);
1136
1137 intel_set_rps(dev_priv->dev, new_delay);
1138
1139 mutex_unlock(&dev_priv->rps.hw_lock);
1140 }
1141
1142
1143 /**
1144 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1145 * occurred.
1146 * @work: workqueue struct
1147 *
1148 * Doesn't actually do anything except notify userspace. As a consequence of
1149 * this event, userspace should try to remap the bad rows since statistically
1150 * it is likely the same row is more likely to go bad again.
1151 */
1152 static void ivybridge_parity_work(struct work_struct *work)
1153 {
1154 struct drm_i915_private *dev_priv =
1155 container_of(work, struct drm_i915_private, l3_parity.error_work);
1156 u32 error_status, row, bank, subbank;
1157 char *parity_event[6];
1158 uint32_t misccpctl;
1159 uint8_t slice = 0;
1160
1161 /* We must turn off DOP level clock gating to access the L3 registers.
1162 * In order to prevent a get/put style interface, acquire struct mutex
1163 * any time we access those registers.
1164 */
1165 mutex_lock(&dev_priv->dev->struct_mutex);
1166
1167 /* If we've screwed up tracking, just let the interrupt fire again */
1168 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1169 goto out;
1170
1171 misccpctl = I915_READ(GEN7_MISCCPCTL);
1172 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1173 POSTING_READ(GEN7_MISCCPCTL);
1174
1175 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1176 u32 reg;
1177
1178 slice--;
1179 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1180 break;
1181
1182 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1183
1184 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1185
1186 error_status = I915_READ(reg);
1187 row = GEN7_PARITY_ERROR_ROW(error_status);
1188 bank = GEN7_PARITY_ERROR_BANK(error_status);
1189 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1190
1191 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1192 POSTING_READ(reg);
1193
1194 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1195 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1196 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1197 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1198 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1199 parity_event[5] = NULL;
1200
1201 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1202 KOBJ_CHANGE, parity_event);
1203
1204 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1205 slice, row, bank, subbank);
1206
1207 kfree(parity_event[4]);
1208 kfree(parity_event[3]);
1209 kfree(parity_event[2]);
1210 kfree(parity_event[1]);
1211 }
1212
1213 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1214
1215 out:
1216 WARN_ON(dev_priv->l3_parity.which_slice);
1217 spin_lock_irq(&dev_priv->irq_lock);
1218 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1219 spin_unlock_irq(&dev_priv->irq_lock);
1220
1221 mutex_unlock(&dev_priv->dev->struct_mutex);
1222 }
1223
1224 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1225 {
1226 struct drm_i915_private *dev_priv = dev->dev_private;
1227
1228 if (!HAS_L3_DPF(dev))
1229 return;
1230
1231 spin_lock(&dev_priv->irq_lock);
1232 gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1233 spin_unlock(&dev_priv->irq_lock);
1234
1235 iir &= GT_PARITY_ERROR(dev);
1236 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1237 dev_priv->l3_parity.which_slice |= 1 << 1;
1238
1239 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1240 dev_priv->l3_parity.which_slice |= 1 << 0;
1241
1242 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1243 }
1244
1245 static void ilk_gt_irq_handler(struct drm_device *dev,
1246 struct drm_i915_private *dev_priv,
1247 u32 gt_iir)
1248 {
1249 if (gt_iir &
1250 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1251 notify_ring(&dev_priv->ring[RCS]);
1252 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1253 notify_ring(&dev_priv->ring[VCS]);
1254 }
1255
1256 static void snb_gt_irq_handler(struct drm_device *dev,
1257 struct drm_i915_private *dev_priv,
1258 u32 gt_iir)
1259 {
1260
1261 if (gt_iir &
1262 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1263 notify_ring(&dev_priv->ring[RCS]);
1264 if (gt_iir & GT_BSD_USER_INTERRUPT)
1265 notify_ring(&dev_priv->ring[VCS]);
1266 if (gt_iir & GT_BLT_USER_INTERRUPT)
1267 notify_ring(&dev_priv->ring[BCS]);
1268
1269 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1270 GT_BSD_CS_ERROR_INTERRUPT |
1271 GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1272 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1273
1274 if (gt_iir & GT_PARITY_ERROR(dev))
1275 ivybridge_parity_error_irq_handler(dev, gt_iir);
1276 }
1277
1278 static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
1279 u32 master_ctl)
1280 {
1281 irqreturn_t ret = IRQ_NONE;
1282
1283 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1284 u32 tmp = I915_READ_FW(GEN8_GT_IIR(0));
1285 if (tmp) {
1286 I915_WRITE_FW(GEN8_GT_IIR(0), tmp);
1287 ret = IRQ_HANDLED;
1288
1289 if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
1290 intel_lrc_irq_handler(&dev_priv->ring[RCS]);
1291 if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
1292 notify_ring(&dev_priv->ring[RCS]);
1293
1294 if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
1295 intel_lrc_irq_handler(&dev_priv->ring[BCS]);
1296 if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
1297 notify_ring(&dev_priv->ring[BCS]);
1298 } else
1299 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1300 }
1301
1302 if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1303 u32 tmp = I915_READ_FW(GEN8_GT_IIR(1));
1304 if (tmp) {
1305 I915_WRITE_FW(GEN8_GT_IIR(1), tmp);
1306 ret = IRQ_HANDLED;
1307
1308 if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
1309 intel_lrc_irq_handler(&dev_priv->ring[VCS]);
1310 if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
1311 notify_ring(&dev_priv->ring[VCS]);
1312
1313 if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
1314 intel_lrc_irq_handler(&dev_priv->ring[VCS2]);
1315 if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
1316 notify_ring(&dev_priv->ring[VCS2]);
1317 } else
1318 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1319 }
1320
1321 if (master_ctl & GEN8_GT_VECS_IRQ) {
1322 u32 tmp = I915_READ_FW(GEN8_GT_IIR(3));
1323 if (tmp) {
1324 I915_WRITE_FW(GEN8_GT_IIR(3), tmp);
1325 ret = IRQ_HANDLED;
1326
1327 if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
1328 intel_lrc_irq_handler(&dev_priv->ring[VECS]);
1329 if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
1330 notify_ring(&dev_priv->ring[VECS]);
1331 } else
1332 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1333 }
1334
1335 if (master_ctl & GEN8_GT_PM_IRQ) {
1336 u32 tmp = I915_READ_FW(GEN8_GT_IIR(2));
1337 if (tmp & dev_priv->pm_rps_events) {
1338 I915_WRITE_FW(GEN8_GT_IIR(2),
1339 tmp & dev_priv->pm_rps_events);
1340 ret = IRQ_HANDLED;
1341 gen6_rps_irq_handler(dev_priv, tmp);
1342 } else
1343 DRM_ERROR("The master control interrupt lied (PM)!\n");
1344 }
1345
1346 return ret;
1347 }
1348
1349 #define HPD_STORM_DETECT_PERIOD 1000
1350 #define HPD_STORM_THRESHOLD 5
1351
1352 /**
1353 * intel_hpd_irq_storm - gather stats and detect HPD irq storm on a pin
1354 * @dev_priv: private driver data pointer
1355 * @pin: the pin to gather stats on
1356 *
1357 * Gather stats about HPD irqs from the specified @pin, and detect irq
1358 * storms. Only the pin specific stats and state are changed, the caller is
1359 * responsible for further action.
1360 *
1361 * @HPD_STORM_THRESHOLD irqs are allowed within @HPD_STORM_DETECT_PERIOD ms,
1362 * otherwise it's considered an irq storm, and the irq state is set to
1363 * @HPD_MARK_DISABLED.
1364 *
1365 * Return true if an irq storm was detected on @pin.
1366 */
1367 static bool intel_hpd_irq_storm(struct drm_i915_private *dev_priv,
1368 enum hpd_pin pin)
1369 {
1370 unsigned long start = dev_priv->hotplug.stats[pin].last_jiffies;
1371 unsigned long end = start + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD);
1372 bool storm = false;
1373
1374 if (!time_in_range(jiffies, start, end)) {
1375 dev_priv->hotplug.stats[pin].last_jiffies = jiffies;
1376 dev_priv->hotplug.stats[pin].count = 0;
1377 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", pin);
1378 } else if (dev_priv->hotplug.stats[pin].count > HPD_STORM_THRESHOLD) {
1379 dev_priv->hotplug.stats[pin].state = HPD_MARK_DISABLED;
1380 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", pin);
1381 storm = true;
1382 } else {
1383 dev_priv->hotplug.stats[pin].count++;
1384 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", pin,
1385 dev_priv->hotplug.stats[pin].count);
1386 }
1387
1388 return storm;
1389 }
1390
1391 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
1392
1393 static void intel_hpd_irq_storm_disable(struct drm_i915_private *dev_priv)
1394 {
1395 struct drm_device *dev = dev_priv->dev;
1396 struct drm_mode_config *mode_config = &dev->mode_config;
1397 struct intel_connector *intel_connector;
1398 struct intel_encoder *intel_encoder;
1399 struct drm_connector *connector;
1400 enum hpd_pin pin;
1401 bool hpd_disabled = false;
1402
1403 assert_spin_locked(&dev_priv->irq_lock);
1404
1405 list_for_each_entry(connector, &mode_config->connector_list, head) {
1406 if (connector->polled != DRM_CONNECTOR_POLL_HPD)
1407 continue;
1408
1409 intel_connector = to_intel_connector(connector);
1410 intel_encoder = intel_connector->encoder;
1411 if (!intel_encoder)
1412 continue;
1413
1414 pin = intel_encoder->hpd_pin;
1415 if (pin == HPD_NONE ||
1416 dev_priv->hotplug.stats[pin].state != HPD_MARK_DISABLED)
1417 continue;
1418
1419 DRM_INFO("HPD interrupt storm detected on connector %s: "
1420 "switching from hotplug detection to polling\n",
1421 connector->name);
1422
1423 dev_priv->hotplug.stats[pin].state = HPD_DISABLED;
1424 connector->polled = DRM_CONNECTOR_POLL_CONNECT
1425 | DRM_CONNECTOR_POLL_DISCONNECT;
1426 hpd_disabled = true;
1427 }
1428
1429 /* Enable polling and queue hotplug re-enabling. */
1430 if (hpd_disabled) {
1431 drm_kms_helper_poll_enable(dev);
1432 mod_delayed_work(system_wq, &dev_priv->hotplug.reenable_work,
1433 msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
1434 }
1435 }
1436
1437 static bool pch_port_hotplug_long_detect(enum port port, u32 val)
1438 {
1439 switch (port) {
1440 case PORT_B:
1441 return val & PORTB_HOTPLUG_LONG_DETECT;
1442 case PORT_C:
1443 return val & PORTC_HOTPLUG_LONG_DETECT;
1444 case PORT_D:
1445 return val & PORTD_HOTPLUG_LONG_DETECT;
1446 default:
1447 return false;
1448 }
1449 }
1450
1451 static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
1452 {
1453 switch (port) {
1454 case PORT_B:
1455 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1456 case PORT_C:
1457 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1458 case PORT_D:
1459 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1460 default:
1461 return false;
1462 }
1463 }
1464
1465 static enum port get_port_from_pin(enum hpd_pin pin)
1466 {
1467 switch (pin) {
1468 case HPD_PORT_B:
1469 return PORT_B;
1470 case HPD_PORT_C:
1471 return PORT_C;
1472 case HPD_PORT_D:
1473 return PORT_D;
1474 default:
1475 return PORT_A; /* no hpd */
1476 }
1477 }
1478
1479 /* Get a bit mask of pins that have triggered, and which ones may be long. */
1480 static void pch_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
1481 u32 hotplug_trigger, u32 dig_hotplug_reg, const u32 hpd[HPD_NUM_PINS])
1482 {
1483 int i;
1484
1485 *pin_mask = 0;
1486 *long_mask = 0;
1487
1488 if (!hotplug_trigger)
1489 return;
1490
1491 for_each_hpd_pin(i) {
1492 if (hpd[i] & hotplug_trigger) {
1493 *pin_mask |= BIT(i);
1494
1495 if (pch_port_hotplug_long_detect(get_port_from_pin(i), dig_hotplug_reg))
1496 *long_mask |= BIT(i);
1497 }
1498 }
1499
1500 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1501 hotplug_trigger, dig_hotplug_reg, *pin_mask);
1502
1503 }
1504
1505 /* Get a bit mask of pins that have triggered, and which ones may be long. */
1506 static void i9xx_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
1507 u32 hotplug_trigger, const u32 hpd[HPD_NUM_PINS])
1508 {
1509 int i;
1510
1511 *pin_mask = 0;
1512 *long_mask = 0;
1513
1514 if (!hotplug_trigger)
1515 return;
1516
1517 for_each_hpd_pin(i) {
1518 if (hpd[i] & hotplug_trigger) {
1519 *pin_mask |= BIT(i);
1520
1521 if (i9xx_port_hotplug_long_detect(get_port_from_pin(i), hotplug_trigger))
1522 *long_mask |= BIT(i);
1523 }
1524 }
1525
1526 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, pins 0x%08x\n",
1527 hotplug_trigger, *pin_mask);
1528 }
1529
1530 /**
1531 * intel_hpd_irq_handler - main hotplug irq handler
1532 * @dev: drm device
1533 * @pin_mask: a mask of hpd pins that have triggered the irq
1534 * @long_mask: a mask of hpd pins that may be long hpd pulses
1535 *
1536 * This is the main hotplug irq handler for all platforms. The platform specific
1537 * irq handlers call the platform specific hotplug irq handlers, which read and
1538 * decode the appropriate registers into bitmasks about hpd pins that have
1539 * triggered (@pin_mask), and which of those pins may be long pulses
1540 * (@long_mask). The @long_mask is ignored if the port corresponding to the pin
1541 * is not a digital port.
1542 *
1543 * Here, we do hotplug irq storm detection and mitigation, and pass further
1544 * processing to appropriate bottom halves.
1545 */
1546 static void intel_hpd_irq_handler(struct drm_device *dev,
1547 u32 pin_mask, u32 long_mask)
1548 {
1549 struct drm_i915_private *dev_priv = dev->dev_private;
1550 int i;
1551 enum port port;
1552 bool storm_detected = false;
1553 bool queue_dig = false, queue_hp = false;
1554 bool is_dig_port;
1555
1556 if (!pin_mask)
1557 return;
1558
1559 spin_lock(&dev_priv->irq_lock);
1560 for_each_hpd_pin(i) {
1561 if (!(BIT(i) & pin_mask))
1562 continue;
1563
1564 port = get_port_from_pin(i);
1565 is_dig_port = port && dev_priv->hotplug.irq_port[port];
1566
1567 if (is_dig_port) {
1568 bool long_hpd = long_mask & BIT(i);
1569
1570 DRM_DEBUG_DRIVER("digital hpd port %c - %s\n", port_name(port),
1571 long_hpd ? "long" : "short");
1572 /*
1573 * For long HPD pulses we want to have the digital queue happen,
1574 * but we still want HPD storm detection to function.
1575 */
1576 queue_dig = true;
1577 if (long_hpd) {
1578 dev_priv->hotplug.long_port_mask |= (1 << port);
1579 } else {
1580 /* for short HPD just trigger the digital queue */
1581 dev_priv->hotplug.short_port_mask |= (1 << port);
1582 continue;
1583 }
1584 }
1585
1586 if (dev_priv->hotplug.stats[i].state == HPD_DISABLED) {
1587 /*
1588 * On GMCH platforms the interrupt mask bits only
1589 * prevent irq generation, not the setting of the
1590 * hotplug bits itself. So only WARN about unexpected
1591 * interrupts on saner platforms.
1592 */
1593 WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
1594 "Received HPD interrupt on pin %d although disabled\n", i);
1595 continue;
1596 }
1597
1598 if (dev_priv->hotplug.stats[i].state != HPD_ENABLED)
1599 continue;
1600
1601 if (!is_dig_port) {
1602 dev_priv->hotplug.event_bits |= BIT(i);
1603 queue_hp = true;
1604 }
1605
1606 if (intel_hpd_irq_storm(dev_priv, i)) {
1607 dev_priv->hotplug.event_bits &= ~BIT(i);
1608 storm_detected = true;
1609 }
1610 }
1611
1612 if (storm_detected)
1613 dev_priv->display.hpd_irq_setup(dev);
1614 spin_unlock(&dev_priv->irq_lock);
1615
1616 /*
1617 * Our hotplug handler can grab modeset locks (by calling down into the
1618 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1619 * queue for otherwise the flush_work in the pageflip code will
1620 * deadlock.
1621 */
1622 if (queue_dig)
1623 queue_work(dev_priv->hotplug.dp_wq, &dev_priv->hotplug.dig_port_work);
1624 if (queue_hp)
1625 schedule_work(&dev_priv->hotplug.hotplug_work);
1626 }
1627
1628 static void gmbus_irq_handler(struct drm_device *dev)
1629 {
1630 struct drm_i915_private *dev_priv = dev->dev_private;
1631
1632 wake_up_all(&dev_priv->gmbus_wait_queue);
1633 }
1634
1635 static void dp_aux_irq_handler(struct drm_device *dev)
1636 {
1637 struct drm_i915_private *dev_priv = dev->dev_private;
1638
1639 wake_up_all(&dev_priv->gmbus_wait_queue);
1640 }
1641
1642 #if defined(CONFIG_DEBUG_FS)
1643 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1644 uint32_t crc0, uint32_t crc1,
1645 uint32_t crc2, uint32_t crc3,
1646 uint32_t crc4)
1647 {
1648 struct drm_i915_private *dev_priv = dev->dev_private;
1649 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1650 struct intel_pipe_crc_entry *entry;
1651 int head, tail;
1652
1653 spin_lock(&pipe_crc->lock);
1654
1655 if (!pipe_crc->entries) {
1656 spin_unlock(&pipe_crc->lock);
1657 DRM_DEBUG_KMS("spurious interrupt\n");
1658 return;
1659 }
1660
1661 head = pipe_crc->head;
1662 tail = pipe_crc->tail;
1663
1664 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1665 spin_unlock(&pipe_crc->lock);
1666 DRM_ERROR("CRC buffer overflowing\n");
1667 return;
1668 }
1669
1670 entry = &pipe_crc->entries[head];
1671
1672 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1673 entry->crc[0] = crc0;
1674 entry->crc[1] = crc1;
1675 entry->crc[2] = crc2;
1676 entry->crc[3] = crc3;
1677 entry->crc[4] = crc4;
1678
1679 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1680 pipe_crc->head = head;
1681
1682 spin_unlock(&pipe_crc->lock);
1683
1684 wake_up_interruptible(&pipe_crc->wq);
1685 }
1686 #else
1687 static inline void
1688 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1689 uint32_t crc0, uint32_t crc1,
1690 uint32_t crc2, uint32_t crc3,
1691 uint32_t crc4) {}
1692 #endif
1693
1694
1695 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1696 {
1697 struct drm_i915_private *dev_priv = dev->dev_private;
1698
1699 display_pipe_crc_irq_handler(dev, pipe,
1700 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1701 0, 0, 0, 0);
1702 }
1703
1704 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1705 {
1706 struct drm_i915_private *dev_priv = dev->dev_private;
1707
1708 display_pipe_crc_irq_handler(dev, pipe,
1709 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1710 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1711 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1712 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1713 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1714 }
1715
1716 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1717 {
1718 struct drm_i915_private *dev_priv = dev->dev_private;
1719 uint32_t res1, res2;
1720
1721 if (INTEL_INFO(dev)->gen >= 3)
1722 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1723 else
1724 res1 = 0;
1725
1726 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1727 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1728 else
1729 res2 = 0;
1730
1731 display_pipe_crc_irq_handler(dev, pipe,
1732 I915_READ(PIPE_CRC_RES_RED(pipe)),
1733 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1734 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1735 res1, res2);
1736 }
1737
1738 /* The RPS events need forcewake, so we add them to a work queue and mask their
1739 * IMR bits until the work is done. Other interrupts can be processed without
1740 * the work queue. */
1741 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1742 {
1743 if (pm_iir & dev_priv->pm_rps_events) {
1744 spin_lock(&dev_priv->irq_lock);
1745 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1746 if (dev_priv->rps.interrupts_enabled) {
1747 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1748 queue_work(dev_priv->wq, &dev_priv->rps.work);
1749 }
1750 spin_unlock(&dev_priv->irq_lock);
1751 }
1752
1753 if (INTEL_INFO(dev_priv)->gen >= 8)
1754 return;
1755
1756 if (HAS_VEBOX(dev_priv->dev)) {
1757 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1758 notify_ring(&dev_priv->ring[VECS]);
1759
1760 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1761 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1762 }
1763 }
1764
1765 static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
1766 {
1767 if (!drm_handle_vblank(dev, pipe))
1768 return false;
1769
1770 return true;
1771 }
1772
1773 static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1774 {
1775 struct drm_i915_private *dev_priv = dev->dev_private;
1776 u32 pipe_stats[I915_MAX_PIPES] = { };
1777 int pipe;
1778
1779 spin_lock(&dev_priv->irq_lock);
1780 for_each_pipe(dev_priv, pipe) {
1781 int reg;
1782 u32 mask, iir_bit = 0;
1783
1784 /*
1785 * PIPESTAT bits get signalled even when the interrupt is
1786 * disabled with the mask bits, and some of the status bits do
1787 * not generate interrupts at all (like the underrun bit). Hence
1788 * we need to be careful that we only handle what we want to
1789 * handle.
1790 */
1791
1792 /* fifo underruns are filterered in the underrun handler. */
1793 mask = PIPE_FIFO_UNDERRUN_STATUS;
1794
1795 switch (pipe) {
1796 case PIPE_A:
1797 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1798 break;
1799 case PIPE_B:
1800 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1801 break;
1802 case PIPE_C:
1803 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1804 break;
1805 }
1806 if (iir & iir_bit)
1807 mask |= dev_priv->pipestat_irq_mask[pipe];
1808
1809 if (!mask)
1810 continue;
1811
1812 reg = PIPESTAT(pipe);
1813 mask |= PIPESTAT_INT_ENABLE_MASK;
1814 pipe_stats[pipe] = I915_READ(reg) & mask;
1815
1816 /*
1817 * Clear the PIPE*STAT regs before the IIR
1818 */
1819 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1820 PIPESTAT_INT_STATUS_MASK))
1821 I915_WRITE(reg, pipe_stats[pipe]);
1822 }
1823 spin_unlock(&dev_priv->irq_lock);
1824
1825 for_each_pipe(dev_priv, pipe) {
1826 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1827 intel_pipe_handle_vblank(dev, pipe))
1828 intel_check_page_flip(dev, pipe);
1829
1830 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
1831 intel_prepare_page_flip(dev, pipe);
1832 intel_finish_page_flip(dev, pipe);
1833 }
1834
1835 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1836 i9xx_pipe_crc_irq_handler(dev, pipe);
1837
1838 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1839 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1840 }
1841
1842 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1843 gmbus_irq_handler(dev);
1844 }
1845
1846 static void i9xx_hpd_irq_handler(struct drm_device *dev)
1847 {
1848 struct drm_i915_private *dev_priv = dev->dev_private;
1849 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1850 u32 pin_mask, long_mask;
1851
1852 if (!hotplug_status)
1853 return;
1854
1855 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1856 /*
1857 * Make sure hotplug status is cleared before we clear IIR, or else we
1858 * may miss hotplug events.
1859 */
1860 POSTING_READ(PORT_HOTPLUG_STAT);
1861
1862 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
1863 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1864
1865 i9xx_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, hpd_status_g4x);
1866 intel_hpd_irq_handler(dev, pin_mask, long_mask);
1867
1868 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1869 dp_aux_irq_handler(dev);
1870 } else {
1871 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1872
1873 i9xx_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, hpd_status_i915);
1874 intel_hpd_irq_handler(dev, pin_mask, long_mask);
1875 }
1876 }
1877
1878 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1879 {
1880 struct drm_device *dev = arg;
1881 struct drm_i915_private *dev_priv = dev->dev_private;
1882 u32 iir, gt_iir, pm_iir;
1883 irqreturn_t ret = IRQ_NONE;
1884
1885 if (!intel_irqs_enabled(dev_priv))
1886 return IRQ_NONE;
1887
1888 while (true) {
1889 /* Find, clear, then process each source of interrupt */
1890
1891 gt_iir = I915_READ(GTIIR);
1892 if (gt_iir)
1893 I915_WRITE(GTIIR, gt_iir);
1894
1895 pm_iir = I915_READ(GEN6_PMIIR);
1896 if (pm_iir)
1897 I915_WRITE(GEN6_PMIIR, pm_iir);
1898
1899 iir = I915_READ(VLV_IIR);
1900 if (iir) {
1901 /* Consume port before clearing IIR or we'll miss events */
1902 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1903 i9xx_hpd_irq_handler(dev);
1904 I915_WRITE(VLV_IIR, iir);
1905 }
1906
1907 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1908 goto out;
1909
1910 ret = IRQ_HANDLED;
1911
1912 if (gt_iir)
1913 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1914 if (pm_iir)
1915 gen6_rps_irq_handler(dev_priv, pm_iir);
1916 /* Call regardless, as some status bits might not be
1917 * signalled in iir */
1918 valleyview_pipestat_irq_handler(dev, iir);
1919 }
1920
1921 out:
1922 return ret;
1923 }
1924
1925 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1926 {
1927 struct drm_device *dev = arg;
1928 struct drm_i915_private *dev_priv = dev->dev_private;
1929 u32 master_ctl, iir;
1930 irqreturn_t ret = IRQ_NONE;
1931
1932 if (!intel_irqs_enabled(dev_priv))
1933 return IRQ_NONE;
1934
1935 for (;;) {
1936 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1937 iir = I915_READ(VLV_IIR);
1938
1939 if (master_ctl == 0 && iir == 0)
1940 break;
1941
1942 ret = IRQ_HANDLED;
1943
1944 I915_WRITE(GEN8_MASTER_IRQ, 0);
1945
1946 /* Find, clear, then process each source of interrupt */
1947
1948 if (iir) {
1949 /* Consume port before clearing IIR or we'll miss events */
1950 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1951 i9xx_hpd_irq_handler(dev);
1952 I915_WRITE(VLV_IIR, iir);
1953 }
1954
1955 gen8_gt_irq_handler(dev_priv, master_ctl);
1956
1957 /* Call regardless, as some status bits might not be
1958 * signalled in iir */
1959 valleyview_pipestat_irq_handler(dev, iir);
1960
1961 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
1962 POSTING_READ(GEN8_MASTER_IRQ);
1963 }
1964
1965 return ret;
1966 }
1967
1968 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1969 {
1970 struct drm_i915_private *dev_priv = dev->dev_private;
1971 int pipe;
1972 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1973 u32 dig_hotplug_reg;
1974 u32 pin_mask, long_mask;
1975
1976 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1977 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1978
1979 pch_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, dig_hotplug_reg, hpd_ibx);
1980 intel_hpd_irq_handler(dev, pin_mask, long_mask);
1981
1982 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1983 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1984 SDE_AUDIO_POWER_SHIFT);
1985 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1986 port_name(port));
1987 }
1988
1989 if (pch_iir & SDE_AUX_MASK)
1990 dp_aux_irq_handler(dev);
1991
1992 if (pch_iir & SDE_GMBUS)
1993 gmbus_irq_handler(dev);
1994
1995 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1996 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1997
1998 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1999 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
2000
2001 if (pch_iir & SDE_POISON)
2002 DRM_ERROR("PCH poison interrupt\n");
2003
2004 if (pch_iir & SDE_FDI_MASK)
2005 for_each_pipe(dev_priv, pipe)
2006 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2007 pipe_name(pipe),
2008 I915_READ(FDI_RX_IIR(pipe)));
2009
2010 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
2011 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
2012
2013 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
2014 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
2015
2016 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
2017 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2018
2019 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
2020 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2021 }
2022
2023 static void ivb_err_int_handler(struct drm_device *dev)
2024 {
2025 struct drm_i915_private *dev_priv = dev->dev_private;
2026 u32 err_int = I915_READ(GEN7_ERR_INT);
2027 enum pipe pipe;
2028
2029 if (err_int & ERR_INT_POISON)
2030 DRM_ERROR("Poison interrupt\n");
2031
2032 for_each_pipe(dev_priv, pipe) {
2033 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
2034 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2035
2036 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
2037 if (IS_IVYBRIDGE(dev))
2038 ivb_pipe_crc_irq_handler(dev, pipe);
2039 else
2040 hsw_pipe_crc_irq_handler(dev, pipe);
2041 }
2042 }
2043
2044 I915_WRITE(GEN7_ERR_INT, err_int);
2045 }
2046
2047 static void cpt_serr_int_handler(struct drm_device *dev)
2048 {
2049 struct drm_i915_private *dev_priv = dev->dev_private;
2050 u32 serr_int = I915_READ(SERR_INT);
2051
2052 if (serr_int & SERR_INT_POISON)
2053 DRM_ERROR("PCH poison interrupt\n");
2054
2055 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2056 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2057
2058 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2059 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2060
2061 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2062 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
2063
2064 I915_WRITE(SERR_INT, serr_int);
2065 }
2066
2067 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
2068 {
2069 struct drm_i915_private *dev_priv = dev->dev_private;
2070 int pipe;
2071 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2072 u32 dig_hotplug_reg;
2073 u32 pin_mask, long_mask;
2074
2075 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2076 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2077
2078 pch_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, dig_hotplug_reg, hpd_cpt);
2079 intel_hpd_irq_handler(dev, pin_mask, long_mask);
2080
2081 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2082 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2083 SDE_AUDIO_POWER_SHIFT_CPT);
2084 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2085 port_name(port));
2086 }
2087
2088 if (pch_iir & SDE_AUX_MASK_CPT)
2089 dp_aux_irq_handler(dev);
2090
2091 if (pch_iir & SDE_GMBUS_CPT)
2092 gmbus_irq_handler(dev);
2093
2094 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2095 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2096
2097 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2098 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2099
2100 if (pch_iir & SDE_FDI_MASK_CPT)
2101 for_each_pipe(dev_priv, pipe)
2102 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2103 pipe_name(pipe),
2104 I915_READ(FDI_RX_IIR(pipe)));
2105
2106 if (pch_iir & SDE_ERROR_CPT)
2107 cpt_serr_int_handler(dev);
2108 }
2109
2110 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
2111 {
2112 struct drm_i915_private *dev_priv = dev->dev_private;
2113 enum pipe pipe;
2114
2115 if (de_iir & DE_AUX_CHANNEL_A)
2116 dp_aux_irq_handler(dev);
2117
2118 if (de_iir & DE_GSE)
2119 intel_opregion_asle_intr(dev);
2120
2121 if (de_iir & DE_POISON)
2122 DRM_ERROR("Poison interrupt\n");
2123
2124 for_each_pipe(dev_priv, pipe) {
2125 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2126 intel_pipe_handle_vblank(dev, pipe))
2127 intel_check_page_flip(dev, pipe);
2128
2129 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2130 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2131
2132 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2133 i9xx_pipe_crc_irq_handler(dev, pipe);
2134
2135 /* plane/pipes map 1:1 on ilk+ */
2136 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
2137 intel_prepare_page_flip(dev, pipe);
2138 intel_finish_page_flip_plane(dev, pipe);
2139 }
2140 }
2141
2142 /* check event from PCH */
2143 if (de_iir & DE_PCH_EVENT) {
2144 u32 pch_iir = I915_READ(SDEIIR);
2145
2146 if (HAS_PCH_CPT(dev))
2147 cpt_irq_handler(dev, pch_iir);
2148 else
2149 ibx_irq_handler(dev, pch_iir);
2150
2151 /* should clear PCH hotplug event before clear CPU irq */
2152 I915_WRITE(SDEIIR, pch_iir);
2153 }
2154
2155 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
2156 ironlake_rps_change_irq_handler(dev);
2157 }
2158
2159 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
2160 {
2161 struct drm_i915_private *dev_priv = dev->dev_private;
2162 enum pipe pipe;
2163
2164 if (de_iir & DE_ERR_INT_IVB)
2165 ivb_err_int_handler(dev);
2166
2167 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2168 dp_aux_irq_handler(dev);
2169
2170 if (de_iir & DE_GSE_IVB)
2171 intel_opregion_asle_intr(dev);
2172
2173 for_each_pipe(dev_priv, pipe) {
2174 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2175 intel_pipe_handle_vblank(dev, pipe))
2176 intel_check_page_flip(dev, pipe);
2177
2178 /* plane/pipes map 1:1 on ilk+ */
2179 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
2180 intel_prepare_page_flip(dev, pipe);
2181 intel_finish_page_flip_plane(dev, pipe);
2182 }
2183 }
2184
2185 /* check event from PCH */
2186 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
2187 u32 pch_iir = I915_READ(SDEIIR);
2188
2189 cpt_irq_handler(dev, pch_iir);
2190
2191 /* clear PCH hotplug event before clear CPU irq */
2192 I915_WRITE(SDEIIR, pch_iir);
2193 }
2194 }
2195
2196 /*
2197 * To handle irqs with the minimum potential races with fresh interrupts, we:
2198 * 1 - Disable Master Interrupt Control.
2199 * 2 - Find the source(s) of the interrupt.
2200 * 3 - Clear the Interrupt Identity bits (IIR).
2201 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2202 * 5 - Re-enable Master Interrupt Control.
2203 */
2204 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2205 {
2206 struct drm_device *dev = arg;
2207 struct drm_i915_private *dev_priv = dev->dev_private;
2208 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2209 irqreturn_t ret = IRQ_NONE;
2210
2211 if (!intel_irqs_enabled(dev_priv))
2212 return IRQ_NONE;
2213
2214 /* We get interrupts on unclaimed registers, so check for this before we
2215 * do any I915_{READ,WRITE}. */
2216 intel_uncore_check_errors(dev);
2217
2218 /* disable master interrupt before clearing iir */
2219 de_ier = I915_READ(DEIER);
2220 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2221 POSTING_READ(DEIER);
2222
2223 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2224 * interrupts will will be stored on its back queue, and then we'll be
2225 * able to process them after we restore SDEIER (as soon as we restore
2226 * it, we'll get an interrupt if SDEIIR still has something to process
2227 * due to its back queue). */
2228 if (!HAS_PCH_NOP(dev)) {
2229 sde_ier = I915_READ(SDEIER);
2230 I915_WRITE(SDEIER, 0);
2231 POSTING_READ(SDEIER);
2232 }
2233
2234 /* Find, clear, then process each source of interrupt */
2235
2236 gt_iir = I915_READ(GTIIR);
2237 if (gt_iir) {
2238 I915_WRITE(GTIIR, gt_iir);
2239 ret = IRQ_HANDLED;
2240 if (INTEL_INFO(dev)->gen >= 6)
2241 snb_gt_irq_handler(dev, dev_priv, gt_iir);
2242 else
2243 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
2244 }
2245
2246 de_iir = I915_READ(DEIIR);
2247 if (de_iir) {
2248 I915_WRITE(DEIIR, de_iir);
2249 ret = IRQ_HANDLED;
2250 if (INTEL_INFO(dev)->gen >= 7)
2251 ivb_display_irq_handler(dev, de_iir);
2252 else
2253 ilk_display_irq_handler(dev, de_iir);
2254 }
2255
2256 if (INTEL_INFO(dev)->gen >= 6) {
2257 u32 pm_iir = I915_READ(GEN6_PMIIR);
2258 if (pm_iir) {
2259 I915_WRITE(GEN6_PMIIR, pm_iir);
2260 ret = IRQ_HANDLED;
2261 gen6_rps_irq_handler(dev_priv, pm_iir);
2262 }
2263 }
2264
2265 I915_WRITE(DEIER, de_ier);
2266 POSTING_READ(DEIER);
2267 if (!HAS_PCH_NOP(dev)) {
2268 I915_WRITE(SDEIER, sde_ier);
2269 POSTING_READ(SDEIER);
2270 }
2271
2272 return ret;
2273 }
2274
2275 static void bxt_hpd_handler(struct drm_device *dev, uint32_t iir_status)
2276 {
2277 struct drm_i915_private *dev_priv = dev->dev_private;
2278 u32 hp_control, hp_trigger;
2279 u32 pin_mask, long_mask;
2280
2281 /* Get the status */
2282 hp_trigger = iir_status & BXT_DE_PORT_HOTPLUG_MASK;
2283 hp_control = I915_READ(BXT_HOTPLUG_CTL);
2284
2285 /* Hotplug not enabled ? */
2286 if (!(hp_control & BXT_HOTPLUG_CTL_MASK)) {
2287 DRM_ERROR("Interrupt when HPD disabled\n");
2288 return;
2289 }
2290
2291 /* Clear sticky bits in hpd status */
2292 I915_WRITE(BXT_HOTPLUG_CTL, hp_control);
2293
2294 pch_get_hpd_pins(&pin_mask, &long_mask, hp_trigger, hp_control, hpd_bxt);
2295 intel_hpd_irq_handler(dev, pin_mask, long_mask);
2296 }
2297
2298 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2299 {
2300 struct drm_device *dev = arg;
2301 struct drm_i915_private *dev_priv = dev->dev_private;
2302 u32 master_ctl;
2303 irqreturn_t ret = IRQ_NONE;
2304 uint32_t tmp = 0;
2305 enum pipe pipe;
2306 u32 aux_mask = GEN8_AUX_CHANNEL_A;
2307
2308 if (!intel_irqs_enabled(dev_priv))
2309 return IRQ_NONE;
2310
2311 if (IS_GEN9(dev))
2312 aux_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
2313 GEN9_AUX_CHANNEL_D;
2314
2315 master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
2316 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2317 if (!master_ctl)
2318 return IRQ_NONE;
2319
2320 I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
2321
2322 /* Find, clear, then process each source of interrupt */
2323
2324 ret = gen8_gt_irq_handler(dev_priv, master_ctl);
2325
2326 if (master_ctl & GEN8_DE_MISC_IRQ) {
2327 tmp = I915_READ(GEN8_DE_MISC_IIR);
2328 if (tmp) {
2329 I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2330 ret = IRQ_HANDLED;
2331 if (tmp & GEN8_DE_MISC_GSE)
2332 intel_opregion_asle_intr(dev);
2333 else
2334 DRM_ERROR("Unexpected DE Misc interrupt\n");
2335 }
2336 else
2337 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2338 }
2339
2340 if (master_ctl & GEN8_DE_PORT_IRQ) {
2341 tmp = I915_READ(GEN8_DE_PORT_IIR);
2342 if (tmp) {
2343 bool found = false;
2344
2345 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2346 ret = IRQ_HANDLED;
2347
2348 if (tmp & aux_mask) {
2349 dp_aux_irq_handler(dev);
2350 found = true;
2351 }
2352
2353 if (IS_BROXTON(dev) && tmp & BXT_DE_PORT_HOTPLUG_MASK) {
2354 bxt_hpd_handler(dev, tmp);
2355 found = true;
2356 }
2357
2358 if (IS_BROXTON(dev) && (tmp & BXT_DE_PORT_GMBUS)) {
2359 gmbus_irq_handler(dev);
2360 found = true;
2361 }
2362
2363 if (!found)
2364 DRM_ERROR("Unexpected DE Port interrupt\n");
2365 }
2366 else
2367 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2368 }
2369
2370 for_each_pipe(dev_priv, pipe) {
2371 uint32_t pipe_iir, flip_done = 0, fault_errors = 0;
2372
2373 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2374 continue;
2375
2376 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2377 if (pipe_iir) {
2378 ret = IRQ_HANDLED;
2379 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2380
2381 if (pipe_iir & GEN8_PIPE_VBLANK &&
2382 intel_pipe_handle_vblank(dev, pipe))
2383 intel_check_page_flip(dev, pipe);
2384
2385 if (IS_GEN9(dev))
2386 flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE;
2387 else
2388 flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE;
2389
2390 if (flip_done) {
2391 intel_prepare_page_flip(dev, pipe);
2392 intel_finish_page_flip_plane(dev, pipe);
2393 }
2394
2395 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2396 hsw_pipe_crc_irq_handler(dev, pipe);
2397
2398 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN)
2399 intel_cpu_fifo_underrun_irq_handler(dev_priv,
2400 pipe);
2401
2402
2403 if (IS_GEN9(dev))
2404 fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2405 else
2406 fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2407
2408 if (fault_errors)
2409 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2410 pipe_name(pipe),
2411 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2412 } else
2413 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2414 }
2415
2416 if (HAS_PCH_SPLIT(dev) && !HAS_PCH_NOP(dev) &&
2417 master_ctl & GEN8_DE_PCH_IRQ) {
2418 /*
2419 * FIXME(BDW): Assume for now that the new interrupt handling
2420 * scheme also closed the SDE interrupt handling race we've seen
2421 * on older pch-split platforms. But this needs testing.
2422 */
2423 u32 pch_iir = I915_READ(SDEIIR);
2424 if (pch_iir) {
2425 I915_WRITE(SDEIIR, pch_iir);
2426 ret = IRQ_HANDLED;
2427 cpt_irq_handler(dev, pch_iir);
2428 } else
2429 DRM_ERROR("The master control interrupt lied (SDE)!\n");
2430
2431 }
2432
2433 I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2434 POSTING_READ_FW(GEN8_MASTER_IRQ);
2435
2436 return ret;
2437 }
2438
2439 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2440 bool reset_completed)
2441 {
2442 struct intel_engine_cs *ring;
2443 int i;
2444
2445 /*
2446 * Notify all waiters for GPU completion events that reset state has
2447 * been changed, and that they need to restart their wait after
2448 * checking for potential errors (and bail out to drop locks if there is
2449 * a gpu reset pending so that i915_error_work_func can acquire them).
2450 */
2451
2452 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2453 for_each_ring(ring, dev_priv, i)
2454 wake_up_all(&ring->irq_queue);
2455
2456 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2457 wake_up_all(&dev_priv->pending_flip_queue);
2458
2459 /*
2460 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2461 * reset state is cleared.
2462 */
2463 if (reset_completed)
2464 wake_up_all(&dev_priv->gpu_error.reset_queue);
2465 }
2466
2467 /**
2468 * i915_reset_and_wakeup - do process context error handling work
2469 *
2470 * Fire an error uevent so userspace can see that a hang or error
2471 * was detected.
2472 */
2473 static void i915_reset_and_wakeup(struct drm_device *dev)
2474 {
2475 struct drm_i915_private *dev_priv = to_i915(dev);
2476 struct i915_gpu_error *error = &dev_priv->gpu_error;
2477 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2478 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2479 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2480 int ret;
2481
2482 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2483
2484 /*
2485 * Note that there's only one work item which does gpu resets, so we
2486 * need not worry about concurrent gpu resets potentially incrementing
2487 * error->reset_counter twice. We only need to take care of another
2488 * racing irq/hangcheck declaring the gpu dead for a second time. A
2489 * quick check for that is good enough: schedule_work ensures the
2490 * correct ordering between hang detection and this work item, and since
2491 * the reset in-progress bit is only ever set by code outside of this
2492 * work we don't need to worry about any other races.
2493 */
2494 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2495 DRM_DEBUG_DRIVER("resetting chip\n");
2496 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2497 reset_event);
2498
2499 /*
2500 * In most cases it's guaranteed that we get here with an RPM
2501 * reference held, for example because there is a pending GPU
2502 * request that won't finish until the reset is done. This
2503 * isn't the case at least when we get here by doing a
2504 * simulated reset via debugs, so get an RPM reference.
2505 */
2506 intel_runtime_pm_get(dev_priv);
2507
2508 intel_prepare_reset(dev);
2509
2510 /*
2511 * All state reset _must_ be completed before we update the
2512 * reset counter, for otherwise waiters might miss the reset
2513 * pending state and not properly drop locks, resulting in
2514 * deadlocks with the reset work.
2515 */
2516 ret = i915_reset(dev);
2517
2518 intel_finish_reset(dev);
2519
2520 intel_runtime_pm_put(dev_priv);
2521
2522 if (ret == 0) {
2523 /*
2524 * After all the gem state is reset, increment the reset
2525 * counter and wake up everyone waiting for the reset to
2526 * complete.
2527 *
2528 * Since unlock operations are a one-sided barrier only,
2529 * we need to insert a barrier here to order any seqno
2530 * updates before
2531 * the counter increment.
2532 */
2533 smp_mb__before_atomic();
2534 atomic_inc(&dev_priv->gpu_error.reset_counter);
2535
2536 kobject_uevent_env(&dev->primary->kdev->kobj,
2537 KOBJ_CHANGE, reset_done_event);
2538 } else {
2539 atomic_set_mask(I915_WEDGED, &error->reset_counter);
2540 }
2541
2542 /*
2543 * Note: The wake_up also serves as a memory barrier so that
2544 * waiters see the update value of the reset counter atomic_t.
2545 */
2546 i915_error_wake_up(dev_priv, true);
2547 }
2548 }
2549
2550 static void i915_report_and_clear_eir(struct drm_device *dev)
2551 {
2552 struct drm_i915_private *dev_priv = dev->dev_private;
2553 uint32_t instdone[I915_NUM_INSTDONE_REG];
2554 u32 eir = I915_READ(EIR);
2555 int pipe, i;
2556
2557 if (!eir)
2558 return;
2559
2560 pr_err("render error detected, EIR: 0x%08x\n", eir);
2561
2562 i915_get_extra_instdone(dev, instdone);
2563
2564 if (IS_G4X(dev)) {
2565 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2566 u32 ipeir = I915_READ(IPEIR_I965);
2567
2568 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2569 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2570 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2571 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2572 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2573 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2574 I915_WRITE(IPEIR_I965, ipeir);
2575 POSTING_READ(IPEIR_I965);
2576 }
2577 if (eir & GM45_ERROR_PAGE_TABLE) {
2578 u32 pgtbl_err = I915_READ(PGTBL_ER);
2579 pr_err("page table error\n");
2580 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2581 I915_WRITE(PGTBL_ER, pgtbl_err);
2582 POSTING_READ(PGTBL_ER);
2583 }
2584 }
2585
2586 if (!IS_GEN2(dev)) {
2587 if (eir & I915_ERROR_PAGE_TABLE) {
2588 u32 pgtbl_err = I915_READ(PGTBL_ER);
2589 pr_err("page table error\n");
2590 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2591 I915_WRITE(PGTBL_ER, pgtbl_err);
2592 POSTING_READ(PGTBL_ER);
2593 }
2594 }
2595
2596 if (eir & I915_ERROR_MEMORY_REFRESH) {
2597 pr_err("memory refresh error:\n");
2598 for_each_pipe(dev_priv, pipe)
2599 pr_err("pipe %c stat: 0x%08x\n",
2600 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2601 /* pipestat has already been acked */
2602 }
2603 if (eir & I915_ERROR_INSTRUCTION) {
2604 pr_err("instruction error\n");
2605 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
2606 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2607 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2608 if (INTEL_INFO(dev)->gen < 4) {
2609 u32 ipeir = I915_READ(IPEIR);
2610
2611 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2612 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
2613 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
2614 I915_WRITE(IPEIR, ipeir);
2615 POSTING_READ(IPEIR);
2616 } else {
2617 u32 ipeir = I915_READ(IPEIR_I965);
2618
2619 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2620 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2621 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2622 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2623 I915_WRITE(IPEIR_I965, ipeir);
2624 POSTING_READ(IPEIR_I965);
2625 }
2626 }
2627
2628 I915_WRITE(EIR, eir);
2629 POSTING_READ(EIR);
2630 eir = I915_READ(EIR);
2631 if (eir) {
2632 /*
2633 * some errors might have become stuck,
2634 * mask them.
2635 */
2636 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2637 I915_WRITE(EMR, I915_READ(EMR) | eir);
2638 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2639 }
2640 }
2641
2642 /**
2643 * i915_handle_error - handle a gpu error
2644 * @dev: drm device
2645 *
2646 * Do some basic checking of regsiter state at error time and
2647 * dump it to the syslog. Also call i915_capture_error_state() to make
2648 * sure we get a record and make it available in debugfs. Fire a uevent
2649 * so userspace knows something bad happened (should trigger collection
2650 * of a ring dump etc.).
2651 */
2652 void i915_handle_error(struct drm_device *dev, bool wedged,
2653 const char *fmt, ...)
2654 {
2655 struct drm_i915_private *dev_priv = dev->dev_private;
2656 va_list args;
2657 char error_msg[80];
2658
2659 va_start(args, fmt);
2660 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2661 va_end(args);
2662
2663 i915_capture_error_state(dev, wedged, error_msg);
2664 i915_report_and_clear_eir(dev);
2665
2666 if (wedged) {
2667 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2668 &dev_priv->gpu_error.reset_counter);
2669
2670 /*
2671 * Wakeup waiting processes so that the reset function
2672 * i915_reset_and_wakeup doesn't deadlock trying to grab
2673 * various locks. By bumping the reset counter first, the woken
2674 * processes will see a reset in progress and back off,
2675 * releasing their locks and then wait for the reset completion.
2676 * We must do this for _all_ gpu waiters that might hold locks
2677 * that the reset work needs to acquire.
2678 *
2679 * Note: The wake_up serves as the required memory barrier to
2680 * ensure that the waiters see the updated value of the reset
2681 * counter atomic_t.
2682 */
2683 i915_error_wake_up(dev_priv, false);
2684 }
2685
2686 i915_reset_and_wakeup(dev);
2687 }
2688
2689 /* Called from drm generic code, passed 'crtc' which
2690 * we use as a pipe index
2691 */
2692 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2693 {
2694 struct drm_i915_private *dev_priv = dev->dev_private;
2695 unsigned long irqflags;
2696
2697 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2698 if (INTEL_INFO(dev)->gen >= 4)
2699 i915_enable_pipestat(dev_priv, pipe,
2700 PIPE_START_VBLANK_INTERRUPT_STATUS);
2701 else
2702 i915_enable_pipestat(dev_priv, pipe,
2703 PIPE_VBLANK_INTERRUPT_STATUS);
2704 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2705
2706 return 0;
2707 }
2708
2709 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2710 {
2711 struct drm_i915_private *dev_priv = dev->dev_private;
2712 unsigned long irqflags;
2713 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2714 DE_PIPE_VBLANK(pipe);
2715
2716 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2717 ironlake_enable_display_irq(dev_priv, bit);
2718 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2719
2720 return 0;
2721 }
2722
2723 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2724 {
2725 struct drm_i915_private *dev_priv = dev->dev_private;
2726 unsigned long irqflags;
2727
2728 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2729 i915_enable_pipestat(dev_priv, pipe,
2730 PIPE_START_VBLANK_INTERRUPT_STATUS);
2731 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2732
2733 return 0;
2734 }
2735
2736 static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2737 {
2738 struct drm_i915_private *dev_priv = dev->dev_private;
2739 unsigned long irqflags;
2740
2741 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2742 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2743 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2744 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2745 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2746 return 0;
2747 }
2748
2749 /* Called from drm generic code, passed 'crtc' which
2750 * we use as a pipe index
2751 */
2752 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2753 {
2754 struct drm_i915_private *dev_priv = dev->dev_private;
2755 unsigned long irqflags;
2756
2757 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2758 i915_disable_pipestat(dev_priv, pipe,
2759 PIPE_VBLANK_INTERRUPT_STATUS |
2760 PIPE_START_VBLANK_INTERRUPT_STATUS);
2761 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2762 }
2763
2764 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2765 {
2766 struct drm_i915_private *dev_priv = dev->dev_private;
2767 unsigned long irqflags;
2768 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2769 DE_PIPE_VBLANK(pipe);
2770
2771 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2772 ironlake_disable_display_irq(dev_priv, bit);
2773 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2774 }
2775
2776 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2777 {
2778 struct drm_i915_private *dev_priv = dev->dev_private;
2779 unsigned long irqflags;
2780
2781 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2782 i915_disable_pipestat(dev_priv, pipe,
2783 PIPE_START_VBLANK_INTERRUPT_STATUS);
2784 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2785 }
2786
2787 static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2788 {
2789 struct drm_i915_private *dev_priv = dev->dev_private;
2790 unsigned long irqflags;
2791
2792 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2793 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2794 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2795 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2796 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2797 }
2798
2799 static struct drm_i915_gem_request *
2800 ring_last_request(struct intel_engine_cs *ring)
2801 {
2802 return list_entry(ring->request_list.prev,
2803 struct drm_i915_gem_request, list);
2804 }
2805
2806 static bool
2807 ring_idle(struct intel_engine_cs *ring)
2808 {
2809 return (list_empty(&ring->request_list) ||
2810 i915_gem_request_completed(ring_last_request(ring), false));
2811 }
2812
2813 static bool
2814 ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
2815 {
2816 if (INTEL_INFO(dev)->gen >= 8) {
2817 return (ipehr >> 23) == 0x1c;
2818 } else {
2819 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2820 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2821 MI_SEMAPHORE_REGISTER);
2822 }
2823 }
2824
2825 static struct intel_engine_cs *
2826 semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset)
2827 {
2828 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2829 struct intel_engine_cs *signaller;
2830 int i;
2831
2832 if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
2833 for_each_ring(signaller, dev_priv, i) {
2834 if (ring == signaller)
2835 continue;
2836
2837 if (offset == signaller->semaphore.signal_ggtt[ring->id])
2838 return signaller;
2839 }
2840 } else {
2841 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2842
2843 for_each_ring(signaller, dev_priv, i) {
2844 if(ring == signaller)
2845 continue;
2846
2847 if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
2848 return signaller;
2849 }
2850 }
2851
2852 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2853 ring->id, ipehr, offset);
2854
2855 return NULL;
2856 }
2857
2858 static struct intel_engine_cs *
2859 semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
2860 {
2861 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2862 u32 cmd, ipehr, head;
2863 u64 offset = 0;
2864 int i, backwards;
2865
2866 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2867 if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
2868 return NULL;
2869
2870 /*
2871 * HEAD is likely pointing to the dword after the actual command,
2872 * so scan backwards until we find the MBOX. But limit it to just 3
2873 * or 4 dwords depending on the semaphore wait command size.
2874 * Note that we don't care about ACTHD here since that might
2875 * point at at batch, and semaphores are always emitted into the
2876 * ringbuffer itself.
2877 */
2878 head = I915_READ_HEAD(ring) & HEAD_ADDR;
2879 backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4;
2880
2881 for (i = backwards; i; --i) {
2882 /*
2883 * Be paranoid and presume the hw has gone off into the wild -
2884 * our ring is smaller than what the hardware (and hence
2885 * HEAD_ADDR) allows. Also handles wrap-around.
2886 */
2887 head &= ring->buffer->size - 1;
2888
2889 /* This here seems to blow up */
2890 cmd = ioread32(ring->buffer->virtual_start + head);
2891 if (cmd == ipehr)
2892 break;
2893
2894 head -= 4;
2895 }
2896
2897 if (!i)
2898 return NULL;
2899
2900 *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
2901 if (INTEL_INFO(ring->dev)->gen >= 8) {
2902 offset = ioread32(ring->buffer->virtual_start + head + 12);
2903 offset <<= 32;
2904 offset = ioread32(ring->buffer->virtual_start + head + 8);
2905 }
2906 return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
2907 }
2908
2909 static int semaphore_passed(struct intel_engine_cs *ring)
2910 {
2911 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2912 struct intel_engine_cs *signaller;
2913 u32 seqno;
2914
2915 ring->hangcheck.deadlock++;
2916
2917 signaller = semaphore_waits_for(ring, &seqno);
2918 if (signaller == NULL)
2919 return -1;
2920
2921 /* Prevent pathological recursion due to driver bugs */
2922 if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
2923 return -1;
2924
2925 if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
2926 return 1;
2927
2928 /* cursory check for an unkickable deadlock */
2929 if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
2930 semaphore_passed(signaller) < 0)
2931 return -1;
2932
2933 return 0;
2934 }
2935
2936 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2937 {
2938 struct intel_engine_cs *ring;
2939 int i;
2940
2941 for_each_ring(ring, dev_priv, i)
2942 ring->hangcheck.deadlock = 0;
2943 }
2944
2945 static enum intel_ring_hangcheck_action
2946 ring_stuck(struct intel_engine_cs *ring, u64 acthd)
2947 {
2948 struct drm_device *dev = ring->dev;
2949 struct drm_i915_private *dev_priv = dev->dev_private;
2950 u32 tmp;
2951
2952 if (acthd != ring->hangcheck.acthd) {
2953 if (acthd > ring->hangcheck.max_acthd) {
2954 ring->hangcheck.max_acthd = acthd;
2955 return HANGCHECK_ACTIVE;
2956 }
2957
2958 return HANGCHECK_ACTIVE_LOOP;
2959 }
2960
2961 if (IS_GEN2(dev))
2962 return HANGCHECK_HUNG;
2963
2964 /* Is the chip hanging on a WAIT_FOR_EVENT?
2965 * If so we can simply poke the RB_WAIT bit
2966 * and break the hang. This should work on
2967 * all but the second generation chipsets.
2968 */
2969 tmp = I915_READ_CTL(ring);
2970 if (tmp & RING_WAIT) {
2971 i915_handle_error(dev, false,
2972 "Kicking stuck wait on %s",
2973 ring->name);
2974 I915_WRITE_CTL(ring, tmp);
2975 return HANGCHECK_KICK;
2976 }
2977
2978 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2979 switch (semaphore_passed(ring)) {
2980 default:
2981 return HANGCHECK_HUNG;
2982 case 1:
2983 i915_handle_error(dev, false,
2984 "Kicking stuck semaphore on %s",
2985 ring->name);
2986 I915_WRITE_CTL(ring, tmp);
2987 return HANGCHECK_KICK;
2988 case 0:
2989 return HANGCHECK_WAIT;
2990 }
2991 }
2992
2993 return HANGCHECK_HUNG;
2994 }
2995
2996 /*
2997 * This is called when the chip hasn't reported back with completed
2998 * batchbuffers in a long time. We keep track per ring seqno progress and
2999 * if there are no progress, hangcheck score for that ring is increased.
3000 * Further, acthd is inspected to see if the ring is stuck. On stuck case
3001 * we kick the ring. If we see no progress on three subsequent calls
3002 * we assume chip is wedged and try to fix it by resetting the chip.
3003 */
3004 static void i915_hangcheck_elapsed(struct work_struct *work)
3005 {
3006 struct drm_i915_private *dev_priv =
3007 container_of(work, typeof(*dev_priv),
3008 gpu_error.hangcheck_work.work);
3009 struct drm_device *dev = dev_priv->dev;
3010 struct intel_engine_cs *ring;
3011 int i;
3012 int busy_count = 0, rings_hung = 0;
3013 bool stuck[I915_NUM_RINGS] = { 0 };
3014 #define BUSY 1
3015 #define KICK 5
3016 #define HUNG 20
3017
3018 if (!i915.enable_hangcheck)
3019 return;
3020
3021 for_each_ring(ring, dev_priv, i) {
3022 u64 acthd;
3023 u32 seqno;
3024 bool busy = true;
3025
3026 semaphore_clear_deadlocks(dev_priv);
3027
3028 seqno = ring->get_seqno(ring, false);
3029 acthd = intel_ring_get_active_head(ring);
3030
3031 if (ring->hangcheck.seqno == seqno) {
3032 if (ring_idle(ring)) {
3033 ring->hangcheck.action = HANGCHECK_IDLE;
3034
3035 if (waitqueue_active(&ring->irq_queue)) {
3036 /* Issue a wake-up to catch stuck h/w. */
3037 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
3038 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
3039 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
3040 ring->name);
3041 else
3042 DRM_INFO("Fake missed irq on %s\n",
3043 ring->name);
3044 wake_up_all(&ring->irq_queue);
3045 }
3046 /* Safeguard against driver failure */
3047 ring->hangcheck.score += BUSY;
3048 } else
3049 busy = false;
3050 } else {
3051 /* We always increment the hangcheck score
3052 * if the ring is busy and still processing
3053 * the same request, so that no single request
3054 * can run indefinitely (such as a chain of
3055 * batches). The only time we do not increment
3056 * the hangcheck score on this ring, if this
3057 * ring is in a legitimate wait for another
3058 * ring. In that case the waiting ring is a
3059 * victim and we want to be sure we catch the
3060 * right culprit. Then every time we do kick
3061 * the ring, add a small increment to the
3062 * score so that we can catch a batch that is
3063 * being repeatedly kicked and so responsible
3064 * for stalling the machine.
3065 */
3066 ring->hangcheck.action = ring_stuck(ring,
3067 acthd);
3068
3069 switch (ring->hangcheck.action) {
3070 case HANGCHECK_IDLE:
3071 case HANGCHECK_WAIT:
3072 case HANGCHECK_ACTIVE:
3073 break;
3074 case HANGCHECK_ACTIVE_LOOP:
3075 ring->hangcheck.score += BUSY;
3076 break;
3077 case HANGCHECK_KICK:
3078 ring->hangcheck.score += KICK;
3079 break;
3080 case HANGCHECK_HUNG:
3081 ring->hangcheck.score += HUNG;
3082 stuck[i] = true;
3083 break;
3084 }
3085 }
3086 } else {
3087 ring->hangcheck.action = HANGCHECK_ACTIVE;
3088
3089 /* Gradually reduce the count so that we catch DoS
3090 * attempts across multiple batches.
3091 */
3092 if (ring->hangcheck.score > 0)
3093 ring->hangcheck.score--;
3094
3095 ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0;
3096 }
3097
3098 ring->hangcheck.seqno = seqno;
3099 ring->hangcheck.acthd = acthd;
3100 busy_count += busy;
3101 }
3102
3103 for_each_ring(ring, dev_priv, i) {
3104 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3105 DRM_INFO("%s on %s\n",
3106 stuck[i] ? "stuck" : "no progress",
3107 ring->name);
3108 rings_hung++;
3109 }
3110 }
3111
3112 if (rings_hung)
3113 return i915_handle_error(dev, true, "Ring hung");
3114
3115 if (busy_count)
3116 /* Reset timer case chip hangs without another request
3117 * being added */
3118 i915_queue_hangcheck(dev);
3119 }
3120
3121 void i915_queue_hangcheck(struct drm_device *dev)
3122 {
3123 struct i915_gpu_error *e = &to_i915(dev)->gpu_error;
3124
3125 if (!i915.enable_hangcheck)
3126 return;
3127
3128 /* Don't continually defer the hangcheck so that it is always run at
3129 * least once after work has been scheduled on any ring. Otherwise,
3130 * we will ignore a hung ring if a second ring is kept busy.
3131 */
3132
3133 queue_delayed_work(e->hangcheck_wq, &e->hangcheck_work,
3134 round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES));
3135 }
3136
3137 static void ibx_irq_reset(struct drm_device *dev)
3138 {
3139 struct drm_i915_private *dev_priv = dev->dev_private;
3140
3141 if (HAS_PCH_NOP(dev))
3142 return;
3143
3144 GEN5_IRQ_RESET(SDE);
3145
3146 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3147 I915_WRITE(SERR_INT, 0xffffffff);
3148 }
3149
3150 /*
3151 * SDEIER is also touched by the interrupt handler to work around missed PCH
3152 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3153 * instead we unconditionally enable all PCH interrupt sources here, but then
3154 * only unmask them as needed with SDEIMR.
3155 *
3156 * This function needs to be called before interrupts are enabled.
3157 */
3158 static void ibx_irq_pre_postinstall(struct drm_device *dev)
3159 {
3160 struct drm_i915_private *dev_priv = dev->dev_private;
3161
3162 if (HAS_PCH_NOP(dev))
3163 return;
3164
3165 WARN_ON(I915_READ(SDEIER) != 0);
3166 I915_WRITE(SDEIER, 0xffffffff);
3167 POSTING_READ(SDEIER);
3168 }
3169
3170 static void gen5_gt_irq_reset(struct drm_device *dev)
3171 {
3172 struct drm_i915_private *dev_priv = dev->dev_private;
3173
3174 GEN5_IRQ_RESET(GT);
3175 if (INTEL_INFO(dev)->gen >= 6)
3176 GEN5_IRQ_RESET(GEN6_PM);
3177 }
3178
3179 /* drm_dma.h hooks
3180 */
3181 static void ironlake_irq_reset(struct drm_device *dev)
3182 {
3183 struct drm_i915_private *dev_priv = dev->dev_private;
3184
3185 I915_WRITE(HWSTAM, 0xffffffff);
3186
3187 GEN5_IRQ_RESET(DE);
3188 if (IS_GEN7(dev))
3189 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3190
3191 gen5_gt_irq_reset(dev);
3192
3193 ibx_irq_reset(dev);
3194 }
3195
3196 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3197 {
3198 enum pipe pipe;
3199
3200 I915_WRITE(PORT_HOTPLUG_EN, 0);
3201 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3202
3203 for_each_pipe(dev_priv, pipe)
3204 I915_WRITE(PIPESTAT(pipe), 0xffff);
3205
3206 GEN5_IRQ_RESET(VLV_);
3207 }
3208
3209 static void valleyview_irq_preinstall(struct drm_device *dev)
3210 {
3211 struct drm_i915_private *dev_priv = dev->dev_private;
3212
3213 /* VLV magic */
3214 I915_WRITE(VLV_IMR, 0);
3215 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
3216 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
3217 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
3218
3219 gen5_gt_irq_reset(dev);
3220
3221 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3222
3223 vlv_display_irq_reset(dev_priv);
3224 }
3225
3226 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3227 {
3228 GEN8_IRQ_RESET_NDX(GT, 0);
3229 GEN8_IRQ_RESET_NDX(GT, 1);
3230 GEN8_IRQ_RESET_NDX(GT, 2);
3231 GEN8_IRQ_RESET_NDX(GT, 3);
3232 }
3233
3234 static void gen8_irq_reset(struct drm_device *dev)
3235 {
3236 struct drm_i915_private *dev_priv = dev->dev_private;
3237 int pipe;
3238
3239 I915_WRITE(GEN8_MASTER_IRQ, 0);
3240 POSTING_READ(GEN8_MASTER_IRQ);
3241
3242 gen8_gt_irq_reset(dev_priv);
3243
3244 for_each_pipe(dev_priv, pipe)
3245 if (intel_display_power_is_enabled(dev_priv,
3246 POWER_DOMAIN_PIPE(pipe)))
3247 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3248
3249 GEN5_IRQ_RESET(GEN8_DE_PORT_);
3250 GEN5_IRQ_RESET(GEN8_DE_MISC_);
3251 GEN5_IRQ_RESET(GEN8_PCU_);
3252
3253 if (HAS_PCH_SPLIT(dev))
3254 ibx_irq_reset(dev);
3255 }
3256
3257 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3258 unsigned int pipe_mask)
3259 {
3260 uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3261
3262 spin_lock_irq(&dev_priv->irq_lock);
3263 if (pipe_mask & 1 << PIPE_A)
3264 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_A,
3265 dev_priv->de_irq_mask[PIPE_A],
3266 ~dev_priv->de_irq_mask[PIPE_A] | extra_ier);
3267 if (pipe_mask & 1 << PIPE_B)
3268 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B,
3269 dev_priv->de_irq_mask[PIPE_B],
3270 ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
3271 if (pipe_mask & 1 << PIPE_C)
3272 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C,
3273 dev_priv->de_irq_mask[PIPE_C],
3274 ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
3275 spin_unlock_irq(&dev_priv->irq_lock);
3276 }
3277
3278 static void cherryview_irq_preinstall(struct drm_device *dev)
3279 {
3280 struct drm_i915_private *dev_priv = dev->dev_private;
3281
3282 I915_WRITE(GEN8_MASTER_IRQ, 0);
3283 POSTING_READ(GEN8_MASTER_IRQ);
3284
3285 gen8_gt_irq_reset(dev_priv);
3286
3287 GEN5_IRQ_RESET(GEN8_PCU_);
3288
3289 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3290
3291 vlv_display_irq_reset(dev_priv);
3292 }
3293
3294 static void ibx_hpd_irq_setup(struct drm_device *dev)
3295 {
3296 struct drm_i915_private *dev_priv = dev->dev_private;
3297 struct intel_encoder *intel_encoder;
3298 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
3299
3300 if (HAS_PCH_IBX(dev)) {
3301 hotplug_irqs = SDE_HOTPLUG_MASK;
3302 for_each_intel_encoder(dev, intel_encoder)
3303 if (dev_priv->hotplug.stats[intel_encoder->hpd_pin].state == HPD_ENABLED)
3304 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
3305 } else {
3306 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3307 for_each_intel_encoder(dev, intel_encoder)
3308 if (dev_priv->hotplug.stats[intel_encoder->hpd_pin].state == HPD_ENABLED)
3309 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
3310 }
3311
3312 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3313
3314 /*
3315 * Enable digital hotplug on the PCH, and configure the DP short pulse
3316 * duration to 2ms (which is the minimum in the Display Port spec)
3317 *
3318 * This register is the same on all known PCH chips.
3319 */
3320 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3321 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3322 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3323 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3324 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3325 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3326 }
3327
3328 static void bxt_hpd_irq_setup(struct drm_device *dev)
3329 {
3330 struct drm_i915_private *dev_priv = dev->dev_private;
3331 struct intel_encoder *intel_encoder;
3332 u32 hotplug_port = 0;
3333 u32 hotplug_ctrl;
3334
3335 /* Now, enable HPD */
3336 for_each_intel_encoder(dev, intel_encoder) {
3337 if (dev_priv->hotplug.stats[intel_encoder->hpd_pin].state
3338 == HPD_ENABLED)
3339 hotplug_port |= hpd_bxt[intel_encoder->hpd_pin];
3340 }
3341
3342 /* Mask all HPD control bits */
3343 hotplug_ctrl = I915_READ(BXT_HOTPLUG_CTL) & ~BXT_HOTPLUG_CTL_MASK;
3344
3345 /* Enable requested port in hotplug control */
3346 /* TODO: implement (short) HPD support on port A */
3347 WARN_ON_ONCE(hotplug_port & BXT_DE_PORT_HP_DDIA);
3348 if (hotplug_port & BXT_DE_PORT_HP_DDIB)
3349 hotplug_ctrl |= BXT_DDIB_HPD_ENABLE;
3350 if (hotplug_port & BXT_DE_PORT_HP_DDIC)
3351 hotplug_ctrl |= BXT_DDIC_HPD_ENABLE;
3352 I915_WRITE(BXT_HOTPLUG_CTL, hotplug_ctrl);
3353
3354 /* Unmask DDI hotplug in IMR */
3355 hotplug_ctrl = I915_READ(GEN8_DE_PORT_IMR) & ~hotplug_port;
3356 I915_WRITE(GEN8_DE_PORT_IMR, hotplug_ctrl);
3357
3358 /* Enable DDI hotplug in IER */
3359 hotplug_ctrl = I915_READ(GEN8_DE_PORT_IER) | hotplug_port;
3360 I915_WRITE(GEN8_DE_PORT_IER, hotplug_ctrl);
3361 POSTING_READ(GEN8_DE_PORT_IER);
3362 }
3363
3364 static void ibx_irq_postinstall(struct drm_device *dev)
3365 {
3366 struct drm_i915_private *dev_priv = dev->dev_private;
3367 u32 mask;
3368
3369 if (HAS_PCH_NOP(dev))
3370 return;
3371
3372 if (HAS_PCH_IBX(dev))
3373 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3374 else
3375 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3376
3377 GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
3378 I915_WRITE(SDEIMR, ~mask);
3379 }
3380
3381 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3382 {
3383 struct drm_i915_private *dev_priv = dev->dev_private;
3384 u32 pm_irqs, gt_irqs;
3385
3386 pm_irqs = gt_irqs = 0;
3387
3388 dev_priv->gt_irq_mask = ~0;
3389 if (HAS_L3_DPF(dev)) {
3390 /* L3 parity interrupt is always unmasked. */
3391 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3392 gt_irqs |= GT_PARITY_ERROR(dev);
3393 }
3394
3395 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3396 if (IS_GEN5(dev)) {
3397 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3398 ILK_BSD_USER_INTERRUPT;
3399 } else {
3400 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3401 }
3402
3403 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3404
3405 if (INTEL_INFO(dev)->gen >= 6) {
3406 /*
3407 * RPS interrupts will get enabled/disabled on demand when RPS
3408 * itself is enabled/disabled.
3409 */
3410 if (HAS_VEBOX(dev))
3411 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3412
3413 dev_priv->pm_irq_mask = 0xffffffff;
3414 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3415 }
3416 }
3417
3418 static int ironlake_irq_postinstall(struct drm_device *dev)
3419 {
3420 struct drm_i915_private *dev_priv = dev->dev_private;
3421 u32 display_mask, extra_mask;
3422
3423 if (INTEL_INFO(dev)->gen >= 7) {
3424 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3425 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3426 DE_PLANEB_FLIP_DONE_IVB |
3427 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3428 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3429 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
3430 } else {
3431 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3432 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3433 DE_AUX_CHANNEL_A |
3434 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3435 DE_POISON);
3436 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3437 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
3438 }
3439
3440 dev_priv->irq_mask = ~display_mask;
3441
3442 I915_WRITE(HWSTAM, 0xeffe);
3443
3444 ibx_irq_pre_postinstall(dev);
3445
3446 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3447
3448 gen5_gt_irq_postinstall(dev);
3449
3450 ibx_irq_postinstall(dev);
3451
3452 if (IS_IRONLAKE_M(dev)) {
3453 /* Enable PCU event interrupts
3454 *
3455 * spinlocking not required here for correctness since interrupt
3456 * setup is guaranteed to run in single-threaded context. But we
3457 * need it to make the assert_spin_locked happy. */
3458 spin_lock_irq(&dev_priv->irq_lock);
3459 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
3460 spin_unlock_irq(&dev_priv->irq_lock);
3461 }
3462
3463 return 0;
3464 }
3465
3466 static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3467 {
3468 u32 pipestat_mask;
3469 u32 iir_mask;
3470 enum pipe pipe;
3471
3472 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3473 PIPE_FIFO_UNDERRUN_STATUS;
3474
3475 for_each_pipe(dev_priv, pipe)
3476 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3477 POSTING_READ(PIPESTAT(PIPE_A));
3478
3479 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3480 PIPE_CRC_DONE_INTERRUPT_STATUS;
3481
3482 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3483 for_each_pipe(dev_priv, pipe)
3484 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3485
3486 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3487 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3488 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3489 if (IS_CHERRYVIEW(dev_priv))
3490 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3491 dev_priv->irq_mask &= ~iir_mask;
3492
3493 I915_WRITE(VLV_IIR, iir_mask);
3494 I915_WRITE(VLV_IIR, iir_mask);
3495 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3496 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3497 POSTING_READ(VLV_IMR);
3498 }
3499
3500 static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3501 {
3502 u32 pipestat_mask;
3503 u32 iir_mask;
3504 enum pipe pipe;
3505
3506 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3507 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3508 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3509 if (IS_CHERRYVIEW(dev_priv))
3510 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3511
3512 dev_priv->irq_mask |= iir_mask;
3513 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3514 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3515 I915_WRITE(VLV_IIR, iir_mask);
3516 I915_WRITE(VLV_IIR, iir_mask);
3517 POSTING_READ(VLV_IIR);
3518
3519 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3520 PIPE_CRC_DONE_INTERRUPT_STATUS;
3521
3522 i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3523 for_each_pipe(dev_priv, pipe)
3524 i915_disable_pipestat(dev_priv, pipe, pipestat_mask);
3525
3526 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3527 PIPE_FIFO_UNDERRUN_STATUS;
3528
3529 for_each_pipe(dev_priv, pipe)
3530 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3531 POSTING_READ(PIPESTAT(PIPE_A));
3532 }
3533
3534 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3535 {
3536 assert_spin_locked(&dev_priv->irq_lock);
3537
3538 if (dev_priv->display_irqs_enabled)
3539 return;
3540
3541 dev_priv->display_irqs_enabled = true;
3542
3543 if (intel_irqs_enabled(dev_priv))
3544 valleyview_display_irqs_install(dev_priv);
3545 }
3546
3547 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3548 {
3549 assert_spin_locked(&dev_priv->irq_lock);
3550
3551 if (!dev_priv->display_irqs_enabled)
3552 return;
3553
3554 dev_priv->display_irqs_enabled = false;
3555
3556 if (intel_irqs_enabled(dev_priv))
3557 valleyview_display_irqs_uninstall(dev_priv);
3558 }
3559
3560 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3561 {
3562 dev_priv->irq_mask = ~0;
3563
3564 I915_WRITE(PORT_HOTPLUG_EN, 0);
3565 POSTING_READ(PORT_HOTPLUG_EN);
3566
3567 I915_WRITE(VLV_IIR, 0xffffffff);
3568 I915_WRITE(VLV_IIR, 0xffffffff);
3569 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3570 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3571 POSTING_READ(VLV_IMR);
3572
3573 /* Interrupt setup is already guaranteed to be single-threaded, this is
3574 * just to make the assert_spin_locked check happy. */
3575 spin_lock_irq(&dev_priv->irq_lock);
3576 if (dev_priv->display_irqs_enabled)
3577 valleyview_display_irqs_install(dev_priv);
3578 spin_unlock_irq(&dev_priv->irq_lock);
3579 }
3580
3581 static int valleyview_irq_postinstall(struct drm_device *dev)
3582 {
3583 struct drm_i915_private *dev_priv = dev->dev_private;
3584
3585 vlv_display_irq_postinstall(dev_priv);
3586
3587 gen5_gt_irq_postinstall(dev);
3588
3589 /* ack & enable invalid PTE error interrupts */
3590 #if 0 /* FIXME: add support to irq handler for checking these bits */
3591 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3592 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3593 #endif
3594
3595 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3596
3597 return 0;
3598 }
3599
3600 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3601 {
3602 /* These are interrupts we'll toggle with the ring mask register */
3603 uint32_t gt_interrupts[] = {
3604 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3605 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3606 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3607 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3608 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3609 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3610 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3611 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3612 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3613 0,
3614 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3615 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3616 };
3617
3618 dev_priv->pm_irq_mask = 0xffffffff;
3619 GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3620 GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3621 /*
3622 * RPS interrupts will get enabled/disabled on demand when RPS itself
3623 * is enabled/disabled.
3624 */
3625 GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
3626 GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3627 }
3628
3629 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3630 {
3631 uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3632 uint32_t de_pipe_enables;
3633 int pipe;
3634 u32 de_port_en = GEN8_AUX_CHANNEL_A;
3635
3636 if (IS_GEN9(dev_priv)) {
3637 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3638 GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3639 de_port_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3640 GEN9_AUX_CHANNEL_D;
3641
3642 if (IS_BROXTON(dev_priv))
3643 de_port_en |= BXT_DE_PORT_GMBUS;
3644 } else
3645 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3646 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3647
3648 de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3649 GEN8_PIPE_FIFO_UNDERRUN;
3650
3651 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3652 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3653 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3654
3655 for_each_pipe(dev_priv, pipe)
3656 if (intel_display_power_is_enabled(dev_priv,
3657 POWER_DOMAIN_PIPE(pipe)))
3658 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3659 dev_priv->de_irq_mask[pipe],
3660 de_pipe_enables);
3661
3662 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_en, de_port_en);
3663 }
3664
3665 static int gen8_irq_postinstall(struct drm_device *dev)
3666 {
3667 struct drm_i915_private *dev_priv = dev->dev_private;
3668
3669 if (HAS_PCH_SPLIT(dev))
3670 ibx_irq_pre_postinstall(dev);
3671
3672 gen8_gt_irq_postinstall(dev_priv);
3673 gen8_de_irq_postinstall(dev_priv);
3674
3675 if (HAS_PCH_SPLIT(dev))
3676 ibx_irq_postinstall(dev);
3677
3678 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3679 POSTING_READ(GEN8_MASTER_IRQ);
3680
3681 return 0;
3682 }
3683
3684 static int cherryview_irq_postinstall(struct drm_device *dev)
3685 {
3686 struct drm_i915_private *dev_priv = dev->dev_private;
3687
3688 vlv_display_irq_postinstall(dev_priv);
3689
3690 gen8_gt_irq_postinstall(dev_priv);
3691
3692 I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
3693 POSTING_READ(GEN8_MASTER_IRQ);
3694
3695 return 0;
3696 }
3697
3698 static void gen8_irq_uninstall(struct drm_device *dev)
3699 {
3700 struct drm_i915_private *dev_priv = dev->dev_private;
3701
3702 if (!dev_priv)
3703 return;
3704
3705 gen8_irq_reset(dev);
3706 }
3707
3708 static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv)
3709 {
3710 /* Interrupt setup is already guaranteed to be single-threaded, this is
3711 * just to make the assert_spin_locked check happy. */
3712 spin_lock_irq(&dev_priv->irq_lock);
3713 if (dev_priv->display_irqs_enabled)
3714 valleyview_display_irqs_uninstall(dev_priv);
3715 spin_unlock_irq(&dev_priv->irq_lock);
3716
3717 vlv_display_irq_reset(dev_priv);
3718
3719 dev_priv->irq_mask = ~0;
3720 }
3721
3722 static void valleyview_irq_uninstall(struct drm_device *dev)
3723 {
3724 struct drm_i915_private *dev_priv = dev->dev_private;
3725
3726 if (!dev_priv)
3727 return;
3728
3729 I915_WRITE(VLV_MASTER_IER, 0);
3730
3731 gen5_gt_irq_reset(dev);
3732
3733 I915_WRITE(HWSTAM, 0xffffffff);
3734
3735 vlv_display_irq_uninstall(dev_priv);
3736 }
3737
3738 static void cherryview_irq_uninstall(struct drm_device *dev)
3739 {
3740 struct drm_i915_private *dev_priv = dev->dev_private;
3741
3742 if (!dev_priv)
3743 return;
3744
3745 I915_WRITE(GEN8_MASTER_IRQ, 0);
3746 POSTING_READ(GEN8_MASTER_IRQ);
3747
3748 gen8_gt_irq_reset(dev_priv);
3749
3750 GEN5_IRQ_RESET(GEN8_PCU_);
3751
3752 vlv_display_irq_uninstall(dev_priv);
3753 }
3754
3755 static void ironlake_irq_uninstall(struct drm_device *dev)
3756 {
3757 struct drm_i915_private *dev_priv = dev->dev_private;
3758
3759 if (!dev_priv)
3760 return;
3761
3762 ironlake_irq_reset(dev);
3763 }
3764
3765 static void i8xx_irq_preinstall(struct drm_device * dev)
3766 {
3767 struct drm_i915_private *dev_priv = dev->dev_private;
3768 int pipe;
3769
3770 for_each_pipe(dev_priv, pipe)
3771 I915_WRITE(PIPESTAT(pipe), 0);
3772 I915_WRITE16(IMR, 0xffff);
3773 I915_WRITE16(IER, 0x0);
3774 POSTING_READ16(IER);
3775 }
3776
3777 static int i8xx_irq_postinstall(struct drm_device *dev)
3778 {
3779 struct drm_i915_private *dev_priv = dev->dev_private;
3780
3781 I915_WRITE16(EMR,
3782 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3783
3784 /* Unmask the interrupts that we always want on. */
3785 dev_priv->irq_mask =
3786 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3787 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3788 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3789 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3790 I915_WRITE16(IMR, dev_priv->irq_mask);
3791
3792 I915_WRITE16(IER,
3793 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3794 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3795 I915_USER_INTERRUPT);
3796 POSTING_READ16(IER);
3797
3798 /* Interrupt setup is already guaranteed to be single-threaded, this is
3799 * just to make the assert_spin_locked check happy. */
3800 spin_lock_irq(&dev_priv->irq_lock);
3801 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3802 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3803 spin_unlock_irq(&dev_priv->irq_lock);
3804
3805 return 0;
3806 }
3807
3808 /*
3809 * Returns true when a page flip has completed.
3810 */
3811 static bool i8xx_handle_vblank(struct drm_device *dev,
3812 int plane, int pipe, u32 iir)
3813 {
3814 struct drm_i915_private *dev_priv = dev->dev_private;
3815 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3816
3817 if (!intel_pipe_handle_vblank(dev, pipe))
3818 return false;
3819
3820 if ((iir & flip_pending) == 0)
3821 goto check_page_flip;
3822
3823 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3824 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3825 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3826 * the flip is completed (no longer pending). Since this doesn't raise
3827 * an interrupt per se, we watch for the change at vblank.
3828 */
3829 if (I915_READ16(ISR) & flip_pending)
3830 goto check_page_flip;
3831
3832 intel_prepare_page_flip(dev, plane);
3833 intel_finish_page_flip(dev, pipe);
3834 return true;
3835
3836 check_page_flip:
3837 intel_check_page_flip(dev, pipe);
3838 return false;
3839 }
3840
3841 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3842 {
3843 struct drm_device *dev = arg;
3844 struct drm_i915_private *dev_priv = dev->dev_private;
3845 u16 iir, new_iir;
3846 u32 pipe_stats[2];
3847 int pipe;
3848 u16 flip_mask =
3849 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3850 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3851
3852 if (!intel_irqs_enabled(dev_priv))
3853 return IRQ_NONE;
3854
3855 iir = I915_READ16(IIR);
3856 if (iir == 0)
3857 return IRQ_NONE;
3858
3859 while (iir & ~flip_mask) {
3860 /* Can't rely on pipestat interrupt bit in iir as it might
3861 * have been cleared after the pipestat interrupt was received.
3862 * It doesn't set the bit in iir again, but it still produces
3863 * interrupts (for non-MSI).
3864 */
3865 spin_lock(&dev_priv->irq_lock);
3866 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3867 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3868
3869 for_each_pipe(dev_priv, pipe) {
3870 int reg = PIPESTAT(pipe);
3871 pipe_stats[pipe] = I915_READ(reg);
3872
3873 /*
3874 * Clear the PIPE*STAT regs before the IIR
3875 */
3876 if (pipe_stats[pipe] & 0x8000ffff)
3877 I915_WRITE(reg, pipe_stats[pipe]);
3878 }
3879 spin_unlock(&dev_priv->irq_lock);
3880
3881 I915_WRITE16(IIR, iir & ~flip_mask);
3882 new_iir = I915_READ16(IIR); /* Flush posted writes */
3883
3884 if (iir & I915_USER_INTERRUPT)
3885 notify_ring(&dev_priv->ring[RCS]);
3886
3887 for_each_pipe(dev_priv, pipe) {
3888 int plane = pipe;
3889 if (HAS_FBC(dev))
3890 plane = !plane;
3891
3892 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3893 i8xx_handle_vblank(dev, plane, pipe, iir))
3894 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3895
3896 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3897 i9xx_pipe_crc_irq_handler(dev, pipe);
3898
3899 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3900 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3901 pipe);
3902 }
3903
3904 iir = new_iir;
3905 }
3906
3907 return IRQ_HANDLED;
3908 }
3909
3910 static void i8xx_irq_uninstall(struct drm_device * dev)
3911 {
3912 struct drm_i915_private *dev_priv = dev->dev_private;
3913 int pipe;
3914
3915 for_each_pipe(dev_priv, pipe) {
3916 /* Clear enable bits; then clear status bits */
3917 I915_WRITE(PIPESTAT(pipe), 0);
3918 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3919 }
3920 I915_WRITE16(IMR, 0xffff);
3921 I915_WRITE16(IER, 0x0);
3922 I915_WRITE16(IIR, I915_READ16(IIR));
3923 }
3924
3925 static void i915_irq_preinstall(struct drm_device * dev)
3926 {
3927 struct drm_i915_private *dev_priv = dev->dev_private;
3928 int pipe;
3929
3930 if (I915_HAS_HOTPLUG(dev)) {
3931 I915_WRITE(PORT_HOTPLUG_EN, 0);
3932 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3933 }
3934
3935 I915_WRITE16(HWSTAM, 0xeffe);
3936 for_each_pipe(dev_priv, pipe)
3937 I915_WRITE(PIPESTAT(pipe), 0);
3938 I915_WRITE(IMR, 0xffffffff);
3939 I915_WRITE(IER, 0x0);
3940 POSTING_READ(IER);
3941 }
3942
3943 static int i915_irq_postinstall(struct drm_device *dev)
3944 {
3945 struct drm_i915_private *dev_priv = dev->dev_private;
3946 u32 enable_mask;
3947
3948 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3949
3950 /* Unmask the interrupts that we always want on. */
3951 dev_priv->irq_mask =
3952 ~(I915_ASLE_INTERRUPT |
3953 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3954 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3955 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3956 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3957
3958 enable_mask =
3959 I915_ASLE_INTERRUPT |
3960 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3961 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3962 I915_USER_INTERRUPT;
3963
3964 if (I915_HAS_HOTPLUG(dev)) {
3965 I915_WRITE(PORT_HOTPLUG_EN, 0);
3966 POSTING_READ(PORT_HOTPLUG_EN);
3967
3968 /* Enable in IER... */
3969 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3970 /* and unmask in IMR */
3971 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3972 }
3973
3974 I915_WRITE(IMR, dev_priv->irq_mask);
3975 I915_WRITE(IER, enable_mask);
3976 POSTING_READ(IER);
3977
3978 i915_enable_asle_pipestat(dev);
3979
3980 /* Interrupt setup is already guaranteed to be single-threaded, this is
3981 * just to make the assert_spin_locked check happy. */
3982 spin_lock_irq(&dev_priv->irq_lock);
3983 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3984 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3985 spin_unlock_irq(&dev_priv->irq_lock);
3986
3987 return 0;
3988 }
3989
3990 /*
3991 * Returns true when a page flip has completed.
3992 */
3993 static bool i915_handle_vblank(struct drm_device *dev,
3994 int plane, int pipe, u32 iir)
3995 {
3996 struct drm_i915_private *dev_priv = dev->dev_private;
3997 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3998
3999 if (!intel_pipe_handle_vblank(dev, pipe))
4000 return false;
4001
4002 if ((iir & flip_pending) == 0)
4003 goto check_page_flip;
4004
4005 /* We detect FlipDone by looking for the change in PendingFlip from '1'
4006 * to '0' on the following vblank, i.e. IIR has the Pendingflip
4007 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
4008 * the flip is completed (no longer pending). Since this doesn't raise
4009 * an interrupt per se, we watch for the change at vblank.
4010 */
4011 if (I915_READ(ISR) & flip_pending)
4012 goto check_page_flip;
4013
4014 intel_prepare_page_flip(dev, plane);
4015 intel_finish_page_flip(dev, pipe);
4016 return true;
4017
4018 check_page_flip:
4019 intel_check_page_flip(dev, pipe);
4020 return false;
4021 }
4022
4023 static irqreturn_t i915_irq_handler(int irq, void *arg)
4024 {
4025 struct drm_device *dev = arg;
4026 struct drm_i915_private *dev_priv = dev->dev_private;
4027 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
4028 u32 flip_mask =
4029 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4030 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4031 int pipe, ret = IRQ_NONE;
4032
4033 if (!intel_irqs_enabled(dev_priv))
4034 return IRQ_NONE;
4035
4036 iir = I915_READ(IIR);
4037 do {
4038 bool irq_received = (iir & ~flip_mask) != 0;
4039 bool blc_event = false;
4040
4041 /* Can't rely on pipestat interrupt bit in iir as it might
4042 * have been cleared after the pipestat interrupt was received.
4043 * It doesn't set the bit in iir again, but it still produces
4044 * interrupts (for non-MSI).
4045 */
4046 spin_lock(&dev_priv->irq_lock);
4047 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4048 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4049
4050 for_each_pipe(dev_priv, pipe) {
4051 int reg = PIPESTAT(pipe);
4052 pipe_stats[pipe] = I915_READ(reg);
4053
4054 /* Clear the PIPE*STAT regs before the IIR */
4055 if (pipe_stats[pipe] & 0x8000ffff) {
4056 I915_WRITE(reg, pipe_stats[pipe]);
4057 irq_received = true;
4058 }
4059 }
4060 spin_unlock(&dev_priv->irq_lock);
4061
4062 if (!irq_received)
4063 break;
4064
4065 /* Consume port. Then clear IIR or we'll miss events */
4066 if (I915_HAS_HOTPLUG(dev) &&
4067 iir & I915_DISPLAY_PORT_INTERRUPT)
4068 i9xx_hpd_irq_handler(dev);
4069
4070 I915_WRITE(IIR, iir & ~flip_mask);
4071 new_iir = I915_READ(IIR); /* Flush posted writes */
4072
4073 if (iir & I915_USER_INTERRUPT)
4074 notify_ring(&dev_priv->ring[RCS]);
4075
4076 for_each_pipe(dev_priv, pipe) {
4077 int plane = pipe;
4078 if (HAS_FBC(dev))
4079 plane = !plane;
4080
4081 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4082 i915_handle_vblank(dev, plane, pipe, iir))
4083 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4084
4085 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4086 blc_event = true;
4087
4088 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4089 i9xx_pipe_crc_irq_handler(dev, pipe);
4090
4091 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4092 intel_cpu_fifo_underrun_irq_handler(dev_priv,
4093 pipe);
4094 }
4095
4096 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4097 intel_opregion_asle_intr(dev);
4098
4099 /* With MSI, interrupts are only generated when iir
4100 * transitions from zero to nonzero. If another bit got
4101 * set while we were handling the existing iir bits, then
4102 * we would never get another interrupt.
4103 *
4104 * This is fine on non-MSI as well, as if we hit this path
4105 * we avoid exiting the interrupt handler only to generate
4106 * another one.
4107 *
4108 * Note that for MSI this could cause a stray interrupt report
4109 * if an interrupt landed in the time between writing IIR and
4110 * the posting read. This should be rare enough to never
4111 * trigger the 99% of 100,000 interrupts test for disabling
4112 * stray interrupts.
4113 */
4114 ret = IRQ_HANDLED;
4115 iir = new_iir;
4116 } while (iir & ~flip_mask);
4117
4118 return ret;
4119 }
4120
4121 static void i915_irq_uninstall(struct drm_device * dev)
4122 {
4123 struct drm_i915_private *dev_priv = dev->dev_private;
4124 int pipe;
4125
4126 if (I915_HAS_HOTPLUG(dev)) {
4127 I915_WRITE(PORT_HOTPLUG_EN, 0);
4128 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4129 }
4130
4131 I915_WRITE16(HWSTAM, 0xffff);
4132 for_each_pipe(dev_priv, pipe) {
4133 /* Clear enable bits; then clear status bits */
4134 I915_WRITE(PIPESTAT(pipe), 0);
4135 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4136 }
4137 I915_WRITE(IMR, 0xffffffff);
4138 I915_WRITE(IER, 0x0);
4139
4140 I915_WRITE(IIR, I915_READ(IIR));
4141 }
4142
4143 static void i965_irq_preinstall(struct drm_device * dev)
4144 {
4145 struct drm_i915_private *dev_priv = dev->dev_private;
4146 int pipe;
4147
4148 I915_WRITE(PORT_HOTPLUG_EN, 0);
4149 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4150
4151 I915_WRITE(HWSTAM, 0xeffe);
4152 for_each_pipe(dev_priv, pipe)
4153 I915_WRITE(PIPESTAT(pipe), 0);
4154 I915_WRITE(IMR, 0xffffffff);
4155 I915_WRITE(IER, 0x0);
4156 POSTING_READ(IER);
4157 }
4158
4159 static int i965_irq_postinstall(struct drm_device *dev)
4160 {
4161 struct drm_i915_private *dev_priv = dev->dev_private;
4162 u32 enable_mask;
4163 u32 error_mask;
4164
4165 /* Unmask the interrupts that we always want on. */
4166 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4167 I915_DISPLAY_PORT_INTERRUPT |
4168 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4169 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4170 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4171 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4172 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4173
4174 enable_mask = ~dev_priv->irq_mask;
4175 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4176 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4177 enable_mask |= I915_USER_INTERRUPT;
4178
4179 if (IS_G4X(dev))
4180 enable_mask |= I915_BSD_USER_INTERRUPT;
4181
4182 /* Interrupt setup is already guaranteed to be single-threaded, this is
4183 * just to make the assert_spin_locked check happy. */
4184 spin_lock_irq(&dev_priv->irq_lock);
4185 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4186 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4187 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4188 spin_unlock_irq(&dev_priv->irq_lock);
4189
4190 /*
4191 * Enable some error detection, note the instruction error mask
4192 * bit is reserved, so we leave it masked.
4193 */
4194 if (IS_G4X(dev)) {
4195 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4196 GM45_ERROR_MEM_PRIV |
4197 GM45_ERROR_CP_PRIV |
4198 I915_ERROR_MEMORY_REFRESH);
4199 } else {
4200 error_mask = ~(I915_ERROR_PAGE_TABLE |
4201 I915_ERROR_MEMORY_REFRESH);
4202 }
4203 I915_WRITE(EMR, error_mask);
4204
4205 I915_WRITE(IMR, dev_priv->irq_mask);
4206 I915_WRITE(IER, enable_mask);
4207 POSTING_READ(IER);
4208
4209 I915_WRITE(PORT_HOTPLUG_EN, 0);
4210 POSTING_READ(PORT_HOTPLUG_EN);
4211
4212 i915_enable_asle_pipestat(dev);
4213
4214 return 0;
4215 }
4216
4217 static void i915_hpd_irq_setup(struct drm_device *dev)
4218 {
4219 struct drm_i915_private *dev_priv = dev->dev_private;
4220 struct intel_encoder *intel_encoder;
4221 u32 hotplug_en;
4222
4223 assert_spin_locked(&dev_priv->irq_lock);
4224
4225 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
4226 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
4227 /* Note HDMI and DP share hotplug bits */
4228 /* enable bits are the same for all generations */
4229 for_each_intel_encoder(dev, intel_encoder)
4230 if (dev_priv->hotplug.stats[intel_encoder->hpd_pin].state == HPD_ENABLED)
4231 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
4232 /* Programming the CRT detection parameters tends
4233 to generate a spurious hotplug event about three
4234 seconds later. So just do it once.
4235 */
4236 if (IS_G4X(dev))
4237 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4238 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
4239 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4240
4241 /* Ignore TV since it's buggy */
4242 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
4243 }
4244
4245 static irqreturn_t i965_irq_handler(int irq, void *arg)
4246 {
4247 struct drm_device *dev = arg;
4248 struct drm_i915_private *dev_priv = dev->dev_private;
4249 u32 iir, new_iir;
4250 u32 pipe_stats[I915_MAX_PIPES];
4251 int ret = IRQ_NONE, pipe;
4252 u32 flip_mask =
4253 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4254 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4255
4256 if (!intel_irqs_enabled(dev_priv))
4257 return IRQ_NONE;
4258
4259 iir = I915_READ(IIR);
4260
4261 for (;;) {
4262 bool irq_received = (iir & ~flip_mask) != 0;
4263 bool blc_event = false;
4264
4265 /* Can't rely on pipestat interrupt bit in iir as it might
4266 * have been cleared after the pipestat interrupt was received.
4267 * It doesn't set the bit in iir again, but it still produces
4268 * interrupts (for non-MSI).
4269 */
4270 spin_lock(&dev_priv->irq_lock);
4271 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4272 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4273
4274 for_each_pipe(dev_priv, pipe) {
4275 int reg = PIPESTAT(pipe);
4276 pipe_stats[pipe] = I915_READ(reg);
4277
4278 /*
4279 * Clear the PIPE*STAT regs before the IIR
4280 */
4281 if (pipe_stats[pipe] & 0x8000ffff) {
4282 I915_WRITE(reg, pipe_stats[pipe]);
4283 irq_received = true;
4284 }
4285 }
4286 spin_unlock(&dev_priv->irq_lock);
4287
4288 if (!irq_received)
4289 break;
4290
4291 ret = IRQ_HANDLED;
4292
4293 /* Consume port. Then clear IIR or we'll miss events */
4294 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4295 i9xx_hpd_irq_handler(dev);
4296
4297 I915_WRITE(IIR, iir & ~flip_mask);
4298 new_iir = I915_READ(IIR); /* Flush posted writes */
4299
4300 if (iir & I915_USER_INTERRUPT)
4301 notify_ring(&dev_priv->ring[RCS]);
4302 if (iir & I915_BSD_USER_INTERRUPT)
4303 notify_ring(&dev_priv->ring[VCS]);
4304
4305 for_each_pipe(dev_priv, pipe) {
4306 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4307 i915_handle_vblank(dev, pipe, pipe, iir))
4308 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4309
4310 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4311 blc_event = true;
4312
4313 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4314 i9xx_pipe_crc_irq_handler(dev, pipe);
4315
4316 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4317 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4318 }
4319
4320 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4321 intel_opregion_asle_intr(dev);
4322
4323 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4324 gmbus_irq_handler(dev);
4325
4326 /* With MSI, interrupts are only generated when iir
4327 * transitions from zero to nonzero. If another bit got
4328 * set while we were handling the existing iir bits, then
4329 * we would never get another interrupt.
4330 *
4331 * This is fine on non-MSI as well, as if we hit this path
4332 * we avoid exiting the interrupt handler only to generate
4333 * another one.
4334 *
4335 * Note that for MSI this could cause a stray interrupt report
4336 * if an interrupt landed in the time between writing IIR and
4337 * the posting read. This should be rare enough to never
4338 * trigger the 99% of 100,000 interrupts test for disabling
4339 * stray interrupts.
4340 */
4341 iir = new_iir;
4342 }
4343
4344 return ret;
4345 }
4346
4347 static void i965_irq_uninstall(struct drm_device * dev)
4348 {
4349 struct drm_i915_private *dev_priv = dev->dev_private;
4350 int pipe;
4351
4352 if (!dev_priv)
4353 return;
4354
4355 I915_WRITE(PORT_HOTPLUG_EN, 0);
4356 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4357
4358 I915_WRITE(HWSTAM, 0xffffffff);
4359 for_each_pipe(dev_priv, pipe)
4360 I915_WRITE(PIPESTAT(pipe), 0);
4361 I915_WRITE(IMR, 0xffffffff);
4362 I915_WRITE(IER, 0x0);
4363
4364 for_each_pipe(dev_priv, pipe)
4365 I915_WRITE(PIPESTAT(pipe),
4366 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4367 I915_WRITE(IIR, I915_READ(IIR));
4368 }
4369
4370 static void intel_hpd_irq_reenable_work(struct work_struct *work)
4371 {
4372 struct drm_i915_private *dev_priv =
4373 container_of(work, typeof(*dev_priv),
4374 hotplug.reenable_work.work);
4375 struct drm_device *dev = dev_priv->dev;
4376 struct drm_mode_config *mode_config = &dev->mode_config;
4377 int i;
4378
4379 intel_runtime_pm_get(dev_priv);
4380
4381 spin_lock_irq(&dev_priv->irq_lock);
4382 for_each_hpd_pin(i) {
4383 struct drm_connector *connector;
4384
4385 if (dev_priv->hotplug.stats[i].state != HPD_DISABLED)
4386 continue;
4387
4388 dev_priv->hotplug.stats[i].state = HPD_ENABLED;
4389
4390 list_for_each_entry(connector, &mode_config->connector_list, head) {
4391 struct intel_connector *intel_connector = to_intel_connector(connector);
4392
4393 if (intel_connector->encoder->hpd_pin == i) {
4394 if (connector->polled != intel_connector->polled)
4395 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
4396 connector->name);
4397 connector->polled = intel_connector->polled;
4398 if (!connector->polled)
4399 connector->polled = DRM_CONNECTOR_POLL_HPD;
4400 }
4401 }
4402 }
4403 if (dev_priv->display.hpd_irq_setup)
4404 dev_priv->display.hpd_irq_setup(dev);
4405 spin_unlock_irq(&dev_priv->irq_lock);
4406
4407 intel_runtime_pm_put(dev_priv);
4408 }
4409
4410 /**
4411 * intel_irq_init - initializes irq support
4412 * @dev_priv: i915 device instance
4413 *
4414 * This function initializes all the irq support including work items, timers
4415 * and all the vtables. It does not setup the interrupt itself though.
4416 */
4417 void intel_irq_init(struct drm_i915_private *dev_priv)
4418 {
4419 struct drm_device *dev = dev_priv->dev;
4420
4421 INIT_WORK(&dev_priv->hotplug.hotplug_work, i915_hotplug_work_func);
4422 INIT_WORK(&dev_priv->hotplug.dig_port_work, i915_digport_work_func);
4423 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4424 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4425
4426 /* Let's track the enabled rps events */
4427 if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
4428 /* WaGsvRC0ResidencyMethod:vlv */
4429 dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
4430 else
4431 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4432
4433 INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
4434 i915_hangcheck_elapsed);
4435 INIT_DELAYED_WORK(&dev_priv->hotplug.reenable_work,
4436 intel_hpd_irq_reenable_work);
4437
4438 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4439
4440 if (IS_GEN2(dev_priv)) {
4441 dev->max_vblank_count = 0;
4442 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4443 } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4444 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4445 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
4446 } else {
4447 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4448 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4449 }
4450
4451 /*
4452 * Opt out of the vblank disable timer on everything except gen2.
4453 * Gen2 doesn't have a hardware frame counter and so depends on
4454 * vblank interrupts to produce sane vblank seuquence numbers.
4455 */
4456 if (!IS_GEN2(dev_priv))
4457 dev->vblank_disable_immediate = true;
4458
4459 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4460 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4461
4462 if (IS_CHERRYVIEW(dev_priv)) {
4463 dev->driver->irq_handler = cherryview_irq_handler;
4464 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4465 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4466 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4467 dev->driver->enable_vblank = valleyview_enable_vblank;
4468 dev->driver->disable_vblank = valleyview_disable_vblank;
4469 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4470 } else if (IS_VALLEYVIEW(dev_priv)) {
4471 dev->driver->irq_handler = valleyview_irq_handler;
4472 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4473 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4474 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4475 dev->driver->enable_vblank = valleyview_enable_vblank;
4476 dev->driver->disable_vblank = valleyview_disable_vblank;
4477 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4478 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
4479 dev->driver->irq_handler = gen8_irq_handler;
4480 dev->driver->irq_preinstall = gen8_irq_reset;
4481 dev->driver->irq_postinstall = gen8_irq_postinstall;
4482 dev->driver->irq_uninstall = gen8_irq_uninstall;
4483 dev->driver->enable_vblank = gen8_enable_vblank;
4484 dev->driver->disable_vblank = gen8_disable_vblank;
4485 if (HAS_PCH_SPLIT(dev))
4486 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4487 else
4488 dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4489 } else if (HAS_PCH_SPLIT(dev)) {
4490 dev->driver->irq_handler = ironlake_irq_handler;
4491 dev->driver->irq_preinstall = ironlake_irq_reset;
4492 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4493 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4494 dev->driver->enable_vblank = ironlake_enable_vblank;
4495 dev->driver->disable_vblank = ironlake_disable_vblank;
4496 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4497 } else {
4498 if (INTEL_INFO(dev_priv)->gen == 2) {
4499 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4500 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4501 dev->driver->irq_handler = i8xx_irq_handler;
4502 dev->driver->irq_uninstall = i8xx_irq_uninstall;
4503 } else if (INTEL_INFO(dev_priv)->gen == 3) {
4504 dev->driver->irq_preinstall = i915_irq_preinstall;
4505 dev->driver->irq_postinstall = i915_irq_postinstall;
4506 dev->driver->irq_uninstall = i915_irq_uninstall;
4507 dev->driver->irq_handler = i915_irq_handler;
4508 } else {
4509 dev->driver->irq_preinstall = i965_irq_preinstall;
4510 dev->driver->irq_postinstall = i965_irq_postinstall;
4511 dev->driver->irq_uninstall = i965_irq_uninstall;
4512 dev->driver->irq_handler = i965_irq_handler;
4513 }
4514 if (I915_HAS_HOTPLUG(dev_priv))
4515 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4516 dev->driver->enable_vblank = i915_enable_vblank;
4517 dev->driver->disable_vblank = i915_disable_vblank;
4518 }
4519 }
4520
4521 /**
4522 * intel_hpd_init - initializes and enables hpd support
4523 * @dev_priv: i915 device instance
4524 *
4525 * This function enables the hotplug support. It requires that interrupts have
4526 * already been enabled with intel_irq_init_hw(). From this point on hotplug and
4527 * poll request can run concurrently to other code, so locking rules must be
4528 * obeyed.
4529 *
4530 * This is a separate step from interrupt enabling to simplify the locking rules
4531 * in the driver load and resume code.
4532 */
4533 void intel_hpd_init(struct drm_i915_private *dev_priv)
4534 {
4535 struct drm_device *dev = dev_priv->dev;
4536 struct drm_mode_config *mode_config = &dev->mode_config;
4537 struct drm_connector *connector;
4538 int i;
4539
4540 for_each_hpd_pin(i) {
4541 dev_priv->hotplug.stats[i].count = 0;
4542 dev_priv->hotplug.stats[i].state = HPD_ENABLED;
4543 }
4544 list_for_each_entry(connector, &mode_config->connector_list, head) {
4545 struct intel_connector *intel_connector = to_intel_connector(connector);
4546 connector->polled = intel_connector->polled;
4547 if (connector->encoder && !connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
4548 connector->polled = DRM_CONNECTOR_POLL_HPD;
4549 if (intel_connector->mst_port)
4550 connector->polled = DRM_CONNECTOR_POLL_HPD;
4551 }
4552
4553 /* Interrupt setup is already guaranteed to be single-threaded, this is
4554 * just to make the assert_spin_locked checks happy. */
4555 spin_lock_irq(&dev_priv->irq_lock);
4556 if (dev_priv->display.hpd_irq_setup)
4557 dev_priv->display.hpd_irq_setup(dev);
4558 spin_unlock_irq(&dev_priv->irq_lock);
4559 }
4560
4561 /**
4562 * intel_irq_install - enables the hardware interrupt
4563 * @dev_priv: i915 device instance
4564 *
4565 * This function enables the hardware interrupt handling, but leaves the hotplug
4566 * handling still disabled. It is called after intel_irq_init().
4567 *
4568 * In the driver load and resume code we need working interrupts in a few places
4569 * but don't want to deal with the hassle of concurrent probe and hotplug
4570 * workers. Hence the split into this two-stage approach.
4571 */
4572 int intel_irq_install(struct drm_i915_private *dev_priv)
4573 {
4574 /*
4575 * We enable some interrupt sources in our postinstall hooks, so mark
4576 * interrupts as enabled _before_ actually enabling them to avoid
4577 * special cases in our ordering checks.
4578 */
4579 dev_priv->pm.irqs_enabled = true;
4580
4581 return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
4582 }
4583
4584 /**
4585 * intel_irq_uninstall - finilizes all irq handling
4586 * @dev_priv: i915 device instance
4587 *
4588 * This stops interrupt and hotplug handling and unregisters and frees all
4589 * resources acquired in the init functions.
4590 */
4591 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4592 {
4593 drm_irq_uninstall(dev_priv->dev);
4594 intel_hpd_cancel_work(dev_priv);
4595 dev_priv->pm.irqs_enabled = false;
4596 }
4597
4598 /**
4599 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4600 * @dev_priv: i915 device instance
4601 *
4602 * This function is used to disable interrupts at runtime, both in the runtime
4603 * pm and the system suspend/resume code.
4604 */
4605 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4606 {
4607 dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
4608 dev_priv->pm.irqs_enabled = false;
4609 synchronize_irq(dev_priv->dev->irq);
4610 }
4611
4612 /**
4613 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4614 * @dev_priv: i915 device instance
4615 *
4616 * This function is used to enable interrupts at runtime, both in the runtime
4617 * pm and the system suspend/resume code.
4618 */
4619 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4620 {
4621 dev_priv->pm.irqs_enabled = true;
4622 dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
4623 dev_priv->dev->driver->irq_postinstall(dev_priv->dev);
4624 }
Linux kernel - Deliverables
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