1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
37 #include "i915_trace.h"
38 #include "intel_drv.h"
40 /* For display hotplug interrupt */
42 ironlake_enable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
44 if ((dev_priv
->irq_mask
& mask
) != 0) {
45 dev_priv
->irq_mask
&= ~mask
;
46 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
52 ironlake_disable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
54 if ((dev_priv
->irq_mask
& mask
) != mask
) {
55 dev_priv
->irq_mask
|= mask
;
56 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
62 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
64 if ((dev_priv
->pipestat
[pipe
] & mask
) != mask
) {
65 u32 reg
= PIPESTAT(pipe
);
67 dev_priv
->pipestat
[pipe
] |= mask
;
68 /* Enable the interrupt, clear any pending status */
69 I915_WRITE(reg
, dev_priv
->pipestat
[pipe
] | (mask
>> 16));
75 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
77 if ((dev_priv
->pipestat
[pipe
] & mask
) != 0) {
78 u32 reg
= PIPESTAT(pipe
);
80 dev_priv
->pipestat
[pipe
] &= ~mask
;
81 I915_WRITE(reg
, dev_priv
->pipestat
[pipe
]);
87 * intel_enable_asle - enable ASLE interrupt for OpRegion
89 void intel_enable_asle(struct drm_device
*dev
)
91 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
92 unsigned long irqflags
;
94 /* FIXME: opregion/asle for VLV */
95 if (IS_VALLEYVIEW(dev
))
98 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
100 if (HAS_PCH_SPLIT(dev
))
101 ironlake_enable_display_irq(dev_priv
, DE_GSE
);
103 i915_enable_pipestat(dev_priv
, 1,
104 PIPE_LEGACY_BLC_EVENT_ENABLE
);
105 if (INTEL_INFO(dev
)->gen
>= 4)
106 i915_enable_pipestat(dev_priv
, 0,
107 PIPE_LEGACY_BLC_EVENT_ENABLE
);
110 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
114 * i915_pipe_enabled - check if a pipe is enabled
116 * @pipe: pipe to check
118 * Reading certain registers when the pipe is disabled can hang the chip.
119 * Use this routine to make sure the PLL is running and the pipe is active
120 * before reading such registers if unsure.
123 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
125 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
126 return I915_READ(PIPECONF(pipe
)) & PIPECONF_ENABLE
;
129 /* Called from drm generic code, passed a 'crtc', which
130 * we use as a pipe index
132 static u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
134 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
135 unsigned long high_frame
;
136 unsigned long low_frame
;
137 u32 high1
, high2
, low
;
139 if (!i915_pipe_enabled(dev
, pipe
)) {
140 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
141 "pipe %c\n", pipe_name(pipe
));
145 high_frame
= PIPEFRAME(pipe
);
146 low_frame
= PIPEFRAMEPIXEL(pipe
);
149 * High & low register fields aren't synchronized, so make sure
150 * we get a low value that's stable across two reads of the high
154 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
155 low
= I915_READ(low_frame
) & PIPE_FRAME_LOW_MASK
;
156 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
157 } while (high1
!= high2
);
159 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
160 low
>>= PIPE_FRAME_LOW_SHIFT
;
161 return (high1
<< 8) | low
;
164 static u32
gm45_get_vblank_counter(struct drm_device
*dev
, int pipe
)
166 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
167 int reg
= PIPE_FRMCOUNT_GM45(pipe
);
169 if (!i915_pipe_enabled(dev
, pipe
)) {
170 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
171 "pipe %c\n", pipe_name(pipe
));
175 return I915_READ(reg
);
178 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, int pipe
,
179 int *vpos
, int *hpos
)
181 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
182 u32 vbl
= 0, position
= 0;
183 int vbl_start
, vbl_end
, htotal
, vtotal
;
187 if (!i915_pipe_enabled(dev
, pipe
)) {
188 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
189 "pipe %c\n", pipe_name(pipe
));
194 vtotal
= 1 + ((I915_READ(VTOTAL(pipe
)) >> 16) & 0x1fff);
196 if (INTEL_INFO(dev
)->gen
>= 4) {
197 /* No obvious pixelcount register. Only query vertical
198 * scanout position from Display scan line register.
200 position
= I915_READ(PIPEDSL(pipe
));
202 /* Decode into vertical scanout position. Don't have
203 * horizontal scanout position.
205 *vpos
= position
& 0x1fff;
208 /* Have access to pixelcount since start of frame.
209 * We can split this into vertical and horizontal
212 position
= (I915_READ(PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
214 htotal
= 1 + ((I915_READ(HTOTAL(pipe
)) >> 16) & 0x1fff);
215 *vpos
= position
/ htotal
;
216 *hpos
= position
- (*vpos
* htotal
);
219 /* Query vblank area. */
220 vbl
= I915_READ(VBLANK(pipe
));
222 /* Test position against vblank region. */
223 vbl_start
= vbl
& 0x1fff;
224 vbl_end
= (vbl
>> 16) & 0x1fff;
226 if ((*vpos
< vbl_start
) || (*vpos
> vbl_end
))
229 /* Inside "upper part" of vblank area? Apply corrective offset: */
230 if (in_vbl
&& (*vpos
>= vbl_start
))
231 *vpos
= *vpos
- vtotal
;
233 /* Readouts valid? */
235 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
239 ret
|= DRM_SCANOUTPOS_INVBL
;
244 static int i915_get_vblank_timestamp(struct drm_device
*dev
, int pipe
,
246 struct timeval
*vblank_time
,
249 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
250 struct drm_crtc
*crtc
;
252 if (pipe
< 0 || pipe
>= dev_priv
->num_pipe
) {
253 DRM_ERROR("Invalid crtc %d\n", pipe
);
257 /* Get drm_crtc to timestamp: */
258 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
260 DRM_ERROR("Invalid crtc %d\n", pipe
);
264 if (!crtc
->enabled
) {
265 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
269 /* Helper routine in DRM core does all the work: */
270 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
276 * Handle hotplug events outside the interrupt handler proper.
278 static void i915_hotplug_work_func(struct work_struct
*work
)
280 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
282 struct drm_device
*dev
= dev_priv
->dev
;
283 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
284 struct intel_encoder
*encoder
;
286 mutex_lock(&mode_config
->mutex
);
287 DRM_DEBUG_KMS("running encoder hotplug functions\n");
289 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
)
290 if (encoder
->hot_plug
)
291 encoder
->hot_plug(encoder
);
293 mutex_unlock(&mode_config
->mutex
);
295 /* Just fire off a uevent and let userspace tell us what to do */
296 drm_helper_hpd_irq_event(dev
);
299 /* defined intel_pm.c */
300 extern spinlock_t mchdev_lock
;
302 static void ironlake_handle_rps_change(struct drm_device
*dev
)
304 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
305 u32 busy_up
, busy_down
, max_avg
, min_avg
;
309 spin_lock_irqsave(&mchdev_lock
, flags
);
311 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
313 new_delay
= dev_priv
->ips
.cur_delay
;
315 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
316 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
317 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
318 max_avg
= I915_READ(RCBMAXAVG
);
319 min_avg
= I915_READ(RCBMINAVG
);
321 /* Handle RCS change request from hw */
322 if (busy_up
> max_avg
) {
323 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
324 new_delay
= dev_priv
->ips
.cur_delay
- 1;
325 if (new_delay
< dev_priv
->ips
.max_delay
)
326 new_delay
= dev_priv
->ips
.max_delay
;
327 } else if (busy_down
< min_avg
) {
328 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
329 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
330 if (new_delay
> dev_priv
->ips
.min_delay
)
331 new_delay
= dev_priv
->ips
.min_delay
;
334 if (ironlake_set_drps(dev
, new_delay
))
335 dev_priv
->ips
.cur_delay
= new_delay
;
337 spin_unlock_irqrestore(&mchdev_lock
, flags
);
342 static void notify_ring(struct drm_device
*dev
,
343 struct intel_ring_buffer
*ring
)
345 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
347 if (ring
->obj
== NULL
)
350 trace_i915_gem_request_complete(ring
, ring
->get_seqno(ring
, false));
352 wake_up_all(&ring
->irq_queue
);
353 if (i915_enable_hangcheck
) {
354 dev_priv
->hangcheck_count
= 0;
355 mod_timer(&dev_priv
->hangcheck_timer
,
357 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD
));
361 static void gen6_pm_rps_work(struct work_struct
*work
)
363 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
368 spin_lock_irq(&dev_priv
->rps
.lock
);
369 pm_iir
= dev_priv
->rps
.pm_iir
;
370 dev_priv
->rps
.pm_iir
= 0;
371 pm_imr
= I915_READ(GEN6_PMIMR
);
372 I915_WRITE(GEN6_PMIMR
, 0);
373 spin_unlock_irq(&dev_priv
->rps
.lock
);
375 if ((pm_iir
& GEN6_PM_DEFERRED_EVENTS
) == 0)
378 mutex_lock(&dev_priv
->dev
->struct_mutex
);
380 if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
)
381 new_delay
= dev_priv
->rps
.cur_delay
+ 1;
383 new_delay
= dev_priv
->rps
.cur_delay
- 1;
385 gen6_set_rps(dev_priv
->dev
, new_delay
);
387 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
392 * ivybridge_parity_work - Workqueue called when a parity error interrupt
394 * @work: workqueue struct
396 * Doesn't actually do anything except notify userspace. As a consequence of
397 * this event, userspace should try to remap the bad rows since statistically
398 * it is likely the same row is more likely to go bad again.
400 static void ivybridge_parity_work(struct work_struct
*work
)
402 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
404 u32 error_status
, row
, bank
, subbank
;
405 char *parity_event
[5];
409 /* We must turn off DOP level clock gating to access the L3 registers.
410 * In order to prevent a get/put style interface, acquire struct mutex
411 * any time we access those registers.
413 mutex_lock(&dev_priv
->dev
->struct_mutex
);
415 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
416 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
417 POSTING_READ(GEN7_MISCCPCTL
);
419 error_status
= I915_READ(GEN7_L3CDERRST1
);
420 row
= GEN7_PARITY_ERROR_ROW(error_status
);
421 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
422 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
424 I915_WRITE(GEN7_L3CDERRST1
, GEN7_PARITY_ERROR_VALID
|
425 GEN7_L3CDERRST1_ENABLE
);
426 POSTING_READ(GEN7_L3CDERRST1
);
428 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
430 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
431 dev_priv
->gt_irq_mask
&= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT
;
432 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
433 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
435 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
437 parity_event
[0] = "L3_PARITY_ERROR=1";
438 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
439 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
440 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
441 parity_event
[4] = NULL
;
443 kobject_uevent_env(&dev_priv
->dev
->primary
->kdev
.kobj
,
444 KOBJ_CHANGE
, parity_event
);
446 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
449 kfree(parity_event
[3]);
450 kfree(parity_event
[2]);
451 kfree(parity_event
[1]);
454 static void ivybridge_handle_parity_error(struct drm_device
*dev
)
456 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
459 if (!HAS_L3_GPU_CACHE(dev
))
462 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
463 dev_priv
->gt_irq_mask
|= GT_GEN7_L3_PARITY_ERROR_INTERRUPT
;
464 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
465 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
467 queue_work(dev_priv
->wq
, &dev_priv
->parity_error_work
);
470 static void snb_gt_irq_handler(struct drm_device
*dev
,
471 struct drm_i915_private
*dev_priv
,
475 if (gt_iir
& (GEN6_RENDER_USER_INTERRUPT
|
476 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT
))
477 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
478 if (gt_iir
& GEN6_BSD_USER_INTERRUPT
)
479 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
480 if (gt_iir
& GEN6_BLITTER_USER_INTERRUPT
)
481 notify_ring(dev
, &dev_priv
->ring
[BCS
]);
483 if (gt_iir
& (GT_GEN6_BLT_CS_ERROR_INTERRUPT
|
484 GT_GEN6_BSD_CS_ERROR_INTERRUPT
|
485 GT_RENDER_CS_ERROR_INTERRUPT
)) {
486 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir
);
487 i915_handle_error(dev
, false);
490 if (gt_iir
& GT_GEN7_L3_PARITY_ERROR_INTERRUPT
)
491 ivybridge_handle_parity_error(dev
);
494 static void gen6_queue_rps_work(struct drm_i915_private
*dev_priv
,
500 * IIR bits should never already be set because IMR should
501 * prevent an interrupt from being shown in IIR. The warning
502 * displays a case where we've unsafely cleared
503 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
504 * type is not a problem, it displays a problem in the logic.
506 * The mask bit in IMR is cleared by dev_priv->rps.work.
509 spin_lock_irqsave(&dev_priv
->rps
.lock
, flags
);
510 dev_priv
->rps
.pm_iir
|= pm_iir
;
511 I915_WRITE(GEN6_PMIMR
, dev_priv
->rps
.pm_iir
);
512 POSTING_READ(GEN6_PMIMR
);
513 spin_unlock_irqrestore(&dev_priv
->rps
.lock
, flags
);
515 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
518 static irqreturn_t
valleyview_irq_handler(DRM_IRQ_ARGS
)
520 struct drm_device
*dev
= (struct drm_device
*) arg
;
521 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
522 u32 iir
, gt_iir
, pm_iir
;
523 irqreturn_t ret
= IRQ_NONE
;
524 unsigned long irqflags
;
526 u32 pipe_stats
[I915_MAX_PIPES
];
529 atomic_inc(&dev_priv
->irq_received
);
532 iir
= I915_READ(VLV_IIR
);
533 gt_iir
= I915_READ(GTIIR
);
534 pm_iir
= I915_READ(GEN6_PMIIR
);
536 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
541 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
543 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
544 for_each_pipe(pipe
) {
545 int reg
= PIPESTAT(pipe
);
546 pipe_stats
[pipe
] = I915_READ(reg
);
549 * Clear the PIPE*STAT regs before the IIR
551 if (pipe_stats
[pipe
] & 0x8000ffff) {
552 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
553 DRM_DEBUG_DRIVER("pipe %c underrun\n",
555 I915_WRITE(reg
, pipe_stats
[pipe
]);
558 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
560 for_each_pipe(pipe
) {
561 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
)
562 drm_handle_vblank(dev
, pipe
);
564 if (pipe_stats
[pipe
] & PLANE_FLIPDONE_INT_STATUS_VLV
) {
565 intel_prepare_page_flip(dev
, pipe
);
566 intel_finish_page_flip(dev
, pipe
);
570 /* Consume port. Then clear IIR or we'll miss events */
571 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
572 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
574 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
576 if (hotplug_status
& dev_priv
->hotplug_supported_mask
)
577 queue_work(dev_priv
->wq
,
578 &dev_priv
->hotplug_work
);
580 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
581 I915_READ(PORT_HOTPLUG_STAT
);
584 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
587 if (pm_iir
& GEN6_PM_DEFERRED_EVENTS
)
588 gen6_queue_rps_work(dev_priv
, pm_iir
);
590 I915_WRITE(GTIIR
, gt_iir
);
591 I915_WRITE(GEN6_PMIIR
, pm_iir
);
592 I915_WRITE(VLV_IIR
, iir
);
599 static void ibx_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
601 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
604 if (pch_iir
& SDE_AUDIO_POWER_MASK
)
605 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
606 (pch_iir
& SDE_AUDIO_POWER_MASK
) >>
607 SDE_AUDIO_POWER_SHIFT
);
609 if (pch_iir
& SDE_GMBUS
)
610 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
612 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
613 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
615 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
616 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
618 if (pch_iir
& SDE_POISON
)
619 DRM_ERROR("PCH poison interrupt\n");
621 if (pch_iir
& SDE_FDI_MASK
)
623 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
625 I915_READ(FDI_RX_IIR(pipe
)));
627 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
628 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
630 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
631 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
633 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
634 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
635 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
636 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
639 static void cpt_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
641 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
644 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
)
645 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
646 (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
647 SDE_AUDIO_POWER_SHIFT_CPT
);
649 if (pch_iir
& SDE_AUX_MASK_CPT
)
650 DRM_DEBUG_DRIVER("AUX channel interrupt\n");
652 if (pch_iir
& SDE_GMBUS_CPT
)
653 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
655 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
656 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
658 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
659 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
661 if (pch_iir
& SDE_FDI_MASK_CPT
)
663 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
665 I915_READ(FDI_RX_IIR(pipe
)));
668 static irqreturn_t
ivybridge_irq_handler(DRM_IRQ_ARGS
)
670 struct drm_device
*dev
= (struct drm_device
*) arg
;
671 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
672 u32 de_iir
, gt_iir
, de_ier
, pm_iir
;
673 irqreturn_t ret
= IRQ_NONE
;
676 atomic_inc(&dev_priv
->irq_received
);
678 /* disable master interrupt before clearing iir */
679 de_ier
= I915_READ(DEIER
);
680 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
682 gt_iir
= I915_READ(GTIIR
);
684 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
685 I915_WRITE(GTIIR
, gt_iir
);
689 de_iir
= I915_READ(DEIIR
);
691 if (de_iir
& DE_GSE_IVB
)
692 intel_opregion_gse_intr(dev
);
694 for (i
= 0; i
< 3; i
++) {
695 if (de_iir
& (DE_PLANEA_FLIP_DONE_IVB
<< (5 * i
))) {
696 intel_prepare_page_flip(dev
, i
);
697 intel_finish_page_flip_plane(dev
, i
);
699 if (de_iir
& (DE_PIPEA_VBLANK_IVB
<< (5 * i
)))
700 drm_handle_vblank(dev
, i
);
703 /* check event from PCH */
704 if (de_iir
& DE_PCH_EVENT_IVB
) {
705 u32 pch_iir
= I915_READ(SDEIIR
);
707 if (pch_iir
& SDE_HOTPLUG_MASK_CPT
)
708 queue_work(dev_priv
->wq
, &dev_priv
->hotplug_work
);
709 cpt_irq_handler(dev
, pch_iir
);
711 /* clear PCH hotplug event before clear CPU irq */
712 I915_WRITE(SDEIIR
, pch_iir
);
715 I915_WRITE(DEIIR
, de_iir
);
719 pm_iir
= I915_READ(GEN6_PMIIR
);
721 if (pm_iir
& GEN6_PM_DEFERRED_EVENTS
)
722 gen6_queue_rps_work(dev_priv
, pm_iir
);
723 I915_WRITE(GEN6_PMIIR
, pm_iir
);
727 I915_WRITE(DEIER
, de_ier
);
733 static void ilk_gt_irq_handler(struct drm_device
*dev
,
734 struct drm_i915_private
*dev_priv
,
737 if (gt_iir
& (GT_USER_INTERRUPT
| GT_PIPE_NOTIFY
))
738 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
739 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
740 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
743 static irqreturn_t
ironlake_irq_handler(DRM_IRQ_ARGS
)
745 struct drm_device
*dev
= (struct drm_device
*) arg
;
746 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
748 u32 de_iir
, gt_iir
, de_ier
, pch_iir
, pm_iir
;
751 atomic_inc(&dev_priv
->irq_received
);
753 /* disable master interrupt before clearing iir */
754 de_ier
= I915_READ(DEIER
);
755 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
758 de_iir
= I915_READ(DEIIR
);
759 gt_iir
= I915_READ(GTIIR
);
760 pch_iir
= I915_READ(SDEIIR
);
761 pm_iir
= I915_READ(GEN6_PMIIR
);
763 if (de_iir
== 0 && gt_iir
== 0 && pch_iir
== 0 &&
764 (!IS_GEN6(dev
) || pm_iir
== 0))
767 if (HAS_PCH_CPT(dev
))
768 hotplug_mask
= SDE_HOTPLUG_MASK_CPT
;
770 hotplug_mask
= SDE_HOTPLUG_MASK
;
775 ilk_gt_irq_handler(dev
, dev_priv
, gt_iir
);
777 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
780 intel_opregion_gse_intr(dev
);
782 if (de_iir
& DE_PLANEA_FLIP_DONE
) {
783 intel_prepare_page_flip(dev
, 0);
784 intel_finish_page_flip_plane(dev
, 0);
787 if (de_iir
& DE_PLANEB_FLIP_DONE
) {
788 intel_prepare_page_flip(dev
, 1);
789 intel_finish_page_flip_plane(dev
, 1);
792 if (de_iir
& DE_PIPEA_VBLANK
)
793 drm_handle_vblank(dev
, 0);
795 if (de_iir
& DE_PIPEB_VBLANK
)
796 drm_handle_vblank(dev
, 1);
798 /* check event from PCH */
799 if (de_iir
& DE_PCH_EVENT
) {
800 if (pch_iir
& hotplug_mask
)
801 queue_work(dev_priv
->wq
, &dev_priv
->hotplug_work
);
802 if (HAS_PCH_CPT(dev
))
803 cpt_irq_handler(dev
, pch_iir
);
805 ibx_irq_handler(dev
, pch_iir
);
808 if (IS_GEN5(dev
) && de_iir
& DE_PCU_EVENT
)
809 ironlake_handle_rps_change(dev
);
811 if (IS_GEN6(dev
) && pm_iir
& GEN6_PM_DEFERRED_EVENTS
)
812 gen6_queue_rps_work(dev_priv
, pm_iir
);
814 /* should clear PCH hotplug event before clear CPU irq */
815 I915_WRITE(SDEIIR
, pch_iir
);
816 I915_WRITE(GTIIR
, gt_iir
);
817 I915_WRITE(DEIIR
, de_iir
);
818 I915_WRITE(GEN6_PMIIR
, pm_iir
);
821 I915_WRITE(DEIER
, de_ier
);
828 * i915_error_work_func - do process context error handling work
831 * Fire an error uevent so userspace can see that a hang or error
834 static void i915_error_work_func(struct work_struct
*work
)
836 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
838 struct drm_device
*dev
= dev_priv
->dev
;
839 char *error_event
[] = { "ERROR=1", NULL
};
840 char *reset_event
[] = { "RESET=1", NULL
};
841 char *reset_done_event
[] = { "ERROR=0", NULL
};
843 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
, error_event
);
845 if (atomic_read(&dev_priv
->mm
.wedged
)) {
846 DRM_DEBUG_DRIVER("resetting chip\n");
847 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
, reset_event
);
848 if (!i915_reset(dev
)) {
849 atomic_set(&dev_priv
->mm
.wedged
, 0);
850 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
, reset_done_event
);
852 complete_all(&dev_priv
->error_completion
);
856 /* NB: please notice the memset */
857 static void i915_get_extra_instdone(struct drm_device
*dev
,
860 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
861 memset(instdone
, 0, sizeof(*instdone
) * I915_NUM_INSTDONE_REG
);
863 switch(INTEL_INFO(dev
)->gen
) {
866 instdone
[0] = I915_READ(INSTDONE
);
871 instdone
[0] = I915_READ(INSTDONE_I965
);
872 instdone
[1] = I915_READ(INSTDONE1
);
875 WARN_ONCE(1, "Unsupported platform\n");
877 instdone
[0] = I915_READ(GEN7_INSTDONE_1
);
878 instdone
[1] = I915_READ(GEN7_SC_INSTDONE
);
879 instdone
[2] = I915_READ(GEN7_SAMPLER_INSTDONE
);
880 instdone
[3] = I915_READ(GEN7_ROW_INSTDONE
);
885 #ifdef CONFIG_DEBUG_FS
886 static struct drm_i915_error_object
*
887 i915_error_object_create(struct drm_i915_private
*dev_priv
,
888 struct drm_i915_gem_object
*src
)
890 struct drm_i915_error_object
*dst
;
894 if (src
== NULL
|| src
->pages
== NULL
)
897 count
= src
->base
.size
/ PAGE_SIZE
;
899 dst
= kmalloc(sizeof(*dst
) + count
* sizeof(u32
*), GFP_ATOMIC
);
903 reloc_offset
= src
->gtt_offset
;
904 for (i
= 0; i
< count
; i
++) {
908 d
= kmalloc(PAGE_SIZE
, GFP_ATOMIC
);
912 local_irq_save(flags
);
913 if (reloc_offset
< dev_priv
->mm
.gtt_mappable_end
&&
914 src
->has_global_gtt_mapping
) {
917 /* Simply ignore tiling or any overlapping fence.
918 * It's part of the error state, and this hopefully
919 * captures what the GPU read.
922 s
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
924 memcpy_fromio(d
, s
, PAGE_SIZE
);
925 io_mapping_unmap_atomic(s
);
930 page
= i915_gem_object_get_page(src
, i
);
932 drm_clflush_pages(&page
, 1);
934 s
= kmap_atomic(page
);
935 memcpy(d
, s
, PAGE_SIZE
);
938 drm_clflush_pages(&page
, 1);
940 local_irq_restore(flags
);
944 reloc_offset
+= PAGE_SIZE
;
946 dst
->page_count
= count
;
947 dst
->gtt_offset
= src
->gtt_offset
;
953 kfree(dst
->pages
[i
]);
959 i915_error_object_free(struct drm_i915_error_object
*obj
)
966 for (page
= 0; page
< obj
->page_count
; page
++)
967 kfree(obj
->pages
[page
]);
973 i915_error_state_free(struct kref
*error_ref
)
975 struct drm_i915_error_state
*error
= container_of(error_ref
,
976 typeof(*error
), ref
);
979 for (i
= 0; i
< ARRAY_SIZE(error
->ring
); i
++) {
980 i915_error_object_free(error
->ring
[i
].batchbuffer
);
981 i915_error_object_free(error
->ring
[i
].ringbuffer
);
982 kfree(error
->ring
[i
].requests
);
985 kfree(error
->active_bo
);
986 kfree(error
->overlay
);
989 static void capture_bo(struct drm_i915_error_buffer
*err
,
990 struct drm_i915_gem_object
*obj
)
992 err
->size
= obj
->base
.size
;
993 err
->name
= obj
->base
.name
;
994 err
->rseqno
= obj
->last_read_seqno
;
995 err
->wseqno
= obj
->last_write_seqno
;
996 err
->gtt_offset
= obj
->gtt_offset
;
997 err
->read_domains
= obj
->base
.read_domains
;
998 err
->write_domain
= obj
->base
.write_domain
;
999 err
->fence_reg
= obj
->fence_reg
;
1001 if (obj
->pin_count
> 0)
1003 if (obj
->user_pin_count
> 0)
1005 err
->tiling
= obj
->tiling_mode
;
1006 err
->dirty
= obj
->dirty
;
1007 err
->purgeable
= obj
->madv
!= I915_MADV_WILLNEED
;
1008 err
->ring
= obj
->ring
? obj
->ring
->id
: -1;
1009 err
->cache_level
= obj
->cache_level
;
1012 static u32
capture_active_bo(struct drm_i915_error_buffer
*err
,
1013 int count
, struct list_head
*head
)
1015 struct drm_i915_gem_object
*obj
;
1018 list_for_each_entry(obj
, head
, mm_list
) {
1019 capture_bo(err
++, obj
);
1027 static u32
capture_pinned_bo(struct drm_i915_error_buffer
*err
,
1028 int count
, struct list_head
*head
)
1030 struct drm_i915_gem_object
*obj
;
1033 list_for_each_entry(obj
, head
, gtt_list
) {
1034 if (obj
->pin_count
== 0)
1037 capture_bo(err
++, obj
);
1045 static void i915_gem_record_fences(struct drm_device
*dev
,
1046 struct drm_i915_error_state
*error
)
1048 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1052 switch (INTEL_INFO(dev
)->gen
) {
1055 for (i
= 0; i
< 16; i
++)
1056 error
->fence
[i
] = I915_READ64(FENCE_REG_SANDYBRIDGE_0
+ (i
* 8));
1060 for (i
= 0; i
< 16; i
++)
1061 error
->fence
[i
] = I915_READ64(FENCE_REG_965_0
+ (i
* 8));
1064 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
1065 for (i
= 0; i
< 8; i
++)
1066 error
->fence
[i
+8] = I915_READ(FENCE_REG_945_8
+ (i
* 4));
1068 for (i
= 0; i
< 8; i
++)
1069 error
->fence
[i
] = I915_READ(FENCE_REG_830_0
+ (i
* 4));
1075 static struct drm_i915_error_object
*
1076 i915_error_first_batchbuffer(struct drm_i915_private
*dev_priv
,
1077 struct intel_ring_buffer
*ring
)
1079 struct drm_i915_gem_object
*obj
;
1082 if (!ring
->get_seqno
)
1085 seqno
= ring
->get_seqno(ring
, false);
1086 list_for_each_entry(obj
, &dev_priv
->mm
.active_list
, mm_list
) {
1087 if (obj
->ring
!= ring
)
1090 if (i915_seqno_passed(seqno
, obj
->last_read_seqno
))
1093 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_COMMAND
) == 0)
1096 /* We need to copy these to an anonymous buffer as the simplest
1097 * method to avoid being overwritten by userspace.
1099 return i915_error_object_create(dev_priv
, obj
);
1105 static void i915_record_ring_state(struct drm_device
*dev
,
1106 struct drm_i915_error_state
*error
,
1107 struct intel_ring_buffer
*ring
)
1109 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1111 if (INTEL_INFO(dev
)->gen
>= 6) {
1112 error
->rc_psmi
[ring
->id
] = I915_READ(ring
->mmio_base
+ 0x50);
1113 error
->fault_reg
[ring
->id
] = I915_READ(RING_FAULT_REG(ring
));
1114 error
->semaphore_mboxes
[ring
->id
][0]
1115 = I915_READ(RING_SYNC_0(ring
->mmio_base
));
1116 error
->semaphore_mboxes
[ring
->id
][1]
1117 = I915_READ(RING_SYNC_1(ring
->mmio_base
));
1120 if (INTEL_INFO(dev
)->gen
>= 4) {
1121 error
->faddr
[ring
->id
] = I915_READ(RING_DMA_FADD(ring
->mmio_base
));
1122 error
->ipeir
[ring
->id
] = I915_READ(RING_IPEIR(ring
->mmio_base
));
1123 error
->ipehr
[ring
->id
] = I915_READ(RING_IPEHR(ring
->mmio_base
));
1124 error
->instdone
[ring
->id
] = I915_READ(RING_INSTDONE(ring
->mmio_base
));
1125 error
->instps
[ring
->id
] = I915_READ(RING_INSTPS(ring
->mmio_base
));
1126 if (ring
->id
== RCS
)
1127 error
->bbaddr
= I915_READ64(BB_ADDR
);
1129 error
->faddr
[ring
->id
] = I915_READ(DMA_FADD_I8XX
);
1130 error
->ipeir
[ring
->id
] = I915_READ(IPEIR
);
1131 error
->ipehr
[ring
->id
] = I915_READ(IPEHR
);
1132 error
->instdone
[ring
->id
] = I915_READ(INSTDONE
);
1135 error
->waiting
[ring
->id
] = waitqueue_active(&ring
->irq_queue
);
1136 error
->instpm
[ring
->id
] = I915_READ(RING_INSTPM(ring
->mmio_base
));
1137 error
->seqno
[ring
->id
] = ring
->get_seqno(ring
, false);
1138 error
->acthd
[ring
->id
] = intel_ring_get_active_head(ring
);
1139 error
->head
[ring
->id
] = I915_READ_HEAD(ring
);
1140 error
->tail
[ring
->id
] = I915_READ_TAIL(ring
);
1142 error
->cpu_ring_head
[ring
->id
] = ring
->head
;
1143 error
->cpu_ring_tail
[ring
->id
] = ring
->tail
;
1146 static void i915_gem_record_rings(struct drm_device
*dev
,
1147 struct drm_i915_error_state
*error
)
1149 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1150 struct intel_ring_buffer
*ring
;
1151 struct drm_i915_gem_request
*request
;
1154 for_each_ring(ring
, dev_priv
, i
) {
1155 i915_record_ring_state(dev
, error
, ring
);
1157 error
->ring
[i
].batchbuffer
=
1158 i915_error_first_batchbuffer(dev_priv
, ring
);
1160 error
->ring
[i
].ringbuffer
=
1161 i915_error_object_create(dev_priv
, ring
->obj
);
1164 list_for_each_entry(request
, &ring
->request_list
, list
)
1167 error
->ring
[i
].num_requests
= count
;
1168 error
->ring
[i
].requests
=
1169 kmalloc(count
*sizeof(struct drm_i915_error_request
),
1171 if (error
->ring
[i
].requests
== NULL
) {
1172 error
->ring
[i
].num_requests
= 0;
1177 list_for_each_entry(request
, &ring
->request_list
, list
) {
1178 struct drm_i915_error_request
*erq
;
1180 erq
= &error
->ring
[i
].requests
[count
++];
1181 erq
->seqno
= request
->seqno
;
1182 erq
->jiffies
= request
->emitted_jiffies
;
1183 erq
->tail
= request
->tail
;
1189 * i915_capture_error_state - capture an error record for later analysis
1192 * Should be called when an error is detected (either a hang or an error
1193 * interrupt) to capture error state from the time of the error. Fills
1194 * out a structure which becomes available in debugfs for user level tools
1197 static void i915_capture_error_state(struct drm_device
*dev
)
1199 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1200 struct drm_i915_gem_object
*obj
;
1201 struct drm_i915_error_state
*error
;
1202 unsigned long flags
;
1205 spin_lock_irqsave(&dev_priv
->error_lock
, flags
);
1206 error
= dev_priv
->first_error
;
1207 spin_unlock_irqrestore(&dev_priv
->error_lock
, flags
);
1211 /* Account for pipe specific data like PIPE*STAT */
1212 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
1214 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1218 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1219 dev
->primary
->index
);
1221 kref_init(&error
->ref
);
1222 error
->eir
= I915_READ(EIR
);
1223 error
->pgtbl_er
= I915_READ(PGTBL_ER
);
1224 error
->ccid
= I915_READ(CCID
);
1226 if (HAS_PCH_SPLIT(dev
))
1227 error
->ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
1228 else if (IS_VALLEYVIEW(dev
))
1229 error
->ier
= I915_READ(GTIER
) | I915_READ(VLV_IER
);
1230 else if (IS_GEN2(dev
))
1231 error
->ier
= I915_READ16(IER
);
1233 error
->ier
= I915_READ(IER
);
1236 error
->pipestat
[pipe
] = I915_READ(PIPESTAT(pipe
));
1238 if (INTEL_INFO(dev
)->gen
>= 6) {
1239 error
->error
= I915_READ(ERROR_GEN6
);
1240 error
->done_reg
= I915_READ(DONE_REG
);
1243 if (INTEL_INFO(dev
)->gen
== 7)
1244 error
->err_int
= I915_READ(GEN7_ERR_INT
);
1246 i915_get_extra_instdone(dev
, error
->extra_instdone
);
1248 i915_gem_record_fences(dev
, error
);
1249 i915_gem_record_rings(dev
, error
);
1251 /* Record buffers on the active and pinned lists. */
1252 error
->active_bo
= NULL
;
1253 error
->pinned_bo
= NULL
;
1256 list_for_each_entry(obj
, &dev_priv
->mm
.active_list
, mm_list
)
1258 error
->active_bo_count
= i
;
1259 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, gtt_list
)
1262 error
->pinned_bo_count
= i
- error
->active_bo_count
;
1264 error
->active_bo
= NULL
;
1265 error
->pinned_bo
= NULL
;
1267 error
->active_bo
= kmalloc(sizeof(*error
->active_bo
)*i
,
1269 if (error
->active_bo
)
1271 error
->active_bo
+ error
->active_bo_count
;
1274 if (error
->active_bo
)
1275 error
->active_bo_count
=
1276 capture_active_bo(error
->active_bo
,
1277 error
->active_bo_count
,
1278 &dev_priv
->mm
.active_list
);
1280 if (error
->pinned_bo
)
1281 error
->pinned_bo_count
=
1282 capture_pinned_bo(error
->pinned_bo
,
1283 error
->pinned_bo_count
,
1284 &dev_priv
->mm
.bound_list
);
1286 do_gettimeofday(&error
->time
);
1288 error
->overlay
= intel_overlay_capture_error_state(dev
);
1289 error
->display
= intel_display_capture_error_state(dev
);
1291 spin_lock_irqsave(&dev_priv
->error_lock
, flags
);
1292 if (dev_priv
->first_error
== NULL
) {
1293 dev_priv
->first_error
= error
;
1296 spin_unlock_irqrestore(&dev_priv
->error_lock
, flags
);
1299 i915_error_state_free(&error
->ref
);
1302 void i915_destroy_error_state(struct drm_device
*dev
)
1304 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1305 struct drm_i915_error_state
*error
;
1306 unsigned long flags
;
1308 spin_lock_irqsave(&dev_priv
->error_lock
, flags
);
1309 error
= dev_priv
->first_error
;
1310 dev_priv
->first_error
= NULL
;
1311 spin_unlock_irqrestore(&dev_priv
->error_lock
, flags
);
1314 kref_put(&error
->ref
, i915_error_state_free
);
1317 #define i915_capture_error_state(x)
1320 static void i915_report_and_clear_eir(struct drm_device
*dev
)
1322 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1323 uint32_t instdone
[I915_NUM_INSTDONE_REG
];
1324 u32 eir
= I915_READ(EIR
);
1330 pr_err("render error detected, EIR: 0x%08x\n", eir
);
1332 i915_get_extra_instdone(dev
, instdone
);
1335 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
1336 u32 ipeir
= I915_READ(IPEIR_I965
);
1338 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1339 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1340 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
1341 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
1342 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1343 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1344 I915_WRITE(IPEIR_I965
, ipeir
);
1345 POSTING_READ(IPEIR_I965
);
1347 if (eir
& GM45_ERROR_PAGE_TABLE
) {
1348 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1349 pr_err("page table error\n");
1350 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1351 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1352 POSTING_READ(PGTBL_ER
);
1356 if (!IS_GEN2(dev
)) {
1357 if (eir
& I915_ERROR_PAGE_TABLE
) {
1358 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1359 pr_err("page table error\n");
1360 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1361 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1362 POSTING_READ(PGTBL_ER
);
1366 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
1367 pr_err("memory refresh error:\n");
1369 pr_err("pipe %c stat: 0x%08x\n",
1370 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
1371 /* pipestat has already been acked */
1373 if (eir
& I915_ERROR_INSTRUCTION
) {
1374 pr_err("instruction error\n");
1375 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
1376 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
1377 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
1378 if (INTEL_INFO(dev
)->gen
< 4) {
1379 u32 ipeir
= I915_READ(IPEIR
);
1381 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
1382 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
1383 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
1384 I915_WRITE(IPEIR
, ipeir
);
1385 POSTING_READ(IPEIR
);
1387 u32 ipeir
= I915_READ(IPEIR_I965
);
1389 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1390 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1391 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1392 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1393 I915_WRITE(IPEIR_I965
, ipeir
);
1394 POSTING_READ(IPEIR_I965
);
1398 I915_WRITE(EIR
, eir
);
1400 eir
= I915_READ(EIR
);
1403 * some errors might have become stuck,
1406 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
1407 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
1408 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
1413 * i915_handle_error - handle an error interrupt
1416 * Do some basic checking of regsiter state at error interrupt time and
1417 * dump it to the syslog. Also call i915_capture_error_state() to make
1418 * sure we get a record and make it available in debugfs. Fire a uevent
1419 * so userspace knows something bad happened (should trigger collection
1420 * of a ring dump etc.).
1422 void i915_handle_error(struct drm_device
*dev
, bool wedged
)
1424 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1425 struct intel_ring_buffer
*ring
;
1428 i915_capture_error_state(dev
);
1429 i915_report_and_clear_eir(dev
);
1432 INIT_COMPLETION(dev_priv
->error_completion
);
1433 atomic_set(&dev_priv
->mm
.wedged
, 1);
1436 * Wakeup waiting processes so they don't hang
1438 for_each_ring(ring
, dev_priv
, i
)
1439 wake_up_all(&ring
->irq_queue
);
1442 queue_work(dev_priv
->wq
, &dev_priv
->error_work
);
1445 static void i915_pageflip_stall_check(struct drm_device
*dev
, int pipe
)
1447 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1448 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1449 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1450 struct drm_i915_gem_object
*obj
;
1451 struct intel_unpin_work
*work
;
1452 unsigned long flags
;
1453 bool stall_detected
;
1455 /* Ignore early vblank irqs */
1456 if (intel_crtc
== NULL
)
1459 spin_lock_irqsave(&dev
->event_lock
, flags
);
1460 work
= intel_crtc
->unpin_work
;
1462 if (work
== NULL
|| work
->pending
|| !work
->enable_stall_check
) {
1463 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1464 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1468 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1469 obj
= work
->pending_flip_obj
;
1470 if (INTEL_INFO(dev
)->gen
>= 4) {
1471 int dspsurf
= DSPSURF(intel_crtc
->plane
);
1472 stall_detected
= I915_HI_DISPBASE(I915_READ(dspsurf
)) ==
1475 int dspaddr
= DSPADDR(intel_crtc
->plane
);
1476 stall_detected
= I915_READ(dspaddr
) == (obj
->gtt_offset
+
1477 crtc
->y
* crtc
->fb
->pitches
[0] +
1478 crtc
->x
* crtc
->fb
->bits_per_pixel
/8);
1481 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1483 if (stall_detected
) {
1484 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1485 intel_prepare_page_flip(dev
, intel_crtc
->plane
);
1489 /* Called from drm generic code, passed 'crtc' which
1490 * we use as a pipe index
1492 static int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
1494 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1495 unsigned long irqflags
;
1497 if (!i915_pipe_enabled(dev
, pipe
))
1500 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1501 if (INTEL_INFO(dev
)->gen
>= 4)
1502 i915_enable_pipestat(dev_priv
, pipe
,
1503 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1505 i915_enable_pipestat(dev_priv
, pipe
,
1506 PIPE_VBLANK_INTERRUPT_ENABLE
);
1508 /* maintain vblank delivery even in deep C-states */
1509 if (dev_priv
->info
->gen
== 3)
1510 I915_WRITE(INSTPM
, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS
));
1511 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1516 static int ironlake_enable_vblank(struct drm_device
*dev
, int pipe
)
1518 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1519 unsigned long irqflags
;
1521 if (!i915_pipe_enabled(dev
, pipe
))
1524 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1525 ironlake_enable_display_irq(dev_priv
, (pipe
== 0) ?
1526 DE_PIPEA_VBLANK
: DE_PIPEB_VBLANK
);
1527 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1532 static int ivybridge_enable_vblank(struct drm_device
*dev
, int pipe
)
1534 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1535 unsigned long irqflags
;
1537 if (!i915_pipe_enabled(dev
, pipe
))
1540 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1541 ironlake_enable_display_irq(dev_priv
,
1542 DE_PIPEA_VBLANK_IVB
<< (5 * pipe
));
1543 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1548 static int valleyview_enable_vblank(struct drm_device
*dev
, int pipe
)
1550 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1551 unsigned long irqflags
;
1554 if (!i915_pipe_enabled(dev
, pipe
))
1557 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1558 imr
= I915_READ(VLV_IMR
);
1560 imr
&= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
1562 imr
&= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1563 I915_WRITE(VLV_IMR
, imr
);
1564 i915_enable_pipestat(dev_priv
, pipe
,
1565 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1566 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1571 /* Called from drm generic code, passed 'crtc' which
1572 * we use as a pipe index
1574 static void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
1576 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1577 unsigned long irqflags
;
1579 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1580 if (dev_priv
->info
->gen
== 3)
1581 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS
));
1583 i915_disable_pipestat(dev_priv
, pipe
,
1584 PIPE_VBLANK_INTERRUPT_ENABLE
|
1585 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1586 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1589 static void ironlake_disable_vblank(struct drm_device
*dev
, int pipe
)
1591 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1592 unsigned long irqflags
;
1594 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1595 ironlake_disable_display_irq(dev_priv
, (pipe
== 0) ?
1596 DE_PIPEA_VBLANK
: DE_PIPEB_VBLANK
);
1597 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1600 static void ivybridge_disable_vblank(struct drm_device
*dev
, int pipe
)
1602 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1603 unsigned long irqflags
;
1605 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1606 ironlake_disable_display_irq(dev_priv
,
1607 DE_PIPEA_VBLANK_IVB
<< (pipe
* 5));
1608 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1611 static void valleyview_disable_vblank(struct drm_device
*dev
, int pipe
)
1613 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1614 unsigned long irqflags
;
1617 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1618 i915_disable_pipestat(dev_priv
, pipe
,
1619 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1620 imr
= I915_READ(VLV_IMR
);
1622 imr
|= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
1624 imr
|= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1625 I915_WRITE(VLV_IMR
, imr
);
1626 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1630 ring_last_seqno(struct intel_ring_buffer
*ring
)
1632 return list_entry(ring
->request_list
.prev
,
1633 struct drm_i915_gem_request
, list
)->seqno
;
1636 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer
*ring
, bool *err
)
1638 if (list_empty(&ring
->request_list
) ||
1639 i915_seqno_passed(ring
->get_seqno(ring
, false),
1640 ring_last_seqno(ring
))) {
1641 /* Issue a wake-up to catch stuck h/w. */
1642 if (waitqueue_active(&ring
->irq_queue
)) {
1643 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1645 wake_up_all(&ring
->irq_queue
);
1653 static bool kick_ring(struct intel_ring_buffer
*ring
)
1655 struct drm_device
*dev
= ring
->dev
;
1656 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1657 u32 tmp
= I915_READ_CTL(ring
);
1658 if (tmp
& RING_WAIT
) {
1659 DRM_ERROR("Kicking stuck wait on %s\n",
1661 I915_WRITE_CTL(ring
, tmp
);
1667 static bool i915_hangcheck_hung(struct drm_device
*dev
)
1669 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1671 if (dev_priv
->hangcheck_count
++ > 1) {
1674 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1675 i915_handle_error(dev
, true);
1677 if (!IS_GEN2(dev
)) {
1678 struct intel_ring_buffer
*ring
;
1681 /* Is the chip hanging on a WAIT_FOR_EVENT?
1682 * If so we can simply poke the RB_WAIT bit
1683 * and break the hang. This should work on
1684 * all but the second generation chipsets.
1686 for_each_ring(ring
, dev_priv
, i
)
1687 hung
&= !kick_ring(ring
);
1697 * This is called when the chip hasn't reported back with completed
1698 * batchbuffers in a long time. The first time this is called we simply record
1699 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1700 * again, we assume the chip is wedged and try to fix it.
1702 void i915_hangcheck_elapsed(unsigned long data
)
1704 struct drm_device
*dev
= (struct drm_device
*)data
;
1705 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1706 uint32_t acthd
[I915_NUM_RINGS
], instdone
[I915_NUM_INSTDONE_REG
];
1707 struct intel_ring_buffer
*ring
;
1708 bool err
= false, idle
;
1711 if (!i915_enable_hangcheck
)
1714 memset(acthd
, 0, sizeof(acthd
));
1716 for_each_ring(ring
, dev_priv
, i
) {
1717 idle
&= i915_hangcheck_ring_idle(ring
, &err
);
1718 acthd
[i
] = intel_ring_get_active_head(ring
);
1721 /* If all work is done then ACTHD clearly hasn't advanced. */
1724 if (i915_hangcheck_hung(dev
))
1730 dev_priv
->hangcheck_count
= 0;
1734 i915_get_extra_instdone(dev
, instdone
);
1735 if (memcmp(dev_priv
->last_acthd
, acthd
, sizeof(acthd
)) == 0 &&
1736 memcmp(dev_priv
->prev_instdone
, instdone
, sizeof(instdone
)) == 0) {
1737 if (i915_hangcheck_hung(dev
))
1740 dev_priv
->hangcheck_count
= 0;
1742 memcpy(dev_priv
->last_acthd
, acthd
, sizeof(acthd
));
1743 memcpy(dev_priv
->prev_instdone
, instdone
, sizeof(instdone
));
1747 /* Reset timer case chip hangs without another request being added */
1748 mod_timer(&dev_priv
->hangcheck_timer
,
1749 jiffies
+ msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD
));
1754 static void ironlake_irq_preinstall(struct drm_device
*dev
)
1756 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1758 atomic_set(&dev_priv
->irq_received
, 0);
1760 I915_WRITE(HWSTAM
, 0xeffe);
1762 /* XXX hotplug from PCH */
1764 I915_WRITE(DEIMR
, 0xffffffff);
1765 I915_WRITE(DEIER
, 0x0);
1766 POSTING_READ(DEIER
);
1769 I915_WRITE(GTIMR
, 0xffffffff);
1770 I915_WRITE(GTIER
, 0x0);
1771 POSTING_READ(GTIER
);
1773 /* south display irq */
1774 I915_WRITE(SDEIMR
, 0xffffffff);
1775 I915_WRITE(SDEIER
, 0x0);
1776 POSTING_READ(SDEIER
);
1779 static void valleyview_irq_preinstall(struct drm_device
*dev
)
1781 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1784 atomic_set(&dev_priv
->irq_received
, 0);
1787 I915_WRITE(VLV_IMR
, 0);
1788 I915_WRITE(RING_IMR(RENDER_RING_BASE
), 0);
1789 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE
), 0);
1790 I915_WRITE(RING_IMR(BLT_RING_BASE
), 0);
1793 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
1794 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
1795 I915_WRITE(GTIMR
, 0xffffffff);
1796 I915_WRITE(GTIER
, 0x0);
1797 POSTING_READ(GTIER
);
1799 I915_WRITE(DPINVGTT
, 0xff);
1801 I915_WRITE(PORT_HOTPLUG_EN
, 0);
1802 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
1804 I915_WRITE(PIPESTAT(pipe
), 0xffff);
1805 I915_WRITE(VLV_IIR
, 0xffffffff);
1806 I915_WRITE(VLV_IMR
, 0xffffffff);
1807 I915_WRITE(VLV_IER
, 0x0);
1808 POSTING_READ(VLV_IER
);
1812 * Enable digital hotplug on the PCH, and configure the DP short pulse
1813 * duration to 2ms (which is the minimum in the Display Port spec)
1815 * This register is the same on all known PCH chips.
1818 static void ironlake_enable_pch_hotplug(struct drm_device
*dev
)
1820 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1823 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
1824 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
1825 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
1826 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
1827 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
1828 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
1831 static int ironlake_irq_postinstall(struct drm_device
*dev
)
1833 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1834 /* enable kind of interrupts always enabled */
1835 u32 display_mask
= DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
1836 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
;
1840 dev_priv
->irq_mask
= ~display_mask
;
1842 /* should always can generate irq */
1843 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
1844 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
1845 I915_WRITE(DEIER
, display_mask
| DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
);
1846 POSTING_READ(DEIER
);
1848 dev_priv
->gt_irq_mask
= ~0;
1850 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
1851 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
1856 GEN6_BSD_USER_INTERRUPT
|
1857 GEN6_BLITTER_USER_INTERRUPT
;
1862 GT_BSD_USER_INTERRUPT
;
1863 I915_WRITE(GTIER
, render_irqs
);
1864 POSTING_READ(GTIER
);
1866 if (HAS_PCH_CPT(dev
)) {
1867 hotplug_mask
= (SDE_CRT_HOTPLUG_CPT
|
1868 SDE_PORTB_HOTPLUG_CPT
|
1869 SDE_PORTC_HOTPLUG_CPT
|
1870 SDE_PORTD_HOTPLUG_CPT
);
1872 hotplug_mask
= (SDE_CRT_HOTPLUG
|
1879 dev_priv
->pch_irq_mask
= ~hotplug_mask
;
1881 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
1882 I915_WRITE(SDEIMR
, dev_priv
->pch_irq_mask
);
1883 I915_WRITE(SDEIER
, hotplug_mask
);
1884 POSTING_READ(SDEIER
);
1886 ironlake_enable_pch_hotplug(dev
);
1888 if (IS_IRONLAKE_M(dev
)) {
1889 /* Clear & enable PCU event interrupts */
1890 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
1891 I915_WRITE(DEIER
, I915_READ(DEIER
) | DE_PCU_EVENT
);
1892 ironlake_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
1898 static int ivybridge_irq_postinstall(struct drm_device
*dev
)
1900 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1901 /* enable kind of interrupts always enabled */
1903 DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
| DE_PCH_EVENT_IVB
|
1904 DE_PLANEC_FLIP_DONE_IVB
|
1905 DE_PLANEB_FLIP_DONE_IVB
|
1906 DE_PLANEA_FLIP_DONE_IVB
;
1910 dev_priv
->irq_mask
= ~display_mask
;
1912 /* should always can generate irq */
1913 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
1914 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
1917 DE_PIPEC_VBLANK_IVB
|
1918 DE_PIPEB_VBLANK_IVB
|
1919 DE_PIPEA_VBLANK_IVB
);
1920 POSTING_READ(DEIER
);
1922 dev_priv
->gt_irq_mask
= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT
;
1924 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
1925 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
1927 render_irqs
= GT_USER_INTERRUPT
| GEN6_BSD_USER_INTERRUPT
|
1928 GEN6_BLITTER_USER_INTERRUPT
| GT_GEN7_L3_PARITY_ERROR_INTERRUPT
;
1929 I915_WRITE(GTIER
, render_irqs
);
1930 POSTING_READ(GTIER
);
1932 hotplug_mask
= (SDE_CRT_HOTPLUG_CPT
|
1933 SDE_PORTB_HOTPLUG_CPT
|
1934 SDE_PORTC_HOTPLUG_CPT
|
1935 SDE_PORTD_HOTPLUG_CPT
);
1936 dev_priv
->pch_irq_mask
= ~hotplug_mask
;
1938 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
1939 I915_WRITE(SDEIMR
, dev_priv
->pch_irq_mask
);
1940 I915_WRITE(SDEIER
, hotplug_mask
);
1941 POSTING_READ(SDEIER
);
1943 ironlake_enable_pch_hotplug(dev
);
1948 static int valleyview_irq_postinstall(struct drm_device
*dev
)
1950 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1952 u32 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
1953 u32 pipestat_enable
= PLANE_FLIP_DONE_INT_EN_VLV
;
1956 enable_mask
= I915_DISPLAY_PORT_INTERRUPT
;
1957 enable_mask
|= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
1958 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
1959 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
1960 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1963 *Leave vblank interrupts masked initially. enable/disable will
1964 * toggle them based on usage.
1966 dev_priv
->irq_mask
= (~enable_mask
) |
1967 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
1968 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1970 dev_priv
->pipestat
[0] = 0;
1971 dev_priv
->pipestat
[1] = 0;
1973 /* Hack for broken MSIs on VLV */
1974 pci_write_config_dword(dev_priv
->dev
->pdev
, 0x94, 0xfee00000);
1975 pci_read_config_word(dev
->pdev
, 0x98, &msid
);
1976 msid
&= 0xff; /* mask out delivery bits */
1978 pci_write_config_word(dev_priv
->dev
->pdev
, 0x98, msid
);
1980 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
1981 I915_WRITE(VLV_IER
, enable_mask
);
1982 I915_WRITE(VLV_IIR
, 0xffffffff);
1983 I915_WRITE(PIPESTAT(0), 0xffff);
1984 I915_WRITE(PIPESTAT(1), 0xffff);
1985 POSTING_READ(VLV_IER
);
1987 i915_enable_pipestat(dev_priv
, 0, pipestat_enable
);
1988 i915_enable_pipestat(dev_priv
, 1, pipestat_enable
);
1990 I915_WRITE(VLV_IIR
, 0xffffffff);
1991 I915_WRITE(VLV_IIR
, 0xffffffff);
1993 dev_priv
->gt_irq_mask
= ~0;
1995 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
1996 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
1997 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
1998 I915_WRITE(GTIER
, GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT
|
1999 GT_GEN6_BLT_CS_ERROR_INTERRUPT
|
2000 GT_GEN6_BLT_USER_INTERRUPT
|
2001 GT_GEN6_BSD_USER_INTERRUPT
|
2002 GT_GEN6_BSD_CS_ERROR_INTERRUPT
|
2003 GT_GEN7_L3_PARITY_ERROR_INTERRUPT
|
2005 GT_RENDER_CS_ERROR_INTERRUPT
|
2008 POSTING_READ(GTIER
);
2010 /* ack & enable invalid PTE error interrupts */
2011 #if 0 /* FIXME: add support to irq handler for checking these bits */
2012 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
2013 I915_WRITE(DPINVGTT
, DPINVGTT_EN_MASK
);
2016 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
2017 #if 0 /* FIXME: check register definitions; some have moved */
2018 /* Note HDMI and DP share bits */
2019 if (dev_priv
->hotplug_supported_mask
& HDMIB_HOTPLUG_INT_STATUS
)
2020 hotplug_en
|= HDMIB_HOTPLUG_INT_EN
;
2021 if (dev_priv
->hotplug_supported_mask
& HDMIC_HOTPLUG_INT_STATUS
)
2022 hotplug_en
|= HDMIC_HOTPLUG_INT_EN
;
2023 if (dev_priv
->hotplug_supported_mask
& HDMID_HOTPLUG_INT_STATUS
)
2024 hotplug_en
|= HDMID_HOTPLUG_INT_EN
;
2025 if (dev_priv
->hotplug_supported_mask
& SDVOC_HOTPLUG_INT_STATUS
)
2026 hotplug_en
|= SDVOC_HOTPLUG_INT_EN
;
2027 if (dev_priv
->hotplug_supported_mask
& SDVOB_HOTPLUG_INT_STATUS
)
2028 hotplug_en
|= SDVOB_HOTPLUG_INT_EN
;
2029 if (dev_priv
->hotplug_supported_mask
& CRT_HOTPLUG_INT_STATUS
) {
2030 hotplug_en
|= CRT_HOTPLUG_INT_EN
;
2031 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
2035 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
2040 static void valleyview_irq_uninstall(struct drm_device
*dev
)
2042 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2049 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2051 I915_WRITE(HWSTAM
, 0xffffffff);
2052 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2053 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2055 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2056 I915_WRITE(VLV_IIR
, 0xffffffff);
2057 I915_WRITE(VLV_IMR
, 0xffffffff);
2058 I915_WRITE(VLV_IER
, 0x0);
2059 POSTING_READ(VLV_IER
);
2062 static void ironlake_irq_uninstall(struct drm_device
*dev
)
2064 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2069 I915_WRITE(HWSTAM
, 0xffffffff);
2071 I915_WRITE(DEIMR
, 0xffffffff);
2072 I915_WRITE(DEIER
, 0x0);
2073 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2075 I915_WRITE(GTIMR
, 0xffffffff);
2076 I915_WRITE(GTIER
, 0x0);
2077 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2079 I915_WRITE(SDEIMR
, 0xffffffff);
2080 I915_WRITE(SDEIER
, 0x0);
2081 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2084 static void i8xx_irq_preinstall(struct drm_device
* dev
)
2086 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2089 atomic_set(&dev_priv
->irq_received
, 0);
2092 I915_WRITE(PIPESTAT(pipe
), 0);
2093 I915_WRITE16(IMR
, 0xffff);
2094 I915_WRITE16(IER
, 0x0);
2095 POSTING_READ16(IER
);
2098 static int i8xx_irq_postinstall(struct drm_device
*dev
)
2100 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2102 dev_priv
->pipestat
[0] = 0;
2103 dev_priv
->pipestat
[1] = 0;
2106 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2108 /* Unmask the interrupts that we always want on. */
2109 dev_priv
->irq_mask
=
2110 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2111 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2112 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2113 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2114 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2115 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
2118 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2119 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2120 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2121 I915_USER_INTERRUPT
);
2122 POSTING_READ16(IER
);
2127 static irqreturn_t
i8xx_irq_handler(DRM_IRQ_ARGS
)
2129 struct drm_device
*dev
= (struct drm_device
*) arg
;
2130 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2133 unsigned long irqflags
;
2137 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2138 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2140 atomic_inc(&dev_priv
->irq_received
);
2142 iir
= I915_READ16(IIR
);
2146 while (iir
& ~flip_mask
) {
2147 /* Can't rely on pipestat interrupt bit in iir as it might
2148 * have been cleared after the pipestat interrupt was received.
2149 * It doesn't set the bit in iir again, but it still produces
2150 * interrupts (for non-MSI).
2152 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2153 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2154 i915_handle_error(dev
, false);
2156 for_each_pipe(pipe
) {
2157 int reg
= PIPESTAT(pipe
);
2158 pipe_stats
[pipe
] = I915_READ(reg
);
2161 * Clear the PIPE*STAT regs before the IIR
2163 if (pipe_stats
[pipe
] & 0x8000ffff) {
2164 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2165 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2167 I915_WRITE(reg
, pipe_stats
[pipe
]);
2171 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2173 I915_WRITE16(IIR
, iir
& ~flip_mask
);
2174 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
2176 i915_update_dri1_breadcrumb(dev
);
2178 if (iir
& I915_USER_INTERRUPT
)
2179 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2181 if (pipe_stats
[0] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2182 drm_handle_vblank(dev
, 0)) {
2183 if (iir
& I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
) {
2184 intel_prepare_page_flip(dev
, 0);
2185 intel_finish_page_flip(dev
, 0);
2186 flip_mask
&= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
;
2190 if (pipe_stats
[1] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2191 drm_handle_vblank(dev
, 1)) {
2192 if (iir
& I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
) {
2193 intel_prepare_page_flip(dev
, 1);
2194 intel_finish_page_flip(dev
, 1);
2195 flip_mask
&= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2205 static void i8xx_irq_uninstall(struct drm_device
* dev
)
2207 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2210 for_each_pipe(pipe
) {
2211 /* Clear enable bits; then clear status bits */
2212 I915_WRITE(PIPESTAT(pipe
), 0);
2213 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
2215 I915_WRITE16(IMR
, 0xffff);
2216 I915_WRITE16(IER
, 0x0);
2217 I915_WRITE16(IIR
, I915_READ16(IIR
));
2220 static void i915_irq_preinstall(struct drm_device
* dev
)
2222 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2225 atomic_set(&dev_priv
->irq_received
, 0);
2227 if (I915_HAS_HOTPLUG(dev
)) {
2228 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2229 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2232 I915_WRITE16(HWSTAM
, 0xeffe);
2234 I915_WRITE(PIPESTAT(pipe
), 0);
2235 I915_WRITE(IMR
, 0xffffffff);
2236 I915_WRITE(IER
, 0x0);
2240 static int i915_irq_postinstall(struct drm_device
*dev
)
2242 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2245 dev_priv
->pipestat
[0] = 0;
2246 dev_priv
->pipestat
[1] = 0;
2248 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2250 /* Unmask the interrupts that we always want on. */
2251 dev_priv
->irq_mask
=
2252 ~(I915_ASLE_INTERRUPT
|
2253 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2254 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2255 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2256 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2257 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2260 I915_ASLE_INTERRUPT
|
2261 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2262 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2263 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2264 I915_USER_INTERRUPT
;
2266 if (I915_HAS_HOTPLUG(dev
)) {
2267 /* Enable in IER... */
2268 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
2269 /* and unmask in IMR */
2270 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
2273 I915_WRITE(IMR
, dev_priv
->irq_mask
);
2274 I915_WRITE(IER
, enable_mask
);
2277 if (I915_HAS_HOTPLUG(dev
)) {
2278 u32 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
2280 if (dev_priv
->hotplug_supported_mask
& HDMIB_HOTPLUG_INT_STATUS
)
2281 hotplug_en
|= HDMIB_HOTPLUG_INT_EN
;
2282 if (dev_priv
->hotplug_supported_mask
& HDMIC_HOTPLUG_INT_STATUS
)
2283 hotplug_en
|= HDMIC_HOTPLUG_INT_EN
;
2284 if (dev_priv
->hotplug_supported_mask
& HDMID_HOTPLUG_INT_STATUS
)
2285 hotplug_en
|= HDMID_HOTPLUG_INT_EN
;
2286 if (dev_priv
->hotplug_supported_mask
& SDVOC_HOTPLUG_INT_STATUS_I915
)
2287 hotplug_en
|= SDVOC_HOTPLUG_INT_EN
;
2288 if (dev_priv
->hotplug_supported_mask
& SDVOB_HOTPLUG_INT_STATUS_I915
)
2289 hotplug_en
|= SDVOB_HOTPLUG_INT_EN
;
2290 if (dev_priv
->hotplug_supported_mask
& CRT_HOTPLUG_INT_STATUS
) {
2291 hotplug_en
|= CRT_HOTPLUG_INT_EN
;
2292 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
2295 /* Ignore TV since it's buggy */
2297 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
2300 intel_opregion_enable_asle(dev
);
2305 static irqreturn_t
i915_irq_handler(DRM_IRQ_ARGS
)
2307 struct drm_device
*dev
= (struct drm_device
*) arg
;
2308 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2309 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
2310 unsigned long irqflags
;
2312 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2313 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2315 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
,
2316 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2318 int pipe
, ret
= IRQ_NONE
;
2320 atomic_inc(&dev_priv
->irq_received
);
2322 iir
= I915_READ(IIR
);
2324 bool irq_received
= (iir
& ~flip_mask
) != 0;
2325 bool blc_event
= false;
2327 /* Can't rely on pipestat interrupt bit in iir as it might
2328 * have been cleared after the pipestat interrupt was received.
2329 * It doesn't set the bit in iir again, but it still produces
2330 * interrupts (for non-MSI).
2332 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2333 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2334 i915_handle_error(dev
, false);
2336 for_each_pipe(pipe
) {
2337 int reg
= PIPESTAT(pipe
);
2338 pipe_stats
[pipe
] = I915_READ(reg
);
2340 /* Clear the PIPE*STAT regs before the IIR */
2341 if (pipe_stats
[pipe
] & 0x8000ffff) {
2342 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2343 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2345 I915_WRITE(reg
, pipe_stats
[pipe
]);
2346 irq_received
= true;
2349 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2354 /* Consume port. Then clear IIR or we'll miss events */
2355 if ((I915_HAS_HOTPLUG(dev
)) &&
2356 (iir
& I915_DISPLAY_PORT_INTERRUPT
)) {
2357 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
2359 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2361 if (hotplug_status
& dev_priv
->hotplug_supported_mask
)
2362 queue_work(dev_priv
->wq
,
2363 &dev_priv
->hotplug_work
);
2365 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
2366 POSTING_READ(PORT_HOTPLUG_STAT
);
2369 I915_WRITE(IIR
, iir
& ~flip_mask
);
2370 new_iir
= I915_READ(IIR
); /* Flush posted writes */
2372 if (iir
& I915_USER_INTERRUPT
)
2373 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2375 for_each_pipe(pipe
) {
2379 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2380 drm_handle_vblank(dev
, pipe
)) {
2381 if (iir
& flip
[plane
]) {
2382 intel_prepare_page_flip(dev
, plane
);
2383 intel_finish_page_flip(dev
, pipe
);
2384 flip_mask
&= ~flip
[plane
];
2388 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
2392 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
2393 intel_opregion_asle_intr(dev
);
2395 /* With MSI, interrupts are only generated when iir
2396 * transitions from zero to nonzero. If another bit got
2397 * set while we were handling the existing iir bits, then
2398 * we would never get another interrupt.
2400 * This is fine on non-MSI as well, as if we hit this path
2401 * we avoid exiting the interrupt handler only to generate
2404 * Note that for MSI this could cause a stray interrupt report
2405 * if an interrupt landed in the time between writing IIR and
2406 * the posting read. This should be rare enough to never
2407 * trigger the 99% of 100,000 interrupts test for disabling
2412 } while (iir
& ~flip_mask
);
2414 i915_update_dri1_breadcrumb(dev
);
2419 static void i915_irq_uninstall(struct drm_device
* dev
)
2421 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2424 if (I915_HAS_HOTPLUG(dev
)) {
2425 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2426 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2429 I915_WRITE16(HWSTAM
, 0xffff);
2430 for_each_pipe(pipe
) {
2431 /* Clear enable bits; then clear status bits */
2432 I915_WRITE(PIPESTAT(pipe
), 0);
2433 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
2435 I915_WRITE(IMR
, 0xffffffff);
2436 I915_WRITE(IER
, 0x0);
2438 I915_WRITE(IIR
, I915_READ(IIR
));
2441 static void i965_irq_preinstall(struct drm_device
* dev
)
2443 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2446 atomic_set(&dev_priv
->irq_received
, 0);
2448 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2449 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2451 I915_WRITE(HWSTAM
, 0xeffe);
2453 I915_WRITE(PIPESTAT(pipe
), 0);
2454 I915_WRITE(IMR
, 0xffffffff);
2455 I915_WRITE(IER
, 0x0);
2459 static int i965_irq_postinstall(struct drm_device
*dev
)
2461 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2466 /* Unmask the interrupts that we always want on. */
2467 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
2468 I915_DISPLAY_PORT_INTERRUPT
|
2469 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2470 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2471 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2472 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2473 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2475 enable_mask
= ~dev_priv
->irq_mask
;
2476 enable_mask
|= I915_USER_INTERRUPT
;
2479 enable_mask
|= I915_BSD_USER_INTERRUPT
;
2481 dev_priv
->pipestat
[0] = 0;
2482 dev_priv
->pipestat
[1] = 0;
2485 * Enable some error detection, note the instruction error mask
2486 * bit is reserved, so we leave it masked.
2489 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
2490 GM45_ERROR_MEM_PRIV
|
2491 GM45_ERROR_CP_PRIV
|
2492 I915_ERROR_MEMORY_REFRESH
);
2494 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
2495 I915_ERROR_MEMORY_REFRESH
);
2497 I915_WRITE(EMR
, error_mask
);
2499 I915_WRITE(IMR
, dev_priv
->irq_mask
);
2500 I915_WRITE(IER
, enable_mask
);
2503 /* Note HDMI and DP share hotplug bits */
2505 if (dev_priv
->hotplug_supported_mask
& HDMIB_HOTPLUG_INT_STATUS
)
2506 hotplug_en
|= HDMIB_HOTPLUG_INT_EN
;
2507 if (dev_priv
->hotplug_supported_mask
& HDMIC_HOTPLUG_INT_STATUS
)
2508 hotplug_en
|= HDMIC_HOTPLUG_INT_EN
;
2509 if (dev_priv
->hotplug_supported_mask
& HDMID_HOTPLUG_INT_STATUS
)
2510 hotplug_en
|= HDMID_HOTPLUG_INT_EN
;
2512 if (dev_priv
->hotplug_supported_mask
& SDVOC_HOTPLUG_INT_STATUS_G4X
)
2513 hotplug_en
|= SDVOC_HOTPLUG_INT_EN
;
2514 if (dev_priv
->hotplug_supported_mask
& SDVOB_HOTPLUG_INT_STATUS_G4X
)
2515 hotplug_en
|= SDVOB_HOTPLUG_INT_EN
;
2517 if (dev_priv
->hotplug_supported_mask
& SDVOC_HOTPLUG_INT_STATUS_I965
)
2518 hotplug_en
|= SDVOC_HOTPLUG_INT_EN
;
2519 if (dev_priv
->hotplug_supported_mask
& SDVOB_HOTPLUG_INT_STATUS_I965
)
2520 hotplug_en
|= SDVOB_HOTPLUG_INT_EN
;
2522 if (dev_priv
->hotplug_supported_mask
& CRT_HOTPLUG_INT_STATUS
) {
2523 hotplug_en
|= CRT_HOTPLUG_INT_EN
;
2525 /* Programming the CRT detection parameters tends
2526 to generate a spurious hotplug event about three
2527 seconds later. So just do it once.
2530 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
2531 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
2534 /* Ignore TV since it's buggy */
2536 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
2538 intel_opregion_enable_asle(dev
);
2543 static irqreturn_t
i965_irq_handler(DRM_IRQ_ARGS
)
2545 struct drm_device
*dev
= (struct drm_device
*) arg
;
2546 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2548 u32 pipe_stats
[I915_MAX_PIPES
];
2549 unsigned long irqflags
;
2551 int ret
= IRQ_NONE
, pipe
;
2553 atomic_inc(&dev_priv
->irq_received
);
2555 iir
= I915_READ(IIR
);
2558 bool blc_event
= false;
2560 irq_received
= iir
!= 0;
2562 /* Can't rely on pipestat interrupt bit in iir as it might
2563 * have been cleared after the pipestat interrupt was received.
2564 * It doesn't set the bit in iir again, but it still produces
2565 * interrupts (for non-MSI).
2567 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2568 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2569 i915_handle_error(dev
, false);
2571 for_each_pipe(pipe
) {
2572 int reg
= PIPESTAT(pipe
);
2573 pipe_stats
[pipe
] = I915_READ(reg
);
2576 * Clear the PIPE*STAT regs before the IIR
2578 if (pipe_stats
[pipe
] & 0x8000ffff) {
2579 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2580 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2582 I915_WRITE(reg
, pipe_stats
[pipe
]);
2586 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2593 /* Consume port. Then clear IIR or we'll miss events */
2594 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
2595 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
2597 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2599 if (hotplug_status
& dev_priv
->hotplug_supported_mask
)
2600 queue_work(dev_priv
->wq
,
2601 &dev_priv
->hotplug_work
);
2603 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
2604 I915_READ(PORT_HOTPLUG_STAT
);
2607 I915_WRITE(IIR
, iir
);
2608 new_iir
= I915_READ(IIR
); /* Flush posted writes */
2610 if (iir
& I915_USER_INTERRUPT
)
2611 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2612 if (iir
& I915_BSD_USER_INTERRUPT
)
2613 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
2615 if (iir
& I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
)
2616 intel_prepare_page_flip(dev
, 0);
2618 if (iir
& I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
)
2619 intel_prepare_page_flip(dev
, 1);
2621 for_each_pipe(pipe
) {
2622 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
2623 drm_handle_vblank(dev
, pipe
)) {
2624 i915_pageflip_stall_check(dev
, pipe
);
2625 intel_finish_page_flip(dev
, pipe
);
2628 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
2633 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
2634 intel_opregion_asle_intr(dev
);
2636 /* With MSI, interrupts are only generated when iir
2637 * transitions from zero to nonzero. If another bit got
2638 * set while we were handling the existing iir bits, then
2639 * we would never get another interrupt.
2641 * This is fine on non-MSI as well, as if we hit this path
2642 * we avoid exiting the interrupt handler only to generate
2645 * Note that for MSI this could cause a stray interrupt report
2646 * if an interrupt landed in the time between writing IIR and
2647 * the posting read. This should be rare enough to never
2648 * trigger the 99% of 100,000 interrupts test for disabling
2654 i915_update_dri1_breadcrumb(dev
);
2659 static void i965_irq_uninstall(struct drm_device
* dev
)
2661 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2667 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2668 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2670 I915_WRITE(HWSTAM
, 0xffffffff);
2672 I915_WRITE(PIPESTAT(pipe
), 0);
2673 I915_WRITE(IMR
, 0xffffffff);
2674 I915_WRITE(IER
, 0x0);
2677 I915_WRITE(PIPESTAT(pipe
),
2678 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
2679 I915_WRITE(IIR
, I915_READ(IIR
));
2682 void intel_irq_init(struct drm_device
*dev
)
2684 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2686 INIT_WORK(&dev_priv
->hotplug_work
, i915_hotplug_work_func
);
2687 INIT_WORK(&dev_priv
->error_work
, i915_error_work_func
);
2688 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
2689 INIT_WORK(&dev_priv
->parity_error_work
, ivybridge_parity_work
);
2691 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
2692 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
2693 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
2694 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
2695 dev
->driver
->get_vblank_counter
= gm45_get_vblank_counter
;
2698 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
2699 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
2701 dev
->driver
->get_vblank_timestamp
= NULL
;
2702 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
2704 if (IS_VALLEYVIEW(dev
)) {
2705 dev
->driver
->irq_handler
= valleyview_irq_handler
;
2706 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
2707 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
2708 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
2709 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
2710 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
2711 } else if (IS_IVYBRIDGE(dev
)) {
2712 /* Share pre & uninstall handlers with ILK/SNB */
2713 dev
->driver
->irq_handler
= ivybridge_irq_handler
;
2714 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
2715 dev
->driver
->irq_postinstall
= ivybridge_irq_postinstall
;
2716 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
2717 dev
->driver
->enable_vblank
= ivybridge_enable_vblank
;
2718 dev
->driver
->disable_vblank
= ivybridge_disable_vblank
;
2719 } else if (IS_HASWELL(dev
)) {
2720 /* Share interrupts handling with IVB */
2721 dev
->driver
->irq_handler
= ivybridge_irq_handler
;
2722 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
2723 dev
->driver
->irq_postinstall
= ivybridge_irq_postinstall
;
2724 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
2725 dev
->driver
->enable_vblank
= ivybridge_enable_vblank
;
2726 dev
->driver
->disable_vblank
= ivybridge_disable_vblank
;
2727 } else if (HAS_PCH_SPLIT(dev
)) {
2728 dev
->driver
->irq_handler
= ironlake_irq_handler
;
2729 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
2730 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
2731 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
2732 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
2733 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
2735 if (INTEL_INFO(dev
)->gen
== 2) {
2736 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
2737 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
2738 dev
->driver
->irq_handler
= i8xx_irq_handler
;
2739 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
2740 } else if (INTEL_INFO(dev
)->gen
== 3) {
2741 /* IIR "flip pending" means done if this bit is set */
2742 I915_WRITE(ECOSKPD
, _MASKED_BIT_DISABLE(ECO_FLIP_DONE
));
2744 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
2745 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
2746 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
2747 dev
->driver
->irq_handler
= i915_irq_handler
;
2749 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
2750 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
2751 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
2752 dev
->driver
->irq_handler
= i965_irq_handler
;
2754 dev
->driver
->enable_vblank
= i915_enable_vblank
;
2755 dev
->driver
->disable_vblank
= i915_disable_vblank
;