1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
34 #include <drm/i915_drm.h>
36 #include "i915_trace.h"
37 #include "intel_drv.h"
39 static const u32 hpd_ibx
[] = {
40 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
41 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
42 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
43 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
44 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
47 static const u32 hpd_cpt
[] = {
48 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
49 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG_CPT
,
50 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
51 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
52 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
55 static const u32 hpd_mask_i915
[] = {
56 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
57 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
58 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
59 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
60 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
61 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
64 static const u32 hpd_status_gen4
[] = {
65 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
66 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
67 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
68 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
69 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
70 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
73 static const u32 hpd_status_i915
[] = { /* i915 and valleyview are the same */
74 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
75 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
76 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
77 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
78 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
79 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
82 /* For display hotplug interrupt */
84 ironlake_enable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
86 assert_spin_locked(&dev_priv
->irq_lock
);
88 if ((dev_priv
->irq_mask
& mask
) != 0) {
89 dev_priv
->irq_mask
&= ~mask
;
90 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
96 ironlake_disable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
98 assert_spin_locked(&dev_priv
->irq_lock
);
100 if ((dev_priv
->irq_mask
& mask
) != mask
) {
101 dev_priv
->irq_mask
|= mask
;
102 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
108 * ilk_update_gt_irq - update GTIMR
109 * @dev_priv: driver private
110 * @interrupt_mask: mask of interrupt bits to update
111 * @enabled_irq_mask: mask of interrupt bits to enable
113 static void ilk_update_gt_irq(struct drm_i915_private
*dev_priv
,
114 uint32_t interrupt_mask
,
115 uint32_t enabled_irq_mask
)
117 assert_spin_locked(&dev_priv
->irq_lock
);
119 dev_priv
->gt_irq_mask
&= ~interrupt_mask
;
120 dev_priv
->gt_irq_mask
|= (~enabled_irq_mask
& interrupt_mask
);
121 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
125 void ilk_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
127 ilk_update_gt_irq(dev_priv
, mask
, mask
);
130 void ilk_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
132 ilk_update_gt_irq(dev_priv
, mask
, 0);
136 * snb_update_pm_irq - update GEN6_PMIMR
137 * @dev_priv: driver private
138 * @interrupt_mask: mask of interrupt bits to update
139 * @enabled_irq_mask: mask of interrupt bits to enable
141 static void snb_update_pm_irq(struct drm_i915_private
*dev_priv
,
142 uint32_t interrupt_mask
,
143 uint32_t enabled_irq_mask
)
147 assert_spin_locked(&dev_priv
->irq_lock
);
149 new_val
= dev_priv
->pm_irq_mask
;
150 new_val
&= ~interrupt_mask
;
151 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
153 if (new_val
!= dev_priv
->pm_irq_mask
) {
154 dev_priv
->pm_irq_mask
= new_val
;
155 I915_WRITE(GEN6_PMIMR
, dev_priv
->pm_irq_mask
);
156 POSTING_READ(GEN6_PMIMR
);
160 void snb_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
162 snb_update_pm_irq(dev_priv
, mask
, mask
);
165 void snb_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
167 snb_update_pm_irq(dev_priv
, mask
, 0);
170 static bool ivb_can_enable_err_int(struct drm_device
*dev
)
172 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
173 struct intel_crtc
*crtc
;
176 assert_spin_locked(&dev_priv
->irq_lock
);
178 for_each_pipe(pipe
) {
179 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
181 if (crtc
->cpu_fifo_underrun_disabled
)
188 static bool cpt_can_enable_serr_int(struct drm_device
*dev
)
190 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
192 struct intel_crtc
*crtc
;
194 assert_spin_locked(&dev_priv
->irq_lock
);
196 for_each_pipe(pipe
) {
197 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
199 if (crtc
->pch_fifo_underrun_disabled
)
206 static void ironlake_set_fifo_underrun_reporting(struct drm_device
*dev
,
207 enum pipe pipe
, bool enable
)
209 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
210 uint32_t bit
= (pipe
== PIPE_A
) ? DE_PIPEA_FIFO_UNDERRUN
:
211 DE_PIPEB_FIFO_UNDERRUN
;
214 ironlake_enable_display_irq(dev_priv
, bit
);
216 ironlake_disable_display_irq(dev_priv
, bit
);
219 static void ivybridge_set_fifo_underrun_reporting(struct drm_device
*dev
,
220 enum pipe pipe
, bool enable
)
222 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
224 I915_WRITE(GEN7_ERR_INT
, ERR_INT_FIFO_UNDERRUN(pipe
));
226 if (!ivb_can_enable_err_int(dev
))
229 ironlake_enable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
231 bool was_enabled
= !(I915_READ(DEIMR
) & DE_ERR_INT_IVB
);
233 /* Change the state _after_ we've read out the current one. */
234 ironlake_disable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
237 (I915_READ(GEN7_ERR_INT
) & ERR_INT_FIFO_UNDERRUN(pipe
))) {
238 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
245 * ibx_display_interrupt_update - update SDEIMR
246 * @dev_priv: driver private
247 * @interrupt_mask: mask of interrupt bits to update
248 * @enabled_irq_mask: mask of interrupt bits to enable
250 static void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
251 uint32_t interrupt_mask
,
252 uint32_t enabled_irq_mask
)
254 uint32_t sdeimr
= I915_READ(SDEIMR
);
255 sdeimr
&= ~interrupt_mask
;
256 sdeimr
|= (~enabled_irq_mask
& interrupt_mask
);
258 assert_spin_locked(&dev_priv
->irq_lock
);
260 I915_WRITE(SDEIMR
, sdeimr
);
261 POSTING_READ(SDEIMR
);
263 #define ibx_enable_display_interrupt(dev_priv, bits) \
264 ibx_display_interrupt_update((dev_priv), (bits), (bits))
265 #define ibx_disable_display_interrupt(dev_priv, bits) \
266 ibx_display_interrupt_update((dev_priv), (bits), 0)
268 static void ibx_set_fifo_underrun_reporting(struct drm_device
*dev
,
269 enum transcoder pch_transcoder
,
272 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
273 uint32_t bit
= (pch_transcoder
== TRANSCODER_A
) ?
274 SDE_TRANSA_FIFO_UNDER
: SDE_TRANSB_FIFO_UNDER
;
277 ibx_enable_display_interrupt(dev_priv
, bit
);
279 ibx_disable_display_interrupt(dev_priv
, bit
);
282 static void cpt_set_fifo_underrun_reporting(struct drm_device
*dev
,
283 enum transcoder pch_transcoder
,
286 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
290 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
));
292 if (!cpt_can_enable_serr_int(dev
))
295 ibx_enable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
297 uint32_t tmp
= I915_READ(SERR_INT
);
298 bool was_enabled
= !(I915_READ(SDEIMR
) & SDE_ERROR_CPT
);
300 /* Change the state _after_ we've read out the current one. */
301 ibx_disable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
304 (tmp
& SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
))) {
305 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
306 transcoder_name(pch_transcoder
));
312 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
315 * @enable: true if we want to report FIFO underrun errors, false otherwise
317 * This function makes us disable or enable CPU fifo underruns for a specific
318 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
319 * reporting for one pipe may also disable all the other CPU error interruts for
320 * the other pipes, due to the fact that there's just one interrupt mask/enable
321 * bit for all the pipes.
323 * Returns the previous state of underrun reporting.
325 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device
*dev
,
326 enum pipe pipe
, bool enable
)
328 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
329 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
330 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
334 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
336 ret
= !intel_crtc
->cpu_fifo_underrun_disabled
;
341 intel_crtc
->cpu_fifo_underrun_disabled
= !enable
;
343 if (IS_GEN5(dev
) || IS_GEN6(dev
))
344 ironlake_set_fifo_underrun_reporting(dev
, pipe
, enable
);
345 else if (IS_GEN7(dev
))
346 ivybridge_set_fifo_underrun_reporting(dev
, pipe
, enable
);
349 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
354 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
356 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
357 * @enable: true if we want to report FIFO underrun errors, false otherwise
359 * This function makes us disable or enable PCH fifo underruns for a specific
360 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
361 * underrun reporting for one transcoder may also disable all the other PCH
362 * error interruts for the other transcoders, due to the fact that there's just
363 * one interrupt mask/enable bit for all the transcoders.
365 * Returns the previous state of underrun reporting.
367 bool intel_set_pch_fifo_underrun_reporting(struct drm_device
*dev
,
368 enum transcoder pch_transcoder
,
371 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
372 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pch_transcoder
];
373 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
378 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
379 * has only one pch transcoder A that all pipes can use. To avoid racy
380 * pch transcoder -> pipe lookups from interrupt code simply store the
381 * underrun statistics in crtc A. Since we never expose this anywhere
382 * nor use it outside of the fifo underrun code here using the "wrong"
383 * crtc on LPT won't cause issues.
386 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
388 ret
= !intel_crtc
->pch_fifo_underrun_disabled
;
393 intel_crtc
->pch_fifo_underrun_disabled
= !enable
;
395 if (HAS_PCH_IBX(dev
))
396 ibx_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
398 cpt_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
401 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
407 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
409 u32 reg
= PIPESTAT(pipe
);
410 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
412 assert_spin_locked(&dev_priv
->irq_lock
);
414 if ((pipestat
& mask
) == mask
)
417 /* Enable the interrupt, clear any pending status */
418 pipestat
|= mask
| (mask
>> 16);
419 I915_WRITE(reg
, pipestat
);
424 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
426 u32 reg
= PIPESTAT(pipe
);
427 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
429 assert_spin_locked(&dev_priv
->irq_lock
);
431 if ((pipestat
& mask
) == 0)
435 I915_WRITE(reg
, pipestat
);
440 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
442 static void i915_enable_asle_pipestat(struct drm_device
*dev
)
444 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
445 unsigned long irqflags
;
447 if (!dev_priv
->opregion
.asle
|| !IS_MOBILE(dev
))
450 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
452 i915_enable_pipestat(dev_priv
, 1, PIPE_LEGACY_BLC_EVENT_ENABLE
);
453 if (INTEL_INFO(dev
)->gen
>= 4)
454 i915_enable_pipestat(dev_priv
, 0, PIPE_LEGACY_BLC_EVENT_ENABLE
);
456 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
460 * i915_pipe_enabled - check if a pipe is enabled
462 * @pipe: pipe to check
464 * Reading certain registers when the pipe is disabled can hang the chip.
465 * Use this routine to make sure the PLL is running and the pipe is active
466 * before reading such registers if unsure.
469 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
471 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
473 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
474 /* Locking is horribly broken here, but whatever. */
475 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
476 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
478 return intel_crtc
->active
;
480 return I915_READ(PIPECONF(pipe
)) & PIPECONF_ENABLE
;
484 /* Called from drm generic code, passed a 'crtc', which
485 * we use as a pipe index
487 static u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
489 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
490 unsigned long high_frame
;
491 unsigned long low_frame
;
492 u32 high1
, high2
, low
;
494 if (!i915_pipe_enabled(dev
, pipe
)) {
495 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
496 "pipe %c\n", pipe_name(pipe
));
500 high_frame
= PIPEFRAME(pipe
);
501 low_frame
= PIPEFRAMEPIXEL(pipe
);
504 * High & low register fields aren't synchronized, so make sure
505 * we get a low value that's stable across two reads of the high
509 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
510 low
= I915_READ(low_frame
) & PIPE_FRAME_LOW_MASK
;
511 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
512 } while (high1
!= high2
);
514 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
515 low
>>= PIPE_FRAME_LOW_SHIFT
;
516 return (high1
<< 8) | low
;
519 static u32
gm45_get_vblank_counter(struct drm_device
*dev
, int pipe
)
521 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
522 int reg
= PIPE_FRMCOUNT_GM45(pipe
);
524 if (!i915_pipe_enabled(dev
, pipe
)) {
525 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
526 "pipe %c\n", pipe_name(pipe
));
530 return I915_READ(reg
);
533 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, int pipe
,
534 int *vpos
, int *hpos
)
536 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
537 u32 vbl
= 0, position
= 0;
538 int vbl_start
, vbl_end
, htotal
, vtotal
;
541 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
544 if (!i915_pipe_enabled(dev
, pipe
)) {
545 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
546 "pipe %c\n", pipe_name(pipe
));
551 vtotal
= 1 + ((I915_READ(VTOTAL(cpu_transcoder
)) >> 16) & 0x1fff);
553 if (INTEL_INFO(dev
)->gen
>= 4) {
554 /* No obvious pixelcount register. Only query vertical
555 * scanout position from Display scan line register.
557 position
= I915_READ(PIPEDSL(pipe
));
559 /* Decode into vertical scanout position. Don't have
560 * horizontal scanout position.
562 *vpos
= position
& 0x1fff;
565 /* Have access to pixelcount since start of frame.
566 * We can split this into vertical and horizontal
569 position
= (I915_READ(PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
571 htotal
= 1 + ((I915_READ(HTOTAL(cpu_transcoder
)) >> 16) & 0x1fff);
572 *vpos
= position
/ htotal
;
573 *hpos
= position
- (*vpos
* htotal
);
576 /* Query vblank area. */
577 vbl
= I915_READ(VBLANK(cpu_transcoder
));
579 /* Test position against vblank region. */
580 vbl_start
= vbl
& 0x1fff;
581 vbl_end
= (vbl
>> 16) & 0x1fff;
583 if ((*vpos
< vbl_start
) || (*vpos
> vbl_end
))
586 /* Inside "upper part" of vblank area? Apply corrective offset: */
587 if (in_vbl
&& (*vpos
>= vbl_start
))
588 *vpos
= *vpos
- vtotal
;
590 /* Readouts valid? */
592 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
596 ret
|= DRM_SCANOUTPOS_INVBL
;
601 static int i915_get_vblank_timestamp(struct drm_device
*dev
, int pipe
,
603 struct timeval
*vblank_time
,
606 struct drm_crtc
*crtc
;
608 if (pipe
< 0 || pipe
>= INTEL_INFO(dev
)->num_pipes
) {
609 DRM_ERROR("Invalid crtc %d\n", pipe
);
613 /* Get drm_crtc to timestamp: */
614 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
616 DRM_ERROR("Invalid crtc %d\n", pipe
);
620 if (!crtc
->enabled
) {
621 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
625 /* Helper routine in DRM core does all the work: */
626 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
631 static int intel_hpd_irq_event(struct drm_device
*dev
, struct drm_connector
*connector
)
633 enum drm_connector_status old_status
;
635 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
636 old_status
= connector
->status
;
638 connector
->status
= connector
->funcs
->detect(connector
, false);
639 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
641 drm_get_connector_name(connector
),
642 old_status
, connector
->status
);
643 return (old_status
!= connector
->status
);
647 * Handle hotplug events outside the interrupt handler proper.
649 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
651 static void i915_hotplug_work_func(struct work_struct
*work
)
653 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
655 struct drm_device
*dev
= dev_priv
->dev
;
656 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
657 struct intel_connector
*intel_connector
;
658 struct intel_encoder
*intel_encoder
;
659 struct drm_connector
*connector
;
660 unsigned long irqflags
;
661 bool hpd_disabled
= false;
662 bool changed
= false;
665 /* HPD irq before everything is fully set up. */
666 if (!dev_priv
->enable_hotplug_processing
)
669 mutex_lock(&mode_config
->mutex
);
670 DRM_DEBUG_KMS("running encoder hotplug functions\n");
672 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
674 hpd_event_bits
= dev_priv
->hpd_event_bits
;
675 dev_priv
->hpd_event_bits
= 0;
676 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
677 intel_connector
= to_intel_connector(connector
);
678 intel_encoder
= intel_connector
->encoder
;
679 if (intel_encoder
->hpd_pin
> HPD_NONE
&&
680 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_MARK_DISABLED
&&
681 connector
->polled
== DRM_CONNECTOR_POLL_HPD
) {
682 DRM_INFO("HPD interrupt storm detected on connector %s: "
683 "switching from hotplug detection to polling\n",
684 drm_get_connector_name(connector
));
685 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
= HPD_DISABLED
;
686 connector
->polled
= DRM_CONNECTOR_POLL_CONNECT
687 | DRM_CONNECTOR_POLL_DISCONNECT
;
690 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
691 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
692 drm_get_connector_name(connector
), intel_encoder
->hpd_pin
);
695 /* if there were no outputs to poll, poll was disabled,
696 * therefore make sure it's enabled when disabling HPD on
699 drm_kms_helper_poll_enable(dev
);
700 mod_timer(&dev_priv
->hotplug_reenable_timer
,
701 jiffies
+ msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY
));
704 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
706 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
707 intel_connector
= to_intel_connector(connector
);
708 intel_encoder
= intel_connector
->encoder
;
709 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
710 if (intel_encoder
->hot_plug
)
711 intel_encoder
->hot_plug(intel_encoder
);
712 if (intel_hpd_irq_event(dev
, connector
))
716 mutex_unlock(&mode_config
->mutex
);
719 drm_kms_helper_hotplug_event(dev
);
722 static void ironlake_rps_change_irq_handler(struct drm_device
*dev
)
724 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
725 u32 busy_up
, busy_down
, max_avg
, min_avg
;
728 spin_lock(&mchdev_lock
);
730 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
732 new_delay
= dev_priv
->ips
.cur_delay
;
734 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
735 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
736 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
737 max_avg
= I915_READ(RCBMAXAVG
);
738 min_avg
= I915_READ(RCBMINAVG
);
740 /* Handle RCS change request from hw */
741 if (busy_up
> max_avg
) {
742 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
743 new_delay
= dev_priv
->ips
.cur_delay
- 1;
744 if (new_delay
< dev_priv
->ips
.max_delay
)
745 new_delay
= dev_priv
->ips
.max_delay
;
746 } else if (busy_down
< min_avg
) {
747 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
748 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
749 if (new_delay
> dev_priv
->ips
.min_delay
)
750 new_delay
= dev_priv
->ips
.min_delay
;
753 if (ironlake_set_drps(dev
, new_delay
))
754 dev_priv
->ips
.cur_delay
= new_delay
;
756 spin_unlock(&mchdev_lock
);
761 static void notify_ring(struct drm_device
*dev
,
762 struct intel_ring_buffer
*ring
)
764 if (ring
->obj
== NULL
)
767 trace_i915_gem_request_complete(ring
, ring
->get_seqno(ring
, false));
769 wake_up_all(&ring
->irq_queue
);
770 i915_queue_hangcheck(dev
);
773 static void gen6_pm_rps_work(struct work_struct
*work
)
775 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
780 spin_lock_irq(&dev_priv
->irq_lock
);
781 pm_iir
= dev_priv
->rps
.pm_iir
;
782 dev_priv
->rps
.pm_iir
= 0;
783 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
784 snb_enable_pm_irq(dev_priv
, GEN6_PM_RPS_EVENTS
);
785 spin_unlock_irq(&dev_priv
->irq_lock
);
787 /* Make sure we didn't queue anything we're not going to process. */
788 WARN_ON(pm_iir
& ~GEN6_PM_RPS_EVENTS
);
790 if ((pm_iir
& GEN6_PM_RPS_EVENTS
) == 0)
793 mutex_lock(&dev_priv
->rps
.hw_lock
);
795 if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
) {
796 new_delay
= dev_priv
->rps
.cur_delay
+ 1;
799 * For better performance, jump directly
800 * to RPe if we're below it.
802 if (IS_VALLEYVIEW(dev_priv
->dev
) &&
803 dev_priv
->rps
.cur_delay
< dev_priv
->rps
.rpe_delay
)
804 new_delay
= dev_priv
->rps
.rpe_delay
;
806 new_delay
= dev_priv
->rps
.cur_delay
- 1;
808 /* sysfs frequency interfaces may have snuck in while servicing the
811 if (new_delay
>= dev_priv
->rps
.min_delay
&&
812 new_delay
<= dev_priv
->rps
.max_delay
) {
813 if (IS_VALLEYVIEW(dev_priv
->dev
))
814 valleyview_set_rps(dev_priv
->dev
, new_delay
);
816 gen6_set_rps(dev_priv
->dev
, new_delay
);
819 if (IS_VALLEYVIEW(dev_priv
->dev
)) {
821 * On VLV, when we enter RC6 we may not be at the minimum
822 * voltage level, so arm a timer to check. It should only
823 * fire when there's activity or once after we've entered
824 * RC6, and then won't be re-armed until the next RPS interrupt.
826 mod_delayed_work(dev_priv
->wq
, &dev_priv
->rps
.vlv_work
,
827 msecs_to_jiffies(100));
830 mutex_unlock(&dev_priv
->rps
.hw_lock
);
835 * ivybridge_parity_work - Workqueue called when a parity error interrupt
837 * @work: workqueue struct
839 * Doesn't actually do anything except notify userspace. As a consequence of
840 * this event, userspace should try to remap the bad rows since statistically
841 * it is likely the same row is more likely to go bad again.
843 static void ivybridge_parity_work(struct work_struct
*work
)
845 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
846 l3_parity
.error_work
);
847 u32 error_status
, row
, bank
, subbank
;
848 char *parity_event
[5];
852 /* We must turn off DOP level clock gating to access the L3 registers.
853 * In order to prevent a get/put style interface, acquire struct mutex
854 * any time we access those registers.
856 mutex_lock(&dev_priv
->dev
->struct_mutex
);
858 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
859 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
860 POSTING_READ(GEN7_MISCCPCTL
);
862 error_status
= I915_READ(GEN7_L3CDERRST1
);
863 row
= GEN7_PARITY_ERROR_ROW(error_status
);
864 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
865 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
867 I915_WRITE(GEN7_L3CDERRST1
, GEN7_PARITY_ERROR_VALID
|
868 GEN7_L3CDERRST1_ENABLE
);
869 POSTING_READ(GEN7_L3CDERRST1
);
871 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
873 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
874 ilk_enable_gt_irq(dev_priv
, GT_RENDER_L3_PARITY_ERROR_INTERRUPT
);
875 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
877 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
879 parity_event
[0] = I915_L3_PARITY_UEVENT
"=1";
880 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
881 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
882 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
883 parity_event
[4] = NULL
;
885 kobject_uevent_env(&dev_priv
->dev
->primary
->kdev
.kobj
,
886 KOBJ_CHANGE
, parity_event
);
888 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
891 kfree(parity_event
[3]);
892 kfree(parity_event
[2]);
893 kfree(parity_event
[1]);
896 static void ivybridge_parity_error_irq_handler(struct drm_device
*dev
)
898 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
900 if (!HAS_L3_GPU_CACHE(dev
))
903 spin_lock(&dev_priv
->irq_lock
);
904 ilk_disable_gt_irq(dev_priv
, GT_RENDER_L3_PARITY_ERROR_INTERRUPT
);
905 spin_unlock(&dev_priv
->irq_lock
);
907 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
910 static void ilk_gt_irq_handler(struct drm_device
*dev
,
911 struct drm_i915_private
*dev_priv
,
915 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
916 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
917 if (gt_iir
& ILK_BSD_USER_INTERRUPT
)
918 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
921 static void snb_gt_irq_handler(struct drm_device
*dev
,
922 struct drm_i915_private
*dev_priv
,
927 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
928 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
929 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
930 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
931 if (gt_iir
& GT_BLT_USER_INTERRUPT
)
932 notify_ring(dev
, &dev_priv
->ring
[BCS
]);
934 if (gt_iir
& (GT_BLT_CS_ERROR_INTERRUPT
|
935 GT_BSD_CS_ERROR_INTERRUPT
|
936 GT_RENDER_CS_MASTER_ERROR_INTERRUPT
)) {
937 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir
);
938 i915_handle_error(dev
, false);
941 if (gt_iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT
)
942 ivybridge_parity_error_irq_handler(dev
);
945 /* Legacy way of handling PM interrupts */
946 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
,
950 * IIR bits should never already be set because IMR should
951 * prevent an interrupt from being shown in IIR. The warning
952 * displays a case where we've unsafely cleared
953 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
954 * type is not a problem, it displays a problem in the logic.
956 * The mask bit in IMR is cleared by dev_priv->rps.work.
959 spin_lock(&dev_priv
->irq_lock
);
960 dev_priv
->rps
.pm_iir
|= pm_iir
& GEN6_PM_RPS_EVENTS
;
961 snb_disable_pm_irq(dev_priv
, pm_iir
& GEN6_PM_RPS_EVENTS
);
962 spin_unlock(&dev_priv
->irq_lock
);
964 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
967 #define HPD_STORM_DETECT_PERIOD 1000
968 #define HPD_STORM_THRESHOLD 5
970 static inline void intel_hpd_irq_handler(struct drm_device
*dev
,
974 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
976 bool storm_detected
= false;
978 if (!hotplug_trigger
)
981 spin_lock(&dev_priv
->irq_lock
);
982 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
984 WARN(((hpd
[i
] & hotplug_trigger
) &&
985 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
),
986 "Received HPD interrupt although disabled\n");
988 if (!(hpd
[i
] & hotplug_trigger
) ||
989 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
)
992 dev_priv
->hpd_event_bits
|= (1 << i
);
993 if (!time_in_range(jiffies
, dev_priv
->hpd_stats
[i
].hpd_last_jiffies
,
994 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
995 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD
))) {
996 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
= jiffies
;
997 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
998 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i
);
999 } else if (dev_priv
->hpd_stats
[i
].hpd_cnt
> HPD_STORM_THRESHOLD
) {
1000 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_MARK_DISABLED
;
1001 dev_priv
->hpd_event_bits
&= ~(1 << i
);
1002 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i
);
1003 storm_detected
= true;
1005 dev_priv
->hpd_stats
[i
].hpd_cnt
++;
1006 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i
,
1007 dev_priv
->hpd_stats
[i
].hpd_cnt
);
1012 dev_priv
->display
.hpd_irq_setup(dev
);
1013 spin_unlock(&dev_priv
->irq_lock
);
1015 queue_work(dev_priv
->wq
,
1016 &dev_priv
->hotplug_work
);
1019 static void gmbus_irq_handler(struct drm_device
*dev
)
1021 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1023 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1026 static void dp_aux_irq_handler(struct drm_device
*dev
)
1028 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1030 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1033 /* Unlike gen6_rps_irq_handler() from which this function is originally derived,
1034 * we must be able to deal with other PM interrupts. This is complicated because
1035 * of the way in which we use the masks to defer the RPS work (which for
1036 * posterity is necessary because of forcewake).
1038 static void hsw_pm_irq_handler(struct drm_i915_private
*dev_priv
,
1041 if (pm_iir
& GEN6_PM_RPS_EVENTS
) {
1042 spin_lock(&dev_priv
->irq_lock
);
1043 dev_priv
->rps
.pm_iir
|= pm_iir
& GEN6_PM_RPS_EVENTS
;
1044 snb_disable_pm_irq(dev_priv
, pm_iir
& GEN6_PM_RPS_EVENTS
);
1045 spin_unlock(&dev_priv
->irq_lock
);
1047 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
1050 if (pm_iir
& PM_VEBOX_USER_INTERRUPT
)
1051 notify_ring(dev_priv
->dev
, &dev_priv
->ring
[VECS
]);
1053 if (pm_iir
& PM_VEBOX_CS_ERROR_INTERRUPT
) {
1054 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir
);
1055 i915_handle_error(dev_priv
->dev
, false);
1059 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
1061 struct drm_device
*dev
= (struct drm_device
*) arg
;
1062 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1063 u32 iir
, gt_iir
, pm_iir
;
1064 irqreturn_t ret
= IRQ_NONE
;
1065 unsigned long irqflags
;
1067 u32 pipe_stats
[I915_MAX_PIPES
];
1069 atomic_inc(&dev_priv
->irq_received
);
1072 iir
= I915_READ(VLV_IIR
);
1073 gt_iir
= I915_READ(GTIIR
);
1074 pm_iir
= I915_READ(GEN6_PMIIR
);
1076 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
1081 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1083 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1084 for_each_pipe(pipe
) {
1085 int reg
= PIPESTAT(pipe
);
1086 pipe_stats
[pipe
] = I915_READ(reg
);
1089 * Clear the PIPE*STAT regs before the IIR
1091 if (pipe_stats
[pipe
] & 0x8000ffff) {
1092 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
1093 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1095 I915_WRITE(reg
, pipe_stats
[pipe
]);
1098 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1100 for_each_pipe(pipe
) {
1101 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
)
1102 drm_handle_vblank(dev
, pipe
);
1104 if (pipe_stats
[pipe
] & PLANE_FLIPDONE_INT_STATUS_VLV
) {
1105 intel_prepare_page_flip(dev
, pipe
);
1106 intel_finish_page_flip(dev
, pipe
);
1110 /* Consume port. Then clear IIR or we'll miss events */
1111 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
1112 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1113 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
1115 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1118 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
1120 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1121 I915_READ(PORT_HOTPLUG_STAT
);
1124 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1125 gmbus_irq_handler(dev
);
1128 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1130 I915_WRITE(GTIIR
, gt_iir
);
1131 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1132 I915_WRITE(VLV_IIR
, iir
);
1139 static void ibx_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1141 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1143 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK
;
1145 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_ibx
);
1147 if (pch_iir
& SDE_AUDIO_POWER_MASK
) {
1148 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK
) >>
1149 SDE_AUDIO_POWER_SHIFT
);
1150 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1154 if (pch_iir
& SDE_AUX_MASK
)
1155 dp_aux_irq_handler(dev
);
1157 if (pch_iir
& SDE_GMBUS
)
1158 gmbus_irq_handler(dev
);
1160 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
1161 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1163 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
1164 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1166 if (pch_iir
& SDE_POISON
)
1167 DRM_ERROR("PCH poison interrupt\n");
1169 if (pch_iir
& SDE_FDI_MASK
)
1171 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1173 I915_READ(FDI_RX_IIR(pipe
)));
1175 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
1176 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1178 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
1179 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1181 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
1182 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1184 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1186 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
1187 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1189 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1192 static void ivb_err_int_handler(struct drm_device
*dev
)
1194 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1195 u32 err_int
= I915_READ(GEN7_ERR_INT
);
1197 if (err_int
& ERR_INT_POISON
)
1198 DRM_ERROR("Poison interrupt\n");
1200 if (err_int
& ERR_INT_FIFO_UNDERRUN_A
)
1201 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_A
, false))
1202 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1204 if (err_int
& ERR_INT_FIFO_UNDERRUN_B
)
1205 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_B
, false))
1206 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1208 if (err_int
& ERR_INT_FIFO_UNDERRUN_C
)
1209 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_C
, false))
1210 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1212 I915_WRITE(GEN7_ERR_INT
, err_int
);
1215 static void cpt_serr_int_handler(struct drm_device
*dev
)
1217 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1218 u32 serr_int
= I915_READ(SERR_INT
);
1220 if (serr_int
& SERR_INT_POISON
)
1221 DRM_ERROR("PCH poison interrupt\n");
1223 if (serr_int
& SERR_INT_TRANS_A_FIFO_UNDERRUN
)
1224 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1226 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1228 if (serr_int
& SERR_INT_TRANS_B_FIFO_UNDERRUN
)
1229 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1231 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1233 if (serr_int
& SERR_INT_TRANS_C_FIFO_UNDERRUN
)
1234 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_C
,
1236 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1238 I915_WRITE(SERR_INT
, serr_int
);
1241 static void cpt_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1243 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1245 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_CPT
;
1247 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_cpt
);
1249 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) {
1250 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
1251 SDE_AUDIO_POWER_SHIFT_CPT
);
1252 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1256 if (pch_iir
& SDE_AUX_MASK_CPT
)
1257 dp_aux_irq_handler(dev
);
1259 if (pch_iir
& SDE_GMBUS_CPT
)
1260 gmbus_irq_handler(dev
);
1262 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
1263 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1265 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
1266 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1268 if (pch_iir
& SDE_FDI_MASK_CPT
)
1270 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1272 I915_READ(FDI_RX_IIR(pipe
)));
1274 if (pch_iir
& SDE_ERROR_CPT
)
1275 cpt_serr_int_handler(dev
);
1278 static void ilk_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
1280 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1282 if (de_iir
& DE_AUX_CHANNEL_A
)
1283 dp_aux_irq_handler(dev
);
1285 if (de_iir
& DE_GSE
)
1286 intel_opregion_asle_intr(dev
);
1288 if (de_iir
& DE_PIPEA_VBLANK
)
1289 drm_handle_vblank(dev
, 0);
1291 if (de_iir
& DE_PIPEB_VBLANK
)
1292 drm_handle_vblank(dev
, 1);
1294 if (de_iir
& DE_POISON
)
1295 DRM_ERROR("Poison interrupt\n");
1297 if (de_iir
& DE_PIPEA_FIFO_UNDERRUN
)
1298 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_A
, false))
1299 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1301 if (de_iir
& DE_PIPEB_FIFO_UNDERRUN
)
1302 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_B
, false))
1303 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1305 if (de_iir
& DE_PLANEA_FLIP_DONE
) {
1306 intel_prepare_page_flip(dev
, 0);
1307 intel_finish_page_flip_plane(dev
, 0);
1310 if (de_iir
& DE_PLANEB_FLIP_DONE
) {
1311 intel_prepare_page_flip(dev
, 1);
1312 intel_finish_page_flip_plane(dev
, 1);
1315 /* check event from PCH */
1316 if (de_iir
& DE_PCH_EVENT
) {
1317 u32 pch_iir
= I915_READ(SDEIIR
);
1319 if (HAS_PCH_CPT(dev
))
1320 cpt_irq_handler(dev
, pch_iir
);
1322 ibx_irq_handler(dev
, pch_iir
);
1324 /* should clear PCH hotplug event before clear CPU irq */
1325 I915_WRITE(SDEIIR
, pch_iir
);
1328 if (IS_GEN5(dev
) && de_iir
& DE_PCU_EVENT
)
1329 ironlake_rps_change_irq_handler(dev
);
1332 static void ivb_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
1334 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1337 if (de_iir
& DE_ERR_INT_IVB
)
1338 ivb_err_int_handler(dev
);
1340 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
1341 dp_aux_irq_handler(dev
);
1343 if (de_iir
& DE_GSE_IVB
)
1344 intel_opregion_asle_intr(dev
);
1346 for (i
= 0; i
< 3; i
++) {
1347 if (de_iir
& (DE_PIPEA_VBLANK_IVB
<< (5 * i
)))
1348 drm_handle_vblank(dev
, i
);
1349 if (de_iir
& (DE_PLANEA_FLIP_DONE_IVB
<< (5 * i
))) {
1350 intel_prepare_page_flip(dev
, i
);
1351 intel_finish_page_flip_plane(dev
, i
);
1355 /* check event from PCH */
1356 if (!HAS_PCH_NOP(dev
) && (de_iir
& DE_PCH_EVENT_IVB
)) {
1357 u32 pch_iir
= I915_READ(SDEIIR
);
1359 cpt_irq_handler(dev
, pch_iir
);
1361 /* clear PCH hotplug event before clear CPU irq */
1362 I915_WRITE(SDEIIR
, pch_iir
);
1366 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
1368 struct drm_device
*dev
= (struct drm_device
*) arg
;
1369 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1370 u32 de_iir
, gt_iir
, de_ier
, sde_ier
= 0;
1371 irqreturn_t ret
= IRQ_NONE
;
1372 bool err_int_reenable
= false;
1374 atomic_inc(&dev_priv
->irq_received
);
1376 /* We get interrupts on unclaimed registers, so check for this before we
1377 * do any I915_{READ,WRITE}. */
1378 intel_uncore_check_errors(dev
);
1380 /* disable master interrupt before clearing iir */
1381 de_ier
= I915_READ(DEIER
);
1382 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
1383 POSTING_READ(DEIER
);
1385 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1386 * interrupts will will be stored on its back queue, and then we'll be
1387 * able to process them after we restore SDEIER (as soon as we restore
1388 * it, we'll get an interrupt if SDEIIR still has something to process
1389 * due to its back queue). */
1390 if (!HAS_PCH_NOP(dev
)) {
1391 sde_ier
= I915_READ(SDEIER
);
1392 I915_WRITE(SDEIER
, 0);
1393 POSTING_READ(SDEIER
);
1396 /* On Haswell, also mask ERR_INT because we don't want to risk
1397 * generating "unclaimed register" interrupts from inside the interrupt
1399 if (IS_HASWELL(dev
)) {
1400 spin_lock(&dev_priv
->irq_lock
);
1401 err_int_reenable
= ~dev_priv
->irq_mask
& DE_ERR_INT_IVB
;
1402 if (err_int_reenable
)
1403 ironlake_disable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
1404 spin_unlock(&dev_priv
->irq_lock
);
1407 gt_iir
= I915_READ(GTIIR
);
1409 if (INTEL_INFO(dev
)->gen
>= 6)
1410 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1412 ilk_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1413 I915_WRITE(GTIIR
, gt_iir
);
1417 de_iir
= I915_READ(DEIIR
);
1419 if (INTEL_INFO(dev
)->gen
>= 7)
1420 ivb_display_irq_handler(dev
, de_iir
);
1422 ilk_display_irq_handler(dev
, de_iir
);
1423 I915_WRITE(DEIIR
, de_iir
);
1427 if (INTEL_INFO(dev
)->gen
>= 6) {
1428 u32 pm_iir
= I915_READ(GEN6_PMIIR
);
1430 if (IS_HASWELL(dev
))
1431 hsw_pm_irq_handler(dev_priv
, pm_iir
);
1433 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1434 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1439 if (err_int_reenable
) {
1440 spin_lock(&dev_priv
->irq_lock
);
1441 if (ivb_can_enable_err_int(dev
))
1442 ironlake_enable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
1443 spin_unlock(&dev_priv
->irq_lock
);
1446 I915_WRITE(DEIER
, de_ier
);
1447 POSTING_READ(DEIER
);
1448 if (!HAS_PCH_NOP(dev
)) {
1449 I915_WRITE(SDEIER
, sde_ier
);
1450 POSTING_READ(SDEIER
);
1457 * i915_error_work_func - do process context error handling work
1458 * @work: work struct
1460 * Fire an error uevent so userspace can see that a hang or error
1463 static void i915_error_work_func(struct work_struct
*work
)
1465 struct i915_gpu_error
*error
= container_of(work
, struct i915_gpu_error
,
1467 drm_i915_private_t
*dev_priv
= container_of(error
, drm_i915_private_t
,
1469 struct drm_device
*dev
= dev_priv
->dev
;
1470 struct intel_ring_buffer
*ring
;
1471 char *error_event
[] = { I915_ERROR_UEVENT
"=1", NULL
};
1472 char *reset_event
[] = { I915_RESET_UEVENT
"=1", NULL
};
1473 char *reset_done_event
[] = { I915_ERROR_UEVENT
"=0", NULL
};
1476 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
, error_event
);
1479 * Note that there's only one work item which does gpu resets, so we
1480 * need not worry about concurrent gpu resets potentially incrementing
1481 * error->reset_counter twice. We only need to take care of another
1482 * racing irq/hangcheck declaring the gpu dead for a second time. A
1483 * quick check for that is good enough: schedule_work ensures the
1484 * correct ordering between hang detection and this work item, and since
1485 * the reset in-progress bit is only ever set by code outside of this
1486 * work we don't need to worry about any other races.
1488 if (i915_reset_in_progress(error
) && !i915_terminally_wedged(error
)) {
1489 DRM_DEBUG_DRIVER("resetting chip\n");
1490 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
,
1493 ret
= i915_reset(dev
);
1497 * After all the gem state is reset, increment the reset
1498 * counter and wake up everyone waiting for the reset to
1501 * Since unlock operations are a one-sided barrier only,
1502 * we need to insert a barrier here to order any seqno
1504 * the counter increment.
1506 smp_mb__before_atomic_inc();
1507 atomic_inc(&dev_priv
->gpu_error
.reset_counter
);
1509 kobject_uevent_env(&dev
->primary
->kdev
.kobj
,
1510 KOBJ_CHANGE
, reset_done_event
);
1512 atomic_set(&error
->reset_counter
, I915_WEDGED
);
1515 for_each_ring(ring
, dev_priv
, i
)
1516 wake_up_all(&ring
->irq_queue
);
1518 intel_display_handle_reset(dev
);
1520 wake_up_all(&dev_priv
->gpu_error
.reset_queue
);
1524 static void i915_report_and_clear_eir(struct drm_device
*dev
)
1526 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1527 uint32_t instdone
[I915_NUM_INSTDONE_REG
];
1528 u32 eir
= I915_READ(EIR
);
1534 pr_err("render error detected, EIR: 0x%08x\n", eir
);
1536 i915_get_extra_instdone(dev
, instdone
);
1539 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
1540 u32 ipeir
= I915_READ(IPEIR_I965
);
1542 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1543 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1544 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
1545 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
1546 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1547 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1548 I915_WRITE(IPEIR_I965
, ipeir
);
1549 POSTING_READ(IPEIR_I965
);
1551 if (eir
& GM45_ERROR_PAGE_TABLE
) {
1552 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1553 pr_err("page table error\n");
1554 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1555 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1556 POSTING_READ(PGTBL_ER
);
1560 if (!IS_GEN2(dev
)) {
1561 if (eir
& I915_ERROR_PAGE_TABLE
) {
1562 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1563 pr_err("page table error\n");
1564 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1565 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1566 POSTING_READ(PGTBL_ER
);
1570 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
1571 pr_err("memory refresh error:\n");
1573 pr_err("pipe %c stat: 0x%08x\n",
1574 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
1575 /* pipestat has already been acked */
1577 if (eir
& I915_ERROR_INSTRUCTION
) {
1578 pr_err("instruction error\n");
1579 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
1580 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
1581 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
1582 if (INTEL_INFO(dev
)->gen
< 4) {
1583 u32 ipeir
= I915_READ(IPEIR
);
1585 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
1586 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
1587 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
1588 I915_WRITE(IPEIR
, ipeir
);
1589 POSTING_READ(IPEIR
);
1591 u32 ipeir
= I915_READ(IPEIR_I965
);
1593 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1594 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1595 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1596 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1597 I915_WRITE(IPEIR_I965
, ipeir
);
1598 POSTING_READ(IPEIR_I965
);
1602 I915_WRITE(EIR
, eir
);
1604 eir
= I915_READ(EIR
);
1607 * some errors might have become stuck,
1610 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
1611 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
1612 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
1617 * i915_handle_error - handle an error interrupt
1620 * Do some basic checking of regsiter state at error interrupt time and
1621 * dump it to the syslog. Also call i915_capture_error_state() to make
1622 * sure we get a record and make it available in debugfs. Fire a uevent
1623 * so userspace knows something bad happened (should trigger collection
1624 * of a ring dump etc.).
1626 void i915_handle_error(struct drm_device
*dev
, bool wedged
)
1628 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1629 struct intel_ring_buffer
*ring
;
1632 i915_capture_error_state(dev
);
1633 i915_report_and_clear_eir(dev
);
1636 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG
,
1637 &dev_priv
->gpu_error
.reset_counter
);
1640 * Wakeup waiting processes so that the reset work item
1641 * doesn't deadlock trying to grab various locks.
1643 for_each_ring(ring
, dev_priv
, i
)
1644 wake_up_all(&ring
->irq_queue
);
1647 queue_work(dev_priv
->wq
, &dev_priv
->gpu_error
.work
);
1650 static void __always_unused
i915_pageflip_stall_check(struct drm_device
*dev
, int pipe
)
1652 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1653 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1654 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1655 struct drm_i915_gem_object
*obj
;
1656 struct intel_unpin_work
*work
;
1657 unsigned long flags
;
1658 bool stall_detected
;
1660 /* Ignore early vblank irqs */
1661 if (intel_crtc
== NULL
)
1664 spin_lock_irqsave(&dev
->event_lock
, flags
);
1665 work
= intel_crtc
->unpin_work
;
1668 atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
||
1669 !work
->enable_stall_check
) {
1670 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1671 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1675 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1676 obj
= work
->pending_flip_obj
;
1677 if (INTEL_INFO(dev
)->gen
>= 4) {
1678 int dspsurf
= DSPSURF(intel_crtc
->plane
);
1679 stall_detected
= I915_HI_DISPBASE(I915_READ(dspsurf
)) ==
1680 i915_gem_obj_ggtt_offset(obj
);
1682 int dspaddr
= DSPADDR(intel_crtc
->plane
);
1683 stall_detected
= I915_READ(dspaddr
) == (i915_gem_obj_ggtt_offset(obj
) +
1684 crtc
->y
* crtc
->fb
->pitches
[0] +
1685 crtc
->x
* crtc
->fb
->bits_per_pixel
/8);
1688 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1690 if (stall_detected
) {
1691 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1692 intel_prepare_page_flip(dev
, intel_crtc
->plane
);
1696 /* Called from drm generic code, passed 'crtc' which
1697 * we use as a pipe index
1699 static int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
1701 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1702 unsigned long irqflags
;
1704 if (!i915_pipe_enabled(dev
, pipe
))
1707 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1708 if (INTEL_INFO(dev
)->gen
>= 4)
1709 i915_enable_pipestat(dev_priv
, pipe
,
1710 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1712 i915_enable_pipestat(dev_priv
, pipe
,
1713 PIPE_VBLANK_INTERRUPT_ENABLE
);
1715 /* maintain vblank delivery even in deep C-states */
1716 if (dev_priv
->info
->gen
== 3)
1717 I915_WRITE(INSTPM
, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS
));
1718 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1723 static int ironlake_enable_vblank(struct drm_device
*dev
, int pipe
)
1725 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1726 unsigned long irqflags
;
1727 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
1728 DE_PIPE_VBLANK_ILK(pipe
);
1730 if (!i915_pipe_enabled(dev
, pipe
))
1733 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1734 ironlake_enable_display_irq(dev_priv
, bit
);
1735 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1740 static int valleyview_enable_vblank(struct drm_device
*dev
, int pipe
)
1742 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1743 unsigned long irqflags
;
1746 if (!i915_pipe_enabled(dev
, pipe
))
1749 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1750 imr
= I915_READ(VLV_IMR
);
1752 imr
&= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
1754 imr
&= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1755 I915_WRITE(VLV_IMR
, imr
);
1756 i915_enable_pipestat(dev_priv
, pipe
,
1757 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1758 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1763 /* Called from drm generic code, passed 'crtc' which
1764 * we use as a pipe index
1766 static void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
1768 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1769 unsigned long irqflags
;
1771 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1772 if (dev_priv
->info
->gen
== 3)
1773 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS
));
1775 i915_disable_pipestat(dev_priv
, pipe
,
1776 PIPE_VBLANK_INTERRUPT_ENABLE
|
1777 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1778 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1781 static void ironlake_disable_vblank(struct drm_device
*dev
, int pipe
)
1783 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1784 unsigned long irqflags
;
1785 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
1786 DE_PIPE_VBLANK_ILK(pipe
);
1788 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1789 ironlake_disable_display_irq(dev_priv
, bit
);
1790 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1793 static void valleyview_disable_vblank(struct drm_device
*dev
, int pipe
)
1795 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1796 unsigned long irqflags
;
1799 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1800 i915_disable_pipestat(dev_priv
, pipe
,
1801 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1802 imr
= I915_READ(VLV_IMR
);
1804 imr
|= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
1806 imr
|= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1807 I915_WRITE(VLV_IMR
, imr
);
1808 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1812 ring_last_seqno(struct intel_ring_buffer
*ring
)
1814 return list_entry(ring
->request_list
.prev
,
1815 struct drm_i915_gem_request
, list
)->seqno
;
1819 ring_idle(struct intel_ring_buffer
*ring
, u32 seqno
)
1821 return (list_empty(&ring
->request_list
) ||
1822 i915_seqno_passed(seqno
, ring_last_seqno(ring
)));
1825 static struct intel_ring_buffer
*
1826 semaphore_waits_for(struct intel_ring_buffer
*ring
, u32
*seqno
)
1828 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1829 u32 cmd
, ipehr
, acthd
, acthd_min
;
1831 ipehr
= I915_READ(RING_IPEHR(ring
->mmio_base
));
1832 if ((ipehr
& ~(0x3 << 16)) !=
1833 (MI_SEMAPHORE_MBOX
| MI_SEMAPHORE_COMPARE
| MI_SEMAPHORE_REGISTER
))
1836 /* ACTHD is likely pointing to the dword after the actual command,
1837 * so scan backwards until we find the MBOX.
1839 acthd
= intel_ring_get_active_head(ring
) & HEAD_ADDR
;
1840 acthd_min
= max((int)acthd
- 3 * 4, 0);
1842 cmd
= ioread32(ring
->virtual_start
+ acthd
);
1847 if (acthd
< acthd_min
)
1851 *seqno
= ioread32(ring
->virtual_start
+acthd
+4)+1;
1852 return &dev_priv
->ring
[(ring
->id
+ (((ipehr
>> 17) & 1) + 1)) % 3];
1855 static int semaphore_passed(struct intel_ring_buffer
*ring
)
1857 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1858 struct intel_ring_buffer
*signaller
;
1861 ring
->hangcheck
.deadlock
= true;
1863 signaller
= semaphore_waits_for(ring
, &seqno
);
1864 if (signaller
== NULL
|| signaller
->hangcheck
.deadlock
)
1867 /* cursory check for an unkickable deadlock */
1868 ctl
= I915_READ_CTL(signaller
);
1869 if (ctl
& RING_WAIT_SEMAPHORE
&& semaphore_passed(signaller
) < 0)
1872 return i915_seqno_passed(signaller
->get_seqno(signaller
, false), seqno
);
1875 static void semaphore_clear_deadlocks(struct drm_i915_private
*dev_priv
)
1877 struct intel_ring_buffer
*ring
;
1880 for_each_ring(ring
, dev_priv
, i
)
1881 ring
->hangcheck
.deadlock
= false;
1884 static enum intel_ring_hangcheck_action
1885 ring_stuck(struct intel_ring_buffer
*ring
, u32 acthd
)
1887 struct drm_device
*dev
= ring
->dev
;
1888 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1891 if (ring
->hangcheck
.acthd
!= acthd
)
1892 return HANGCHECK_ACTIVE
;
1895 return HANGCHECK_HUNG
;
1897 /* Is the chip hanging on a WAIT_FOR_EVENT?
1898 * If so we can simply poke the RB_WAIT bit
1899 * and break the hang. This should work on
1900 * all but the second generation chipsets.
1902 tmp
= I915_READ_CTL(ring
);
1903 if (tmp
& RING_WAIT
) {
1904 DRM_ERROR("Kicking stuck wait on %s\n",
1906 I915_WRITE_CTL(ring
, tmp
);
1907 return HANGCHECK_KICK
;
1910 if (INTEL_INFO(dev
)->gen
>= 6 && tmp
& RING_WAIT_SEMAPHORE
) {
1911 switch (semaphore_passed(ring
)) {
1913 return HANGCHECK_HUNG
;
1915 DRM_ERROR("Kicking stuck semaphore on %s\n",
1917 I915_WRITE_CTL(ring
, tmp
);
1918 return HANGCHECK_KICK
;
1920 return HANGCHECK_WAIT
;
1924 return HANGCHECK_HUNG
;
1928 * This is called when the chip hasn't reported back with completed
1929 * batchbuffers in a long time. We keep track per ring seqno progress and
1930 * if there are no progress, hangcheck score for that ring is increased.
1931 * Further, acthd is inspected to see if the ring is stuck. On stuck case
1932 * we kick the ring. If we see no progress on three subsequent calls
1933 * we assume chip is wedged and try to fix it by resetting the chip.
1935 static void i915_hangcheck_elapsed(unsigned long data
)
1937 struct drm_device
*dev
= (struct drm_device
*)data
;
1938 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1939 struct intel_ring_buffer
*ring
;
1941 int busy_count
= 0, rings_hung
= 0;
1942 bool stuck
[I915_NUM_RINGS
] = { 0 };
1948 if (!i915_enable_hangcheck
)
1951 for_each_ring(ring
, dev_priv
, i
) {
1955 semaphore_clear_deadlocks(dev_priv
);
1957 seqno
= ring
->get_seqno(ring
, false);
1958 acthd
= intel_ring_get_active_head(ring
);
1960 if (ring
->hangcheck
.seqno
== seqno
) {
1961 if (ring_idle(ring
, seqno
)) {
1962 if (waitqueue_active(&ring
->irq_queue
)) {
1963 /* Issue a wake-up to catch stuck h/w. */
1964 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1966 wake_up_all(&ring
->irq_queue
);
1967 ring
->hangcheck
.score
+= HUNG
;
1971 /* We always increment the hangcheck score
1972 * if the ring is busy and still processing
1973 * the same request, so that no single request
1974 * can run indefinitely (such as a chain of
1975 * batches). The only time we do not increment
1976 * the hangcheck score on this ring, if this
1977 * ring is in a legitimate wait for another
1978 * ring. In that case the waiting ring is a
1979 * victim and we want to be sure we catch the
1980 * right culprit. Then every time we do kick
1981 * the ring, add a small increment to the
1982 * score so that we can catch a batch that is
1983 * being repeatedly kicked and so responsible
1984 * for stalling the machine.
1986 ring
->hangcheck
.action
= ring_stuck(ring
,
1989 switch (ring
->hangcheck
.action
) {
1990 case HANGCHECK_WAIT
:
1992 case HANGCHECK_ACTIVE
:
1993 ring
->hangcheck
.score
+= BUSY
;
1995 case HANGCHECK_KICK
:
1996 ring
->hangcheck
.score
+= KICK
;
1998 case HANGCHECK_HUNG
:
1999 ring
->hangcheck
.score
+= HUNG
;
2005 /* Gradually reduce the count so that we catch DoS
2006 * attempts across multiple batches.
2008 if (ring
->hangcheck
.score
> 0)
2009 ring
->hangcheck
.score
--;
2012 ring
->hangcheck
.seqno
= seqno
;
2013 ring
->hangcheck
.acthd
= acthd
;
2017 for_each_ring(ring
, dev_priv
, i
) {
2018 if (ring
->hangcheck
.score
> FIRE
) {
2019 DRM_ERROR("%s on %s\n",
2020 stuck
[i
] ? "stuck" : "no progress",
2027 return i915_handle_error(dev
, true);
2030 /* Reset timer case chip hangs without another request
2032 i915_queue_hangcheck(dev
);
2035 void i915_queue_hangcheck(struct drm_device
*dev
)
2037 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2038 if (!i915_enable_hangcheck
)
2041 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
2042 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
2045 static void ibx_irq_preinstall(struct drm_device
*dev
)
2047 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2049 if (HAS_PCH_NOP(dev
))
2052 /* south display irq */
2053 I915_WRITE(SDEIMR
, 0xffffffff);
2055 * SDEIER is also touched by the interrupt handler to work around missed
2056 * PCH interrupts. Hence we can't update it after the interrupt handler
2057 * is enabled - instead we unconditionally enable all PCH interrupt
2058 * sources here, but then only unmask them as needed with SDEIMR.
2060 I915_WRITE(SDEIER
, 0xffffffff);
2061 POSTING_READ(SDEIER
);
2064 static void gen5_gt_irq_preinstall(struct drm_device
*dev
)
2066 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2069 I915_WRITE(GTIMR
, 0xffffffff);
2070 I915_WRITE(GTIER
, 0x0);
2071 POSTING_READ(GTIER
);
2073 if (INTEL_INFO(dev
)->gen
>= 6) {
2075 I915_WRITE(GEN6_PMIMR
, 0xffffffff);
2076 I915_WRITE(GEN6_PMIER
, 0x0);
2077 POSTING_READ(GEN6_PMIER
);
2083 static void ironlake_irq_preinstall(struct drm_device
*dev
)
2085 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2087 atomic_set(&dev_priv
->irq_received
, 0);
2089 I915_WRITE(HWSTAM
, 0xeffe);
2091 I915_WRITE(DEIMR
, 0xffffffff);
2092 I915_WRITE(DEIER
, 0x0);
2093 POSTING_READ(DEIER
);
2095 gen5_gt_irq_preinstall(dev
);
2097 ibx_irq_preinstall(dev
);
2100 static void valleyview_irq_preinstall(struct drm_device
*dev
)
2102 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2105 atomic_set(&dev_priv
->irq_received
, 0);
2108 I915_WRITE(VLV_IMR
, 0);
2109 I915_WRITE(RING_IMR(RENDER_RING_BASE
), 0);
2110 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE
), 0);
2111 I915_WRITE(RING_IMR(BLT_RING_BASE
), 0);
2114 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2115 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2117 gen5_gt_irq_preinstall(dev
);
2119 I915_WRITE(DPINVGTT
, 0xff);
2121 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2122 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2124 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2125 I915_WRITE(VLV_IIR
, 0xffffffff);
2126 I915_WRITE(VLV_IMR
, 0xffffffff);
2127 I915_WRITE(VLV_IER
, 0x0);
2128 POSTING_READ(VLV_IER
);
2131 static void ibx_hpd_irq_setup(struct drm_device
*dev
)
2133 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2134 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2135 struct intel_encoder
*intel_encoder
;
2136 u32 hotplug_irqs
, hotplug
, enabled_irqs
= 0;
2138 if (HAS_PCH_IBX(dev
)) {
2139 hotplug_irqs
= SDE_HOTPLUG_MASK
;
2140 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2141 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2142 enabled_irqs
|= hpd_ibx
[intel_encoder
->hpd_pin
];
2144 hotplug_irqs
= SDE_HOTPLUG_MASK_CPT
;
2145 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2146 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2147 enabled_irqs
|= hpd_cpt
[intel_encoder
->hpd_pin
];
2150 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
2153 * Enable digital hotplug on the PCH, and configure the DP short pulse
2154 * duration to 2ms (which is the minimum in the Display Port spec)
2156 * This register is the same on all known PCH chips.
2158 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
2159 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
2160 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
2161 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
2162 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
2163 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
2166 static void ibx_irq_postinstall(struct drm_device
*dev
)
2168 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2171 if (HAS_PCH_NOP(dev
))
2174 if (HAS_PCH_IBX(dev
)) {
2175 mask
= SDE_GMBUS
| SDE_AUX_MASK
| SDE_TRANSB_FIFO_UNDER
|
2176 SDE_TRANSA_FIFO_UNDER
| SDE_POISON
;
2178 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
| SDE_ERROR_CPT
;
2180 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2183 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2184 I915_WRITE(SDEIMR
, ~mask
);
2187 static void gen5_gt_irq_postinstall(struct drm_device
*dev
)
2189 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2190 u32 pm_irqs
, gt_irqs
;
2192 pm_irqs
= gt_irqs
= 0;
2194 dev_priv
->gt_irq_mask
= ~0;
2195 if (HAS_L3_GPU_CACHE(dev
)) {
2196 /* L3 parity interrupt is always unmasked. */
2197 dev_priv
->gt_irq_mask
= ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
2198 gt_irqs
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
2201 gt_irqs
|= GT_RENDER_USER_INTERRUPT
;
2203 gt_irqs
|= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
|
2204 ILK_BSD_USER_INTERRUPT
;
2206 gt_irqs
|= GT_BLT_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
;
2209 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2210 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
2211 I915_WRITE(GTIER
, gt_irqs
);
2212 POSTING_READ(GTIER
);
2214 if (INTEL_INFO(dev
)->gen
>= 6) {
2215 pm_irqs
|= GEN6_PM_RPS_EVENTS
;
2218 pm_irqs
|= PM_VEBOX_USER_INTERRUPT
;
2220 dev_priv
->pm_irq_mask
= 0xffffffff;
2221 I915_WRITE(GEN6_PMIIR
, I915_READ(GEN6_PMIIR
));
2222 I915_WRITE(GEN6_PMIMR
, dev_priv
->pm_irq_mask
);
2223 I915_WRITE(GEN6_PMIER
, pm_irqs
);
2224 POSTING_READ(GEN6_PMIER
);
2228 static int ironlake_irq_postinstall(struct drm_device
*dev
)
2230 unsigned long irqflags
;
2231 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2232 u32 display_mask
, extra_mask
;
2234 if (INTEL_INFO(dev
)->gen
>= 7) {
2235 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
|
2236 DE_PCH_EVENT_IVB
| DE_PLANEC_FLIP_DONE_IVB
|
2237 DE_PLANEB_FLIP_DONE_IVB
|
2238 DE_PLANEA_FLIP_DONE_IVB
| DE_AUX_CHANNEL_A_IVB
|
2240 extra_mask
= (DE_PIPEC_VBLANK_IVB
| DE_PIPEB_VBLANK_IVB
|
2241 DE_PIPEA_VBLANK_IVB
);
2243 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2245 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
2246 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
|
2247 DE_AUX_CHANNEL_A
| DE_PIPEB_FIFO_UNDERRUN
|
2248 DE_PIPEA_FIFO_UNDERRUN
| DE_POISON
);
2249 extra_mask
= DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
| DE_PCU_EVENT
;
2252 dev_priv
->irq_mask
= ~display_mask
;
2254 /* should always can generate irq */
2255 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2256 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
2257 I915_WRITE(DEIER
, display_mask
| extra_mask
);
2258 POSTING_READ(DEIER
);
2260 gen5_gt_irq_postinstall(dev
);
2262 ibx_irq_postinstall(dev
);
2264 if (IS_IRONLAKE_M(dev
)) {
2265 /* Enable PCU event interrupts
2267 * spinlocking not required here for correctness since interrupt
2268 * setup is guaranteed to run in single-threaded context. But we
2269 * need it to make the assert_spin_locked happy. */
2270 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2271 ironlake_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
2272 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2278 static int valleyview_irq_postinstall(struct drm_device
*dev
)
2280 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2282 u32 pipestat_enable
= PLANE_FLIP_DONE_INT_EN_VLV
;
2283 unsigned long irqflags
;
2285 enable_mask
= I915_DISPLAY_PORT_INTERRUPT
;
2286 enable_mask
|= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2287 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2288 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2289 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2292 *Leave vblank interrupts masked initially. enable/disable will
2293 * toggle them based on usage.
2295 dev_priv
->irq_mask
= (~enable_mask
) |
2296 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2297 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2299 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2300 POSTING_READ(PORT_HOTPLUG_EN
);
2302 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
2303 I915_WRITE(VLV_IER
, enable_mask
);
2304 I915_WRITE(VLV_IIR
, 0xffffffff);
2305 I915_WRITE(PIPESTAT(0), 0xffff);
2306 I915_WRITE(PIPESTAT(1), 0xffff);
2307 POSTING_READ(VLV_IER
);
2309 /* Interrupt setup is already guaranteed to be single-threaded, this is
2310 * just to make the assert_spin_locked check happy. */
2311 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2312 i915_enable_pipestat(dev_priv
, 0, pipestat_enable
);
2313 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
2314 i915_enable_pipestat(dev_priv
, 1, pipestat_enable
);
2315 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2317 I915_WRITE(VLV_IIR
, 0xffffffff);
2318 I915_WRITE(VLV_IIR
, 0xffffffff);
2320 gen5_gt_irq_postinstall(dev
);
2322 /* ack & enable invalid PTE error interrupts */
2323 #if 0 /* FIXME: add support to irq handler for checking these bits */
2324 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
2325 I915_WRITE(DPINVGTT
, DPINVGTT_EN_MASK
);
2328 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
2333 static void valleyview_irq_uninstall(struct drm_device
*dev
)
2335 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2341 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2344 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2346 I915_WRITE(HWSTAM
, 0xffffffff);
2347 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2348 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2350 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2351 I915_WRITE(VLV_IIR
, 0xffffffff);
2352 I915_WRITE(VLV_IMR
, 0xffffffff);
2353 I915_WRITE(VLV_IER
, 0x0);
2354 POSTING_READ(VLV_IER
);
2357 static void ironlake_irq_uninstall(struct drm_device
*dev
)
2359 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2364 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2366 I915_WRITE(HWSTAM
, 0xffffffff);
2368 I915_WRITE(DEIMR
, 0xffffffff);
2369 I915_WRITE(DEIER
, 0x0);
2370 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2372 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2374 I915_WRITE(GTIMR
, 0xffffffff);
2375 I915_WRITE(GTIER
, 0x0);
2376 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2378 if (HAS_PCH_NOP(dev
))
2381 I915_WRITE(SDEIMR
, 0xffffffff);
2382 I915_WRITE(SDEIER
, 0x0);
2383 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2384 if (HAS_PCH_CPT(dev
) || HAS_PCH_LPT(dev
))
2385 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2388 static void i8xx_irq_preinstall(struct drm_device
* dev
)
2390 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2393 atomic_set(&dev_priv
->irq_received
, 0);
2396 I915_WRITE(PIPESTAT(pipe
), 0);
2397 I915_WRITE16(IMR
, 0xffff);
2398 I915_WRITE16(IER
, 0x0);
2399 POSTING_READ16(IER
);
2402 static int i8xx_irq_postinstall(struct drm_device
*dev
)
2404 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2407 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2409 /* Unmask the interrupts that we always want on. */
2410 dev_priv
->irq_mask
=
2411 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2412 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2413 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2414 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2415 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2416 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
2419 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2420 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2421 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2422 I915_USER_INTERRUPT
);
2423 POSTING_READ16(IER
);
2429 * Returns true when a page flip has completed.
2431 static bool i8xx_handle_vblank(struct drm_device
*dev
,
2434 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2435 u16 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(pipe
);
2437 if (!drm_handle_vblank(dev
, pipe
))
2440 if ((iir
& flip_pending
) == 0)
2443 intel_prepare_page_flip(dev
, pipe
);
2445 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2446 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2447 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2448 * the flip is completed (no longer pending). Since this doesn't raise
2449 * an interrupt per se, we watch for the change at vblank.
2451 if (I915_READ16(ISR
) & flip_pending
)
2454 intel_finish_page_flip(dev
, pipe
);
2459 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
2461 struct drm_device
*dev
= (struct drm_device
*) arg
;
2462 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2465 unsigned long irqflags
;
2468 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2469 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2471 atomic_inc(&dev_priv
->irq_received
);
2473 iir
= I915_READ16(IIR
);
2477 while (iir
& ~flip_mask
) {
2478 /* Can't rely on pipestat interrupt bit in iir as it might
2479 * have been cleared after the pipestat interrupt was received.
2480 * It doesn't set the bit in iir again, but it still produces
2481 * interrupts (for non-MSI).
2483 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2484 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2485 i915_handle_error(dev
, false);
2487 for_each_pipe(pipe
) {
2488 int reg
= PIPESTAT(pipe
);
2489 pipe_stats
[pipe
] = I915_READ(reg
);
2492 * Clear the PIPE*STAT regs before the IIR
2494 if (pipe_stats
[pipe
] & 0x8000ffff) {
2495 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2496 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2498 I915_WRITE(reg
, pipe_stats
[pipe
]);
2501 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2503 I915_WRITE16(IIR
, iir
& ~flip_mask
);
2504 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
2506 i915_update_dri1_breadcrumb(dev
);
2508 if (iir
& I915_USER_INTERRUPT
)
2509 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2511 if (pipe_stats
[0] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2512 i8xx_handle_vblank(dev
, 0, iir
))
2513 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(0);
2515 if (pipe_stats
[1] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2516 i8xx_handle_vblank(dev
, 1, iir
))
2517 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(1);
2525 static void i8xx_irq_uninstall(struct drm_device
* dev
)
2527 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2530 for_each_pipe(pipe
) {
2531 /* Clear enable bits; then clear status bits */
2532 I915_WRITE(PIPESTAT(pipe
), 0);
2533 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
2535 I915_WRITE16(IMR
, 0xffff);
2536 I915_WRITE16(IER
, 0x0);
2537 I915_WRITE16(IIR
, I915_READ16(IIR
));
2540 static void i915_irq_preinstall(struct drm_device
* dev
)
2542 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2545 atomic_set(&dev_priv
->irq_received
, 0);
2547 if (I915_HAS_HOTPLUG(dev
)) {
2548 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2549 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2552 I915_WRITE16(HWSTAM
, 0xeffe);
2554 I915_WRITE(PIPESTAT(pipe
), 0);
2555 I915_WRITE(IMR
, 0xffffffff);
2556 I915_WRITE(IER
, 0x0);
2560 static int i915_irq_postinstall(struct drm_device
*dev
)
2562 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2565 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2567 /* Unmask the interrupts that we always want on. */
2568 dev_priv
->irq_mask
=
2569 ~(I915_ASLE_INTERRUPT
|
2570 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2571 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2572 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2573 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2574 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2577 I915_ASLE_INTERRUPT
|
2578 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2579 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2580 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2581 I915_USER_INTERRUPT
;
2583 if (I915_HAS_HOTPLUG(dev
)) {
2584 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2585 POSTING_READ(PORT_HOTPLUG_EN
);
2587 /* Enable in IER... */
2588 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
2589 /* and unmask in IMR */
2590 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
2593 I915_WRITE(IMR
, dev_priv
->irq_mask
);
2594 I915_WRITE(IER
, enable_mask
);
2597 i915_enable_asle_pipestat(dev
);
2603 * Returns true when a page flip has completed.
2605 static bool i915_handle_vblank(struct drm_device
*dev
,
2606 int plane
, int pipe
, u32 iir
)
2608 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2609 u32 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
2611 if (!drm_handle_vblank(dev
, pipe
))
2614 if ((iir
& flip_pending
) == 0)
2617 intel_prepare_page_flip(dev
, plane
);
2619 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2620 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2621 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2622 * the flip is completed (no longer pending). Since this doesn't raise
2623 * an interrupt per se, we watch for the change at vblank.
2625 if (I915_READ(ISR
) & flip_pending
)
2628 intel_finish_page_flip(dev
, pipe
);
2633 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
2635 struct drm_device
*dev
= (struct drm_device
*) arg
;
2636 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2637 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
2638 unsigned long irqflags
;
2640 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2641 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2642 int pipe
, ret
= IRQ_NONE
;
2644 atomic_inc(&dev_priv
->irq_received
);
2646 iir
= I915_READ(IIR
);
2648 bool irq_received
= (iir
& ~flip_mask
) != 0;
2649 bool blc_event
= false;
2651 /* Can't rely on pipestat interrupt bit in iir as it might
2652 * have been cleared after the pipestat interrupt was received.
2653 * It doesn't set the bit in iir again, but it still produces
2654 * interrupts (for non-MSI).
2656 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2657 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2658 i915_handle_error(dev
, false);
2660 for_each_pipe(pipe
) {
2661 int reg
= PIPESTAT(pipe
);
2662 pipe_stats
[pipe
] = I915_READ(reg
);
2664 /* Clear the PIPE*STAT regs before the IIR */
2665 if (pipe_stats
[pipe
] & 0x8000ffff) {
2666 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2667 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2669 I915_WRITE(reg
, pipe_stats
[pipe
]);
2670 irq_received
= true;
2673 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2678 /* Consume port. Then clear IIR or we'll miss events */
2679 if ((I915_HAS_HOTPLUG(dev
)) &&
2680 (iir
& I915_DISPLAY_PORT_INTERRUPT
)) {
2681 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
2682 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
2684 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2687 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
2689 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
2690 POSTING_READ(PORT_HOTPLUG_STAT
);
2693 I915_WRITE(IIR
, iir
& ~flip_mask
);
2694 new_iir
= I915_READ(IIR
); /* Flush posted writes */
2696 if (iir
& I915_USER_INTERRUPT
)
2697 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2699 for_each_pipe(pipe
) {
2704 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2705 i915_handle_vblank(dev
, plane
, pipe
, iir
))
2706 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
2708 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
2712 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
2713 intel_opregion_asle_intr(dev
);
2715 /* With MSI, interrupts are only generated when iir
2716 * transitions from zero to nonzero. If another bit got
2717 * set while we were handling the existing iir bits, then
2718 * we would never get another interrupt.
2720 * This is fine on non-MSI as well, as if we hit this path
2721 * we avoid exiting the interrupt handler only to generate
2724 * Note that for MSI this could cause a stray interrupt report
2725 * if an interrupt landed in the time between writing IIR and
2726 * the posting read. This should be rare enough to never
2727 * trigger the 99% of 100,000 interrupts test for disabling
2732 } while (iir
& ~flip_mask
);
2734 i915_update_dri1_breadcrumb(dev
);
2739 static void i915_irq_uninstall(struct drm_device
* dev
)
2741 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2744 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2746 if (I915_HAS_HOTPLUG(dev
)) {
2747 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2748 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2751 I915_WRITE16(HWSTAM
, 0xffff);
2752 for_each_pipe(pipe
) {
2753 /* Clear enable bits; then clear status bits */
2754 I915_WRITE(PIPESTAT(pipe
), 0);
2755 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
2757 I915_WRITE(IMR
, 0xffffffff);
2758 I915_WRITE(IER
, 0x0);
2760 I915_WRITE(IIR
, I915_READ(IIR
));
2763 static void i965_irq_preinstall(struct drm_device
* dev
)
2765 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2768 atomic_set(&dev_priv
->irq_received
, 0);
2770 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2771 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2773 I915_WRITE(HWSTAM
, 0xeffe);
2775 I915_WRITE(PIPESTAT(pipe
), 0);
2776 I915_WRITE(IMR
, 0xffffffff);
2777 I915_WRITE(IER
, 0x0);
2781 static int i965_irq_postinstall(struct drm_device
*dev
)
2783 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2786 unsigned long irqflags
;
2788 /* Unmask the interrupts that we always want on. */
2789 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
2790 I915_DISPLAY_PORT_INTERRUPT
|
2791 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2792 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2793 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2794 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2795 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2797 enable_mask
= ~dev_priv
->irq_mask
;
2798 enable_mask
&= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2799 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
2800 enable_mask
|= I915_USER_INTERRUPT
;
2803 enable_mask
|= I915_BSD_USER_INTERRUPT
;
2805 /* Interrupt setup is already guaranteed to be single-threaded, this is
2806 * just to make the assert_spin_locked check happy. */
2807 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2808 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
2809 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2812 * Enable some error detection, note the instruction error mask
2813 * bit is reserved, so we leave it masked.
2816 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
2817 GM45_ERROR_MEM_PRIV
|
2818 GM45_ERROR_CP_PRIV
|
2819 I915_ERROR_MEMORY_REFRESH
);
2821 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
2822 I915_ERROR_MEMORY_REFRESH
);
2824 I915_WRITE(EMR
, error_mask
);
2826 I915_WRITE(IMR
, dev_priv
->irq_mask
);
2827 I915_WRITE(IER
, enable_mask
);
2830 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2831 POSTING_READ(PORT_HOTPLUG_EN
);
2833 i915_enable_asle_pipestat(dev
);
2838 static void i915_hpd_irq_setup(struct drm_device
*dev
)
2840 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2841 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2842 struct intel_encoder
*intel_encoder
;
2845 assert_spin_locked(&dev_priv
->irq_lock
);
2847 if (I915_HAS_HOTPLUG(dev
)) {
2848 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
2849 hotplug_en
&= ~HOTPLUG_INT_EN_MASK
;
2850 /* Note HDMI and DP share hotplug bits */
2851 /* enable bits are the same for all generations */
2852 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2853 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2854 hotplug_en
|= hpd_mask_i915
[intel_encoder
->hpd_pin
];
2855 /* Programming the CRT detection parameters tends
2856 to generate a spurious hotplug event about three
2857 seconds later. So just do it once.
2860 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
2861 hotplug_en
&= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK
;
2862 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
2864 /* Ignore TV since it's buggy */
2865 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
2869 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
2871 struct drm_device
*dev
= (struct drm_device
*) arg
;
2872 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2874 u32 pipe_stats
[I915_MAX_PIPES
];
2875 unsigned long irqflags
;
2877 int ret
= IRQ_NONE
, pipe
;
2879 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2880 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2882 atomic_inc(&dev_priv
->irq_received
);
2884 iir
= I915_READ(IIR
);
2887 bool blc_event
= false;
2889 irq_received
= (iir
& ~flip_mask
) != 0;
2891 /* Can't rely on pipestat interrupt bit in iir as it might
2892 * have been cleared after the pipestat interrupt was received.
2893 * It doesn't set the bit in iir again, but it still produces
2894 * interrupts (for non-MSI).
2896 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2897 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2898 i915_handle_error(dev
, false);
2900 for_each_pipe(pipe
) {
2901 int reg
= PIPESTAT(pipe
);
2902 pipe_stats
[pipe
] = I915_READ(reg
);
2905 * Clear the PIPE*STAT regs before the IIR
2907 if (pipe_stats
[pipe
] & 0x8000ffff) {
2908 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2909 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2911 I915_WRITE(reg
, pipe_stats
[pipe
]);
2915 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2922 /* Consume port. Then clear IIR or we'll miss events */
2923 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
2924 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
2925 u32 hotplug_trigger
= hotplug_status
& (IS_G4X(dev
) ?
2926 HOTPLUG_INT_STATUS_G4X
:
2927 HOTPLUG_INT_STATUS_I915
);
2929 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2932 intel_hpd_irq_handler(dev
, hotplug_trigger
,
2933 IS_G4X(dev
) ? hpd_status_gen4
: hpd_status_i915
);
2935 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
2936 I915_READ(PORT_HOTPLUG_STAT
);
2939 I915_WRITE(IIR
, iir
& ~flip_mask
);
2940 new_iir
= I915_READ(IIR
); /* Flush posted writes */
2942 if (iir
& I915_USER_INTERRUPT
)
2943 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2944 if (iir
& I915_BSD_USER_INTERRUPT
)
2945 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
2947 for_each_pipe(pipe
) {
2948 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
2949 i915_handle_vblank(dev
, pipe
, pipe
, iir
))
2950 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
2952 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
2957 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
2958 intel_opregion_asle_intr(dev
);
2960 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
2961 gmbus_irq_handler(dev
);
2963 /* With MSI, interrupts are only generated when iir
2964 * transitions from zero to nonzero. If another bit got
2965 * set while we were handling the existing iir bits, then
2966 * we would never get another interrupt.
2968 * This is fine on non-MSI as well, as if we hit this path
2969 * we avoid exiting the interrupt handler only to generate
2972 * Note that for MSI this could cause a stray interrupt report
2973 * if an interrupt landed in the time between writing IIR and
2974 * the posting read. This should be rare enough to never
2975 * trigger the 99% of 100,000 interrupts test for disabling
2981 i915_update_dri1_breadcrumb(dev
);
2986 static void i965_irq_uninstall(struct drm_device
* dev
)
2988 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2994 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2996 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2997 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2999 I915_WRITE(HWSTAM
, 0xffffffff);
3001 I915_WRITE(PIPESTAT(pipe
), 0);
3002 I915_WRITE(IMR
, 0xffffffff);
3003 I915_WRITE(IER
, 0x0);
3006 I915_WRITE(PIPESTAT(pipe
),
3007 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
3008 I915_WRITE(IIR
, I915_READ(IIR
));
3011 static void i915_reenable_hotplug_timer_func(unsigned long data
)
3013 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*)data
;
3014 struct drm_device
*dev
= dev_priv
->dev
;
3015 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3016 unsigned long irqflags
;
3019 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3020 for (i
= (HPD_NONE
+ 1); i
< HPD_NUM_PINS
; i
++) {
3021 struct drm_connector
*connector
;
3023 if (dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_DISABLED
)
3026 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3028 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3029 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3031 if (intel_connector
->encoder
->hpd_pin
== i
) {
3032 if (connector
->polled
!= intel_connector
->polled
)
3033 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3034 drm_get_connector_name(connector
));
3035 connector
->polled
= intel_connector
->polled
;
3036 if (!connector
->polled
)
3037 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3041 if (dev_priv
->display
.hpd_irq_setup
)
3042 dev_priv
->display
.hpd_irq_setup(dev
);
3043 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3046 void intel_irq_init(struct drm_device
*dev
)
3048 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3050 INIT_WORK(&dev_priv
->hotplug_work
, i915_hotplug_work_func
);
3051 INIT_WORK(&dev_priv
->gpu_error
.work
, i915_error_work_func
);
3052 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
3053 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
3055 setup_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
3056 i915_hangcheck_elapsed
,
3057 (unsigned long) dev
);
3058 setup_timer(&dev_priv
->hotplug_reenable_timer
, i915_reenable_hotplug_timer_func
,
3059 (unsigned long) dev_priv
);
3061 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
, PM_QOS_DEFAULT_VALUE
);
3063 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
3064 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
3065 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
3066 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
3067 dev
->driver
->get_vblank_counter
= gm45_get_vblank_counter
;
3070 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3071 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
3073 dev
->driver
->get_vblank_timestamp
= NULL
;
3074 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
3076 if (IS_VALLEYVIEW(dev
)) {
3077 dev
->driver
->irq_handler
= valleyview_irq_handler
;
3078 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
3079 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
3080 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
3081 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
3082 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
3083 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3084 } else if (HAS_PCH_SPLIT(dev
)) {
3085 dev
->driver
->irq_handler
= ironlake_irq_handler
;
3086 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
3087 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
3088 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
3089 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
3090 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
3091 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
3093 if (INTEL_INFO(dev
)->gen
== 2) {
3094 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
3095 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
3096 dev
->driver
->irq_handler
= i8xx_irq_handler
;
3097 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
3098 } else if (INTEL_INFO(dev
)->gen
== 3) {
3099 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
3100 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
3101 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
3102 dev
->driver
->irq_handler
= i915_irq_handler
;
3103 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3105 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
3106 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
3107 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
3108 dev
->driver
->irq_handler
= i965_irq_handler
;
3109 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3111 dev
->driver
->enable_vblank
= i915_enable_vblank
;
3112 dev
->driver
->disable_vblank
= i915_disable_vblank
;
3116 void intel_hpd_init(struct drm_device
*dev
)
3118 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3119 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3120 struct drm_connector
*connector
;
3121 unsigned long irqflags
;
3124 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
3125 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
3126 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3128 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3129 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3130 connector
->polled
= intel_connector
->polled
;
3131 if (!connector
->polled
&& I915_HAS_HOTPLUG(dev
) && intel_connector
->encoder
->hpd_pin
> HPD_NONE
)
3132 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3135 /* Interrupt setup is already guaranteed to be single-threaded, this is
3136 * just to make the assert_spin_locked checks happy. */
3137 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3138 if (dev_priv
->display
.hpd_irq_setup
)
3139 dev_priv
->display
.hpd_irq_setup(dev
);
3140 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);