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drm/i915: Recognise non-VGA display devices
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #include <linux/sysrq.h>
30 #include <linux/slab.h>
31 #include "drmP.h"
32 #include "drm.h"
33 #include "i915_drm.h"
34 #include "i915_drv.h"
35 #include "i915_trace.h"
36 #include "intel_drv.h"
37
38 #define MAX_NOPID ((u32)~0)
39
40 /**
41 * Interrupts that are always left unmasked.
42 *
43 * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
44 * we leave them always unmasked in IMR and then control enabling them through
45 * PIPESTAT alone.
46 */
47 #define I915_INTERRUPT_ENABLE_FIX \
48 (I915_ASLE_INTERRUPT | \
49 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
50 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
51 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \
52 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \
53 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
54
55 /** Interrupts that we mask and unmask at runtime. */
56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
57
58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
59 PIPE_VBLANK_INTERRUPT_STATUS)
60
61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
62 PIPE_VBLANK_INTERRUPT_ENABLE)
63
64 #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
65 DRM_I915_VBLANK_PIPE_B)
66
67 /* For display hotplug interrupt */
68 static void
69 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
70 {
71 if ((dev_priv->irq_mask & mask) != 0) {
72 dev_priv->irq_mask &= ~mask;
73 I915_WRITE(DEIMR, dev_priv->irq_mask);
74 POSTING_READ(DEIMR);
75 }
76 }
77
78 static inline void
79 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
80 {
81 if ((dev_priv->irq_mask & mask) != mask) {
82 dev_priv->irq_mask |= mask;
83 I915_WRITE(DEIMR, dev_priv->irq_mask);
84 POSTING_READ(DEIMR);
85 }
86 }
87
88 static inline u32
89 i915_pipestat(int pipe)
90 {
91 if (pipe == 0)
92 return PIPEASTAT;
93 if (pipe == 1)
94 return PIPEBSTAT;
95 BUG();
96 }
97
98 void
99 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
100 {
101 if ((dev_priv->pipestat[pipe] & mask) != mask) {
102 u32 reg = i915_pipestat(pipe);
103
104 dev_priv->pipestat[pipe] |= mask;
105 /* Enable the interrupt, clear any pending status */
106 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
107 POSTING_READ(reg);
108 }
109 }
110
111 void
112 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
113 {
114 if ((dev_priv->pipestat[pipe] & mask) != 0) {
115 u32 reg = i915_pipestat(pipe);
116
117 dev_priv->pipestat[pipe] &= ~mask;
118 I915_WRITE(reg, dev_priv->pipestat[pipe]);
119 POSTING_READ(reg);
120 }
121 }
122
123 /**
124 * intel_enable_asle - enable ASLE interrupt for OpRegion
125 */
126 void intel_enable_asle(struct drm_device *dev)
127 {
128 drm_i915_private_t *dev_priv = dev->dev_private;
129 unsigned long irqflags;
130
131 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
132
133 if (HAS_PCH_SPLIT(dev))
134 ironlake_enable_display_irq(dev_priv, DE_GSE);
135 else {
136 i915_enable_pipestat(dev_priv, 1,
137 PIPE_LEGACY_BLC_EVENT_ENABLE);
138 if (INTEL_INFO(dev)->gen >= 4)
139 i915_enable_pipestat(dev_priv, 0,
140 PIPE_LEGACY_BLC_EVENT_ENABLE);
141 }
142
143 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
144 }
145
146 /**
147 * i915_pipe_enabled - check if a pipe is enabled
148 * @dev: DRM device
149 * @pipe: pipe to check
150 *
151 * Reading certain registers when the pipe is disabled can hang the chip.
152 * Use this routine to make sure the PLL is running and the pipe is active
153 * before reading such registers if unsure.
154 */
155 static int
156 i915_pipe_enabled(struct drm_device *dev, int pipe)
157 {
158 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
159 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
160 }
161
162 /* Called from drm generic code, passed a 'crtc', which
163 * we use as a pipe index
164 */
165 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
166 {
167 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
168 unsigned long high_frame;
169 unsigned long low_frame;
170 u32 high1, high2, low;
171
172 if (!i915_pipe_enabled(dev, pipe)) {
173 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
174 "pipe %d\n", pipe);
175 return 0;
176 }
177
178 high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
179 low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
180
181 /*
182 * High & low register fields aren't synchronized, so make sure
183 * we get a low value that's stable across two reads of the high
184 * register.
185 */
186 do {
187 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
188 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
189 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
190 } while (high1 != high2);
191
192 high1 >>= PIPE_FRAME_HIGH_SHIFT;
193 low >>= PIPE_FRAME_LOW_SHIFT;
194 return (high1 << 8) | low;
195 }
196
197 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
198 {
199 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
200 int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
201
202 if (!i915_pipe_enabled(dev, pipe)) {
203 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
204 "pipe %d\n", pipe);
205 return 0;
206 }
207
208 return I915_READ(reg);
209 }
210
211 int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
212 int *vpos, int *hpos)
213 {
214 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
215 u32 vbl = 0, position = 0;
216 int vbl_start, vbl_end, htotal, vtotal;
217 bool in_vbl = true;
218 int ret = 0;
219
220 if (!i915_pipe_enabled(dev, pipe)) {
221 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
222 "pipe %d\n", pipe);
223 return 0;
224 }
225
226 /* Get vtotal. */
227 vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
228
229 if (INTEL_INFO(dev)->gen >= 4) {
230 /* No obvious pixelcount register. Only query vertical
231 * scanout position from Display scan line register.
232 */
233 position = I915_READ(PIPEDSL(pipe));
234
235 /* Decode into vertical scanout position. Don't have
236 * horizontal scanout position.
237 */
238 *vpos = position & 0x1fff;
239 *hpos = 0;
240 } else {
241 /* Have access to pixelcount since start of frame.
242 * We can split this into vertical and horizontal
243 * scanout position.
244 */
245 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
246
247 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
248 *vpos = position / htotal;
249 *hpos = position - (*vpos * htotal);
250 }
251
252 /* Query vblank area. */
253 vbl = I915_READ(VBLANK(pipe));
254
255 /* Test position against vblank region. */
256 vbl_start = vbl & 0x1fff;
257 vbl_end = (vbl >> 16) & 0x1fff;
258
259 if ((*vpos < vbl_start) || (*vpos > vbl_end))
260 in_vbl = false;
261
262 /* Inside "upper part" of vblank area? Apply corrective offset: */
263 if (in_vbl && (*vpos >= vbl_start))
264 *vpos = *vpos - vtotal;
265
266 /* Readouts valid? */
267 if (vbl > 0)
268 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
269
270 /* In vblank? */
271 if (in_vbl)
272 ret |= DRM_SCANOUTPOS_INVBL;
273
274 return ret;
275 }
276
277 int i915_get_vblank_timestamp(struct drm_device *dev, int crtc,
278 int *max_error,
279 struct timeval *vblank_time,
280 unsigned flags)
281 {
282 struct drm_crtc *drmcrtc;
283
284 if (crtc < 0 || crtc >= dev->num_crtcs) {
285 DRM_ERROR("Invalid crtc %d\n", crtc);
286 return -EINVAL;
287 }
288
289 /* Get drm_crtc to timestamp: */
290 drmcrtc = intel_get_crtc_for_pipe(dev, crtc);
291
292 /* Helper routine in DRM core does all the work: */
293 return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
294 vblank_time, flags, drmcrtc);
295 }
296
297 /*
298 * Handle hotplug events outside the interrupt handler proper.
299 */
300 static void i915_hotplug_work_func(struct work_struct *work)
301 {
302 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
303 hotplug_work);
304 struct drm_device *dev = dev_priv->dev;
305 struct drm_mode_config *mode_config = &dev->mode_config;
306 struct intel_encoder *encoder;
307
308 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
309 if (encoder->hot_plug)
310 encoder->hot_plug(encoder);
311
312 /* Just fire off a uevent and let userspace tell us what to do */
313 drm_helper_hpd_irq_event(dev);
314 }
315
316 static void i915_handle_rps_change(struct drm_device *dev)
317 {
318 drm_i915_private_t *dev_priv = dev->dev_private;
319 u32 busy_up, busy_down, max_avg, min_avg;
320 u8 new_delay = dev_priv->cur_delay;
321
322 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
323 busy_up = I915_READ(RCPREVBSYTUPAVG);
324 busy_down = I915_READ(RCPREVBSYTDNAVG);
325 max_avg = I915_READ(RCBMAXAVG);
326 min_avg = I915_READ(RCBMINAVG);
327
328 /* Handle RCS change request from hw */
329 if (busy_up > max_avg) {
330 if (dev_priv->cur_delay != dev_priv->max_delay)
331 new_delay = dev_priv->cur_delay - 1;
332 if (new_delay < dev_priv->max_delay)
333 new_delay = dev_priv->max_delay;
334 } else if (busy_down < min_avg) {
335 if (dev_priv->cur_delay != dev_priv->min_delay)
336 new_delay = dev_priv->cur_delay + 1;
337 if (new_delay > dev_priv->min_delay)
338 new_delay = dev_priv->min_delay;
339 }
340
341 if (ironlake_set_drps(dev, new_delay))
342 dev_priv->cur_delay = new_delay;
343
344 return;
345 }
346
347 static void notify_ring(struct drm_device *dev,
348 struct intel_ring_buffer *ring)
349 {
350 struct drm_i915_private *dev_priv = dev->dev_private;
351 u32 seqno;
352
353 if (ring->obj == NULL)
354 return;
355
356 seqno = ring->get_seqno(ring);
357 trace_i915_gem_request_complete(dev, seqno);
358
359 ring->irq_seqno = seqno;
360 wake_up_all(&ring->irq_queue);
361
362 dev_priv->hangcheck_count = 0;
363 mod_timer(&dev_priv->hangcheck_timer,
364 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
365 }
366
367 static void gen6_pm_irq_handler(struct drm_device *dev)
368 {
369 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
370 u8 new_delay = dev_priv->cur_delay;
371 u32 pm_iir;
372
373 pm_iir = I915_READ(GEN6_PMIIR);
374 if (!pm_iir)
375 return;
376
377 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
378 if (dev_priv->cur_delay != dev_priv->max_delay)
379 new_delay = dev_priv->cur_delay + 1;
380 if (new_delay > dev_priv->max_delay)
381 new_delay = dev_priv->max_delay;
382 } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
383 if (dev_priv->cur_delay != dev_priv->min_delay)
384 new_delay = dev_priv->cur_delay - 1;
385 if (new_delay < dev_priv->min_delay) {
386 new_delay = dev_priv->min_delay;
387 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
388 I915_READ(GEN6_RP_INTERRUPT_LIMITS) |
389 ((new_delay << 16) & 0x3f0000));
390 } else {
391 /* Make sure we continue to get down interrupts
392 * until we hit the minimum frequency */
393 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
394 I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
395 }
396
397 }
398
399 gen6_set_rps(dev, new_delay);
400 dev_priv->cur_delay = new_delay;
401
402 I915_WRITE(GEN6_PMIIR, pm_iir);
403 }
404
405 static void pch_irq_handler(struct drm_device *dev)
406 {
407 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
408 u32 pch_iir;
409
410 pch_iir = I915_READ(SDEIIR);
411
412 if (pch_iir & SDE_AUDIO_POWER_MASK)
413 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
414 (pch_iir & SDE_AUDIO_POWER_MASK) >>
415 SDE_AUDIO_POWER_SHIFT);
416
417 if (pch_iir & SDE_GMBUS)
418 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
419
420 if (pch_iir & SDE_AUDIO_HDCP_MASK)
421 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
422
423 if (pch_iir & SDE_AUDIO_TRANS_MASK)
424 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
425
426 if (pch_iir & SDE_POISON)
427 DRM_ERROR("PCH poison interrupt\n");
428
429 if (pch_iir & SDE_FDI_MASK) {
430 u32 fdia, fdib;
431
432 fdia = I915_READ(FDI_RXA_IIR);
433 fdib = I915_READ(FDI_RXB_IIR);
434 DRM_DEBUG_DRIVER("PCH FDI RX interrupt; FDI RXA IIR: 0x%08x, FDI RXB IIR: 0x%08x\n", fdia, fdib);
435 }
436
437 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
438 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
439
440 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
441 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
442
443 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
444 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
445 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
446 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
447 }
448
449 static irqreturn_t ironlake_irq_handler(struct drm_device *dev)
450 {
451 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
452 int ret = IRQ_NONE;
453 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
454 u32 hotplug_mask;
455 struct drm_i915_master_private *master_priv;
456 u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
457
458 if (IS_GEN6(dev))
459 bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
460
461 /* disable master interrupt before clearing iir */
462 de_ier = I915_READ(DEIER);
463 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
464 POSTING_READ(DEIER);
465
466 de_iir = I915_READ(DEIIR);
467 gt_iir = I915_READ(GTIIR);
468 pch_iir = I915_READ(SDEIIR);
469 pm_iir = I915_READ(GEN6_PMIIR);
470
471 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
472 (!IS_GEN6(dev) || pm_iir == 0))
473 goto done;
474
475 if (HAS_PCH_CPT(dev))
476 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
477 else
478 hotplug_mask = SDE_HOTPLUG_MASK;
479
480 ret = IRQ_HANDLED;
481
482 if (dev->primary->master) {
483 master_priv = dev->primary->master->driver_priv;
484 if (master_priv->sarea_priv)
485 master_priv->sarea_priv->last_dispatch =
486 READ_BREADCRUMB(dev_priv);
487 }
488
489 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
490 notify_ring(dev, &dev_priv->ring[RCS]);
491 if (gt_iir & bsd_usr_interrupt)
492 notify_ring(dev, &dev_priv->ring[VCS]);
493 if (gt_iir & GT_BLT_USER_INTERRUPT)
494 notify_ring(dev, &dev_priv->ring[BCS]);
495
496 if (de_iir & DE_GSE)
497 intel_opregion_gse_intr(dev);
498
499 if (de_iir & DE_PLANEA_FLIP_DONE) {
500 intel_prepare_page_flip(dev, 0);
501 intel_finish_page_flip_plane(dev, 0);
502 }
503
504 if (de_iir & DE_PLANEB_FLIP_DONE) {
505 intel_prepare_page_flip(dev, 1);
506 intel_finish_page_flip_plane(dev, 1);
507 }
508
509 if (de_iir & DE_PIPEA_VBLANK)
510 drm_handle_vblank(dev, 0);
511
512 if (de_iir & DE_PIPEB_VBLANK)
513 drm_handle_vblank(dev, 1);
514
515 /* check event from PCH */
516 if (de_iir & DE_PCH_EVENT) {
517 if (pch_iir & hotplug_mask)
518 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
519 pch_irq_handler(dev);
520 }
521
522 if (de_iir & DE_PCU_EVENT) {
523 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
524 i915_handle_rps_change(dev);
525 }
526
527 if (IS_GEN6(dev))
528 gen6_pm_irq_handler(dev);
529
530 /* should clear PCH hotplug event before clear CPU irq */
531 I915_WRITE(SDEIIR, pch_iir);
532 I915_WRITE(GTIIR, gt_iir);
533 I915_WRITE(DEIIR, de_iir);
534
535 done:
536 I915_WRITE(DEIER, de_ier);
537 POSTING_READ(DEIER);
538
539 return ret;
540 }
541
542 /**
543 * i915_error_work_func - do process context error handling work
544 * @work: work struct
545 *
546 * Fire an error uevent so userspace can see that a hang or error
547 * was detected.
548 */
549 static void i915_error_work_func(struct work_struct *work)
550 {
551 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
552 error_work);
553 struct drm_device *dev = dev_priv->dev;
554 char *error_event[] = { "ERROR=1", NULL };
555 char *reset_event[] = { "RESET=1", NULL };
556 char *reset_done_event[] = { "ERROR=0", NULL };
557
558 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
559
560 if (atomic_read(&dev_priv->mm.wedged)) {
561 DRM_DEBUG_DRIVER("resetting chip\n");
562 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
563 if (!i915_reset(dev, GRDOM_RENDER)) {
564 atomic_set(&dev_priv->mm.wedged, 0);
565 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
566 }
567 complete_all(&dev_priv->error_completion);
568 }
569 }
570
571 #ifdef CONFIG_DEBUG_FS
572 static struct drm_i915_error_object *
573 i915_error_object_create(struct drm_i915_private *dev_priv,
574 struct drm_i915_gem_object *src)
575 {
576 struct drm_i915_error_object *dst;
577 int page, page_count;
578 u32 reloc_offset;
579
580 if (src == NULL || src->pages == NULL)
581 return NULL;
582
583 page_count = src->base.size / PAGE_SIZE;
584
585 dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
586 if (dst == NULL)
587 return NULL;
588
589 reloc_offset = src->gtt_offset;
590 for (page = 0; page < page_count; page++) {
591 unsigned long flags;
592 void __iomem *s;
593 void *d;
594
595 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
596 if (d == NULL)
597 goto unwind;
598
599 local_irq_save(flags);
600 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
601 reloc_offset);
602 memcpy_fromio(d, s, PAGE_SIZE);
603 io_mapping_unmap_atomic(s);
604 local_irq_restore(flags);
605
606 dst->pages[page] = d;
607
608 reloc_offset += PAGE_SIZE;
609 }
610 dst->page_count = page_count;
611 dst->gtt_offset = src->gtt_offset;
612
613 return dst;
614
615 unwind:
616 while (page--)
617 kfree(dst->pages[page]);
618 kfree(dst);
619 return NULL;
620 }
621
622 static void
623 i915_error_object_free(struct drm_i915_error_object *obj)
624 {
625 int page;
626
627 if (obj == NULL)
628 return;
629
630 for (page = 0; page < obj->page_count; page++)
631 kfree(obj->pages[page]);
632
633 kfree(obj);
634 }
635
636 static void
637 i915_error_state_free(struct drm_device *dev,
638 struct drm_i915_error_state *error)
639 {
640 i915_error_object_free(error->batchbuffer[0]);
641 i915_error_object_free(error->batchbuffer[1]);
642 i915_error_object_free(error->ringbuffer);
643 kfree(error->active_bo);
644 kfree(error->overlay);
645 kfree(error);
646 }
647
648 static u32 capture_bo_list(struct drm_i915_error_buffer *err,
649 int count,
650 struct list_head *head)
651 {
652 struct drm_i915_gem_object *obj;
653 int i = 0;
654
655 list_for_each_entry(obj, head, mm_list) {
656 err->size = obj->base.size;
657 err->name = obj->base.name;
658 err->seqno = obj->last_rendering_seqno;
659 err->gtt_offset = obj->gtt_offset;
660 err->read_domains = obj->base.read_domains;
661 err->write_domain = obj->base.write_domain;
662 err->fence_reg = obj->fence_reg;
663 err->pinned = 0;
664 if (obj->pin_count > 0)
665 err->pinned = 1;
666 if (obj->user_pin_count > 0)
667 err->pinned = -1;
668 err->tiling = obj->tiling_mode;
669 err->dirty = obj->dirty;
670 err->purgeable = obj->madv != I915_MADV_WILLNEED;
671 err->ring = obj->ring ? obj->ring->id : 0;
672 err->agp_type = obj->agp_type == AGP_USER_CACHED_MEMORY;
673
674 if (++i == count)
675 break;
676
677 err++;
678 }
679
680 return i;
681 }
682
683 static void i915_gem_record_fences(struct drm_device *dev,
684 struct drm_i915_error_state *error)
685 {
686 struct drm_i915_private *dev_priv = dev->dev_private;
687 int i;
688
689 /* Fences */
690 switch (INTEL_INFO(dev)->gen) {
691 case 6:
692 for (i = 0; i < 16; i++)
693 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
694 break;
695 case 5:
696 case 4:
697 for (i = 0; i < 16; i++)
698 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
699 break;
700 case 3:
701 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
702 for (i = 0; i < 8; i++)
703 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
704 case 2:
705 for (i = 0; i < 8; i++)
706 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
707 break;
708
709 }
710 }
711
712 static struct drm_i915_error_object *
713 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
714 struct intel_ring_buffer *ring)
715 {
716 struct drm_i915_gem_object *obj;
717 u32 seqno;
718
719 if (!ring->get_seqno)
720 return NULL;
721
722 seqno = ring->get_seqno(ring);
723 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
724 if (obj->ring != ring)
725 continue;
726
727 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
728 continue;
729
730 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
731 continue;
732
733 /* We need to copy these to an anonymous buffer as the simplest
734 * method to avoid being overwritten by userspace.
735 */
736 return i915_error_object_create(dev_priv, obj);
737 }
738
739 return NULL;
740 }
741
742 /**
743 * i915_capture_error_state - capture an error record for later analysis
744 * @dev: drm device
745 *
746 * Should be called when an error is detected (either a hang or an error
747 * interrupt) to capture error state from the time of the error. Fills
748 * out a structure which becomes available in debugfs for user level tools
749 * to pick up.
750 */
751 static void i915_capture_error_state(struct drm_device *dev)
752 {
753 struct drm_i915_private *dev_priv = dev->dev_private;
754 struct drm_i915_gem_object *obj;
755 struct drm_i915_error_state *error;
756 unsigned long flags;
757 int i;
758
759 spin_lock_irqsave(&dev_priv->error_lock, flags);
760 error = dev_priv->first_error;
761 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
762 if (error)
763 return;
764
765 error = kmalloc(sizeof(*error), GFP_ATOMIC);
766 if (!error) {
767 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
768 return;
769 }
770
771 DRM_DEBUG_DRIVER("generating error event\n");
772
773 error->seqno = dev_priv->ring[RCS].get_seqno(&dev_priv->ring[RCS]);
774 error->eir = I915_READ(EIR);
775 error->pgtbl_er = I915_READ(PGTBL_ER);
776 error->pipeastat = I915_READ(PIPEASTAT);
777 error->pipebstat = I915_READ(PIPEBSTAT);
778 error->instpm = I915_READ(INSTPM);
779 error->error = 0;
780 if (INTEL_INFO(dev)->gen >= 6) {
781 error->error = I915_READ(ERROR_GEN6);
782
783 error->bcs_acthd = I915_READ(BCS_ACTHD);
784 error->bcs_ipehr = I915_READ(BCS_IPEHR);
785 error->bcs_ipeir = I915_READ(BCS_IPEIR);
786 error->bcs_instdone = I915_READ(BCS_INSTDONE);
787 error->bcs_seqno = 0;
788 if (dev_priv->ring[BCS].get_seqno)
789 error->bcs_seqno = dev_priv->ring[BCS].get_seqno(&dev_priv->ring[BCS]);
790
791 error->vcs_acthd = I915_READ(VCS_ACTHD);
792 error->vcs_ipehr = I915_READ(VCS_IPEHR);
793 error->vcs_ipeir = I915_READ(VCS_IPEIR);
794 error->vcs_instdone = I915_READ(VCS_INSTDONE);
795 error->vcs_seqno = 0;
796 if (dev_priv->ring[VCS].get_seqno)
797 error->vcs_seqno = dev_priv->ring[VCS].get_seqno(&dev_priv->ring[VCS]);
798 }
799 if (INTEL_INFO(dev)->gen >= 4) {
800 error->ipeir = I915_READ(IPEIR_I965);
801 error->ipehr = I915_READ(IPEHR_I965);
802 error->instdone = I915_READ(INSTDONE_I965);
803 error->instps = I915_READ(INSTPS);
804 error->instdone1 = I915_READ(INSTDONE1);
805 error->acthd = I915_READ(ACTHD_I965);
806 error->bbaddr = I915_READ64(BB_ADDR);
807 } else {
808 error->ipeir = I915_READ(IPEIR);
809 error->ipehr = I915_READ(IPEHR);
810 error->instdone = I915_READ(INSTDONE);
811 error->acthd = I915_READ(ACTHD);
812 error->bbaddr = 0;
813 }
814 i915_gem_record_fences(dev, error);
815
816 /* Record the active batchbuffers */
817 for (i = 0; i < I915_NUM_RINGS; i++)
818 error->batchbuffer[i] =
819 i915_error_first_batchbuffer(dev_priv,
820 &dev_priv->ring[i]);
821
822 /* Record the ringbuffer */
823 error->ringbuffer = i915_error_object_create(dev_priv,
824 dev_priv->ring[RCS].obj);
825
826 /* Record buffers on the active and pinned lists. */
827 error->active_bo = NULL;
828 error->pinned_bo = NULL;
829
830 i = 0;
831 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
832 i++;
833 error->active_bo_count = i;
834 list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
835 i++;
836 error->pinned_bo_count = i - error->active_bo_count;
837
838 if (i) {
839 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
840 GFP_ATOMIC);
841 if (error->active_bo)
842 error->pinned_bo =
843 error->active_bo + error->active_bo_count;
844 }
845
846 if (error->active_bo)
847 error->active_bo_count =
848 capture_bo_list(error->active_bo,
849 error->active_bo_count,
850 &dev_priv->mm.active_list);
851
852 if (error->pinned_bo)
853 error->pinned_bo_count =
854 capture_bo_list(error->pinned_bo,
855 error->pinned_bo_count,
856 &dev_priv->mm.pinned_list);
857
858 do_gettimeofday(&error->time);
859
860 error->overlay = intel_overlay_capture_error_state(dev);
861 error->display = intel_display_capture_error_state(dev);
862
863 spin_lock_irqsave(&dev_priv->error_lock, flags);
864 if (dev_priv->first_error == NULL) {
865 dev_priv->first_error = error;
866 error = NULL;
867 }
868 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
869
870 if (error)
871 i915_error_state_free(dev, error);
872 }
873
874 void i915_destroy_error_state(struct drm_device *dev)
875 {
876 struct drm_i915_private *dev_priv = dev->dev_private;
877 struct drm_i915_error_state *error;
878
879 spin_lock(&dev_priv->error_lock);
880 error = dev_priv->first_error;
881 dev_priv->first_error = NULL;
882 spin_unlock(&dev_priv->error_lock);
883
884 if (error)
885 i915_error_state_free(dev, error);
886 }
887 #else
888 #define i915_capture_error_state(x)
889 #endif
890
891 static void i915_report_and_clear_eir(struct drm_device *dev)
892 {
893 struct drm_i915_private *dev_priv = dev->dev_private;
894 u32 eir = I915_READ(EIR);
895
896 if (!eir)
897 return;
898
899 printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
900 eir);
901
902 if (IS_G4X(dev)) {
903 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
904 u32 ipeir = I915_READ(IPEIR_I965);
905
906 printk(KERN_ERR " IPEIR: 0x%08x\n",
907 I915_READ(IPEIR_I965));
908 printk(KERN_ERR " IPEHR: 0x%08x\n",
909 I915_READ(IPEHR_I965));
910 printk(KERN_ERR " INSTDONE: 0x%08x\n",
911 I915_READ(INSTDONE_I965));
912 printk(KERN_ERR " INSTPS: 0x%08x\n",
913 I915_READ(INSTPS));
914 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
915 I915_READ(INSTDONE1));
916 printk(KERN_ERR " ACTHD: 0x%08x\n",
917 I915_READ(ACTHD_I965));
918 I915_WRITE(IPEIR_I965, ipeir);
919 POSTING_READ(IPEIR_I965);
920 }
921 if (eir & GM45_ERROR_PAGE_TABLE) {
922 u32 pgtbl_err = I915_READ(PGTBL_ER);
923 printk(KERN_ERR "page table error\n");
924 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
925 pgtbl_err);
926 I915_WRITE(PGTBL_ER, pgtbl_err);
927 POSTING_READ(PGTBL_ER);
928 }
929 }
930
931 if (!IS_GEN2(dev)) {
932 if (eir & I915_ERROR_PAGE_TABLE) {
933 u32 pgtbl_err = I915_READ(PGTBL_ER);
934 printk(KERN_ERR "page table error\n");
935 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
936 pgtbl_err);
937 I915_WRITE(PGTBL_ER, pgtbl_err);
938 POSTING_READ(PGTBL_ER);
939 }
940 }
941
942 if (eir & I915_ERROR_MEMORY_REFRESH) {
943 u32 pipea_stats = I915_READ(PIPEASTAT);
944 u32 pipeb_stats = I915_READ(PIPEBSTAT);
945
946 printk(KERN_ERR "memory refresh error\n");
947 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
948 pipea_stats);
949 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
950 pipeb_stats);
951 /* pipestat has already been acked */
952 }
953 if (eir & I915_ERROR_INSTRUCTION) {
954 printk(KERN_ERR "instruction error\n");
955 printk(KERN_ERR " INSTPM: 0x%08x\n",
956 I915_READ(INSTPM));
957 if (INTEL_INFO(dev)->gen < 4) {
958 u32 ipeir = I915_READ(IPEIR);
959
960 printk(KERN_ERR " IPEIR: 0x%08x\n",
961 I915_READ(IPEIR));
962 printk(KERN_ERR " IPEHR: 0x%08x\n",
963 I915_READ(IPEHR));
964 printk(KERN_ERR " INSTDONE: 0x%08x\n",
965 I915_READ(INSTDONE));
966 printk(KERN_ERR " ACTHD: 0x%08x\n",
967 I915_READ(ACTHD));
968 I915_WRITE(IPEIR, ipeir);
969 POSTING_READ(IPEIR);
970 } else {
971 u32 ipeir = I915_READ(IPEIR_I965);
972
973 printk(KERN_ERR " IPEIR: 0x%08x\n",
974 I915_READ(IPEIR_I965));
975 printk(KERN_ERR " IPEHR: 0x%08x\n",
976 I915_READ(IPEHR_I965));
977 printk(KERN_ERR " INSTDONE: 0x%08x\n",
978 I915_READ(INSTDONE_I965));
979 printk(KERN_ERR " INSTPS: 0x%08x\n",
980 I915_READ(INSTPS));
981 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
982 I915_READ(INSTDONE1));
983 printk(KERN_ERR " ACTHD: 0x%08x\n",
984 I915_READ(ACTHD_I965));
985 I915_WRITE(IPEIR_I965, ipeir);
986 POSTING_READ(IPEIR_I965);
987 }
988 }
989
990 I915_WRITE(EIR, eir);
991 POSTING_READ(EIR);
992 eir = I915_READ(EIR);
993 if (eir) {
994 /*
995 * some errors might have become stuck,
996 * mask them.
997 */
998 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
999 I915_WRITE(EMR, I915_READ(EMR) | eir);
1000 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1001 }
1002 }
1003
1004 /**
1005 * i915_handle_error - handle an error interrupt
1006 * @dev: drm device
1007 *
1008 * Do some basic checking of regsiter state at error interrupt time and
1009 * dump it to the syslog. Also call i915_capture_error_state() to make
1010 * sure we get a record and make it available in debugfs. Fire a uevent
1011 * so userspace knows something bad happened (should trigger collection
1012 * of a ring dump etc.).
1013 */
1014 void i915_handle_error(struct drm_device *dev, bool wedged)
1015 {
1016 struct drm_i915_private *dev_priv = dev->dev_private;
1017
1018 i915_capture_error_state(dev);
1019 i915_report_and_clear_eir(dev);
1020
1021 if (wedged) {
1022 INIT_COMPLETION(dev_priv->error_completion);
1023 atomic_set(&dev_priv->mm.wedged, 1);
1024
1025 /*
1026 * Wakeup waiting processes so they don't hang
1027 */
1028 wake_up_all(&dev_priv->ring[RCS].irq_queue);
1029 if (HAS_BSD(dev))
1030 wake_up_all(&dev_priv->ring[VCS].irq_queue);
1031 if (HAS_BLT(dev))
1032 wake_up_all(&dev_priv->ring[BCS].irq_queue);
1033 }
1034
1035 queue_work(dev_priv->wq, &dev_priv->error_work);
1036 }
1037
1038 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1039 {
1040 drm_i915_private_t *dev_priv = dev->dev_private;
1041 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1042 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1043 struct drm_i915_gem_object *obj;
1044 struct intel_unpin_work *work;
1045 unsigned long flags;
1046 bool stall_detected;
1047
1048 /* Ignore early vblank irqs */
1049 if (intel_crtc == NULL)
1050 return;
1051
1052 spin_lock_irqsave(&dev->event_lock, flags);
1053 work = intel_crtc->unpin_work;
1054
1055 if (work == NULL || work->pending || !work->enable_stall_check) {
1056 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1057 spin_unlock_irqrestore(&dev->event_lock, flags);
1058 return;
1059 }
1060
1061 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1062 obj = work->pending_flip_obj;
1063 if (INTEL_INFO(dev)->gen >= 4) {
1064 int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF;
1065 stall_detected = I915_READ(dspsurf) == obj->gtt_offset;
1066 } else {
1067 int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR;
1068 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1069 crtc->y * crtc->fb->pitch +
1070 crtc->x * crtc->fb->bits_per_pixel/8);
1071 }
1072
1073 spin_unlock_irqrestore(&dev->event_lock, flags);
1074
1075 if (stall_detected) {
1076 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1077 intel_prepare_page_flip(dev, intel_crtc->plane);
1078 }
1079 }
1080
1081 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
1082 {
1083 struct drm_device *dev = (struct drm_device *) arg;
1084 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1085 struct drm_i915_master_private *master_priv;
1086 u32 iir, new_iir;
1087 u32 pipea_stats, pipeb_stats;
1088 u32 vblank_status;
1089 int vblank = 0;
1090 unsigned long irqflags;
1091 int irq_received;
1092 int ret = IRQ_NONE;
1093
1094 atomic_inc(&dev_priv->irq_received);
1095
1096 if (HAS_PCH_SPLIT(dev))
1097 return ironlake_irq_handler(dev);
1098
1099 iir = I915_READ(IIR);
1100
1101 if (INTEL_INFO(dev)->gen >= 4)
1102 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
1103 else
1104 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
1105
1106 for (;;) {
1107 irq_received = iir != 0;
1108
1109 /* Can't rely on pipestat interrupt bit in iir as it might
1110 * have been cleared after the pipestat interrupt was received.
1111 * It doesn't set the bit in iir again, but it still produces
1112 * interrupts (for non-MSI).
1113 */
1114 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1115 pipea_stats = I915_READ(PIPEASTAT);
1116 pipeb_stats = I915_READ(PIPEBSTAT);
1117
1118 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
1119 i915_handle_error(dev, false);
1120
1121 /*
1122 * Clear the PIPE(A|B)STAT regs before the IIR
1123 */
1124 if (pipea_stats & 0x8000ffff) {
1125 if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS)
1126 DRM_DEBUG_DRIVER("pipe a underrun\n");
1127 I915_WRITE(PIPEASTAT, pipea_stats);
1128 irq_received = 1;
1129 }
1130
1131 if (pipeb_stats & 0x8000ffff) {
1132 if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS)
1133 DRM_DEBUG_DRIVER("pipe b underrun\n");
1134 I915_WRITE(PIPEBSTAT, pipeb_stats);
1135 irq_received = 1;
1136 }
1137 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1138
1139 if (!irq_received)
1140 break;
1141
1142 ret = IRQ_HANDLED;
1143
1144 /* Consume port. Then clear IIR or we'll miss events */
1145 if ((I915_HAS_HOTPLUG(dev)) &&
1146 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
1147 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1148
1149 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1150 hotplug_status);
1151 if (hotplug_status & dev_priv->hotplug_supported_mask)
1152 queue_work(dev_priv->wq,
1153 &dev_priv->hotplug_work);
1154
1155 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1156 I915_READ(PORT_HOTPLUG_STAT);
1157 }
1158
1159 I915_WRITE(IIR, iir);
1160 new_iir = I915_READ(IIR); /* Flush posted writes */
1161
1162 if (dev->primary->master) {
1163 master_priv = dev->primary->master->driver_priv;
1164 if (master_priv->sarea_priv)
1165 master_priv->sarea_priv->last_dispatch =
1166 READ_BREADCRUMB(dev_priv);
1167 }
1168
1169 if (iir & I915_USER_INTERRUPT)
1170 notify_ring(dev, &dev_priv->ring[RCS]);
1171 if (iir & I915_BSD_USER_INTERRUPT)
1172 notify_ring(dev, &dev_priv->ring[VCS]);
1173
1174 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
1175 intel_prepare_page_flip(dev, 0);
1176 if (dev_priv->flip_pending_is_done)
1177 intel_finish_page_flip_plane(dev, 0);
1178 }
1179
1180 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
1181 intel_prepare_page_flip(dev, 1);
1182 if (dev_priv->flip_pending_is_done)
1183 intel_finish_page_flip_plane(dev, 1);
1184 }
1185
1186 if (pipea_stats & vblank_status) {
1187 vblank++;
1188 drm_handle_vblank(dev, 0);
1189 if (!dev_priv->flip_pending_is_done) {
1190 i915_pageflip_stall_check(dev, 0);
1191 intel_finish_page_flip(dev, 0);
1192 }
1193 }
1194
1195 if (pipeb_stats & vblank_status) {
1196 vblank++;
1197 drm_handle_vblank(dev, 1);
1198 if (!dev_priv->flip_pending_is_done) {
1199 i915_pageflip_stall_check(dev, 1);
1200 intel_finish_page_flip(dev, 1);
1201 }
1202 }
1203
1204 if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1205 (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1206 (iir & I915_ASLE_INTERRUPT))
1207 intel_opregion_asle_intr(dev);
1208
1209 /* With MSI, interrupts are only generated when iir
1210 * transitions from zero to nonzero. If another bit got
1211 * set while we were handling the existing iir bits, then
1212 * we would never get another interrupt.
1213 *
1214 * This is fine on non-MSI as well, as if we hit this path
1215 * we avoid exiting the interrupt handler only to generate
1216 * another one.
1217 *
1218 * Note that for MSI this could cause a stray interrupt report
1219 * if an interrupt landed in the time between writing IIR and
1220 * the posting read. This should be rare enough to never
1221 * trigger the 99% of 100,000 interrupts test for disabling
1222 * stray interrupts.
1223 */
1224 iir = new_iir;
1225 }
1226
1227 return ret;
1228 }
1229
1230 static int i915_emit_irq(struct drm_device * dev)
1231 {
1232 drm_i915_private_t *dev_priv = dev->dev_private;
1233 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1234
1235 i915_kernel_lost_context(dev);
1236
1237 DRM_DEBUG_DRIVER("\n");
1238
1239 dev_priv->counter++;
1240 if (dev_priv->counter > 0x7FFFFFFFUL)
1241 dev_priv->counter = 1;
1242 if (master_priv->sarea_priv)
1243 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1244
1245 if (BEGIN_LP_RING(4) == 0) {
1246 OUT_RING(MI_STORE_DWORD_INDEX);
1247 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1248 OUT_RING(dev_priv->counter);
1249 OUT_RING(MI_USER_INTERRUPT);
1250 ADVANCE_LP_RING();
1251 }
1252
1253 return dev_priv->counter;
1254 }
1255
1256 void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
1257 {
1258 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1259 struct intel_ring_buffer *ring = LP_RING(dev_priv);
1260
1261 if (dev_priv->trace_irq_seqno == 0 &&
1262 ring->irq_get(ring))
1263 dev_priv->trace_irq_seqno = seqno;
1264 }
1265
1266 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1267 {
1268 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1269 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1270 int ret = 0;
1271 struct intel_ring_buffer *ring = LP_RING(dev_priv);
1272
1273 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1274 READ_BREADCRUMB(dev_priv));
1275
1276 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1277 if (master_priv->sarea_priv)
1278 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1279 return 0;
1280 }
1281
1282 if (master_priv->sarea_priv)
1283 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1284
1285 ret = -ENODEV;
1286 if (ring->irq_get(ring)) {
1287 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
1288 READ_BREADCRUMB(dev_priv) >= irq_nr);
1289 ring->irq_put(ring);
1290 }
1291
1292 if (ret == -EBUSY) {
1293 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1294 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1295 }
1296
1297 return ret;
1298 }
1299
1300 /* Needs the lock as it touches the ring.
1301 */
1302 int i915_irq_emit(struct drm_device *dev, void *data,
1303 struct drm_file *file_priv)
1304 {
1305 drm_i915_private_t *dev_priv = dev->dev_private;
1306 drm_i915_irq_emit_t *emit = data;
1307 int result;
1308
1309 if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
1310 DRM_ERROR("called with no initialization\n");
1311 return -EINVAL;
1312 }
1313
1314 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1315
1316 mutex_lock(&dev->struct_mutex);
1317 result = i915_emit_irq(dev);
1318 mutex_unlock(&dev->struct_mutex);
1319
1320 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1321 DRM_ERROR("copy_to_user\n");
1322 return -EFAULT;
1323 }
1324
1325 return 0;
1326 }
1327
1328 /* Doesn't need the hardware lock.
1329 */
1330 int i915_irq_wait(struct drm_device *dev, void *data,
1331 struct drm_file *file_priv)
1332 {
1333 drm_i915_private_t *dev_priv = dev->dev_private;
1334 drm_i915_irq_wait_t *irqwait = data;
1335
1336 if (!dev_priv) {
1337 DRM_ERROR("called with no initialization\n");
1338 return -EINVAL;
1339 }
1340
1341 return i915_wait_irq(dev, irqwait->irq_seq);
1342 }
1343
1344 /* Called from drm generic code, passed 'crtc' which
1345 * we use as a pipe index
1346 */
1347 int i915_enable_vblank(struct drm_device *dev, int pipe)
1348 {
1349 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1350 unsigned long irqflags;
1351
1352 if (!i915_pipe_enabled(dev, pipe))
1353 return -EINVAL;
1354
1355 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1356 if (HAS_PCH_SPLIT(dev))
1357 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1358 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1359 else if (INTEL_INFO(dev)->gen >= 4)
1360 i915_enable_pipestat(dev_priv, pipe,
1361 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1362 else
1363 i915_enable_pipestat(dev_priv, pipe,
1364 PIPE_VBLANK_INTERRUPT_ENABLE);
1365 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1366 return 0;
1367 }
1368
1369 /* Called from drm generic code, passed 'crtc' which
1370 * we use as a pipe index
1371 */
1372 void i915_disable_vblank(struct drm_device *dev, int pipe)
1373 {
1374 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1375 unsigned long irqflags;
1376
1377 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1378 if (HAS_PCH_SPLIT(dev))
1379 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1380 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1381 else
1382 i915_disable_pipestat(dev_priv, pipe,
1383 PIPE_VBLANK_INTERRUPT_ENABLE |
1384 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1385 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1386 }
1387
1388 void i915_enable_interrupt (struct drm_device *dev)
1389 {
1390 struct drm_i915_private *dev_priv = dev->dev_private;
1391
1392 if (!HAS_PCH_SPLIT(dev))
1393 intel_opregion_enable_asle(dev);
1394 dev_priv->irq_enabled = 1;
1395 }
1396
1397
1398 /* Set the vblank monitor pipe
1399 */
1400 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1401 struct drm_file *file_priv)
1402 {
1403 drm_i915_private_t *dev_priv = dev->dev_private;
1404
1405 if (!dev_priv) {
1406 DRM_ERROR("called with no initialization\n");
1407 return -EINVAL;
1408 }
1409
1410 return 0;
1411 }
1412
1413 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1414 struct drm_file *file_priv)
1415 {
1416 drm_i915_private_t *dev_priv = dev->dev_private;
1417 drm_i915_vblank_pipe_t *pipe = data;
1418
1419 if (!dev_priv) {
1420 DRM_ERROR("called with no initialization\n");
1421 return -EINVAL;
1422 }
1423
1424 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1425
1426 return 0;
1427 }
1428
1429 /**
1430 * Schedule buffer swap at given vertical blank.
1431 */
1432 int i915_vblank_swap(struct drm_device *dev, void *data,
1433 struct drm_file *file_priv)
1434 {
1435 /* The delayed swap mechanism was fundamentally racy, and has been
1436 * removed. The model was that the client requested a delayed flip/swap
1437 * from the kernel, then waited for vblank before continuing to perform
1438 * rendering. The problem was that the kernel might wake the client
1439 * up before it dispatched the vblank swap (since the lock has to be
1440 * held while touching the ringbuffer), in which case the client would
1441 * clear and start the next frame before the swap occurred, and
1442 * flicker would occur in addition to likely missing the vblank.
1443 *
1444 * In the absence of this ioctl, userland falls back to a correct path
1445 * of waiting for a vblank, then dispatching the swap on its own.
1446 * Context switching to userland and back is plenty fast enough for
1447 * meeting the requirements of vblank swapping.
1448 */
1449 return -EINVAL;
1450 }
1451
1452 static u32
1453 ring_last_seqno(struct intel_ring_buffer *ring)
1454 {
1455 return list_entry(ring->request_list.prev,
1456 struct drm_i915_gem_request, list)->seqno;
1457 }
1458
1459 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1460 {
1461 if (list_empty(&ring->request_list) ||
1462 i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1463 /* Issue a wake-up to catch stuck h/w. */
1464 if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) {
1465 DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n",
1466 ring->name,
1467 ring->waiting_seqno,
1468 ring->get_seqno(ring));
1469 wake_up_all(&ring->irq_queue);
1470 *err = true;
1471 }
1472 return true;
1473 }
1474 return false;
1475 }
1476
1477 static bool kick_ring(struct intel_ring_buffer *ring)
1478 {
1479 struct drm_device *dev = ring->dev;
1480 struct drm_i915_private *dev_priv = dev->dev_private;
1481 u32 tmp = I915_READ_CTL(ring);
1482 if (tmp & RING_WAIT) {
1483 DRM_ERROR("Kicking stuck wait on %s\n",
1484 ring->name);
1485 I915_WRITE_CTL(ring, tmp);
1486 return true;
1487 }
1488 if (IS_GEN6(dev) &&
1489 (tmp & RING_WAIT_SEMAPHORE)) {
1490 DRM_ERROR("Kicking stuck semaphore on %s\n",
1491 ring->name);
1492 I915_WRITE_CTL(ring, tmp);
1493 return true;
1494 }
1495 return false;
1496 }
1497
1498 /**
1499 * This is called when the chip hasn't reported back with completed
1500 * batchbuffers in a long time. The first time this is called we simply record
1501 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1502 * again, we assume the chip is wedged and try to fix it.
1503 */
1504 void i915_hangcheck_elapsed(unsigned long data)
1505 {
1506 struct drm_device *dev = (struct drm_device *)data;
1507 drm_i915_private_t *dev_priv = dev->dev_private;
1508 uint32_t acthd, instdone, instdone1;
1509 bool err = false;
1510
1511 /* If all work is done then ACTHD clearly hasn't advanced. */
1512 if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) &&
1513 i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) &&
1514 i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) {
1515 dev_priv->hangcheck_count = 0;
1516 if (err)
1517 goto repeat;
1518 return;
1519 }
1520
1521 if (INTEL_INFO(dev)->gen < 4) {
1522 acthd = I915_READ(ACTHD);
1523 instdone = I915_READ(INSTDONE);
1524 instdone1 = 0;
1525 } else {
1526 acthd = I915_READ(ACTHD_I965);
1527 instdone = I915_READ(INSTDONE_I965);
1528 instdone1 = I915_READ(INSTDONE1);
1529 }
1530
1531 if (dev_priv->last_acthd == acthd &&
1532 dev_priv->last_instdone == instdone &&
1533 dev_priv->last_instdone1 == instdone1) {
1534 if (dev_priv->hangcheck_count++ > 1) {
1535 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1536
1537 if (!IS_GEN2(dev)) {
1538 /* Is the chip hanging on a WAIT_FOR_EVENT?
1539 * If so we can simply poke the RB_WAIT bit
1540 * and break the hang. This should work on
1541 * all but the second generation chipsets.
1542 */
1543
1544 if (kick_ring(&dev_priv->ring[RCS]))
1545 goto repeat;
1546
1547 if (HAS_BSD(dev) &&
1548 kick_ring(&dev_priv->ring[VCS]))
1549 goto repeat;
1550
1551 if (HAS_BLT(dev) &&
1552 kick_ring(&dev_priv->ring[BCS]))
1553 goto repeat;
1554 }
1555
1556 i915_handle_error(dev, true);
1557 return;
1558 }
1559 } else {
1560 dev_priv->hangcheck_count = 0;
1561
1562 dev_priv->last_acthd = acthd;
1563 dev_priv->last_instdone = instdone;
1564 dev_priv->last_instdone1 = instdone1;
1565 }
1566
1567 repeat:
1568 /* Reset timer case chip hangs without another request being added */
1569 mod_timer(&dev_priv->hangcheck_timer,
1570 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1571 }
1572
1573 /* drm_dma.h hooks
1574 */
1575 static void ironlake_irq_preinstall(struct drm_device *dev)
1576 {
1577 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1578
1579 I915_WRITE(HWSTAM, 0xeffe);
1580
1581 /* XXX hotplug from PCH */
1582
1583 I915_WRITE(DEIMR, 0xffffffff);
1584 I915_WRITE(DEIER, 0x0);
1585 POSTING_READ(DEIER);
1586
1587 /* and GT */
1588 I915_WRITE(GTIMR, 0xffffffff);
1589 I915_WRITE(GTIER, 0x0);
1590 POSTING_READ(GTIER);
1591
1592 /* south display irq */
1593 I915_WRITE(SDEIMR, 0xffffffff);
1594 I915_WRITE(SDEIER, 0x0);
1595 POSTING_READ(SDEIER);
1596 }
1597
1598 static int ironlake_irq_postinstall(struct drm_device *dev)
1599 {
1600 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1601 /* enable kind of interrupts always enabled */
1602 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1603 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1604 u32 render_irqs;
1605 u32 hotplug_mask;
1606
1607 dev_priv->irq_mask = ~display_mask;
1608
1609 /* should always can generate irq */
1610 I915_WRITE(DEIIR, I915_READ(DEIIR));
1611 I915_WRITE(DEIMR, dev_priv->irq_mask);
1612 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
1613 POSTING_READ(DEIER);
1614
1615 dev_priv->gt_irq_mask = ~0;
1616
1617 I915_WRITE(GTIIR, I915_READ(GTIIR));
1618 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1619
1620 if (IS_GEN6(dev))
1621 render_irqs =
1622 GT_USER_INTERRUPT |
1623 GT_GEN6_BSD_USER_INTERRUPT |
1624 GT_BLT_USER_INTERRUPT;
1625 else
1626 render_irqs =
1627 GT_USER_INTERRUPT |
1628 GT_PIPE_NOTIFY |
1629 GT_BSD_USER_INTERRUPT;
1630 I915_WRITE(GTIER, render_irqs);
1631 POSTING_READ(GTIER);
1632
1633 if (HAS_PCH_CPT(dev)) {
1634 hotplug_mask = SDE_CRT_HOTPLUG_CPT | SDE_PORTB_HOTPLUG_CPT |
1635 SDE_PORTC_HOTPLUG_CPT | SDE_PORTD_HOTPLUG_CPT ;
1636 } else {
1637 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1638 SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1639 hotplug_mask |= SDE_AUX_MASK | SDE_FDI_MASK | SDE_TRANS_MASK;
1640 I915_WRITE(FDI_RXA_IMR, 0);
1641 I915_WRITE(FDI_RXB_IMR, 0);
1642 }
1643
1644 dev_priv->pch_irq_mask = ~hotplug_mask;
1645
1646 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1647 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1648 I915_WRITE(SDEIER, hotplug_mask);
1649 POSTING_READ(SDEIER);
1650
1651 if (IS_IRONLAKE_M(dev)) {
1652 /* Clear & enable PCU event interrupts */
1653 I915_WRITE(DEIIR, DE_PCU_EVENT);
1654 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1655 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1656 }
1657
1658 return 0;
1659 }
1660
1661 void i915_driver_irq_preinstall(struct drm_device * dev)
1662 {
1663 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1664
1665 atomic_set(&dev_priv->irq_received, 0);
1666
1667 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1668 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1669
1670 if (HAS_PCH_SPLIT(dev)) {
1671 ironlake_irq_preinstall(dev);
1672 return;
1673 }
1674
1675 if (I915_HAS_HOTPLUG(dev)) {
1676 I915_WRITE(PORT_HOTPLUG_EN, 0);
1677 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1678 }
1679
1680 I915_WRITE(HWSTAM, 0xeffe);
1681 I915_WRITE(PIPEASTAT, 0);
1682 I915_WRITE(PIPEBSTAT, 0);
1683 I915_WRITE(IMR, 0xffffffff);
1684 I915_WRITE(IER, 0x0);
1685 POSTING_READ(IER);
1686 }
1687
1688 /*
1689 * Must be called after intel_modeset_init or hotplug interrupts won't be
1690 * enabled correctly.
1691 */
1692 int i915_driver_irq_postinstall(struct drm_device *dev)
1693 {
1694 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1695 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1696 u32 error_mask;
1697
1698 DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
1699 if (HAS_BSD(dev))
1700 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
1701 if (HAS_BLT(dev))
1702 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
1703
1704 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1705
1706 if (HAS_PCH_SPLIT(dev))
1707 return ironlake_irq_postinstall(dev);
1708
1709 /* Unmask the interrupts that we always want on. */
1710 dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX;
1711
1712 dev_priv->pipestat[0] = 0;
1713 dev_priv->pipestat[1] = 0;
1714
1715 if (I915_HAS_HOTPLUG(dev)) {
1716 /* Enable in IER... */
1717 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1718 /* and unmask in IMR */
1719 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
1720 }
1721
1722 /*
1723 * Enable some error detection, note the instruction error mask
1724 * bit is reserved, so we leave it masked.
1725 */
1726 if (IS_G4X(dev)) {
1727 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1728 GM45_ERROR_MEM_PRIV |
1729 GM45_ERROR_CP_PRIV |
1730 I915_ERROR_MEMORY_REFRESH);
1731 } else {
1732 error_mask = ~(I915_ERROR_PAGE_TABLE |
1733 I915_ERROR_MEMORY_REFRESH);
1734 }
1735 I915_WRITE(EMR, error_mask);
1736
1737 I915_WRITE(IMR, dev_priv->irq_mask);
1738 I915_WRITE(IER, enable_mask);
1739 POSTING_READ(IER);
1740
1741 if (I915_HAS_HOTPLUG(dev)) {
1742 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1743
1744 /* Note HDMI and DP share bits */
1745 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1746 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1747 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1748 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1749 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1750 hotplug_en |= HDMID_HOTPLUG_INT_EN;
1751 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1752 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1753 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1754 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1755 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1756 hotplug_en |= CRT_HOTPLUG_INT_EN;
1757
1758 /* Programming the CRT detection parameters tends
1759 to generate a spurious hotplug event about three
1760 seconds later. So just do it once.
1761 */
1762 if (IS_G4X(dev))
1763 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
1764 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1765 }
1766
1767 /* Ignore TV since it's buggy */
1768
1769 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1770 }
1771
1772 intel_opregion_enable_asle(dev);
1773
1774 return 0;
1775 }
1776
1777 static void ironlake_irq_uninstall(struct drm_device *dev)
1778 {
1779 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1780 I915_WRITE(HWSTAM, 0xffffffff);
1781
1782 I915_WRITE(DEIMR, 0xffffffff);
1783 I915_WRITE(DEIER, 0x0);
1784 I915_WRITE(DEIIR, I915_READ(DEIIR));
1785
1786 I915_WRITE(GTIMR, 0xffffffff);
1787 I915_WRITE(GTIER, 0x0);
1788 I915_WRITE(GTIIR, I915_READ(GTIIR));
1789 }
1790
1791 void i915_driver_irq_uninstall(struct drm_device * dev)
1792 {
1793 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1794
1795 if (!dev_priv)
1796 return;
1797
1798 dev_priv->vblank_pipe = 0;
1799
1800 if (HAS_PCH_SPLIT(dev)) {
1801 ironlake_irq_uninstall(dev);
1802 return;
1803 }
1804
1805 if (I915_HAS_HOTPLUG(dev)) {
1806 I915_WRITE(PORT_HOTPLUG_EN, 0);
1807 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1808 }
1809
1810 I915_WRITE(HWSTAM, 0xffffffff);
1811 I915_WRITE(PIPEASTAT, 0);
1812 I915_WRITE(PIPEBSTAT, 0);
1813 I915_WRITE(IMR, 0xffffffff);
1814 I915_WRITE(IER, 0x0);
1815
1816 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1817 I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1818 I915_WRITE(IIR, I915_READ(IIR));
1819 }
Linux kernel - Deliverables
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