1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
34 #include <drm/i915_drm.h>
36 #include "i915_trace.h"
37 #include "intel_drv.h"
39 static const u32 hpd_ibx
[] = {
40 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
41 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
42 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
43 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
44 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
47 static const u32 hpd_cpt
[] = {
48 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
49 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG_CPT
,
50 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
51 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
52 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
55 static const u32 hpd_mask_i915
[] = {
56 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
57 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
58 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
59 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
60 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
61 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
64 static const u32 hpd_status_gen4
[] = {
65 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
66 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
67 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
68 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
69 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
70 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
73 static const u32 hpd_status_i915
[] = { /* i915 and valleyview are the same */
74 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
75 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
76 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
77 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
78 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
79 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
82 /* For display hotplug interrupt */
84 ironlake_enable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
86 assert_spin_locked(&dev_priv
->irq_lock
);
88 if (dev_priv
->pc8
.irqs_disabled
) {
89 WARN(1, "IRQs disabled\n");
90 dev_priv
->pc8
.regsave
.deimr
&= ~mask
;
94 if ((dev_priv
->irq_mask
& mask
) != 0) {
95 dev_priv
->irq_mask
&= ~mask
;
96 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
102 ironlake_disable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
104 assert_spin_locked(&dev_priv
->irq_lock
);
106 if (dev_priv
->pc8
.irqs_disabled
) {
107 WARN(1, "IRQs disabled\n");
108 dev_priv
->pc8
.regsave
.deimr
|= mask
;
112 if ((dev_priv
->irq_mask
& mask
) != mask
) {
113 dev_priv
->irq_mask
|= mask
;
114 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
120 * ilk_update_gt_irq - update GTIMR
121 * @dev_priv: driver private
122 * @interrupt_mask: mask of interrupt bits to update
123 * @enabled_irq_mask: mask of interrupt bits to enable
125 static void ilk_update_gt_irq(struct drm_i915_private
*dev_priv
,
126 uint32_t interrupt_mask
,
127 uint32_t enabled_irq_mask
)
129 assert_spin_locked(&dev_priv
->irq_lock
);
131 if (dev_priv
->pc8
.irqs_disabled
) {
132 WARN(1, "IRQs disabled\n");
133 dev_priv
->pc8
.regsave
.gtimr
&= ~interrupt_mask
;
134 dev_priv
->pc8
.regsave
.gtimr
|= (~enabled_irq_mask
&
139 dev_priv
->gt_irq_mask
&= ~interrupt_mask
;
140 dev_priv
->gt_irq_mask
|= (~enabled_irq_mask
& interrupt_mask
);
141 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
145 void ilk_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
147 ilk_update_gt_irq(dev_priv
, mask
, mask
);
150 void ilk_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
152 ilk_update_gt_irq(dev_priv
, mask
, 0);
156 * snb_update_pm_irq - update GEN6_PMIMR
157 * @dev_priv: driver private
158 * @interrupt_mask: mask of interrupt bits to update
159 * @enabled_irq_mask: mask of interrupt bits to enable
161 static void snb_update_pm_irq(struct drm_i915_private
*dev_priv
,
162 uint32_t interrupt_mask
,
163 uint32_t enabled_irq_mask
)
167 assert_spin_locked(&dev_priv
->irq_lock
);
169 if (dev_priv
->pc8
.irqs_disabled
) {
170 WARN(1, "IRQs disabled\n");
171 dev_priv
->pc8
.regsave
.gen6_pmimr
&= ~interrupt_mask
;
172 dev_priv
->pc8
.regsave
.gen6_pmimr
|= (~enabled_irq_mask
&
177 new_val
= dev_priv
->pm_irq_mask
;
178 new_val
&= ~interrupt_mask
;
179 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
181 if (new_val
!= dev_priv
->pm_irq_mask
) {
182 dev_priv
->pm_irq_mask
= new_val
;
183 I915_WRITE(GEN6_PMIMR
, dev_priv
->pm_irq_mask
);
184 POSTING_READ(GEN6_PMIMR
);
188 void snb_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
190 snb_update_pm_irq(dev_priv
, mask
, mask
);
193 void snb_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
195 snb_update_pm_irq(dev_priv
, mask
, 0);
198 static bool ivb_can_enable_err_int(struct drm_device
*dev
)
200 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
201 struct intel_crtc
*crtc
;
204 assert_spin_locked(&dev_priv
->irq_lock
);
206 for_each_pipe(pipe
) {
207 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
209 if (crtc
->cpu_fifo_underrun_disabled
)
216 static bool cpt_can_enable_serr_int(struct drm_device
*dev
)
218 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
220 struct intel_crtc
*crtc
;
222 assert_spin_locked(&dev_priv
->irq_lock
);
224 for_each_pipe(pipe
) {
225 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
227 if (crtc
->pch_fifo_underrun_disabled
)
234 static void ironlake_set_fifo_underrun_reporting(struct drm_device
*dev
,
235 enum pipe pipe
, bool enable
)
237 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
238 uint32_t bit
= (pipe
== PIPE_A
) ? DE_PIPEA_FIFO_UNDERRUN
:
239 DE_PIPEB_FIFO_UNDERRUN
;
242 ironlake_enable_display_irq(dev_priv
, bit
);
244 ironlake_disable_display_irq(dev_priv
, bit
);
247 static void ivybridge_set_fifo_underrun_reporting(struct drm_device
*dev
,
248 enum pipe pipe
, bool enable
)
250 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
252 I915_WRITE(GEN7_ERR_INT
, ERR_INT_FIFO_UNDERRUN(pipe
));
254 if (!ivb_can_enable_err_int(dev
))
257 ironlake_enable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
259 bool was_enabled
= !(I915_READ(DEIMR
) & DE_ERR_INT_IVB
);
261 /* Change the state _after_ we've read out the current one. */
262 ironlake_disable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
265 (I915_READ(GEN7_ERR_INT
) & ERR_INT_FIFO_UNDERRUN(pipe
))) {
266 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
273 * ibx_display_interrupt_update - update SDEIMR
274 * @dev_priv: driver private
275 * @interrupt_mask: mask of interrupt bits to update
276 * @enabled_irq_mask: mask of interrupt bits to enable
278 static void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
279 uint32_t interrupt_mask
,
280 uint32_t enabled_irq_mask
)
282 uint32_t sdeimr
= I915_READ(SDEIMR
);
283 sdeimr
&= ~interrupt_mask
;
284 sdeimr
|= (~enabled_irq_mask
& interrupt_mask
);
286 assert_spin_locked(&dev_priv
->irq_lock
);
288 if (dev_priv
->pc8
.irqs_disabled
&&
289 (interrupt_mask
& SDE_HOTPLUG_MASK_CPT
)) {
290 WARN(1, "IRQs disabled\n");
291 dev_priv
->pc8
.regsave
.sdeimr
&= ~interrupt_mask
;
292 dev_priv
->pc8
.regsave
.sdeimr
|= (~enabled_irq_mask
&
297 I915_WRITE(SDEIMR
, sdeimr
);
298 POSTING_READ(SDEIMR
);
300 #define ibx_enable_display_interrupt(dev_priv, bits) \
301 ibx_display_interrupt_update((dev_priv), (bits), (bits))
302 #define ibx_disable_display_interrupt(dev_priv, bits) \
303 ibx_display_interrupt_update((dev_priv), (bits), 0)
305 static void ibx_set_fifo_underrun_reporting(struct drm_device
*dev
,
306 enum transcoder pch_transcoder
,
309 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
310 uint32_t bit
= (pch_transcoder
== TRANSCODER_A
) ?
311 SDE_TRANSA_FIFO_UNDER
: SDE_TRANSB_FIFO_UNDER
;
314 ibx_enable_display_interrupt(dev_priv
, bit
);
316 ibx_disable_display_interrupt(dev_priv
, bit
);
319 static void cpt_set_fifo_underrun_reporting(struct drm_device
*dev
,
320 enum transcoder pch_transcoder
,
323 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
327 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
));
329 if (!cpt_can_enable_serr_int(dev
))
332 ibx_enable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
334 uint32_t tmp
= I915_READ(SERR_INT
);
335 bool was_enabled
= !(I915_READ(SDEIMR
) & SDE_ERROR_CPT
);
337 /* Change the state _after_ we've read out the current one. */
338 ibx_disable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
341 (tmp
& SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
))) {
342 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
343 transcoder_name(pch_transcoder
));
349 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
352 * @enable: true if we want to report FIFO underrun errors, false otherwise
354 * This function makes us disable or enable CPU fifo underruns for a specific
355 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
356 * reporting for one pipe may also disable all the other CPU error interruts for
357 * the other pipes, due to the fact that there's just one interrupt mask/enable
358 * bit for all the pipes.
360 * Returns the previous state of underrun reporting.
362 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device
*dev
,
363 enum pipe pipe
, bool enable
)
365 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
366 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
367 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
371 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
373 ret
= !intel_crtc
->cpu_fifo_underrun_disabled
;
378 intel_crtc
->cpu_fifo_underrun_disabled
= !enable
;
380 if (IS_GEN5(dev
) || IS_GEN6(dev
))
381 ironlake_set_fifo_underrun_reporting(dev
, pipe
, enable
);
382 else if (IS_GEN7(dev
))
383 ivybridge_set_fifo_underrun_reporting(dev
, pipe
, enable
);
386 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
391 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
393 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
394 * @enable: true if we want to report FIFO underrun errors, false otherwise
396 * This function makes us disable or enable PCH fifo underruns for a specific
397 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
398 * underrun reporting for one transcoder may also disable all the other PCH
399 * error interruts for the other transcoders, due to the fact that there's just
400 * one interrupt mask/enable bit for all the transcoders.
402 * Returns the previous state of underrun reporting.
404 bool intel_set_pch_fifo_underrun_reporting(struct drm_device
*dev
,
405 enum transcoder pch_transcoder
,
408 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
409 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pch_transcoder
];
410 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
415 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
416 * has only one pch transcoder A that all pipes can use. To avoid racy
417 * pch transcoder -> pipe lookups from interrupt code simply store the
418 * underrun statistics in crtc A. Since we never expose this anywhere
419 * nor use it outside of the fifo underrun code here using the "wrong"
420 * crtc on LPT won't cause issues.
423 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
425 ret
= !intel_crtc
->pch_fifo_underrun_disabled
;
430 intel_crtc
->pch_fifo_underrun_disabled
= !enable
;
432 if (HAS_PCH_IBX(dev
))
433 ibx_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
435 cpt_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
438 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
444 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
446 u32 reg
= PIPESTAT(pipe
);
447 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
449 assert_spin_locked(&dev_priv
->irq_lock
);
451 if ((pipestat
& mask
) == mask
)
454 /* Enable the interrupt, clear any pending status */
455 pipestat
|= mask
| (mask
>> 16);
456 I915_WRITE(reg
, pipestat
);
461 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
463 u32 reg
= PIPESTAT(pipe
);
464 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
466 assert_spin_locked(&dev_priv
->irq_lock
);
468 if ((pipestat
& mask
) == 0)
472 I915_WRITE(reg
, pipestat
);
477 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
479 static void i915_enable_asle_pipestat(struct drm_device
*dev
)
481 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
482 unsigned long irqflags
;
484 if (!dev_priv
->opregion
.asle
|| !IS_MOBILE(dev
))
487 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
489 i915_enable_pipestat(dev_priv
, 1, PIPE_LEGACY_BLC_EVENT_ENABLE
);
490 if (INTEL_INFO(dev
)->gen
>= 4)
491 i915_enable_pipestat(dev_priv
, 0, PIPE_LEGACY_BLC_EVENT_ENABLE
);
493 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
497 * i915_pipe_enabled - check if a pipe is enabled
499 * @pipe: pipe to check
501 * Reading certain registers when the pipe is disabled can hang the chip.
502 * Use this routine to make sure the PLL is running and the pipe is active
503 * before reading such registers if unsure.
506 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
508 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
510 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
511 /* Locking is horribly broken here, but whatever. */
512 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
513 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
515 return intel_crtc
->active
;
517 return I915_READ(PIPECONF(pipe
)) & PIPECONF_ENABLE
;
521 /* Called from drm generic code, passed a 'crtc', which
522 * we use as a pipe index
524 static u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
526 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
527 unsigned long high_frame
;
528 unsigned long low_frame
;
529 u32 high1
, high2
, low
;
531 if (!i915_pipe_enabled(dev
, pipe
)) {
532 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
533 "pipe %c\n", pipe_name(pipe
));
537 high_frame
= PIPEFRAME(pipe
);
538 low_frame
= PIPEFRAMEPIXEL(pipe
);
541 * High & low register fields aren't synchronized, so make sure
542 * we get a low value that's stable across two reads of the high
546 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
547 low
= I915_READ(low_frame
) & PIPE_FRAME_LOW_MASK
;
548 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
549 } while (high1
!= high2
);
551 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
552 low
>>= PIPE_FRAME_LOW_SHIFT
;
553 return (high1
<< 8) | low
;
556 static u32
gm45_get_vblank_counter(struct drm_device
*dev
, int pipe
)
558 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
559 int reg
= PIPE_FRMCOUNT_GM45(pipe
);
561 if (!i915_pipe_enabled(dev
, pipe
)) {
562 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
563 "pipe %c\n", pipe_name(pipe
));
567 return I915_READ(reg
);
570 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, int pipe
,
571 int *vpos
, int *hpos
)
573 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
574 u32 vbl
= 0, position
= 0;
575 int vbl_start
, vbl_end
, htotal
, vtotal
;
578 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
581 if (!i915_pipe_enabled(dev
, pipe
)) {
582 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
583 "pipe %c\n", pipe_name(pipe
));
588 vtotal
= 1 + ((I915_READ(VTOTAL(cpu_transcoder
)) >> 16) & 0x1fff);
590 if (INTEL_INFO(dev
)->gen
>= 4) {
591 /* No obvious pixelcount register. Only query vertical
592 * scanout position from Display scan line register.
594 position
= I915_READ(PIPEDSL(pipe
));
596 /* Decode into vertical scanout position. Don't have
597 * horizontal scanout position.
599 *vpos
= position
& 0x1fff;
602 /* Have access to pixelcount since start of frame.
603 * We can split this into vertical and horizontal
606 position
= (I915_READ(PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
608 htotal
= 1 + ((I915_READ(HTOTAL(cpu_transcoder
)) >> 16) & 0x1fff);
609 *vpos
= position
/ htotal
;
610 *hpos
= position
- (*vpos
* htotal
);
613 /* Query vblank area. */
614 vbl
= I915_READ(VBLANK(cpu_transcoder
));
616 /* Test position against vblank region. */
617 vbl_start
= vbl
& 0x1fff;
618 vbl_end
= (vbl
>> 16) & 0x1fff;
620 if ((*vpos
< vbl_start
) || (*vpos
> vbl_end
))
623 /* Inside "upper part" of vblank area? Apply corrective offset: */
624 if (in_vbl
&& (*vpos
>= vbl_start
))
625 *vpos
= *vpos
- vtotal
;
627 /* Readouts valid? */
629 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
633 ret
|= DRM_SCANOUTPOS_INVBL
;
638 static int i915_get_vblank_timestamp(struct drm_device
*dev
, int pipe
,
640 struct timeval
*vblank_time
,
643 struct drm_crtc
*crtc
;
645 if (pipe
< 0 || pipe
>= INTEL_INFO(dev
)->num_pipes
) {
646 DRM_ERROR("Invalid crtc %d\n", pipe
);
650 /* Get drm_crtc to timestamp: */
651 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
653 DRM_ERROR("Invalid crtc %d\n", pipe
);
657 if (!crtc
->enabled
) {
658 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
662 /* Helper routine in DRM core does all the work: */
663 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
668 static bool intel_hpd_irq_event(struct drm_device
*dev
,
669 struct drm_connector
*connector
)
671 enum drm_connector_status old_status
;
673 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
674 old_status
= connector
->status
;
676 connector
->status
= connector
->funcs
->detect(connector
, false);
677 if (old_status
== connector
->status
)
680 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
682 drm_get_connector_name(connector
),
683 drm_get_connector_status_name(old_status
),
684 drm_get_connector_status_name(connector
->status
));
690 * Handle hotplug events outside the interrupt handler proper.
692 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
694 static void i915_hotplug_work_func(struct work_struct
*work
)
696 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
698 struct drm_device
*dev
= dev_priv
->dev
;
699 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
700 struct intel_connector
*intel_connector
;
701 struct intel_encoder
*intel_encoder
;
702 struct drm_connector
*connector
;
703 unsigned long irqflags
;
704 bool hpd_disabled
= false;
705 bool changed
= false;
708 /* HPD irq before everything is fully set up. */
709 if (!dev_priv
->enable_hotplug_processing
)
712 mutex_lock(&mode_config
->mutex
);
713 DRM_DEBUG_KMS("running encoder hotplug functions\n");
715 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
717 hpd_event_bits
= dev_priv
->hpd_event_bits
;
718 dev_priv
->hpd_event_bits
= 0;
719 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
720 intel_connector
= to_intel_connector(connector
);
721 intel_encoder
= intel_connector
->encoder
;
722 if (intel_encoder
->hpd_pin
> HPD_NONE
&&
723 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_MARK_DISABLED
&&
724 connector
->polled
== DRM_CONNECTOR_POLL_HPD
) {
725 DRM_INFO("HPD interrupt storm detected on connector %s: "
726 "switching from hotplug detection to polling\n",
727 drm_get_connector_name(connector
));
728 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
= HPD_DISABLED
;
729 connector
->polled
= DRM_CONNECTOR_POLL_CONNECT
730 | DRM_CONNECTOR_POLL_DISCONNECT
;
733 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
734 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
735 drm_get_connector_name(connector
), intel_encoder
->hpd_pin
);
738 /* if there were no outputs to poll, poll was disabled,
739 * therefore make sure it's enabled when disabling HPD on
742 drm_kms_helper_poll_enable(dev
);
743 mod_timer(&dev_priv
->hotplug_reenable_timer
,
744 jiffies
+ msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY
));
747 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
749 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
750 intel_connector
= to_intel_connector(connector
);
751 intel_encoder
= intel_connector
->encoder
;
752 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
753 if (intel_encoder
->hot_plug
)
754 intel_encoder
->hot_plug(intel_encoder
);
755 if (intel_hpd_irq_event(dev
, connector
))
759 mutex_unlock(&mode_config
->mutex
);
762 drm_kms_helper_hotplug_event(dev
);
765 static void ironlake_rps_change_irq_handler(struct drm_device
*dev
)
767 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
768 u32 busy_up
, busy_down
, max_avg
, min_avg
;
771 spin_lock(&mchdev_lock
);
773 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
775 new_delay
= dev_priv
->ips
.cur_delay
;
777 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
778 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
779 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
780 max_avg
= I915_READ(RCBMAXAVG
);
781 min_avg
= I915_READ(RCBMINAVG
);
783 /* Handle RCS change request from hw */
784 if (busy_up
> max_avg
) {
785 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
786 new_delay
= dev_priv
->ips
.cur_delay
- 1;
787 if (new_delay
< dev_priv
->ips
.max_delay
)
788 new_delay
= dev_priv
->ips
.max_delay
;
789 } else if (busy_down
< min_avg
) {
790 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
791 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
792 if (new_delay
> dev_priv
->ips
.min_delay
)
793 new_delay
= dev_priv
->ips
.min_delay
;
796 if (ironlake_set_drps(dev
, new_delay
))
797 dev_priv
->ips
.cur_delay
= new_delay
;
799 spin_unlock(&mchdev_lock
);
804 static void notify_ring(struct drm_device
*dev
,
805 struct intel_ring_buffer
*ring
)
807 if (ring
->obj
== NULL
)
810 trace_i915_gem_request_complete(ring
);
812 wake_up_all(&ring
->irq_queue
);
813 i915_queue_hangcheck(dev
);
816 static void gen6_pm_rps_work(struct work_struct
*work
)
818 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
823 spin_lock_irq(&dev_priv
->irq_lock
);
824 pm_iir
= dev_priv
->rps
.pm_iir
;
825 dev_priv
->rps
.pm_iir
= 0;
826 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
827 snb_enable_pm_irq(dev_priv
, GEN6_PM_RPS_EVENTS
);
828 spin_unlock_irq(&dev_priv
->irq_lock
);
830 /* Make sure we didn't queue anything we're not going to process. */
831 WARN_ON(pm_iir
& ~GEN6_PM_RPS_EVENTS
);
833 if ((pm_iir
& GEN6_PM_RPS_EVENTS
) == 0)
836 mutex_lock(&dev_priv
->rps
.hw_lock
);
838 adj
= dev_priv
->rps
.last_adj
;
839 if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
) {
844 new_delay
= dev_priv
->rps
.cur_delay
+ adj
;
847 * For better performance, jump directly
848 * to RPe if we're below it.
850 if (new_delay
< dev_priv
->rps
.rpe_delay
)
851 new_delay
= dev_priv
->rps
.rpe_delay
;
852 } else if (pm_iir
& GEN6_PM_RP_DOWN_TIMEOUT
) {
853 if (dev_priv
->rps
.cur_delay
> dev_priv
->rps
.rpe_delay
)
854 new_delay
= dev_priv
->rps
.rpe_delay
;
856 new_delay
= dev_priv
->rps
.min_delay
;
858 } else if (pm_iir
& GEN6_PM_RP_DOWN_THRESHOLD
) {
863 new_delay
= dev_priv
->rps
.cur_delay
+ adj
;
864 } else { /* unknown event */
865 new_delay
= dev_priv
->rps
.cur_delay
;
868 /* sysfs frequency interfaces may have snuck in while servicing the
871 if (new_delay
< (int)dev_priv
->rps
.min_delay
)
872 new_delay
= dev_priv
->rps
.min_delay
;
873 if (new_delay
> (int)dev_priv
->rps
.max_delay
)
874 new_delay
= dev_priv
->rps
.max_delay
;
875 dev_priv
->rps
.last_adj
= new_delay
- dev_priv
->rps
.cur_delay
;
877 if (IS_VALLEYVIEW(dev_priv
->dev
))
878 valleyview_set_rps(dev_priv
->dev
, new_delay
);
880 gen6_set_rps(dev_priv
->dev
, new_delay
);
882 mutex_unlock(&dev_priv
->rps
.hw_lock
);
887 * ivybridge_parity_work - Workqueue called when a parity error interrupt
889 * @work: workqueue struct
891 * Doesn't actually do anything except notify userspace. As a consequence of
892 * this event, userspace should try to remap the bad rows since statistically
893 * it is likely the same row is more likely to go bad again.
895 static void ivybridge_parity_work(struct work_struct
*work
)
897 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
898 l3_parity
.error_work
);
899 u32 error_status
, row
, bank
, subbank
;
900 char *parity_event
[6];
905 /* We must turn off DOP level clock gating to access the L3 registers.
906 * In order to prevent a get/put style interface, acquire struct mutex
907 * any time we access those registers.
909 mutex_lock(&dev_priv
->dev
->struct_mutex
);
911 /* If we've screwed up tracking, just let the interrupt fire again */
912 if (WARN_ON(!dev_priv
->l3_parity
.which_slice
))
915 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
916 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
917 POSTING_READ(GEN7_MISCCPCTL
);
919 while ((slice
= ffs(dev_priv
->l3_parity
.which_slice
)) != 0) {
923 if (WARN_ON_ONCE(slice
>= NUM_L3_SLICES(dev_priv
->dev
)))
926 dev_priv
->l3_parity
.which_slice
&= ~(1<<slice
);
928 reg
= GEN7_L3CDERRST1
+ (slice
* 0x200);
930 error_status
= I915_READ(reg
);
931 row
= GEN7_PARITY_ERROR_ROW(error_status
);
932 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
933 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
935 I915_WRITE(reg
, GEN7_PARITY_ERROR_VALID
| GEN7_L3CDERRST1_ENABLE
);
938 parity_event
[0] = I915_L3_PARITY_UEVENT
"=1";
939 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
940 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
941 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
942 parity_event
[4] = kasprintf(GFP_KERNEL
, "SLICE=%d", slice
);
943 parity_event
[5] = NULL
;
945 kobject_uevent_env(&dev_priv
->dev
->primary
->kdev
.kobj
,
946 KOBJ_CHANGE
, parity_event
);
948 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
949 slice
, row
, bank
, subbank
);
951 kfree(parity_event
[4]);
952 kfree(parity_event
[3]);
953 kfree(parity_event
[2]);
954 kfree(parity_event
[1]);
957 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
960 WARN_ON(dev_priv
->l3_parity
.which_slice
);
961 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
962 ilk_enable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev_priv
->dev
));
963 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
965 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
968 static void ivybridge_parity_error_irq_handler(struct drm_device
*dev
, u32 iir
)
970 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
972 if (!HAS_L3_DPF(dev
))
975 spin_lock(&dev_priv
->irq_lock
);
976 ilk_disable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev
));
977 spin_unlock(&dev_priv
->irq_lock
);
979 iir
&= GT_PARITY_ERROR(dev
);
980 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1
)
981 dev_priv
->l3_parity
.which_slice
|= 1 << 1;
983 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT
)
984 dev_priv
->l3_parity
.which_slice
|= 1 << 0;
986 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
989 static void ilk_gt_irq_handler(struct drm_device
*dev
,
990 struct drm_i915_private
*dev_priv
,
994 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
995 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
996 if (gt_iir
& ILK_BSD_USER_INTERRUPT
)
997 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1000 static void snb_gt_irq_handler(struct drm_device
*dev
,
1001 struct drm_i915_private
*dev_priv
,
1006 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1007 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
1008 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
1009 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1010 if (gt_iir
& GT_BLT_USER_INTERRUPT
)
1011 notify_ring(dev
, &dev_priv
->ring
[BCS
]);
1013 if (gt_iir
& (GT_BLT_CS_ERROR_INTERRUPT
|
1014 GT_BSD_CS_ERROR_INTERRUPT
|
1015 GT_RENDER_CS_MASTER_ERROR_INTERRUPT
)) {
1016 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir
);
1017 i915_handle_error(dev
, false);
1020 if (gt_iir
& GT_PARITY_ERROR(dev
))
1021 ivybridge_parity_error_irq_handler(dev
, gt_iir
);
1024 #define HPD_STORM_DETECT_PERIOD 1000
1025 #define HPD_STORM_THRESHOLD 5
1027 static inline void intel_hpd_irq_handler(struct drm_device
*dev
,
1028 u32 hotplug_trigger
,
1031 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1033 bool storm_detected
= false;
1035 if (!hotplug_trigger
)
1038 spin_lock(&dev_priv
->irq_lock
);
1039 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
1041 WARN(((hpd
[i
] & hotplug_trigger
) &&
1042 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
),
1043 "Received HPD interrupt although disabled\n");
1045 if (!(hpd
[i
] & hotplug_trigger
) ||
1046 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
)
1049 dev_priv
->hpd_event_bits
|= (1 << i
);
1050 if (!time_in_range(jiffies
, dev_priv
->hpd_stats
[i
].hpd_last_jiffies
,
1051 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
1052 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD
))) {
1053 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
= jiffies
;
1054 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
1055 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i
);
1056 } else if (dev_priv
->hpd_stats
[i
].hpd_cnt
> HPD_STORM_THRESHOLD
) {
1057 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_MARK_DISABLED
;
1058 dev_priv
->hpd_event_bits
&= ~(1 << i
);
1059 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i
);
1060 storm_detected
= true;
1062 dev_priv
->hpd_stats
[i
].hpd_cnt
++;
1063 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i
,
1064 dev_priv
->hpd_stats
[i
].hpd_cnt
);
1069 dev_priv
->display
.hpd_irq_setup(dev
);
1070 spin_unlock(&dev_priv
->irq_lock
);
1073 * Our hotplug handler can grab modeset locks (by calling down into the
1074 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1075 * queue for otherwise the flush_work in the pageflip code will
1078 schedule_work(&dev_priv
->hotplug_work
);
1081 static void gmbus_irq_handler(struct drm_device
*dev
)
1083 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1085 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1088 static void dp_aux_irq_handler(struct drm_device
*dev
)
1090 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1092 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1095 /* The RPS events need forcewake, so we add them to a work queue and mask their
1096 * IMR bits until the work is done. Other interrupts can be processed without
1097 * the work queue. */
1098 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1100 if (pm_iir
& GEN6_PM_RPS_EVENTS
) {
1101 spin_lock(&dev_priv
->irq_lock
);
1102 dev_priv
->rps
.pm_iir
|= pm_iir
& GEN6_PM_RPS_EVENTS
;
1103 snb_disable_pm_irq(dev_priv
, pm_iir
& GEN6_PM_RPS_EVENTS
);
1104 spin_unlock(&dev_priv
->irq_lock
);
1106 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
1109 if (HAS_VEBOX(dev_priv
->dev
)) {
1110 if (pm_iir
& PM_VEBOX_USER_INTERRUPT
)
1111 notify_ring(dev_priv
->dev
, &dev_priv
->ring
[VECS
]);
1113 if (pm_iir
& PM_VEBOX_CS_ERROR_INTERRUPT
) {
1114 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir
);
1115 i915_handle_error(dev_priv
->dev
, false);
1120 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
1122 struct drm_device
*dev
= (struct drm_device
*) arg
;
1123 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1124 u32 iir
, gt_iir
, pm_iir
;
1125 irqreturn_t ret
= IRQ_NONE
;
1126 unsigned long irqflags
;
1128 u32 pipe_stats
[I915_MAX_PIPES
];
1130 atomic_inc(&dev_priv
->irq_received
);
1133 iir
= I915_READ(VLV_IIR
);
1134 gt_iir
= I915_READ(GTIIR
);
1135 pm_iir
= I915_READ(GEN6_PMIIR
);
1137 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
1142 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1144 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1145 for_each_pipe(pipe
) {
1146 int reg
= PIPESTAT(pipe
);
1147 pipe_stats
[pipe
] = I915_READ(reg
);
1150 * Clear the PIPE*STAT regs before the IIR
1152 if (pipe_stats
[pipe
] & 0x8000ffff) {
1153 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
1154 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1156 I915_WRITE(reg
, pipe_stats
[pipe
]);
1159 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1161 for_each_pipe(pipe
) {
1162 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
)
1163 drm_handle_vblank(dev
, pipe
);
1165 if (pipe_stats
[pipe
] & PLANE_FLIPDONE_INT_STATUS_VLV
) {
1166 intel_prepare_page_flip(dev
, pipe
);
1167 intel_finish_page_flip(dev
, pipe
);
1171 /* Consume port. Then clear IIR or we'll miss events */
1172 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
1173 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1174 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
1176 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1179 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
1181 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1182 I915_READ(PORT_HOTPLUG_STAT
);
1185 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1186 gmbus_irq_handler(dev
);
1189 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1191 I915_WRITE(GTIIR
, gt_iir
);
1192 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1193 I915_WRITE(VLV_IIR
, iir
);
1200 static void ibx_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1202 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1204 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK
;
1206 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_ibx
);
1208 if (pch_iir
& SDE_AUDIO_POWER_MASK
) {
1209 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK
) >>
1210 SDE_AUDIO_POWER_SHIFT
);
1211 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1215 if (pch_iir
& SDE_AUX_MASK
)
1216 dp_aux_irq_handler(dev
);
1218 if (pch_iir
& SDE_GMBUS
)
1219 gmbus_irq_handler(dev
);
1221 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
1222 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1224 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
1225 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1227 if (pch_iir
& SDE_POISON
)
1228 DRM_ERROR("PCH poison interrupt\n");
1230 if (pch_iir
& SDE_FDI_MASK
)
1232 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1234 I915_READ(FDI_RX_IIR(pipe
)));
1236 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
1237 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1239 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
1240 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1242 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
1243 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1245 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1247 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
1248 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1250 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1253 static void ivb_err_int_handler(struct drm_device
*dev
)
1255 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1256 u32 err_int
= I915_READ(GEN7_ERR_INT
);
1258 if (err_int
& ERR_INT_POISON
)
1259 DRM_ERROR("Poison interrupt\n");
1261 if (err_int
& ERR_INT_FIFO_UNDERRUN_A
)
1262 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_A
, false))
1263 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1265 if (err_int
& ERR_INT_FIFO_UNDERRUN_B
)
1266 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_B
, false))
1267 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1269 if (err_int
& ERR_INT_FIFO_UNDERRUN_C
)
1270 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_C
, false))
1271 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1273 I915_WRITE(GEN7_ERR_INT
, err_int
);
1276 static void cpt_serr_int_handler(struct drm_device
*dev
)
1278 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1279 u32 serr_int
= I915_READ(SERR_INT
);
1281 if (serr_int
& SERR_INT_POISON
)
1282 DRM_ERROR("PCH poison interrupt\n");
1284 if (serr_int
& SERR_INT_TRANS_A_FIFO_UNDERRUN
)
1285 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1287 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1289 if (serr_int
& SERR_INT_TRANS_B_FIFO_UNDERRUN
)
1290 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1292 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1294 if (serr_int
& SERR_INT_TRANS_C_FIFO_UNDERRUN
)
1295 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_C
,
1297 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1299 I915_WRITE(SERR_INT
, serr_int
);
1302 static void cpt_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1304 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1306 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_CPT
;
1308 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_cpt
);
1310 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) {
1311 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
1312 SDE_AUDIO_POWER_SHIFT_CPT
);
1313 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1317 if (pch_iir
& SDE_AUX_MASK_CPT
)
1318 dp_aux_irq_handler(dev
);
1320 if (pch_iir
& SDE_GMBUS_CPT
)
1321 gmbus_irq_handler(dev
);
1323 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
1324 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1326 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
1327 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1329 if (pch_iir
& SDE_FDI_MASK_CPT
)
1331 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1333 I915_READ(FDI_RX_IIR(pipe
)));
1335 if (pch_iir
& SDE_ERROR_CPT
)
1336 cpt_serr_int_handler(dev
);
1339 static void ilk_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
1341 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1343 if (de_iir
& DE_AUX_CHANNEL_A
)
1344 dp_aux_irq_handler(dev
);
1346 if (de_iir
& DE_GSE
)
1347 intel_opregion_asle_intr(dev
);
1349 if (de_iir
& DE_PIPEA_VBLANK
)
1350 drm_handle_vblank(dev
, 0);
1352 if (de_iir
& DE_PIPEB_VBLANK
)
1353 drm_handle_vblank(dev
, 1);
1355 if (de_iir
& DE_POISON
)
1356 DRM_ERROR("Poison interrupt\n");
1358 if (de_iir
& DE_PIPEA_FIFO_UNDERRUN
)
1359 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_A
, false))
1360 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1362 if (de_iir
& DE_PIPEB_FIFO_UNDERRUN
)
1363 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_B
, false))
1364 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1366 if (de_iir
& DE_PLANEA_FLIP_DONE
) {
1367 intel_prepare_page_flip(dev
, 0);
1368 intel_finish_page_flip_plane(dev
, 0);
1371 if (de_iir
& DE_PLANEB_FLIP_DONE
) {
1372 intel_prepare_page_flip(dev
, 1);
1373 intel_finish_page_flip_plane(dev
, 1);
1376 /* check event from PCH */
1377 if (de_iir
& DE_PCH_EVENT
) {
1378 u32 pch_iir
= I915_READ(SDEIIR
);
1380 if (HAS_PCH_CPT(dev
))
1381 cpt_irq_handler(dev
, pch_iir
);
1383 ibx_irq_handler(dev
, pch_iir
);
1385 /* should clear PCH hotplug event before clear CPU irq */
1386 I915_WRITE(SDEIIR
, pch_iir
);
1389 if (IS_GEN5(dev
) && de_iir
& DE_PCU_EVENT
)
1390 ironlake_rps_change_irq_handler(dev
);
1393 static void ivb_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
1395 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1398 if (de_iir
& DE_ERR_INT_IVB
)
1399 ivb_err_int_handler(dev
);
1401 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
1402 dp_aux_irq_handler(dev
);
1404 if (de_iir
& DE_GSE_IVB
)
1405 intel_opregion_asle_intr(dev
);
1407 for (i
= 0; i
< 3; i
++) {
1408 if (de_iir
& (DE_PIPEA_VBLANK_IVB
<< (5 * i
)))
1409 drm_handle_vblank(dev
, i
);
1410 if (de_iir
& (DE_PLANEA_FLIP_DONE_IVB
<< (5 * i
))) {
1411 intel_prepare_page_flip(dev
, i
);
1412 intel_finish_page_flip_plane(dev
, i
);
1416 /* check event from PCH */
1417 if (!HAS_PCH_NOP(dev
) && (de_iir
& DE_PCH_EVENT_IVB
)) {
1418 u32 pch_iir
= I915_READ(SDEIIR
);
1420 cpt_irq_handler(dev
, pch_iir
);
1422 /* clear PCH hotplug event before clear CPU irq */
1423 I915_WRITE(SDEIIR
, pch_iir
);
1427 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
1429 struct drm_device
*dev
= (struct drm_device
*) arg
;
1430 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1431 u32 de_iir
, gt_iir
, de_ier
, sde_ier
= 0;
1432 irqreturn_t ret
= IRQ_NONE
;
1434 atomic_inc(&dev_priv
->irq_received
);
1436 /* We get interrupts on unclaimed registers, so check for this before we
1437 * do any I915_{READ,WRITE}. */
1438 intel_uncore_check_errors(dev
);
1440 /* disable master interrupt before clearing iir */
1441 de_ier
= I915_READ(DEIER
);
1442 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
1443 POSTING_READ(DEIER
);
1445 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1446 * interrupts will will be stored on its back queue, and then we'll be
1447 * able to process them after we restore SDEIER (as soon as we restore
1448 * it, we'll get an interrupt if SDEIIR still has something to process
1449 * due to its back queue). */
1450 if (!HAS_PCH_NOP(dev
)) {
1451 sde_ier
= I915_READ(SDEIER
);
1452 I915_WRITE(SDEIER
, 0);
1453 POSTING_READ(SDEIER
);
1456 gt_iir
= I915_READ(GTIIR
);
1458 if (INTEL_INFO(dev
)->gen
>= 6)
1459 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1461 ilk_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1462 I915_WRITE(GTIIR
, gt_iir
);
1466 de_iir
= I915_READ(DEIIR
);
1468 if (INTEL_INFO(dev
)->gen
>= 7)
1469 ivb_display_irq_handler(dev
, de_iir
);
1471 ilk_display_irq_handler(dev
, de_iir
);
1472 I915_WRITE(DEIIR
, de_iir
);
1476 if (INTEL_INFO(dev
)->gen
>= 6) {
1477 u32 pm_iir
= I915_READ(GEN6_PMIIR
);
1479 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1480 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1485 I915_WRITE(DEIER
, de_ier
);
1486 POSTING_READ(DEIER
);
1487 if (!HAS_PCH_NOP(dev
)) {
1488 I915_WRITE(SDEIER
, sde_ier
);
1489 POSTING_READ(SDEIER
);
1495 static void i915_error_wake_up(struct drm_i915_private
*dev_priv
,
1496 bool reset_completed
)
1498 struct intel_ring_buffer
*ring
;
1502 * Notify all waiters for GPU completion events that reset state has
1503 * been changed, and that they need to restart their wait after
1504 * checking for potential errors (and bail out to drop locks if there is
1505 * a gpu reset pending so that i915_error_work_func can acquire them).
1508 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
1509 for_each_ring(ring
, dev_priv
, i
)
1510 wake_up_all(&ring
->irq_queue
);
1512 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
1513 wake_up_all(&dev_priv
->pending_flip_queue
);
1516 * Signal tasks blocked in i915_gem_wait_for_error that the pending
1517 * reset state is cleared.
1519 if (reset_completed
)
1520 wake_up_all(&dev_priv
->gpu_error
.reset_queue
);
1524 * i915_error_work_func - do process context error handling work
1525 * @work: work struct
1527 * Fire an error uevent so userspace can see that a hang or error
1530 static void i915_error_work_func(struct work_struct
*work
)
1532 struct i915_gpu_error
*error
= container_of(work
, struct i915_gpu_error
,
1534 drm_i915_private_t
*dev_priv
= container_of(error
, drm_i915_private_t
,
1536 struct drm_device
*dev
= dev_priv
->dev
;
1537 char *error_event
[] = { I915_ERROR_UEVENT
"=1", NULL
};
1538 char *reset_event
[] = { I915_RESET_UEVENT
"=1", NULL
};
1539 char *reset_done_event
[] = { I915_ERROR_UEVENT
"=0", NULL
};
1542 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
, error_event
);
1545 * Note that there's only one work item which does gpu resets, so we
1546 * need not worry about concurrent gpu resets potentially incrementing
1547 * error->reset_counter twice. We only need to take care of another
1548 * racing irq/hangcheck declaring the gpu dead for a second time. A
1549 * quick check for that is good enough: schedule_work ensures the
1550 * correct ordering between hang detection and this work item, and since
1551 * the reset in-progress bit is only ever set by code outside of this
1552 * work we don't need to worry about any other races.
1554 if (i915_reset_in_progress(error
) && !i915_terminally_wedged(error
)) {
1555 DRM_DEBUG_DRIVER("resetting chip\n");
1556 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
,
1560 * All state reset _must_ be completed before we update the
1561 * reset counter, for otherwise waiters might miss the reset
1562 * pending state and not properly drop locks, resulting in
1563 * deadlocks with the reset work.
1565 ret
= i915_reset(dev
);
1567 intel_display_handle_reset(dev
);
1571 * After all the gem state is reset, increment the reset
1572 * counter and wake up everyone waiting for the reset to
1575 * Since unlock operations are a one-sided barrier only,
1576 * we need to insert a barrier here to order any seqno
1578 * the counter increment.
1580 smp_mb__before_atomic_inc();
1581 atomic_inc(&dev_priv
->gpu_error
.reset_counter
);
1583 kobject_uevent_env(&dev
->primary
->kdev
.kobj
,
1584 KOBJ_CHANGE
, reset_done_event
);
1586 atomic_set(&error
->reset_counter
, I915_WEDGED
);
1590 * Note: The wake_up also serves as a memory barrier so that
1591 * waiters see the update value of the reset counter atomic_t.
1593 i915_error_wake_up(dev_priv
, true);
1597 static void i915_report_and_clear_eir(struct drm_device
*dev
)
1599 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1600 uint32_t instdone
[I915_NUM_INSTDONE_REG
];
1601 u32 eir
= I915_READ(EIR
);
1607 pr_err("render error detected, EIR: 0x%08x\n", eir
);
1609 i915_get_extra_instdone(dev
, instdone
);
1612 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
1613 u32 ipeir
= I915_READ(IPEIR_I965
);
1615 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1616 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1617 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
1618 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
1619 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1620 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1621 I915_WRITE(IPEIR_I965
, ipeir
);
1622 POSTING_READ(IPEIR_I965
);
1624 if (eir
& GM45_ERROR_PAGE_TABLE
) {
1625 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1626 pr_err("page table error\n");
1627 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1628 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1629 POSTING_READ(PGTBL_ER
);
1633 if (!IS_GEN2(dev
)) {
1634 if (eir
& I915_ERROR_PAGE_TABLE
) {
1635 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1636 pr_err("page table error\n");
1637 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1638 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1639 POSTING_READ(PGTBL_ER
);
1643 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
1644 pr_err("memory refresh error:\n");
1646 pr_err("pipe %c stat: 0x%08x\n",
1647 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
1648 /* pipestat has already been acked */
1650 if (eir
& I915_ERROR_INSTRUCTION
) {
1651 pr_err("instruction error\n");
1652 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
1653 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
1654 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
1655 if (INTEL_INFO(dev
)->gen
< 4) {
1656 u32 ipeir
= I915_READ(IPEIR
);
1658 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
1659 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
1660 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
1661 I915_WRITE(IPEIR
, ipeir
);
1662 POSTING_READ(IPEIR
);
1664 u32 ipeir
= I915_READ(IPEIR_I965
);
1666 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1667 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1668 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1669 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1670 I915_WRITE(IPEIR_I965
, ipeir
);
1671 POSTING_READ(IPEIR_I965
);
1675 I915_WRITE(EIR
, eir
);
1677 eir
= I915_READ(EIR
);
1680 * some errors might have become stuck,
1683 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
1684 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
1685 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
1690 * i915_handle_error - handle an error interrupt
1693 * Do some basic checking of regsiter state at error interrupt time and
1694 * dump it to the syslog. Also call i915_capture_error_state() to make
1695 * sure we get a record and make it available in debugfs. Fire a uevent
1696 * so userspace knows something bad happened (should trigger collection
1697 * of a ring dump etc.).
1699 void i915_handle_error(struct drm_device
*dev
, bool wedged
)
1701 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1703 i915_capture_error_state(dev
);
1704 i915_report_and_clear_eir(dev
);
1707 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG
,
1708 &dev_priv
->gpu_error
.reset_counter
);
1711 * Wakeup waiting processes so that the reset work function
1712 * i915_error_work_func doesn't deadlock trying to grab various
1713 * locks. By bumping the reset counter first, the woken
1714 * processes will see a reset in progress and back off,
1715 * releasing their locks and then wait for the reset completion.
1716 * We must do this for _all_ gpu waiters that might hold locks
1717 * that the reset work needs to acquire.
1719 * Note: The wake_up serves as the required memory barrier to
1720 * ensure that the waiters see the updated value of the reset
1723 i915_error_wake_up(dev_priv
, false);
1727 * Our reset work can grab modeset locks (since it needs to reset the
1728 * state of outstanding pagelips). Hence it must not be run on our own
1729 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
1730 * code will deadlock.
1732 schedule_work(&dev_priv
->gpu_error
.work
);
1735 static void __always_unused
i915_pageflip_stall_check(struct drm_device
*dev
, int pipe
)
1737 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1738 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1739 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1740 struct drm_i915_gem_object
*obj
;
1741 struct intel_unpin_work
*work
;
1742 unsigned long flags
;
1743 bool stall_detected
;
1745 /* Ignore early vblank irqs */
1746 if (intel_crtc
== NULL
)
1749 spin_lock_irqsave(&dev
->event_lock
, flags
);
1750 work
= intel_crtc
->unpin_work
;
1753 atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
||
1754 !work
->enable_stall_check
) {
1755 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1756 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1760 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1761 obj
= work
->pending_flip_obj
;
1762 if (INTEL_INFO(dev
)->gen
>= 4) {
1763 int dspsurf
= DSPSURF(intel_crtc
->plane
);
1764 stall_detected
= I915_HI_DISPBASE(I915_READ(dspsurf
)) ==
1765 i915_gem_obj_ggtt_offset(obj
);
1767 int dspaddr
= DSPADDR(intel_crtc
->plane
);
1768 stall_detected
= I915_READ(dspaddr
) == (i915_gem_obj_ggtt_offset(obj
) +
1769 crtc
->y
* crtc
->fb
->pitches
[0] +
1770 crtc
->x
* crtc
->fb
->bits_per_pixel
/8);
1773 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1775 if (stall_detected
) {
1776 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1777 intel_prepare_page_flip(dev
, intel_crtc
->plane
);
1781 /* Called from drm generic code, passed 'crtc' which
1782 * we use as a pipe index
1784 static int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
1786 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1787 unsigned long irqflags
;
1789 if (!i915_pipe_enabled(dev
, pipe
))
1792 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1793 if (INTEL_INFO(dev
)->gen
>= 4)
1794 i915_enable_pipestat(dev_priv
, pipe
,
1795 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1797 i915_enable_pipestat(dev_priv
, pipe
,
1798 PIPE_VBLANK_INTERRUPT_ENABLE
);
1800 /* maintain vblank delivery even in deep C-states */
1801 if (dev_priv
->info
->gen
== 3)
1802 I915_WRITE(INSTPM
, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS
));
1803 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1808 static int ironlake_enable_vblank(struct drm_device
*dev
, int pipe
)
1810 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1811 unsigned long irqflags
;
1812 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
1813 DE_PIPE_VBLANK_ILK(pipe
);
1815 if (!i915_pipe_enabled(dev
, pipe
))
1818 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1819 ironlake_enable_display_irq(dev_priv
, bit
);
1820 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1825 static int valleyview_enable_vblank(struct drm_device
*dev
, int pipe
)
1827 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1828 unsigned long irqflags
;
1831 if (!i915_pipe_enabled(dev
, pipe
))
1834 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1835 imr
= I915_READ(VLV_IMR
);
1837 imr
&= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
1839 imr
&= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1840 I915_WRITE(VLV_IMR
, imr
);
1841 i915_enable_pipestat(dev_priv
, pipe
,
1842 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1843 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1848 /* Called from drm generic code, passed 'crtc' which
1849 * we use as a pipe index
1851 static void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
1853 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1854 unsigned long irqflags
;
1856 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1857 if (dev_priv
->info
->gen
== 3)
1858 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS
));
1860 i915_disable_pipestat(dev_priv
, pipe
,
1861 PIPE_VBLANK_INTERRUPT_ENABLE
|
1862 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1863 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1866 static void ironlake_disable_vblank(struct drm_device
*dev
, int pipe
)
1868 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1869 unsigned long irqflags
;
1870 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
1871 DE_PIPE_VBLANK_ILK(pipe
);
1873 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1874 ironlake_disable_display_irq(dev_priv
, bit
);
1875 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1878 static void valleyview_disable_vblank(struct drm_device
*dev
, int pipe
)
1880 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1881 unsigned long irqflags
;
1884 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1885 i915_disable_pipestat(dev_priv
, pipe
,
1886 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1887 imr
= I915_READ(VLV_IMR
);
1889 imr
|= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
1891 imr
|= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1892 I915_WRITE(VLV_IMR
, imr
);
1893 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1897 ring_last_seqno(struct intel_ring_buffer
*ring
)
1899 return list_entry(ring
->request_list
.prev
,
1900 struct drm_i915_gem_request
, list
)->seqno
;
1904 ring_idle(struct intel_ring_buffer
*ring
, u32 seqno
)
1906 return (list_empty(&ring
->request_list
) ||
1907 i915_seqno_passed(seqno
, ring_last_seqno(ring
)));
1910 static struct intel_ring_buffer
*
1911 semaphore_waits_for(struct intel_ring_buffer
*ring
, u32
*seqno
)
1913 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1914 u32 cmd
, ipehr
, acthd
, acthd_min
;
1916 ipehr
= I915_READ(RING_IPEHR(ring
->mmio_base
));
1917 if ((ipehr
& ~(0x3 << 16)) !=
1918 (MI_SEMAPHORE_MBOX
| MI_SEMAPHORE_COMPARE
| MI_SEMAPHORE_REGISTER
))
1921 /* ACTHD is likely pointing to the dword after the actual command,
1922 * so scan backwards until we find the MBOX.
1924 acthd
= intel_ring_get_active_head(ring
) & HEAD_ADDR
;
1925 acthd_min
= max((int)acthd
- 3 * 4, 0);
1927 cmd
= ioread32(ring
->virtual_start
+ acthd
);
1932 if (acthd
< acthd_min
)
1936 *seqno
= ioread32(ring
->virtual_start
+acthd
+4)+1;
1937 return &dev_priv
->ring
[(ring
->id
+ (((ipehr
>> 17) & 1) + 1)) % 3];
1940 static int semaphore_passed(struct intel_ring_buffer
*ring
)
1942 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1943 struct intel_ring_buffer
*signaller
;
1946 ring
->hangcheck
.deadlock
= true;
1948 signaller
= semaphore_waits_for(ring
, &seqno
);
1949 if (signaller
== NULL
|| signaller
->hangcheck
.deadlock
)
1952 /* cursory check for an unkickable deadlock */
1953 ctl
= I915_READ_CTL(signaller
);
1954 if (ctl
& RING_WAIT_SEMAPHORE
&& semaphore_passed(signaller
) < 0)
1957 return i915_seqno_passed(signaller
->get_seqno(signaller
, false), seqno
);
1960 static void semaphore_clear_deadlocks(struct drm_i915_private
*dev_priv
)
1962 struct intel_ring_buffer
*ring
;
1965 for_each_ring(ring
, dev_priv
, i
)
1966 ring
->hangcheck
.deadlock
= false;
1969 static enum intel_ring_hangcheck_action
1970 ring_stuck(struct intel_ring_buffer
*ring
, u32 acthd
)
1972 struct drm_device
*dev
= ring
->dev
;
1973 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1976 if (ring
->hangcheck
.acthd
!= acthd
)
1977 return HANGCHECK_ACTIVE
;
1980 return HANGCHECK_HUNG
;
1982 /* Is the chip hanging on a WAIT_FOR_EVENT?
1983 * If so we can simply poke the RB_WAIT bit
1984 * and break the hang. This should work on
1985 * all but the second generation chipsets.
1987 tmp
= I915_READ_CTL(ring
);
1988 if (tmp
& RING_WAIT
) {
1989 DRM_ERROR("Kicking stuck wait on %s\n",
1991 i915_handle_error(dev
, false);
1992 I915_WRITE_CTL(ring
, tmp
);
1993 return HANGCHECK_KICK
;
1996 if (INTEL_INFO(dev
)->gen
>= 6 && tmp
& RING_WAIT_SEMAPHORE
) {
1997 switch (semaphore_passed(ring
)) {
1999 return HANGCHECK_HUNG
;
2001 DRM_ERROR("Kicking stuck semaphore on %s\n",
2003 i915_handle_error(dev
, false);
2004 I915_WRITE_CTL(ring
, tmp
);
2005 return HANGCHECK_KICK
;
2007 return HANGCHECK_WAIT
;
2011 return HANGCHECK_HUNG
;
2015 * This is called when the chip hasn't reported back with completed
2016 * batchbuffers in a long time. We keep track per ring seqno progress and
2017 * if there are no progress, hangcheck score for that ring is increased.
2018 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2019 * we kick the ring. If we see no progress on three subsequent calls
2020 * we assume chip is wedged and try to fix it by resetting the chip.
2022 static void i915_hangcheck_elapsed(unsigned long data
)
2024 struct drm_device
*dev
= (struct drm_device
*)data
;
2025 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2026 struct intel_ring_buffer
*ring
;
2028 int busy_count
= 0, rings_hung
= 0;
2029 bool stuck
[I915_NUM_RINGS
] = { 0 };
2035 if (!i915_enable_hangcheck
)
2038 for_each_ring(ring
, dev_priv
, i
) {
2042 semaphore_clear_deadlocks(dev_priv
);
2044 seqno
= ring
->get_seqno(ring
, false);
2045 acthd
= intel_ring_get_active_head(ring
);
2047 if (ring
->hangcheck
.seqno
== seqno
) {
2048 if (ring_idle(ring
, seqno
)) {
2049 ring
->hangcheck
.action
= HANGCHECK_IDLE
;
2051 if (waitqueue_active(&ring
->irq_queue
)) {
2052 /* Issue a wake-up to catch stuck h/w. */
2053 if (!test_and_set_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
)) {
2054 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2056 wake_up_all(&ring
->irq_queue
);
2058 /* Safeguard against driver failure */
2059 ring
->hangcheck
.score
+= BUSY
;
2063 /* We always increment the hangcheck score
2064 * if the ring is busy and still processing
2065 * the same request, so that no single request
2066 * can run indefinitely (such as a chain of
2067 * batches). The only time we do not increment
2068 * the hangcheck score on this ring, if this
2069 * ring is in a legitimate wait for another
2070 * ring. In that case the waiting ring is a
2071 * victim and we want to be sure we catch the
2072 * right culprit. Then every time we do kick
2073 * the ring, add a small increment to the
2074 * score so that we can catch a batch that is
2075 * being repeatedly kicked and so responsible
2076 * for stalling the machine.
2078 ring
->hangcheck
.action
= ring_stuck(ring
,
2081 switch (ring
->hangcheck
.action
) {
2082 case HANGCHECK_IDLE
:
2083 case HANGCHECK_WAIT
:
2085 case HANGCHECK_ACTIVE
:
2086 ring
->hangcheck
.score
+= BUSY
;
2088 case HANGCHECK_KICK
:
2089 ring
->hangcheck
.score
+= KICK
;
2091 case HANGCHECK_HUNG
:
2092 ring
->hangcheck
.score
+= HUNG
;
2098 ring
->hangcheck
.action
= HANGCHECK_ACTIVE
;
2100 /* Gradually reduce the count so that we catch DoS
2101 * attempts across multiple batches.
2103 if (ring
->hangcheck
.score
> 0)
2104 ring
->hangcheck
.score
--;
2107 ring
->hangcheck
.seqno
= seqno
;
2108 ring
->hangcheck
.acthd
= acthd
;
2112 for_each_ring(ring
, dev_priv
, i
) {
2113 if (ring
->hangcheck
.score
> FIRE
) {
2114 DRM_INFO("%s on %s\n",
2115 stuck
[i
] ? "stuck" : "no progress",
2122 return i915_handle_error(dev
, true);
2125 /* Reset timer case chip hangs without another request
2127 i915_queue_hangcheck(dev
);
2130 void i915_queue_hangcheck(struct drm_device
*dev
)
2132 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2133 if (!i915_enable_hangcheck
)
2136 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
2137 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
2140 static void ibx_irq_preinstall(struct drm_device
*dev
)
2142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2144 if (HAS_PCH_NOP(dev
))
2147 /* south display irq */
2148 I915_WRITE(SDEIMR
, 0xffffffff);
2150 * SDEIER is also touched by the interrupt handler to work around missed
2151 * PCH interrupts. Hence we can't update it after the interrupt handler
2152 * is enabled - instead we unconditionally enable all PCH interrupt
2153 * sources here, but then only unmask them as needed with SDEIMR.
2155 I915_WRITE(SDEIER
, 0xffffffff);
2156 POSTING_READ(SDEIER
);
2159 static void gen5_gt_irq_preinstall(struct drm_device
*dev
)
2161 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2164 I915_WRITE(GTIMR
, 0xffffffff);
2165 I915_WRITE(GTIER
, 0x0);
2166 POSTING_READ(GTIER
);
2168 if (INTEL_INFO(dev
)->gen
>= 6) {
2170 I915_WRITE(GEN6_PMIMR
, 0xffffffff);
2171 I915_WRITE(GEN6_PMIER
, 0x0);
2172 POSTING_READ(GEN6_PMIER
);
2178 static void ironlake_irq_preinstall(struct drm_device
*dev
)
2180 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2182 atomic_set(&dev_priv
->irq_received
, 0);
2184 I915_WRITE(HWSTAM
, 0xeffe);
2186 I915_WRITE(DEIMR
, 0xffffffff);
2187 I915_WRITE(DEIER
, 0x0);
2188 POSTING_READ(DEIER
);
2190 gen5_gt_irq_preinstall(dev
);
2192 ibx_irq_preinstall(dev
);
2195 static void valleyview_irq_preinstall(struct drm_device
*dev
)
2197 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2200 atomic_set(&dev_priv
->irq_received
, 0);
2203 I915_WRITE(VLV_IMR
, 0);
2204 I915_WRITE(RING_IMR(RENDER_RING_BASE
), 0);
2205 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE
), 0);
2206 I915_WRITE(RING_IMR(BLT_RING_BASE
), 0);
2209 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2210 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2212 gen5_gt_irq_preinstall(dev
);
2214 I915_WRITE(DPINVGTT
, 0xff);
2216 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2217 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2219 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2220 I915_WRITE(VLV_IIR
, 0xffffffff);
2221 I915_WRITE(VLV_IMR
, 0xffffffff);
2222 I915_WRITE(VLV_IER
, 0x0);
2223 POSTING_READ(VLV_IER
);
2226 static void ibx_hpd_irq_setup(struct drm_device
*dev
)
2228 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2229 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2230 struct intel_encoder
*intel_encoder
;
2231 u32 hotplug_irqs
, hotplug
, enabled_irqs
= 0;
2233 if (HAS_PCH_IBX(dev
)) {
2234 hotplug_irqs
= SDE_HOTPLUG_MASK
;
2235 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2236 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2237 enabled_irqs
|= hpd_ibx
[intel_encoder
->hpd_pin
];
2239 hotplug_irqs
= SDE_HOTPLUG_MASK_CPT
;
2240 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2241 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2242 enabled_irqs
|= hpd_cpt
[intel_encoder
->hpd_pin
];
2245 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
2248 * Enable digital hotplug on the PCH, and configure the DP short pulse
2249 * duration to 2ms (which is the minimum in the Display Port spec)
2251 * This register is the same on all known PCH chips.
2253 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
2254 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
2255 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
2256 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
2257 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
2258 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
2261 static void ibx_irq_postinstall(struct drm_device
*dev
)
2263 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2266 if (HAS_PCH_NOP(dev
))
2269 if (HAS_PCH_IBX(dev
)) {
2270 mask
= SDE_GMBUS
| SDE_AUX_MASK
| SDE_TRANSB_FIFO_UNDER
|
2271 SDE_TRANSA_FIFO_UNDER
| SDE_POISON
;
2273 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
| SDE_ERROR_CPT
;
2275 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2278 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2279 I915_WRITE(SDEIMR
, ~mask
);
2282 static void gen5_gt_irq_postinstall(struct drm_device
*dev
)
2284 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2285 u32 pm_irqs
, gt_irqs
;
2287 pm_irqs
= gt_irqs
= 0;
2289 dev_priv
->gt_irq_mask
= ~0;
2290 if (HAS_L3_DPF(dev
)) {
2291 /* L3 parity interrupt is always unmasked. */
2292 dev_priv
->gt_irq_mask
= ~GT_PARITY_ERROR(dev
);
2293 gt_irqs
|= GT_PARITY_ERROR(dev
);
2296 gt_irqs
|= GT_RENDER_USER_INTERRUPT
;
2298 gt_irqs
|= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
|
2299 ILK_BSD_USER_INTERRUPT
;
2301 gt_irqs
|= GT_BLT_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
;
2304 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2305 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
2306 I915_WRITE(GTIER
, gt_irqs
);
2307 POSTING_READ(GTIER
);
2309 if (INTEL_INFO(dev
)->gen
>= 6) {
2310 pm_irqs
|= GEN6_PM_RPS_EVENTS
;
2313 pm_irqs
|= PM_VEBOX_USER_INTERRUPT
;
2315 dev_priv
->pm_irq_mask
= 0xffffffff;
2316 I915_WRITE(GEN6_PMIIR
, I915_READ(GEN6_PMIIR
));
2317 I915_WRITE(GEN6_PMIMR
, dev_priv
->pm_irq_mask
);
2318 I915_WRITE(GEN6_PMIER
, pm_irqs
);
2319 POSTING_READ(GEN6_PMIER
);
2323 static int ironlake_irq_postinstall(struct drm_device
*dev
)
2325 unsigned long irqflags
;
2326 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2327 u32 display_mask
, extra_mask
;
2329 if (INTEL_INFO(dev
)->gen
>= 7) {
2330 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
|
2331 DE_PCH_EVENT_IVB
| DE_PLANEC_FLIP_DONE_IVB
|
2332 DE_PLANEB_FLIP_DONE_IVB
|
2333 DE_PLANEA_FLIP_DONE_IVB
| DE_AUX_CHANNEL_A_IVB
|
2335 extra_mask
= (DE_PIPEC_VBLANK_IVB
| DE_PIPEB_VBLANK_IVB
|
2336 DE_PIPEA_VBLANK_IVB
);
2338 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2340 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
2341 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
|
2342 DE_AUX_CHANNEL_A
| DE_PIPEB_FIFO_UNDERRUN
|
2343 DE_PIPEA_FIFO_UNDERRUN
| DE_POISON
);
2344 extra_mask
= DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
| DE_PCU_EVENT
;
2347 dev_priv
->irq_mask
= ~display_mask
;
2349 /* should always can generate irq */
2350 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2351 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
2352 I915_WRITE(DEIER
, display_mask
| extra_mask
);
2353 POSTING_READ(DEIER
);
2355 gen5_gt_irq_postinstall(dev
);
2357 ibx_irq_postinstall(dev
);
2359 if (IS_IRONLAKE_M(dev
)) {
2360 /* Enable PCU event interrupts
2362 * spinlocking not required here for correctness since interrupt
2363 * setup is guaranteed to run in single-threaded context. But we
2364 * need it to make the assert_spin_locked happy. */
2365 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2366 ironlake_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
2367 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2373 static int valleyview_irq_postinstall(struct drm_device
*dev
)
2375 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2377 u32 pipestat_enable
= PLANE_FLIP_DONE_INT_EN_VLV
;
2378 unsigned long irqflags
;
2380 enable_mask
= I915_DISPLAY_PORT_INTERRUPT
;
2381 enable_mask
|= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2382 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2383 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2384 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2387 *Leave vblank interrupts masked initially. enable/disable will
2388 * toggle them based on usage.
2390 dev_priv
->irq_mask
= (~enable_mask
) |
2391 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2392 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2394 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2395 POSTING_READ(PORT_HOTPLUG_EN
);
2397 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
2398 I915_WRITE(VLV_IER
, enable_mask
);
2399 I915_WRITE(VLV_IIR
, 0xffffffff);
2400 I915_WRITE(PIPESTAT(0), 0xffff);
2401 I915_WRITE(PIPESTAT(1), 0xffff);
2402 POSTING_READ(VLV_IER
);
2404 /* Interrupt setup is already guaranteed to be single-threaded, this is
2405 * just to make the assert_spin_locked check happy. */
2406 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2407 i915_enable_pipestat(dev_priv
, 0, pipestat_enable
);
2408 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
2409 i915_enable_pipestat(dev_priv
, 1, pipestat_enable
);
2410 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2412 I915_WRITE(VLV_IIR
, 0xffffffff);
2413 I915_WRITE(VLV_IIR
, 0xffffffff);
2415 gen5_gt_irq_postinstall(dev
);
2417 /* ack & enable invalid PTE error interrupts */
2418 #if 0 /* FIXME: add support to irq handler for checking these bits */
2419 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
2420 I915_WRITE(DPINVGTT
, DPINVGTT_EN_MASK
);
2423 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
2428 static void valleyview_irq_uninstall(struct drm_device
*dev
)
2430 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2436 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2439 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2441 I915_WRITE(HWSTAM
, 0xffffffff);
2442 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2443 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2445 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2446 I915_WRITE(VLV_IIR
, 0xffffffff);
2447 I915_WRITE(VLV_IMR
, 0xffffffff);
2448 I915_WRITE(VLV_IER
, 0x0);
2449 POSTING_READ(VLV_IER
);
2452 static void ironlake_irq_uninstall(struct drm_device
*dev
)
2454 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2459 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2461 I915_WRITE(HWSTAM
, 0xffffffff);
2463 I915_WRITE(DEIMR
, 0xffffffff);
2464 I915_WRITE(DEIER
, 0x0);
2465 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2467 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2469 I915_WRITE(GTIMR
, 0xffffffff);
2470 I915_WRITE(GTIER
, 0x0);
2471 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2473 if (HAS_PCH_NOP(dev
))
2476 I915_WRITE(SDEIMR
, 0xffffffff);
2477 I915_WRITE(SDEIER
, 0x0);
2478 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2479 if (HAS_PCH_CPT(dev
) || HAS_PCH_LPT(dev
))
2480 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2483 static void i8xx_irq_preinstall(struct drm_device
* dev
)
2485 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2488 atomic_set(&dev_priv
->irq_received
, 0);
2491 I915_WRITE(PIPESTAT(pipe
), 0);
2492 I915_WRITE16(IMR
, 0xffff);
2493 I915_WRITE16(IER
, 0x0);
2494 POSTING_READ16(IER
);
2497 static int i8xx_irq_postinstall(struct drm_device
*dev
)
2499 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2502 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2504 /* Unmask the interrupts that we always want on. */
2505 dev_priv
->irq_mask
=
2506 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2507 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2508 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2509 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2510 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2511 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
2514 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2515 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2516 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2517 I915_USER_INTERRUPT
);
2518 POSTING_READ16(IER
);
2524 * Returns true when a page flip has completed.
2526 static bool i8xx_handle_vblank(struct drm_device
*dev
,
2529 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2530 u16 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(pipe
);
2532 if (!drm_handle_vblank(dev
, pipe
))
2535 if ((iir
& flip_pending
) == 0)
2538 intel_prepare_page_flip(dev
, pipe
);
2540 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2541 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2542 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2543 * the flip is completed (no longer pending). Since this doesn't raise
2544 * an interrupt per se, we watch for the change at vblank.
2546 if (I915_READ16(ISR
) & flip_pending
)
2549 intel_finish_page_flip(dev
, pipe
);
2554 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
2556 struct drm_device
*dev
= (struct drm_device
*) arg
;
2557 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2560 unsigned long irqflags
;
2563 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2564 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2566 atomic_inc(&dev_priv
->irq_received
);
2568 iir
= I915_READ16(IIR
);
2572 while (iir
& ~flip_mask
) {
2573 /* Can't rely on pipestat interrupt bit in iir as it might
2574 * have been cleared after the pipestat interrupt was received.
2575 * It doesn't set the bit in iir again, but it still produces
2576 * interrupts (for non-MSI).
2578 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2579 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2580 i915_handle_error(dev
, false);
2582 for_each_pipe(pipe
) {
2583 int reg
= PIPESTAT(pipe
);
2584 pipe_stats
[pipe
] = I915_READ(reg
);
2587 * Clear the PIPE*STAT regs before the IIR
2589 if (pipe_stats
[pipe
] & 0x8000ffff) {
2590 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2591 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2593 I915_WRITE(reg
, pipe_stats
[pipe
]);
2596 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2598 I915_WRITE16(IIR
, iir
& ~flip_mask
);
2599 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
2601 i915_update_dri1_breadcrumb(dev
);
2603 if (iir
& I915_USER_INTERRUPT
)
2604 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2606 if (pipe_stats
[0] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2607 i8xx_handle_vblank(dev
, 0, iir
))
2608 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(0);
2610 if (pipe_stats
[1] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2611 i8xx_handle_vblank(dev
, 1, iir
))
2612 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(1);
2620 static void i8xx_irq_uninstall(struct drm_device
* dev
)
2622 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2625 for_each_pipe(pipe
) {
2626 /* Clear enable bits; then clear status bits */
2627 I915_WRITE(PIPESTAT(pipe
), 0);
2628 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
2630 I915_WRITE16(IMR
, 0xffff);
2631 I915_WRITE16(IER
, 0x0);
2632 I915_WRITE16(IIR
, I915_READ16(IIR
));
2635 static void i915_irq_preinstall(struct drm_device
* dev
)
2637 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2640 atomic_set(&dev_priv
->irq_received
, 0);
2642 if (I915_HAS_HOTPLUG(dev
)) {
2643 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2644 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2647 I915_WRITE16(HWSTAM
, 0xeffe);
2649 I915_WRITE(PIPESTAT(pipe
), 0);
2650 I915_WRITE(IMR
, 0xffffffff);
2651 I915_WRITE(IER
, 0x0);
2655 static int i915_irq_postinstall(struct drm_device
*dev
)
2657 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2660 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2662 /* Unmask the interrupts that we always want on. */
2663 dev_priv
->irq_mask
=
2664 ~(I915_ASLE_INTERRUPT
|
2665 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2666 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2667 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2668 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2669 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2672 I915_ASLE_INTERRUPT
|
2673 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2674 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2675 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2676 I915_USER_INTERRUPT
;
2678 if (I915_HAS_HOTPLUG(dev
)) {
2679 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2680 POSTING_READ(PORT_HOTPLUG_EN
);
2682 /* Enable in IER... */
2683 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
2684 /* and unmask in IMR */
2685 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
2688 I915_WRITE(IMR
, dev_priv
->irq_mask
);
2689 I915_WRITE(IER
, enable_mask
);
2692 i915_enable_asle_pipestat(dev
);
2698 * Returns true when a page flip has completed.
2700 static bool i915_handle_vblank(struct drm_device
*dev
,
2701 int plane
, int pipe
, u32 iir
)
2703 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2704 u32 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
2706 if (!drm_handle_vblank(dev
, pipe
))
2709 if ((iir
& flip_pending
) == 0)
2712 intel_prepare_page_flip(dev
, plane
);
2714 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2715 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2716 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2717 * the flip is completed (no longer pending). Since this doesn't raise
2718 * an interrupt per se, we watch for the change at vblank.
2720 if (I915_READ(ISR
) & flip_pending
)
2723 intel_finish_page_flip(dev
, pipe
);
2728 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
2730 struct drm_device
*dev
= (struct drm_device
*) arg
;
2731 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2732 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
2733 unsigned long irqflags
;
2735 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2736 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2737 int pipe
, ret
= IRQ_NONE
;
2739 atomic_inc(&dev_priv
->irq_received
);
2741 iir
= I915_READ(IIR
);
2743 bool irq_received
= (iir
& ~flip_mask
) != 0;
2744 bool blc_event
= false;
2746 /* Can't rely on pipestat interrupt bit in iir as it might
2747 * have been cleared after the pipestat interrupt was received.
2748 * It doesn't set the bit in iir again, but it still produces
2749 * interrupts (for non-MSI).
2751 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2752 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2753 i915_handle_error(dev
, false);
2755 for_each_pipe(pipe
) {
2756 int reg
= PIPESTAT(pipe
);
2757 pipe_stats
[pipe
] = I915_READ(reg
);
2759 /* Clear the PIPE*STAT regs before the IIR */
2760 if (pipe_stats
[pipe
] & 0x8000ffff) {
2761 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2762 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2764 I915_WRITE(reg
, pipe_stats
[pipe
]);
2765 irq_received
= true;
2768 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2773 /* Consume port. Then clear IIR or we'll miss events */
2774 if ((I915_HAS_HOTPLUG(dev
)) &&
2775 (iir
& I915_DISPLAY_PORT_INTERRUPT
)) {
2776 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
2777 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
2779 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2782 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
2784 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
2785 POSTING_READ(PORT_HOTPLUG_STAT
);
2788 I915_WRITE(IIR
, iir
& ~flip_mask
);
2789 new_iir
= I915_READ(IIR
); /* Flush posted writes */
2791 if (iir
& I915_USER_INTERRUPT
)
2792 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2794 for_each_pipe(pipe
) {
2799 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2800 i915_handle_vblank(dev
, plane
, pipe
, iir
))
2801 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
2803 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
2807 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
2808 intel_opregion_asle_intr(dev
);
2810 /* With MSI, interrupts are only generated when iir
2811 * transitions from zero to nonzero. If another bit got
2812 * set while we were handling the existing iir bits, then
2813 * we would never get another interrupt.
2815 * This is fine on non-MSI as well, as if we hit this path
2816 * we avoid exiting the interrupt handler only to generate
2819 * Note that for MSI this could cause a stray interrupt report
2820 * if an interrupt landed in the time between writing IIR and
2821 * the posting read. This should be rare enough to never
2822 * trigger the 99% of 100,000 interrupts test for disabling
2827 } while (iir
& ~flip_mask
);
2829 i915_update_dri1_breadcrumb(dev
);
2834 static void i915_irq_uninstall(struct drm_device
* dev
)
2836 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2839 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2841 if (I915_HAS_HOTPLUG(dev
)) {
2842 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2843 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2846 I915_WRITE16(HWSTAM
, 0xffff);
2847 for_each_pipe(pipe
) {
2848 /* Clear enable bits; then clear status bits */
2849 I915_WRITE(PIPESTAT(pipe
), 0);
2850 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
2852 I915_WRITE(IMR
, 0xffffffff);
2853 I915_WRITE(IER
, 0x0);
2855 I915_WRITE(IIR
, I915_READ(IIR
));
2858 static void i965_irq_preinstall(struct drm_device
* dev
)
2860 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2863 atomic_set(&dev_priv
->irq_received
, 0);
2865 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2866 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2868 I915_WRITE(HWSTAM
, 0xeffe);
2870 I915_WRITE(PIPESTAT(pipe
), 0);
2871 I915_WRITE(IMR
, 0xffffffff);
2872 I915_WRITE(IER
, 0x0);
2876 static int i965_irq_postinstall(struct drm_device
*dev
)
2878 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2881 unsigned long irqflags
;
2883 /* Unmask the interrupts that we always want on. */
2884 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
2885 I915_DISPLAY_PORT_INTERRUPT
|
2886 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2887 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2888 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2889 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2890 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2892 enable_mask
= ~dev_priv
->irq_mask
;
2893 enable_mask
&= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2894 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
2895 enable_mask
|= I915_USER_INTERRUPT
;
2898 enable_mask
|= I915_BSD_USER_INTERRUPT
;
2900 /* Interrupt setup is already guaranteed to be single-threaded, this is
2901 * just to make the assert_spin_locked check happy. */
2902 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2903 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
2904 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2907 * Enable some error detection, note the instruction error mask
2908 * bit is reserved, so we leave it masked.
2911 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
2912 GM45_ERROR_MEM_PRIV
|
2913 GM45_ERROR_CP_PRIV
|
2914 I915_ERROR_MEMORY_REFRESH
);
2916 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
2917 I915_ERROR_MEMORY_REFRESH
);
2919 I915_WRITE(EMR
, error_mask
);
2921 I915_WRITE(IMR
, dev_priv
->irq_mask
);
2922 I915_WRITE(IER
, enable_mask
);
2925 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2926 POSTING_READ(PORT_HOTPLUG_EN
);
2928 i915_enable_asle_pipestat(dev
);
2933 static void i915_hpd_irq_setup(struct drm_device
*dev
)
2935 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2936 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2937 struct intel_encoder
*intel_encoder
;
2940 assert_spin_locked(&dev_priv
->irq_lock
);
2942 if (I915_HAS_HOTPLUG(dev
)) {
2943 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
2944 hotplug_en
&= ~HOTPLUG_INT_EN_MASK
;
2945 /* Note HDMI and DP share hotplug bits */
2946 /* enable bits are the same for all generations */
2947 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2948 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2949 hotplug_en
|= hpd_mask_i915
[intel_encoder
->hpd_pin
];
2950 /* Programming the CRT detection parameters tends
2951 to generate a spurious hotplug event about three
2952 seconds later. So just do it once.
2955 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
2956 hotplug_en
&= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK
;
2957 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
2959 /* Ignore TV since it's buggy */
2960 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
2964 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
2966 struct drm_device
*dev
= (struct drm_device
*) arg
;
2967 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2969 u32 pipe_stats
[I915_MAX_PIPES
];
2970 unsigned long irqflags
;
2972 int ret
= IRQ_NONE
, pipe
;
2974 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2975 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2977 atomic_inc(&dev_priv
->irq_received
);
2979 iir
= I915_READ(IIR
);
2982 bool blc_event
= false;
2984 irq_received
= (iir
& ~flip_mask
) != 0;
2986 /* Can't rely on pipestat interrupt bit in iir as it might
2987 * have been cleared after the pipestat interrupt was received.
2988 * It doesn't set the bit in iir again, but it still produces
2989 * interrupts (for non-MSI).
2991 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2992 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2993 i915_handle_error(dev
, false);
2995 for_each_pipe(pipe
) {
2996 int reg
= PIPESTAT(pipe
);
2997 pipe_stats
[pipe
] = I915_READ(reg
);
3000 * Clear the PIPE*STAT regs before the IIR
3002 if (pipe_stats
[pipe
] & 0x8000ffff) {
3003 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
3004 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3006 I915_WRITE(reg
, pipe_stats
[pipe
]);
3010 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3017 /* Consume port. Then clear IIR or we'll miss events */
3018 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
3019 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
3020 u32 hotplug_trigger
= hotplug_status
& (IS_G4X(dev
) ?
3021 HOTPLUG_INT_STATUS_G4X
:
3022 HOTPLUG_INT_STATUS_I915
);
3024 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3027 intel_hpd_irq_handler(dev
, hotplug_trigger
,
3028 IS_G4X(dev
) ? hpd_status_gen4
: hpd_status_i915
);
3030 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
3031 I915_READ(PORT_HOTPLUG_STAT
);
3034 I915_WRITE(IIR
, iir
& ~flip_mask
);
3035 new_iir
= I915_READ(IIR
); /* Flush posted writes */
3037 if (iir
& I915_USER_INTERRUPT
)
3038 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
3039 if (iir
& I915_BSD_USER_INTERRUPT
)
3040 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
3042 for_each_pipe(pipe
) {
3043 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
3044 i915_handle_vblank(dev
, pipe
, pipe
, iir
))
3045 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
3047 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
3052 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
3053 intel_opregion_asle_intr(dev
);
3055 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
3056 gmbus_irq_handler(dev
);
3058 /* With MSI, interrupts are only generated when iir
3059 * transitions from zero to nonzero. If another bit got
3060 * set while we were handling the existing iir bits, then
3061 * we would never get another interrupt.
3063 * This is fine on non-MSI as well, as if we hit this path
3064 * we avoid exiting the interrupt handler only to generate
3067 * Note that for MSI this could cause a stray interrupt report
3068 * if an interrupt landed in the time between writing IIR and
3069 * the posting read. This should be rare enough to never
3070 * trigger the 99% of 100,000 interrupts test for disabling
3076 i915_update_dri1_breadcrumb(dev
);
3081 static void i965_irq_uninstall(struct drm_device
* dev
)
3083 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3089 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
3091 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3092 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3094 I915_WRITE(HWSTAM
, 0xffffffff);
3096 I915_WRITE(PIPESTAT(pipe
), 0);
3097 I915_WRITE(IMR
, 0xffffffff);
3098 I915_WRITE(IER
, 0x0);
3101 I915_WRITE(PIPESTAT(pipe
),
3102 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
3103 I915_WRITE(IIR
, I915_READ(IIR
));
3106 static void i915_reenable_hotplug_timer_func(unsigned long data
)
3108 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*)data
;
3109 struct drm_device
*dev
= dev_priv
->dev
;
3110 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3111 unsigned long irqflags
;
3114 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3115 for (i
= (HPD_NONE
+ 1); i
< HPD_NUM_PINS
; i
++) {
3116 struct drm_connector
*connector
;
3118 if (dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_DISABLED
)
3121 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3123 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3124 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3126 if (intel_connector
->encoder
->hpd_pin
== i
) {
3127 if (connector
->polled
!= intel_connector
->polled
)
3128 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3129 drm_get_connector_name(connector
));
3130 connector
->polled
= intel_connector
->polled
;
3131 if (!connector
->polled
)
3132 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3136 if (dev_priv
->display
.hpd_irq_setup
)
3137 dev_priv
->display
.hpd_irq_setup(dev
);
3138 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3141 void intel_irq_init(struct drm_device
*dev
)
3143 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3145 INIT_WORK(&dev_priv
->hotplug_work
, i915_hotplug_work_func
);
3146 INIT_WORK(&dev_priv
->gpu_error
.work
, i915_error_work_func
);
3147 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
3148 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
3150 setup_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
3151 i915_hangcheck_elapsed
,
3152 (unsigned long) dev
);
3153 setup_timer(&dev_priv
->hotplug_reenable_timer
, i915_reenable_hotplug_timer_func
,
3154 (unsigned long) dev_priv
);
3156 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
, PM_QOS_DEFAULT_VALUE
);
3158 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
3159 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
3160 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
3161 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
3162 dev
->driver
->get_vblank_counter
= gm45_get_vblank_counter
;
3165 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3166 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
3168 dev
->driver
->get_vblank_timestamp
= NULL
;
3169 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
3171 if (IS_VALLEYVIEW(dev
)) {
3172 dev
->driver
->irq_handler
= valleyview_irq_handler
;
3173 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
3174 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
3175 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
3176 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
3177 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
3178 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3179 } else if (HAS_PCH_SPLIT(dev
)) {
3180 dev
->driver
->irq_handler
= ironlake_irq_handler
;
3181 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
3182 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
3183 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
3184 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
3185 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
3186 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
3188 if (INTEL_INFO(dev
)->gen
== 2) {
3189 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
3190 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
3191 dev
->driver
->irq_handler
= i8xx_irq_handler
;
3192 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
3193 } else if (INTEL_INFO(dev
)->gen
== 3) {
3194 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
3195 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
3196 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
3197 dev
->driver
->irq_handler
= i915_irq_handler
;
3198 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3200 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
3201 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
3202 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
3203 dev
->driver
->irq_handler
= i965_irq_handler
;
3204 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3206 dev
->driver
->enable_vblank
= i915_enable_vblank
;
3207 dev
->driver
->disable_vblank
= i915_disable_vblank
;
3211 void intel_hpd_init(struct drm_device
*dev
)
3213 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3214 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3215 struct drm_connector
*connector
;
3216 unsigned long irqflags
;
3219 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
3220 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
3221 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3223 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3224 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3225 connector
->polled
= intel_connector
->polled
;
3226 if (!connector
->polled
&& I915_HAS_HOTPLUG(dev
) && intel_connector
->encoder
->hpd_pin
> HPD_NONE
)
3227 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3230 /* Interrupt setup is already guaranteed to be single-threaded, this is
3231 * just to make the assert_spin_locked checks happy. */
3232 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3233 if (dev_priv
->display
.hpd_irq_setup
)
3234 dev_priv
->display
.hpd_irq_setup(dev
);
3235 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3238 /* Disable interrupts so we can allow Package C8+. */
3239 void hsw_pc8_disable_interrupts(struct drm_device
*dev
)
3241 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3242 unsigned long irqflags
;
3244 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3246 dev_priv
->pc8
.regsave
.deimr
= I915_READ(DEIMR
);
3247 dev_priv
->pc8
.regsave
.sdeimr
= I915_READ(SDEIMR
);
3248 dev_priv
->pc8
.regsave
.gtimr
= I915_READ(GTIMR
);
3249 dev_priv
->pc8
.regsave
.gtier
= I915_READ(GTIER
);
3250 dev_priv
->pc8
.regsave
.gen6_pmimr
= I915_READ(GEN6_PMIMR
);
3252 ironlake_disable_display_irq(dev_priv
, ~DE_PCH_EVENT_IVB
);
3253 ibx_disable_display_interrupt(dev_priv
, ~SDE_HOTPLUG_MASK_CPT
);
3254 ilk_disable_gt_irq(dev_priv
, 0xffffffff);
3255 snb_disable_pm_irq(dev_priv
, 0xffffffff);
3257 dev_priv
->pc8
.irqs_disabled
= true;
3259 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3262 /* Restore interrupts so we can recover from Package C8+. */
3263 void hsw_pc8_restore_interrupts(struct drm_device
*dev
)
3265 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3266 unsigned long irqflags
;
3267 uint32_t val
, expected
;
3269 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3271 val
= I915_READ(DEIMR
);
3272 expected
= ~DE_PCH_EVENT_IVB
;
3273 WARN(val
!= expected
, "DEIMR is 0x%08x, not 0x%08x\n", val
, expected
);
3275 val
= I915_READ(SDEIMR
) & ~SDE_HOTPLUG_MASK_CPT
;
3276 expected
= ~SDE_HOTPLUG_MASK_CPT
;
3277 WARN(val
!= expected
, "SDEIMR non-HPD bits are 0x%08x, not 0x%08x\n",
3280 val
= I915_READ(GTIMR
);
3281 expected
= 0xffffffff;
3282 WARN(val
!= expected
, "GTIMR is 0x%08x, not 0x%08x\n", val
, expected
);
3284 val
= I915_READ(GEN6_PMIMR
);
3285 expected
= 0xffffffff;
3286 WARN(val
!= expected
, "GEN6_PMIMR is 0x%08x, not 0x%08x\n", val
,
3289 dev_priv
->pc8
.irqs_disabled
= false;
3291 ironlake_enable_display_irq(dev_priv
, ~dev_priv
->pc8
.regsave
.deimr
);
3292 ibx_enable_display_interrupt(dev_priv
,
3293 ~dev_priv
->pc8
.regsave
.sdeimr
&
3294 ~SDE_HOTPLUG_MASK_CPT
);
3295 ilk_enable_gt_irq(dev_priv
, ~dev_priv
->pc8
.regsave
.gtimr
);
3296 snb_enable_pm_irq(dev_priv
, ~dev_priv
->pc8
.regsave
.gen6_pmimr
);
3297 I915_WRITE(GTIER
, dev_priv
->pc8
.regsave
.gtier
);
3299 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);