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drm/i914: Refactor vlv_display_irq_postinstall()
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
34 #include <drm/drmP.h>
35 #include <drm/i915_drm.h>
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "intel_drv.h"
39
40 /**
41 * DOC: interrupt handling
42 *
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
46 */
47
48 static const u32 hpd_ibx[] = {
49 [HPD_CRT] = SDE_CRT_HOTPLUG,
50 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
51 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
52 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
53 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
54 };
55
56 static const u32 hpd_cpt[] = {
57 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
58 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
59 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
60 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
61 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
62 };
63
64 static const u32 hpd_mask_i915[] = {
65 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
66 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
67 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
68 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
69 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
70 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
71 };
72
73 static const u32 hpd_status_g4x[] = {
74 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
75 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
76 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
77 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
78 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
79 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
80 };
81
82 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
83 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
84 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
85 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
86 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
87 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
88 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
89 };
90
91 /* IIR can theoretically queue up two events. Be paranoid. */
92 #define GEN8_IRQ_RESET_NDX(type, which) do { \
93 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
94 POSTING_READ(GEN8_##type##_IMR(which)); \
95 I915_WRITE(GEN8_##type##_IER(which), 0); \
96 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
97 POSTING_READ(GEN8_##type##_IIR(which)); \
98 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
99 POSTING_READ(GEN8_##type##_IIR(which)); \
100 } while (0)
101
102 #define GEN5_IRQ_RESET(type) do { \
103 I915_WRITE(type##IMR, 0xffffffff); \
104 POSTING_READ(type##IMR); \
105 I915_WRITE(type##IER, 0); \
106 I915_WRITE(type##IIR, 0xffffffff); \
107 POSTING_READ(type##IIR); \
108 I915_WRITE(type##IIR, 0xffffffff); \
109 POSTING_READ(type##IIR); \
110 } while (0)
111
112 /*
113 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
114 */
115 #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
116 u32 val = I915_READ(reg); \
117 if (val) { \
118 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
119 (reg), val); \
120 I915_WRITE((reg), 0xffffffff); \
121 POSTING_READ(reg); \
122 I915_WRITE((reg), 0xffffffff); \
123 POSTING_READ(reg); \
124 } \
125 } while (0)
126
127 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
128 GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
129 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
130 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
131 POSTING_READ(GEN8_##type##_IMR(which)); \
132 } while (0)
133
134 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
135 GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
136 I915_WRITE(type##IER, (ier_val)); \
137 I915_WRITE(type##IMR, (imr_val)); \
138 POSTING_READ(type##IMR); \
139 } while (0)
140
141 /* For display hotplug interrupt */
142 void
143 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
144 {
145 assert_spin_locked(&dev_priv->irq_lock);
146
147 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
148 return;
149
150 if ((dev_priv->irq_mask & mask) != 0) {
151 dev_priv->irq_mask &= ~mask;
152 I915_WRITE(DEIMR, dev_priv->irq_mask);
153 POSTING_READ(DEIMR);
154 }
155 }
156
157 void
158 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
159 {
160 assert_spin_locked(&dev_priv->irq_lock);
161
162 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
163 return;
164
165 if ((dev_priv->irq_mask & mask) != mask) {
166 dev_priv->irq_mask |= mask;
167 I915_WRITE(DEIMR, dev_priv->irq_mask);
168 POSTING_READ(DEIMR);
169 }
170 }
171
172 /**
173 * ilk_update_gt_irq - update GTIMR
174 * @dev_priv: driver private
175 * @interrupt_mask: mask of interrupt bits to update
176 * @enabled_irq_mask: mask of interrupt bits to enable
177 */
178 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
179 uint32_t interrupt_mask,
180 uint32_t enabled_irq_mask)
181 {
182 assert_spin_locked(&dev_priv->irq_lock);
183
184 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
185 return;
186
187 dev_priv->gt_irq_mask &= ~interrupt_mask;
188 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
189 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
190 POSTING_READ(GTIMR);
191 }
192
193 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
194 {
195 ilk_update_gt_irq(dev_priv, mask, mask);
196 }
197
198 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
199 {
200 ilk_update_gt_irq(dev_priv, mask, 0);
201 }
202
203 /**
204 * snb_update_pm_irq - update GEN6_PMIMR
205 * @dev_priv: driver private
206 * @interrupt_mask: mask of interrupt bits to update
207 * @enabled_irq_mask: mask of interrupt bits to enable
208 */
209 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
210 uint32_t interrupt_mask,
211 uint32_t enabled_irq_mask)
212 {
213 uint32_t new_val;
214
215 assert_spin_locked(&dev_priv->irq_lock);
216
217 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
218 return;
219
220 new_val = dev_priv->pm_irq_mask;
221 new_val &= ~interrupt_mask;
222 new_val |= (~enabled_irq_mask & interrupt_mask);
223
224 if (new_val != dev_priv->pm_irq_mask) {
225 dev_priv->pm_irq_mask = new_val;
226 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
227 POSTING_READ(GEN6_PMIMR);
228 }
229 }
230
231 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
232 {
233 snb_update_pm_irq(dev_priv, mask, mask);
234 }
235
236 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
237 {
238 snb_update_pm_irq(dev_priv, mask, 0);
239 }
240
241 /**
242 * bdw_update_pm_irq - update GT interrupt 2
243 * @dev_priv: driver private
244 * @interrupt_mask: mask of interrupt bits to update
245 * @enabled_irq_mask: mask of interrupt bits to enable
246 *
247 * Copied from the snb function, updated with relevant register offsets
248 */
249 static void bdw_update_pm_irq(struct drm_i915_private *dev_priv,
250 uint32_t interrupt_mask,
251 uint32_t enabled_irq_mask)
252 {
253 uint32_t new_val;
254
255 assert_spin_locked(&dev_priv->irq_lock);
256
257 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
258 return;
259
260 new_val = dev_priv->pm_irq_mask;
261 new_val &= ~interrupt_mask;
262 new_val |= (~enabled_irq_mask & interrupt_mask);
263
264 if (new_val != dev_priv->pm_irq_mask) {
265 dev_priv->pm_irq_mask = new_val;
266 I915_WRITE(GEN8_GT_IMR(2), dev_priv->pm_irq_mask);
267 POSTING_READ(GEN8_GT_IMR(2));
268 }
269 }
270
271 void gen8_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
272 {
273 bdw_update_pm_irq(dev_priv, mask, mask);
274 }
275
276 void gen8_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
277 {
278 bdw_update_pm_irq(dev_priv, mask, 0);
279 }
280
281 /**
282 * ibx_display_interrupt_update - update SDEIMR
283 * @dev_priv: driver private
284 * @interrupt_mask: mask of interrupt bits to update
285 * @enabled_irq_mask: mask of interrupt bits to enable
286 */
287 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
288 uint32_t interrupt_mask,
289 uint32_t enabled_irq_mask)
290 {
291 uint32_t sdeimr = I915_READ(SDEIMR);
292 sdeimr &= ~interrupt_mask;
293 sdeimr |= (~enabled_irq_mask & interrupt_mask);
294
295 assert_spin_locked(&dev_priv->irq_lock);
296
297 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
298 return;
299
300 I915_WRITE(SDEIMR, sdeimr);
301 POSTING_READ(SDEIMR);
302 }
303
304 static void
305 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
306 u32 enable_mask, u32 status_mask)
307 {
308 u32 reg = PIPESTAT(pipe);
309 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
310
311 assert_spin_locked(&dev_priv->irq_lock);
312 WARN_ON(!intel_irqs_enabled(dev_priv));
313
314 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
315 status_mask & ~PIPESTAT_INT_STATUS_MASK,
316 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
317 pipe_name(pipe), enable_mask, status_mask))
318 return;
319
320 if ((pipestat & enable_mask) == enable_mask)
321 return;
322
323 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
324
325 /* Enable the interrupt, clear any pending status */
326 pipestat |= enable_mask | status_mask;
327 I915_WRITE(reg, pipestat);
328 POSTING_READ(reg);
329 }
330
331 static void
332 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
333 u32 enable_mask, u32 status_mask)
334 {
335 u32 reg = PIPESTAT(pipe);
336 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
337
338 assert_spin_locked(&dev_priv->irq_lock);
339 WARN_ON(!intel_irqs_enabled(dev_priv));
340
341 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
342 status_mask & ~PIPESTAT_INT_STATUS_MASK,
343 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
344 pipe_name(pipe), enable_mask, status_mask))
345 return;
346
347 if ((pipestat & enable_mask) == 0)
348 return;
349
350 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
351
352 pipestat &= ~enable_mask;
353 I915_WRITE(reg, pipestat);
354 POSTING_READ(reg);
355 }
356
357 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
358 {
359 u32 enable_mask = status_mask << 16;
360
361 /*
362 * On pipe A we don't support the PSR interrupt yet,
363 * on pipe B and C the same bit MBZ.
364 */
365 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
366 return 0;
367 /*
368 * On pipe B and C we don't support the PSR interrupt yet, on pipe
369 * A the same bit is for perf counters which we don't use either.
370 */
371 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
372 return 0;
373
374 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
375 SPRITE0_FLIP_DONE_INT_EN_VLV |
376 SPRITE1_FLIP_DONE_INT_EN_VLV);
377 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
378 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
379 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
380 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
381
382 return enable_mask;
383 }
384
385 void
386 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
387 u32 status_mask)
388 {
389 u32 enable_mask;
390
391 if (IS_VALLEYVIEW(dev_priv->dev))
392 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
393 status_mask);
394 else
395 enable_mask = status_mask << 16;
396 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
397 }
398
399 void
400 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
401 u32 status_mask)
402 {
403 u32 enable_mask;
404
405 if (IS_VALLEYVIEW(dev_priv->dev))
406 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
407 status_mask);
408 else
409 enable_mask = status_mask << 16;
410 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
411 }
412
413 /**
414 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
415 */
416 static void i915_enable_asle_pipestat(struct drm_device *dev)
417 {
418 struct drm_i915_private *dev_priv = dev->dev_private;
419
420 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
421 return;
422
423 spin_lock_irq(&dev_priv->irq_lock);
424
425 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
426 if (INTEL_INFO(dev)->gen >= 4)
427 i915_enable_pipestat(dev_priv, PIPE_A,
428 PIPE_LEGACY_BLC_EVENT_STATUS);
429
430 spin_unlock_irq(&dev_priv->irq_lock);
431 }
432
433 /**
434 * i915_pipe_enabled - check if a pipe is enabled
435 * @dev: DRM device
436 * @pipe: pipe to check
437 *
438 * Reading certain registers when the pipe is disabled can hang the chip.
439 * Use this routine to make sure the PLL is running and the pipe is active
440 * before reading such registers if unsure.
441 */
442 static int
443 i915_pipe_enabled(struct drm_device *dev, int pipe)
444 {
445 struct drm_i915_private *dev_priv = dev->dev_private;
446
447 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
448 /* Locking is horribly broken here, but whatever. */
449 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
450 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
451
452 return intel_crtc->active;
453 } else {
454 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
455 }
456 }
457
458 /*
459 * This timing diagram depicts the video signal in and
460 * around the vertical blanking period.
461 *
462 * Assumptions about the fictitious mode used in this example:
463 * vblank_start >= 3
464 * vsync_start = vblank_start + 1
465 * vsync_end = vblank_start + 2
466 * vtotal = vblank_start + 3
467 *
468 * start of vblank:
469 * latch double buffered registers
470 * increment frame counter (ctg+)
471 * generate start of vblank interrupt (gen4+)
472 * |
473 * | frame start:
474 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
475 * | may be shifted forward 1-3 extra lines via PIPECONF
476 * | |
477 * | | start of vsync:
478 * | | generate vsync interrupt
479 * | | |
480 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
481 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
482 * ----va---> <-----------------vb--------------------> <--------va-------------
483 * | | <----vs-----> |
484 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
485 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
486 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
487 * | | |
488 * last visible pixel first visible pixel
489 * | increment frame counter (gen3/4)
490 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
491 *
492 * x = horizontal active
493 * _ = horizontal blanking
494 * hs = horizontal sync
495 * va = vertical active
496 * vb = vertical blanking
497 * vs = vertical sync
498 * vbs = vblank_start (number)
499 *
500 * Summary:
501 * - most events happen at the start of horizontal sync
502 * - frame start happens at the start of horizontal blank, 1-4 lines
503 * (depending on PIPECONF settings) after the start of vblank
504 * - gen3/4 pixel and frame counter are synchronized with the start
505 * of horizontal active on the first line of vertical active
506 */
507
508 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
509 {
510 /* Gen2 doesn't have a hardware frame counter */
511 return 0;
512 }
513
514 /* Called from drm generic code, passed a 'crtc', which
515 * we use as a pipe index
516 */
517 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
518 {
519 struct drm_i915_private *dev_priv = dev->dev_private;
520 unsigned long high_frame;
521 unsigned long low_frame;
522 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
523
524 if (!i915_pipe_enabled(dev, pipe)) {
525 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
526 "pipe %c\n", pipe_name(pipe));
527 return 0;
528 }
529
530 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
531 struct intel_crtc *intel_crtc =
532 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
533 const struct drm_display_mode *mode =
534 &intel_crtc->config.adjusted_mode;
535
536 htotal = mode->crtc_htotal;
537 hsync_start = mode->crtc_hsync_start;
538 vbl_start = mode->crtc_vblank_start;
539 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
540 vbl_start = DIV_ROUND_UP(vbl_start, 2);
541 } else {
542 enum transcoder cpu_transcoder = (enum transcoder) pipe;
543
544 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
545 hsync_start = (I915_READ(HSYNC(cpu_transcoder)) & 0x1fff) + 1;
546 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
547 if ((I915_READ(PIPECONF(cpu_transcoder)) &
548 PIPECONF_INTERLACE_MASK) != PIPECONF_PROGRESSIVE)
549 vbl_start = DIV_ROUND_UP(vbl_start, 2);
550 }
551
552 /* Convert to pixel count */
553 vbl_start *= htotal;
554
555 /* Start of vblank event occurs at start of hsync */
556 vbl_start -= htotal - hsync_start;
557
558 high_frame = PIPEFRAME(pipe);
559 low_frame = PIPEFRAMEPIXEL(pipe);
560
561 /*
562 * High & low register fields aren't synchronized, so make sure
563 * we get a low value that's stable across two reads of the high
564 * register.
565 */
566 do {
567 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
568 low = I915_READ(low_frame);
569 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
570 } while (high1 != high2);
571
572 high1 >>= PIPE_FRAME_HIGH_SHIFT;
573 pixel = low & PIPE_PIXEL_MASK;
574 low >>= PIPE_FRAME_LOW_SHIFT;
575
576 /*
577 * The frame counter increments at beginning of active.
578 * Cook up a vblank counter by also checking the pixel
579 * counter against vblank start.
580 */
581 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
582 }
583
584 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
585 {
586 struct drm_i915_private *dev_priv = dev->dev_private;
587 int reg = PIPE_FRMCOUNT_GM45(pipe);
588
589 if (!i915_pipe_enabled(dev, pipe)) {
590 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
591 "pipe %c\n", pipe_name(pipe));
592 return 0;
593 }
594
595 return I915_READ(reg);
596 }
597
598 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
599 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
600
601 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
602 {
603 struct drm_device *dev = crtc->base.dev;
604 struct drm_i915_private *dev_priv = dev->dev_private;
605 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
606 enum pipe pipe = crtc->pipe;
607 int position, vtotal;
608
609 vtotal = mode->crtc_vtotal;
610 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
611 vtotal /= 2;
612
613 if (IS_GEN2(dev))
614 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
615 else
616 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
617
618 /*
619 * See update_scanline_offset() for the details on the
620 * scanline_offset adjustment.
621 */
622 return (position + crtc->scanline_offset) % vtotal;
623 }
624
625 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
626 unsigned int flags, int *vpos, int *hpos,
627 ktime_t *stime, ktime_t *etime)
628 {
629 struct drm_i915_private *dev_priv = dev->dev_private;
630 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
631 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
632 const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
633 int position;
634 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
635 bool in_vbl = true;
636 int ret = 0;
637 unsigned long irqflags;
638
639 if (!intel_crtc->active) {
640 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
641 "pipe %c\n", pipe_name(pipe));
642 return 0;
643 }
644
645 htotal = mode->crtc_htotal;
646 hsync_start = mode->crtc_hsync_start;
647 vtotal = mode->crtc_vtotal;
648 vbl_start = mode->crtc_vblank_start;
649 vbl_end = mode->crtc_vblank_end;
650
651 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
652 vbl_start = DIV_ROUND_UP(vbl_start, 2);
653 vbl_end /= 2;
654 vtotal /= 2;
655 }
656
657 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
658
659 /*
660 * Lock uncore.lock, as we will do multiple timing critical raw
661 * register reads, potentially with preemption disabled, so the
662 * following code must not block on uncore.lock.
663 */
664 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
665
666 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
667
668 /* Get optional system timestamp before query. */
669 if (stime)
670 *stime = ktime_get();
671
672 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
673 /* No obvious pixelcount register. Only query vertical
674 * scanout position from Display scan line register.
675 */
676 position = __intel_get_crtc_scanline(intel_crtc);
677 } else {
678 /* Have access to pixelcount since start of frame.
679 * We can split this into vertical and horizontal
680 * scanout position.
681 */
682 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
683
684 /* convert to pixel counts */
685 vbl_start *= htotal;
686 vbl_end *= htotal;
687 vtotal *= htotal;
688
689 /*
690 * In interlaced modes, the pixel counter counts all pixels,
691 * so one field will have htotal more pixels. In order to avoid
692 * the reported position from jumping backwards when the pixel
693 * counter is beyond the length of the shorter field, just
694 * clamp the position the length of the shorter field. This
695 * matches how the scanline counter based position works since
696 * the scanline counter doesn't count the two half lines.
697 */
698 if (position >= vtotal)
699 position = vtotal - 1;
700
701 /*
702 * Start of vblank interrupt is triggered at start of hsync,
703 * just prior to the first active line of vblank. However we
704 * consider lines to start at the leading edge of horizontal
705 * active. So, should we get here before we've crossed into
706 * the horizontal active of the first line in vblank, we would
707 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
708 * always add htotal-hsync_start to the current pixel position.
709 */
710 position = (position + htotal - hsync_start) % vtotal;
711 }
712
713 /* Get optional system timestamp after query. */
714 if (etime)
715 *etime = ktime_get();
716
717 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
718
719 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
720
721 in_vbl = position >= vbl_start && position < vbl_end;
722
723 /*
724 * While in vblank, position will be negative
725 * counting up towards 0 at vbl_end. And outside
726 * vblank, position will be positive counting
727 * up since vbl_end.
728 */
729 if (position >= vbl_start)
730 position -= vbl_end;
731 else
732 position += vtotal - vbl_end;
733
734 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
735 *vpos = position;
736 *hpos = 0;
737 } else {
738 *vpos = position / htotal;
739 *hpos = position - (*vpos * htotal);
740 }
741
742 /* In vblank? */
743 if (in_vbl)
744 ret |= DRM_SCANOUTPOS_IN_VBLANK;
745
746 return ret;
747 }
748
749 int intel_get_crtc_scanline(struct intel_crtc *crtc)
750 {
751 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
752 unsigned long irqflags;
753 int position;
754
755 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
756 position = __intel_get_crtc_scanline(crtc);
757 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
758
759 return position;
760 }
761
762 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
763 int *max_error,
764 struct timeval *vblank_time,
765 unsigned flags)
766 {
767 struct drm_crtc *crtc;
768
769 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
770 DRM_ERROR("Invalid crtc %d\n", pipe);
771 return -EINVAL;
772 }
773
774 /* Get drm_crtc to timestamp: */
775 crtc = intel_get_crtc_for_pipe(dev, pipe);
776 if (crtc == NULL) {
777 DRM_ERROR("Invalid crtc %d\n", pipe);
778 return -EINVAL;
779 }
780
781 if (!crtc->enabled) {
782 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
783 return -EBUSY;
784 }
785
786 /* Helper routine in DRM core does all the work: */
787 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
788 vblank_time, flags,
789 crtc,
790 &to_intel_crtc(crtc)->config.adjusted_mode);
791 }
792
793 static bool intel_hpd_irq_event(struct drm_device *dev,
794 struct drm_connector *connector)
795 {
796 enum drm_connector_status old_status;
797
798 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
799 old_status = connector->status;
800
801 connector->status = connector->funcs->detect(connector, false);
802 if (old_status == connector->status)
803 return false;
804
805 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
806 connector->base.id,
807 connector->name,
808 drm_get_connector_status_name(old_status),
809 drm_get_connector_status_name(connector->status));
810
811 return true;
812 }
813
814 static void i915_digport_work_func(struct work_struct *work)
815 {
816 struct drm_i915_private *dev_priv =
817 container_of(work, struct drm_i915_private, dig_port_work);
818 u32 long_port_mask, short_port_mask;
819 struct intel_digital_port *intel_dig_port;
820 int i, ret;
821 u32 old_bits = 0;
822
823 spin_lock_irq(&dev_priv->irq_lock);
824 long_port_mask = dev_priv->long_hpd_port_mask;
825 dev_priv->long_hpd_port_mask = 0;
826 short_port_mask = dev_priv->short_hpd_port_mask;
827 dev_priv->short_hpd_port_mask = 0;
828 spin_unlock_irq(&dev_priv->irq_lock);
829
830 for (i = 0; i < I915_MAX_PORTS; i++) {
831 bool valid = false;
832 bool long_hpd = false;
833 intel_dig_port = dev_priv->hpd_irq_port[i];
834 if (!intel_dig_port || !intel_dig_port->hpd_pulse)
835 continue;
836
837 if (long_port_mask & (1 << i)) {
838 valid = true;
839 long_hpd = true;
840 } else if (short_port_mask & (1 << i))
841 valid = true;
842
843 if (valid) {
844 ret = intel_dig_port->hpd_pulse(intel_dig_port, long_hpd);
845 if (ret == true) {
846 /* if we get true fallback to old school hpd */
847 old_bits |= (1 << intel_dig_port->base.hpd_pin);
848 }
849 }
850 }
851
852 if (old_bits) {
853 spin_lock_irq(&dev_priv->irq_lock);
854 dev_priv->hpd_event_bits |= old_bits;
855 spin_unlock_irq(&dev_priv->irq_lock);
856 schedule_work(&dev_priv->hotplug_work);
857 }
858 }
859
860 /*
861 * Handle hotplug events outside the interrupt handler proper.
862 */
863 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
864
865 static void i915_hotplug_work_func(struct work_struct *work)
866 {
867 struct drm_i915_private *dev_priv =
868 container_of(work, struct drm_i915_private, hotplug_work);
869 struct drm_device *dev = dev_priv->dev;
870 struct drm_mode_config *mode_config = &dev->mode_config;
871 struct intel_connector *intel_connector;
872 struct intel_encoder *intel_encoder;
873 struct drm_connector *connector;
874 bool hpd_disabled = false;
875 bool changed = false;
876 u32 hpd_event_bits;
877
878 mutex_lock(&mode_config->mutex);
879 DRM_DEBUG_KMS("running encoder hotplug functions\n");
880
881 spin_lock_irq(&dev_priv->irq_lock);
882
883 hpd_event_bits = dev_priv->hpd_event_bits;
884 dev_priv->hpd_event_bits = 0;
885 list_for_each_entry(connector, &mode_config->connector_list, head) {
886 intel_connector = to_intel_connector(connector);
887 if (!intel_connector->encoder)
888 continue;
889 intel_encoder = intel_connector->encoder;
890 if (intel_encoder->hpd_pin > HPD_NONE &&
891 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
892 connector->polled == DRM_CONNECTOR_POLL_HPD) {
893 DRM_INFO("HPD interrupt storm detected on connector %s: "
894 "switching from hotplug detection to polling\n",
895 connector->name);
896 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
897 connector->polled = DRM_CONNECTOR_POLL_CONNECT
898 | DRM_CONNECTOR_POLL_DISCONNECT;
899 hpd_disabled = true;
900 }
901 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
902 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
903 connector->name, intel_encoder->hpd_pin);
904 }
905 }
906 /* if there were no outputs to poll, poll was disabled,
907 * therefore make sure it's enabled when disabling HPD on
908 * some connectors */
909 if (hpd_disabled) {
910 drm_kms_helper_poll_enable(dev);
911 mod_delayed_work(system_wq, &dev_priv->hotplug_reenable_work,
912 msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
913 }
914
915 spin_unlock_irq(&dev_priv->irq_lock);
916
917 list_for_each_entry(connector, &mode_config->connector_list, head) {
918 intel_connector = to_intel_connector(connector);
919 if (!intel_connector->encoder)
920 continue;
921 intel_encoder = intel_connector->encoder;
922 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
923 if (intel_encoder->hot_plug)
924 intel_encoder->hot_plug(intel_encoder);
925 if (intel_hpd_irq_event(dev, connector))
926 changed = true;
927 }
928 }
929 mutex_unlock(&mode_config->mutex);
930
931 if (changed)
932 drm_kms_helper_hotplug_event(dev);
933 }
934
935 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
936 {
937 struct drm_i915_private *dev_priv = dev->dev_private;
938 u32 busy_up, busy_down, max_avg, min_avg;
939 u8 new_delay;
940
941 spin_lock(&mchdev_lock);
942
943 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
944
945 new_delay = dev_priv->ips.cur_delay;
946
947 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
948 busy_up = I915_READ(RCPREVBSYTUPAVG);
949 busy_down = I915_READ(RCPREVBSYTDNAVG);
950 max_avg = I915_READ(RCBMAXAVG);
951 min_avg = I915_READ(RCBMINAVG);
952
953 /* Handle RCS change request from hw */
954 if (busy_up > max_avg) {
955 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
956 new_delay = dev_priv->ips.cur_delay - 1;
957 if (new_delay < dev_priv->ips.max_delay)
958 new_delay = dev_priv->ips.max_delay;
959 } else if (busy_down < min_avg) {
960 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
961 new_delay = dev_priv->ips.cur_delay + 1;
962 if (new_delay > dev_priv->ips.min_delay)
963 new_delay = dev_priv->ips.min_delay;
964 }
965
966 if (ironlake_set_drps(dev, new_delay))
967 dev_priv->ips.cur_delay = new_delay;
968
969 spin_unlock(&mchdev_lock);
970
971 return;
972 }
973
974 static void notify_ring(struct drm_device *dev,
975 struct intel_engine_cs *ring)
976 {
977 if (!intel_ring_initialized(ring))
978 return;
979
980 trace_i915_gem_request_complete(ring);
981
982 if (drm_core_check_feature(dev, DRIVER_MODESET))
983 intel_notify_mmio_flip(ring);
984
985 wake_up_all(&ring->irq_queue);
986 i915_queue_hangcheck(dev);
987 }
988
989 static u32 vlv_c0_residency(struct drm_i915_private *dev_priv,
990 struct intel_rps_ei *rps_ei)
991 {
992 u32 cz_ts, cz_freq_khz;
993 u32 render_count, media_count;
994 u32 elapsed_render, elapsed_media, elapsed_time;
995 u32 residency = 0;
996
997 cz_ts = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
998 cz_freq_khz = DIV_ROUND_CLOSEST(dev_priv->mem_freq * 1000, 4);
999
1000 render_count = I915_READ(VLV_RENDER_C0_COUNT_REG);
1001 media_count = I915_READ(VLV_MEDIA_C0_COUNT_REG);
1002
1003 if (rps_ei->cz_clock == 0) {
1004 rps_ei->cz_clock = cz_ts;
1005 rps_ei->render_c0 = render_count;
1006 rps_ei->media_c0 = media_count;
1007
1008 return dev_priv->rps.cur_freq;
1009 }
1010
1011 elapsed_time = cz_ts - rps_ei->cz_clock;
1012 rps_ei->cz_clock = cz_ts;
1013
1014 elapsed_render = render_count - rps_ei->render_c0;
1015 rps_ei->render_c0 = render_count;
1016
1017 elapsed_media = media_count - rps_ei->media_c0;
1018 rps_ei->media_c0 = media_count;
1019
1020 /* Convert all the counters into common unit of milli sec */
1021 elapsed_time /= VLV_CZ_CLOCK_TO_MILLI_SEC;
1022 elapsed_render /= cz_freq_khz;
1023 elapsed_media /= cz_freq_khz;
1024
1025 /*
1026 * Calculate overall C0 residency percentage
1027 * only if elapsed time is non zero
1028 */
1029 if (elapsed_time) {
1030 residency =
1031 ((max(elapsed_render, elapsed_media) * 100)
1032 / elapsed_time);
1033 }
1034
1035 return residency;
1036 }
1037
1038 /**
1039 * vlv_calc_delay_from_C0_counters - Increase/Decrease freq based on GPU
1040 * busy-ness calculated from C0 counters of render & media power wells
1041 * @dev_priv: DRM device private
1042 *
1043 */
1044 static int vlv_calc_delay_from_C0_counters(struct drm_i915_private *dev_priv)
1045 {
1046 u32 residency_C0_up = 0, residency_C0_down = 0;
1047 int new_delay, adj;
1048
1049 dev_priv->rps.ei_interrupt_count++;
1050
1051 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
1052
1053
1054 if (dev_priv->rps.up_ei.cz_clock == 0) {
1055 vlv_c0_residency(dev_priv, &dev_priv->rps.up_ei);
1056 vlv_c0_residency(dev_priv, &dev_priv->rps.down_ei);
1057 return dev_priv->rps.cur_freq;
1058 }
1059
1060
1061 /*
1062 * To down throttle, C0 residency should be less than down threshold
1063 * for continous EI intervals. So calculate down EI counters
1064 * once in VLV_INT_COUNT_FOR_DOWN_EI
1065 */
1066 if (dev_priv->rps.ei_interrupt_count == VLV_INT_COUNT_FOR_DOWN_EI) {
1067
1068 dev_priv->rps.ei_interrupt_count = 0;
1069
1070 residency_C0_down = vlv_c0_residency(dev_priv,
1071 &dev_priv->rps.down_ei);
1072 } else {
1073 residency_C0_up = vlv_c0_residency(dev_priv,
1074 &dev_priv->rps.up_ei);
1075 }
1076
1077 new_delay = dev_priv->rps.cur_freq;
1078
1079 adj = dev_priv->rps.last_adj;
1080 /* C0 residency is greater than UP threshold. Increase Frequency */
1081 if (residency_C0_up >= VLV_RP_UP_EI_THRESHOLD) {
1082 if (adj > 0)
1083 adj *= 2;
1084 else
1085 adj = 1;
1086
1087 if (dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit)
1088 new_delay = dev_priv->rps.cur_freq + adj;
1089
1090 /*
1091 * For better performance, jump directly
1092 * to RPe if we're below it.
1093 */
1094 if (new_delay < dev_priv->rps.efficient_freq)
1095 new_delay = dev_priv->rps.efficient_freq;
1096
1097 } else if (!dev_priv->rps.ei_interrupt_count &&
1098 (residency_C0_down < VLV_RP_DOWN_EI_THRESHOLD)) {
1099 if (adj < 0)
1100 adj *= 2;
1101 else
1102 adj = -1;
1103 /*
1104 * This means, C0 residency is less than down threshold over
1105 * a period of VLV_INT_COUNT_FOR_DOWN_EI. So, reduce the freq
1106 */
1107 if (dev_priv->rps.cur_freq > dev_priv->rps.min_freq_softlimit)
1108 new_delay = dev_priv->rps.cur_freq + adj;
1109 }
1110
1111 return new_delay;
1112 }
1113
1114 static void gen6_pm_rps_work(struct work_struct *work)
1115 {
1116 struct drm_i915_private *dev_priv =
1117 container_of(work, struct drm_i915_private, rps.work);
1118 u32 pm_iir;
1119 int new_delay, adj;
1120
1121 spin_lock_irq(&dev_priv->irq_lock);
1122 pm_iir = dev_priv->rps.pm_iir;
1123 dev_priv->rps.pm_iir = 0;
1124 if (INTEL_INFO(dev_priv->dev)->gen >= 8)
1125 gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1126 else {
1127 /* Make sure not to corrupt PMIMR state used by ringbuffer */
1128 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1129 }
1130 spin_unlock_irq(&dev_priv->irq_lock);
1131
1132 /* Make sure we didn't queue anything we're not going to process. */
1133 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1134
1135 if ((pm_iir & dev_priv->pm_rps_events) == 0)
1136 return;
1137
1138 mutex_lock(&dev_priv->rps.hw_lock);
1139
1140 adj = dev_priv->rps.last_adj;
1141 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1142 if (adj > 0)
1143 adj *= 2;
1144 else {
1145 /* CHV needs even encode values */
1146 adj = IS_CHERRYVIEW(dev_priv->dev) ? 2 : 1;
1147 }
1148 new_delay = dev_priv->rps.cur_freq + adj;
1149
1150 /*
1151 * For better performance, jump directly
1152 * to RPe if we're below it.
1153 */
1154 if (new_delay < dev_priv->rps.efficient_freq)
1155 new_delay = dev_priv->rps.efficient_freq;
1156 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1157 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1158 new_delay = dev_priv->rps.efficient_freq;
1159 else
1160 new_delay = dev_priv->rps.min_freq_softlimit;
1161 adj = 0;
1162 } else if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1163 new_delay = vlv_calc_delay_from_C0_counters(dev_priv);
1164 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1165 if (adj < 0)
1166 adj *= 2;
1167 else {
1168 /* CHV needs even encode values */
1169 adj = IS_CHERRYVIEW(dev_priv->dev) ? -2 : -1;
1170 }
1171 new_delay = dev_priv->rps.cur_freq + adj;
1172 } else { /* unknown event */
1173 new_delay = dev_priv->rps.cur_freq;
1174 }
1175
1176 /* sysfs frequency interfaces may have snuck in while servicing the
1177 * interrupt
1178 */
1179 new_delay = clamp_t(int, new_delay,
1180 dev_priv->rps.min_freq_softlimit,
1181 dev_priv->rps.max_freq_softlimit);
1182
1183 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq;
1184
1185 if (IS_VALLEYVIEW(dev_priv->dev))
1186 valleyview_set_rps(dev_priv->dev, new_delay);
1187 else
1188 gen6_set_rps(dev_priv->dev, new_delay);
1189
1190 mutex_unlock(&dev_priv->rps.hw_lock);
1191 }
1192
1193
1194 /**
1195 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1196 * occurred.
1197 * @work: workqueue struct
1198 *
1199 * Doesn't actually do anything except notify userspace. As a consequence of
1200 * this event, userspace should try to remap the bad rows since statistically
1201 * it is likely the same row is more likely to go bad again.
1202 */
1203 static void ivybridge_parity_work(struct work_struct *work)
1204 {
1205 struct drm_i915_private *dev_priv =
1206 container_of(work, struct drm_i915_private, l3_parity.error_work);
1207 u32 error_status, row, bank, subbank;
1208 char *parity_event[6];
1209 uint32_t misccpctl;
1210 uint8_t slice = 0;
1211
1212 /* We must turn off DOP level clock gating to access the L3 registers.
1213 * In order to prevent a get/put style interface, acquire struct mutex
1214 * any time we access those registers.
1215 */
1216 mutex_lock(&dev_priv->dev->struct_mutex);
1217
1218 /* If we've screwed up tracking, just let the interrupt fire again */
1219 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1220 goto out;
1221
1222 misccpctl = I915_READ(GEN7_MISCCPCTL);
1223 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1224 POSTING_READ(GEN7_MISCCPCTL);
1225
1226 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1227 u32 reg;
1228
1229 slice--;
1230 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1231 break;
1232
1233 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1234
1235 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1236
1237 error_status = I915_READ(reg);
1238 row = GEN7_PARITY_ERROR_ROW(error_status);
1239 bank = GEN7_PARITY_ERROR_BANK(error_status);
1240 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1241
1242 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1243 POSTING_READ(reg);
1244
1245 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1246 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1247 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1248 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1249 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1250 parity_event[5] = NULL;
1251
1252 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1253 KOBJ_CHANGE, parity_event);
1254
1255 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1256 slice, row, bank, subbank);
1257
1258 kfree(parity_event[4]);
1259 kfree(parity_event[3]);
1260 kfree(parity_event[2]);
1261 kfree(parity_event[1]);
1262 }
1263
1264 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1265
1266 out:
1267 WARN_ON(dev_priv->l3_parity.which_slice);
1268 spin_lock_irq(&dev_priv->irq_lock);
1269 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1270 spin_unlock_irq(&dev_priv->irq_lock);
1271
1272 mutex_unlock(&dev_priv->dev->struct_mutex);
1273 }
1274
1275 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1276 {
1277 struct drm_i915_private *dev_priv = dev->dev_private;
1278
1279 if (!HAS_L3_DPF(dev))
1280 return;
1281
1282 spin_lock(&dev_priv->irq_lock);
1283 gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1284 spin_unlock(&dev_priv->irq_lock);
1285
1286 iir &= GT_PARITY_ERROR(dev);
1287 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1288 dev_priv->l3_parity.which_slice |= 1 << 1;
1289
1290 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1291 dev_priv->l3_parity.which_slice |= 1 << 0;
1292
1293 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1294 }
1295
1296 static void ilk_gt_irq_handler(struct drm_device *dev,
1297 struct drm_i915_private *dev_priv,
1298 u32 gt_iir)
1299 {
1300 if (gt_iir &
1301 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1302 notify_ring(dev, &dev_priv->ring[RCS]);
1303 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1304 notify_ring(dev, &dev_priv->ring[VCS]);
1305 }
1306
1307 static void snb_gt_irq_handler(struct drm_device *dev,
1308 struct drm_i915_private *dev_priv,
1309 u32 gt_iir)
1310 {
1311
1312 if (gt_iir &
1313 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1314 notify_ring(dev, &dev_priv->ring[RCS]);
1315 if (gt_iir & GT_BSD_USER_INTERRUPT)
1316 notify_ring(dev, &dev_priv->ring[VCS]);
1317 if (gt_iir & GT_BLT_USER_INTERRUPT)
1318 notify_ring(dev, &dev_priv->ring[BCS]);
1319
1320 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1321 GT_BSD_CS_ERROR_INTERRUPT |
1322 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
1323 i915_handle_error(dev, false, "GT error interrupt 0x%08x",
1324 gt_iir);
1325 }
1326
1327 if (gt_iir & GT_PARITY_ERROR(dev))
1328 ivybridge_parity_error_irq_handler(dev, gt_iir);
1329 }
1330
1331 static void gen8_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1332 {
1333 if ((pm_iir & dev_priv->pm_rps_events) == 0)
1334 return;
1335
1336 spin_lock(&dev_priv->irq_lock);
1337 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1338 gen8_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1339 spin_unlock(&dev_priv->irq_lock);
1340
1341 queue_work(dev_priv->wq, &dev_priv->rps.work);
1342 }
1343
1344 static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1345 struct drm_i915_private *dev_priv,
1346 u32 master_ctl)
1347 {
1348 struct intel_engine_cs *ring;
1349 u32 rcs, bcs, vcs;
1350 uint32_t tmp = 0;
1351 irqreturn_t ret = IRQ_NONE;
1352
1353 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1354 tmp = I915_READ(GEN8_GT_IIR(0));
1355 if (tmp) {
1356 I915_WRITE(GEN8_GT_IIR(0), tmp);
1357 ret = IRQ_HANDLED;
1358
1359 rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1360 ring = &dev_priv->ring[RCS];
1361 if (rcs & GT_RENDER_USER_INTERRUPT)
1362 notify_ring(dev, ring);
1363 if (rcs & GT_CONTEXT_SWITCH_INTERRUPT)
1364 intel_execlists_handle_ctx_events(ring);
1365
1366 bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1367 ring = &dev_priv->ring[BCS];
1368 if (bcs & GT_RENDER_USER_INTERRUPT)
1369 notify_ring(dev, ring);
1370 if (bcs & GT_CONTEXT_SWITCH_INTERRUPT)
1371 intel_execlists_handle_ctx_events(ring);
1372 } else
1373 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1374 }
1375
1376 if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1377 tmp = I915_READ(GEN8_GT_IIR(1));
1378 if (tmp) {
1379 I915_WRITE(GEN8_GT_IIR(1), tmp);
1380 ret = IRQ_HANDLED;
1381
1382 vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1383 ring = &dev_priv->ring[VCS];
1384 if (vcs & GT_RENDER_USER_INTERRUPT)
1385 notify_ring(dev, ring);
1386 if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1387 intel_execlists_handle_ctx_events(ring);
1388
1389 vcs = tmp >> GEN8_VCS2_IRQ_SHIFT;
1390 ring = &dev_priv->ring[VCS2];
1391 if (vcs & GT_RENDER_USER_INTERRUPT)
1392 notify_ring(dev, ring);
1393 if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1394 intel_execlists_handle_ctx_events(ring);
1395 } else
1396 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1397 }
1398
1399 if (master_ctl & GEN8_GT_PM_IRQ) {
1400 tmp = I915_READ(GEN8_GT_IIR(2));
1401 if (tmp & dev_priv->pm_rps_events) {
1402 I915_WRITE(GEN8_GT_IIR(2),
1403 tmp & dev_priv->pm_rps_events);
1404 ret = IRQ_HANDLED;
1405 gen8_rps_irq_handler(dev_priv, tmp);
1406 } else
1407 DRM_ERROR("The master control interrupt lied (PM)!\n");
1408 }
1409
1410 if (master_ctl & GEN8_GT_VECS_IRQ) {
1411 tmp = I915_READ(GEN8_GT_IIR(3));
1412 if (tmp) {
1413 I915_WRITE(GEN8_GT_IIR(3), tmp);
1414 ret = IRQ_HANDLED;
1415
1416 vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1417 ring = &dev_priv->ring[VECS];
1418 if (vcs & GT_RENDER_USER_INTERRUPT)
1419 notify_ring(dev, ring);
1420 if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1421 intel_execlists_handle_ctx_events(ring);
1422 } else
1423 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1424 }
1425
1426 return ret;
1427 }
1428
1429 #define HPD_STORM_DETECT_PERIOD 1000
1430 #define HPD_STORM_THRESHOLD 5
1431
1432 static int pch_port_to_hotplug_shift(enum port port)
1433 {
1434 switch (port) {
1435 case PORT_A:
1436 case PORT_E:
1437 default:
1438 return -1;
1439 case PORT_B:
1440 return 0;
1441 case PORT_C:
1442 return 8;
1443 case PORT_D:
1444 return 16;
1445 }
1446 }
1447
1448 static int i915_port_to_hotplug_shift(enum port port)
1449 {
1450 switch (port) {
1451 case PORT_A:
1452 case PORT_E:
1453 default:
1454 return -1;
1455 case PORT_B:
1456 return 17;
1457 case PORT_C:
1458 return 19;
1459 case PORT_D:
1460 return 21;
1461 }
1462 }
1463
1464 static inline enum port get_port_from_pin(enum hpd_pin pin)
1465 {
1466 switch (pin) {
1467 case HPD_PORT_B:
1468 return PORT_B;
1469 case HPD_PORT_C:
1470 return PORT_C;
1471 case HPD_PORT_D:
1472 return PORT_D;
1473 default:
1474 return PORT_A; /* no hpd */
1475 }
1476 }
1477
1478 static inline void intel_hpd_irq_handler(struct drm_device *dev,
1479 u32 hotplug_trigger,
1480 u32 dig_hotplug_reg,
1481 const u32 *hpd)
1482 {
1483 struct drm_i915_private *dev_priv = dev->dev_private;
1484 int i;
1485 enum port port;
1486 bool storm_detected = false;
1487 bool queue_dig = false, queue_hp = false;
1488 u32 dig_shift;
1489 u32 dig_port_mask = 0;
1490
1491 if (!hotplug_trigger)
1492 return;
1493
1494 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x\n",
1495 hotplug_trigger, dig_hotplug_reg);
1496
1497 spin_lock(&dev_priv->irq_lock);
1498 for (i = 1; i < HPD_NUM_PINS; i++) {
1499 if (!(hpd[i] & hotplug_trigger))
1500 continue;
1501
1502 port = get_port_from_pin(i);
1503 if (port && dev_priv->hpd_irq_port[port]) {
1504 bool long_hpd;
1505
1506 if (HAS_PCH_SPLIT(dev)) {
1507 dig_shift = pch_port_to_hotplug_shift(port);
1508 long_hpd = (dig_hotplug_reg >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
1509 } else {
1510 dig_shift = i915_port_to_hotplug_shift(port);
1511 long_hpd = (hotplug_trigger >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
1512 }
1513
1514 DRM_DEBUG_DRIVER("digital hpd port %c - %s\n",
1515 port_name(port),
1516 long_hpd ? "long" : "short");
1517 /* for long HPD pulses we want to have the digital queue happen,
1518 but we still want HPD storm detection to function. */
1519 if (long_hpd) {
1520 dev_priv->long_hpd_port_mask |= (1 << port);
1521 dig_port_mask |= hpd[i];
1522 } else {
1523 /* for short HPD just trigger the digital queue */
1524 dev_priv->short_hpd_port_mask |= (1 << port);
1525 hotplug_trigger &= ~hpd[i];
1526 }
1527 queue_dig = true;
1528 }
1529 }
1530
1531 for (i = 1; i < HPD_NUM_PINS; i++) {
1532 if (hpd[i] & hotplug_trigger &&
1533 dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) {
1534 /*
1535 * On GMCH platforms the interrupt mask bits only
1536 * prevent irq generation, not the setting of the
1537 * hotplug bits itself. So only WARN about unexpected
1538 * interrupts on saner platforms.
1539 */
1540 WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
1541 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1542 hotplug_trigger, i, hpd[i]);
1543
1544 continue;
1545 }
1546
1547 if (!(hpd[i] & hotplug_trigger) ||
1548 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1549 continue;
1550
1551 if (!(dig_port_mask & hpd[i])) {
1552 dev_priv->hpd_event_bits |= (1 << i);
1553 queue_hp = true;
1554 }
1555
1556 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1557 dev_priv->hpd_stats[i].hpd_last_jiffies
1558 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1559 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1560 dev_priv->hpd_stats[i].hpd_cnt = 0;
1561 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1562 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1563 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1564 dev_priv->hpd_event_bits &= ~(1 << i);
1565 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1566 storm_detected = true;
1567 } else {
1568 dev_priv->hpd_stats[i].hpd_cnt++;
1569 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1570 dev_priv->hpd_stats[i].hpd_cnt);
1571 }
1572 }
1573
1574 if (storm_detected)
1575 dev_priv->display.hpd_irq_setup(dev);
1576 spin_unlock(&dev_priv->irq_lock);
1577
1578 /*
1579 * Our hotplug handler can grab modeset locks (by calling down into the
1580 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1581 * queue for otherwise the flush_work in the pageflip code will
1582 * deadlock.
1583 */
1584 if (queue_dig)
1585 queue_work(dev_priv->dp_wq, &dev_priv->dig_port_work);
1586 if (queue_hp)
1587 schedule_work(&dev_priv->hotplug_work);
1588 }
1589
1590 static void gmbus_irq_handler(struct drm_device *dev)
1591 {
1592 struct drm_i915_private *dev_priv = dev->dev_private;
1593
1594 wake_up_all(&dev_priv->gmbus_wait_queue);
1595 }
1596
1597 static void dp_aux_irq_handler(struct drm_device *dev)
1598 {
1599 struct drm_i915_private *dev_priv = dev->dev_private;
1600
1601 wake_up_all(&dev_priv->gmbus_wait_queue);
1602 }
1603
1604 #if defined(CONFIG_DEBUG_FS)
1605 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1606 uint32_t crc0, uint32_t crc1,
1607 uint32_t crc2, uint32_t crc3,
1608 uint32_t crc4)
1609 {
1610 struct drm_i915_private *dev_priv = dev->dev_private;
1611 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1612 struct intel_pipe_crc_entry *entry;
1613 int head, tail;
1614
1615 spin_lock(&pipe_crc->lock);
1616
1617 if (!pipe_crc->entries) {
1618 spin_unlock(&pipe_crc->lock);
1619 DRM_ERROR("spurious interrupt\n");
1620 return;
1621 }
1622
1623 head = pipe_crc->head;
1624 tail = pipe_crc->tail;
1625
1626 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1627 spin_unlock(&pipe_crc->lock);
1628 DRM_ERROR("CRC buffer overflowing\n");
1629 return;
1630 }
1631
1632 entry = &pipe_crc->entries[head];
1633
1634 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1635 entry->crc[0] = crc0;
1636 entry->crc[1] = crc1;
1637 entry->crc[2] = crc2;
1638 entry->crc[3] = crc3;
1639 entry->crc[4] = crc4;
1640
1641 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1642 pipe_crc->head = head;
1643
1644 spin_unlock(&pipe_crc->lock);
1645
1646 wake_up_interruptible(&pipe_crc->wq);
1647 }
1648 #else
1649 static inline void
1650 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1651 uint32_t crc0, uint32_t crc1,
1652 uint32_t crc2, uint32_t crc3,
1653 uint32_t crc4) {}
1654 #endif
1655
1656
1657 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1658 {
1659 struct drm_i915_private *dev_priv = dev->dev_private;
1660
1661 display_pipe_crc_irq_handler(dev, pipe,
1662 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1663 0, 0, 0, 0);
1664 }
1665
1666 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1667 {
1668 struct drm_i915_private *dev_priv = dev->dev_private;
1669
1670 display_pipe_crc_irq_handler(dev, pipe,
1671 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1672 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1673 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1674 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1675 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1676 }
1677
1678 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1679 {
1680 struct drm_i915_private *dev_priv = dev->dev_private;
1681 uint32_t res1, res2;
1682
1683 if (INTEL_INFO(dev)->gen >= 3)
1684 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1685 else
1686 res1 = 0;
1687
1688 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1689 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1690 else
1691 res2 = 0;
1692
1693 display_pipe_crc_irq_handler(dev, pipe,
1694 I915_READ(PIPE_CRC_RES_RED(pipe)),
1695 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1696 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1697 res1, res2);
1698 }
1699
1700 /* The RPS events need forcewake, so we add them to a work queue and mask their
1701 * IMR bits until the work is done. Other interrupts can be processed without
1702 * the work queue. */
1703 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1704 {
1705 if (pm_iir & dev_priv->pm_rps_events) {
1706 spin_lock(&dev_priv->irq_lock);
1707 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1708 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1709 spin_unlock(&dev_priv->irq_lock);
1710
1711 queue_work(dev_priv->wq, &dev_priv->rps.work);
1712 }
1713
1714 if (HAS_VEBOX(dev_priv->dev)) {
1715 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1716 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1717
1718 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1719 i915_handle_error(dev_priv->dev, false,
1720 "VEBOX CS error interrupt 0x%08x",
1721 pm_iir);
1722 }
1723 }
1724 }
1725
1726 static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
1727 {
1728 if (!drm_handle_vblank(dev, pipe))
1729 return false;
1730
1731 return true;
1732 }
1733
1734 static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1735 {
1736 struct drm_i915_private *dev_priv = dev->dev_private;
1737 u32 pipe_stats[I915_MAX_PIPES] = { };
1738 int pipe;
1739
1740 spin_lock(&dev_priv->irq_lock);
1741 for_each_pipe(dev_priv, pipe) {
1742 int reg;
1743 u32 mask, iir_bit = 0;
1744
1745 /*
1746 * PIPESTAT bits get signalled even when the interrupt is
1747 * disabled with the mask bits, and some of the status bits do
1748 * not generate interrupts at all (like the underrun bit). Hence
1749 * we need to be careful that we only handle what we want to
1750 * handle.
1751 */
1752
1753 /* fifo underruns are filterered in the underrun handler. */
1754 mask = PIPE_FIFO_UNDERRUN_STATUS;
1755
1756 switch (pipe) {
1757 case PIPE_A:
1758 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1759 break;
1760 case PIPE_B:
1761 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1762 break;
1763 case PIPE_C:
1764 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1765 break;
1766 }
1767 if (iir & iir_bit)
1768 mask |= dev_priv->pipestat_irq_mask[pipe];
1769
1770 if (!mask)
1771 continue;
1772
1773 reg = PIPESTAT(pipe);
1774 mask |= PIPESTAT_INT_ENABLE_MASK;
1775 pipe_stats[pipe] = I915_READ(reg) & mask;
1776
1777 /*
1778 * Clear the PIPE*STAT regs before the IIR
1779 */
1780 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1781 PIPESTAT_INT_STATUS_MASK))
1782 I915_WRITE(reg, pipe_stats[pipe]);
1783 }
1784 spin_unlock(&dev_priv->irq_lock);
1785
1786 for_each_pipe(dev_priv, pipe) {
1787 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1788 intel_pipe_handle_vblank(dev, pipe))
1789 intel_check_page_flip(dev, pipe);
1790
1791 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
1792 intel_prepare_page_flip(dev, pipe);
1793 intel_finish_page_flip(dev, pipe);
1794 }
1795
1796 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1797 i9xx_pipe_crc_irq_handler(dev, pipe);
1798
1799 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1800 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1801 }
1802
1803 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1804 gmbus_irq_handler(dev);
1805 }
1806
1807 static void i9xx_hpd_irq_handler(struct drm_device *dev)
1808 {
1809 struct drm_i915_private *dev_priv = dev->dev_private;
1810 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1811
1812 if (hotplug_status) {
1813 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1814 /*
1815 * Make sure hotplug status is cleared before we clear IIR, or else we
1816 * may miss hotplug events.
1817 */
1818 POSTING_READ(PORT_HOTPLUG_STAT);
1819
1820 if (IS_G4X(dev)) {
1821 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1822
1823 intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_g4x);
1824 } else {
1825 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1826
1827 intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_i915);
1828 }
1829
1830 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) &&
1831 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1832 dp_aux_irq_handler(dev);
1833 }
1834 }
1835
1836 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1837 {
1838 struct drm_device *dev = arg;
1839 struct drm_i915_private *dev_priv = dev->dev_private;
1840 u32 iir, gt_iir, pm_iir;
1841 irqreturn_t ret = IRQ_NONE;
1842
1843 while (true) {
1844 /* Find, clear, then process each source of interrupt */
1845
1846 gt_iir = I915_READ(GTIIR);
1847 if (gt_iir)
1848 I915_WRITE(GTIIR, gt_iir);
1849
1850 pm_iir = I915_READ(GEN6_PMIIR);
1851 if (pm_iir)
1852 I915_WRITE(GEN6_PMIIR, pm_iir);
1853
1854 iir = I915_READ(VLV_IIR);
1855 if (iir) {
1856 /* Consume port before clearing IIR or we'll miss events */
1857 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1858 i9xx_hpd_irq_handler(dev);
1859 I915_WRITE(VLV_IIR, iir);
1860 }
1861
1862 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1863 goto out;
1864
1865 ret = IRQ_HANDLED;
1866
1867 if (gt_iir)
1868 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1869 if (pm_iir)
1870 gen6_rps_irq_handler(dev_priv, pm_iir);
1871 /* Call regardless, as some status bits might not be
1872 * signalled in iir */
1873 valleyview_pipestat_irq_handler(dev, iir);
1874 }
1875
1876 out:
1877 return ret;
1878 }
1879
1880 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1881 {
1882 struct drm_device *dev = arg;
1883 struct drm_i915_private *dev_priv = dev->dev_private;
1884 u32 master_ctl, iir;
1885 irqreturn_t ret = IRQ_NONE;
1886
1887 for (;;) {
1888 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1889 iir = I915_READ(VLV_IIR);
1890
1891 if (master_ctl == 0 && iir == 0)
1892 break;
1893
1894 ret = IRQ_HANDLED;
1895
1896 I915_WRITE(GEN8_MASTER_IRQ, 0);
1897
1898 /* Find, clear, then process each source of interrupt */
1899
1900 if (iir) {
1901 /* Consume port before clearing IIR or we'll miss events */
1902 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1903 i9xx_hpd_irq_handler(dev);
1904 I915_WRITE(VLV_IIR, iir);
1905 }
1906
1907 gen8_gt_irq_handler(dev, dev_priv, master_ctl);
1908
1909 /* Call regardless, as some status bits might not be
1910 * signalled in iir */
1911 valleyview_pipestat_irq_handler(dev, iir);
1912
1913 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
1914 POSTING_READ(GEN8_MASTER_IRQ);
1915 }
1916
1917 return ret;
1918 }
1919
1920 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1921 {
1922 struct drm_i915_private *dev_priv = dev->dev_private;
1923 int pipe;
1924 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1925 u32 dig_hotplug_reg;
1926
1927 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1928 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1929
1930 intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_ibx);
1931
1932 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1933 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1934 SDE_AUDIO_POWER_SHIFT);
1935 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1936 port_name(port));
1937 }
1938
1939 if (pch_iir & SDE_AUX_MASK)
1940 dp_aux_irq_handler(dev);
1941
1942 if (pch_iir & SDE_GMBUS)
1943 gmbus_irq_handler(dev);
1944
1945 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1946 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1947
1948 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1949 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1950
1951 if (pch_iir & SDE_POISON)
1952 DRM_ERROR("PCH poison interrupt\n");
1953
1954 if (pch_iir & SDE_FDI_MASK)
1955 for_each_pipe(dev_priv, pipe)
1956 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1957 pipe_name(pipe),
1958 I915_READ(FDI_RX_IIR(pipe)));
1959
1960 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1961 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1962
1963 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1964 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1965
1966 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1967 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1968
1969 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1970 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
1971 }
1972
1973 static void ivb_err_int_handler(struct drm_device *dev)
1974 {
1975 struct drm_i915_private *dev_priv = dev->dev_private;
1976 u32 err_int = I915_READ(GEN7_ERR_INT);
1977 enum pipe pipe;
1978
1979 if (err_int & ERR_INT_POISON)
1980 DRM_ERROR("Poison interrupt\n");
1981
1982 for_each_pipe(dev_priv, pipe) {
1983 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
1984 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1985
1986 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1987 if (IS_IVYBRIDGE(dev))
1988 ivb_pipe_crc_irq_handler(dev, pipe);
1989 else
1990 hsw_pipe_crc_irq_handler(dev, pipe);
1991 }
1992 }
1993
1994 I915_WRITE(GEN7_ERR_INT, err_int);
1995 }
1996
1997 static void cpt_serr_int_handler(struct drm_device *dev)
1998 {
1999 struct drm_i915_private *dev_priv = dev->dev_private;
2000 u32 serr_int = I915_READ(SERR_INT);
2001
2002 if (serr_int & SERR_INT_POISON)
2003 DRM_ERROR("PCH poison interrupt\n");
2004
2005 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2006 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2007
2008 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2009 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2010
2011 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2012 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
2013
2014 I915_WRITE(SERR_INT, serr_int);
2015 }
2016
2017 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
2018 {
2019 struct drm_i915_private *dev_priv = dev->dev_private;
2020 int pipe;
2021 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2022 u32 dig_hotplug_reg;
2023
2024 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2025 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2026
2027 intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_cpt);
2028
2029 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2030 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2031 SDE_AUDIO_POWER_SHIFT_CPT);
2032 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2033 port_name(port));
2034 }
2035
2036 if (pch_iir & SDE_AUX_MASK_CPT)
2037 dp_aux_irq_handler(dev);
2038
2039 if (pch_iir & SDE_GMBUS_CPT)
2040 gmbus_irq_handler(dev);
2041
2042 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2043 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2044
2045 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2046 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2047
2048 if (pch_iir & SDE_FDI_MASK_CPT)
2049 for_each_pipe(dev_priv, pipe)
2050 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2051 pipe_name(pipe),
2052 I915_READ(FDI_RX_IIR(pipe)));
2053
2054 if (pch_iir & SDE_ERROR_CPT)
2055 cpt_serr_int_handler(dev);
2056 }
2057
2058 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
2059 {
2060 struct drm_i915_private *dev_priv = dev->dev_private;
2061 enum pipe pipe;
2062
2063 if (de_iir & DE_AUX_CHANNEL_A)
2064 dp_aux_irq_handler(dev);
2065
2066 if (de_iir & DE_GSE)
2067 intel_opregion_asle_intr(dev);
2068
2069 if (de_iir & DE_POISON)
2070 DRM_ERROR("Poison interrupt\n");
2071
2072 for_each_pipe(dev_priv, pipe) {
2073 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2074 intel_pipe_handle_vblank(dev, pipe))
2075 intel_check_page_flip(dev, pipe);
2076
2077 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2078 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2079
2080 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2081 i9xx_pipe_crc_irq_handler(dev, pipe);
2082
2083 /* plane/pipes map 1:1 on ilk+ */
2084 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
2085 intel_prepare_page_flip(dev, pipe);
2086 intel_finish_page_flip_plane(dev, pipe);
2087 }
2088 }
2089
2090 /* check event from PCH */
2091 if (de_iir & DE_PCH_EVENT) {
2092 u32 pch_iir = I915_READ(SDEIIR);
2093
2094 if (HAS_PCH_CPT(dev))
2095 cpt_irq_handler(dev, pch_iir);
2096 else
2097 ibx_irq_handler(dev, pch_iir);
2098
2099 /* should clear PCH hotplug event before clear CPU irq */
2100 I915_WRITE(SDEIIR, pch_iir);
2101 }
2102
2103 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
2104 ironlake_rps_change_irq_handler(dev);
2105 }
2106
2107 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
2108 {
2109 struct drm_i915_private *dev_priv = dev->dev_private;
2110 enum pipe pipe;
2111
2112 if (de_iir & DE_ERR_INT_IVB)
2113 ivb_err_int_handler(dev);
2114
2115 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2116 dp_aux_irq_handler(dev);
2117
2118 if (de_iir & DE_GSE_IVB)
2119 intel_opregion_asle_intr(dev);
2120
2121 for_each_pipe(dev_priv, pipe) {
2122 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2123 intel_pipe_handle_vblank(dev, pipe))
2124 intel_check_page_flip(dev, pipe);
2125
2126 /* plane/pipes map 1:1 on ilk+ */
2127 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
2128 intel_prepare_page_flip(dev, pipe);
2129 intel_finish_page_flip_plane(dev, pipe);
2130 }
2131 }
2132
2133 /* check event from PCH */
2134 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
2135 u32 pch_iir = I915_READ(SDEIIR);
2136
2137 cpt_irq_handler(dev, pch_iir);
2138
2139 /* clear PCH hotplug event before clear CPU irq */
2140 I915_WRITE(SDEIIR, pch_iir);
2141 }
2142 }
2143
2144 /*
2145 * To handle irqs with the minimum potential races with fresh interrupts, we:
2146 * 1 - Disable Master Interrupt Control.
2147 * 2 - Find the source(s) of the interrupt.
2148 * 3 - Clear the Interrupt Identity bits (IIR).
2149 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2150 * 5 - Re-enable Master Interrupt Control.
2151 */
2152 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2153 {
2154 struct drm_device *dev = arg;
2155 struct drm_i915_private *dev_priv = dev->dev_private;
2156 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2157 irqreturn_t ret = IRQ_NONE;
2158
2159 /* We get interrupts on unclaimed registers, so check for this before we
2160 * do any I915_{READ,WRITE}. */
2161 intel_uncore_check_errors(dev);
2162
2163 /* disable master interrupt before clearing iir */
2164 de_ier = I915_READ(DEIER);
2165 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2166 POSTING_READ(DEIER);
2167
2168 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2169 * interrupts will will be stored on its back queue, and then we'll be
2170 * able to process them after we restore SDEIER (as soon as we restore
2171 * it, we'll get an interrupt if SDEIIR still has something to process
2172 * due to its back queue). */
2173 if (!HAS_PCH_NOP(dev)) {
2174 sde_ier = I915_READ(SDEIER);
2175 I915_WRITE(SDEIER, 0);
2176 POSTING_READ(SDEIER);
2177 }
2178
2179 /* Find, clear, then process each source of interrupt */
2180
2181 gt_iir = I915_READ(GTIIR);
2182 if (gt_iir) {
2183 I915_WRITE(GTIIR, gt_iir);
2184 ret = IRQ_HANDLED;
2185 if (INTEL_INFO(dev)->gen >= 6)
2186 snb_gt_irq_handler(dev, dev_priv, gt_iir);
2187 else
2188 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
2189 }
2190
2191 de_iir = I915_READ(DEIIR);
2192 if (de_iir) {
2193 I915_WRITE(DEIIR, de_iir);
2194 ret = IRQ_HANDLED;
2195 if (INTEL_INFO(dev)->gen >= 7)
2196 ivb_display_irq_handler(dev, de_iir);
2197 else
2198 ilk_display_irq_handler(dev, de_iir);
2199 }
2200
2201 if (INTEL_INFO(dev)->gen >= 6) {
2202 u32 pm_iir = I915_READ(GEN6_PMIIR);
2203 if (pm_iir) {
2204 I915_WRITE(GEN6_PMIIR, pm_iir);
2205 ret = IRQ_HANDLED;
2206 gen6_rps_irq_handler(dev_priv, pm_iir);
2207 }
2208 }
2209
2210 I915_WRITE(DEIER, de_ier);
2211 POSTING_READ(DEIER);
2212 if (!HAS_PCH_NOP(dev)) {
2213 I915_WRITE(SDEIER, sde_ier);
2214 POSTING_READ(SDEIER);
2215 }
2216
2217 return ret;
2218 }
2219
2220 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2221 {
2222 struct drm_device *dev = arg;
2223 struct drm_i915_private *dev_priv = dev->dev_private;
2224 u32 master_ctl;
2225 irqreturn_t ret = IRQ_NONE;
2226 uint32_t tmp = 0;
2227 enum pipe pipe;
2228
2229 master_ctl = I915_READ(GEN8_MASTER_IRQ);
2230 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2231 if (!master_ctl)
2232 return IRQ_NONE;
2233
2234 I915_WRITE(GEN8_MASTER_IRQ, 0);
2235 POSTING_READ(GEN8_MASTER_IRQ);
2236
2237 /* Find, clear, then process each source of interrupt */
2238
2239 ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
2240
2241 if (master_ctl & GEN8_DE_MISC_IRQ) {
2242 tmp = I915_READ(GEN8_DE_MISC_IIR);
2243 if (tmp) {
2244 I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2245 ret = IRQ_HANDLED;
2246 if (tmp & GEN8_DE_MISC_GSE)
2247 intel_opregion_asle_intr(dev);
2248 else
2249 DRM_ERROR("Unexpected DE Misc interrupt\n");
2250 }
2251 else
2252 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2253 }
2254
2255 if (master_ctl & GEN8_DE_PORT_IRQ) {
2256 tmp = I915_READ(GEN8_DE_PORT_IIR);
2257 if (tmp) {
2258 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2259 ret = IRQ_HANDLED;
2260 if (tmp & GEN8_AUX_CHANNEL_A)
2261 dp_aux_irq_handler(dev);
2262 else
2263 DRM_ERROR("Unexpected DE Port interrupt\n");
2264 }
2265 else
2266 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2267 }
2268
2269 for_each_pipe(dev_priv, pipe) {
2270 uint32_t pipe_iir, flip_done = 0, fault_errors = 0;
2271
2272 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2273 continue;
2274
2275 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2276 if (pipe_iir) {
2277 ret = IRQ_HANDLED;
2278 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2279
2280 if (pipe_iir & GEN8_PIPE_VBLANK &&
2281 intel_pipe_handle_vblank(dev, pipe))
2282 intel_check_page_flip(dev, pipe);
2283
2284 if (IS_GEN9(dev))
2285 flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE;
2286 else
2287 flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE;
2288
2289 if (flip_done) {
2290 intel_prepare_page_flip(dev, pipe);
2291 intel_finish_page_flip_plane(dev, pipe);
2292 }
2293
2294 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2295 hsw_pipe_crc_irq_handler(dev, pipe);
2296
2297 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN)
2298 intel_cpu_fifo_underrun_irq_handler(dev_priv,
2299 pipe);
2300
2301
2302 if (IS_GEN9(dev))
2303 fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2304 else
2305 fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2306
2307 if (fault_errors)
2308 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2309 pipe_name(pipe),
2310 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2311 } else
2312 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2313 }
2314
2315 if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
2316 /*
2317 * FIXME(BDW): Assume for now that the new interrupt handling
2318 * scheme also closed the SDE interrupt handling race we've seen
2319 * on older pch-split platforms. But this needs testing.
2320 */
2321 u32 pch_iir = I915_READ(SDEIIR);
2322 if (pch_iir) {
2323 I915_WRITE(SDEIIR, pch_iir);
2324 ret = IRQ_HANDLED;
2325 cpt_irq_handler(dev, pch_iir);
2326 } else
2327 DRM_ERROR("The master control interrupt lied (SDE)!\n");
2328
2329 }
2330
2331 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2332 POSTING_READ(GEN8_MASTER_IRQ);
2333
2334 return ret;
2335 }
2336
2337 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2338 bool reset_completed)
2339 {
2340 struct intel_engine_cs *ring;
2341 int i;
2342
2343 /*
2344 * Notify all waiters for GPU completion events that reset state has
2345 * been changed, and that they need to restart their wait after
2346 * checking for potential errors (and bail out to drop locks if there is
2347 * a gpu reset pending so that i915_error_work_func can acquire them).
2348 */
2349
2350 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2351 for_each_ring(ring, dev_priv, i)
2352 wake_up_all(&ring->irq_queue);
2353
2354 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2355 wake_up_all(&dev_priv->pending_flip_queue);
2356
2357 /*
2358 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2359 * reset state is cleared.
2360 */
2361 if (reset_completed)
2362 wake_up_all(&dev_priv->gpu_error.reset_queue);
2363 }
2364
2365 /**
2366 * i915_error_work_func - do process context error handling work
2367 * @work: work struct
2368 *
2369 * Fire an error uevent so userspace can see that a hang or error
2370 * was detected.
2371 */
2372 static void i915_error_work_func(struct work_struct *work)
2373 {
2374 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
2375 work);
2376 struct drm_i915_private *dev_priv =
2377 container_of(error, struct drm_i915_private, gpu_error);
2378 struct drm_device *dev = dev_priv->dev;
2379 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2380 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2381 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2382 int ret;
2383
2384 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2385
2386 /*
2387 * Note that there's only one work item which does gpu resets, so we
2388 * need not worry about concurrent gpu resets potentially incrementing
2389 * error->reset_counter twice. We only need to take care of another
2390 * racing irq/hangcheck declaring the gpu dead for a second time. A
2391 * quick check for that is good enough: schedule_work ensures the
2392 * correct ordering between hang detection and this work item, and since
2393 * the reset in-progress bit is only ever set by code outside of this
2394 * work we don't need to worry about any other races.
2395 */
2396 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2397 DRM_DEBUG_DRIVER("resetting chip\n");
2398 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2399 reset_event);
2400
2401 /*
2402 * In most cases it's guaranteed that we get here with an RPM
2403 * reference held, for example because there is a pending GPU
2404 * request that won't finish until the reset is done. This
2405 * isn't the case at least when we get here by doing a
2406 * simulated reset via debugs, so get an RPM reference.
2407 */
2408 intel_runtime_pm_get(dev_priv);
2409 /*
2410 * All state reset _must_ be completed before we update the
2411 * reset counter, for otherwise waiters might miss the reset
2412 * pending state and not properly drop locks, resulting in
2413 * deadlocks with the reset work.
2414 */
2415 ret = i915_reset(dev);
2416
2417 intel_display_handle_reset(dev);
2418
2419 intel_runtime_pm_put(dev_priv);
2420
2421 if (ret == 0) {
2422 /*
2423 * After all the gem state is reset, increment the reset
2424 * counter and wake up everyone waiting for the reset to
2425 * complete.
2426 *
2427 * Since unlock operations are a one-sided barrier only,
2428 * we need to insert a barrier here to order any seqno
2429 * updates before
2430 * the counter increment.
2431 */
2432 smp_mb__before_atomic();
2433 atomic_inc(&dev_priv->gpu_error.reset_counter);
2434
2435 kobject_uevent_env(&dev->primary->kdev->kobj,
2436 KOBJ_CHANGE, reset_done_event);
2437 } else {
2438 atomic_set_mask(I915_WEDGED, &error->reset_counter);
2439 }
2440
2441 /*
2442 * Note: The wake_up also serves as a memory barrier so that
2443 * waiters see the update value of the reset counter atomic_t.
2444 */
2445 i915_error_wake_up(dev_priv, true);
2446 }
2447 }
2448
2449 static void i915_report_and_clear_eir(struct drm_device *dev)
2450 {
2451 struct drm_i915_private *dev_priv = dev->dev_private;
2452 uint32_t instdone[I915_NUM_INSTDONE_REG];
2453 u32 eir = I915_READ(EIR);
2454 int pipe, i;
2455
2456 if (!eir)
2457 return;
2458
2459 pr_err("render error detected, EIR: 0x%08x\n", eir);
2460
2461 i915_get_extra_instdone(dev, instdone);
2462
2463 if (IS_G4X(dev)) {
2464 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2465 u32 ipeir = I915_READ(IPEIR_I965);
2466
2467 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2468 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2469 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2470 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2471 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2472 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2473 I915_WRITE(IPEIR_I965, ipeir);
2474 POSTING_READ(IPEIR_I965);
2475 }
2476 if (eir & GM45_ERROR_PAGE_TABLE) {
2477 u32 pgtbl_err = I915_READ(PGTBL_ER);
2478 pr_err("page table error\n");
2479 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2480 I915_WRITE(PGTBL_ER, pgtbl_err);
2481 POSTING_READ(PGTBL_ER);
2482 }
2483 }
2484
2485 if (!IS_GEN2(dev)) {
2486 if (eir & I915_ERROR_PAGE_TABLE) {
2487 u32 pgtbl_err = I915_READ(PGTBL_ER);
2488 pr_err("page table error\n");
2489 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2490 I915_WRITE(PGTBL_ER, pgtbl_err);
2491 POSTING_READ(PGTBL_ER);
2492 }
2493 }
2494
2495 if (eir & I915_ERROR_MEMORY_REFRESH) {
2496 pr_err("memory refresh error:\n");
2497 for_each_pipe(dev_priv, pipe)
2498 pr_err("pipe %c stat: 0x%08x\n",
2499 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2500 /* pipestat has already been acked */
2501 }
2502 if (eir & I915_ERROR_INSTRUCTION) {
2503 pr_err("instruction error\n");
2504 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
2505 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2506 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2507 if (INTEL_INFO(dev)->gen < 4) {
2508 u32 ipeir = I915_READ(IPEIR);
2509
2510 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2511 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
2512 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
2513 I915_WRITE(IPEIR, ipeir);
2514 POSTING_READ(IPEIR);
2515 } else {
2516 u32 ipeir = I915_READ(IPEIR_I965);
2517
2518 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2519 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2520 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2521 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2522 I915_WRITE(IPEIR_I965, ipeir);
2523 POSTING_READ(IPEIR_I965);
2524 }
2525 }
2526
2527 I915_WRITE(EIR, eir);
2528 POSTING_READ(EIR);
2529 eir = I915_READ(EIR);
2530 if (eir) {
2531 /*
2532 * some errors might have become stuck,
2533 * mask them.
2534 */
2535 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2536 I915_WRITE(EMR, I915_READ(EMR) | eir);
2537 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2538 }
2539 }
2540
2541 /**
2542 * i915_handle_error - handle an error interrupt
2543 * @dev: drm device
2544 *
2545 * Do some basic checking of regsiter state at error interrupt time and
2546 * dump it to the syslog. Also call i915_capture_error_state() to make
2547 * sure we get a record and make it available in debugfs. Fire a uevent
2548 * so userspace knows something bad happened (should trigger collection
2549 * of a ring dump etc.).
2550 */
2551 void i915_handle_error(struct drm_device *dev, bool wedged,
2552 const char *fmt, ...)
2553 {
2554 struct drm_i915_private *dev_priv = dev->dev_private;
2555 va_list args;
2556 char error_msg[80];
2557
2558 va_start(args, fmt);
2559 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2560 va_end(args);
2561
2562 i915_capture_error_state(dev, wedged, error_msg);
2563 i915_report_and_clear_eir(dev);
2564
2565 if (wedged) {
2566 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2567 &dev_priv->gpu_error.reset_counter);
2568
2569 /*
2570 * Wakeup waiting processes so that the reset work function
2571 * i915_error_work_func doesn't deadlock trying to grab various
2572 * locks. By bumping the reset counter first, the woken
2573 * processes will see a reset in progress and back off,
2574 * releasing their locks and then wait for the reset completion.
2575 * We must do this for _all_ gpu waiters that might hold locks
2576 * that the reset work needs to acquire.
2577 *
2578 * Note: The wake_up serves as the required memory barrier to
2579 * ensure that the waiters see the updated value of the reset
2580 * counter atomic_t.
2581 */
2582 i915_error_wake_up(dev_priv, false);
2583 }
2584
2585 /*
2586 * Our reset work can grab modeset locks (since it needs to reset the
2587 * state of outstanding pagelips). Hence it must not be run on our own
2588 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2589 * code will deadlock.
2590 */
2591 schedule_work(&dev_priv->gpu_error.work);
2592 }
2593
2594 /* Called from drm generic code, passed 'crtc' which
2595 * we use as a pipe index
2596 */
2597 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2598 {
2599 struct drm_i915_private *dev_priv = dev->dev_private;
2600 unsigned long irqflags;
2601
2602 if (!i915_pipe_enabled(dev, pipe))
2603 return -EINVAL;
2604
2605 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2606 if (INTEL_INFO(dev)->gen >= 4)
2607 i915_enable_pipestat(dev_priv, pipe,
2608 PIPE_START_VBLANK_INTERRUPT_STATUS);
2609 else
2610 i915_enable_pipestat(dev_priv, pipe,
2611 PIPE_VBLANK_INTERRUPT_STATUS);
2612 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2613
2614 return 0;
2615 }
2616
2617 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2618 {
2619 struct drm_i915_private *dev_priv = dev->dev_private;
2620 unsigned long irqflags;
2621 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2622 DE_PIPE_VBLANK(pipe);
2623
2624 if (!i915_pipe_enabled(dev, pipe))
2625 return -EINVAL;
2626
2627 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2628 ironlake_enable_display_irq(dev_priv, bit);
2629 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2630
2631 return 0;
2632 }
2633
2634 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2635 {
2636 struct drm_i915_private *dev_priv = dev->dev_private;
2637 unsigned long irqflags;
2638
2639 if (!i915_pipe_enabled(dev, pipe))
2640 return -EINVAL;
2641
2642 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2643 i915_enable_pipestat(dev_priv, pipe,
2644 PIPE_START_VBLANK_INTERRUPT_STATUS);
2645 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2646
2647 return 0;
2648 }
2649
2650 static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2651 {
2652 struct drm_i915_private *dev_priv = dev->dev_private;
2653 unsigned long irqflags;
2654
2655 if (!i915_pipe_enabled(dev, pipe))
2656 return -EINVAL;
2657
2658 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2659 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2660 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2661 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2662 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2663 return 0;
2664 }
2665
2666 /* Called from drm generic code, passed 'crtc' which
2667 * we use as a pipe index
2668 */
2669 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2670 {
2671 struct drm_i915_private *dev_priv = dev->dev_private;
2672 unsigned long irqflags;
2673
2674 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2675 i915_disable_pipestat(dev_priv, pipe,
2676 PIPE_VBLANK_INTERRUPT_STATUS |
2677 PIPE_START_VBLANK_INTERRUPT_STATUS);
2678 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2679 }
2680
2681 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2682 {
2683 struct drm_i915_private *dev_priv = dev->dev_private;
2684 unsigned long irqflags;
2685 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2686 DE_PIPE_VBLANK(pipe);
2687
2688 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2689 ironlake_disable_display_irq(dev_priv, bit);
2690 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2691 }
2692
2693 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2694 {
2695 struct drm_i915_private *dev_priv = dev->dev_private;
2696 unsigned long irqflags;
2697
2698 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2699 i915_disable_pipestat(dev_priv, pipe,
2700 PIPE_START_VBLANK_INTERRUPT_STATUS);
2701 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2702 }
2703
2704 static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2705 {
2706 struct drm_i915_private *dev_priv = dev->dev_private;
2707 unsigned long irqflags;
2708
2709 if (!i915_pipe_enabled(dev, pipe))
2710 return;
2711
2712 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2713 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2714 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2715 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2716 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2717 }
2718
2719 static u32
2720 ring_last_seqno(struct intel_engine_cs *ring)
2721 {
2722 return list_entry(ring->request_list.prev,
2723 struct drm_i915_gem_request, list)->seqno;
2724 }
2725
2726 static bool
2727 ring_idle(struct intel_engine_cs *ring, u32 seqno)
2728 {
2729 return (list_empty(&ring->request_list) ||
2730 i915_seqno_passed(seqno, ring_last_seqno(ring)));
2731 }
2732
2733 static bool
2734 ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
2735 {
2736 if (INTEL_INFO(dev)->gen >= 8) {
2737 return (ipehr >> 23) == 0x1c;
2738 } else {
2739 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2740 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2741 MI_SEMAPHORE_REGISTER);
2742 }
2743 }
2744
2745 static struct intel_engine_cs *
2746 semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset)
2747 {
2748 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2749 struct intel_engine_cs *signaller;
2750 int i;
2751
2752 if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
2753 for_each_ring(signaller, dev_priv, i) {
2754 if (ring == signaller)
2755 continue;
2756
2757 if (offset == signaller->semaphore.signal_ggtt[ring->id])
2758 return signaller;
2759 }
2760 } else {
2761 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2762
2763 for_each_ring(signaller, dev_priv, i) {
2764 if(ring == signaller)
2765 continue;
2766
2767 if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
2768 return signaller;
2769 }
2770 }
2771
2772 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2773 ring->id, ipehr, offset);
2774
2775 return NULL;
2776 }
2777
2778 static struct intel_engine_cs *
2779 semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
2780 {
2781 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2782 u32 cmd, ipehr, head;
2783 u64 offset = 0;
2784 int i, backwards;
2785
2786 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2787 if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
2788 return NULL;
2789
2790 /*
2791 * HEAD is likely pointing to the dword after the actual command,
2792 * so scan backwards until we find the MBOX. But limit it to just 3
2793 * or 4 dwords depending on the semaphore wait command size.
2794 * Note that we don't care about ACTHD here since that might
2795 * point at at batch, and semaphores are always emitted into the
2796 * ringbuffer itself.
2797 */
2798 head = I915_READ_HEAD(ring) & HEAD_ADDR;
2799 backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4;
2800
2801 for (i = backwards; i; --i) {
2802 /*
2803 * Be paranoid and presume the hw has gone off into the wild -
2804 * our ring is smaller than what the hardware (and hence
2805 * HEAD_ADDR) allows. Also handles wrap-around.
2806 */
2807 head &= ring->buffer->size - 1;
2808
2809 /* This here seems to blow up */
2810 cmd = ioread32(ring->buffer->virtual_start + head);
2811 if (cmd == ipehr)
2812 break;
2813
2814 head -= 4;
2815 }
2816
2817 if (!i)
2818 return NULL;
2819
2820 *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
2821 if (INTEL_INFO(ring->dev)->gen >= 8) {
2822 offset = ioread32(ring->buffer->virtual_start + head + 12);
2823 offset <<= 32;
2824 offset = ioread32(ring->buffer->virtual_start + head + 8);
2825 }
2826 return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
2827 }
2828
2829 static int semaphore_passed(struct intel_engine_cs *ring)
2830 {
2831 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2832 struct intel_engine_cs *signaller;
2833 u32 seqno;
2834
2835 ring->hangcheck.deadlock++;
2836
2837 signaller = semaphore_waits_for(ring, &seqno);
2838 if (signaller == NULL)
2839 return -1;
2840
2841 /* Prevent pathological recursion due to driver bugs */
2842 if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
2843 return -1;
2844
2845 if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
2846 return 1;
2847
2848 /* cursory check for an unkickable deadlock */
2849 if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
2850 semaphore_passed(signaller) < 0)
2851 return -1;
2852
2853 return 0;
2854 }
2855
2856 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2857 {
2858 struct intel_engine_cs *ring;
2859 int i;
2860
2861 for_each_ring(ring, dev_priv, i)
2862 ring->hangcheck.deadlock = 0;
2863 }
2864
2865 static enum intel_ring_hangcheck_action
2866 ring_stuck(struct intel_engine_cs *ring, u64 acthd)
2867 {
2868 struct drm_device *dev = ring->dev;
2869 struct drm_i915_private *dev_priv = dev->dev_private;
2870 u32 tmp;
2871
2872 if (acthd != ring->hangcheck.acthd) {
2873 if (acthd > ring->hangcheck.max_acthd) {
2874 ring->hangcheck.max_acthd = acthd;
2875 return HANGCHECK_ACTIVE;
2876 }
2877
2878 return HANGCHECK_ACTIVE_LOOP;
2879 }
2880
2881 if (IS_GEN2(dev))
2882 return HANGCHECK_HUNG;
2883
2884 /* Is the chip hanging on a WAIT_FOR_EVENT?
2885 * If so we can simply poke the RB_WAIT bit
2886 * and break the hang. This should work on
2887 * all but the second generation chipsets.
2888 */
2889 tmp = I915_READ_CTL(ring);
2890 if (tmp & RING_WAIT) {
2891 i915_handle_error(dev, false,
2892 "Kicking stuck wait on %s",
2893 ring->name);
2894 I915_WRITE_CTL(ring, tmp);
2895 return HANGCHECK_KICK;
2896 }
2897
2898 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2899 switch (semaphore_passed(ring)) {
2900 default:
2901 return HANGCHECK_HUNG;
2902 case 1:
2903 i915_handle_error(dev, false,
2904 "Kicking stuck semaphore on %s",
2905 ring->name);
2906 I915_WRITE_CTL(ring, tmp);
2907 return HANGCHECK_KICK;
2908 case 0:
2909 return HANGCHECK_WAIT;
2910 }
2911 }
2912
2913 return HANGCHECK_HUNG;
2914 }
2915
2916 /**
2917 * This is called when the chip hasn't reported back with completed
2918 * batchbuffers in a long time. We keep track per ring seqno progress and
2919 * if there are no progress, hangcheck score for that ring is increased.
2920 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2921 * we kick the ring. If we see no progress on three subsequent calls
2922 * we assume chip is wedged and try to fix it by resetting the chip.
2923 */
2924 static void i915_hangcheck_elapsed(unsigned long data)
2925 {
2926 struct drm_device *dev = (struct drm_device *)data;
2927 struct drm_i915_private *dev_priv = dev->dev_private;
2928 struct intel_engine_cs *ring;
2929 int i;
2930 int busy_count = 0, rings_hung = 0;
2931 bool stuck[I915_NUM_RINGS] = { 0 };
2932 #define BUSY 1
2933 #define KICK 5
2934 #define HUNG 20
2935
2936 if (!i915.enable_hangcheck)
2937 return;
2938
2939 for_each_ring(ring, dev_priv, i) {
2940 u64 acthd;
2941 u32 seqno;
2942 bool busy = true;
2943
2944 semaphore_clear_deadlocks(dev_priv);
2945
2946 seqno = ring->get_seqno(ring, false);
2947 acthd = intel_ring_get_active_head(ring);
2948
2949 if (ring->hangcheck.seqno == seqno) {
2950 if (ring_idle(ring, seqno)) {
2951 ring->hangcheck.action = HANGCHECK_IDLE;
2952
2953 if (waitqueue_active(&ring->irq_queue)) {
2954 /* Issue a wake-up to catch stuck h/w. */
2955 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2956 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2957 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2958 ring->name);
2959 else
2960 DRM_INFO("Fake missed irq on %s\n",
2961 ring->name);
2962 wake_up_all(&ring->irq_queue);
2963 }
2964 /* Safeguard against driver failure */
2965 ring->hangcheck.score += BUSY;
2966 } else
2967 busy = false;
2968 } else {
2969 /* We always increment the hangcheck score
2970 * if the ring is busy and still processing
2971 * the same request, so that no single request
2972 * can run indefinitely (such as a chain of
2973 * batches). The only time we do not increment
2974 * the hangcheck score on this ring, if this
2975 * ring is in a legitimate wait for another
2976 * ring. In that case the waiting ring is a
2977 * victim and we want to be sure we catch the
2978 * right culprit. Then every time we do kick
2979 * the ring, add a small increment to the
2980 * score so that we can catch a batch that is
2981 * being repeatedly kicked and so responsible
2982 * for stalling the machine.
2983 */
2984 ring->hangcheck.action = ring_stuck(ring,
2985 acthd);
2986
2987 switch (ring->hangcheck.action) {
2988 case HANGCHECK_IDLE:
2989 case HANGCHECK_WAIT:
2990 case HANGCHECK_ACTIVE:
2991 break;
2992 case HANGCHECK_ACTIVE_LOOP:
2993 ring->hangcheck.score += BUSY;
2994 break;
2995 case HANGCHECK_KICK:
2996 ring->hangcheck.score += KICK;
2997 break;
2998 case HANGCHECK_HUNG:
2999 ring->hangcheck.score += HUNG;
3000 stuck[i] = true;
3001 break;
3002 }
3003 }
3004 } else {
3005 ring->hangcheck.action = HANGCHECK_ACTIVE;
3006
3007 /* Gradually reduce the count so that we catch DoS
3008 * attempts across multiple batches.
3009 */
3010 if (ring->hangcheck.score > 0)
3011 ring->hangcheck.score--;
3012
3013 ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0;
3014 }
3015
3016 ring->hangcheck.seqno = seqno;
3017 ring->hangcheck.acthd = acthd;
3018 busy_count += busy;
3019 }
3020
3021 for_each_ring(ring, dev_priv, i) {
3022 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3023 DRM_INFO("%s on %s\n",
3024 stuck[i] ? "stuck" : "no progress",
3025 ring->name);
3026 rings_hung++;
3027 }
3028 }
3029
3030 if (rings_hung)
3031 return i915_handle_error(dev, true, "Ring hung");
3032
3033 if (busy_count)
3034 /* Reset timer case chip hangs without another request
3035 * being added */
3036 i915_queue_hangcheck(dev);
3037 }
3038
3039 void i915_queue_hangcheck(struct drm_device *dev)
3040 {
3041 struct drm_i915_private *dev_priv = dev->dev_private;
3042 if (!i915.enable_hangcheck)
3043 return;
3044
3045 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
3046 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
3047 }
3048
3049 static void ibx_irq_reset(struct drm_device *dev)
3050 {
3051 struct drm_i915_private *dev_priv = dev->dev_private;
3052
3053 if (HAS_PCH_NOP(dev))
3054 return;
3055
3056 GEN5_IRQ_RESET(SDE);
3057
3058 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3059 I915_WRITE(SERR_INT, 0xffffffff);
3060 }
3061
3062 /*
3063 * SDEIER is also touched by the interrupt handler to work around missed PCH
3064 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3065 * instead we unconditionally enable all PCH interrupt sources here, but then
3066 * only unmask them as needed with SDEIMR.
3067 *
3068 * This function needs to be called before interrupts are enabled.
3069 */
3070 static void ibx_irq_pre_postinstall(struct drm_device *dev)
3071 {
3072 struct drm_i915_private *dev_priv = dev->dev_private;
3073
3074 if (HAS_PCH_NOP(dev))
3075 return;
3076
3077 WARN_ON(I915_READ(SDEIER) != 0);
3078 I915_WRITE(SDEIER, 0xffffffff);
3079 POSTING_READ(SDEIER);
3080 }
3081
3082 static void gen5_gt_irq_reset(struct drm_device *dev)
3083 {
3084 struct drm_i915_private *dev_priv = dev->dev_private;
3085
3086 GEN5_IRQ_RESET(GT);
3087 if (INTEL_INFO(dev)->gen >= 6)
3088 GEN5_IRQ_RESET(GEN6_PM);
3089 }
3090
3091 /* drm_dma.h hooks
3092 */
3093 static void ironlake_irq_reset(struct drm_device *dev)
3094 {
3095 struct drm_i915_private *dev_priv = dev->dev_private;
3096
3097 I915_WRITE(HWSTAM, 0xffffffff);
3098
3099 GEN5_IRQ_RESET(DE);
3100 if (IS_GEN7(dev))
3101 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3102
3103 gen5_gt_irq_reset(dev);
3104
3105 ibx_irq_reset(dev);
3106 }
3107
3108 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3109 {
3110 enum pipe pipe;
3111
3112 I915_WRITE(PORT_HOTPLUG_EN, 0);
3113 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3114
3115 for_each_pipe(dev_priv, pipe)
3116 I915_WRITE(PIPESTAT(pipe), 0xffff);
3117
3118 GEN5_IRQ_RESET(VLV_);
3119 }
3120
3121 static void valleyview_irq_preinstall(struct drm_device *dev)
3122 {
3123 struct drm_i915_private *dev_priv = dev->dev_private;
3124
3125 /* VLV magic */
3126 I915_WRITE(VLV_IMR, 0);
3127 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
3128 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
3129 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
3130
3131 /* and GT */
3132 I915_WRITE(GTIIR, I915_READ(GTIIR));
3133 I915_WRITE(GTIIR, I915_READ(GTIIR));
3134
3135 gen5_gt_irq_reset(dev);
3136
3137 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3138
3139 vlv_display_irq_reset(dev_priv);
3140 }
3141
3142 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3143 {
3144 GEN8_IRQ_RESET_NDX(GT, 0);
3145 GEN8_IRQ_RESET_NDX(GT, 1);
3146 GEN8_IRQ_RESET_NDX(GT, 2);
3147 GEN8_IRQ_RESET_NDX(GT, 3);
3148 }
3149
3150 static void gen8_irq_reset(struct drm_device *dev)
3151 {
3152 struct drm_i915_private *dev_priv = dev->dev_private;
3153 int pipe;
3154
3155 I915_WRITE(GEN8_MASTER_IRQ, 0);
3156 POSTING_READ(GEN8_MASTER_IRQ);
3157
3158 gen8_gt_irq_reset(dev_priv);
3159
3160 for_each_pipe(dev_priv, pipe)
3161 if (intel_display_power_is_enabled(dev_priv,
3162 POWER_DOMAIN_PIPE(pipe)))
3163 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3164
3165 GEN5_IRQ_RESET(GEN8_DE_PORT_);
3166 GEN5_IRQ_RESET(GEN8_DE_MISC_);
3167 GEN5_IRQ_RESET(GEN8_PCU_);
3168
3169 ibx_irq_reset(dev);
3170 }
3171
3172 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv)
3173 {
3174 uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3175
3176 spin_lock_irq(&dev_priv->irq_lock);
3177 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B],
3178 ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
3179 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C],
3180 ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
3181 spin_unlock_irq(&dev_priv->irq_lock);
3182 }
3183
3184 static void cherryview_irq_preinstall(struct drm_device *dev)
3185 {
3186 struct drm_i915_private *dev_priv = dev->dev_private;
3187
3188 I915_WRITE(GEN8_MASTER_IRQ, 0);
3189 POSTING_READ(GEN8_MASTER_IRQ);
3190
3191 gen8_gt_irq_reset(dev_priv);
3192
3193 GEN5_IRQ_RESET(GEN8_PCU_);
3194
3195 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3196
3197 vlv_display_irq_reset(dev_priv);
3198 }
3199
3200 static void ibx_hpd_irq_setup(struct drm_device *dev)
3201 {
3202 struct drm_i915_private *dev_priv = dev->dev_private;
3203 struct intel_encoder *intel_encoder;
3204 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
3205
3206 if (HAS_PCH_IBX(dev)) {
3207 hotplug_irqs = SDE_HOTPLUG_MASK;
3208 for_each_intel_encoder(dev, intel_encoder)
3209 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3210 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
3211 } else {
3212 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3213 for_each_intel_encoder(dev, intel_encoder)
3214 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3215 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
3216 }
3217
3218 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3219
3220 /*
3221 * Enable digital hotplug on the PCH, and configure the DP short pulse
3222 * duration to 2ms (which is the minimum in the Display Port spec)
3223 *
3224 * This register is the same on all known PCH chips.
3225 */
3226 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3227 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3228 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3229 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3230 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3231 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3232 }
3233
3234 static void ibx_irq_postinstall(struct drm_device *dev)
3235 {
3236 struct drm_i915_private *dev_priv = dev->dev_private;
3237 u32 mask;
3238
3239 if (HAS_PCH_NOP(dev))
3240 return;
3241
3242 if (HAS_PCH_IBX(dev))
3243 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3244 else
3245 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3246
3247 GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
3248 I915_WRITE(SDEIMR, ~mask);
3249 }
3250
3251 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3252 {
3253 struct drm_i915_private *dev_priv = dev->dev_private;
3254 u32 pm_irqs, gt_irqs;
3255
3256 pm_irqs = gt_irqs = 0;
3257
3258 dev_priv->gt_irq_mask = ~0;
3259 if (HAS_L3_DPF(dev)) {
3260 /* L3 parity interrupt is always unmasked. */
3261 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3262 gt_irqs |= GT_PARITY_ERROR(dev);
3263 }
3264
3265 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3266 if (IS_GEN5(dev)) {
3267 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3268 ILK_BSD_USER_INTERRUPT;
3269 } else {
3270 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3271 }
3272
3273 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3274
3275 if (INTEL_INFO(dev)->gen >= 6) {
3276 pm_irqs |= dev_priv->pm_rps_events;
3277
3278 if (HAS_VEBOX(dev))
3279 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3280
3281 dev_priv->pm_irq_mask = 0xffffffff;
3282 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3283 }
3284 }
3285
3286 static int ironlake_irq_postinstall(struct drm_device *dev)
3287 {
3288 struct drm_i915_private *dev_priv = dev->dev_private;
3289 u32 display_mask, extra_mask;
3290
3291 if (INTEL_INFO(dev)->gen >= 7) {
3292 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3293 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3294 DE_PLANEB_FLIP_DONE_IVB |
3295 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3296 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3297 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
3298 } else {
3299 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3300 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3301 DE_AUX_CHANNEL_A |
3302 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3303 DE_POISON);
3304 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3305 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
3306 }
3307
3308 dev_priv->irq_mask = ~display_mask;
3309
3310 I915_WRITE(HWSTAM, 0xeffe);
3311
3312 ibx_irq_pre_postinstall(dev);
3313
3314 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3315
3316 gen5_gt_irq_postinstall(dev);
3317
3318 ibx_irq_postinstall(dev);
3319
3320 if (IS_IRONLAKE_M(dev)) {
3321 /* Enable PCU event interrupts
3322 *
3323 * spinlocking not required here for correctness since interrupt
3324 * setup is guaranteed to run in single-threaded context. But we
3325 * need it to make the assert_spin_locked happy. */
3326 spin_lock_irq(&dev_priv->irq_lock);
3327 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
3328 spin_unlock_irq(&dev_priv->irq_lock);
3329 }
3330
3331 return 0;
3332 }
3333
3334 static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3335 {
3336 u32 pipestat_mask;
3337 u32 iir_mask;
3338 enum pipe pipe;
3339
3340 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3341 PIPE_FIFO_UNDERRUN_STATUS;
3342
3343 for_each_pipe(dev_priv, pipe)
3344 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3345 POSTING_READ(PIPESTAT(PIPE_A));
3346
3347 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3348 PIPE_CRC_DONE_INTERRUPT_STATUS;
3349
3350 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3351 for_each_pipe(dev_priv, pipe)
3352 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3353
3354 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3355 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3356 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3357 if (IS_CHERRYVIEW(dev_priv))
3358 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3359 dev_priv->irq_mask &= ~iir_mask;
3360
3361 I915_WRITE(VLV_IIR, iir_mask);
3362 I915_WRITE(VLV_IIR, iir_mask);
3363 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3364 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3365 POSTING_READ(VLV_IMR);
3366 }
3367
3368 static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3369 {
3370 u32 pipestat_mask;
3371 u32 iir_mask;
3372 enum pipe pipe;
3373
3374 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3375 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3376 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3377 if (IS_CHERRYVIEW(dev_priv))
3378 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3379
3380 dev_priv->irq_mask |= iir_mask;
3381 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3382 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3383 I915_WRITE(VLV_IIR, iir_mask);
3384 I915_WRITE(VLV_IIR, iir_mask);
3385 POSTING_READ(VLV_IIR);
3386
3387 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3388 PIPE_CRC_DONE_INTERRUPT_STATUS;
3389
3390 i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3391 for_each_pipe(dev_priv, pipe)
3392 i915_disable_pipestat(dev_priv, pipe, pipestat_mask);
3393
3394 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3395 PIPE_FIFO_UNDERRUN_STATUS;
3396
3397 for_each_pipe(dev_priv, pipe)
3398 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3399 POSTING_READ(PIPESTAT(PIPE_A));
3400 }
3401
3402 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3403 {
3404 assert_spin_locked(&dev_priv->irq_lock);
3405
3406 if (dev_priv->display_irqs_enabled)
3407 return;
3408
3409 dev_priv->display_irqs_enabled = true;
3410
3411 if (intel_irqs_enabled(dev_priv))
3412 valleyview_display_irqs_install(dev_priv);
3413 }
3414
3415 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3416 {
3417 assert_spin_locked(&dev_priv->irq_lock);
3418
3419 if (!dev_priv->display_irqs_enabled)
3420 return;
3421
3422 dev_priv->display_irqs_enabled = false;
3423
3424 if (intel_irqs_enabled(dev_priv))
3425 valleyview_display_irqs_uninstall(dev_priv);
3426 }
3427
3428 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3429 {
3430 dev_priv->irq_mask = ~0;
3431
3432 I915_WRITE(PORT_HOTPLUG_EN, 0);
3433 POSTING_READ(PORT_HOTPLUG_EN);
3434
3435 I915_WRITE(VLV_IIR, 0xffffffff);
3436 I915_WRITE(VLV_IIR, 0xffffffff);
3437 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3438 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3439 POSTING_READ(VLV_IMR);
3440
3441 /* Interrupt setup is already guaranteed to be single-threaded, this is
3442 * just to make the assert_spin_locked check happy. */
3443 spin_lock_irq(&dev_priv->irq_lock);
3444 if (dev_priv->display_irqs_enabled)
3445 valleyview_display_irqs_install(dev_priv);
3446 spin_unlock_irq(&dev_priv->irq_lock);
3447
3448 I915_WRITE(VLV_IIR, 0xffffffff);
3449 I915_WRITE(VLV_IIR, 0xffffffff);
3450 }
3451
3452 static int valleyview_irq_postinstall(struct drm_device *dev)
3453 {
3454 struct drm_i915_private *dev_priv = dev->dev_private;
3455
3456 vlv_display_irq_postinstall(dev_priv);
3457
3458 gen5_gt_irq_postinstall(dev);
3459
3460 /* ack & enable invalid PTE error interrupts */
3461 #if 0 /* FIXME: add support to irq handler for checking these bits */
3462 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3463 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3464 #endif
3465
3466 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3467
3468 return 0;
3469 }
3470
3471 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3472 {
3473 /* These are interrupts we'll toggle with the ring mask register */
3474 uint32_t gt_interrupts[] = {
3475 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3476 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3477 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3478 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3479 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3480 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3481 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3482 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3483 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3484 0,
3485 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3486 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3487 };
3488
3489 dev_priv->pm_irq_mask = 0xffffffff;
3490 GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3491 GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3492 GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, dev_priv->pm_rps_events);
3493 GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3494 }
3495
3496 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3497 {
3498 uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3499 uint32_t de_pipe_enables;
3500 int pipe;
3501
3502 if (IS_GEN9(dev_priv))
3503 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3504 GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3505 else
3506 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3507 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3508
3509 de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3510 GEN8_PIPE_FIFO_UNDERRUN;
3511
3512 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3513 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3514 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3515
3516 for_each_pipe(dev_priv, pipe)
3517 if (intel_display_power_is_enabled(dev_priv,
3518 POWER_DOMAIN_PIPE(pipe)))
3519 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3520 dev_priv->de_irq_mask[pipe],
3521 de_pipe_enables);
3522
3523 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~GEN8_AUX_CHANNEL_A, GEN8_AUX_CHANNEL_A);
3524 }
3525
3526 static int gen8_irq_postinstall(struct drm_device *dev)
3527 {
3528 struct drm_i915_private *dev_priv = dev->dev_private;
3529
3530 ibx_irq_pre_postinstall(dev);
3531
3532 gen8_gt_irq_postinstall(dev_priv);
3533 gen8_de_irq_postinstall(dev_priv);
3534
3535 ibx_irq_postinstall(dev);
3536
3537 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3538 POSTING_READ(GEN8_MASTER_IRQ);
3539
3540 return 0;
3541 }
3542
3543 static int cherryview_irq_postinstall(struct drm_device *dev)
3544 {
3545 struct drm_i915_private *dev_priv = dev->dev_private;
3546 u32 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
3547 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3548 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3549 I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3550 u32 pipestat_enable = PLANE_FLIP_DONE_INT_STATUS_VLV |
3551 PIPE_CRC_DONE_INTERRUPT_STATUS;
3552 int pipe;
3553
3554 /*
3555 * Leave vblank interrupts masked initially. enable/disable will
3556 * toggle them based on usage.
3557 */
3558 dev_priv->irq_mask = ~enable_mask;
3559
3560 for_each_pipe(dev_priv, pipe)
3561 I915_WRITE(PIPESTAT(pipe), 0xffff);
3562
3563 spin_lock_irq(&dev_priv->irq_lock);
3564 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3565 for_each_pipe(dev_priv, pipe)
3566 i915_enable_pipestat(dev_priv, pipe, pipestat_enable);
3567 spin_unlock_irq(&dev_priv->irq_lock);
3568
3569 I915_WRITE(VLV_IIR, 0xffffffff);
3570 I915_WRITE(VLV_IIR, 0xffffffff);
3571 I915_WRITE(VLV_IER, enable_mask);
3572 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3573 POSTING_READ(VLV_IMR);
3574
3575 gen8_gt_irq_postinstall(dev_priv);
3576
3577 I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
3578 POSTING_READ(GEN8_MASTER_IRQ);
3579
3580 return 0;
3581 }
3582
3583 static void gen8_irq_uninstall(struct drm_device *dev)
3584 {
3585 struct drm_i915_private *dev_priv = dev->dev_private;
3586
3587 if (!dev_priv)
3588 return;
3589
3590 gen8_irq_reset(dev);
3591 }
3592
3593 static void valleyview_irq_uninstall(struct drm_device *dev)
3594 {
3595 struct drm_i915_private *dev_priv = dev->dev_private;
3596
3597 if (!dev_priv)
3598 return;
3599
3600 I915_WRITE(VLV_MASTER_IER, 0);
3601
3602 gen5_gt_irq_reset(dev);
3603
3604 I915_WRITE(HWSTAM, 0xffffffff);
3605
3606 /* Interrupt setup is already guaranteed to be single-threaded, this is
3607 * just to make the assert_spin_locked check happy. */
3608 spin_lock_irq(&dev_priv->irq_lock);
3609 if (dev_priv->display_irqs_enabled)
3610 valleyview_display_irqs_uninstall(dev_priv);
3611 spin_unlock_irq(&dev_priv->irq_lock);
3612
3613 vlv_display_irq_reset(dev_priv);
3614
3615 dev_priv->irq_mask = 0;
3616 }
3617
3618 static void cherryview_irq_uninstall(struct drm_device *dev)
3619 {
3620 struct drm_i915_private *dev_priv = dev->dev_private;
3621 int pipe;
3622
3623 if (!dev_priv)
3624 return;
3625
3626 I915_WRITE(GEN8_MASTER_IRQ, 0);
3627 POSTING_READ(GEN8_MASTER_IRQ);
3628
3629 gen8_gt_irq_reset(dev_priv);
3630
3631 GEN5_IRQ_RESET(GEN8_PCU_);
3632
3633 I915_WRITE(PORT_HOTPLUG_EN, 0);
3634 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3635
3636 for_each_pipe(dev_priv, pipe)
3637 I915_WRITE(PIPESTAT(pipe), 0xffff);
3638
3639 GEN5_IRQ_RESET(VLV_);
3640 }
3641
3642 static void ironlake_irq_uninstall(struct drm_device *dev)
3643 {
3644 struct drm_i915_private *dev_priv = dev->dev_private;
3645
3646 if (!dev_priv)
3647 return;
3648
3649 ironlake_irq_reset(dev);
3650 }
3651
3652 static void i8xx_irq_preinstall(struct drm_device * dev)
3653 {
3654 struct drm_i915_private *dev_priv = dev->dev_private;
3655 int pipe;
3656
3657 for_each_pipe(dev_priv, pipe)
3658 I915_WRITE(PIPESTAT(pipe), 0);
3659 I915_WRITE16(IMR, 0xffff);
3660 I915_WRITE16(IER, 0x0);
3661 POSTING_READ16(IER);
3662 }
3663
3664 static int i8xx_irq_postinstall(struct drm_device *dev)
3665 {
3666 struct drm_i915_private *dev_priv = dev->dev_private;
3667
3668 I915_WRITE16(EMR,
3669 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3670
3671 /* Unmask the interrupts that we always want on. */
3672 dev_priv->irq_mask =
3673 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3674 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3675 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3676 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3677 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3678 I915_WRITE16(IMR, dev_priv->irq_mask);
3679
3680 I915_WRITE16(IER,
3681 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3682 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3683 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3684 I915_USER_INTERRUPT);
3685 POSTING_READ16(IER);
3686
3687 /* Interrupt setup is already guaranteed to be single-threaded, this is
3688 * just to make the assert_spin_locked check happy. */
3689 spin_lock_irq(&dev_priv->irq_lock);
3690 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3691 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3692 spin_unlock_irq(&dev_priv->irq_lock);
3693
3694 return 0;
3695 }
3696
3697 /*
3698 * Returns true when a page flip has completed.
3699 */
3700 static bool i8xx_handle_vblank(struct drm_device *dev,
3701 int plane, int pipe, u32 iir)
3702 {
3703 struct drm_i915_private *dev_priv = dev->dev_private;
3704 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3705
3706 if (!intel_pipe_handle_vblank(dev, pipe))
3707 return false;
3708
3709 if ((iir & flip_pending) == 0)
3710 goto check_page_flip;
3711
3712 intel_prepare_page_flip(dev, plane);
3713
3714 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3715 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3716 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3717 * the flip is completed (no longer pending). Since this doesn't raise
3718 * an interrupt per se, we watch for the change at vblank.
3719 */
3720 if (I915_READ16(ISR) & flip_pending)
3721 goto check_page_flip;
3722
3723 intel_finish_page_flip(dev, pipe);
3724 return true;
3725
3726 check_page_flip:
3727 intel_check_page_flip(dev, pipe);
3728 return false;
3729 }
3730
3731 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3732 {
3733 struct drm_device *dev = arg;
3734 struct drm_i915_private *dev_priv = dev->dev_private;
3735 u16 iir, new_iir;
3736 u32 pipe_stats[2];
3737 int pipe;
3738 u16 flip_mask =
3739 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3740 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3741
3742 iir = I915_READ16(IIR);
3743 if (iir == 0)
3744 return IRQ_NONE;
3745
3746 while (iir & ~flip_mask) {
3747 /* Can't rely on pipestat interrupt bit in iir as it might
3748 * have been cleared after the pipestat interrupt was received.
3749 * It doesn't set the bit in iir again, but it still produces
3750 * interrupts (for non-MSI).
3751 */
3752 spin_lock(&dev_priv->irq_lock);
3753 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3754 i915_handle_error(dev, false,
3755 "Command parser error, iir 0x%08x",
3756 iir);
3757
3758 for_each_pipe(dev_priv, pipe) {
3759 int reg = PIPESTAT(pipe);
3760 pipe_stats[pipe] = I915_READ(reg);
3761
3762 /*
3763 * Clear the PIPE*STAT regs before the IIR
3764 */
3765 if (pipe_stats[pipe] & 0x8000ffff)
3766 I915_WRITE(reg, pipe_stats[pipe]);
3767 }
3768 spin_unlock(&dev_priv->irq_lock);
3769
3770 I915_WRITE16(IIR, iir & ~flip_mask);
3771 new_iir = I915_READ16(IIR); /* Flush posted writes */
3772
3773 i915_update_dri1_breadcrumb(dev);
3774
3775 if (iir & I915_USER_INTERRUPT)
3776 notify_ring(dev, &dev_priv->ring[RCS]);
3777
3778 for_each_pipe(dev_priv, pipe) {
3779 int plane = pipe;
3780 if (HAS_FBC(dev))
3781 plane = !plane;
3782
3783 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3784 i8xx_handle_vblank(dev, plane, pipe, iir))
3785 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3786
3787 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3788 i9xx_pipe_crc_irq_handler(dev, pipe);
3789
3790 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3791 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3792 pipe);
3793 }
3794
3795 iir = new_iir;
3796 }
3797
3798 return IRQ_HANDLED;
3799 }
3800
3801 static void i8xx_irq_uninstall(struct drm_device * dev)
3802 {
3803 struct drm_i915_private *dev_priv = dev->dev_private;
3804 int pipe;
3805
3806 for_each_pipe(dev_priv, pipe) {
3807 /* Clear enable bits; then clear status bits */
3808 I915_WRITE(PIPESTAT(pipe), 0);
3809 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3810 }
3811 I915_WRITE16(IMR, 0xffff);
3812 I915_WRITE16(IER, 0x0);
3813 I915_WRITE16(IIR, I915_READ16(IIR));
3814 }
3815
3816 static void i915_irq_preinstall(struct drm_device * dev)
3817 {
3818 struct drm_i915_private *dev_priv = dev->dev_private;
3819 int pipe;
3820
3821 if (I915_HAS_HOTPLUG(dev)) {
3822 I915_WRITE(PORT_HOTPLUG_EN, 0);
3823 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3824 }
3825
3826 I915_WRITE16(HWSTAM, 0xeffe);
3827 for_each_pipe(dev_priv, pipe)
3828 I915_WRITE(PIPESTAT(pipe), 0);
3829 I915_WRITE(IMR, 0xffffffff);
3830 I915_WRITE(IER, 0x0);
3831 POSTING_READ(IER);
3832 }
3833
3834 static int i915_irq_postinstall(struct drm_device *dev)
3835 {
3836 struct drm_i915_private *dev_priv = dev->dev_private;
3837 u32 enable_mask;
3838
3839 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3840
3841 /* Unmask the interrupts that we always want on. */
3842 dev_priv->irq_mask =
3843 ~(I915_ASLE_INTERRUPT |
3844 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3845 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3846 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3847 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3848 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3849
3850 enable_mask =
3851 I915_ASLE_INTERRUPT |
3852 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3853 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3854 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3855 I915_USER_INTERRUPT;
3856
3857 if (I915_HAS_HOTPLUG(dev)) {
3858 I915_WRITE(PORT_HOTPLUG_EN, 0);
3859 POSTING_READ(PORT_HOTPLUG_EN);
3860
3861 /* Enable in IER... */
3862 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3863 /* and unmask in IMR */
3864 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3865 }
3866
3867 I915_WRITE(IMR, dev_priv->irq_mask);
3868 I915_WRITE(IER, enable_mask);
3869 POSTING_READ(IER);
3870
3871 i915_enable_asle_pipestat(dev);
3872
3873 /* Interrupt setup is already guaranteed to be single-threaded, this is
3874 * just to make the assert_spin_locked check happy. */
3875 spin_lock_irq(&dev_priv->irq_lock);
3876 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3877 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3878 spin_unlock_irq(&dev_priv->irq_lock);
3879
3880 return 0;
3881 }
3882
3883 /*
3884 * Returns true when a page flip has completed.
3885 */
3886 static bool i915_handle_vblank(struct drm_device *dev,
3887 int plane, int pipe, u32 iir)
3888 {
3889 struct drm_i915_private *dev_priv = dev->dev_private;
3890 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3891
3892 if (!intel_pipe_handle_vblank(dev, pipe))
3893 return false;
3894
3895 if ((iir & flip_pending) == 0)
3896 goto check_page_flip;
3897
3898 intel_prepare_page_flip(dev, plane);
3899
3900 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3901 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3902 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3903 * the flip is completed (no longer pending). Since this doesn't raise
3904 * an interrupt per se, we watch for the change at vblank.
3905 */
3906 if (I915_READ(ISR) & flip_pending)
3907 goto check_page_flip;
3908
3909 intel_finish_page_flip(dev, pipe);
3910 return true;
3911
3912 check_page_flip:
3913 intel_check_page_flip(dev, pipe);
3914 return false;
3915 }
3916
3917 static irqreturn_t i915_irq_handler(int irq, void *arg)
3918 {
3919 struct drm_device *dev = arg;
3920 struct drm_i915_private *dev_priv = dev->dev_private;
3921 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3922 u32 flip_mask =
3923 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3924 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3925 int pipe, ret = IRQ_NONE;
3926
3927 iir = I915_READ(IIR);
3928 do {
3929 bool irq_received = (iir & ~flip_mask) != 0;
3930 bool blc_event = false;
3931
3932 /* Can't rely on pipestat interrupt bit in iir as it might
3933 * have been cleared after the pipestat interrupt was received.
3934 * It doesn't set the bit in iir again, but it still produces
3935 * interrupts (for non-MSI).
3936 */
3937 spin_lock(&dev_priv->irq_lock);
3938 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3939 i915_handle_error(dev, false,
3940 "Command parser error, iir 0x%08x",
3941 iir);
3942
3943 for_each_pipe(dev_priv, pipe) {
3944 int reg = PIPESTAT(pipe);
3945 pipe_stats[pipe] = I915_READ(reg);
3946
3947 /* Clear the PIPE*STAT regs before the IIR */
3948 if (pipe_stats[pipe] & 0x8000ffff) {
3949 I915_WRITE(reg, pipe_stats[pipe]);
3950 irq_received = true;
3951 }
3952 }
3953 spin_unlock(&dev_priv->irq_lock);
3954
3955 if (!irq_received)
3956 break;
3957
3958 /* Consume port. Then clear IIR or we'll miss events */
3959 if (I915_HAS_HOTPLUG(dev) &&
3960 iir & I915_DISPLAY_PORT_INTERRUPT)
3961 i9xx_hpd_irq_handler(dev);
3962
3963 I915_WRITE(IIR, iir & ~flip_mask);
3964 new_iir = I915_READ(IIR); /* Flush posted writes */
3965
3966 if (iir & I915_USER_INTERRUPT)
3967 notify_ring(dev, &dev_priv->ring[RCS]);
3968
3969 for_each_pipe(dev_priv, pipe) {
3970 int plane = pipe;
3971 if (HAS_FBC(dev))
3972 plane = !plane;
3973
3974 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3975 i915_handle_vblank(dev, plane, pipe, iir))
3976 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3977
3978 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3979 blc_event = true;
3980
3981 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3982 i9xx_pipe_crc_irq_handler(dev, pipe);
3983
3984 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3985 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3986 pipe);
3987 }
3988
3989 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3990 intel_opregion_asle_intr(dev);
3991
3992 /* With MSI, interrupts are only generated when iir
3993 * transitions from zero to nonzero. If another bit got
3994 * set while we were handling the existing iir bits, then
3995 * we would never get another interrupt.
3996 *
3997 * This is fine on non-MSI as well, as if we hit this path
3998 * we avoid exiting the interrupt handler only to generate
3999 * another one.
4000 *
4001 * Note that for MSI this could cause a stray interrupt report
4002 * if an interrupt landed in the time between writing IIR and
4003 * the posting read. This should be rare enough to never
4004 * trigger the 99% of 100,000 interrupts test for disabling
4005 * stray interrupts.
4006 */
4007 ret = IRQ_HANDLED;
4008 iir = new_iir;
4009 } while (iir & ~flip_mask);
4010
4011 i915_update_dri1_breadcrumb(dev);
4012
4013 return ret;
4014 }
4015
4016 static void i915_irq_uninstall(struct drm_device * dev)
4017 {
4018 struct drm_i915_private *dev_priv = dev->dev_private;
4019 int pipe;
4020
4021 if (I915_HAS_HOTPLUG(dev)) {
4022 I915_WRITE(PORT_HOTPLUG_EN, 0);
4023 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4024 }
4025
4026 I915_WRITE16(HWSTAM, 0xffff);
4027 for_each_pipe(dev_priv, pipe) {
4028 /* Clear enable bits; then clear status bits */
4029 I915_WRITE(PIPESTAT(pipe), 0);
4030 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4031 }
4032 I915_WRITE(IMR, 0xffffffff);
4033 I915_WRITE(IER, 0x0);
4034
4035 I915_WRITE(IIR, I915_READ(IIR));
4036 }
4037
4038 static void i965_irq_preinstall(struct drm_device * dev)
4039 {
4040 struct drm_i915_private *dev_priv = dev->dev_private;
4041 int pipe;
4042
4043 I915_WRITE(PORT_HOTPLUG_EN, 0);
4044 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4045
4046 I915_WRITE(HWSTAM, 0xeffe);
4047 for_each_pipe(dev_priv, pipe)
4048 I915_WRITE(PIPESTAT(pipe), 0);
4049 I915_WRITE(IMR, 0xffffffff);
4050 I915_WRITE(IER, 0x0);
4051 POSTING_READ(IER);
4052 }
4053
4054 static int i965_irq_postinstall(struct drm_device *dev)
4055 {
4056 struct drm_i915_private *dev_priv = dev->dev_private;
4057 u32 enable_mask;
4058 u32 error_mask;
4059
4060 /* Unmask the interrupts that we always want on. */
4061 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4062 I915_DISPLAY_PORT_INTERRUPT |
4063 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4064 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4065 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4066 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4067 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4068
4069 enable_mask = ~dev_priv->irq_mask;
4070 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4071 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4072 enable_mask |= I915_USER_INTERRUPT;
4073
4074 if (IS_G4X(dev))
4075 enable_mask |= I915_BSD_USER_INTERRUPT;
4076
4077 /* Interrupt setup is already guaranteed to be single-threaded, this is
4078 * just to make the assert_spin_locked check happy. */
4079 spin_lock_irq(&dev_priv->irq_lock);
4080 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4081 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4082 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4083 spin_unlock_irq(&dev_priv->irq_lock);
4084
4085 /*
4086 * Enable some error detection, note the instruction error mask
4087 * bit is reserved, so we leave it masked.
4088 */
4089 if (IS_G4X(dev)) {
4090 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4091 GM45_ERROR_MEM_PRIV |
4092 GM45_ERROR_CP_PRIV |
4093 I915_ERROR_MEMORY_REFRESH);
4094 } else {
4095 error_mask = ~(I915_ERROR_PAGE_TABLE |
4096 I915_ERROR_MEMORY_REFRESH);
4097 }
4098 I915_WRITE(EMR, error_mask);
4099
4100 I915_WRITE(IMR, dev_priv->irq_mask);
4101 I915_WRITE(IER, enable_mask);
4102 POSTING_READ(IER);
4103
4104 I915_WRITE(PORT_HOTPLUG_EN, 0);
4105 POSTING_READ(PORT_HOTPLUG_EN);
4106
4107 i915_enable_asle_pipestat(dev);
4108
4109 return 0;
4110 }
4111
4112 static void i915_hpd_irq_setup(struct drm_device *dev)
4113 {
4114 struct drm_i915_private *dev_priv = dev->dev_private;
4115 struct intel_encoder *intel_encoder;
4116 u32 hotplug_en;
4117
4118 assert_spin_locked(&dev_priv->irq_lock);
4119
4120 if (I915_HAS_HOTPLUG(dev)) {
4121 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
4122 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
4123 /* Note HDMI and DP share hotplug bits */
4124 /* enable bits are the same for all generations */
4125 for_each_intel_encoder(dev, intel_encoder)
4126 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
4127 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
4128 /* Programming the CRT detection parameters tends
4129 to generate a spurious hotplug event about three
4130 seconds later. So just do it once.
4131 */
4132 if (IS_G4X(dev))
4133 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4134 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
4135 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4136
4137 /* Ignore TV since it's buggy */
4138 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
4139 }
4140 }
4141
4142 static irqreturn_t i965_irq_handler(int irq, void *arg)
4143 {
4144 struct drm_device *dev = arg;
4145 struct drm_i915_private *dev_priv = dev->dev_private;
4146 u32 iir, new_iir;
4147 u32 pipe_stats[I915_MAX_PIPES];
4148 int ret = IRQ_NONE, pipe;
4149 u32 flip_mask =
4150 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4151 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4152
4153 iir = I915_READ(IIR);
4154
4155 for (;;) {
4156 bool irq_received = (iir & ~flip_mask) != 0;
4157 bool blc_event = false;
4158
4159 /* Can't rely on pipestat interrupt bit in iir as it might
4160 * have been cleared after the pipestat interrupt was received.
4161 * It doesn't set the bit in iir again, but it still produces
4162 * interrupts (for non-MSI).
4163 */
4164 spin_lock(&dev_priv->irq_lock);
4165 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4166 i915_handle_error(dev, false,
4167 "Command parser error, iir 0x%08x",
4168 iir);
4169
4170 for_each_pipe(dev_priv, pipe) {
4171 int reg = PIPESTAT(pipe);
4172 pipe_stats[pipe] = I915_READ(reg);
4173
4174 /*
4175 * Clear the PIPE*STAT regs before the IIR
4176 */
4177 if (pipe_stats[pipe] & 0x8000ffff) {
4178 I915_WRITE(reg, pipe_stats[pipe]);
4179 irq_received = true;
4180 }
4181 }
4182 spin_unlock(&dev_priv->irq_lock);
4183
4184 if (!irq_received)
4185 break;
4186
4187 ret = IRQ_HANDLED;
4188
4189 /* Consume port. Then clear IIR or we'll miss events */
4190 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4191 i9xx_hpd_irq_handler(dev);
4192
4193 I915_WRITE(IIR, iir & ~flip_mask);
4194 new_iir = I915_READ(IIR); /* Flush posted writes */
4195
4196 if (iir & I915_USER_INTERRUPT)
4197 notify_ring(dev, &dev_priv->ring[RCS]);
4198 if (iir & I915_BSD_USER_INTERRUPT)
4199 notify_ring(dev, &dev_priv->ring[VCS]);
4200
4201 for_each_pipe(dev_priv, pipe) {
4202 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4203 i915_handle_vblank(dev, pipe, pipe, iir))
4204 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4205
4206 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4207 blc_event = true;
4208
4209 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4210 i9xx_pipe_crc_irq_handler(dev, pipe);
4211
4212 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4213 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4214 }
4215
4216 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4217 intel_opregion_asle_intr(dev);
4218
4219 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4220 gmbus_irq_handler(dev);
4221
4222 /* With MSI, interrupts are only generated when iir
4223 * transitions from zero to nonzero. If another bit got
4224 * set while we were handling the existing iir bits, then
4225 * we would never get another interrupt.
4226 *
4227 * This is fine on non-MSI as well, as if we hit this path
4228 * we avoid exiting the interrupt handler only to generate
4229 * another one.
4230 *
4231 * Note that for MSI this could cause a stray interrupt report
4232 * if an interrupt landed in the time between writing IIR and
4233 * the posting read. This should be rare enough to never
4234 * trigger the 99% of 100,000 interrupts test for disabling
4235 * stray interrupts.
4236 */
4237 iir = new_iir;
4238 }
4239
4240 i915_update_dri1_breadcrumb(dev);
4241
4242 return ret;
4243 }
4244
4245 static void i965_irq_uninstall(struct drm_device * dev)
4246 {
4247 struct drm_i915_private *dev_priv = dev->dev_private;
4248 int pipe;
4249
4250 if (!dev_priv)
4251 return;
4252
4253 I915_WRITE(PORT_HOTPLUG_EN, 0);
4254 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4255
4256 I915_WRITE(HWSTAM, 0xffffffff);
4257 for_each_pipe(dev_priv, pipe)
4258 I915_WRITE(PIPESTAT(pipe), 0);
4259 I915_WRITE(IMR, 0xffffffff);
4260 I915_WRITE(IER, 0x0);
4261
4262 for_each_pipe(dev_priv, pipe)
4263 I915_WRITE(PIPESTAT(pipe),
4264 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4265 I915_WRITE(IIR, I915_READ(IIR));
4266 }
4267
4268 static void intel_hpd_irq_reenable_work(struct work_struct *work)
4269 {
4270 struct drm_i915_private *dev_priv =
4271 container_of(work, typeof(*dev_priv),
4272 hotplug_reenable_work.work);
4273 struct drm_device *dev = dev_priv->dev;
4274 struct drm_mode_config *mode_config = &dev->mode_config;
4275 int i;
4276
4277 intel_runtime_pm_get(dev_priv);
4278
4279 spin_lock_irq(&dev_priv->irq_lock);
4280 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
4281 struct drm_connector *connector;
4282
4283 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
4284 continue;
4285
4286 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4287
4288 list_for_each_entry(connector, &mode_config->connector_list, head) {
4289 struct intel_connector *intel_connector = to_intel_connector(connector);
4290
4291 if (intel_connector->encoder->hpd_pin == i) {
4292 if (connector->polled != intel_connector->polled)
4293 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
4294 connector->name);
4295 connector->polled = intel_connector->polled;
4296 if (!connector->polled)
4297 connector->polled = DRM_CONNECTOR_POLL_HPD;
4298 }
4299 }
4300 }
4301 if (dev_priv->display.hpd_irq_setup)
4302 dev_priv->display.hpd_irq_setup(dev);
4303 spin_unlock_irq(&dev_priv->irq_lock);
4304
4305 intel_runtime_pm_put(dev_priv);
4306 }
4307
4308 /**
4309 * intel_irq_init - initializes irq support
4310 * @dev_priv: i915 device instance
4311 *
4312 * This function initializes all the irq support including work items, timers
4313 * and all the vtables. It does not setup the interrupt itself though.
4314 */
4315 void intel_irq_init(struct drm_i915_private *dev_priv)
4316 {
4317 struct drm_device *dev = dev_priv->dev;
4318
4319 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
4320 INIT_WORK(&dev_priv->dig_port_work, i915_digport_work_func);
4321 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
4322 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4323 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4324
4325 /* Let's track the enabled rps events */
4326 if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
4327 /* WaGsvRC0ResidencyMethod:vlv */
4328 dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
4329 else
4330 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4331
4332 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
4333 i915_hangcheck_elapsed,
4334 (unsigned long) dev);
4335 INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work,
4336 intel_hpd_irq_reenable_work);
4337
4338 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4339
4340 if (IS_GEN2(dev_priv)) {
4341 dev->max_vblank_count = 0;
4342 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4343 } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4344 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4345 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
4346 } else {
4347 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4348 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4349 }
4350
4351 /*
4352 * Opt out of the vblank disable timer on everything except gen2.
4353 * Gen2 doesn't have a hardware frame counter and so depends on
4354 * vblank interrupts to produce sane vblank seuquence numbers.
4355 */
4356 if (!IS_GEN2(dev_priv))
4357 dev->vblank_disable_immediate = true;
4358
4359 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
4360 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4361 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4362 }
4363
4364 if (IS_CHERRYVIEW(dev_priv)) {
4365 dev->driver->irq_handler = cherryview_irq_handler;
4366 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4367 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4368 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4369 dev->driver->enable_vblank = valleyview_enable_vblank;
4370 dev->driver->disable_vblank = valleyview_disable_vblank;
4371 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4372 } else if (IS_VALLEYVIEW(dev_priv)) {
4373 dev->driver->irq_handler = valleyview_irq_handler;
4374 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4375 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4376 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4377 dev->driver->enable_vblank = valleyview_enable_vblank;
4378 dev->driver->disable_vblank = valleyview_disable_vblank;
4379 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4380 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
4381 dev->driver->irq_handler = gen8_irq_handler;
4382 dev->driver->irq_preinstall = gen8_irq_reset;
4383 dev->driver->irq_postinstall = gen8_irq_postinstall;
4384 dev->driver->irq_uninstall = gen8_irq_uninstall;
4385 dev->driver->enable_vblank = gen8_enable_vblank;
4386 dev->driver->disable_vblank = gen8_disable_vblank;
4387 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4388 } else if (HAS_PCH_SPLIT(dev)) {
4389 dev->driver->irq_handler = ironlake_irq_handler;
4390 dev->driver->irq_preinstall = ironlake_irq_reset;
4391 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4392 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4393 dev->driver->enable_vblank = ironlake_enable_vblank;
4394 dev->driver->disable_vblank = ironlake_disable_vblank;
4395 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4396 } else {
4397 if (INTEL_INFO(dev_priv)->gen == 2) {
4398 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4399 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4400 dev->driver->irq_handler = i8xx_irq_handler;
4401 dev->driver->irq_uninstall = i8xx_irq_uninstall;
4402 } else if (INTEL_INFO(dev_priv)->gen == 3) {
4403 dev->driver->irq_preinstall = i915_irq_preinstall;
4404 dev->driver->irq_postinstall = i915_irq_postinstall;
4405 dev->driver->irq_uninstall = i915_irq_uninstall;
4406 dev->driver->irq_handler = i915_irq_handler;
4407 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4408 } else {
4409 dev->driver->irq_preinstall = i965_irq_preinstall;
4410 dev->driver->irq_postinstall = i965_irq_postinstall;
4411 dev->driver->irq_uninstall = i965_irq_uninstall;
4412 dev->driver->irq_handler = i965_irq_handler;
4413 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4414 }
4415 dev->driver->enable_vblank = i915_enable_vblank;
4416 dev->driver->disable_vblank = i915_disable_vblank;
4417 }
4418 }
4419
4420 /**
4421 * intel_hpd_init - initializes and enables hpd support
4422 * @dev_priv: i915 device instance
4423 *
4424 * This function enables the hotplug support. It requires that interrupts have
4425 * already been enabled with intel_irq_init_hw(). From this point on hotplug and
4426 * poll request can run concurrently to other code, so locking rules must be
4427 * obeyed.
4428 *
4429 * This is a separate step from interrupt enabling to simplify the locking rules
4430 * in the driver load and resume code.
4431 */
4432 void intel_hpd_init(struct drm_i915_private *dev_priv)
4433 {
4434 struct drm_device *dev = dev_priv->dev;
4435 struct drm_mode_config *mode_config = &dev->mode_config;
4436 struct drm_connector *connector;
4437 int i;
4438
4439 for (i = 1; i < HPD_NUM_PINS; i++) {
4440 dev_priv->hpd_stats[i].hpd_cnt = 0;
4441 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4442 }
4443 list_for_each_entry(connector, &mode_config->connector_list, head) {
4444 struct intel_connector *intel_connector = to_intel_connector(connector);
4445 connector->polled = intel_connector->polled;
4446 if (connector->encoder && !connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
4447 connector->polled = DRM_CONNECTOR_POLL_HPD;
4448 if (intel_connector->mst_port)
4449 connector->polled = DRM_CONNECTOR_POLL_HPD;
4450 }
4451
4452 /* Interrupt setup is already guaranteed to be single-threaded, this is
4453 * just to make the assert_spin_locked checks happy. */
4454 spin_lock_irq(&dev_priv->irq_lock);
4455 if (dev_priv->display.hpd_irq_setup)
4456 dev_priv->display.hpd_irq_setup(dev);
4457 spin_unlock_irq(&dev_priv->irq_lock);
4458 }
4459
4460 /**
4461 * intel_irq_install - enables the hardware interrupt
4462 * @dev_priv: i915 device instance
4463 *
4464 * This function enables the hardware interrupt handling, but leaves the hotplug
4465 * handling still disabled. It is called after intel_irq_init().
4466 *
4467 * In the driver load and resume code we need working interrupts in a few places
4468 * but don't want to deal with the hassle of concurrent probe and hotplug
4469 * workers. Hence the split into this two-stage approach.
4470 */
4471 int intel_irq_install(struct drm_i915_private *dev_priv)
4472 {
4473 /*
4474 * We enable some interrupt sources in our postinstall hooks, so mark
4475 * interrupts as enabled _before_ actually enabling them to avoid
4476 * special cases in our ordering checks.
4477 */
4478 dev_priv->pm.irqs_enabled = true;
4479
4480 return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
4481 }
4482
4483 /**
4484 * intel_irq_uninstall - finilizes all irq handling
4485 * @dev_priv: i915 device instance
4486 *
4487 * This stops interrupt and hotplug handling and unregisters and frees all
4488 * resources acquired in the init functions.
4489 */
4490 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4491 {
4492 drm_irq_uninstall(dev_priv->dev);
4493 intel_hpd_cancel_work(dev_priv);
4494 dev_priv->pm.irqs_enabled = false;
4495 }
4496
4497 /**
4498 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4499 * @dev_priv: i915 device instance
4500 *
4501 * This function is used to disable interrupts at runtime, both in the runtime
4502 * pm and the system suspend/resume code.
4503 */
4504 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4505 {
4506 dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
4507 dev_priv->pm.irqs_enabled = false;
4508 }
4509
4510 /**
4511 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4512 * @dev_priv: i915 device instance
4513 *
4514 * This function is used to enable interrupts at runtime, both in the runtime
4515 * pm and the system suspend/resume code.
4516 */
4517 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4518 {
4519 dev_priv->pm.irqs_enabled = true;
4520 dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
4521 dev_priv->dev->driver->irq_postinstall(dev_priv->dev);
4522 }
Linux kernel - Deliverables
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