1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include <linux/sysrq.h>
34 #include "intel_drv.h"
36 #define MAX_NOPID ((u32)~0)
39 * Interrupts that are always left unmasked.
41 * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
42 * we leave them always unmasked in IMR and then control enabling them through
45 #define I915_INTERRUPT_ENABLE_FIX (I915_ASLE_INTERRUPT | \
46 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
47 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
48 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
50 /** Interrupts that we mask and unmask at runtime. */
51 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
53 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
54 PIPE_VBLANK_INTERRUPT_STATUS)
56 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
57 PIPE_VBLANK_INTERRUPT_ENABLE)
59 #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
60 DRM_I915_VBLANK_PIPE_B)
63 igdng_enable_graphics_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
65 if ((dev_priv
->gt_irq_mask_reg
& mask
) != 0) {
66 dev_priv
->gt_irq_mask_reg
&= ~mask
;
67 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask_reg
);
68 (void) I915_READ(GTIMR
);
73 igdng_disable_graphics_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
75 if ((dev_priv
->gt_irq_mask_reg
& mask
) != mask
) {
76 dev_priv
->gt_irq_mask_reg
|= mask
;
77 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask_reg
);
78 (void) I915_READ(GTIMR
);
82 /* For display hotplug interrupt */
84 igdng_enable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
86 if ((dev_priv
->irq_mask_reg
& mask
) != 0) {
87 dev_priv
->irq_mask_reg
&= ~mask
;
88 I915_WRITE(DEIMR
, dev_priv
->irq_mask_reg
);
89 (void) I915_READ(DEIMR
);
94 igdng_disable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
96 if ((dev_priv
->irq_mask_reg
& mask
) != mask
) {
97 dev_priv
->irq_mask_reg
|= mask
;
98 I915_WRITE(DEIMR
, dev_priv
->irq_mask_reg
);
99 (void) I915_READ(DEIMR
);
104 i915_enable_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
106 if ((dev_priv
->irq_mask_reg
& mask
) != 0) {
107 dev_priv
->irq_mask_reg
&= ~mask
;
108 I915_WRITE(IMR
, dev_priv
->irq_mask_reg
);
109 (void) I915_READ(IMR
);
114 i915_disable_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
116 if ((dev_priv
->irq_mask_reg
& mask
) != mask
) {
117 dev_priv
->irq_mask_reg
|= mask
;
118 I915_WRITE(IMR
, dev_priv
->irq_mask_reg
);
119 (void) I915_READ(IMR
);
124 i915_pipestat(int pipe
)
134 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
136 if ((dev_priv
->pipestat
[pipe
] & mask
) != mask
) {
137 u32 reg
= i915_pipestat(pipe
);
139 dev_priv
->pipestat
[pipe
] |= mask
;
140 /* Enable the interrupt, clear any pending status */
141 I915_WRITE(reg
, dev_priv
->pipestat
[pipe
] | (mask
>> 16));
142 (void) I915_READ(reg
);
147 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
149 if ((dev_priv
->pipestat
[pipe
] & mask
) != 0) {
150 u32 reg
= i915_pipestat(pipe
);
152 dev_priv
->pipestat
[pipe
] &= ~mask
;
153 I915_WRITE(reg
, dev_priv
->pipestat
[pipe
]);
154 (void) I915_READ(reg
);
159 * i915_pipe_enabled - check if a pipe is enabled
161 * @pipe: pipe to check
163 * Reading certain registers when the pipe is disabled can hang the chip.
164 * Use this routine to make sure the PLL is running and the pipe is active
165 * before reading such registers if unsure.
168 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
170 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
171 unsigned long pipeconf
= pipe
? PIPEBCONF
: PIPEACONF
;
173 if (I915_READ(pipeconf
) & PIPEACONF_ENABLE
)
179 /* Called from drm generic code, passed a 'crtc', which
180 * we use as a pipe index
182 u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
184 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
185 unsigned long high_frame
;
186 unsigned long low_frame
;
187 u32 high1
, high2
, low
, count
;
189 high_frame
= pipe
? PIPEBFRAMEHIGH
: PIPEAFRAMEHIGH
;
190 low_frame
= pipe
? PIPEBFRAMEPIXEL
: PIPEAFRAMEPIXEL
;
192 if (!i915_pipe_enabled(dev
, pipe
)) {
193 DRM_DEBUG("trying to get vblank count for disabled pipe %d\n", pipe
);
198 * High & low register fields aren't synchronized, so make sure
199 * we get a low value that's stable across two reads of the high
203 high1
= ((I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
) >>
204 PIPE_FRAME_HIGH_SHIFT
);
205 low
= ((I915_READ(low_frame
) & PIPE_FRAME_LOW_MASK
) >>
206 PIPE_FRAME_LOW_SHIFT
);
207 high2
= ((I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
) >>
208 PIPE_FRAME_HIGH_SHIFT
);
209 } while (high1
!= high2
);
211 count
= (high1
<< 8) | low
;
216 u32
gm45_get_vblank_counter(struct drm_device
*dev
, int pipe
)
218 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
219 int reg
= pipe
? PIPEB_FRMCOUNT_GM45
: PIPEA_FRMCOUNT_GM45
;
221 if (!i915_pipe_enabled(dev
, pipe
)) {
222 DRM_DEBUG("trying to get vblank count for disabled pipe %d\n", pipe
);
226 return I915_READ(reg
);
230 * Handle hotplug events outside the interrupt handler proper.
232 static void i915_hotplug_work_func(struct work_struct
*work
)
234 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
236 struct drm_device
*dev
= dev_priv
->dev
;
237 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
238 struct drm_connector
*connector
;
240 if (mode_config
->num_connector
) {
241 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
242 struct intel_output
*intel_output
= to_intel_output(connector
);
244 if (intel_output
->hot_plug
)
245 (*intel_output
->hot_plug
) (intel_output
);
248 /* Just fire off a uevent and let userspace tell us what to do */
249 drm_sysfs_hotplug_event(dev
);
252 irqreturn_t
igdng_irq_handler(struct drm_device
*dev
)
254 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
257 u32 new_de_iir
, new_gt_iir
;
258 struct drm_i915_master_private
*master_priv
;
260 de_iir
= I915_READ(DEIIR
);
261 gt_iir
= I915_READ(GTIIR
);
264 if (de_iir
== 0 && gt_iir
== 0)
269 I915_WRITE(DEIIR
, de_iir
);
270 new_de_iir
= I915_READ(DEIIR
);
271 I915_WRITE(GTIIR
, gt_iir
);
272 new_gt_iir
= I915_READ(GTIIR
);
274 if (dev
->primary
->master
) {
275 master_priv
= dev
->primary
->master
->driver_priv
;
276 if (master_priv
->sarea_priv
)
277 master_priv
->sarea_priv
->last_dispatch
=
278 READ_BREADCRUMB(dev_priv
);
281 if (gt_iir
& GT_USER_INTERRUPT
) {
282 dev_priv
->mm
.irq_gem_seqno
= i915_get_gem_seqno(dev
);
283 DRM_WAKEUP(&dev_priv
->irq_queue
);
294 * i915_error_work_func - do process context error handling work
297 * Fire an error uevent so userspace can see that a hang or error
300 static void i915_error_work_func(struct work_struct
*work
)
302 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
304 struct drm_device
*dev
= dev_priv
->dev
;
305 char *event_string
= "ERROR=1";
306 char *envp
[] = { event_string
, NULL
};
308 DRM_DEBUG("generating error event\n");
310 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
, envp
);
314 * i915_capture_error_state - capture an error record for later analysis
317 * Should be called when an error is detected (either a hang or an error
318 * interrupt) to capture error state from the time of the error. Fills
319 * out a structure which becomes available in debugfs for user level tools
322 static void i915_capture_error_state(struct drm_device
*dev
)
324 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
325 struct drm_i915_error_state
*error
;
328 spin_lock_irqsave(&dev_priv
->error_lock
, flags
);
329 if (dev_priv
->first_error
)
332 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
334 DRM_DEBUG("out ot memory, not capturing error state\n");
338 error
->eir
= I915_READ(EIR
);
339 error
->pgtbl_er
= I915_READ(PGTBL_ER
);
340 error
->pipeastat
= I915_READ(PIPEASTAT
);
341 error
->pipebstat
= I915_READ(PIPEBSTAT
);
342 error
->instpm
= I915_READ(INSTPM
);
343 if (!IS_I965G(dev
)) {
344 error
->ipeir
= I915_READ(IPEIR
);
345 error
->ipehr
= I915_READ(IPEHR
);
346 error
->instdone
= I915_READ(INSTDONE
);
347 error
->acthd
= I915_READ(ACTHD
);
349 error
->ipeir
= I915_READ(IPEIR_I965
);
350 error
->ipehr
= I915_READ(IPEHR_I965
);
351 error
->instdone
= I915_READ(INSTDONE_I965
);
352 error
->instps
= I915_READ(INSTPS
);
353 error
->instdone1
= I915_READ(INSTDONE1
);
354 error
->acthd
= I915_READ(ACTHD_I965
);
357 do_gettimeofday(&error
->time
);
359 dev_priv
->first_error
= error
;
362 spin_unlock_irqrestore(&dev_priv
->error_lock
, flags
);
366 * i915_handle_error - handle an error interrupt
369 * Do some basic checking of regsiter state at error interrupt time and
370 * dump it to the syslog. Also call i915_capture_error_state() to make
371 * sure we get a record and make it available in debugfs. Fire a uevent
372 * so userspace knows something bad happened (should trigger collection
373 * of a ring dump etc.).
375 static void i915_handle_error(struct drm_device
*dev
)
377 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
378 u32 eir
= I915_READ(EIR
);
379 u32 pipea_stats
= I915_READ(PIPEASTAT
);
380 u32 pipeb_stats
= I915_READ(PIPEBSTAT
);
382 i915_capture_error_state(dev
);
384 printk(KERN_ERR
"render error detected, EIR: 0x%08x\n",
388 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
389 u32 ipeir
= I915_READ(IPEIR_I965
);
391 printk(KERN_ERR
" IPEIR: 0x%08x\n",
392 I915_READ(IPEIR_I965
));
393 printk(KERN_ERR
" IPEHR: 0x%08x\n",
394 I915_READ(IPEHR_I965
));
395 printk(KERN_ERR
" INSTDONE: 0x%08x\n",
396 I915_READ(INSTDONE_I965
));
397 printk(KERN_ERR
" INSTPS: 0x%08x\n",
399 printk(KERN_ERR
" INSTDONE1: 0x%08x\n",
400 I915_READ(INSTDONE1
));
401 printk(KERN_ERR
" ACTHD: 0x%08x\n",
402 I915_READ(ACTHD_I965
));
403 I915_WRITE(IPEIR_I965
, ipeir
);
404 (void)I915_READ(IPEIR_I965
);
406 if (eir
& GM45_ERROR_PAGE_TABLE
) {
407 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
408 printk(KERN_ERR
"page table error\n");
409 printk(KERN_ERR
" PGTBL_ER: 0x%08x\n",
411 I915_WRITE(PGTBL_ER
, pgtbl_err
);
412 (void)I915_READ(PGTBL_ER
);
417 if (eir
& I915_ERROR_PAGE_TABLE
) {
418 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
419 printk(KERN_ERR
"page table error\n");
420 printk(KERN_ERR
" PGTBL_ER: 0x%08x\n",
422 I915_WRITE(PGTBL_ER
, pgtbl_err
);
423 (void)I915_READ(PGTBL_ER
);
427 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
428 printk(KERN_ERR
"memory refresh error\n");
429 printk(KERN_ERR
"PIPEASTAT: 0x%08x\n",
431 printk(KERN_ERR
"PIPEBSTAT: 0x%08x\n",
433 /* pipestat has already been acked */
435 if (eir
& I915_ERROR_INSTRUCTION
) {
436 printk(KERN_ERR
"instruction error\n");
437 printk(KERN_ERR
" INSTPM: 0x%08x\n",
439 if (!IS_I965G(dev
)) {
440 u32 ipeir
= I915_READ(IPEIR
);
442 printk(KERN_ERR
" IPEIR: 0x%08x\n",
444 printk(KERN_ERR
" IPEHR: 0x%08x\n",
446 printk(KERN_ERR
" INSTDONE: 0x%08x\n",
447 I915_READ(INSTDONE
));
448 printk(KERN_ERR
" ACTHD: 0x%08x\n",
450 I915_WRITE(IPEIR
, ipeir
);
451 (void)I915_READ(IPEIR
);
453 u32 ipeir
= I915_READ(IPEIR_I965
);
455 printk(KERN_ERR
" IPEIR: 0x%08x\n",
456 I915_READ(IPEIR_I965
));
457 printk(KERN_ERR
" IPEHR: 0x%08x\n",
458 I915_READ(IPEHR_I965
));
459 printk(KERN_ERR
" INSTDONE: 0x%08x\n",
460 I915_READ(INSTDONE_I965
));
461 printk(KERN_ERR
" INSTPS: 0x%08x\n",
463 printk(KERN_ERR
" INSTDONE1: 0x%08x\n",
464 I915_READ(INSTDONE1
));
465 printk(KERN_ERR
" ACTHD: 0x%08x\n",
466 I915_READ(ACTHD_I965
));
467 I915_WRITE(IPEIR_I965
, ipeir
);
468 (void)I915_READ(IPEIR_I965
);
472 I915_WRITE(EIR
, eir
);
473 (void)I915_READ(EIR
);
474 eir
= I915_READ(EIR
);
477 * some errors might have become stuck,
480 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
481 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
482 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
485 if (dev_priv
->mm
.wedged
) {
487 * Wakeup waiting processes so they don't hang
489 printk("i915: Waking up sleeping processes\n");
490 DRM_WAKEUP(&dev_priv
->irq_queue
);
493 queue_work(dev_priv
->wq
, &dev_priv
->error_work
);
496 irqreturn_t
i915_driver_irq_handler(DRM_IRQ_ARGS
)
498 struct drm_device
*dev
= (struct drm_device
*) arg
;
499 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
500 struct drm_i915_master_private
*master_priv
;
502 u32 pipea_stats
, pipeb_stats
;
506 unsigned long irqflags
;
510 atomic_inc(&dev_priv
->irq_received
);
513 return igdng_irq_handler(dev
);
515 iir
= I915_READ(IIR
);
518 vblank_status
= I915_START_VBLANK_INTERRUPT_STATUS
;
519 vblank_enable
= PIPE_START_VBLANK_INTERRUPT_ENABLE
;
521 vblank_status
= I915_VBLANK_INTERRUPT_STATUS
;
522 vblank_enable
= I915_VBLANK_INTERRUPT_ENABLE
;
526 irq_received
= iir
!= 0;
528 /* Can't rely on pipestat interrupt bit in iir as it might
529 * have been cleared after the pipestat interrupt was received.
530 * It doesn't set the bit in iir again, but it still produces
531 * interrupts (for non-MSI).
533 spin_lock_irqsave(&dev_priv
->user_irq_lock
, irqflags
);
534 pipea_stats
= I915_READ(PIPEASTAT
);
535 pipeb_stats
= I915_READ(PIPEBSTAT
);
537 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
538 i915_handle_error(dev
);
541 * Clear the PIPE(A|B)STAT regs before the IIR
543 if (pipea_stats
& 0x8000ffff) {
544 if (pipea_stats
& PIPE_FIFO_UNDERRUN_STATUS
)
545 DRM_DEBUG("pipe a underrun\n");
546 I915_WRITE(PIPEASTAT
, pipea_stats
);
550 if (pipeb_stats
& 0x8000ffff) {
551 if (pipeb_stats
& PIPE_FIFO_UNDERRUN_STATUS
)
552 DRM_DEBUG("pipe b underrun\n");
553 I915_WRITE(PIPEBSTAT
, pipeb_stats
);
556 spin_unlock_irqrestore(&dev_priv
->user_irq_lock
, irqflags
);
563 /* Consume port. Then clear IIR or we'll miss events */
564 if ((I915_HAS_HOTPLUG(dev
)) &&
565 (iir
& I915_DISPLAY_PORT_INTERRUPT
)) {
566 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
568 DRM_DEBUG("hotplug event received, stat 0x%08x\n",
570 if (hotplug_status
& dev_priv
->hotplug_supported_mask
)
571 queue_work(dev_priv
->wq
,
572 &dev_priv
->hotplug_work
);
574 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
575 I915_READ(PORT_HOTPLUG_STAT
);
577 /* EOS interrupts occurs */
579 (hotplug_status
& CRT_EOS_INT_STATUS
)) {
582 DRM_DEBUG("EOS interrupt occurs\n");
583 /* status is already cleared */
584 temp
= I915_READ(ADPA
);
585 temp
&= ~ADPA_DAC_ENABLE
;
586 I915_WRITE(ADPA
, temp
);
588 temp
= I915_READ(PORT_HOTPLUG_EN
);
589 temp
&= ~CRT_EOS_INT_EN
;
590 I915_WRITE(PORT_HOTPLUG_EN
, temp
);
592 temp
= I915_READ(PORT_HOTPLUG_STAT
);
593 if (temp
& CRT_EOS_INT_STATUS
)
594 I915_WRITE(PORT_HOTPLUG_STAT
,
599 I915_WRITE(IIR
, iir
);
600 new_iir
= I915_READ(IIR
); /* Flush posted writes */
602 if (dev
->primary
->master
) {
603 master_priv
= dev
->primary
->master
->driver_priv
;
604 if (master_priv
->sarea_priv
)
605 master_priv
->sarea_priv
->last_dispatch
=
606 READ_BREADCRUMB(dev_priv
);
609 if (iir
& I915_USER_INTERRUPT
) {
610 dev_priv
->mm
.irq_gem_seqno
= i915_get_gem_seqno(dev
);
611 DRM_WAKEUP(&dev_priv
->irq_queue
);
612 dev_priv
->hangcheck_count
= 0;
613 mod_timer(&dev_priv
->hangcheck_timer
, jiffies
+ DRM_I915_HANGCHECK_PERIOD
);
616 if (pipea_stats
& vblank_status
) {
618 drm_handle_vblank(dev
, 0);
621 if (pipeb_stats
& vblank_status
) {
623 drm_handle_vblank(dev
, 1);
626 if ((pipeb_stats
& I915_LEGACY_BLC_EVENT_STATUS
) ||
627 (iir
& I915_ASLE_INTERRUPT
))
628 opregion_asle_intr(dev
);
630 /* With MSI, interrupts are only generated when iir
631 * transitions from zero to nonzero. If another bit got
632 * set while we were handling the existing iir bits, then
633 * we would never get another interrupt.
635 * This is fine on non-MSI as well, as if we hit this path
636 * we avoid exiting the interrupt handler only to generate
639 * Note that for MSI this could cause a stray interrupt report
640 * if an interrupt landed in the time between writing IIR and
641 * the posting read. This should be rare enough to never
642 * trigger the 99% of 100,000 interrupts test for disabling
651 static int i915_emit_irq(struct drm_device
* dev
)
653 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
654 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
657 i915_kernel_lost_context(dev
);
662 if (dev_priv
->counter
> 0x7FFFFFFFUL
)
663 dev_priv
->counter
= 1;
664 if (master_priv
->sarea_priv
)
665 master_priv
->sarea_priv
->last_enqueue
= dev_priv
->counter
;
668 OUT_RING(MI_STORE_DWORD_INDEX
);
669 OUT_RING(I915_BREADCRUMB_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
670 OUT_RING(dev_priv
->counter
);
671 OUT_RING(MI_USER_INTERRUPT
);
674 return dev_priv
->counter
;
677 void i915_user_irq_get(struct drm_device
*dev
)
679 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
680 unsigned long irqflags
;
682 spin_lock_irqsave(&dev_priv
->user_irq_lock
, irqflags
);
683 if (dev
->irq_enabled
&& (++dev_priv
->user_irq_refcount
== 1)) {
685 igdng_enable_graphics_irq(dev_priv
, GT_USER_INTERRUPT
);
687 i915_enable_irq(dev_priv
, I915_USER_INTERRUPT
);
689 spin_unlock_irqrestore(&dev_priv
->user_irq_lock
, irqflags
);
692 void i915_user_irq_put(struct drm_device
*dev
)
694 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
695 unsigned long irqflags
;
697 spin_lock_irqsave(&dev_priv
->user_irq_lock
, irqflags
);
698 BUG_ON(dev
->irq_enabled
&& dev_priv
->user_irq_refcount
<= 0);
699 if (dev
->irq_enabled
&& (--dev_priv
->user_irq_refcount
== 0)) {
701 igdng_disable_graphics_irq(dev_priv
, GT_USER_INTERRUPT
);
703 i915_disable_irq(dev_priv
, I915_USER_INTERRUPT
);
705 spin_unlock_irqrestore(&dev_priv
->user_irq_lock
, irqflags
);
708 static int i915_wait_irq(struct drm_device
* dev
, int irq_nr
)
710 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
711 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
714 DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr
,
715 READ_BREADCRUMB(dev_priv
));
717 if (READ_BREADCRUMB(dev_priv
) >= irq_nr
) {
718 if (master_priv
->sarea_priv
)
719 master_priv
->sarea_priv
->last_dispatch
= READ_BREADCRUMB(dev_priv
);
723 if (master_priv
->sarea_priv
)
724 master_priv
->sarea_priv
->perf_boxes
|= I915_BOX_WAIT
;
726 i915_user_irq_get(dev
);
727 DRM_WAIT_ON(ret
, dev_priv
->irq_queue
, 3 * DRM_HZ
,
728 READ_BREADCRUMB(dev_priv
) >= irq_nr
);
729 i915_user_irq_put(dev
);
732 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
733 READ_BREADCRUMB(dev_priv
), (int)dev_priv
->counter
);
739 /* Needs the lock as it touches the ring.
741 int i915_irq_emit(struct drm_device
*dev
, void *data
,
742 struct drm_file
*file_priv
)
744 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
745 drm_i915_irq_emit_t
*emit
= data
;
748 if (!dev_priv
|| !dev_priv
->ring
.virtual_start
) {
749 DRM_ERROR("called with no initialization\n");
753 RING_LOCK_TEST_WITH_RETURN(dev
, file_priv
);
755 mutex_lock(&dev
->struct_mutex
);
756 result
= i915_emit_irq(dev
);
757 mutex_unlock(&dev
->struct_mutex
);
759 if (DRM_COPY_TO_USER(emit
->irq_seq
, &result
, sizeof(int))) {
760 DRM_ERROR("copy_to_user\n");
767 /* Doesn't need the hardware lock.
769 int i915_irq_wait(struct drm_device
*dev
, void *data
,
770 struct drm_file
*file_priv
)
772 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
773 drm_i915_irq_wait_t
*irqwait
= data
;
776 DRM_ERROR("called with no initialization\n");
780 return i915_wait_irq(dev
, irqwait
->irq_seq
);
783 /* Called from drm generic code, passed 'crtc' which
784 * we use as a pipe index
786 int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
788 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
789 unsigned long irqflags
;
790 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
793 pipeconf
= I915_READ(pipeconf_reg
);
794 if (!(pipeconf
& PIPEACONF_ENABLE
))
800 spin_lock_irqsave(&dev_priv
->user_irq_lock
, irqflags
);
802 i915_enable_pipestat(dev_priv
, pipe
,
803 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
805 i915_enable_pipestat(dev_priv
, pipe
,
806 PIPE_VBLANK_INTERRUPT_ENABLE
);
807 spin_unlock_irqrestore(&dev_priv
->user_irq_lock
, irqflags
);
811 /* Called from drm generic code, passed 'crtc' which
812 * we use as a pipe index
814 void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
816 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
817 unsigned long irqflags
;
822 spin_lock_irqsave(&dev_priv
->user_irq_lock
, irqflags
);
823 i915_disable_pipestat(dev_priv
, pipe
,
824 PIPE_VBLANK_INTERRUPT_ENABLE
|
825 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
826 spin_unlock_irqrestore(&dev_priv
->user_irq_lock
, irqflags
);
829 void i915_enable_interrupt (struct drm_device
*dev
)
831 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
834 opregion_enable_asle(dev
);
835 dev_priv
->irq_enabled
= 1;
839 /* Set the vblank monitor pipe
841 int i915_vblank_pipe_set(struct drm_device
*dev
, void *data
,
842 struct drm_file
*file_priv
)
844 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
847 DRM_ERROR("called with no initialization\n");
854 int i915_vblank_pipe_get(struct drm_device
*dev
, void *data
,
855 struct drm_file
*file_priv
)
857 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
858 drm_i915_vblank_pipe_t
*pipe
= data
;
861 DRM_ERROR("called with no initialization\n");
865 pipe
->pipe
= DRM_I915_VBLANK_PIPE_A
| DRM_I915_VBLANK_PIPE_B
;
871 * Schedule buffer swap at given vertical blank.
873 int i915_vblank_swap(struct drm_device
*dev
, void *data
,
874 struct drm_file
*file_priv
)
876 /* The delayed swap mechanism was fundamentally racy, and has been
877 * removed. The model was that the client requested a delayed flip/swap
878 * from the kernel, then waited for vblank before continuing to perform
879 * rendering. The problem was that the kernel might wake the client
880 * up before it dispatched the vblank swap (since the lock has to be
881 * held while touching the ringbuffer), in which case the client would
882 * clear and start the next frame before the swap occurred, and
883 * flicker would occur in addition to likely missing the vblank.
885 * In the absence of this ioctl, userland falls back to a correct path
886 * of waiting for a vblank, then dispatching the swap on its own.
887 * Context switching to userland and back is plenty fast enough for
888 * meeting the requirements of vblank swapping.
893 struct drm_i915_gem_request
*i915_get_tail_request(struct drm_device
*dev
) {
894 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
895 return list_entry(dev_priv
->mm
.request_list
.prev
, struct drm_i915_gem_request
, list
);
899 * This is called when the chip hasn't reported back with completed
900 * batchbuffers in a long time. The first time this is called we simply record
901 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
902 * again, we assume the chip is wedged and try to fix it.
904 void i915_hangcheck_elapsed(unsigned long data
)
906 struct drm_device
*dev
= (struct drm_device
*)data
;
907 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
911 acthd
= I915_READ(ACTHD
);
913 acthd
= I915_READ(ACTHD_I965
);
915 /* If all work is done then ACTHD clearly hasn't advanced. */
916 if (list_empty(&dev_priv
->mm
.request_list
) ||
917 i915_seqno_passed(i915_get_gem_seqno(dev
), i915_get_tail_request(dev
)->seqno
)) {
918 dev_priv
->hangcheck_count
= 0;
922 if (dev_priv
->last_acthd
== acthd
&& dev_priv
->hangcheck_count
> 0) {
923 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
924 dev_priv
->mm
.wedged
= true; /* Hopefully this is atomic */
925 i915_handle_error(dev
);
929 /* Reset timer case chip hangs without another request being added */
930 mod_timer(&dev_priv
->hangcheck_timer
, jiffies
+ DRM_I915_HANGCHECK_PERIOD
);
932 if (acthd
!= dev_priv
->last_acthd
)
933 dev_priv
->hangcheck_count
= 0;
935 dev_priv
->hangcheck_count
++;
937 dev_priv
->last_acthd
= acthd
;
942 static void igdng_irq_preinstall(struct drm_device
*dev
)
944 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
946 I915_WRITE(HWSTAM
, 0xeffe);
948 /* XXX hotplug from PCH */
950 I915_WRITE(DEIMR
, 0xffffffff);
951 I915_WRITE(DEIER
, 0x0);
952 (void) I915_READ(DEIER
);
955 I915_WRITE(GTIMR
, 0xffffffff);
956 I915_WRITE(GTIER
, 0x0);
957 (void) I915_READ(GTIER
);
960 static int igdng_irq_postinstall(struct drm_device
*dev
)
962 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
963 /* enable kind of interrupts always enabled */
964 u32 display_mask
= DE_MASTER_IRQ_CONTROL
/*| DE_PCH_EVENT */;
965 u32 render_mask
= GT_USER_INTERRUPT
;
967 dev_priv
->irq_mask_reg
= ~display_mask
;
968 dev_priv
->de_irq_enable_reg
= display_mask
;
970 /* should always can generate irq */
971 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
972 I915_WRITE(DEIMR
, dev_priv
->irq_mask_reg
);
973 I915_WRITE(DEIER
, dev_priv
->de_irq_enable_reg
);
974 (void) I915_READ(DEIER
);
976 /* user interrupt should be enabled, but masked initial */
977 dev_priv
->gt_irq_mask_reg
= 0xffffffff;
978 dev_priv
->gt_irq_enable_reg
= render_mask
;
980 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
981 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask_reg
);
982 I915_WRITE(GTIER
, dev_priv
->gt_irq_enable_reg
);
983 (void) I915_READ(GTIER
);
988 void i915_driver_irq_preinstall(struct drm_device
* dev
)
990 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
992 atomic_set(&dev_priv
->irq_received
, 0);
994 INIT_WORK(&dev_priv
->hotplug_work
, i915_hotplug_work_func
);
995 INIT_WORK(&dev_priv
->error_work
, i915_error_work_func
);
998 igdng_irq_preinstall(dev
);
1002 if (I915_HAS_HOTPLUG(dev
)) {
1003 I915_WRITE(PORT_HOTPLUG_EN
, 0);
1004 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
1007 I915_WRITE(HWSTAM
, 0xeffe);
1008 I915_WRITE(PIPEASTAT
, 0);
1009 I915_WRITE(PIPEBSTAT
, 0);
1010 I915_WRITE(IMR
, 0xffffffff);
1011 I915_WRITE(IER
, 0x0);
1012 (void) I915_READ(IER
);
1015 int i915_driver_irq_postinstall(struct drm_device
*dev
)
1017 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1018 u32 enable_mask
= I915_INTERRUPT_ENABLE_FIX
| I915_INTERRUPT_ENABLE_VAR
;
1021 DRM_INIT_WAITQUEUE(&dev_priv
->irq_queue
);
1023 dev_priv
->vblank_pipe
= DRM_I915_VBLANK_PIPE_A
| DRM_I915_VBLANK_PIPE_B
;
1026 return igdng_irq_postinstall(dev
);
1028 /* Unmask the interrupts that we always want on. */
1029 dev_priv
->irq_mask_reg
= ~I915_INTERRUPT_ENABLE_FIX
;
1031 dev_priv
->pipestat
[0] = 0;
1032 dev_priv
->pipestat
[1] = 0;
1034 if (I915_HAS_HOTPLUG(dev
)) {
1035 u32 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
1037 /* Leave other bits alone */
1038 hotplug_en
|= HOTPLUG_EN_MASK
;
1039 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
1041 dev_priv
->hotplug_supported_mask
= CRT_HOTPLUG_INT_STATUS
|
1042 TV_HOTPLUG_INT_STATUS
| SDVOC_HOTPLUG_INT_STATUS
|
1043 SDVOB_HOTPLUG_INT_STATUS
;
1045 dev_priv
->hotplug_supported_mask
|=
1046 HDMIB_HOTPLUG_INT_STATUS
|
1047 HDMIC_HOTPLUG_INT_STATUS
|
1048 HDMID_HOTPLUG_INT_STATUS
;
1050 /* Enable in IER... */
1051 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
1052 /* and unmask in IMR */
1053 i915_enable_irq(dev_priv
, I915_DISPLAY_PORT_INTERRUPT
);
1057 * Enable some error detection, note the instruction error mask
1058 * bit is reserved, so we leave it masked.
1061 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
1062 GM45_ERROR_MEM_PRIV
|
1063 GM45_ERROR_CP_PRIV
|
1064 I915_ERROR_MEMORY_REFRESH
);
1066 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
1067 I915_ERROR_MEMORY_REFRESH
);
1069 I915_WRITE(EMR
, error_mask
);
1071 /* Disable pipe interrupt enables, clear pending pipe status */
1072 I915_WRITE(PIPEASTAT
, I915_READ(PIPEASTAT
) & 0x8000ffff);
1073 I915_WRITE(PIPEBSTAT
, I915_READ(PIPEBSTAT
) & 0x8000ffff);
1074 /* Clear pending interrupt status */
1075 I915_WRITE(IIR
, I915_READ(IIR
));
1077 I915_WRITE(IER
, enable_mask
);
1078 I915_WRITE(IMR
, dev_priv
->irq_mask_reg
);
1079 (void) I915_READ(IER
);
1081 opregion_enable_asle(dev
);
1086 static void igdng_irq_uninstall(struct drm_device
*dev
)
1088 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1089 I915_WRITE(HWSTAM
, 0xffffffff);
1091 I915_WRITE(DEIMR
, 0xffffffff);
1092 I915_WRITE(DEIER
, 0x0);
1093 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
1095 I915_WRITE(GTIMR
, 0xffffffff);
1096 I915_WRITE(GTIER
, 0x0);
1097 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
1100 void i915_driver_irq_uninstall(struct drm_device
* dev
)
1102 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1107 dev_priv
->vblank_pipe
= 0;
1109 if (IS_IGDNG(dev
)) {
1110 igdng_irq_uninstall(dev
);
1114 if (I915_HAS_HOTPLUG(dev
)) {
1115 I915_WRITE(PORT_HOTPLUG_EN
, 0);
1116 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
1119 I915_WRITE(HWSTAM
, 0xffffffff);
1120 I915_WRITE(PIPEASTAT
, 0);
1121 I915_WRITE(PIPEBSTAT
, 0);
1122 I915_WRITE(IMR
, 0xffffffff);
1123 I915_WRITE(IER
, 0x0);
1125 I915_WRITE(PIPEASTAT
, I915_READ(PIPEASTAT
) & 0x8000ffff);
1126 I915_WRITE(PIPEBSTAT
, I915_READ(PIPEBSTAT
) & 0x8000ffff);
1127 I915_WRITE(IIR
, I915_READ(IIR
));