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drm/i915: WARN if we receive any gen9 rps interrupts
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
34 #include <drm/drmP.h>
35 #include <drm/i915_drm.h>
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "intel_drv.h"
39
40 /**
41 * DOC: interrupt handling
42 *
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
46 */
47
48 static const u32 hpd_ibx[] = {
49 [HPD_CRT] = SDE_CRT_HOTPLUG,
50 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
51 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
52 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
53 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
54 };
55
56 static const u32 hpd_cpt[] = {
57 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
58 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
59 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
60 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
61 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
62 };
63
64 static const u32 hpd_mask_i915[] = {
65 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
66 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
67 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
68 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
69 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
70 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
71 };
72
73 static const u32 hpd_status_g4x[] = {
74 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
75 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
76 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
77 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
78 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
79 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
80 };
81
82 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
83 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
84 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
85 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
86 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
87 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
88 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
89 };
90
91 /* IIR can theoretically queue up two events. Be paranoid. */
92 #define GEN8_IRQ_RESET_NDX(type, which) do { \
93 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
94 POSTING_READ(GEN8_##type##_IMR(which)); \
95 I915_WRITE(GEN8_##type##_IER(which), 0); \
96 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
97 POSTING_READ(GEN8_##type##_IIR(which)); \
98 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
99 POSTING_READ(GEN8_##type##_IIR(which)); \
100 } while (0)
101
102 #define GEN5_IRQ_RESET(type) do { \
103 I915_WRITE(type##IMR, 0xffffffff); \
104 POSTING_READ(type##IMR); \
105 I915_WRITE(type##IER, 0); \
106 I915_WRITE(type##IIR, 0xffffffff); \
107 POSTING_READ(type##IIR); \
108 I915_WRITE(type##IIR, 0xffffffff); \
109 POSTING_READ(type##IIR); \
110 } while (0)
111
112 /*
113 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
114 */
115 #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
116 u32 val = I915_READ(reg); \
117 if (val) { \
118 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
119 (reg), val); \
120 I915_WRITE((reg), 0xffffffff); \
121 POSTING_READ(reg); \
122 I915_WRITE((reg), 0xffffffff); \
123 POSTING_READ(reg); \
124 } \
125 } while (0)
126
127 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
128 GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
129 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
130 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
131 POSTING_READ(GEN8_##type##_IMR(which)); \
132 } while (0)
133
134 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
135 GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
136 I915_WRITE(type##IER, (ier_val)); \
137 I915_WRITE(type##IMR, (imr_val)); \
138 POSTING_READ(type##IMR); \
139 } while (0)
140
141 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
142
143 /* For display hotplug interrupt */
144 void
145 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
146 {
147 assert_spin_locked(&dev_priv->irq_lock);
148
149 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
150 return;
151
152 if ((dev_priv->irq_mask & mask) != 0) {
153 dev_priv->irq_mask &= ~mask;
154 I915_WRITE(DEIMR, dev_priv->irq_mask);
155 POSTING_READ(DEIMR);
156 }
157 }
158
159 void
160 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
161 {
162 assert_spin_locked(&dev_priv->irq_lock);
163
164 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
165 return;
166
167 if ((dev_priv->irq_mask & mask) != mask) {
168 dev_priv->irq_mask |= mask;
169 I915_WRITE(DEIMR, dev_priv->irq_mask);
170 POSTING_READ(DEIMR);
171 }
172 }
173
174 /**
175 * ilk_update_gt_irq - update GTIMR
176 * @dev_priv: driver private
177 * @interrupt_mask: mask of interrupt bits to update
178 * @enabled_irq_mask: mask of interrupt bits to enable
179 */
180 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
181 uint32_t interrupt_mask,
182 uint32_t enabled_irq_mask)
183 {
184 assert_spin_locked(&dev_priv->irq_lock);
185
186 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
187 return;
188
189 dev_priv->gt_irq_mask &= ~interrupt_mask;
190 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
191 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
192 POSTING_READ(GTIMR);
193 }
194
195 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
196 {
197 ilk_update_gt_irq(dev_priv, mask, mask);
198 }
199
200 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
201 {
202 ilk_update_gt_irq(dev_priv, mask, 0);
203 }
204
205 static u32 gen6_pm_iir(struct drm_i915_private *dev_priv)
206 {
207 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
208 }
209
210 static u32 gen6_pm_imr(struct drm_i915_private *dev_priv)
211 {
212 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
213 }
214
215 static u32 gen6_pm_ier(struct drm_i915_private *dev_priv)
216 {
217 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
218 }
219
220 /**
221 * snb_update_pm_irq - update GEN6_PMIMR
222 * @dev_priv: driver private
223 * @interrupt_mask: mask of interrupt bits to update
224 * @enabled_irq_mask: mask of interrupt bits to enable
225 */
226 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
227 uint32_t interrupt_mask,
228 uint32_t enabled_irq_mask)
229 {
230 uint32_t new_val;
231
232 assert_spin_locked(&dev_priv->irq_lock);
233
234 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
235 return;
236
237 new_val = dev_priv->pm_irq_mask;
238 new_val &= ~interrupt_mask;
239 new_val |= (~enabled_irq_mask & interrupt_mask);
240
241 if (new_val != dev_priv->pm_irq_mask) {
242 dev_priv->pm_irq_mask = new_val;
243 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
244 POSTING_READ(gen6_pm_imr(dev_priv));
245 }
246 }
247
248 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
249 {
250 snb_update_pm_irq(dev_priv, mask, mask);
251 }
252
253 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
254 {
255 snb_update_pm_irq(dev_priv, mask, 0);
256 }
257
258 void gen6_enable_rps_interrupts(struct drm_device *dev)
259 {
260 struct drm_i915_private *dev_priv = dev->dev_private;
261
262 spin_lock_irq(&dev_priv->irq_lock);
263 WARN_ON(dev_priv->rps.pm_iir);
264 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
265 I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events);
266 spin_unlock_irq(&dev_priv->irq_lock);
267 }
268
269 void gen6_disable_rps_interrupts(struct drm_device *dev)
270 {
271 struct drm_i915_private *dev_priv = dev->dev_private;
272
273 I915_WRITE(GEN6_PMINTRMSK, INTEL_INFO(dev_priv)->gen >= 8 ?
274 ~GEN8_PMINTR_REDIRECT_TO_NON_DISP : ~0);
275 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
276 ~dev_priv->pm_rps_events);
277 /* Complete PM interrupt masking here doesn't race with the rps work
278 * item again unmasking PM interrupts because that is using a different
279 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
280 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
281
282 spin_lock_irq(&dev_priv->irq_lock);
283 dev_priv->rps.pm_iir = 0;
284 spin_unlock_irq(&dev_priv->irq_lock);
285
286 I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events);
287 }
288
289 /**
290 * ibx_display_interrupt_update - update SDEIMR
291 * @dev_priv: driver private
292 * @interrupt_mask: mask of interrupt bits to update
293 * @enabled_irq_mask: mask of interrupt bits to enable
294 */
295 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
296 uint32_t interrupt_mask,
297 uint32_t enabled_irq_mask)
298 {
299 uint32_t sdeimr = I915_READ(SDEIMR);
300 sdeimr &= ~interrupt_mask;
301 sdeimr |= (~enabled_irq_mask & interrupt_mask);
302
303 assert_spin_locked(&dev_priv->irq_lock);
304
305 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
306 return;
307
308 I915_WRITE(SDEIMR, sdeimr);
309 POSTING_READ(SDEIMR);
310 }
311
312 static void
313 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
314 u32 enable_mask, u32 status_mask)
315 {
316 u32 reg = PIPESTAT(pipe);
317 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
318
319 assert_spin_locked(&dev_priv->irq_lock);
320 WARN_ON(!intel_irqs_enabled(dev_priv));
321
322 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
323 status_mask & ~PIPESTAT_INT_STATUS_MASK,
324 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
325 pipe_name(pipe), enable_mask, status_mask))
326 return;
327
328 if ((pipestat & enable_mask) == enable_mask)
329 return;
330
331 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
332
333 /* Enable the interrupt, clear any pending status */
334 pipestat |= enable_mask | status_mask;
335 I915_WRITE(reg, pipestat);
336 POSTING_READ(reg);
337 }
338
339 static void
340 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
341 u32 enable_mask, u32 status_mask)
342 {
343 u32 reg = PIPESTAT(pipe);
344 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
345
346 assert_spin_locked(&dev_priv->irq_lock);
347 WARN_ON(!intel_irqs_enabled(dev_priv));
348
349 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
350 status_mask & ~PIPESTAT_INT_STATUS_MASK,
351 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
352 pipe_name(pipe), enable_mask, status_mask))
353 return;
354
355 if ((pipestat & enable_mask) == 0)
356 return;
357
358 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
359
360 pipestat &= ~enable_mask;
361 I915_WRITE(reg, pipestat);
362 POSTING_READ(reg);
363 }
364
365 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
366 {
367 u32 enable_mask = status_mask << 16;
368
369 /*
370 * On pipe A we don't support the PSR interrupt yet,
371 * on pipe B and C the same bit MBZ.
372 */
373 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
374 return 0;
375 /*
376 * On pipe B and C we don't support the PSR interrupt yet, on pipe
377 * A the same bit is for perf counters which we don't use either.
378 */
379 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
380 return 0;
381
382 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
383 SPRITE0_FLIP_DONE_INT_EN_VLV |
384 SPRITE1_FLIP_DONE_INT_EN_VLV);
385 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
386 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
387 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
388 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
389
390 return enable_mask;
391 }
392
393 void
394 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
395 u32 status_mask)
396 {
397 u32 enable_mask;
398
399 if (IS_VALLEYVIEW(dev_priv->dev))
400 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
401 status_mask);
402 else
403 enable_mask = status_mask << 16;
404 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
405 }
406
407 void
408 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
409 u32 status_mask)
410 {
411 u32 enable_mask;
412
413 if (IS_VALLEYVIEW(dev_priv->dev))
414 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
415 status_mask);
416 else
417 enable_mask = status_mask << 16;
418 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
419 }
420
421 /**
422 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
423 */
424 static void i915_enable_asle_pipestat(struct drm_device *dev)
425 {
426 struct drm_i915_private *dev_priv = dev->dev_private;
427
428 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
429 return;
430
431 spin_lock_irq(&dev_priv->irq_lock);
432
433 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
434 if (INTEL_INFO(dev)->gen >= 4)
435 i915_enable_pipestat(dev_priv, PIPE_A,
436 PIPE_LEGACY_BLC_EVENT_STATUS);
437
438 spin_unlock_irq(&dev_priv->irq_lock);
439 }
440
441 /**
442 * i915_pipe_enabled - check if a pipe is enabled
443 * @dev: DRM device
444 * @pipe: pipe to check
445 *
446 * Reading certain registers when the pipe is disabled can hang the chip.
447 * Use this routine to make sure the PLL is running and the pipe is active
448 * before reading such registers if unsure.
449 */
450 static int
451 i915_pipe_enabled(struct drm_device *dev, int pipe)
452 {
453 struct drm_i915_private *dev_priv = dev->dev_private;
454
455 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
456 /* Locking is horribly broken here, but whatever. */
457 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
458 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
459
460 return intel_crtc->active;
461 } else {
462 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
463 }
464 }
465
466 /*
467 * This timing diagram depicts the video signal in and
468 * around the vertical blanking period.
469 *
470 * Assumptions about the fictitious mode used in this example:
471 * vblank_start >= 3
472 * vsync_start = vblank_start + 1
473 * vsync_end = vblank_start + 2
474 * vtotal = vblank_start + 3
475 *
476 * start of vblank:
477 * latch double buffered registers
478 * increment frame counter (ctg+)
479 * generate start of vblank interrupt (gen4+)
480 * |
481 * | frame start:
482 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
483 * | may be shifted forward 1-3 extra lines via PIPECONF
484 * | |
485 * | | start of vsync:
486 * | | generate vsync interrupt
487 * | | |
488 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
489 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
490 * ----va---> <-----------------vb--------------------> <--------va-------------
491 * | | <----vs-----> |
492 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
493 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
494 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
495 * | | |
496 * last visible pixel first visible pixel
497 * | increment frame counter (gen3/4)
498 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
499 *
500 * x = horizontal active
501 * _ = horizontal blanking
502 * hs = horizontal sync
503 * va = vertical active
504 * vb = vertical blanking
505 * vs = vertical sync
506 * vbs = vblank_start (number)
507 *
508 * Summary:
509 * - most events happen at the start of horizontal sync
510 * - frame start happens at the start of horizontal blank, 1-4 lines
511 * (depending on PIPECONF settings) after the start of vblank
512 * - gen3/4 pixel and frame counter are synchronized with the start
513 * of horizontal active on the first line of vertical active
514 */
515
516 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
517 {
518 /* Gen2 doesn't have a hardware frame counter */
519 return 0;
520 }
521
522 /* Called from drm generic code, passed a 'crtc', which
523 * we use as a pipe index
524 */
525 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
526 {
527 struct drm_i915_private *dev_priv = dev->dev_private;
528 unsigned long high_frame;
529 unsigned long low_frame;
530 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
531
532 if (!i915_pipe_enabled(dev, pipe)) {
533 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
534 "pipe %c\n", pipe_name(pipe));
535 return 0;
536 }
537
538 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
539 struct intel_crtc *intel_crtc =
540 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
541 const struct drm_display_mode *mode =
542 &intel_crtc->config.adjusted_mode;
543
544 htotal = mode->crtc_htotal;
545 hsync_start = mode->crtc_hsync_start;
546 vbl_start = mode->crtc_vblank_start;
547 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
548 vbl_start = DIV_ROUND_UP(vbl_start, 2);
549 } else {
550 enum transcoder cpu_transcoder = (enum transcoder) pipe;
551
552 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
553 hsync_start = (I915_READ(HSYNC(cpu_transcoder)) & 0x1fff) + 1;
554 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
555 if ((I915_READ(PIPECONF(cpu_transcoder)) &
556 PIPECONF_INTERLACE_MASK) != PIPECONF_PROGRESSIVE)
557 vbl_start = DIV_ROUND_UP(vbl_start, 2);
558 }
559
560 /* Convert to pixel count */
561 vbl_start *= htotal;
562
563 /* Start of vblank event occurs at start of hsync */
564 vbl_start -= htotal - hsync_start;
565
566 high_frame = PIPEFRAME(pipe);
567 low_frame = PIPEFRAMEPIXEL(pipe);
568
569 /*
570 * High & low register fields aren't synchronized, so make sure
571 * we get a low value that's stable across two reads of the high
572 * register.
573 */
574 do {
575 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
576 low = I915_READ(low_frame);
577 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
578 } while (high1 != high2);
579
580 high1 >>= PIPE_FRAME_HIGH_SHIFT;
581 pixel = low & PIPE_PIXEL_MASK;
582 low >>= PIPE_FRAME_LOW_SHIFT;
583
584 /*
585 * The frame counter increments at beginning of active.
586 * Cook up a vblank counter by also checking the pixel
587 * counter against vblank start.
588 */
589 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
590 }
591
592 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
593 {
594 struct drm_i915_private *dev_priv = dev->dev_private;
595 int reg = PIPE_FRMCOUNT_GM45(pipe);
596
597 if (!i915_pipe_enabled(dev, pipe)) {
598 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
599 "pipe %c\n", pipe_name(pipe));
600 return 0;
601 }
602
603 return I915_READ(reg);
604 }
605
606 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
607 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
608
609 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
610 {
611 struct drm_device *dev = crtc->base.dev;
612 struct drm_i915_private *dev_priv = dev->dev_private;
613 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
614 enum pipe pipe = crtc->pipe;
615 int position, vtotal;
616
617 vtotal = mode->crtc_vtotal;
618 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
619 vtotal /= 2;
620
621 if (IS_GEN2(dev))
622 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
623 else
624 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
625
626 /*
627 * See update_scanline_offset() for the details on the
628 * scanline_offset adjustment.
629 */
630 return (position + crtc->scanline_offset) % vtotal;
631 }
632
633 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
634 unsigned int flags, int *vpos, int *hpos,
635 ktime_t *stime, ktime_t *etime)
636 {
637 struct drm_i915_private *dev_priv = dev->dev_private;
638 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
639 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
640 const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
641 int position;
642 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
643 bool in_vbl = true;
644 int ret = 0;
645 unsigned long irqflags;
646
647 if (!intel_crtc->active) {
648 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
649 "pipe %c\n", pipe_name(pipe));
650 return 0;
651 }
652
653 htotal = mode->crtc_htotal;
654 hsync_start = mode->crtc_hsync_start;
655 vtotal = mode->crtc_vtotal;
656 vbl_start = mode->crtc_vblank_start;
657 vbl_end = mode->crtc_vblank_end;
658
659 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
660 vbl_start = DIV_ROUND_UP(vbl_start, 2);
661 vbl_end /= 2;
662 vtotal /= 2;
663 }
664
665 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
666
667 /*
668 * Lock uncore.lock, as we will do multiple timing critical raw
669 * register reads, potentially with preemption disabled, so the
670 * following code must not block on uncore.lock.
671 */
672 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
673
674 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
675
676 /* Get optional system timestamp before query. */
677 if (stime)
678 *stime = ktime_get();
679
680 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
681 /* No obvious pixelcount register. Only query vertical
682 * scanout position from Display scan line register.
683 */
684 position = __intel_get_crtc_scanline(intel_crtc);
685 } else {
686 /* Have access to pixelcount since start of frame.
687 * We can split this into vertical and horizontal
688 * scanout position.
689 */
690 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
691
692 /* convert to pixel counts */
693 vbl_start *= htotal;
694 vbl_end *= htotal;
695 vtotal *= htotal;
696
697 /*
698 * In interlaced modes, the pixel counter counts all pixels,
699 * so one field will have htotal more pixels. In order to avoid
700 * the reported position from jumping backwards when the pixel
701 * counter is beyond the length of the shorter field, just
702 * clamp the position the length of the shorter field. This
703 * matches how the scanline counter based position works since
704 * the scanline counter doesn't count the two half lines.
705 */
706 if (position >= vtotal)
707 position = vtotal - 1;
708
709 /*
710 * Start of vblank interrupt is triggered at start of hsync,
711 * just prior to the first active line of vblank. However we
712 * consider lines to start at the leading edge of horizontal
713 * active. So, should we get here before we've crossed into
714 * the horizontal active of the first line in vblank, we would
715 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
716 * always add htotal-hsync_start to the current pixel position.
717 */
718 position = (position + htotal - hsync_start) % vtotal;
719 }
720
721 /* Get optional system timestamp after query. */
722 if (etime)
723 *etime = ktime_get();
724
725 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
726
727 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
728
729 in_vbl = position >= vbl_start && position < vbl_end;
730
731 /*
732 * While in vblank, position will be negative
733 * counting up towards 0 at vbl_end. And outside
734 * vblank, position will be positive counting
735 * up since vbl_end.
736 */
737 if (position >= vbl_start)
738 position -= vbl_end;
739 else
740 position += vtotal - vbl_end;
741
742 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
743 *vpos = position;
744 *hpos = 0;
745 } else {
746 *vpos = position / htotal;
747 *hpos = position - (*vpos * htotal);
748 }
749
750 /* In vblank? */
751 if (in_vbl)
752 ret |= DRM_SCANOUTPOS_IN_VBLANK;
753
754 return ret;
755 }
756
757 int intel_get_crtc_scanline(struct intel_crtc *crtc)
758 {
759 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
760 unsigned long irqflags;
761 int position;
762
763 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
764 position = __intel_get_crtc_scanline(crtc);
765 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
766
767 return position;
768 }
769
770 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
771 int *max_error,
772 struct timeval *vblank_time,
773 unsigned flags)
774 {
775 struct drm_crtc *crtc;
776
777 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
778 DRM_ERROR("Invalid crtc %d\n", pipe);
779 return -EINVAL;
780 }
781
782 /* Get drm_crtc to timestamp: */
783 crtc = intel_get_crtc_for_pipe(dev, pipe);
784 if (crtc == NULL) {
785 DRM_ERROR("Invalid crtc %d\n", pipe);
786 return -EINVAL;
787 }
788
789 if (!crtc->enabled) {
790 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
791 return -EBUSY;
792 }
793
794 /* Helper routine in DRM core does all the work: */
795 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
796 vblank_time, flags,
797 crtc,
798 &to_intel_crtc(crtc)->config.adjusted_mode);
799 }
800
801 static bool intel_hpd_irq_event(struct drm_device *dev,
802 struct drm_connector *connector)
803 {
804 enum drm_connector_status old_status;
805
806 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
807 old_status = connector->status;
808
809 connector->status = connector->funcs->detect(connector, false);
810 if (old_status == connector->status)
811 return false;
812
813 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
814 connector->base.id,
815 connector->name,
816 drm_get_connector_status_name(old_status),
817 drm_get_connector_status_name(connector->status));
818
819 return true;
820 }
821
822 static void i915_digport_work_func(struct work_struct *work)
823 {
824 struct drm_i915_private *dev_priv =
825 container_of(work, struct drm_i915_private, dig_port_work);
826 u32 long_port_mask, short_port_mask;
827 struct intel_digital_port *intel_dig_port;
828 int i, ret;
829 u32 old_bits = 0;
830
831 spin_lock_irq(&dev_priv->irq_lock);
832 long_port_mask = dev_priv->long_hpd_port_mask;
833 dev_priv->long_hpd_port_mask = 0;
834 short_port_mask = dev_priv->short_hpd_port_mask;
835 dev_priv->short_hpd_port_mask = 0;
836 spin_unlock_irq(&dev_priv->irq_lock);
837
838 for (i = 0; i < I915_MAX_PORTS; i++) {
839 bool valid = false;
840 bool long_hpd = false;
841 intel_dig_port = dev_priv->hpd_irq_port[i];
842 if (!intel_dig_port || !intel_dig_port->hpd_pulse)
843 continue;
844
845 if (long_port_mask & (1 << i)) {
846 valid = true;
847 long_hpd = true;
848 } else if (short_port_mask & (1 << i))
849 valid = true;
850
851 if (valid) {
852 ret = intel_dig_port->hpd_pulse(intel_dig_port, long_hpd);
853 if (ret == true) {
854 /* if we get true fallback to old school hpd */
855 old_bits |= (1 << intel_dig_port->base.hpd_pin);
856 }
857 }
858 }
859
860 if (old_bits) {
861 spin_lock_irq(&dev_priv->irq_lock);
862 dev_priv->hpd_event_bits |= old_bits;
863 spin_unlock_irq(&dev_priv->irq_lock);
864 schedule_work(&dev_priv->hotplug_work);
865 }
866 }
867
868 /*
869 * Handle hotplug events outside the interrupt handler proper.
870 */
871 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
872
873 static void i915_hotplug_work_func(struct work_struct *work)
874 {
875 struct drm_i915_private *dev_priv =
876 container_of(work, struct drm_i915_private, hotplug_work);
877 struct drm_device *dev = dev_priv->dev;
878 struct drm_mode_config *mode_config = &dev->mode_config;
879 struct intel_connector *intel_connector;
880 struct intel_encoder *intel_encoder;
881 struct drm_connector *connector;
882 bool hpd_disabled = false;
883 bool changed = false;
884 u32 hpd_event_bits;
885
886 mutex_lock(&mode_config->mutex);
887 DRM_DEBUG_KMS("running encoder hotplug functions\n");
888
889 spin_lock_irq(&dev_priv->irq_lock);
890
891 hpd_event_bits = dev_priv->hpd_event_bits;
892 dev_priv->hpd_event_bits = 0;
893 list_for_each_entry(connector, &mode_config->connector_list, head) {
894 intel_connector = to_intel_connector(connector);
895 if (!intel_connector->encoder)
896 continue;
897 intel_encoder = intel_connector->encoder;
898 if (intel_encoder->hpd_pin > HPD_NONE &&
899 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
900 connector->polled == DRM_CONNECTOR_POLL_HPD) {
901 DRM_INFO("HPD interrupt storm detected on connector %s: "
902 "switching from hotplug detection to polling\n",
903 connector->name);
904 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
905 connector->polled = DRM_CONNECTOR_POLL_CONNECT
906 | DRM_CONNECTOR_POLL_DISCONNECT;
907 hpd_disabled = true;
908 }
909 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
910 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
911 connector->name, intel_encoder->hpd_pin);
912 }
913 }
914 /* if there were no outputs to poll, poll was disabled,
915 * therefore make sure it's enabled when disabling HPD on
916 * some connectors */
917 if (hpd_disabled) {
918 drm_kms_helper_poll_enable(dev);
919 mod_delayed_work(system_wq, &dev_priv->hotplug_reenable_work,
920 msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
921 }
922
923 spin_unlock_irq(&dev_priv->irq_lock);
924
925 list_for_each_entry(connector, &mode_config->connector_list, head) {
926 intel_connector = to_intel_connector(connector);
927 if (!intel_connector->encoder)
928 continue;
929 intel_encoder = intel_connector->encoder;
930 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
931 if (intel_encoder->hot_plug)
932 intel_encoder->hot_plug(intel_encoder);
933 if (intel_hpd_irq_event(dev, connector))
934 changed = true;
935 }
936 }
937 mutex_unlock(&mode_config->mutex);
938
939 if (changed)
940 drm_kms_helper_hotplug_event(dev);
941 }
942
943 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
944 {
945 struct drm_i915_private *dev_priv = dev->dev_private;
946 u32 busy_up, busy_down, max_avg, min_avg;
947 u8 new_delay;
948
949 spin_lock(&mchdev_lock);
950
951 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
952
953 new_delay = dev_priv->ips.cur_delay;
954
955 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
956 busy_up = I915_READ(RCPREVBSYTUPAVG);
957 busy_down = I915_READ(RCPREVBSYTDNAVG);
958 max_avg = I915_READ(RCBMAXAVG);
959 min_avg = I915_READ(RCBMINAVG);
960
961 /* Handle RCS change request from hw */
962 if (busy_up > max_avg) {
963 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
964 new_delay = dev_priv->ips.cur_delay - 1;
965 if (new_delay < dev_priv->ips.max_delay)
966 new_delay = dev_priv->ips.max_delay;
967 } else if (busy_down < min_avg) {
968 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
969 new_delay = dev_priv->ips.cur_delay + 1;
970 if (new_delay > dev_priv->ips.min_delay)
971 new_delay = dev_priv->ips.min_delay;
972 }
973
974 if (ironlake_set_drps(dev, new_delay))
975 dev_priv->ips.cur_delay = new_delay;
976
977 spin_unlock(&mchdev_lock);
978
979 return;
980 }
981
982 static void notify_ring(struct drm_device *dev,
983 struct intel_engine_cs *ring)
984 {
985 if (!intel_ring_initialized(ring))
986 return;
987
988 trace_i915_gem_request_complete(ring);
989
990 wake_up_all(&ring->irq_queue);
991 i915_queue_hangcheck(dev);
992 }
993
994 static u32 vlv_c0_residency(struct drm_i915_private *dev_priv,
995 struct intel_rps_ei *rps_ei)
996 {
997 u32 cz_ts, cz_freq_khz;
998 u32 render_count, media_count;
999 u32 elapsed_render, elapsed_media, elapsed_time;
1000 u32 residency = 0;
1001
1002 cz_ts = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
1003 cz_freq_khz = DIV_ROUND_CLOSEST(dev_priv->mem_freq * 1000, 4);
1004
1005 render_count = I915_READ(VLV_RENDER_C0_COUNT_REG);
1006 media_count = I915_READ(VLV_MEDIA_C0_COUNT_REG);
1007
1008 if (rps_ei->cz_clock == 0) {
1009 rps_ei->cz_clock = cz_ts;
1010 rps_ei->render_c0 = render_count;
1011 rps_ei->media_c0 = media_count;
1012
1013 return dev_priv->rps.cur_freq;
1014 }
1015
1016 elapsed_time = cz_ts - rps_ei->cz_clock;
1017 rps_ei->cz_clock = cz_ts;
1018
1019 elapsed_render = render_count - rps_ei->render_c0;
1020 rps_ei->render_c0 = render_count;
1021
1022 elapsed_media = media_count - rps_ei->media_c0;
1023 rps_ei->media_c0 = media_count;
1024
1025 /* Convert all the counters into common unit of milli sec */
1026 elapsed_time /= VLV_CZ_CLOCK_TO_MILLI_SEC;
1027 elapsed_render /= cz_freq_khz;
1028 elapsed_media /= cz_freq_khz;
1029
1030 /*
1031 * Calculate overall C0 residency percentage
1032 * only if elapsed time is non zero
1033 */
1034 if (elapsed_time) {
1035 residency =
1036 ((max(elapsed_render, elapsed_media) * 100)
1037 / elapsed_time);
1038 }
1039
1040 return residency;
1041 }
1042
1043 /**
1044 * vlv_calc_delay_from_C0_counters - Increase/Decrease freq based on GPU
1045 * busy-ness calculated from C0 counters of render & media power wells
1046 * @dev_priv: DRM device private
1047 *
1048 */
1049 static int vlv_calc_delay_from_C0_counters(struct drm_i915_private *dev_priv)
1050 {
1051 u32 residency_C0_up = 0, residency_C0_down = 0;
1052 int new_delay, adj;
1053
1054 dev_priv->rps.ei_interrupt_count++;
1055
1056 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
1057
1058
1059 if (dev_priv->rps.up_ei.cz_clock == 0) {
1060 vlv_c0_residency(dev_priv, &dev_priv->rps.up_ei);
1061 vlv_c0_residency(dev_priv, &dev_priv->rps.down_ei);
1062 return dev_priv->rps.cur_freq;
1063 }
1064
1065
1066 /*
1067 * To down throttle, C0 residency should be less than down threshold
1068 * for continous EI intervals. So calculate down EI counters
1069 * once in VLV_INT_COUNT_FOR_DOWN_EI
1070 */
1071 if (dev_priv->rps.ei_interrupt_count == VLV_INT_COUNT_FOR_DOWN_EI) {
1072
1073 dev_priv->rps.ei_interrupt_count = 0;
1074
1075 residency_C0_down = vlv_c0_residency(dev_priv,
1076 &dev_priv->rps.down_ei);
1077 } else {
1078 residency_C0_up = vlv_c0_residency(dev_priv,
1079 &dev_priv->rps.up_ei);
1080 }
1081
1082 new_delay = dev_priv->rps.cur_freq;
1083
1084 adj = dev_priv->rps.last_adj;
1085 /* C0 residency is greater than UP threshold. Increase Frequency */
1086 if (residency_C0_up >= VLV_RP_UP_EI_THRESHOLD) {
1087 if (adj > 0)
1088 adj *= 2;
1089 else
1090 adj = 1;
1091
1092 if (dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit)
1093 new_delay = dev_priv->rps.cur_freq + adj;
1094
1095 /*
1096 * For better performance, jump directly
1097 * to RPe if we're below it.
1098 */
1099 if (new_delay < dev_priv->rps.efficient_freq)
1100 new_delay = dev_priv->rps.efficient_freq;
1101
1102 } else if (!dev_priv->rps.ei_interrupt_count &&
1103 (residency_C0_down < VLV_RP_DOWN_EI_THRESHOLD)) {
1104 if (adj < 0)
1105 adj *= 2;
1106 else
1107 adj = -1;
1108 /*
1109 * This means, C0 residency is less than down threshold over
1110 * a period of VLV_INT_COUNT_FOR_DOWN_EI. So, reduce the freq
1111 */
1112 if (dev_priv->rps.cur_freq > dev_priv->rps.min_freq_softlimit)
1113 new_delay = dev_priv->rps.cur_freq + adj;
1114 }
1115
1116 return new_delay;
1117 }
1118
1119 static void gen6_pm_rps_work(struct work_struct *work)
1120 {
1121 struct drm_i915_private *dev_priv =
1122 container_of(work, struct drm_i915_private, rps.work);
1123 u32 pm_iir;
1124 int new_delay, adj;
1125
1126 spin_lock_irq(&dev_priv->irq_lock);
1127 pm_iir = dev_priv->rps.pm_iir;
1128 dev_priv->rps.pm_iir = 0;
1129 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1130 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1131 spin_unlock_irq(&dev_priv->irq_lock);
1132
1133 /* Make sure we didn't queue anything we're not going to process. */
1134 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1135
1136 if ((pm_iir & dev_priv->pm_rps_events) == 0)
1137 return;
1138
1139 mutex_lock(&dev_priv->rps.hw_lock);
1140
1141 adj = dev_priv->rps.last_adj;
1142 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1143 if (adj > 0)
1144 adj *= 2;
1145 else {
1146 /* CHV needs even encode values */
1147 adj = IS_CHERRYVIEW(dev_priv->dev) ? 2 : 1;
1148 }
1149 new_delay = dev_priv->rps.cur_freq + adj;
1150
1151 /*
1152 * For better performance, jump directly
1153 * to RPe if we're below it.
1154 */
1155 if (new_delay < dev_priv->rps.efficient_freq)
1156 new_delay = dev_priv->rps.efficient_freq;
1157 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1158 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1159 new_delay = dev_priv->rps.efficient_freq;
1160 else
1161 new_delay = dev_priv->rps.min_freq_softlimit;
1162 adj = 0;
1163 } else if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1164 new_delay = vlv_calc_delay_from_C0_counters(dev_priv);
1165 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1166 if (adj < 0)
1167 adj *= 2;
1168 else {
1169 /* CHV needs even encode values */
1170 adj = IS_CHERRYVIEW(dev_priv->dev) ? -2 : -1;
1171 }
1172 new_delay = dev_priv->rps.cur_freq + adj;
1173 } else { /* unknown event */
1174 new_delay = dev_priv->rps.cur_freq;
1175 }
1176
1177 /* sysfs frequency interfaces may have snuck in while servicing the
1178 * interrupt
1179 */
1180 new_delay = clamp_t(int, new_delay,
1181 dev_priv->rps.min_freq_softlimit,
1182 dev_priv->rps.max_freq_softlimit);
1183
1184 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq;
1185
1186 if (IS_VALLEYVIEW(dev_priv->dev))
1187 valleyview_set_rps(dev_priv->dev, new_delay);
1188 else
1189 gen6_set_rps(dev_priv->dev, new_delay);
1190
1191 mutex_unlock(&dev_priv->rps.hw_lock);
1192 }
1193
1194
1195 /**
1196 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1197 * occurred.
1198 * @work: workqueue struct
1199 *
1200 * Doesn't actually do anything except notify userspace. As a consequence of
1201 * this event, userspace should try to remap the bad rows since statistically
1202 * it is likely the same row is more likely to go bad again.
1203 */
1204 static void ivybridge_parity_work(struct work_struct *work)
1205 {
1206 struct drm_i915_private *dev_priv =
1207 container_of(work, struct drm_i915_private, l3_parity.error_work);
1208 u32 error_status, row, bank, subbank;
1209 char *parity_event[6];
1210 uint32_t misccpctl;
1211 uint8_t slice = 0;
1212
1213 /* We must turn off DOP level clock gating to access the L3 registers.
1214 * In order to prevent a get/put style interface, acquire struct mutex
1215 * any time we access those registers.
1216 */
1217 mutex_lock(&dev_priv->dev->struct_mutex);
1218
1219 /* If we've screwed up tracking, just let the interrupt fire again */
1220 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1221 goto out;
1222
1223 misccpctl = I915_READ(GEN7_MISCCPCTL);
1224 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1225 POSTING_READ(GEN7_MISCCPCTL);
1226
1227 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1228 u32 reg;
1229
1230 slice--;
1231 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1232 break;
1233
1234 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1235
1236 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1237
1238 error_status = I915_READ(reg);
1239 row = GEN7_PARITY_ERROR_ROW(error_status);
1240 bank = GEN7_PARITY_ERROR_BANK(error_status);
1241 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1242
1243 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1244 POSTING_READ(reg);
1245
1246 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1247 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1248 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1249 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1250 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1251 parity_event[5] = NULL;
1252
1253 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1254 KOBJ_CHANGE, parity_event);
1255
1256 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1257 slice, row, bank, subbank);
1258
1259 kfree(parity_event[4]);
1260 kfree(parity_event[3]);
1261 kfree(parity_event[2]);
1262 kfree(parity_event[1]);
1263 }
1264
1265 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1266
1267 out:
1268 WARN_ON(dev_priv->l3_parity.which_slice);
1269 spin_lock_irq(&dev_priv->irq_lock);
1270 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1271 spin_unlock_irq(&dev_priv->irq_lock);
1272
1273 mutex_unlock(&dev_priv->dev->struct_mutex);
1274 }
1275
1276 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1277 {
1278 struct drm_i915_private *dev_priv = dev->dev_private;
1279
1280 if (!HAS_L3_DPF(dev))
1281 return;
1282
1283 spin_lock(&dev_priv->irq_lock);
1284 gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1285 spin_unlock(&dev_priv->irq_lock);
1286
1287 iir &= GT_PARITY_ERROR(dev);
1288 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1289 dev_priv->l3_parity.which_slice |= 1 << 1;
1290
1291 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1292 dev_priv->l3_parity.which_slice |= 1 << 0;
1293
1294 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1295 }
1296
1297 static void ilk_gt_irq_handler(struct drm_device *dev,
1298 struct drm_i915_private *dev_priv,
1299 u32 gt_iir)
1300 {
1301 if (gt_iir &
1302 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1303 notify_ring(dev, &dev_priv->ring[RCS]);
1304 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1305 notify_ring(dev, &dev_priv->ring[VCS]);
1306 }
1307
1308 static void snb_gt_irq_handler(struct drm_device *dev,
1309 struct drm_i915_private *dev_priv,
1310 u32 gt_iir)
1311 {
1312
1313 if (gt_iir &
1314 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1315 notify_ring(dev, &dev_priv->ring[RCS]);
1316 if (gt_iir & GT_BSD_USER_INTERRUPT)
1317 notify_ring(dev, &dev_priv->ring[VCS]);
1318 if (gt_iir & GT_BLT_USER_INTERRUPT)
1319 notify_ring(dev, &dev_priv->ring[BCS]);
1320
1321 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1322 GT_BSD_CS_ERROR_INTERRUPT |
1323 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
1324 i915_handle_error(dev, false, "GT error interrupt 0x%08x",
1325 gt_iir);
1326 }
1327
1328 if (gt_iir & GT_PARITY_ERROR(dev))
1329 ivybridge_parity_error_irq_handler(dev, gt_iir);
1330 }
1331
1332 static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1333 struct drm_i915_private *dev_priv,
1334 u32 master_ctl)
1335 {
1336 struct intel_engine_cs *ring;
1337 u32 rcs, bcs, vcs;
1338 uint32_t tmp = 0;
1339 irqreturn_t ret = IRQ_NONE;
1340
1341 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1342 tmp = I915_READ(GEN8_GT_IIR(0));
1343 if (tmp) {
1344 I915_WRITE(GEN8_GT_IIR(0), tmp);
1345 ret = IRQ_HANDLED;
1346
1347 rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1348 ring = &dev_priv->ring[RCS];
1349 if (rcs & GT_RENDER_USER_INTERRUPT)
1350 notify_ring(dev, ring);
1351 if (rcs & GT_CONTEXT_SWITCH_INTERRUPT)
1352 intel_execlists_handle_ctx_events(ring);
1353
1354 bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1355 ring = &dev_priv->ring[BCS];
1356 if (bcs & GT_RENDER_USER_INTERRUPT)
1357 notify_ring(dev, ring);
1358 if (bcs & GT_CONTEXT_SWITCH_INTERRUPT)
1359 intel_execlists_handle_ctx_events(ring);
1360 } else
1361 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1362 }
1363
1364 if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1365 tmp = I915_READ(GEN8_GT_IIR(1));
1366 if (tmp) {
1367 I915_WRITE(GEN8_GT_IIR(1), tmp);
1368 ret = IRQ_HANDLED;
1369
1370 vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1371 ring = &dev_priv->ring[VCS];
1372 if (vcs & GT_RENDER_USER_INTERRUPT)
1373 notify_ring(dev, ring);
1374 if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1375 intel_execlists_handle_ctx_events(ring);
1376
1377 vcs = tmp >> GEN8_VCS2_IRQ_SHIFT;
1378 ring = &dev_priv->ring[VCS2];
1379 if (vcs & GT_RENDER_USER_INTERRUPT)
1380 notify_ring(dev, ring);
1381 if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1382 intel_execlists_handle_ctx_events(ring);
1383 } else
1384 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1385 }
1386
1387 if (master_ctl & GEN8_GT_PM_IRQ) {
1388 tmp = I915_READ(GEN8_GT_IIR(2));
1389 if (tmp & dev_priv->pm_rps_events) {
1390 I915_WRITE(GEN8_GT_IIR(2),
1391 tmp & dev_priv->pm_rps_events);
1392 ret = IRQ_HANDLED;
1393 gen6_rps_irq_handler(dev_priv, tmp);
1394 } else
1395 DRM_ERROR("The master control interrupt lied (PM)!\n");
1396 }
1397
1398 if (master_ctl & GEN8_GT_VECS_IRQ) {
1399 tmp = I915_READ(GEN8_GT_IIR(3));
1400 if (tmp) {
1401 I915_WRITE(GEN8_GT_IIR(3), tmp);
1402 ret = IRQ_HANDLED;
1403
1404 vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1405 ring = &dev_priv->ring[VECS];
1406 if (vcs & GT_RENDER_USER_INTERRUPT)
1407 notify_ring(dev, ring);
1408 if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1409 intel_execlists_handle_ctx_events(ring);
1410 } else
1411 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1412 }
1413
1414 return ret;
1415 }
1416
1417 #define HPD_STORM_DETECT_PERIOD 1000
1418 #define HPD_STORM_THRESHOLD 5
1419
1420 static int pch_port_to_hotplug_shift(enum port port)
1421 {
1422 switch (port) {
1423 case PORT_A:
1424 case PORT_E:
1425 default:
1426 return -1;
1427 case PORT_B:
1428 return 0;
1429 case PORT_C:
1430 return 8;
1431 case PORT_D:
1432 return 16;
1433 }
1434 }
1435
1436 static int i915_port_to_hotplug_shift(enum port port)
1437 {
1438 switch (port) {
1439 case PORT_A:
1440 case PORT_E:
1441 default:
1442 return -1;
1443 case PORT_B:
1444 return 17;
1445 case PORT_C:
1446 return 19;
1447 case PORT_D:
1448 return 21;
1449 }
1450 }
1451
1452 static inline enum port get_port_from_pin(enum hpd_pin pin)
1453 {
1454 switch (pin) {
1455 case HPD_PORT_B:
1456 return PORT_B;
1457 case HPD_PORT_C:
1458 return PORT_C;
1459 case HPD_PORT_D:
1460 return PORT_D;
1461 default:
1462 return PORT_A; /* no hpd */
1463 }
1464 }
1465
1466 static inline void intel_hpd_irq_handler(struct drm_device *dev,
1467 u32 hotplug_trigger,
1468 u32 dig_hotplug_reg,
1469 const u32 *hpd)
1470 {
1471 struct drm_i915_private *dev_priv = dev->dev_private;
1472 int i;
1473 enum port port;
1474 bool storm_detected = false;
1475 bool queue_dig = false, queue_hp = false;
1476 u32 dig_shift;
1477 u32 dig_port_mask = 0;
1478
1479 if (!hotplug_trigger)
1480 return;
1481
1482 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x\n",
1483 hotplug_trigger, dig_hotplug_reg);
1484
1485 spin_lock(&dev_priv->irq_lock);
1486 for (i = 1; i < HPD_NUM_PINS; i++) {
1487 if (!(hpd[i] & hotplug_trigger))
1488 continue;
1489
1490 port = get_port_from_pin(i);
1491 if (port && dev_priv->hpd_irq_port[port]) {
1492 bool long_hpd;
1493
1494 if (HAS_PCH_SPLIT(dev)) {
1495 dig_shift = pch_port_to_hotplug_shift(port);
1496 long_hpd = (dig_hotplug_reg >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
1497 } else {
1498 dig_shift = i915_port_to_hotplug_shift(port);
1499 long_hpd = (hotplug_trigger >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
1500 }
1501
1502 DRM_DEBUG_DRIVER("digital hpd port %c - %s\n",
1503 port_name(port),
1504 long_hpd ? "long" : "short");
1505 /* for long HPD pulses we want to have the digital queue happen,
1506 but we still want HPD storm detection to function. */
1507 if (long_hpd) {
1508 dev_priv->long_hpd_port_mask |= (1 << port);
1509 dig_port_mask |= hpd[i];
1510 } else {
1511 /* for short HPD just trigger the digital queue */
1512 dev_priv->short_hpd_port_mask |= (1 << port);
1513 hotplug_trigger &= ~hpd[i];
1514 }
1515 queue_dig = true;
1516 }
1517 }
1518
1519 for (i = 1; i < HPD_NUM_PINS; i++) {
1520 if (hpd[i] & hotplug_trigger &&
1521 dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) {
1522 /*
1523 * On GMCH platforms the interrupt mask bits only
1524 * prevent irq generation, not the setting of the
1525 * hotplug bits itself. So only WARN about unexpected
1526 * interrupts on saner platforms.
1527 */
1528 WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
1529 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1530 hotplug_trigger, i, hpd[i]);
1531
1532 continue;
1533 }
1534
1535 if (!(hpd[i] & hotplug_trigger) ||
1536 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1537 continue;
1538
1539 if (!(dig_port_mask & hpd[i])) {
1540 dev_priv->hpd_event_bits |= (1 << i);
1541 queue_hp = true;
1542 }
1543
1544 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1545 dev_priv->hpd_stats[i].hpd_last_jiffies
1546 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1547 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1548 dev_priv->hpd_stats[i].hpd_cnt = 0;
1549 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1550 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1551 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1552 dev_priv->hpd_event_bits &= ~(1 << i);
1553 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1554 storm_detected = true;
1555 } else {
1556 dev_priv->hpd_stats[i].hpd_cnt++;
1557 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1558 dev_priv->hpd_stats[i].hpd_cnt);
1559 }
1560 }
1561
1562 if (storm_detected)
1563 dev_priv->display.hpd_irq_setup(dev);
1564 spin_unlock(&dev_priv->irq_lock);
1565
1566 /*
1567 * Our hotplug handler can grab modeset locks (by calling down into the
1568 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1569 * queue for otherwise the flush_work in the pageflip code will
1570 * deadlock.
1571 */
1572 if (queue_dig)
1573 queue_work(dev_priv->dp_wq, &dev_priv->dig_port_work);
1574 if (queue_hp)
1575 schedule_work(&dev_priv->hotplug_work);
1576 }
1577
1578 static void gmbus_irq_handler(struct drm_device *dev)
1579 {
1580 struct drm_i915_private *dev_priv = dev->dev_private;
1581
1582 wake_up_all(&dev_priv->gmbus_wait_queue);
1583 }
1584
1585 static void dp_aux_irq_handler(struct drm_device *dev)
1586 {
1587 struct drm_i915_private *dev_priv = dev->dev_private;
1588
1589 wake_up_all(&dev_priv->gmbus_wait_queue);
1590 }
1591
1592 #if defined(CONFIG_DEBUG_FS)
1593 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1594 uint32_t crc0, uint32_t crc1,
1595 uint32_t crc2, uint32_t crc3,
1596 uint32_t crc4)
1597 {
1598 struct drm_i915_private *dev_priv = dev->dev_private;
1599 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1600 struct intel_pipe_crc_entry *entry;
1601 int head, tail;
1602
1603 spin_lock(&pipe_crc->lock);
1604
1605 if (!pipe_crc->entries) {
1606 spin_unlock(&pipe_crc->lock);
1607 DRM_ERROR("spurious interrupt\n");
1608 return;
1609 }
1610
1611 head = pipe_crc->head;
1612 tail = pipe_crc->tail;
1613
1614 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1615 spin_unlock(&pipe_crc->lock);
1616 DRM_ERROR("CRC buffer overflowing\n");
1617 return;
1618 }
1619
1620 entry = &pipe_crc->entries[head];
1621
1622 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1623 entry->crc[0] = crc0;
1624 entry->crc[1] = crc1;
1625 entry->crc[2] = crc2;
1626 entry->crc[3] = crc3;
1627 entry->crc[4] = crc4;
1628
1629 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1630 pipe_crc->head = head;
1631
1632 spin_unlock(&pipe_crc->lock);
1633
1634 wake_up_interruptible(&pipe_crc->wq);
1635 }
1636 #else
1637 static inline void
1638 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1639 uint32_t crc0, uint32_t crc1,
1640 uint32_t crc2, uint32_t crc3,
1641 uint32_t crc4) {}
1642 #endif
1643
1644
1645 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1646 {
1647 struct drm_i915_private *dev_priv = dev->dev_private;
1648
1649 display_pipe_crc_irq_handler(dev, pipe,
1650 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1651 0, 0, 0, 0);
1652 }
1653
1654 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1655 {
1656 struct drm_i915_private *dev_priv = dev->dev_private;
1657
1658 display_pipe_crc_irq_handler(dev, pipe,
1659 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1660 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1661 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1662 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1663 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1664 }
1665
1666 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1667 {
1668 struct drm_i915_private *dev_priv = dev->dev_private;
1669 uint32_t res1, res2;
1670
1671 if (INTEL_INFO(dev)->gen >= 3)
1672 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1673 else
1674 res1 = 0;
1675
1676 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1677 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1678 else
1679 res2 = 0;
1680
1681 display_pipe_crc_irq_handler(dev, pipe,
1682 I915_READ(PIPE_CRC_RES_RED(pipe)),
1683 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1684 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1685 res1, res2);
1686 }
1687
1688 /* The RPS events need forcewake, so we add them to a work queue and mask their
1689 * IMR bits until the work is done. Other interrupts can be processed without
1690 * the work queue. */
1691 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1692 {
1693 /* TODO: RPS on GEN9 is not supported yet. */
1694 if (WARN_ONCE(INTEL_INFO(dev_priv)->gen == 9,
1695 "GEN9: unexpected RPS IRQ\n"))
1696 return;
1697
1698 if (pm_iir & dev_priv->pm_rps_events) {
1699 spin_lock(&dev_priv->irq_lock);
1700 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1701 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1702 spin_unlock(&dev_priv->irq_lock);
1703
1704 queue_work(dev_priv->wq, &dev_priv->rps.work);
1705 }
1706
1707 if (INTEL_INFO(dev_priv)->gen >= 8)
1708 return;
1709
1710 if (HAS_VEBOX(dev_priv->dev)) {
1711 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1712 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1713
1714 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1715 i915_handle_error(dev_priv->dev, false,
1716 "VEBOX CS error interrupt 0x%08x",
1717 pm_iir);
1718 }
1719 }
1720 }
1721
1722 static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
1723 {
1724 if (!drm_handle_vblank(dev, pipe))
1725 return false;
1726
1727 return true;
1728 }
1729
1730 static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1731 {
1732 struct drm_i915_private *dev_priv = dev->dev_private;
1733 u32 pipe_stats[I915_MAX_PIPES] = { };
1734 int pipe;
1735
1736 spin_lock(&dev_priv->irq_lock);
1737 for_each_pipe(dev_priv, pipe) {
1738 int reg;
1739 u32 mask, iir_bit = 0;
1740
1741 /*
1742 * PIPESTAT bits get signalled even when the interrupt is
1743 * disabled with the mask bits, and some of the status bits do
1744 * not generate interrupts at all (like the underrun bit). Hence
1745 * we need to be careful that we only handle what we want to
1746 * handle.
1747 */
1748
1749 /* fifo underruns are filterered in the underrun handler. */
1750 mask = PIPE_FIFO_UNDERRUN_STATUS;
1751
1752 switch (pipe) {
1753 case PIPE_A:
1754 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1755 break;
1756 case PIPE_B:
1757 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1758 break;
1759 case PIPE_C:
1760 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1761 break;
1762 }
1763 if (iir & iir_bit)
1764 mask |= dev_priv->pipestat_irq_mask[pipe];
1765
1766 if (!mask)
1767 continue;
1768
1769 reg = PIPESTAT(pipe);
1770 mask |= PIPESTAT_INT_ENABLE_MASK;
1771 pipe_stats[pipe] = I915_READ(reg) & mask;
1772
1773 /*
1774 * Clear the PIPE*STAT regs before the IIR
1775 */
1776 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1777 PIPESTAT_INT_STATUS_MASK))
1778 I915_WRITE(reg, pipe_stats[pipe]);
1779 }
1780 spin_unlock(&dev_priv->irq_lock);
1781
1782 for_each_pipe(dev_priv, pipe) {
1783 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1784 intel_pipe_handle_vblank(dev, pipe))
1785 intel_check_page_flip(dev, pipe);
1786
1787 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
1788 intel_prepare_page_flip(dev, pipe);
1789 intel_finish_page_flip(dev, pipe);
1790 }
1791
1792 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1793 i9xx_pipe_crc_irq_handler(dev, pipe);
1794
1795 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1796 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1797 }
1798
1799 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1800 gmbus_irq_handler(dev);
1801 }
1802
1803 static void i9xx_hpd_irq_handler(struct drm_device *dev)
1804 {
1805 struct drm_i915_private *dev_priv = dev->dev_private;
1806 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1807
1808 if (hotplug_status) {
1809 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1810 /*
1811 * Make sure hotplug status is cleared before we clear IIR, or else we
1812 * may miss hotplug events.
1813 */
1814 POSTING_READ(PORT_HOTPLUG_STAT);
1815
1816 if (IS_G4X(dev)) {
1817 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1818
1819 intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_g4x);
1820 } else {
1821 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1822
1823 intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_i915);
1824 }
1825
1826 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) &&
1827 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1828 dp_aux_irq_handler(dev);
1829 }
1830 }
1831
1832 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1833 {
1834 struct drm_device *dev = arg;
1835 struct drm_i915_private *dev_priv = dev->dev_private;
1836 u32 iir, gt_iir, pm_iir;
1837 irqreturn_t ret = IRQ_NONE;
1838
1839 while (true) {
1840 /* Find, clear, then process each source of interrupt */
1841
1842 gt_iir = I915_READ(GTIIR);
1843 if (gt_iir)
1844 I915_WRITE(GTIIR, gt_iir);
1845
1846 pm_iir = I915_READ(GEN6_PMIIR);
1847 if (pm_iir)
1848 I915_WRITE(GEN6_PMIIR, pm_iir);
1849
1850 iir = I915_READ(VLV_IIR);
1851 if (iir) {
1852 /* Consume port before clearing IIR or we'll miss events */
1853 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1854 i9xx_hpd_irq_handler(dev);
1855 I915_WRITE(VLV_IIR, iir);
1856 }
1857
1858 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1859 goto out;
1860
1861 ret = IRQ_HANDLED;
1862
1863 if (gt_iir)
1864 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1865 if (pm_iir)
1866 gen6_rps_irq_handler(dev_priv, pm_iir);
1867 /* Call regardless, as some status bits might not be
1868 * signalled in iir */
1869 valleyview_pipestat_irq_handler(dev, iir);
1870 }
1871
1872 out:
1873 return ret;
1874 }
1875
1876 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1877 {
1878 struct drm_device *dev = arg;
1879 struct drm_i915_private *dev_priv = dev->dev_private;
1880 u32 master_ctl, iir;
1881 irqreturn_t ret = IRQ_NONE;
1882
1883 for (;;) {
1884 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1885 iir = I915_READ(VLV_IIR);
1886
1887 if (master_ctl == 0 && iir == 0)
1888 break;
1889
1890 ret = IRQ_HANDLED;
1891
1892 I915_WRITE(GEN8_MASTER_IRQ, 0);
1893
1894 /* Find, clear, then process each source of interrupt */
1895
1896 if (iir) {
1897 /* Consume port before clearing IIR or we'll miss events */
1898 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1899 i9xx_hpd_irq_handler(dev);
1900 I915_WRITE(VLV_IIR, iir);
1901 }
1902
1903 gen8_gt_irq_handler(dev, dev_priv, master_ctl);
1904
1905 /* Call regardless, as some status bits might not be
1906 * signalled in iir */
1907 valleyview_pipestat_irq_handler(dev, iir);
1908
1909 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
1910 POSTING_READ(GEN8_MASTER_IRQ);
1911 }
1912
1913 return ret;
1914 }
1915
1916 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1917 {
1918 struct drm_i915_private *dev_priv = dev->dev_private;
1919 int pipe;
1920 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1921 u32 dig_hotplug_reg;
1922
1923 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1924 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1925
1926 intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_ibx);
1927
1928 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1929 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1930 SDE_AUDIO_POWER_SHIFT);
1931 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1932 port_name(port));
1933 }
1934
1935 if (pch_iir & SDE_AUX_MASK)
1936 dp_aux_irq_handler(dev);
1937
1938 if (pch_iir & SDE_GMBUS)
1939 gmbus_irq_handler(dev);
1940
1941 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1942 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1943
1944 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1945 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1946
1947 if (pch_iir & SDE_POISON)
1948 DRM_ERROR("PCH poison interrupt\n");
1949
1950 if (pch_iir & SDE_FDI_MASK)
1951 for_each_pipe(dev_priv, pipe)
1952 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1953 pipe_name(pipe),
1954 I915_READ(FDI_RX_IIR(pipe)));
1955
1956 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1957 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1958
1959 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1960 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1961
1962 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1963 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1964
1965 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1966 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
1967 }
1968
1969 static void ivb_err_int_handler(struct drm_device *dev)
1970 {
1971 struct drm_i915_private *dev_priv = dev->dev_private;
1972 u32 err_int = I915_READ(GEN7_ERR_INT);
1973 enum pipe pipe;
1974
1975 if (err_int & ERR_INT_POISON)
1976 DRM_ERROR("Poison interrupt\n");
1977
1978 for_each_pipe(dev_priv, pipe) {
1979 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
1980 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1981
1982 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1983 if (IS_IVYBRIDGE(dev))
1984 ivb_pipe_crc_irq_handler(dev, pipe);
1985 else
1986 hsw_pipe_crc_irq_handler(dev, pipe);
1987 }
1988 }
1989
1990 I915_WRITE(GEN7_ERR_INT, err_int);
1991 }
1992
1993 static void cpt_serr_int_handler(struct drm_device *dev)
1994 {
1995 struct drm_i915_private *dev_priv = dev->dev_private;
1996 u32 serr_int = I915_READ(SERR_INT);
1997
1998 if (serr_int & SERR_INT_POISON)
1999 DRM_ERROR("PCH poison interrupt\n");
2000
2001 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2002 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2003
2004 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2005 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2006
2007 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2008 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
2009
2010 I915_WRITE(SERR_INT, serr_int);
2011 }
2012
2013 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
2014 {
2015 struct drm_i915_private *dev_priv = dev->dev_private;
2016 int pipe;
2017 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2018 u32 dig_hotplug_reg;
2019
2020 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2021 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2022
2023 intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_cpt);
2024
2025 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2026 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2027 SDE_AUDIO_POWER_SHIFT_CPT);
2028 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2029 port_name(port));
2030 }
2031
2032 if (pch_iir & SDE_AUX_MASK_CPT)
2033 dp_aux_irq_handler(dev);
2034
2035 if (pch_iir & SDE_GMBUS_CPT)
2036 gmbus_irq_handler(dev);
2037
2038 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2039 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2040
2041 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2042 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2043
2044 if (pch_iir & SDE_FDI_MASK_CPT)
2045 for_each_pipe(dev_priv, pipe)
2046 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2047 pipe_name(pipe),
2048 I915_READ(FDI_RX_IIR(pipe)));
2049
2050 if (pch_iir & SDE_ERROR_CPT)
2051 cpt_serr_int_handler(dev);
2052 }
2053
2054 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
2055 {
2056 struct drm_i915_private *dev_priv = dev->dev_private;
2057 enum pipe pipe;
2058
2059 if (de_iir & DE_AUX_CHANNEL_A)
2060 dp_aux_irq_handler(dev);
2061
2062 if (de_iir & DE_GSE)
2063 intel_opregion_asle_intr(dev);
2064
2065 if (de_iir & DE_POISON)
2066 DRM_ERROR("Poison interrupt\n");
2067
2068 for_each_pipe(dev_priv, pipe) {
2069 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2070 intel_pipe_handle_vblank(dev, pipe))
2071 intel_check_page_flip(dev, pipe);
2072
2073 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2074 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2075
2076 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2077 i9xx_pipe_crc_irq_handler(dev, pipe);
2078
2079 /* plane/pipes map 1:1 on ilk+ */
2080 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
2081 intel_prepare_page_flip(dev, pipe);
2082 intel_finish_page_flip_plane(dev, pipe);
2083 }
2084 }
2085
2086 /* check event from PCH */
2087 if (de_iir & DE_PCH_EVENT) {
2088 u32 pch_iir = I915_READ(SDEIIR);
2089
2090 if (HAS_PCH_CPT(dev))
2091 cpt_irq_handler(dev, pch_iir);
2092 else
2093 ibx_irq_handler(dev, pch_iir);
2094
2095 /* should clear PCH hotplug event before clear CPU irq */
2096 I915_WRITE(SDEIIR, pch_iir);
2097 }
2098
2099 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
2100 ironlake_rps_change_irq_handler(dev);
2101 }
2102
2103 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
2104 {
2105 struct drm_i915_private *dev_priv = dev->dev_private;
2106 enum pipe pipe;
2107
2108 if (de_iir & DE_ERR_INT_IVB)
2109 ivb_err_int_handler(dev);
2110
2111 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2112 dp_aux_irq_handler(dev);
2113
2114 if (de_iir & DE_GSE_IVB)
2115 intel_opregion_asle_intr(dev);
2116
2117 for_each_pipe(dev_priv, pipe) {
2118 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2119 intel_pipe_handle_vblank(dev, pipe))
2120 intel_check_page_flip(dev, pipe);
2121
2122 /* plane/pipes map 1:1 on ilk+ */
2123 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
2124 intel_prepare_page_flip(dev, pipe);
2125 intel_finish_page_flip_plane(dev, pipe);
2126 }
2127 }
2128
2129 /* check event from PCH */
2130 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
2131 u32 pch_iir = I915_READ(SDEIIR);
2132
2133 cpt_irq_handler(dev, pch_iir);
2134
2135 /* clear PCH hotplug event before clear CPU irq */
2136 I915_WRITE(SDEIIR, pch_iir);
2137 }
2138 }
2139
2140 /*
2141 * To handle irqs with the minimum potential races with fresh interrupts, we:
2142 * 1 - Disable Master Interrupt Control.
2143 * 2 - Find the source(s) of the interrupt.
2144 * 3 - Clear the Interrupt Identity bits (IIR).
2145 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2146 * 5 - Re-enable Master Interrupt Control.
2147 */
2148 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2149 {
2150 struct drm_device *dev = arg;
2151 struct drm_i915_private *dev_priv = dev->dev_private;
2152 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2153 irqreturn_t ret = IRQ_NONE;
2154
2155 /* We get interrupts on unclaimed registers, so check for this before we
2156 * do any I915_{READ,WRITE}. */
2157 intel_uncore_check_errors(dev);
2158
2159 /* disable master interrupt before clearing iir */
2160 de_ier = I915_READ(DEIER);
2161 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2162 POSTING_READ(DEIER);
2163
2164 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2165 * interrupts will will be stored on its back queue, and then we'll be
2166 * able to process them after we restore SDEIER (as soon as we restore
2167 * it, we'll get an interrupt if SDEIIR still has something to process
2168 * due to its back queue). */
2169 if (!HAS_PCH_NOP(dev)) {
2170 sde_ier = I915_READ(SDEIER);
2171 I915_WRITE(SDEIER, 0);
2172 POSTING_READ(SDEIER);
2173 }
2174
2175 /* Find, clear, then process each source of interrupt */
2176
2177 gt_iir = I915_READ(GTIIR);
2178 if (gt_iir) {
2179 I915_WRITE(GTIIR, gt_iir);
2180 ret = IRQ_HANDLED;
2181 if (INTEL_INFO(dev)->gen >= 6)
2182 snb_gt_irq_handler(dev, dev_priv, gt_iir);
2183 else
2184 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
2185 }
2186
2187 de_iir = I915_READ(DEIIR);
2188 if (de_iir) {
2189 I915_WRITE(DEIIR, de_iir);
2190 ret = IRQ_HANDLED;
2191 if (INTEL_INFO(dev)->gen >= 7)
2192 ivb_display_irq_handler(dev, de_iir);
2193 else
2194 ilk_display_irq_handler(dev, de_iir);
2195 }
2196
2197 if (INTEL_INFO(dev)->gen >= 6) {
2198 u32 pm_iir = I915_READ(GEN6_PMIIR);
2199 if (pm_iir) {
2200 I915_WRITE(GEN6_PMIIR, pm_iir);
2201 ret = IRQ_HANDLED;
2202 gen6_rps_irq_handler(dev_priv, pm_iir);
2203 }
2204 }
2205
2206 I915_WRITE(DEIER, de_ier);
2207 POSTING_READ(DEIER);
2208 if (!HAS_PCH_NOP(dev)) {
2209 I915_WRITE(SDEIER, sde_ier);
2210 POSTING_READ(SDEIER);
2211 }
2212
2213 return ret;
2214 }
2215
2216 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2217 {
2218 struct drm_device *dev = arg;
2219 struct drm_i915_private *dev_priv = dev->dev_private;
2220 u32 master_ctl;
2221 irqreturn_t ret = IRQ_NONE;
2222 uint32_t tmp = 0;
2223 enum pipe pipe;
2224
2225 master_ctl = I915_READ(GEN8_MASTER_IRQ);
2226 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2227 if (!master_ctl)
2228 return IRQ_NONE;
2229
2230 I915_WRITE(GEN8_MASTER_IRQ, 0);
2231 POSTING_READ(GEN8_MASTER_IRQ);
2232
2233 /* Find, clear, then process each source of interrupt */
2234
2235 ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
2236
2237 if (master_ctl & GEN8_DE_MISC_IRQ) {
2238 tmp = I915_READ(GEN8_DE_MISC_IIR);
2239 if (tmp) {
2240 I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2241 ret = IRQ_HANDLED;
2242 if (tmp & GEN8_DE_MISC_GSE)
2243 intel_opregion_asle_intr(dev);
2244 else
2245 DRM_ERROR("Unexpected DE Misc interrupt\n");
2246 }
2247 else
2248 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2249 }
2250
2251 if (master_ctl & GEN8_DE_PORT_IRQ) {
2252 tmp = I915_READ(GEN8_DE_PORT_IIR);
2253 if (tmp) {
2254 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2255 ret = IRQ_HANDLED;
2256 if (tmp & GEN8_AUX_CHANNEL_A)
2257 dp_aux_irq_handler(dev);
2258 else
2259 DRM_ERROR("Unexpected DE Port interrupt\n");
2260 }
2261 else
2262 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2263 }
2264
2265 for_each_pipe(dev_priv, pipe) {
2266 uint32_t pipe_iir, flip_done = 0, fault_errors = 0;
2267
2268 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2269 continue;
2270
2271 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2272 if (pipe_iir) {
2273 ret = IRQ_HANDLED;
2274 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2275
2276 if (pipe_iir & GEN8_PIPE_VBLANK &&
2277 intel_pipe_handle_vblank(dev, pipe))
2278 intel_check_page_flip(dev, pipe);
2279
2280 if (IS_GEN9(dev))
2281 flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE;
2282 else
2283 flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE;
2284
2285 if (flip_done) {
2286 intel_prepare_page_flip(dev, pipe);
2287 intel_finish_page_flip_plane(dev, pipe);
2288 }
2289
2290 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2291 hsw_pipe_crc_irq_handler(dev, pipe);
2292
2293 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN)
2294 intel_cpu_fifo_underrun_irq_handler(dev_priv,
2295 pipe);
2296
2297
2298 if (IS_GEN9(dev))
2299 fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2300 else
2301 fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2302
2303 if (fault_errors)
2304 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2305 pipe_name(pipe),
2306 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2307 } else
2308 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2309 }
2310
2311 if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
2312 /*
2313 * FIXME(BDW): Assume for now that the new interrupt handling
2314 * scheme also closed the SDE interrupt handling race we've seen
2315 * on older pch-split platforms. But this needs testing.
2316 */
2317 u32 pch_iir = I915_READ(SDEIIR);
2318 if (pch_iir) {
2319 I915_WRITE(SDEIIR, pch_iir);
2320 ret = IRQ_HANDLED;
2321 cpt_irq_handler(dev, pch_iir);
2322 } else
2323 DRM_ERROR("The master control interrupt lied (SDE)!\n");
2324
2325 }
2326
2327 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2328 POSTING_READ(GEN8_MASTER_IRQ);
2329
2330 return ret;
2331 }
2332
2333 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2334 bool reset_completed)
2335 {
2336 struct intel_engine_cs *ring;
2337 int i;
2338
2339 /*
2340 * Notify all waiters for GPU completion events that reset state has
2341 * been changed, and that they need to restart their wait after
2342 * checking for potential errors (and bail out to drop locks if there is
2343 * a gpu reset pending so that i915_error_work_func can acquire them).
2344 */
2345
2346 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2347 for_each_ring(ring, dev_priv, i)
2348 wake_up_all(&ring->irq_queue);
2349
2350 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2351 wake_up_all(&dev_priv->pending_flip_queue);
2352
2353 /*
2354 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2355 * reset state is cleared.
2356 */
2357 if (reset_completed)
2358 wake_up_all(&dev_priv->gpu_error.reset_queue);
2359 }
2360
2361 /**
2362 * i915_error_work_func - do process context error handling work
2363 * @work: work struct
2364 *
2365 * Fire an error uevent so userspace can see that a hang or error
2366 * was detected.
2367 */
2368 static void i915_error_work_func(struct work_struct *work)
2369 {
2370 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
2371 work);
2372 struct drm_i915_private *dev_priv =
2373 container_of(error, struct drm_i915_private, gpu_error);
2374 struct drm_device *dev = dev_priv->dev;
2375 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2376 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2377 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2378 int ret;
2379
2380 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2381
2382 /*
2383 * Note that there's only one work item which does gpu resets, so we
2384 * need not worry about concurrent gpu resets potentially incrementing
2385 * error->reset_counter twice. We only need to take care of another
2386 * racing irq/hangcheck declaring the gpu dead for a second time. A
2387 * quick check for that is good enough: schedule_work ensures the
2388 * correct ordering between hang detection and this work item, and since
2389 * the reset in-progress bit is only ever set by code outside of this
2390 * work we don't need to worry about any other races.
2391 */
2392 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2393 DRM_DEBUG_DRIVER("resetting chip\n");
2394 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2395 reset_event);
2396
2397 /*
2398 * In most cases it's guaranteed that we get here with an RPM
2399 * reference held, for example because there is a pending GPU
2400 * request that won't finish until the reset is done. This
2401 * isn't the case at least when we get here by doing a
2402 * simulated reset via debugs, so get an RPM reference.
2403 */
2404 intel_runtime_pm_get(dev_priv);
2405 /*
2406 * All state reset _must_ be completed before we update the
2407 * reset counter, for otherwise waiters might miss the reset
2408 * pending state and not properly drop locks, resulting in
2409 * deadlocks with the reset work.
2410 */
2411 ret = i915_reset(dev);
2412
2413 intel_display_handle_reset(dev);
2414
2415 intel_runtime_pm_put(dev_priv);
2416
2417 if (ret == 0) {
2418 /*
2419 * After all the gem state is reset, increment the reset
2420 * counter and wake up everyone waiting for the reset to
2421 * complete.
2422 *
2423 * Since unlock operations are a one-sided barrier only,
2424 * we need to insert a barrier here to order any seqno
2425 * updates before
2426 * the counter increment.
2427 */
2428 smp_mb__before_atomic();
2429 atomic_inc(&dev_priv->gpu_error.reset_counter);
2430
2431 kobject_uevent_env(&dev->primary->kdev->kobj,
2432 KOBJ_CHANGE, reset_done_event);
2433 } else {
2434 atomic_set_mask(I915_WEDGED, &error->reset_counter);
2435 }
2436
2437 /*
2438 * Note: The wake_up also serves as a memory barrier so that
2439 * waiters see the update value of the reset counter atomic_t.
2440 */
2441 i915_error_wake_up(dev_priv, true);
2442 }
2443 }
2444
2445 static void i915_report_and_clear_eir(struct drm_device *dev)
2446 {
2447 struct drm_i915_private *dev_priv = dev->dev_private;
2448 uint32_t instdone[I915_NUM_INSTDONE_REG];
2449 u32 eir = I915_READ(EIR);
2450 int pipe, i;
2451
2452 if (!eir)
2453 return;
2454
2455 pr_err("render error detected, EIR: 0x%08x\n", eir);
2456
2457 i915_get_extra_instdone(dev, instdone);
2458
2459 if (IS_G4X(dev)) {
2460 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2461 u32 ipeir = I915_READ(IPEIR_I965);
2462
2463 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2464 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2465 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2466 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2467 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2468 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2469 I915_WRITE(IPEIR_I965, ipeir);
2470 POSTING_READ(IPEIR_I965);
2471 }
2472 if (eir & GM45_ERROR_PAGE_TABLE) {
2473 u32 pgtbl_err = I915_READ(PGTBL_ER);
2474 pr_err("page table error\n");
2475 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2476 I915_WRITE(PGTBL_ER, pgtbl_err);
2477 POSTING_READ(PGTBL_ER);
2478 }
2479 }
2480
2481 if (!IS_GEN2(dev)) {
2482 if (eir & I915_ERROR_PAGE_TABLE) {
2483 u32 pgtbl_err = I915_READ(PGTBL_ER);
2484 pr_err("page table error\n");
2485 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2486 I915_WRITE(PGTBL_ER, pgtbl_err);
2487 POSTING_READ(PGTBL_ER);
2488 }
2489 }
2490
2491 if (eir & I915_ERROR_MEMORY_REFRESH) {
2492 pr_err("memory refresh error:\n");
2493 for_each_pipe(dev_priv, pipe)
2494 pr_err("pipe %c stat: 0x%08x\n",
2495 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2496 /* pipestat has already been acked */
2497 }
2498 if (eir & I915_ERROR_INSTRUCTION) {
2499 pr_err("instruction error\n");
2500 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
2501 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2502 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2503 if (INTEL_INFO(dev)->gen < 4) {
2504 u32 ipeir = I915_READ(IPEIR);
2505
2506 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2507 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
2508 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
2509 I915_WRITE(IPEIR, ipeir);
2510 POSTING_READ(IPEIR);
2511 } else {
2512 u32 ipeir = I915_READ(IPEIR_I965);
2513
2514 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2515 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2516 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2517 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2518 I915_WRITE(IPEIR_I965, ipeir);
2519 POSTING_READ(IPEIR_I965);
2520 }
2521 }
2522
2523 I915_WRITE(EIR, eir);
2524 POSTING_READ(EIR);
2525 eir = I915_READ(EIR);
2526 if (eir) {
2527 /*
2528 * some errors might have become stuck,
2529 * mask them.
2530 */
2531 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2532 I915_WRITE(EMR, I915_READ(EMR) | eir);
2533 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2534 }
2535 }
2536
2537 /**
2538 * i915_handle_error - handle an error interrupt
2539 * @dev: drm device
2540 *
2541 * Do some basic checking of regsiter state at error interrupt time and
2542 * dump it to the syslog. Also call i915_capture_error_state() to make
2543 * sure we get a record and make it available in debugfs. Fire a uevent
2544 * so userspace knows something bad happened (should trigger collection
2545 * of a ring dump etc.).
2546 */
2547 void i915_handle_error(struct drm_device *dev, bool wedged,
2548 const char *fmt, ...)
2549 {
2550 struct drm_i915_private *dev_priv = dev->dev_private;
2551 va_list args;
2552 char error_msg[80];
2553
2554 va_start(args, fmt);
2555 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2556 va_end(args);
2557
2558 i915_capture_error_state(dev, wedged, error_msg);
2559 i915_report_and_clear_eir(dev);
2560
2561 if (wedged) {
2562 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2563 &dev_priv->gpu_error.reset_counter);
2564
2565 /*
2566 * Wakeup waiting processes so that the reset work function
2567 * i915_error_work_func doesn't deadlock trying to grab various
2568 * locks. By bumping the reset counter first, the woken
2569 * processes will see a reset in progress and back off,
2570 * releasing their locks and then wait for the reset completion.
2571 * We must do this for _all_ gpu waiters that might hold locks
2572 * that the reset work needs to acquire.
2573 *
2574 * Note: The wake_up serves as the required memory barrier to
2575 * ensure that the waiters see the updated value of the reset
2576 * counter atomic_t.
2577 */
2578 i915_error_wake_up(dev_priv, false);
2579 }
2580
2581 /*
2582 * Our reset work can grab modeset locks (since it needs to reset the
2583 * state of outstanding pagelips). Hence it must not be run on our own
2584 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2585 * code will deadlock.
2586 */
2587 schedule_work(&dev_priv->gpu_error.work);
2588 }
2589
2590 /* Called from drm generic code, passed 'crtc' which
2591 * we use as a pipe index
2592 */
2593 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2594 {
2595 struct drm_i915_private *dev_priv = dev->dev_private;
2596 unsigned long irqflags;
2597
2598 if (!i915_pipe_enabled(dev, pipe))
2599 return -EINVAL;
2600
2601 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2602 if (INTEL_INFO(dev)->gen >= 4)
2603 i915_enable_pipestat(dev_priv, pipe,
2604 PIPE_START_VBLANK_INTERRUPT_STATUS);
2605 else
2606 i915_enable_pipestat(dev_priv, pipe,
2607 PIPE_VBLANK_INTERRUPT_STATUS);
2608 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2609
2610 return 0;
2611 }
2612
2613 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2614 {
2615 struct drm_i915_private *dev_priv = dev->dev_private;
2616 unsigned long irqflags;
2617 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2618 DE_PIPE_VBLANK(pipe);
2619
2620 if (!i915_pipe_enabled(dev, pipe))
2621 return -EINVAL;
2622
2623 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2624 ironlake_enable_display_irq(dev_priv, bit);
2625 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2626
2627 return 0;
2628 }
2629
2630 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2631 {
2632 struct drm_i915_private *dev_priv = dev->dev_private;
2633 unsigned long irqflags;
2634
2635 if (!i915_pipe_enabled(dev, pipe))
2636 return -EINVAL;
2637
2638 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2639 i915_enable_pipestat(dev_priv, pipe,
2640 PIPE_START_VBLANK_INTERRUPT_STATUS);
2641 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2642
2643 return 0;
2644 }
2645
2646 static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2647 {
2648 struct drm_i915_private *dev_priv = dev->dev_private;
2649 unsigned long irqflags;
2650
2651 if (!i915_pipe_enabled(dev, pipe))
2652 return -EINVAL;
2653
2654 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2655 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2656 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2657 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2658 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2659 return 0;
2660 }
2661
2662 /* Called from drm generic code, passed 'crtc' which
2663 * we use as a pipe index
2664 */
2665 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2666 {
2667 struct drm_i915_private *dev_priv = dev->dev_private;
2668 unsigned long irqflags;
2669
2670 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2671 i915_disable_pipestat(dev_priv, pipe,
2672 PIPE_VBLANK_INTERRUPT_STATUS |
2673 PIPE_START_VBLANK_INTERRUPT_STATUS);
2674 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2675 }
2676
2677 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2678 {
2679 struct drm_i915_private *dev_priv = dev->dev_private;
2680 unsigned long irqflags;
2681 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2682 DE_PIPE_VBLANK(pipe);
2683
2684 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2685 ironlake_disable_display_irq(dev_priv, bit);
2686 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2687 }
2688
2689 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2690 {
2691 struct drm_i915_private *dev_priv = dev->dev_private;
2692 unsigned long irqflags;
2693
2694 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2695 i915_disable_pipestat(dev_priv, pipe,
2696 PIPE_START_VBLANK_INTERRUPT_STATUS);
2697 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2698 }
2699
2700 static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2701 {
2702 struct drm_i915_private *dev_priv = dev->dev_private;
2703 unsigned long irqflags;
2704
2705 if (!i915_pipe_enabled(dev, pipe))
2706 return;
2707
2708 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2709 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2710 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2711 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2712 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2713 }
2714
2715 static u32
2716 ring_last_seqno(struct intel_engine_cs *ring)
2717 {
2718 return list_entry(ring->request_list.prev,
2719 struct drm_i915_gem_request, list)->seqno;
2720 }
2721
2722 static bool
2723 ring_idle(struct intel_engine_cs *ring, u32 seqno)
2724 {
2725 return (list_empty(&ring->request_list) ||
2726 i915_seqno_passed(seqno, ring_last_seqno(ring)));
2727 }
2728
2729 static bool
2730 ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
2731 {
2732 if (INTEL_INFO(dev)->gen >= 8) {
2733 return (ipehr >> 23) == 0x1c;
2734 } else {
2735 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2736 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2737 MI_SEMAPHORE_REGISTER);
2738 }
2739 }
2740
2741 static struct intel_engine_cs *
2742 semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset)
2743 {
2744 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2745 struct intel_engine_cs *signaller;
2746 int i;
2747
2748 if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
2749 for_each_ring(signaller, dev_priv, i) {
2750 if (ring == signaller)
2751 continue;
2752
2753 if (offset == signaller->semaphore.signal_ggtt[ring->id])
2754 return signaller;
2755 }
2756 } else {
2757 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2758
2759 for_each_ring(signaller, dev_priv, i) {
2760 if(ring == signaller)
2761 continue;
2762
2763 if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
2764 return signaller;
2765 }
2766 }
2767
2768 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2769 ring->id, ipehr, offset);
2770
2771 return NULL;
2772 }
2773
2774 static struct intel_engine_cs *
2775 semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
2776 {
2777 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2778 u32 cmd, ipehr, head;
2779 u64 offset = 0;
2780 int i, backwards;
2781
2782 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2783 if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
2784 return NULL;
2785
2786 /*
2787 * HEAD is likely pointing to the dword after the actual command,
2788 * so scan backwards until we find the MBOX. But limit it to just 3
2789 * or 4 dwords depending on the semaphore wait command size.
2790 * Note that we don't care about ACTHD here since that might
2791 * point at at batch, and semaphores are always emitted into the
2792 * ringbuffer itself.
2793 */
2794 head = I915_READ_HEAD(ring) & HEAD_ADDR;
2795 backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4;
2796
2797 for (i = backwards; i; --i) {
2798 /*
2799 * Be paranoid and presume the hw has gone off into the wild -
2800 * our ring is smaller than what the hardware (and hence
2801 * HEAD_ADDR) allows. Also handles wrap-around.
2802 */
2803 head &= ring->buffer->size - 1;
2804
2805 /* This here seems to blow up */
2806 cmd = ioread32(ring->buffer->virtual_start + head);
2807 if (cmd == ipehr)
2808 break;
2809
2810 head -= 4;
2811 }
2812
2813 if (!i)
2814 return NULL;
2815
2816 *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
2817 if (INTEL_INFO(ring->dev)->gen >= 8) {
2818 offset = ioread32(ring->buffer->virtual_start + head + 12);
2819 offset <<= 32;
2820 offset = ioread32(ring->buffer->virtual_start + head + 8);
2821 }
2822 return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
2823 }
2824
2825 static int semaphore_passed(struct intel_engine_cs *ring)
2826 {
2827 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2828 struct intel_engine_cs *signaller;
2829 u32 seqno;
2830
2831 ring->hangcheck.deadlock++;
2832
2833 signaller = semaphore_waits_for(ring, &seqno);
2834 if (signaller == NULL)
2835 return -1;
2836
2837 /* Prevent pathological recursion due to driver bugs */
2838 if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
2839 return -1;
2840
2841 if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
2842 return 1;
2843
2844 /* cursory check for an unkickable deadlock */
2845 if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
2846 semaphore_passed(signaller) < 0)
2847 return -1;
2848
2849 return 0;
2850 }
2851
2852 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2853 {
2854 struct intel_engine_cs *ring;
2855 int i;
2856
2857 for_each_ring(ring, dev_priv, i)
2858 ring->hangcheck.deadlock = 0;
2859 }
2860
2861 static enum intel_ring_hangcheck_action
2862 ring_stuck(struct intel_engine_cs *ring, u64 acthd)
2863 {
2864 struct drm_device *dev = ring->dev;
2865 struct drm_i915_private *dev_priv = dev->dev_private;
2866 u32 tmp;
2867
2868 if (acthd != ring->hangcheck.acthd) {
2869 if (acthd > ring->hangcheck.max_acthd) {
2870 ring->hangcheck.max_acthd = acthd;
2871 return HANGCHECK_ACTIVE;
2872 }
2873
2874 return HANGCHECK_ACTIVE_LOOP;
2875 }
2876
2877 if (IS_GEN2(dev))
2878 return HANGCHECK_HUNG;
2879
2880 /* Is the chip hanging on a WAIT_FOR_EVENT?
2881 * If so we can simply poke the RB_WAIT bit
2882 * and break the hang. This should work on
2883 * all but the second generation chipsets.
2884 */
2885 tmp = I915_READ_CTL(ring);
2886 if (tmp & RING_WAIT) {
2887 i915_handle_error(dev, false,
2888 "Kicking stuck wait on %s",
2889 ring->name);
2890 I915_WRITE_CTL(ring, tmp);
2891 return HANGCHECK_KICK;
2892 }
2893
2894 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2895 switch (semaphore_passed(ring)) {
2896 default:
2897 return HANGCHECK_HUNG;
2898 case 1:
2899 i915_handle_error(dev, false,
2900 "Kicking stuck semaphore on %s",
2901 ring->name);
2902 I915_WRITE_CTL(ring, tmp);
2903 return HANGCHECK_KICK;
2904 case 0:
2905 return HANGCHECK_WAIT;
2906 }
2907 }
2908
2909 return HANGCHECK_HUNG;
2910 }
2911
2912 /**
2913 * This is called when the chip hasn't reported back with completed
2914 * batchbuffers in a long time. We keep track per ring seqno progress and
2915 * if there are no progress, hangcheck score for that ring is increased.
2916 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2917 * we kick the ring. If we see no progress on three subsequent calls
2918 * we assume chip is wedged and try to fix it by resetting the chip.
2919 */
2920 static void i915_hangcheck_elapsed(unsigned long data)
2921 {
2922 struct drm_device *dev = (struct drm_device *)data;
2923 struct drm_i915_private *dev_priv = dev->dev_private;
2924 struct intel_engine_cs *ring;
2925 int i;
2926 int busy_count = 0, rings_hung = 0;
2927 bool stuck[I915_NUM_RINGS] = { 0 };
2928 #define BUSY 1
2929 #define KICK 5
2930 #define HUNG 20
2931
2932 if (!i915.enable_hangcheck)
2933 return;
2934
2935 for_each_ring(ring, dev_priv, i) {
2936 u64 acthd;
2937 u32 seqno;
2938 bool busy = true;
2939
2940 semaphore_clear_deadlocks(dev_priv);
2941
2942 seqno = ring->get_seqno(ring, false);
2943 acthd = intel_ring_get_active_head(ring);
2944
2945 if (ring->hangcheck.seqno == seqno) {
2946 if (ring_idle(ring, seqno)) {
2947 ring->hangcheck.action = HANGCHECK_IDLE;
2948
2949 if (waitqueue_active(&ring->irq_queue)) {
2950 /* Issue a wake-up to catch stuck h/w. */
2951 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2952 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2953 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2954 ring->name);
2955 else
2956 DRM_INFO("Fake missed irq on %s\n",
2957 ring->name);
2958 wake_up_all(&ring->irq_queue);
2959 }
2960 /* Safeguard against driver failure */
2961 ring->hangcheck.score += BUSY;
2962 } else
2963 busy = false;
2964 } else {
2965 /* We always increment the hangcheck score
2966 * if the ring is busy and still processing
2967 * the same request, so that no single request
2968 * can run indefinitely (such as a chain of
2969 * batches). The only time we do not increment
2970 * the hangcheck score on this ring, if this
2971 * ring is in a legitimate wait for another
2972 * ring. In that case the waiting ring is a
2973 * victim and we want to be sure we catch the
2974 * right culprit. Then every time we do kick
2975 * the ring, add a small increment to the
2976 * score so that we can catch a batch that is
2977 * being repeatedly kicked and so responsible
2978 * for stalling the machine.
2979 */
2980 ring->hangcheck.action = ring_stuck(ring,
2981 acthd);
2982
2983 switch (ring->hangcheck.action) {
2984 case HANGCHECK_IDLE:
2985 case HANGCHECK_WAIT:
2986 case HANGCHECK_ACTIVE:
2987 break;
2988 case HANGCHECK_ACTIVE_LOOP:
2989 ring->hangcheck.score += BUSY;
2990 break;
2991 case HANGCHECK_KICK:
2992 ring->hangcheck.score += KICK;
2993 break;
2994 case HANGCHECK_HUNG:
2995 ring->hangcheck.score += HUNG;
2996 stuck[i] = true;
2997 break;
2998 }
2999 }
3000 } else {
3001 ring->hangcheck.action = HANGCHECK_ACTIVE;
3002
3003 /* Gradually reduce the count so that we catch DoS
3004 * attempts across multiple batches.
3005 */
3006 if (ring->hangcheck.score > 0)
3007 ring->hangcheck.score--;
3008
3009 ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0;
3010 }
3011
3012 ring->hangcheck.seqno = seqno;
3013 ring->hangcheck.acthd = acthd;
3014 busy_count += busy;
3015 }
3016
3017 for_each_ring(ring, dev_priv, i) {
3018 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3019 DRM_INFO("%s on %s\n",
3020 stuck[i] ? "stuck" : "no progress",
3021 ring->name);
3022 rings_hung++;
3023 }
3024 }
3025
3026 if (rings_hung)
3027 return i915_handle_error(dev, true, "Ring hung");
3028
3029 if (busy_count)
3030 /* Reset timer case chip hangs without another request
3031 * being added */
3032 i915_queue_hangcheck(dev);
3033 }
3034
3035 void i915_queue_hangcheck(struct drm_device *dev)
3036 {
3037 struct drm_i915_private *dev_priv = dev->dev_private;
3038 if (!i915.enable_hangcheck)
3039 return;
3040
3041 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
3042 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
3043 }
3044
3045 static void ibx_irq_reset(struct drm_device *dev)
3046 {
3047 struct drm_i915_private *dev_priv = dev->dev_private;
3048
3049 if (HAS_PCH_NOP(dev))
3050 return;
3051
3052 GEN5_IRQ_RESET(SDE);
3053
3054 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3055 I915_WRITE(SERR_INT, 0xffffffff);
3056 }
3057
3058 /*
3059 * SDEIER is also touched by the interrupt handler to work around missed PCH
3060 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3061 * instead we unconditionally enable all PCH interrupt sources here, but then
3062 * only unmask them as needed with SDEIMR.
3063 *
3064 * This function needs to be called before interrupts are enabled.
3065 */
3066 static void ibx_irq_pre_postinstall(struct drm_device *dev)
3067 {
3068 struct drm_i915_private *dev_priv = dev->dev_private;
3069
3070 if (HAS_PCH_NOP(dev))
3071 return;
3072
3073 WARN_ON(I915_READ(SDEIER) != 0);
3074 I915_WRITE(SDEIER, 0xffffffff);
3075 POSTING_READ(SDEIER);
3076 }
3077
3078 static void gen5_gt_irq_reset(struct drm_device *dev)
3079 {
3080 struct drm_i915_private *dev_priv = dev->dev_private;
3081
3082 GEN5_IRQ_RESET(GT);
3083 if (INTEL_INFO(dev)->gen >= 6)
3084 GEN5_IRQ_RESET(GEN6_PM);
3085 }
3086
3087 /* drm_dma.h hooks
3088 */
3089 static void ironlake_irq_reset(struct drm_device *dev)
3090 {
3091 struct drm_i915_private *dev_priv = dev->dev_private;
3092
3093 I915_WRITE(HWSTAM, 0xffffffff);
3094
3095 GEN5_IRQ_RESET(DE);
3096 if (IS_GEN7(dev))
3097 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3098
3099 gen5_gt_irq_reset(dev);
3100
3101 ibx_irq_reset(dev);
3102 }
3103
3104 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3105 {
3106 enum pipe pipe;
3107
3108 I915_WRITE(PORT_HOTPLUG_EN, 0);
3109 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3110
3111 for_each_pipe(dev_priv, pipe)
3112 I915_WRITE(PIPESTAT(pipe), 0xffff);
3113
3114 GEN5_IRQ_RESET(VLV_);
3115 }
3116
3117 static void valleyview_irq_preinstall(struct drm_device *dev)
3118 {
3119 struct drm_i915_private *dev_priv = dev->dev_private;
3120
3121 /* VLV magic */
3122 I915_WRITE(VLV_IMR, 0);
3123 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
3124 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
3125 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
3126
3127 gen5_gt_irq_reset(dev);
3128
3129 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3130
3131 vlv_display_irq_reset(dev_priv);
3132 }
3133
3134 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3135 {
3136 GEN8_IRQ_RESET_NDX(GT, 0);
3137 GEN8_IRQ_RESET_NDX(GT, 1);
3138 GEN8_IRQ_RESET_NDX(GT, 2);
3139 GEN8_IRQ_RESET_NDX(GT, 3);
3140 }
3141
3142 static void gen8_irq_reset(struct drm_device *dev)
3143 {
3144 struct drm_i915_private *dev_priv = dev->dev_private;
3145 int pipe;
3146
3147 I915_WRITE(GEN8_MASTER_IRQ, 0);
3148 POSTING_READ(GEN8_MASTER_IRQ);
3149
3150 gen8_gt_irq_reset(dev_priv);
3151
3152 for_each_pipe(dev_priv, pipe)
3153 if (intel_display_power_is_enabled(dev_priv,
3154 POWER_DOMAIN_PIPE(pipe)))
3155 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3156
3157 GEN5_IRQ_RESET(GEN8_DE_PORT_);
3158 GEN5_IRQ_RESET(GEN8_DE_MISC_);
3159 GEN5_IRQ_RESET(GEN8_PCU_);
3160
3161 ibx_irq_reset(dev);
3162 }
3163
3164 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv)
3165 {
3166 uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3167
3168 spin_lock_irq(&dev_priv->irq_lock);
3169 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B],
3170 ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
3171 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C],
3172 ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
3173 spin_unlock_irq(&dev_priv->irq_lock);
3174 }
3175
3176 static void cherryview_irq_preinstall(struct drm_device *dev)
3177 {
3178 struct drm_i915_private *dev_priv = dev->dev_private;
3179
3180 I915_WRITE(GEN8_MASTER_IRQ, 0);
3181 POSTING_READ(GEN8_MASTER_IRQ);
3182
3183 gen8_gt_irq_reset(dev_priv);
3184
3185 GEN5_IRQ_RESET(GEN8_PCU_);
3186
3187 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3188
3189 vlv_display_irq_reset(dev_priv);
3190 }
3191
3192 static void ibx_hpd_irq_setup(struct drm_device *dev)
3193 {
3194 struct drm_i915_private *dev_priv = dev->dev_private;
3195 struct intel_encoder *intel_encoder;
3196 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
3197
3198 if (HAS_PCH_IBX(dev)) {
3199 hotplug_irqs = SDE_HOTPLUG_MASK;
3200 for_each_intel_encoder(dev, intel_encoder)
3201 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3202 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
3203 } else {
3204 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3205 for_each_intel_encoder(dev, intel_encoder)
3206 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3207 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
3208 }
3209
3210 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3211
3212 /*
3213 * Enable digital hotplug on the PCH, and configure the DP short pulse
3214 * duration to 2ms (which is the minimum in the Display Port spec)
3215 *
3216 * This register is the same on all known PCH chips.
3217 */
3218 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3219 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3220 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3221 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3222 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3223 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3224 }
3225
3226 static void ibx_irq_postinstall(struct drm_device *dev)
3227 {
3228 struct drm_i915_private *dev_priv = dev->dev_private;
3229 u32 mask;
3230
3231 if (HAS_PCH_NOP(dev))
3232 return;
3233
3234 if (HAS_PCH_IBX(dev))
3235 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3236 else
3237 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3238
3239 GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
3240 I915_WRITE(SDEIMR, ~mask);
3241 }
3242
3243 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3244 {
3245 struct drm_i915_private *dev_priv = dev->dev_private;
3246 u32 pm_irqs, gt_irqs;
3247
3248 pm_irqs = gt_irqs = 0;
3249
3250 dev_priv->gt_irq_mask = ~0;
3251 if (HAS_L3_DPF(dev)) {
3252 /* L3 parity interrupt is always unmasked. */
3253 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3254 gt_irqs |= GT_PARITY_ERROR(dev);
3255 }
3256
3257 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3258 if (IS_GEN5(dev)) {
3259 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3260 ILK_BSD_USER_INTERRUPT;
3261 } else {
3262 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3263 }
3264
3265 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3266
3267 if (INTEL_INFO(dev)->gen >= 6) {
3268 pm_irqs |= dev_priv->pm_rps_events;
3269
3270 if (HAS_VEBOX(dev))
3271 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3272
3273 dev_priv->pm_irq_mask = 0xffffffff;
3274 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3275 }
3276 }
3277
3278 static int ironlake_irq_postinstall(struct drm_device *dev)
3279 {
3280 struct drm_i915_private *dev_priv = dev->dev_private;
3281 u32 display_mask, extra_mask;
3282
3283 if (INTEL_INFO(dev)->gen >= 7) {
3284 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3285 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3286 DE_PLANEB_FLIP_DONE_IVB |
3287 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3288 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3289 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
3290 } else {
3291 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3292 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3293 DE_AUX_CHANNEL_A |
3294 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3295 DE_POISON);
3296 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3297 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
3298 }
3299
3300 dev_priv->irq_mask = ~display_mask;
3301
3302 I915_WRITE(HWSTAM, 0xeffe);
3303
3304 ibx_irq_pre_postinstall(dev);
3305
3306 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3307
3308 gen5_gt_irq_postinstall(dev);
3309
3310 ibx_irq_postinstall(dev);
3311
3312 if (IS_IRONLAKE_M(dev)) {
3313 /* Enable PCU event interrupts
3314 *
3315 * spinlocking not required here for correctness since interrupt
3316 * setup is guaranteed to run in single-threaded context. But we
3317 * need it to make the assert_spin_locked happy. */
3318 spin_lock_irq(&dev_priv->irq_lock);
3319 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
3320 spin_unlock_irq(&dev_priv->irq_lock);
3321 }
3322
3323 return 0;
3324 }
3325
3326 static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3327 {
3328 u32 pipestat_mask;
3329 u32 iir_mask;
3330 enum pipe pipe;
3331
3332 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3333 PIPE_FIFO_UNDERRUN_STATUS;
3334
3335 for_each_pipe(dev_priv, pipe)
3336 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3337 POSTING_READ(PIPESTAT(PIPE_A));
3338
3339 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3340 PIPE_CRC_DONE_INTERRUPT_STATUS;
3341
3342 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3343 for_each_pipe(dev_priv, pipe)
3344 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3345
3346 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3347 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3348 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3349 if (IS_CHERRYVIEW(dev_priv))
3350 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3351 dev_priv->irq_mask &= ~iir_mask;
3352
3353 I915_WRITE(VLV_IIR, iir_mask);
3354 I915_WRITE(VLV_IIR, iir_mask);
3355 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3356 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3357 POSTING_READ(VLV_IMR);
3358 }
3359
3360 static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3361 {
3362 u32 pipestat_mask;
3363 u32 iir_mask;
3364 enum pipe pipe;
3365
3366 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3367 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3368 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3369 if (IS_CHERRYVIEW(dev_priv))
3370 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3371
3372 dev_priv->irq_mask |= iir_mask;
3373 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3374 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3375 I915_WRITE(VLV_IIR, iir_mask);
3376 I915_WRITE(VLV_IIR, iir_mask);
3377 POSTING_READ(VLV_IIR);
3378
3379 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3380 PIPE_CRC_DONE_INTERRUPT_STATUS;
3381
3382 i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3383 for_each_pipe(dev_priv, pipe)
3384 i915_disable_pipestat(dev_priv, pipe, pipestat_mask);
3385
3386 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3387 PIPE_FIFO_UNDERRUN_STATUS;
3388
3389 for_each_pipe(dev_priv, pipe)
3390 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3391 POSTING_READ(PIPESTAT(PIPE_A));
3392 }
3393
3394 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3395 {
3396 assert_spin_locked(&dev_priv->irq_lock);
3397
3398 if (dev_priv->display_irqs_enabled)
3399 return;
3400
3401 dev_priv->display_irqs_enabled = true;
3402
3403 if (intel_irqs_enabled(dev_priv))
3404 valleyview_display_irqs_install(dev_priv);
3405 }
3406
3407 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3408 {
3409 assert_spin_locked(&dev_priv->irq_lock);
3410
3411 if (!dev_priv->display_irqs_enabled)
3412 return;
3413
3414 dev_priv->display_irqs_enabled = false;
3415
3416 if (intel_irqs_enabled(dev_priv))
3417 valleyview_display_irqs_uninstall(dev_priv);
3418 }
3419
3420 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3421 {
3422 dev_priv->irq_mask = ~0;
3423
3424 I915_WRITE(PORT_HOTPLUG_EN, 0);
3425 POSTING_READ(PORT_HOTPLUG_EN);
3426
3427 I915_WRITE(VLV_IIR, 0xffffffff);
3428 I915_WRITE(VLV_IIR, 0xffffffff);
3429 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3430 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3431 POSTING_READ(VLV_IMR);
3432
3433 /* Interrupt setup is already guaranteed to be single-threaded, this is
3434 * just to make the assert_spin_locked check happy. */
3435 spin_lock_irq(&dev_priv->irq_lock);
3436 if (dev_priv->display_irqs_enabled)
3437 valleyview_display_irqs_install(dev_priv);
3438 spin_unlock_irq(&dev_priv->irq_lock);
3439 }
3440
3441 static int valleyview_irq_postinstall(struct drm_device *dev)
3442 {
3443 struct drm_i915_private *dev_priv = dev->dev_private;
3444
3445 vlv_display_irq_postinstall(dev_priv);
3446
3447 gen5_gt_irq_postinstall(dev);
3448
3449 /* ack & enable invalid PTE error interrupts */
3450 #if 0 /* FIXME: add support to irq handler for checking these bits */
3451 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3452 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3453 #endif
3454
3455 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3456
3457 return 0;
3458 }
3459
3460 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3461 {
3462 /* These are interrupts we'll toggle with the ring mask register */
3463 uint32_t gt_interrupts[] = {
3464 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3465 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3466 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3467 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3468 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3469 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3470 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3471 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3472 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3473 0,
3474 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3475 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3476 };
3477
3478 dev_priv->pm_irq_mask = 0xffffffff;
3479 GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3480 GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3481 GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, dev_priv->pm_rps_events);
3482 GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3483 }
3484
3485 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3486 {
3487 uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3488 uint32_t de_pipe_enables;
3489 int pipe;
3490
3491 if (IS_GEN9(dev_priv))
3492 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3493 GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3494 else
3495 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3496 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3497
3498 de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3499 GEN8_PIPE_FIFO_UNDERRUN;
3500
3501 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3502 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3503 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3504
3505 for_each_pipe(dev_priv, pipe)
3506 if (intel_display_power_is_enabled(dev_priv,
3507 POWER_DOMAIN_PIPE(pipe)))
3508 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3509 dev_priv->de_irq_mask[pipe],
3510 de_pipe_enables);
3511
3512 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~GEN8_AUX_CHANNEL_A, GEN8_AUX_CHANNEL_A);
3513 }
3514
3515 static int gen8_irq_postinstall(struct drm_device *dev)
3516 {
3517 struct drm_i915_private *dev_priv = dev->dev_private;
3518
3519 ibx_irq_pre_postinstall(dev);
3520
3521 gen8_gt_irq_postinstall(dev_priv);
3522 gen8_de_irq_postinstall(dev_priv);
3523
3524 ibx_irq_postinstall(dev);
3525
3526 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3527 POSTING_READ(GEN8_MASTER_IRQ);
3528
3529 return 0;
3530 }
3531
3532 static int cherryview_irq_postinstall(struct drm_device *dev)
3533 {
3534 struct drm_i915_private *dev_priv = dev->dev_private;
3535 u32 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
3536 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3537 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3538 I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3539 u32 pipestat_enable = PLANE_FLIP_DONE_INT_STATUS_VLV |
3540 PIPE_CRC_DONE_INTERRUPT_STATUS;
3541 int pipe;
3542
3543 /*
3544 * Leave vblank interrupts masked initially. enable/disable will
3545 * toggle them based on usage.
3546 */
3547 dev_priv->irq_mask = ~enable_mask;
3548
3549 for_each_pipe(dev_priv, pipe)
3550 I915_WRITE(PIPESTAT(pipe), 0xffff);
3551
3552 spin_lock_irq(&dev_priv->irq_lock);
3553 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3554 for_each_pipe(dev_priv, pipe)
3555 i915_enable_pipestat(dev_priv, pipe, pipestat_enable);
3556 spin_unlock_irq(&dev_priv->irq_lock);
3557
3558 I915_WRITE(VLV_IIR, 0xffffffff);
3559 I915_WRITE(VLV_IIR, 0xffffffff);
3560 I915_WRITE(VLV_IER, enable_mask);
3561 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3562 POSTING_READ(VLV_IMR);
3563
3564 gen8_gt_irq_postinstall(dev_priv);
3565
3566 I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
3567 POSTING_READ(GEN8_MASTER_IRQ);
3568
3569 return 0;
3570 }
3571
3572 static void gen8_irq_uninstall(struct drm_device *dev)
3573 {
3574 struct drm_i915_private *dev_priv = dev->dev_private;
3575
3576 if (!dev_priv)
3577 return;
3578
3579 gen8_irq_reset(dev);
3580 }
3581
3582 static void valleyview_irq_uninstall(struct drm_device *dev)
3583 {
3584 struct drm_i915_private *dev_priv = dev->dev_private;
3585
3586 if (!dev_priv)
3587 return;
3588
3589 I915_WRITE(VLV_MASTER_IER, 0);
3590
3591 gen5_gt_irq_reset(dev);
3592
3593 I915_WRITE(HWSTAM, 0xffffffff);
3594
3595 /* Interrupt setup is already guaranteed to be single-threaded, this is
3596 * just to make the assert_spin_locked check happy. */
3597 spin_lock_irq(&dev_priv->irq_lock);
3598 if (dev_priv->display_irqs_enabled)
3599 valleyview_display_irqs_uninstall(dev_priv);
3600 spin_unlock_irq(&dev_priv->irq_lock);
3601
3602 vlv_display_irq_reset(dev_priv);
3603
3604 dev_priv->irq_mask = 0;
3605 }
3606
3607 static void cherryview_irq_uninstall(struct drm_device *dev)
3608 {
3609 struct drm_i915_private *dev_priv = dev->dev_private;
3610 int pipe;
3611
3612 if (!dev_priv)
3613 return;
3614
3615 I915_WRITE(GEN8_MASTER_IRQ, 0);
3616 POSTING_READ(GEN8_MASTER_IRQ);
3617
3618 gen8_gt_irq_reset(dev_priv);
3619
3620 GEN5_IRQ_RESET(GEN8_PCU_);
3621
3622 I915_WRITE(PORT_HOTPLUG_EN, 0);
3623 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3624
3625 for_each_pipe(dev_priv, pipe)
3626 I915_WRITE(PIPESTAT(pipe), 0xffff);
3627
3628 GEN5_IRQ_RESET(VLV_);
3629 }
3630
3631 static void ironlake_irq_uninstall(struct drm_device *dev)
3632 {
3633 struct drm_i915_private *dev_priv = dev->dev_private;
3634
3635 if (!dev_priv)
3636 return;
3637
3638 ironlake_irq_reset(dev);
3639 }
3640
3641 static void i8xx_irq_preinstall(struct drm_device * dev)
3642 {
3643 struct drm_i915_private *dev_priv = dev->dev_private;
3644 int pipe;
3645
3646 for_each_pipe(dev_priv, pipe)
3647 I915_WRITE(PIPESTAT(pipe), 0);
3648 I915_WRITE16(IMR, 0xffff);
3649 I915_WRITE16(IER, 0x0);
3650 POSTING_READ16(IER);
3651 }
3652
3653 static int i8xx_irq_postinstall(struct drm_device *dev)
3654 {
3655 struct drm_i915_private *dev_priv = dev->dev_private;
3656
3657 I915_WRITE16(EMR,
3658 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3659
3660 /* Unmask the interrupts that we always want on. */
3661 dev_priv->irq_mask =
3662 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3663 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3664 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3665 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3666 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3667 I915_WRITE16(IMR, dev_priv->irq_mask);
3668
3669 I915_WRITE16(IER,
3670 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3671 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3672 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3673 I915_USER_INTERRUPT);
3674 POSTING_READ16(IER);
3675
3676 /* Interrupt setup is already guaranteed to be single-threaded, this is
3677 * just to make the assert_spin_locked check happy. */
3678 spin_lock_irq(&dev_priv->irq_lock);
3679 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3680 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3681 spin_unlock_irq(&dev_priv->irq_lock);
3682
3683 return 0;
3684 }
3685
3686 /*
3687 * Returns true when a page flip has completed.
3688 */
3689 static bool i8xx_handle_vblank(struct drm_device *dev,
3690 int plane, int pipe, u32 iir)
3691 {
3692 struct drm_i915_private *dev_priv = dev->dev_private;
3693 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3694
3695 if (!intel_pipe_handle_vblank(dev, pipe))
3696 return false;
3697
3698 if ((iir & flip_pending) == 0)
3699 goto check_page_flip;
3700
3701 intel_prepare_page_flip(dev, plane);
3702
3703 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3704 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3705 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3706 * the flip is completed (no longer pending). Since this doesn't raise
3707 * an interrupt per se, we watch for the change at vblank.
3708 */
3709 if (I915_READ16(ISR) & flip_pending)
3710 goto check_page_flip;
3711
3712 intel_finish_page_flip(dev, pipe);
3713 return true;
3714
3715 check_page_flip:
3716 intel_check_page_flip(dev, pipe);
3717 return false;
3718 }
3719
3720 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3721 {
3722 struct drm_device *dev = arg;
3723 struct drm_i915_private *dev_priv = dev->dev_private;
3724 u16 iir, new_iir;
3725 u32 pipe_stats[2];
3726 int pipe;
3727 u16 flip_mask =
3728 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3729 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3730
3731 iir = I915_READ16(IIR);
3732 if (iir == 0)
3733 return IRQ_NONE;
3734
3735 while (iir & ~flip_mask) {
3736 /* Can't rely on pipestat interrupt bit in iir as it might
3737 * have been cleared after the pipestat interrupt was received.
3738 * It doesn't set the bit in iir again, but it still produces
3739 * interrupts (for non-MSI).
3740 */
3741 spin_lock(&dev_priv->irq_lock);
3742 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3743 i915_handle_error(dev, false,
3744 "Command parser error, iir 0x%08x",
3745 iir);
3746
3747 for_each_pipe(dev_priv, pipe) {
3748 int reg = PIPESTAT(pipe);
3749 pipe_stats[pipe] = I915_READ(reg);
3750
3751 /*
3752 * Clear the PIPE*STAT regs before the IIR
3753 */
3754 if (pipe_stats[pipe] & 0x8000ffff)
3755 I915_WRITE(reg, pipe_stats[pipe]);
3756 }
3757 spin_unlock(&dev_priv->irq_lock);
3758
3759 I915_WRITE16(IIR, iir & ~flip_mask);
3760 new_iir = I915_READ16(IIR); /* Flush posted writes */
3761
3762 i915_update_dri1_breadcrumb(dev);
3763
3764 if (iir & I915_USER_INTERRUPT)
3765 notify_ring(dev, &dev_priv->ring[RCS]);
3766
3767 for_each_pipe(dev_priv, pipe) {
3768 int plane = pipe;
3769 if (HAS_FBC(dev))
3770 plane = !plane;
3771
3772 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3773 i8xx_handle_vblank(dev, plane, pipe, iir))
3774 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3775
3776 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3777 i9xx_pipe_crc_irq_handler(dev, pipe);
3778
3779 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3780 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3781 pipe);
3782 }
3783
3784 iir = new_iir;
3785 }
3786
3787 return IRQ_HANDLED;
3788 }
3789
3790 static void i8xx_irq_uninstall(struct drm_device * dev)
3791 {
3792 struct drm_i915_private *dev_priv = dev->dev_private;
3793 int pipe;
3794
3795 for_each_pipe(dev_priv, pipe) {
3796 /* Clear enable bits; then clear status bits */
3797 I915_WRITE(PIPESTAT(pipe), 0);
3798 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3799 }
3800 I915_WRITE16(IMR, 0xffff);
3801 I915_WRITE16(IER, 0x0);
3802 I915_WRITE16(IIR, I915_READ16(IIR));
3803 }
3804
3805 static void i915_irq_preinstall(struct drm_device * dev)
3806 {
3807 struct drm_i915_private *dev_priv = dev->dev_private;
3808 int pipe;
3809
3810 if (I915_HAS_HOTPLUG(dev)) {
3811 I915_WRITE(PORT_HOTPLUG_EN, 0);
3812 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3813 }
3814
3815 I915_WRITE16(HWSTAM, 0xeffe);
3816 for_each_pipe(dev_priv, pipe)
3817 I915_WRITE(PIPESTAT(pipe), 0);
3818 I915_WRITE(IMR, 0xffffffff);
3819 I915_WRITE(IER, 0x0);
3820 POSTING_READ(IER);
3821 }
3822
3823 static int i915_irq_postinstall(struct drm_device *dev)
3824 {
3825 struct drm_i915_private *dev_priv = dev->dev_private;
3826 u32 enable_mask;
3827
3828 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3829
3830 /* Unmask the interrupts that we always want on. */
3831 dev_priv->irq_mask =
3832 ~(I915_ASLE_INTERRUPT |
3833 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3834 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3835 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3836 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3837 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3838
3839 enable_mask =
3840 I915_ASLE_INTERRUPT |
3841 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3842 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3843 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3844 I915_USER_INTERRUPT;
3845
3846 if (I915_HAS_HOTPLUG(dev)) {
3847 I915_WRITE(PORT_HOTPLUG_EN, 0);
3848 POSTING_READ(PORT_HOTPLUG_EN);
3849
3850 /* Enable in IER... */
3851 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3852 /* and unmask in IMR */
3853 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3854 }
3855
3856 I915_WRITE(IMR, dev_priv->irq_mask);
3857 I915_WRITE(IER, enable_mask);
3858 POSTING_READ(IER);
3859
3860 i915_enable_asle_pipestat(dev);
3861
3862 /* Interrupt setup is already guaranteed to be single-threaded, this is
3863 * just to make the assert_spin_locked check happy. */
3864 spin_lock_irq(&dev_priv->irq_lock);
3865 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3866 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3867 spin_unlock_irq(&dev_priv->irq_lock);
3868
3869 return 0;
3870 }
3871
3872 /*
3873 * Returns true when a page flip has completed.
3874 */
3875 static bool i915_handle_vblank(struct drm_device *dev,
3876 int plane, int pipe, u32 iir)
3877 {
3878 struct drm_i915_private *dev_priv = dev->dev_private;
3879 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3880
3881 if (!intel_pipe_handle_vblank(dev, pipe))
3882 return false;
3883
3884 if ((iir & flip_pending) == 0)
3885 goto check_page_flip;
3886
3887 intel_prepare_page_flip(dev, plane);
3888
3889 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3890 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3891 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3892 * the flip is completed (no longer pending). Since this doesn't raise
3893 * an interrupt per se, we watch for the change at vblank.
3894 */
3895 if (I915_READ(ISR) & flip_pending)
3896 goto check_page_flip;
3897
3898 intel_finish_page_flip(dev, pipe);
3899 return true;
3900
3901 check_page_flip:
3902 intel_check_page_flip(dev, pipe);
3903 return false;
3904 }
3905
3906 static irqreturn_t i915_irq_handler(int irq, void *arg)
3907 {
3908 struct drm_device *dev = arg;
3909 struct drm_i915_private *dev_priv = dev->dev_private;
3910 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3911 u32 flip_mask =
3912 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3913 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3914 int pipe, ret = IRQ_NONE;
3915
3916 iir = I915_READ(IIR);
3917 do {
3918 bool irq_received = (iir & ~flip_mask) != 0;
3919 bool blc_event = false;
3920
3921 /* Can't rely on pipestat interrupt bit in iir as it might
3922 * have been cleared after the pipestat interrupt was received.
3923 * It doesn't set the bit in iir again, but it still produces
3924 * interrupts (for non-MSI).
3925 */
3926 spin_lock(&dev_priv->irq_lock);
3927 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3928 i915_handle_error(dev, false,
3929 "Command parser error, iir 0x%08x",
3930 iir);
3931
3932 for_each_pipe(dev_priv, pipe) {
3933 int reg = PIPESTAT(pipe);
3934 pipe_stats[pipe] = I915_READ(reg);
3935
3936 /* Clear the PIPE*STAT regs before the IIR */
3937 if (pipe_stats[pipe] & 0x8000ffff) {
3938 I915_WRITE(reg, pipe_stats[pipe]);
3939 irq_received = true;
3940 }
3941 }
3942 spin_unlock(&dev_priv->irq_lock);
3943
3944 if (!irq_received)
3945 break;
3946
3947 /* Consume port. Then clear IIR or we'll miss events */
3948 if (I915_HAS_HOTPLUG(dev) &&
3949 iir & I915_DISPLAY_PORT_INTERRUPT)
3950 i9xx_hpd_irq_handler(dev);
3951
3952 I915_WRITE(IIR, iir & ~flip_mask);
3953 new_iir = I915_READ(IIR); /* Flush posted writes */
3954
3955 if (iir & I915_USER_INTERRUPT)
3956 notify_ring(dev, &dev_priv->ring[RCS]);
3957
3958 for_each_pipe(dev_priv, pipe) {
3959 int plane = pipe;
3960 if (HAS_FBC(dev))
3961 plane = !plane;
3962
3963 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3964 i915_handle_vblank(dev, plane, pipe, iir))
3965 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3966
3967 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3968 blc_event = true;
3969
3970 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3971 i9xx_pipe_crc_irq_handler(dev, pipe);
3972
3973 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3974 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3975 pipe);
3976 }
3977
3978 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3979 intel_opregion_asle_intr(dev);
3980
3981 /* With MSI, interrupts are only generated when iir
3982 * transitions from zero to nonzero. If another bit got
3983 * set while we were handling the existing iir bits, then
3984 * we would never get another interrupt.
3985 *
3986 * This is fine on non-MSI as well, as if we hit this path
3987 * we avoid exiting the interrupt handler only to generate
3988 * another one.
3989 *
3990 * Note that for MSI this could cause a stray interrupt report
3991 * if an interrupt landed in the time between writing IIR and
3992 * the posting read. This should be rare enough to never
3993 * trigger the 99% of 100,000 interrupts test for disabling
3994 * stray interrupts.
3995 */
3996 ret = IRQ_HANDLED;
3997 iir = new_iir;
3998 } while (iir & ~flip_mask);
3999
4000 i915_update_dri1_breadcrumb(dev);
4001
4002 return ret;
4003 }
4004
4005 static void i915_irq_uninstall(struct drm_device * dev)
4006 {
4007 struct drm_i915_private *dev_priv = dev->dev_private;
4008 int pipe;
4009
4010 if (I915_HAS_HOTPLUG(dev)) {
4011 I915_WRITE(PORT_HOTPLUG_EN, 0);
4012 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4013 }
4014
4015 I915_WRITE16(HWSTAM, 0xffff);
4016 for_each_pipe(dev_priv, pipe) {
4017 /* Clear enable bits; then clear status bits */
4018 I915_WRITE(PIPESTAT(pipe), 0);
4019 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4020 }
4021 I915_WRITE(IMR, 0xffffffff);
4022 I915_WRITE(IER, 0x0);
4023
4024 I915_WRITE(IIR, I915_READ(IIR));
4025 }
4026
4027 static void i965_irq_preinstall(struct drm_device * dev)
4028 {
4029 struct drm_i915_private *dev_priv = dev->dev_private;
4030 int pipe;
4031
4032 I915_WRITE(PORT_HOTPLUG_EN, 0);
4033 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4034
4035 I915_WRITE(HWSTAM, 0xeffe);
4036 for_each_pipe(dev_priv, pipe)
4037 I915_WRITE(PIPESTAT(pipe), 0);
4038 I915_WRITE(IMR, 0xffffffff);
4039 I915_WRITE(IER, 0x0);
4040 POSTING_READ(IER);
4041 }
4042
4043 static int i965_irq_postinstall(struct drm_device *dev)
4044 {
4045 struct drm_i915_private *dev_priv = dev->dev_private;
4046 u32 enable_mask;
4047 u32 error_mask;
4048
4049 /* Unmask the interrupts that we always want on. */
4050 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4051 I915_DISPLAY_PORT_INTERRUPT |
4052 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4053 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4054 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4055 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4056 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4057
4058 enable_mask = ~dev_priv->irq_mask;
4059 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4060 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4061 enable_mask |= I915_USER_INTERRUPT;
4062
4063 if (IS_G4X(dev))
4064 enable_mask |= I915_BSD_USER_INTERRUPT;
4065
4066 /* Interrupt setup is already guaranteed to be single-threaded, this is
4067 * just to make the assert_spin_locked check happy. */
4068 spin_lock_irq(&dev_priv->irq_lock);
4069 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4070 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4071 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4072 spin_unlock_irq(&dev_priv->irq_lock);
4073
4074 /*
4075 * Enable some error detection, note the instruction error mask
4076 * bit is reserved, so we leave it masked.
4077 */
4078 if (IS_G4X(dev)) {
4079 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4080 GM45_ERROR_MEM_PRIV |
4081 GM45_ERROR_CP_PRIV |
4082 I915_ERROR_MEMORY_REFRESH);
4083 } else {
4084 error_mask = ~(I915_ERROR_PAGE_TABLE |
4085 I915_ERROR_MEMORY_REFRESH);
4086 }
4087 I915_WRITE(EMR, error_mask);
4088
4089 I915_WRITE(IMR, dev_priv->irq_mask);
4090 I915_WRITE(IER, enable_mask);
4091 POSTING_READ(IER);
4092
4093 I915_WRITE(PORT_HOTPLUG_EN, 0);
4094 POSTING_READ(PORT_HOTPLUG_EN);
4095
4096 i915_enable_asle_pipestat(dev);
4097
4098 return 0;
4099 }
4100
4101 static void i915_hpd_irq_setup(struct drm_device *dev)
4102 {
4103 struct drm_i915_private *dev_priv = dev->dev_private;
4104 struct intel_encoder *intel_encoder;
4105 u32 hotplug_en;
4106
4107 assert_spin_locked(&dev_priv->irq_lock);
4108
4109 if (I915_HAS_HOTPLUG(dev)) {
4110 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
4111 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
4112 /* Note HDMI and DP share hotplug bits */
4113 /* enable bits are the same for all generations */
4114 for_each_intel_encoder(dev, intel_encoder)
4115 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
4116 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
4117 /* Programming the CRT detection parameters tends
4118 to generate a spurious hotplug event about three
4119 seconds later. So just do it once.
4120 */
4121 if (IS_G4X(dev))
4122 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4123 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
4124 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4125
4126 /* Ignore TV since it's buggy */
4127 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
4128 }
4129 }
4130
4131 static irqreturn_t i965_irq_handler(int irq, void *arg)
4132 {
4133 struct drm_device *dev = arg;
4134 struct drm_i915_private *dev_priv = dev->dev_private;
4135 u32 iir, new_iir;
4136 u32 pipe_stats[I915_MAX_PIPES];
4137 int ret = IRQ_NONE, pipe;
4138 u32 flip_mask =
4139 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4140 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4141
4142 iir = I915_READ(IIR);
4143
4144 for (;;) {
4145 bool irq_received = (iir & ~flip_mask) != 0;
4146 bool blc_event = false;
4147
4148 /* Can't rely on pipestat interrupt bit in iir as it might
4149 * have been cleared after the pipestat interrupt was received.
4150 * It doesn't set the bit in iir again, but it still produces
4151 * interrupts (for non-MSI).
4152 */
4153 spin_lock(&dev_priv->irq_lock);
4154 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4155 i915_handle_error(dev, false,
4156 "Command parser error, iir 0x%08x",
4157 iir);
4158
4159 for_each_pipe(dev_priv, pipe) {
4160 int reg = PIPESTAT(pipe);
4161 pipe_stats[pipe] = I915_READ(reg);
4162
4163 /*
4164 * Clear the PIPE*STAT regs before the IIR
4165 */
4166 if (pipe_stats[pipe] & 0x8000ffff) {
4167 I915_WRITE(reg, pipe_stats[pipe]);
4168 irq_received = true;
4169 }
4170 }
4171 spin_unlock(&dev_priv->irq_lock);
4172
4173 if (!irq_received)
4174 break;
4175
4176 ret = IRQ_HANDLED;
4177
4178 /* Consume port. Then clear IIR or we'll miss events */
4179 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4180 i9xx_hpd_irq_handler(dev);
4181
4182 I915_WRITE(IIR, iir & ~flip_mask);
4183 new_iir = I915_READ(IIR); /* Flush posted writes */
4184
4185 if (iir & I915_USER_INTERRUPT)
4186 notify_ring(dev, &dev_priv->ring[RCS]);
4187 if (iir & I915_BSD_USER_INTERRUPT)
4188 notify_ring(dev, &dev_priv->ring[VCS]);
4189
4190 for_each_pipe(dev_priv, pipe) {
4191 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4192 i915_handle_vblank(dev, pipe, pipe, iir))
4193 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4194
4195 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4196 blc_event = true;
4197
4198 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4199 i9xx_pipe_crc_irq_handler(dev, pipe);
4200
4201 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4202 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4203 }
4204
4205 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4206 intel_opregion_asle_intr(dev);
4207
4208 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4209 gmbus_irq_handler(dev);
4210
4211 /* With MSI, interrupts are only generated when iir
4212 * transitions from zero to nonzero. If another bit got
4213 * set while we were handling the existing iir bits, then
4214 * we would never get another interrupt.
4215 *
4216 * This is fine on non-MSI as well, as if we hit this path
4217 * we avoid exiting the interrupt handler only to generate
4218 * another one.
4219 *
4220 * Note that for MSI this could cause a stray interrupt report
4221 * if an interrupt landed in the time between writing IIR and
4222 * the posting read. This should be rare enough to never
4223 * trigger the 99% of 100,000 interrupts test for disabling
4224 * stray interrupts.
4225 */
4226 iir = new_iir;
4227 }
4228
4229 i915_update_dri1_breadcrumb(dev);
4230
4231 return ret;
4232 }
4233
4234 static void i965_irq_uninstall(struct drm_device * dev)
4235 {
4236 struct drm_i915_private *dev_priv = dev->dev_private;
4237 int pipe;
4238
4239 if (!dev_priv)
4240 return;
4241
4242 I915_WRITE(PORT_HOTPLUG_EN, 0);
4243 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4244
4245 I915_WRITE(HWSTAM, 0xffffffff);
4246 for_each_pipe(dev_priv, pipe)
4247 I915_WRITE(PIPESTAT(pipe), 0);
4248 I915_WRITE(IMR, 0xffffffff);
4249 I915_WRITE(IER, 0x0);
4250
4251 for_each_pipe(dev_priv, pipe)
4252 I915_WRITE(PIPESTAT(pipe),
4253 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4254 I915_WRITE(IIR, I915_READ(IIR));
4255 }
4256
4257 static void intel_hpd_irq_reenable_work(struct work_struct *work)
4258 {
4259 struct drm_i915_private *dev_priv =
4260 container_of(work, typeof(*dev_priv),
4261 hotplug_reenable_work.work);
4262 struct drm_device *dev = dev_priv->dev;
4263 struct drm_mode_config *mode_config = &dev->mode_config;
4264 int i;
4265
4266 intel_runtime_pm_get(dev_priv);
4267
4268 spin_lock_irq(&dev_priv->irq_lock);
4269 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
4270 struct drm_connector *connector;
4271
4272 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
4273 continue;
4274
4275 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4276
4277 list_for_each_entry(connector, &mode_config->connector_list, head) {
4278 struct intel_connector *intel_connector = to_intel_connector(connector);
4279
4280 if (intel_connector->encoder->hpd_pin == i) {
4281 if (connector->polled != intel_connector->polled)
4282 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
4283 connector->name);
4284 connector->polled = intel_connector->polled;
4285 if (!connector->polled)
4286 connector->polled = DRM_CONNECTOR_POLL_HPD;
4287 }
4288 }
4289 }
4290 if (dev_priv->display.hpd_irq_setup)
4291 dev_priv->display.hpd_irq_setup(dev);
4292 spin_unlock_irq(&dev_priv->irq_lock);
4293
4294 intel_runtime_pm_put(dev_priv);
4295 }
4296
4297 /**
4298 * intel_irq_init - initializes irq support
4299 * @dev_priv: i915 device instance
4300 *
4301 * This function initializes all the irq support including work items, timers
4302 * and all the vtables. It does not setup the interrupt itself though.
4303 */
4304 void intel_irq_init(struct drm_i915_private *dev_priv)
4305 {
4306 struct drm_device *dev = dev_priv->dev;
4307
4308 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
4309 INIT_WORK(&dev_priv->dig_port_work, i915_digport_work_func);
4310 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
4311 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4312 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4313
4314 /* Let's track the enabled rps events */
4315 if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
4316 /* WaGsvRC0ResidencyMethod:vlv */
4317 dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
4318 else
4319 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4320
4321 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
4322 i915_hangcheck_elapsed,
4323 (unsigned long) dev);
4324 INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work,
4325 intel_hpd_irq_reenable_work);
4326
4327 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4328
4329 if (IS_GEN2(dev_priv)) {
4330 dev->max_vblank_count = 0;
4331 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4332 } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4333 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4334 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
4335 } else {
4336 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4337 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4338 }
4339
4340 /*
4341 * Opt out of the vblank disable timer on everything except gen2.
4342 * Gen2 doesn't have a hardware frame counter and so depends on
4343 * vblank interrupts to produce sane vblank seuquence numbers.
4344 */
4345 if (!IS_GEN2(dev_priv))
4346 dev->vblank_disable_immediate = true;
4347
4348 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
4349 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4350 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4351 }
4352
4353 if (IS_CHERRYVIEW(dev_priv)) {
4354 dev->driver->irq_handler = cherryview_irq_handler;
4355 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4356 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4357 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4358 dev->driver->enable_vblank = valleyview_enable_vblank;
4359 dev->driver->disable_vblank = valleyview_disable_vblank;
4360 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4361 } else if (IS_VALLEYVIEW(dev_priv)) {
4362 dev->driver->irq_handler = valleyview_irq_handler;
4363 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4364 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4365 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4366 dev->driver->enable_vblank = valleyview_enable_vblank;
4367 dev->driver->disable_vblank = valleyview_disable_vblank;
4368 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4369 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
4370 dev->driver->irq_handler = gen8_irq_handler;
4371 dev->driver->irq_preinstall = gen8_irq_reset;
4372 dev->driver->irq_postinstall = gen8_irq_postinstall;
4373 dev->driver->irq_uninstall = gen8_irq_uninstall;
4374 dev->driver->enable_vblank = gen8_enable_vblank;
4375 dev->driver->disable_vblank = gen8_disable_vblank;
4376 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4377 } else if (HAS_PCH_SPLIT(dev)) {
4378 dev->driver->irq_handler = ironlake_irq_handler;
4379 dev->driver->irq_preinstall = ironlake_irq_reset;
4380 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4381 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4382 dev->driver->enable_vblank = ironlake_enable_vblank;
4383 dev->driver->disable_vblank = ironlake_disable_vblank;
4384 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4385 } else {
4386 if (INTEL_INFO(dev_priv)->gen == 2) {
4387 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4388 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4389 dev->driver->irq_handler = i8xx_irq_handler;
4390 dev->driver->irq_uninstall = i8xx_irq_uninstall;
4391 } else if (INTEL_INFO(dev_priv)->gen == 3) {
4392 dev->driver->irq_preinstall = i915_irq_preinstall;
4393 dev->driver->irq_postinstall = i915_irq_postinstall;
4394 dev->driver->irq_uninstall = i915_irq_uninstall;
4395 dev->driver->irq_handler = i915_irq_handler;
4396 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4397 } else {
4398 dev->driver->irq_preinstall = i965_irq_preinstall;
4399 dev->driver->irq_postinstall = i965_irq_postinstall;
4400 dev->driver->irq_uninstall = i965_irq_uninstall;
4401 dev->driver->irq_handler = i965_irq_handler;
4402 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4403 }
4404 dev->driver->enable_vblank = i915_enable_vblank;
4405 dev->driver->disable_vblank = i915_disable_vblank;
4406 }
4407 }
4408
4409 /**
4410 * intel_hpd_init - initializes and enables hpd support
4411 * @dev_priv: i915 device instance
4412 *
4413 * This function enables the hotplug support. It requires that interrupts have
4414 * already been enabled with intel_irq_init_hw(). From this point on hotplug and
4415 * poll request can run concurrently to other code, so locking rules must be
4416 * obeyed.
4417 *
4418 * This is a separate step from interrupt enabling to simplify the locking rules
4419 * in the driver load and resume code.
4420 */
4421 void intel_hpd_init(struct drm_i915_private *dev_priv)
4422 {
4423 struct drm_device *dev = dev_priv->dev;
4424 struct drm_mode_config *mode_config = &dev->mode_config;
4425 struct drm_connector *connector;
4426 int i;
4427
4428 for (i = 1; i < HPD_NUM_PINS; i++) {
4429 dev_priv->hpd_stats[i].hpd_cnt = 0;
4430 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4431 }
4432 list_for_each_entry(connector, &mode_config->connector_list, head) {
4433 struct intel_connector *intel_connector = to_intel_connector(connector);
4434 connector->polled = intel_connector->polled;
4435 if (connector->encoder && !connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
4436 connector->polled = DRM_CONNECTOR_POLL_HPD;
4437 if (intel_connector->mst_port)
4438 connector->polled = DRM_CONNECTOR_POLL_HPD;
4439 }
4440
4441 /* Interrupt setup is already guaranteed to be single-threaded, this is
4442 * just to make the assert_spin_locked checks happy. */
4443 spin_lock_irq(&dev_priv->irq_lock);
4444 if (dev_priv->display.hpd_irq_setup)
4445 dev_priv->display.hpd_irq_setup(dev);
4446 spin_unlock_irq(&dev_priv->irq_lock);
4447 }
4448
4449 /**
4450 * intel_irq_install - enables the hardware interrupt
4451 * @dev_priv: i915 device instance
4452 *
4453 * This function enables the hardware interrupt handling, but leaves the hotplug
4454 * handling still disabled. It is called after intel_irq_init().
4455 *
4456 * In the driver load and resume code we need working interrupts in a few places
4457 * but don't want to deal with the hassle of concurrent probe and hotplug
4458 * workers. Hence the split into this two-stage approach.
4459 */
4460 int intel_irq_install(struct drm_i915_private *dev_priv)
4461 {
4462 /*
4463 * We enable some interrupt sources in our postinstall hooks, so mark
4464 * interrupts as enabled _before_ actually enabling them to avoid
4465 * special cases in our ordering checks.
4466 */
4467 dev_priv->pm.irqs_enabled = true;
4468
4469 return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
4470 }
4471
4472 /**
4473 * intel_irq_uninstall - finilizes all irq handling
4474 * @dev_priv: i915 device instance
4475 *
4476 * This stops interrupt and hotplug handling and unregisters and frees all
4477 * resources acquired in the init functions.
4478 */
4479 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4480 {
4481 drm_irq_uninstall(dev_priv->dev);
4482 intel_hpd_cancel_work(dev_priv);
4483 dev_priv->pm.irqs_enabled = false;
4484 }
4485
4486 /**
4487 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4488 * @dev_priv: i915 device instance
4489 *
4490 * This function is used to disable interrupts at runtime, both in the runtime
4491 * pm and the system suspend/resume code.
4492 */
4493 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4494 {
4495 dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
4496 dev_priv->pm.irqs_enabled = false;
4497 }
4498
4499 /**
4500 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4501 * @dev_priv: i915 device instance
4502 *
4503 * This function is used to enable interrupts at runtime, both in the runtime
4504 * pm and the system suspend/resume code.
4505 */
4506 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4507 {
4508 dev_priv->pm.irqs_enabled = true;
4509 dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
4510 dev_priv->dev->driver->irq_postinstall(dev_priv->dev);
4511 }
Linux kernel - Deliverables
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