1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
35 #include <drm/i915_drm.h>
37 #include "i915_trace.h"
38 #include "intel_drv.h"
41 * DOC: interrupt handling
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
48 static const u32 hpd_ilk
[HPD_NUM_PINS
] = {
49 [HPD_PORT_A
] = DE_DP_A_HOTPLUG
,
52 static const u32 hpd_ivb
[HPD_NUM_PINS
] = {
53 [HPD_PORT_A
] = DE_DP_A_HOTPLUG_IVB
,
56 static const u32 hpd_bdw
[HPD_NUM_PINS
] = {
57 [HPD_PORT_A
] = GEN8_PORT_DP_A_HOTPLUG
,
60 static const u32 hpd_ibx
[HPD_NUM_PINS
] = {
61 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
62 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
63 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
64 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
65 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
68 static const u32 hpd_cpt
[HPD_NUM_PINS
] = {
69 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
70 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG_CPT
,
71 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
72 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
73 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
76 static const u32 hpd_spt
[HPD_NUM_PINS
] = {
77 [HPD_PORT_A
] = SDE_PORTA_HOTPLUG_SPT
,
78 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
79 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
80 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
,
81 [HPD_PORT_E
] = SDE_PORTE_HOTPLUG_SPT
84 static const u32 hpd_mask_i915
[HPD_NUM_PINS
] = {
85 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
86 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
87 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
88 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
89 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
90 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
93 static const u32 hpd_status_g4x
[HPD_NUM_PINS
] = {
94 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
95 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
96 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
97 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
98 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
99 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
102 static const u32 hpd_status_i915
[HPD_NUM_PINS
] = {
103 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
104 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
105 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
106 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
107 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
108 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
112 static const u32 hpd_bxt
[HPD_NUM_PINS
] = {
113 [HPD_PORT_A
] = BXT_DE_PORT_HP_DDIA
,
114 [HPD_PORT_B
] = BXT_DE_PORT_HP_DDIB
,
115 [HPD_PORT_C
] = BXT_DE_PORT_HP_DDIC
118 /* IIR can theoretically queue up two events. Be paranoid. */
119 #define GEN8_IRQ_RESET_NDX(type, which) do { \
120 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
121 POSTING_READ(GEN8_##type##_IMR(which)); \
122 I915_WRITE(GEN8_##type##_IER(which), 0); \
123 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
124 POSTING_READ(GEN8_##type##_IIR(which)); \
125 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
126 POSTING_READ(GEN8_##type##_IIR(which)); \
129 #define GEN5_IRQ_RESET(type) do { \
130 I915_WRITE(type##IMR, 0xffffffff); \
131 POSTING_READ(type##IMR); \
132 I915_WRITE(type##IER, 0); \
133 I915_WRITE(type##IIR, 0xffffffff); \
134 POSTING_READ(type##IIR); \
135 I915_WRITE(type##IIR, 0xffffffff); \
136 POSTING_READ(type##IIR); \
140 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
142 static void gen5_assert_iir_is_zero(struct drm_i915_private
*dev_priv
,
145 u32 val
= I915_READ(reg
);
150 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
151 i915_mmio_reg_offset(reg
), val
);
152 I915_WRITE(reg
, 0xffffffff);
154 I915_WRITE(reg
, 0xffffffff);
158 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
159 gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
160 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
161 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
162 POSTING_READ(GEN8_##type##_IMR(which)); \
165 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
166 gen5_assert_iir_is_zero(dev_priv, type##IIR); \
167 I915_WRITE(type##IER, (ier_val)); \
168 I915_WRITE(type##IMR, (imr_val)); \
169 POSTING_READ(type##IMR); \
172 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
);
174 /* For display hotplug interrupt */
176 i915_hotplug_interrupt_update_locked(struct drm_i915_private
*dev_priv
,
182 assert_spin_locked(&dev_priv
->irq_lock
);
183 WARN_ON(bits
& ~mask
);
185 val
= I915_READ(PORT_HOTPLUG_EN
);
188 I915_WRITE(PORT_HOTPLUG_EN
, val
);
192 * i915_hotplug_interrupt_update - update hotplug interrupt enable
193 * @dev_priv: driver private
194 * @mask: bits to update
195 * @bits: bits to enable
196 * NOTE: the HPD enable bits are modified both inside and outside
197 * of an interrupt context. To avoid that read-modify-write cycles
198 * interfer, these bits are protected by a spinlock. Since this
199 * function is usually not called from a context where the lock is
200 * held already, this function acquires the lock itself. A non-locking
201 * version is also available.
203 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
207 spin_lock_irq(&dev_priv
->irq_lock
);
208 i915_hotplug_interrupt_update_locked(dev_priv
, mask
, bits
);
209 spin_unlock_irq(&dev_priv
->irq_lock
);
213 * ilk_update_display_irq - update DEIMR
214 * @dev_priv: driver private
215 * @interrupt_mask: mask of interrupt bits to update
216 * @enabled_irq_mask: mask of interrupt bits to enable
218 void ilk_update_display_irq(struct drm_i915_private
*dev_priv
,
219 uint32_t interrupt_mask
,
220 uint32_t enabled_irq_mask
)
224 assert_spin_locked(&dev_priv
->irq_lock
);
226 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
228 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
231 new_val
= dev_priv
->irq_mask
;
232 new_val
&= ~interrupt_mask
;
233 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
235 if (new_val
!= dev_priv
->irq_mask
) {
236 dev_priv
->irq_mask
= new_val
;
237 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
243 * ilk_update_gt_irq - update GTIMR
244 * @dev_priv: driver private
245 * @interrupt_mask: mask of interrupt bits to update
246 * @enabled_irq_mask: mask of interrupt bits to enable
248 static void ilk_update_gt_irq(struct drm_i915_private
*dev_priv
,
249 uint32_t interrupt_mask
,
250 uint32_t enabled_irq_mask
)
252 assert_spin_locked(&dev_priv
->irq_lock
);
254 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
256 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
259 dev_priv
->gt_irq_mask
&= ~interrupt_mask
;
260 dev_priv
->gt_irq_mask
|= (~enabled_irq_mask
& interrupt_mask
);
261 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
265 void gen5_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
267 ilk_update_gt_irq(dev_priv
, mask
, mask
);
270 void gen5_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
272 ilk_update_gt_irq(dev_priv
, mask
, 0);
275 static i915_reg_t
gen6_pm_iir(struct drm_i915_private
*dev_priv
)
277 return INTEL_INFO(dev_priv
)->gen
>= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR
;
280 static i915_reg_t
gen6_pm_imr(struct drm_i915_private
*dev_priv
)
282 return INTEL_INFO(dev_priv
)->gen
>= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR
;
285 static i915_reg_t
gen6_pm_ier(struct drm_i915_private
*dev_priv
)
287 return INTEL_INFO(dev_priv
)->gen
>= 8 ? GEN8_GT_IER(2) : GEN6_PMIER
;
291 * snb_update_pm_irq - update GEN6_PMIMR
292 * @dev_priv: driver private
293 * @interrupt_mask: mask of interrupt bits to update
294 * @enabled_irq_mask: mask of interrupt bits to enable
296 static void snb_update_pm_irq(struct drm_i915_private
*dev_priv
,
297 uint32_t interrupt_mask
,
298 uint32_t enabled_irq_mask
)
302 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
304 assert_spin_locked(&dev_priv
->irq_lock
);
306 new_val
= dev_priv
->pm_irq_mask
;
307 new_val
&= ~interrupt_mask
;
308 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
310 if (new_val
!= dev_priv
->pm_irq_mask
) {
311 dev_priv
->pm_irq_mask
= new_val
;
312 I915_WRITE(gen6_pm_imr(dev_priv
), dev_priv
->pm_irq_mask
);
313 POSTING_READ(gen6_pm_imr(dev_priv
));
317 void gen6_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
319 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
322 snb_update_pm_irq(dev_priv
, mask
, mask
);
325 static void __gen6_disable_pm_irq(struct drm_i915_private
*dev_priv
,
328 snb_update_pm_irq(dev_priv
, mask
, 0);
331 void gen6_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
333 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
336 __gen6_disable_pm_irq(dev_priv
, mask
);
339 void gen6_reset_rps_interrupts(struct drm_device
*dev
)
341 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
342 i915_reg_t reg
= gen6_pm_iir(dev_priv
);
344 spin_lock_irq(&dev_priv
->irq_lock
);
345 I915_WRITE(reg
, dev_priv
->pm_rps_events
);
346 I915_WRITE(reg
, dev_priv
->pm_rps_events
);
348 dev_priv
->rps
.pm_iir
= 0;
349 spin_unlock_irq(&dev_priv
->irq_lock
);
352 void gen6_enable_rps_interrupts(struct drm_device
*dev
)
354 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
356 spin_lock_irq(&dev_priv
->irq_lock
);
358 WARN_ON(dev_priv
->rps
.pm_iir
);
359 WARN_ON(I915_READ(gen6_pm_iir(dev_priv
)) & dev_priv
->pm_rps_events
);
360 dev_priv
->rps
.interrupts_enabled
= true;
361 I915_WRITE(gen6_pm_ier(dev_priv
), I915_READ(gen6_pm_ier(dev_priv
)) |
362 dev_priv
->pm_rps_events
);
363 gen6_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
365 spin_unlock_irq(&dev_priv
->irq_lock
);
368 u32
gen6_sanitize_rps_pm_mask(struct drm_i915_private
*dev_priv
, u32 mask
)
371 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
372 * if GEN6_PM_UP_EI_EXPIRED is masked.
374 * TODO: verify if this can be reproduced on VLV,CHV.
376 if (INTEL_INFO(dev_priv
)->gen
<= 7 && !IS_HASWELL(dev_priv
))
377 mask
&= ~GEN6_PM_RP_UP_EI_EXPIRED
;
379 if (INTEL_INFO(dev_priv
)->gen
>= 8)
380 mask
&= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP
;
385 void gen6_disable_rps_interrupts(struct drm_device
*dev
)
387 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
389 spin_lock_irq(&dev_priv
->irq_lock
);
390 dev_priv
->rps
.interrupts_enabled
= false;
391 spin_unlock_irq(&dev_priv
->irq_lock
);
393 cancel_work_sync(&dev_priv
->rps
.work
);
395 spin_lock_irq(&dev_priv
->irq_lock
);
397 I915_WRITE(GEN6_PMINTRMSK
, gen6_sanitize_rps_pm_mask(dev_priv
, ~0));
399 __gen6_disable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
400 I915_WRITE(gen6_pm_ier(dev_priv
), I915_READ(gen6_pm_ier(dev_priv
)) &
401 ~dev_priv
->pm_rps_events
);
403 spin_unlock_irq(&dev_priv
->irq_lock
);
405 synchronize_irq(dev
->irq
);
409 * bdw_update_port_irq - update DE port interrupt
410 * @dev_priv: driver private
411 * @interrupt_mask: mask of interrupt bits to update
412 * @enabled_irq_mask: mask of interrupt bits to enable
414 static void bdw_update_port_irq(struct drm_i915_private
*dev_priv
,
415 uint32_t interrupt_mask
,
416 uint32_t enabled_irq_mask
)
421 assert_spin_locked(&dev_priv
->irq_lock
);
423 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
425 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
428 old_val
= I915_READ(GEN8_DE_PORT_IMR
);
431 new_val
&= ~interrupt_mask
;
432 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
434 if (new_val
!= old_val
) {
435 I915_WRITE(GEN8_DE_PORT_IMR
, new_val
);
436 POSTING_READ(GEN8_DE_PORT_IMR
);
441 * bdw_update_pipe_irq - update DE pipe interrupt
442 * @dev_priv: driver private
443 * @pipe: pipe whose interrupt to update
444 * @interrupt_mask: mask of interrupt bits to update
445 * @enabled_irq_mask: mask of interrupt bits to enable
447 void bdw_update_pipe_irq(struct drm_i915_private
*dev_priv
,
449 uint32_t interrupt_mask
,
450 uint32_t enabled_irq_mask
)
454 assert_spin_locked(&dev_priv
->irq_lock
);
456 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
458 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
461 new_val
= dev_priv
->de_irq_mask
[pipe
];
462 new_val
&= ~interrupt_mask
;
463 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
465 if (new_val
!= dev_priv
->de_irq_mask
[pipe
]) {
466 dev_priv
->de_irq_mask
[pipe
] = new_val
;
467 I915_WRITE(GEN8_DE_PIPE_IMR(pipe
), dev_priv
->de_irq_mask
[pipe
]);
468 POSTING_READ(GEN8_DE_PIPE_IMR(pipe
));
473 * ibx_display_interrupt_update - update SDEIMR
474 * @dev_priv: driver private
475 * @interrupt_mask: mask of interrupt bits to update
476 * @enabled_irq_mask: mask of interrupt bits to enable
478 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
479 uint32_t interrupt_mask
,
480 uint32_t enabled_irq_mask
)
482 uint32_t sdeimr
= I915_READ(SDEIMR
);
483 sdeimr
&= ~interrupt_mask
;
484 sdeimr
|= (~enabled_irq_mask
& interrupt_mask
);
486 WARN_ON(enabled_irq_mask
& ~interrupt_mask
);
488 assert_spin_locked(&dev_priv
->irq_lock
);
490 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
493 I915_WRITE(SDEIMR
, sdeimr
);
494 POSTING_READ(SDEIMR
);
498 __i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
499 u32 enable_mask
, u32 status_mask
)
501 i915_reg_t reg
= PIPESTAT(pipe
);
502 u32 pipestat
= I915_READ(reg
) & PIPESTAT_INT_ENABLE_MASK
;
504 assert_spin_locked(&dev_priv
->irq_lock
);
505 WARN_ON(!intel_irqs_enabled(dev_priv
));
507 if (WARN_ONCE(enable_mask
& ~PIPESTAT_INT_ENABLE_MASK
||
508 status_mask
& ~PIPESTAT_INT_STATUS_MASK
,
509 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
510 pipe_name(pipe
), enable_mask
, status_mask
))
513 if ((pipestat
& enable_mask
) == enable_mask
)
516 dev_priv
->pipestat_irq_mask
[pipe
] |= status_mask
;
518 /* Enable the interrupt, clear any pending status */
519 pipestat
|= enable_mask
| status_mask
;
520 I915_WRITE(reg
, pipestat
);
525 __i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
526 u32 enable_mask
, u32 status_mask
)
528 i915_reg_t reg
= PIPESTAT(pipe
);
529 u32 pipestat
= I915_READ(reg
) & PIPESTAT_INT_ENABLE_MASK
;
531 assert_spin_locked(&dev_priv
->irq_lock
);
532 WARN_ON(!intel_irqs_enabled(dev_priv
));
534 if (WARN_ONCE(enable_mask
& ~PIPESTAT_INT_ENABLE_MASK
||
535 status_mask
& ~PIPESTAT_INT_STATUS_MASK
,
536 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
537 pipe_name(pipe
), enable_mask
, status_mask
))
540 if ((pipestat
& enable_mask
) == 0)
543 dev_priv
->pipestat_irq_mask
[pipe
] &= ~status_mask
;
545 pipestat
&= ~enable_mask
;
546 I915_WRITE(reg
, pipestat
);
550 static u32
vlv_get_pipestat_enable_mask(struct drm_device
*dev
, u32 status_mask
)
552 u32 enable_mask
= status_mask
<< 16;
555 * On pipe A we don't support the PSR interrupt yet,
556 * on pipe B and C the same bit MBZ.
558 if (WARN_ON_ONCE(status_mask
& PIPE_A_PSR_STATUS_VLV
))
561 * On pipe B and C we don't support the PSR interrupt yet, on pipe
562 * A the same bit is for perf counters which we don't use either.
564 if (WARN_ON_ONCE(status_mask
& PIPE_B_PSR_STATUS_VLV
))
567 enable_mask
&= ~(PIPE_FIFO_UNDERRUN_STATUS
|
568 SPRITE0_FLIP_DONE_INT_EN_VLV
|
569 SPRITE1_FLIP_DONE_INT_EN_VLV
);
570 if (status_mask
& SPRITE0_FLIP_DONE_INT_STATUS_VLV
)
571 enable_mask
|= SPRITE0_FLIP_DONE_INT_EN_VLV
;
572 if (status_mask
& SPRITE1_FLIP_DONE_INT_STATUS_VLV
)
573 enable_mask
|= SPRITE1_FLIP_DONE_INT_EN_VLV
;
579 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
584 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
585 enable_mask
= vlv_get_pipestat_enable_mask(dev_priv
->dev
,
588 enable_mask
= status_mask
<< 16;
589 __i915_enable_pipestat(dev_priv
, pipe
, enable_mask
, status_mask
);
593 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
598 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
599 enable_mask
= vlv_get_pipestat_enable_mask(dev_priv
->dev
,
602 enable_mask
= status_mask
<< 16;
603 __i915_disable_pipestat(dev_priv
, pipe
, enable_mask
, status_mask
);
607 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
610 static void i915_enable_asle_pipestat(struct drm_device
*dev
)
612 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
614 if (!dev_priv
->opregion
.asle
|| !IS_MOBILE(dev
))
617 spin_lock_irq(&dev_priv
->irq_lock
);
619 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_LEGACY_BLC_EVENT_STATUS
);
620 if (INTEL_INFO(dev
)->gen
>= 4)
621 i915_enable_pipestat(dev_priv
, PIPE_A
,
622 PIPE_LEGACY_BLC_EVENT_STATUS
);
624 spin_unlock_irq(&dev_priv
->irq_lock
);
628 * This timing diagram depicts the video signal in and
629 * around the vertical blanking period.
631 * Assumptions about the fictitious mode used in this example:
633 * vsync_start = vblank_start + 1
634 * vsync_end = vblank_start + 2
635 * vtotal = vblank_start + 3
638 * latch double buffered registers
639 * increment frame counter (ctg+)
640 * generate start of vblank interrupt (gen4+)
643 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
644 * | may be shifted forward 1-3 extra lines via PIPECONF
646 * | | start of vsync:
647 * | | generate vsync interrupt
649 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
650 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
651 * ----va---> <-----------------vb--------------------> <--------va-------------
652 * | | <----vs-----> |
653 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
654 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
655 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
657 * last visible pixel first visible pixel
658 * | increment frame counter (gen3/4)
659 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
661 * x = horizontal active
662 * _ = horizontal blanking
663 * hs = horizontal sync
664 * va = vertical active
665 * vb = vertical blanking
667 * vbs = vblank_start (number)
670 * - most events happen at the start of horizontal sync
671 * - frame start happens at the start of horizontal blank, 1-4 lines
672 * (depending on PIPECONF settings) after the start of vblank
673 * - gen3/4 pixel and frame counter are synchronized with the start
674 * of horizontal active on the first line of vertical active
677 static u32
i8xx_get_vblank_counter(struct drm_device
*dev
, unsigned int pipe
)
679 /* Gen2 doesn't have a hardware frame counter */
683 /* Called from drm generic code, passed a 'crtc', which
684 * we use as a pipe index
686 static u32
i915_get_vblank_counter(struct drm_device
*dev
, unsigned int pipe
)
688 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
689 i915_reg_t high_frame
, low_frame
;
690 u32 high1
, high2
, low
, pixel
, vbl_start
, hsync_start
, htotal
;
691 struct intel_crtc
*intel_crtc
=
692 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
693 const struct drm_display_mode
*mode
= &intel_crtc
->base
.hwmode
;
695 htotal
= mode
->crtc_htotal
;
696 hsync_start
= mode
->crtc_hsync_start
;
697 vbl_start
= mode
->crtc_vblank_start
;
698 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
699 vbl_start
= DIV_ROUND_UP(vbl_start
, 2);
701 /* Convert to pixel count */
704 /* Start of vblank event occurs at start of hsync */
705 vbl_start
-= htotal
- hsync_start
;
707 high_frame
= PIPEFRAME(pipe
);
708 low_frame
= PIPEFRAMEPIXEL(pipe
);
711 * High & low register fields aren't synchronized, so make sure
712 * we get a low value that's stable across two reads of the high
716 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
717 low
= I915_READ(low_frame
);
718 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
719 } while (high1
!= high2
);
721 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
722 pixel
= low
& PIPE_PIXEL_MASK
;
723 low
>>= PIPE_FRAME_LOW_SHIFT
;
726 * The frame counter increments at beginning of active.
727 * Cook up a vblank counter by also checking the pixel
728 * counter against vblank start.
730 return (((high1
<< 8) | low
) + (pixel
>= vbl_start
)) & 0xffffff;
733 static u32
g4x_get_vblank_counter(struct drm_device
*dev
, unsigned int pipe
)
735 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
737 return I915_READ(PIPE_FRMCOUNT_G4X(pipe
));
740 /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
741 static int __intel_get_crtc_scanline(struct intel_crtc
*crtc
)
743 struct drm_device
*dev
= crtc
->base
.dev
;
744 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
745 const struct drm_display_mode
*mode
= &crtc
->base
.hwmode
;
746 enum pipe pipe
= crtc
->pipe
;
747 int position
, vtotal
;
749 vtotal
= mode
->crtc_vtotal
;
750 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
754 position
= I915_READ_FW(PIPEDSL(pipe
)) & DSL_LINEMASK_GEN2
;
756 position
= I915_READ_FW(PIPEDSL(pipe
)) & DSL_LINEMASK_GEN3
;
759 * On HSW, the DSL reg (0x70000) appears to return 0 if we
760 * read it just before the start of vblank. So try it again
761 * so we don't accidentally end up spanning a vblank frame
762 * increment, causing the pipe_update_end() code to squak at us.
764 * The nature of this problem means we can't simply check the ISR
765 * bit and return the vblank start value; nor can we use the scanline
766 * debug register in the transcoder as it appears to have the same
767 * problem. We may need to extend this to include other platforms,
768 * but so far testing only shows the problem on HSW.
770 if (HAS_DDI(dev
) && !position
) {
773 for (i
= 0; i
< 100; i
++) {
775 temp
= __raw_i915_read32(dev_priv
, PIPEDSL(pipe
)) &
777 if (temp
!= position
) {
785 * See update_scanline_offset() for the details on the
786 * scanline_offset adjustment.
788 return (position
+ crtc
->scanline_offset
) % vtotal
;
791 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, unsigned int pipe
,
792 unsigned int flags
, int *vpos
, int *hpos
,
793 ktime_t
*stime
, ktime_t
*etime
,
794 const struct drm_display_mode
*mode
)
796 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
797 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
798 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
800 int vbl_start
, vbl_end
, hsync_start
, htotal
, vtotal
;
803 unsigned long irqflags
;
805 if (WARN_ON(!mode
->crtc_clock
)) {
806 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
807 "pipe %c\n", pipe_name(pipe
));
811 htotal
= mode
->crtc_htotal
;
812 hsync_start
= mode
->crtc_hsync_start
;
813 vtotal
= mode
->crtc_vtotal
;
814 vbl_start
= mode
->crtc_vblank_start
;
815 vbl_end
= mode
->crtc_vblank_end
;
817 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
818 vbl_start
= DIV_ROUND_UP(vbl_start
, 2);
823 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
826 * Lock uncore.lock, as we will do multiple timing critical raw
827 * register reads, potentially with preemption disabled, so the
828 * following code must not block on uncore.lock.
830 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
832 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
834 /* Get optional system timestamp before query. */
836 *stime
= ktime_get();
838 if (IS_GEN2(dev
) || IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
839 /* No obvious pixelcount register. Only query vertical
840 * scanout position from Display scan line register.
842 position
= __intel_get_crtc_scanline(intel_crtc
);
844 /* Have access to pixelcount since start of frame.
845 * We can split this into vertical and horizontal
848 position
= (I915_READ_FW(PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
850 /* convert to pixel counts */
856 * In interlaced modes, the pixel counter counts all pixels,
857 * so one field will have htotal more pixels. In order to avoid
858 * the reported position from jumping backwards when the pixel
859 * counter is beyond the length of the shorter field, just
860 * clamp the position the length of the shorter field. This
861 * matches how the scanline counter based position works since
862 * the scanline counter doesn't count the two half lines.
864 if (position
>= vtotal
)
865 position
= vtotal
- 1;
868 * Start of vblank interrupt is triggered at start of hsync,
869 * just prior to the first active line of vblank. However we
870 * consider lines to start at the leading edge of horizontal
871 * active. So, should we get here before we've crossed into
872 * the horizontal active of the first line in vblank, we would
873 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
874 * always add htotal-hsync_start to the current pixel position.
876 position
= (position
+ htotal
- hsync_start
) % vtotal
;
879 /* Get optional system timestamp after query. */
881 *etime
= ktime_get();
883 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
885 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
887 in_vbl
= position
>= vbl_start
&& position
< vbl_end
;
890 * While in vblank, position will be negative
891 * counting up towards 0 at vbl_end. And outside
892 * vblank, position will be positive counting
895 if (position
>= vbl_start
)
898 position
+= vtotal
- vbl_end
;
900 if (IS_GEN2(dev
) || IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
904 *vpos
= position
/ htotal
;
905 *hpos
= position
- (*vpos
* htotal
);
910 ret
|= DRM_SCANOUTPOS_IN_VBLANK
;
915 int intel_get_crtc_scanline(struct intel_crtc
*crtc
)
917 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
918 unsigned long irqflags
;
921 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
922 position
= __intel_get_crtc_scanline(crtc
);
923 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
928 static int i915_get_vblank_timestamp(struct drm_device
*dev
, unsigned int pipe
,
930 struct timeval
*vblank_time
,
933 struct drm_crtc
*crtc
;
935 if (pipe
>= INTEL_INFO(dev
)->num_pipes
) {
936 DRM_ERROR("Invalid crtc %u\n", pipe
);
940 /* Get drm_crtc to timestamp: */
941 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
943 DRM_ERROR("Invalid crtc %u\n", pipe
);
947 if (!crtc
->hwmode
.crtc_clock
) {
948 DRM_DEBUG_KMS("crtc %u is disabled\n", pipe
);
952 /* Helper routine in DRM core does all the work: */
953 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
958 static void ironlake_rps_change_irq_handler(struct drm_device
*dev
)
960 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
961 u32 busy_up
, busy_down
, max_avg
, min_avg
;
964 spin_lock(&mchdev_lock
);
966 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
968 new_delay
= dev_priv
->ips
.cur_delay
;
970 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
971 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
972 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
973 max_avg
= I915_READ(RCBMAXAVG
);
974 min_avg
= I915_READ(RCBMINAVG
);
976 /* Handle RCS change request from hw */
977 if (busy_up
> max_avg
) {
978 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
979 new_delay
= dev_priv
->ips
.cur_delay
- 1;
980 if (new_delay
< dev_priv
->ips
.max_delay
)
981 new_delay
= dev_priv
->ips
.max_delay
;
982 } else if (busy_down
< min_avg
) {
983 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
984 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
985 if (new_delay
> dev_priv
->ips
.min_delay
)
986 new_delay
= dev_priv
->ips
.min_delay
;
989 if (ironlake_set_drps(dev
, new_delay
))
990 dev_priv
->ips
.cur_delay
= new_delay
;
992 spin_unlock(&mchdev_lock
);
997 static void notify_ring(struct intel_engine_cs
*engine
)
999 if (!intel_engine_initialized(engine
))
1002 trace_i915_gem_request_notify(engine
);
1003 engine
->user_interrupts
++;
1005 wake_up_all(&engine
->irq_queue
);
1008 static void vlv_c0_read(struct drm_i915_private
*dev_priv
,
1009 struct intel_rps_ei
*ei
)
1011 ei
->cz_clock
= vlv_punit_read(dev_priv
, PUNIT_REG_CZ_TIMESTAMP
);
1012 ei
->render_c0
= I915_READ(VLV_RENDER_C0_COUNT
);
1013 ei
->media_c0
= I915_READ(VLV_MEDIA_C0_COUNT
);
1016 static bool vlv_c0_above(struct drm_i915_private
*dev_priv
,
1017 const struct intel_rps_ei
*old
,
1018 const struct intel_rps_ei
*now
,
1022 unsigned int mul
= 100;
1024 if (old
->cz_clock
== 0)
1027 if (I915_READ(VLV_COUNTER_CONTROL
) & VLV_COUNT_RANGE_HIGH
)
1030 time
= now
->cz_clock
- old
->cz_clock
;
1031 time
*= threshold
* dev_priv
->czclk_freq
;
1033 /* Workload can be split between render + media, e.g. SwapBuffers
1034 * being blitted in X after being rendered in mesa. To account for
1035 * this we need to combine both engines into our activity counter.
1037 c0
= now
->render_c0
- old
->render_c0
;
1038 c0
+= now
->media_c0
- old
->media_c0
;
1039 c0
*= mul
* VLV_CZ_CLOCK_TO_MILLI_SEC
;
1044 void gen6_rps_reset_ei(struct drm_i915_private
*dev_priv
)
1046 vlv_c0_read(dev_priv
, &dev_priv
->rps
.down_ei
);
1047 dev_priv
->rps
.up_ei
= dev_priv
->rps
.down_ei
;
1050 static u32
vlv_wa_c0_ei(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1052 struct intel_rps_ei now
;
1055 if ((pm_iir
& (GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_UP_EI_EXPIRED
)) == 0)
1058 vlv_c0_read(dev_priv
, &now
);
1059 if (now
.cz_clock
== 0)
1062 if (pm_iir
& GEN6_PM_RP_DOWN_EI_EXPIRED
) {
1063 if (!vlv_c0_above(dev_priv
,
1064 &dev_priv
->rps
.down_ei
, &now
,
1065 dev_priv
->rps
.down_threshold
))
1066 events
|= GEN6_PM_RP_DOWN_THRESHOLD
;
1067 dev_priv
->rps
.down_ei
= now
;
1070 if (pm_iir
& GEN6_PM_RP_UP_EI_EXPIRED
) {
1071 if (vlv_c0_above(dev_priv
,
1072 &dev_priv
->rps
.up_ei
, &now
,
1073 dev_priv
->rps
.up_threshold
))
1074 events
|= GEN6_PM_RP_UP_THRESHOLD
;
1075 dev_priv
->rps
.up_ei
= now
;
1081 static bool any_waiters(struct drm_i915_private
*dev_priv
)
1083 struct intel_engine_cs
*engine
;
1085 for_each_engine(engine
, dev_priv
)
1086 if (engine
->irq_refcount
)
1092 static void gen6_pm_rps_work(struct work_struct
*work
)
1094 struct drm_i915_private
*dev_priv
=
1095 container_of(work
, struct drm_i915_private
, rps
.work
);
1097 int new_delay
, adj
, min
, max
;
1100 spin_lock_irq(&dev_priv
->irq_lock
);
1101 /* Speed up work cancelation during disabling rps interrupts. */
1102 if (!dev_priv
->rps
.interrupts_enabled
) {
1103 spin_unlock_irq(&dev_priv
->irq_lock
);
1108 * The RPS work is synced during runtime suspend, we don't require a
1109 * wakeref. TODO: instead of disabling the asserts make sure that we
1110 * always hold an RPM reference while the work is running.
1112 DISABLE_RPM_WAKEREF_ASSERTS(dev_priv
);
1114 pm_iir
= dev_priv
->rps
.pm_iir
;
1115 dev_priv
->rps
.pm_iir
= 0;
1116 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1117 gen6_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
1118 client_boost
= dev_priv
->rps
.client_boost
;
1119 dev_priv
->rps
.client_boost
= false;
1120 spin_unlock_irq(&dev_priv
->irq_lock
);
1122 /* Make sure we didn't queue anything we're not going to process. */
1123 WARN_ON(pm_iir
& ~dev_priv
->pm_rps_events
);
1125 if ((pm_iir
& dev_priv
->pm_rps_events
) == 0 && !client_boost
)
1128 mutex_lock(&dev_priv
->rps
.hw_lock
);
1130 pm_iir
|= vlv_wa_c0_ei(dev_priv
, pm_iir
);
1132 adj
= dev_priv
->rps
.last_adj
;
1133 new_delay
= dev_priv
->rps
.cur_freq
;
1134 min
= dev_priv
->rps
.min_freq_softlimit
;
1135 max
= dev_priv
->rps
.max_freq_softlimit
;
1138 new_delay
= dev_priv
->rps
.max_freq_softlimit
;
1140 } else if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
) {
1143 else /* CHV needs even encode values */
1144 adj
= IS_CHERRYVIEW(dev_priv
) ? 2 : 1;
1146 * For better performance, jump directly
1147 * to RPe if we're below it.
1149 if (new_delay
< dev_priv
->rps
.efficient_freq
- adj
) {
1150 new_delay
= dev_priv
->rps
.efficient_freq
;
1153 } else if (any_waiters(dev_priv
)) {
1155 } else if (pm_iir
& GEN6_PM_RP_DOWN_TIMEOUT
) {
1156 if (dev_priv
->rps
.cur_freq
> dev_priv
->rps
.efficient_freq
)
1157 new_delay
= dev_priv
->rps
.efficient_freq
;
1159 new_delay
= dev_priv
->rps
.min_freq_softlimit
;
1161 } else if (pm_iir
& GEN6_PM_RP_DOWN_THRESHOLD
) {
1164 else /* CHV needs even encode values */
1165 adj
= IS_CHERRYVIEW(dev_priv
) ? -2 : -1;
1166 } else { /* unknown event */
1170 dev_priv
->rps
.last_adj
= adj
;
1172 /* sysfs frequency interfaces may have snuck in while servicing the
1176 new_delay
= clamp_t(int, new_delay
, min
, max
);
1178 intel_set_rps(dev_priv
->dev
, new_delay
);
1180 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1182 ENABLE_RPM_WAKEREF_ASSERTS(dev_priv
);
1187 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1189 * @work: workqueue struct
1191 * Doesn't actually do anything except notify userspace. As a consequence of
1192 * this event, userspace should try to remap the bad rows since statistically
1193 * it is likely the same row is more likely to go bad again.
1195 static void ivybridge_parity_work(struct work_struct
*work
)
1197 struct drm_i915_private
*dev_priv
=
1198 container_of(work
, struct drm_i915_private
, l3_parity
.error_work
);
1199 u32 error_status
, row
, bank
, subbank
;
1200 char *parity_event
[6];
1204 /* We must turn off DOP level clock gating to access the L3 registers.
1205 * In order to prevent a get/put style interface, acquire struct mutex
1206 * any time we access those registers.
1208 mutex_lock(&dev_priv
->dev
->struct_mutex
);
1210 /* If we've screwed up tracking, just let the interrupt fire again */
1211 if (WARN_ON(!dev_priv
->l3_parity
.which_slice
))
1214 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
1215 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
1216 POSTING_READ(GEN7_MISCCPCTL
);
1218 while ((slice
= ffs(dev_priv
->l3_parity
.which_slice
)) != 0) {
1222 if (WARN_ON_ONCE(slice
>= NUM_L3_SLICES(dev_priv
)))
1225 dev_priv
->l3_parity
.which_slice
&= ~(1<<slice
);
1227 reg
= GEN7_L3CDERRST1(slice
);
1229 error_status
= I915_READ(reg
);
1230 row
= GEN7_PARITY_ERROR_ROW(error_status
);
1231 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
1232 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
1234 I915_WRITE(reg
, GEN7_PARITY_ERROR_VALID
| GEN7_L3CDERRST1_ENABLE
);
1237 parity_event
[0] = I915_L3_PARITY_UEVENT
"=1";
1238 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
1239 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
1240 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
1241 parity_event
[4] = kasprintf(GFP_KERNEL
, "SLICE=%d", slice
);
1242 parity_event
[5] = NULL
;
1244 kobject_uevent_env(&dev_priv
->dev
->primary
->kdev
->kobj
,
1245 KOBJ_CHANGE
, parity_event
);
1247 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1248 slice
, row
, bank
, subbank
);
1250 kfree(parity_event
[4]);
1251 kfree(parity_event
[3]);
1252 kfree(parity_event
[2]);
1253 kfree(parity_event
[1]);
1256 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
1259 WARN_ON(dev_priv
->l3_parity
.which_slice
);
1260 spin_lock_irq(&dev_priv
->irq_lock
);
1261 gen5_enable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev_priv
));
1262 spin_unlock_irq(&dev_priv
->irq_lock
);
1264 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
1267 static void ivybridge_parity_error_irq_handler(struct drm_device
*dev
, u32 iir
)
1269 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1271 if (!HAS_L3_DPF(dev
))
1274 spin_lock(&dev_priv
->irq_lock
);
1275 gen5_disable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev
));
1276 spin_unlock(&dev_priv
->irq_lock
);
1278 iir
&= GT_PARITY_ERROR(dev
);
1279 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1
)
1280 dev_priv
->l3_parity
.which_slice
|= 1 << 1;
1282 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT
)
1283 dev_priv
->l3_parity
.which_slice
|= 1 << 0;
1285 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
1288 static void ilk_gt_irq_handler(struct drm_device
*dev
,
1289 struct drm_i915_private
*dev_priv
,
1293 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1294 notify_ring(&dev_priv
->engine
[RCS
]);
1295 if (gt_iir
& ILK_BSD_USER_INTERRUPT
)
1296 notify_ring(&dev_priv
->engine
[VCS
]);
1299 static void snb_gt_irq_handler(struct drm_device
*dev
,
1300 struct drm_i915_private
*dev_priv
,
1305 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1306 notify_ring(&dev_priv
->engine
[RCS
]);
1307 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
1308 notify_ring(&dev_priv
->engine
[VCS
]);
1309 if (gt_iir
& GT_BLT_USER_INTERRUPT
)
1310 notify_ring(&dev_priv
->engine
[BCS
]);
1312 if (gt_iir
& (GT_BLT_CS_ERROR_INTERRUPT
|
1313 GT_BSD_CS_ERROR_INTERRUPT
|
1314 GT_RENDER_CS_MASTER_ERROR_INTERRUPT
))
1315 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir
);
1317 if (gt_iir
& GT_PARITY_ERROR(dev
))
1318 ivybridge_parity_error_irq_handler(dev
, gt_iir
);
1321 static __always_inline
void
1322 gen8_cs_irq_handler(struct intel_engine_cs
*engine
, u32 iir
, int test_shift
)
1324 if (iir
& (GT_RENDER_USER_INTERRUPT
<< test_shift
))
1325 notify_ring(engine
);
1326 if (iir
& (GT_CONTEXT_SWITCH_INTERRUPT
<< test_shift
))
1327 tasklet_schedule(&engine
->irq_tasklet
);
1330 static irqreturn_t
gen8_gt_irq_handler(struct drm_i915_private
*dev_priv
,
1333 irqreturn_t ret
= IRQ_NONE
;
1335 if (master_ctl
& (GEN8_GT_RCS_IRQ
| GEN8_GT_BCS_IRQ
)) {
1336 u32 iir
= I915_READ_FW(GEN8_GT_IIR(0));
1338 I915_WRITE_FW(GEN8_GT_IIR(0), iir
);
1341 gen8_cs_irq_handler(&dev_priv
->engine
[RCS
],
1342 iir
, GEN8_RCS_IRQ_SHIFT
);
1344 gen8_cs_irq_handler(&dev_priv
->engine
[BCS
],
1345 iir
, GEN8_BCS_IRQ_SHIFT
);
1347 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1350 if (master_ctl
& (GEN8_GT_VCS1_IRQ
| GEN8_GT_VCS2_IRQ
)) {
1351 u32 iir
= I915_READ_FW(GEN8_GT_IIR(1));
1353 I915_WRITE_FW(GEN8_GT_IIR(1), iir
);
1356 gen8_cs_irq_handler(&dev_priv
->engine
[VCS
],
1357 iir
, GEN8_VCS1_IRQ_SHIFT
);
1359 gen8_cs_irq_handler(&dev_priv
->engine
[VCS2
],
1360 iir
, GEN8_VCS2_IRQ_SHIFT
);
1362 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1365 if (master_ctl
& GEN8_GT_VECS_IRQ
) {
1366 u32 iir
= I915_READ_FW(GEN8_GT_IIR(3));
1368 I915_WRITE_FW(GEN8_GT_IIR(3), iir
);
1371 gen8_cs_irq_handler(&dev_priv
->engine
[VECS
],
1372 iir
, GEN8_VECS_IRQ_SHIFT
);
1374 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1377 if (master_ctl
& GEN8_GT_PM_IRQ
) {
1378 u32 iir
= I915_READ_FW(GEN8_GT_IIR(2));
1379 if (iir
& dev_priv
->pm_rps_events
) {
1380 I915_WRITE_FW(GEN8_GT_IIR(2),
1381 iir
& dev_priv
->pm_rps_events
);
1383 gen6_rps_irq_handler(dev_priv
, iir
);
1385 DRM_ERROR("The master control interrupt lied (PM)!\n");
1391 static bool bxt_port_hotplug_long_detect(enum port port
, u32 val
)
1395 return val
& PORTA_HOTPLUG_LONG_DETECT
;
1397 return val
& PORTB_HOTPLUG_LONG_DETECT
;
1399 return val
& PORTC_HOTPLUG_LONG_DETECT
;
1405 static bool spt_port_hotplug2_long_detect(enum port port
, u32 val
)
1409 return val
& PORTE_HOTPLUG_LONG_DETECT
;
1415 static bool spt_port_hotplug_long_detect(enum port port
, u32 val
)
1419 return val
& PORTA_HOTPLUG_LONG_DETECT
;
1421 return val
& PORTB_HOTPLUG_LONG_DETECT
;
1423 return val
& PORTC_HOTPLUG_LONG_DETECT
;
1425 return val
& PORTD_HOTPLUG_LONG_DETECT
;
1431 static bool ilk_port_hotplug_long_detect(enum port port
, u32 val
)
1435 return val
& DIGITAL_PORTA_HOTPLUG_LONG_DETECT
;
1441 static bool pch_port_hotplug_long_detect(enum port port
, u32 val
)
1445 return val
& PORTB_HOTPLUG_LONG_DETECT
;
1447 return val
& PORTC_HOTPLUG_LONG_DETECT
;
1449 return val
& PORTD_HOTPLUG_LONG_DETECT
;
1455 static bool i9xx_port_hotplug_long_detect(enum port port
, u32 val
)
1459 return val
& PORTB_HOTPLUG_INT_LONG_PULSE
;
1461 return val
& PORTC_HOTPLUG_INT_LONG_PULSE
;
1463 return val
& PORTD_HOTPLUG_INT_LONG_PULSE
;
1470 * Get a bit mask of pins that have triggered, and which ones may be long.
1471 * This can be called multiple times with the same masks to accumulate
1472 * hotplug detection results from several registers.
1474 * Note that the caller is expected to zero out the masks initially.
1476 static void intel_get_hpd_pins(u32
*pin_mask
, u32
*long_mask
,
1477 u32 hotplug_trigger
, u32 dig_hotplug_reg
,
1478 const u32 hpd
[HPD_NUM_PINS
],
1479 bool long_pulse_detect(enum port port
, u32 val
))
1484 for_each_hpd_pin(i
) {
1485 if ((hpd
[i
] & hotplug_trigger
) == 0)
1488 *pin_mask
|= BIT(i
);
1490 if (!intel_hpd_pin_to_port(i
, &port
))
1493 if (long_pulse_detect(port
, dig_hotplug_reg
))
1494 *long_mask
|= BIT(i
);
1497 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1498 hotplug_trigger
, dig_hotplug_reg
, *pin_mask
);
1502 static void gmbus_irq_handler(struct drm_device
*dev
)
1504 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1506 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1509 static void dp_aux_irq_handler(struct drm_device
*dev
)
1511 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1513 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1516 #if defined(CONFIG_DEBUG_FS)
1517 static void display_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
,
1518 uint32_t crc0
, uint32_t crc1
,
1519 uint32_t crc2
, uint32_t crc3
,
1522 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1523 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
1524 struct intel_pipe_crc_entry
*entry
;
1527 spin_lock(&pipe_crc
->lock
);
1529 if (!pipe_crc
->entries
) {
1530 spin_unlock(&pipe_crc
->lock
);
1531 DRM_DEBUG_KMS("spurious interrupt\n");
1535 head
= pipe_crc
->head
;
1536 tail
= pipe_crc
->tail
;
1538 if (CIRC_SPACE(head
, tail
, INTEL_PIPE_CRC_ENTRIES_NR
) < 1) {
1539 spin_unlock(&pipe_crc
->lock
);
1540 DRM_ERROR("CRC buffer overflowing\n");
1544 entry
= &pipe_crc
->entries
[head
];
1546 entry
->frame
= dev
->driver
->get_vblank_counter(dev
, pipe
);
1547 entry
->crc
[0] = crc0
;
1548 entry
->crc
[1] = crc1
;
1549 entry
->crc
[2] = crc2
;
1550 entry
->crc
[3] = crc3
;
1551 entry
->crc
[4] = crc4
;
1553 head
= (head
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
1554 pipe_crc
->head
= head
;
1556 spin_unlock(&pipe_crc
->lock
);
1558 wake_up_interruptible(&pipe_crc
->wq
);
1562 display_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
,
1563 uint32_t crc0
, uint32_t crc1
,
1564 uint32_t crc2
, uint32_t crc3
,
1569 static void hsw_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
)
1571 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1573 display_pipe_crc_irq_handler(dev
, pipe
,
1574 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1578 static void ivb_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
)
1580 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1582 display_pipe_crc_irq_handler(dev
, pipe
,
1583 I915_READ(PIPE_CRC_RES_1_IVB(pipe
)),
1584 I915_READ(PIPE_CRC_RES_2_IVB(pipe
)),
1585 I915_READ(PIPE_CRC_RES_3_IVB(pipe
)),
1586 I915_READ(PIPE_CRC_RES_4_IVB(pipe
)),
1587 I915_READ(PIPE_CRC_RES_5_IVB(pipe
)));
1590 static void i9xx_pipe_crc_irq_handler(struct drm_device
*dev
, enum pipe pipe
)
1592 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1593 uint32_t res1
, res2
;
1595 if (INTEL_INFO(dev
)->gen
>= 3)
1596 res1
= I915_READ(PIPE_CRC_RES_RES1_I915(pipe
));
1600 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
1601 res2
= I915_READ(PIPE_CRC_RES_RES2_G4X(pipe
));
1605 display_pipe_crc_irq_handler(dev
, pipe
,
1606 I915_READ(PIPE_CRC_RES_RED(pipe
)),
1607 I915_READ(PIPE_CRC_RES_GREEN(pipe
)),
1608 I915_READ(PIPE_CRC_RES_BLUE(pipe
)),
1612 /* The RPS events need forcewake, so we add them to a work queue and mask their
1613 * IMR bits until the work is done. Other interrupts can be processed without
1614 * the work queue. */
1615 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1617 if (pm_iir
& dev_priv
->pm_rps_events
) {
1618 spin_lock(&dev_priv
->irq_lock
);
1619 gen6_disable_pm_irq(dev_priv
, pm_iir
& dev_priv
->pm_rps_events
);
1620 if (dev_priv
->rps
.interrupts_enabled
) {
1621 dev_priv
->rps
.pm_iir
|= pm_iir
& dev_priv
->pm_rps_events
;
1622 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
1624 spin_unlock(&dev_priv
->irq_lock
);
1627 if (INTEL_INFO(dev_priv
)->gen
>= 8)
1630 if (HAS_VEBOX(dev_priv
)) {
1631 if (pm_iir
& PM_VEBOX_USER_INTERRUPT
)
1632 notify_ring(&dev_priv
->engine
[VECS
]);
1634 if (pm_iir
& PM_VEBOX_CS_ERROR_INTERRUPT
)
1635 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir
);
1639 static bool intel_pipe_handle_vblank(struct drm_device
*dev
, enum pipe pipe
)
1641 if (!drm_handle_vblank(dev
, pipe
))
1647 static void valleyview_pipestat_irq_handler(struct drm_device
*dev
, u32 iir
)
1649 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1650 u32 pipe_stats
[I915_MAX_PIPES
] = { };
1653 spin_lock(&dev_priv
->irq_lock
);
1655 if (!dev_priv
->display_irqs_enabled
) {
1656 spin_unlock(&dev_priv
->irq_lock
);
1660 for_each_pipe(dev_priv
, pipe
) {
1662 u32 mask
, iir_bit
= 0;
1665 * PIPESTAT bits get signalled even when the interrupt is
1666 * disabled with the mask bits, and some of the status bits do
1667 * not generate interrupts at all (like the underrun bit). Hence
1668 * we need to be careful that we only handle what we want to
1672 /* fifo underruns are filterered in the underrun handler. */
1673 mask
= PIPE_FIFO_UNDERRUN_STATUS
;
1677 iir_bit
= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
;
1680 iir_bit
= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
1683 iir_bit
= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
;
1687 mask
|= dev_priv
->pipestat_irq_mask
[pipe
];
1692 reg
= PIPESTAT(pipe
);
1693 mask
|= PIPESTAT_INT_ENABLE_MASK
;
1694 pipe_stats
[pipe
] = I915_READ(reg
) & mask
;
1697 * Clear the PIPE*STAT regs before the IIR
1699 if (pipe_stats
[pipe
] & (PIPE_FIFO_UNDERRUN_STATUS
|
1700 PIPESTAT_INT_STATUS_MASK
))
1701 I915_WRITE(reg
, pipe_stats
[pipe
]);
1703 spin_unlock(&dev_priv
->irq_lock
);
1705 for_each_pipe(dev_priv
, pipe
) {
1706 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
1707 intel_pipe_handle_vblank(dev
, pipe
))
1708 intel_check_page_flip(dev
, pipe
);
1710 if (pipe_stats
[pipe
] & PLANE_FLIP_DONE_INT_STATUS_VLV
) {
1711 intel_prepare_page_flip(dev
, pipe
);
1712 intel_finish_page_flip(dev
, pipe
);
1715 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
1716 i9xx_pipe_crc_irq_handler(dev
, pipe
);
1718 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
1719 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
1722 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1723 gmbus_irq_handler(dev
);
1726 static void i9xx_hpd_irq_handler(struct drm_device
*dev
)
1728 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1729 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1730 u32 pin_mask
= 0, long_mask
= 0;
1732 if (!hotplug_status
)
1735 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1737 * Make sure hotplug status is cleared before we clear IIR, or else we
1738 * may miss hotplug events.
1740 POSTING_READ(PORT_HOTPLUG_STAT
);
1742 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
1743 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_G4X
;
1745 if (hotplug_trigger
) {
1746 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
1747 hotplug_trigger
, hpd_status_g4x
,
1748 i9xx_port_hotplug_long_detect
);
1750 intel_hpd_irq_handler(dev
, pin_mask
, long_mask
);
1753 if (hotplug_status
& DP_AUX_CHANNEL_MASK_INT_STATUS_G4X
)
1754 dp_aux_irq_handler(dev
);
1756 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
1758 if (hotplug_trigger
) {
1759 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
1760 hotplug_trigger
, hpd_status_i915
,
1761 i9xx_port_hotplug_long_detect
);
1762 intel_hpd_irq_handler(dev
, pin_mask
, long_mask
);
1767 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
1769 struct drm_device
*dev
= arg
;
1770 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1771 u32 iir
, gt_iir
, pm_iir
;
1772 irqreturn_t ret
= IRQ_NONE
;
1774 if (!intel_irqs_enabled(dev_priv
))
1777 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1778 disable_rpm_wakeref_asserts(dev_priv
);
1783 gt_iir
= I915_READ(GTIIR
);
1784 pm_iir
= I915_READ(GEN6_PMIIR
);
1785 iir
= I915_READ(VLV_IIR
);
1787 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
1793 * Theory on interrupt generation, based on empirical evidence:
1795 * x = ((VLV_IIR & VLV_IER) ||
1796 * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1797 * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1799 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1800 * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1801 * guarantee the CPU interrupt will be raised again even if we
1802 * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1803 * bits this time around.
1805 I915_WRITE(VLV_MASTER_IER
, 0);
1806 ier
= I915_READ(VLV_IER
);
1807 I915_WRITE(VLV_IER
, 0);
1810 I915_WRITE(GTIIR
, gt_iir
);
1812 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1815 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1817 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1819 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
1820 i9xx_hpd_irq_handler(dev
);
1822 /* Call regardless, as some status bits might not be
1823 * signalled in iir */
1824 valleyview_pipestat_irq_handler(dev
, iir
);
1827 * VLV_IIR is single buffered, and reflects the level
1828 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1831 I915_WRITE(VLV_IIR
, iir
);
1833 I915_WRITE(VLV_IER
, ier
);
1834 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
1835 POSTING_READ(VLV_MASTER_IER
);
1838 enable_rpm_wakeref_asserts(dev_priv
);
1843 static irqreturn_t
cherryview_irq_handler(int irq
, void *arg
)
1845 struct drm_device
*dev
= arg
;
1846 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1847 u32 master_ctl
, iir
;
1848 irqreturn_t ret
= IRQ_NONE
;
1850 if (!intel_irqs_enabled(dev_priv
))
1853 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1854 disable_rpm_wakeref_asserts(dev_priv
);
1859 master_ctl
= I915_READ(GEN8_MASTER_IRQ
) & ~GEN8_MASTER_IRQ_CONTROL
;
1860 iir
= I915_READ(VLV_IIR
);
1862 if (master_ctl
== 0 && iir
== 0)
1868 * Theory on interrupt generation, based on empirical evidence:
1870 * x = ((VLV_IIR & VLV_IER) ||
1871 * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
1872 * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
1874 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1875 * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
1876 * guarantee the CPU interrupt will be raised again even if we
1877 * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
1878 * bits this time around.
1880 I915_WRITE(GEN8_MASTER_IRQ
, 0);
1881 ier
= I915_READ(VLV_IER
);
1882 I915_WRITE(VLV_IER
, 0);
1884 gen8_gt_irq_handler(dev_priv
, master_ctl
);
1886 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
1887 i9xx_hpd_irq_handler(dev
);
1889 /* Call regardless, as some status bits might not be
1890 * signalled in iir */
1891 valleyview_pipestat_irq_handler(dev
, iir
);
1894 * VLV_IIR is single buffered, and reflects the level
1895 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1898 I915_WRITE(VLV_IIR
, iir
);
1900 I915_WRITE(VLV_IER
, ier
);
1901 I915_WRITE(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
1902 POSTING_READ(GEN8_MASTER_IRQ
);
1905 enable_rpm_wakeref_asserts(dev_priv
);
1910 static void ibx_hpd_irq_handler(struct drm_device
*dev
, u32 hotplug_trigger
,
1911 const u32 hpd
[HPD_NUM_PINS
])
1913 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1914 u32 dig_hotplug_reg
, pin_mask
= 0, long_mask
= 0;
1917 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
1918 * unless we touch the hotplug register, even if hotplug_trigger is
1919 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
1922 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
1923 if (!hotplug_trigger
) {
1924 u32 mask
= PORTA_HOTPLUG_STATUS_MASK
|
1925 PORTD_HOTPLUG_STATUS_MASK
|
1926 PORTC_HOTPLUG_STATUS_MASK
|
1927 PORTB_HOTPLUG_STATUS_MASK
;
1928 dig_hotplug_reg
&= ~mask
;
1931 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
1932 if (!hotplug_trigger
)
1935 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
1936 dig_hotplug_reg
, hpd
,
1937 pch_port_hotplug_long_detect
);
1939 intel_hpd_irq_handler(dev
, pin_mask
, long_mask
);
1942 static void ibx_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1944 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1946 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK
;
1948 ibx_hpd_irq_handler(dev
, hotplug_trigger
, hpd_ibx
);
1950 if (pch_iir
& SDE_AUDIO_POWER_MASK
) {
1951 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK
) >>
1952 SDE_AUDIO_POWER_SHIFT
);
1953 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1957 if (pch_iir
& SDE_AUX_MASK
)
1958 dp_aux_irq_handler(dev
);
1960 if (pch_iir
& SDE_GMBUS
)
1961 gmbus_irq_handler(dev
);
1963 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
1964 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1966 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
1967 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1969 if (pch_iir
& SDE_POISON
)
1970 DRM_ERROR("PCH poison interrupt\n");
1972 if (pch_iir
& SDE_FDI_MASK
)
1973 for_each_pipe(dev_priv
, pipe
)
1974 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1976 I915_READ(FDI_RX_IIR(pipe
)));
1978 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
1979 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1981 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
1982 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1984 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
1985 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_A
);
1987 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
1988 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_B
);
1991 static void ivb_err_int_handler(struct drm_device
*dev
)
1993 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1994 u32 err_int
= I915_READ(GEN7_ERR_INT
);
1997 if (err_int
& ERR_INT_POISON
)
1998 DRM_ERROR("Poison interrupt\n");
2000 for_each_pipe(dev_priv
, pipe
) {
2001 if (err_int
& ERR_INT_FIFO_UNDERRUN(pipe
))
2002 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
2004 if (err_int
& ERR_INT_PIPE_CRC_DONE(pipe
)) {
2005 if (IS_IVYBRIDGE(dev
))
2006 ivb_pipe_crc_irq_handler(dev
, pipe
);
2008 hsw_pipe_crc_irq_handler(dev
, pipe
);
2012 I915_WRITE(GEN7_ERR_INT
, err_int
);
2015 static void cpt_serr_int_handler(struct drm_device
*dev
)
2017 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2018 u32 serr_int
= I915_READ(SERR_INT
);
2020 if (serr_int
& SERR_INT_POISON
)
2021 DRM_ERROR("PCH poison interrupt\n");
2023 if (serr_int
& SERR_INT_TRANS_A_FIFO_UNDERRUN
)
2024 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_A
);
2026 if (serr_int
& SERR_INT_TRANS_B_FIFO_UNDERRUN
)
2027 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_B
);
2029 if (serr_int
& SERR_INT_TRANS_C_FIFO_UNDERRUN
)
2030 intel_pch_fifo_underrun_irq_handler(dev_priv
, TRANSCODER_C
);
2032 I915_WRITE(SERR_INT
, serr_int
);
2035 static void cpt_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
2037 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2039 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_CPT
;
2041 ibx_hpd_irq_handler(dev
, hotplug_trigger
, hpd_cpt
);
2043 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) {
2044 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
2045 SDE_AUDIO_POWER_SHIFT_CPT
);
2046 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2050 if (pch_iir
& SDE_AUX_MASK_CPT
)
2051 dp_aux_irq_handler(dev
);
2053 if (pch_iir
& SDE_GMBUS_CPT
)
2054 gmbus_irq_handler(dev
);
2056 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
2057 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2059 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
2060 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2062 if (pch_iir
& SDE_FDI_MASK_CPT
)
2063 for_each_pipe(dev_priv
, pipe
)
2064 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2066 I915_READ(FDI_RX_IIR(pipe
)));
2068 if (pch_iir
& SDE_ERROR_CPT
)
2069 cpt_serr_int_handler(dev
);
2072 static void spt_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
2074 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2075 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_SPT
&
2076 ~SDE_PORTE_HOTPLUG_SPT
;
2077 u32 hotplug2_trigger
= pch_iir
& SDE_PORTE_HOTPLUG_SPT
;
2078 u32 pin_mask
= 0, long_mask
= 0;
2080 if (hotplug_trigger
) {
2081 u32 dig_hotplug_reg
;
2083 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
2084 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
2086 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
2087 dig_hotplug_reg
, hpd_spt
,
2088 spt_port_hotplug_long_detect
);
2091 if (hotplug2_trigger
) {
2092 u32 dig_hotplug_reg
;
2094 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG2
);
2095 I915_WRITE(PCH_PORT_HOTPLUG2
, dig_hotplug_reg
);
2097 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug2_trigger
,
2098 dig_hotplug_reg
, hpd_spt
,
2099 spt_port_hotplug2_long_detect
);
2103 intel_hpd_irq_handler(dev
, pin_mask
, long_mask
);
2105 if (pch_iir
& SDE_GMBUS_CPT
)
2106 gmbus_irq_handler(dev
);
2109 static void ilk_hpd_irq_handler(struct drm_device
*dev
, u32 hotplug_trigger
,
2110 const u32 hpd
[HPD_NUM_PINS
])
2112 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2113 u32 dig_hotplug_reg
, pin_mask
= 0, long_mask
= 0;
2115 dig_hotplug_reg
= I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL
);
2116 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL
, dig_hotplug_reg
);
2118 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
2119 dig_hotplug_reg
, hpd
,
2120 ilk_port_hotplug_long_detect
);
2122 intel_hpd_irq_handler(dev
, pin_mask
, long_mask
);
2125 static void ilk_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
2127 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2129 u32 hotplug_trigger
= de_iir
& DE_DP_A_HOTPLUG
;
2131 if (hotplug_trigger
)
2132 ilk_hpd_irq_handler(dev
, hotplug_trigger
, hpd_ilk
);
2134 if (de_iir
& DE_AUX_CHANNEL_A
)
2135 dp_aux_irq_handler(dev
);
2137 if (de_iir
& DE_GSE
)
2138 intel_opregion_asle_intr(dev
);
2140 if (de_iir
& DE_POISON
)
2141 DRM_ERROR("Poison interrupt\n");
2143 for_each_pipe(dev_priv
, pipe
) {
2144 if (de_iir
& DE_PIPE_VBLANK(pipe
) &&
2145 intel_pipe_handle_vblank(dev
, pipe
))
2146 intel_check_page_flip(dev
, pipe
);
2148 if (de_iir
& DE_PIPE_FIFO_UNDERRUN(pipe
))
2149 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
2151 if (de_iir
& DE_PIPE_CRC_DONE(pipe
))
2152 i9xx_pipe_crc_irq_handler(dev
, pipe
);
2154 /* plane/pipes map 1:1 on ilk+ */
2155 if (de_iir
& DE_PLANE_FLIP_DONE(pipe
)) {
2156 intel_prepare_page_flip(dev
, pipe
);
2157 intel_finish_page_flip_plane(dev
, pipe
);
2161 /* check event from PCH */
2162 if (de_iir
& DE_PCH_EVENT
) {
2163 u32 pch_iir
= I915_READ(SDEIIR
);
2165 if (HAS_PCH_CPT(dev
))
2166 cpt_irq_handler(dev
, pch_iir
);
2168 ibx_irq_handler(dev
, pch_iir
);
2170 /* should clear PCH hotplug event before clear CPU irq */
2171 I915_WRITE(SDEIIR
, pch_iir
);
2174 if (IS_GEN5(dev
) && de_iir
& DE_PCU_EVENT
)
2175 ironlake_rps_change_irq_handler(dev
);
2178 static void ivb_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
2180 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2182 u32 hotplug_trigger
= de_iir
& DE_DP_A_HOTPLUG_IVB
;
2184 if (hotplug_trigger
)
2185 ilk_hpd_irq_handler(dev
, hotplug_trigger
, hpd_ivb
);
2187 if (de_iir
& DE_ERR_INT_IVB
)
2188 ivb_err_int_handler(dev
);
2190 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
2191 dp_aux_irq_handler(dev
);
2193 if (de_iir
& DE_GSE_IVB
)
2194 intel_opregion_asle_intr(dev
);
2196 for_each_pipe(dev_priv
, pipe
) {
2197 if (de_iir
& (DE_PIPE_VBLANK_IVB(pipe
)) &&
2198 intel_pipe_handle_vblank(dev
, pipe
))
2199 intel_check_page_flip(dev
, pipe
);
2201 /* plane/pipes map 1:1 on ilk+ */
2202 if (de_iir
& DE_PLANE_FLIP_DONE_IVB(pipe
)) {
2203 intel_prepare_page_flip(dev
, pipe
);
2204 intel_finish_page_flip_plane(dev
, pipe
);
2208 /* check event from PCH */
2209 if (!HAS_PCH_NOP(dev
) && (de_iir
& DE_PCH_EVENT_IVB
)) {
2210 u32 pch_iir
= I915_READ(SDEIIR
);
2212 cpt_irq_handler(dev
, pch_iir
);
2214 /* clear PCH hotplug event before clear CPU irq */
2215 I915_WRITE(SDEIIR
, pch_iir
);
2220 * To handle irqs with the minimum potential races with fresh interrupts, we:
2221 * 1 - Disable Master Interrupt Control.
2222 * 2 - Find the source(s) of the interrupt.
2223 * 3 - Clear the Interrupt Identity bits (IIR).
2224 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2225 * 5 - Re-enable Master Interrupt Control.
2227 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
2229 struct drm_device
*dev
= arg
;
2230 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2231 u32 de_iir
, gt_iir
, de_ier
, sde_ier
= 0;
2232 irqreturn_t ret
= IRQ_NONE
;
2234 if (!intel_irqs_enabled(dev_priv
))
2237 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2238 disable_rpm_wakeref_asserts(dev_priv
);
2240 /* disable master interrupt before clearing iir */
2241 de_ier
= I915_READ(DEIER
);
2242 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
2243 POSTING_READ(DEIER
);
2245 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2246 * interrupts will will be stored on its back queue, and then we'll be
2247 * able to process them after we restore SDEIER (as soon as we restore
2248 * it, we'll get an interrupt if SDEIIR still has something to process
2249 * due to its back queue). */
2250 if (!HAS_PCH_NOP(dev
)) {
2251 sde_ier
= I915_READ(SDEIER
);
2252 I915_WRITE(SDEIER
, 0);
2253 POSTING_READ(SDEIER
);
2256 /* Find, clear, then process each source of interrupt */
2258 gt_iir
= I915_READ(GTIIR
);
2260 I915_WRITE(GTIIR
, gt_iir
);
2262 if (INTEL_INFO(dev
)->gen
>= 6)
2263 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
2265 ilk_gt_irq_handler(dev
, dev_priv
, gt_iir
);
2268 de_iir
= I915_READ(DEIIR
);
2270 I915_WRITE(DEIIR
, de_iir
);
2272 if (INTEL_INFO(dev
)->gen
>= 7)
2273 ivb_display_irq_handler(dev
, de_iir
);
2275 ilk_display_irq_handler(dev
, de_iir
);
2278 if (INTEL_INFO(dev
)->gen
>= 6) {
2279 u32 pm_iir
= I915_READ(GEN6_PMIIR
);
2281 I915_WRITE(GEN6_PMIIR
, pm_iir
);
2283 gen6_rps_irq_handler(dev_priv
, pm_iir
);
2287 I915_WRITE(DEIER
, de_ier
);
2288 POSTING_READ(DEIER
);
2289 if (!HAS_PCH_NOP(dev
)) {
2290 I915_WRITE(SDEIER
, sde_ier
);
2291 POSTING_READ(SDEIER
);
2294 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2295 enable_rpm_wakeref_asserts(dev_priv
);
2300 static void bxt_hpd_irq_handler(struct drm_device
*dev
, u32 hotplug_trigger
,
2301 const u32 hpd
[HPD_NUM_PINS
])
2303 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2304 u32 dig_hotplug_reg
, pin_mask
= 0, long_mask
= 0;
2306 dig_hotplug_reg
= I915_READ(PCH_PORT_HOTPLUG
);
2307 I915_WRITE(PCH_PORT_HOTPLUG
, dig_hotplug_reg
);
2309 intel_get_hpd_pins(&pin_mask
, &long_mask
, hotplug_trigger
,
2310 dig_hotplug_reg
, hpd
,
2311 bxt_port_hotplug_long_detect
);
2313 intel_hpd_irq_handler(dev
, pin_mask
, long_mask
);
2317 gen8_de_irq_handler(struct drm_i915_private
*dev_priv
, u32 master_ctl
)
2319 struct drm_device
*dev
= dev_priv
->dev
;
2320 irqreturn_t ret
= IRQ_NONE
;
2324 if (master_ctl
& GEN8_DE_MISC_IRQ
) {
2325 iir
= I915_READ(GEN8_DE_MISC_IIR
);
2327 I915_WRITE(GEN8_DE_MISC_IIR
, iir
);
2329 if (iir
& GEN8_DE_MISC_GSE
)
2330 intel_opregion_asle_intr(dev
);
2332 DRM_ERROR("Unexpected DE Misc interrupt\n");
2335 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2338 if (master_ctl
& GEN8_DE_PORT_IRQ
) {
2339 iir
= I915_READ(GEN8_DE_PORT_IIR
);
2344 I915_WRITE(GEN8_DE_PORT_IIR
, iir
);
2347 tmp_mask
= GEN8_AUX_CHANNEL_A
;
2348 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2349 tmp_mask
|= GEN9_AUX_CHANNEL_B
|
2350 GEN9_AUX_CHANNEL_C
|
2353 if (iir
& tmp_mask
) {
2354 dp_aux_irq_handler(dev
);
2358 if (IS_BROXTON(dev_priv
)) {
2359 tmp_mask
= iir
& BXT_DE_PORT_HOTPLUG_MASK
;
2361 bxt_hpd_irq_handler(dev
, tmp_mask
, hpd_bxt
);
2364 } else if (IS_BROADWELL(dev_priv
)) {
2365 tmp_mask
= iir
& GEN8_PORT_DP_A_HOTPLUG
;
2367 ilk_hpd_irq_handler(dev
, tmp_mask
, hpd_bdw
);
2372 if (IS_BROXTON(dev
) && (iir
& BXT_DE_PORT_GMBUS
)) {
2373 gmbus_irq_handler(dev
);
2378 DRM_ERROR("Unexpected DE Port interrupt\n");
2381 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2384 for_each_pipe(dev_priv
, pipe
) {
2385 u32 flip_done
, fault_errors
;
2387 if (!(master_ctl
& GEN8_DE_PIPE_IRQ(pipe
)))
2390 iir
= I915_READ(GEN8_DE_PIPE_IIR(pipe
));
2392 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2397 I915_WRITE(GEN8_DE_PIPE_IIR(pipe
), iir
);
2399 if (iir
& GEN8_PIPE_VBLANK
&&
2400 intel_pipe_handle_vblank(dev
, pipe
))
2401 intel_check_page_flip(dev
, pipe
);
2404 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2405 flip_done
&= GEN9_PIPE_PLANE1_FLIP_DONE
;
2407 flip_done
&= GEN8_PIPE_PRIMARY_FLIP_DONE
;
2410 intel_prepare_page_flip(dev
, pipe
);
2411 intel_finish_page_flip_plane(dev
, pipe
);
2414 if (iir
& GEN8_PIPE_CDCLK_CRC_DONE
)
2415 hsw_pipe_crc_irq_handler(dev
, pipe
);
2417 if (iir
& GEN8_PIPE_FIFO_UNDERRUN
)
2418 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
2421 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2422 fault_errors
&= GEN9_DE_PIPE_IRQ_FAULT_ERRORS
;
2424 fault_errors
&= GEN8_DE_PIPE_IRQ_FAULT_ERRORS
;
2427 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2432 if (HAS_PCH_SPLIT(dev
) && !HAS_PCH_NOP(dev
) &&
2433 master_ctl
& GEN8_DE_PCH_IRQ
) {
2435 * FIXME(BDW): Assume for now that the new interrupt handling
2436 * scheme also closed the SDE interrupt handling race we've seen
2437 * on older pch-split platforms. But this needs testing.
2439 iir
= I915_READ(SDEIIR
);
2441 I915_WRITE(SDEIIR
, iir
);
2444 if (HAS_PCH_SPT(dev_priv
))
2445 spt_irq_handler(dev
, iir
);
2447 cpt_irq_handler(dev
, iir
);
2450 * Like on previous PCH there seems to be something
2451 * fishy going on with forwarding PCH interrupts.
2453 DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2460 static irqreturn_t
gen8_irq_handler(int irq
, void *arg
)
2462 struct drm_device
*dev
= arg
;
2463 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2467 if (!intel_irqs_enabled(dev_priv
))
2470 master_ctl
= I915_READ_FW(GEN8_MASTER_IRQ
);
2471 master_ctl
&= ~GEN8_MASTER_IRQ_CONTROL
;
2475 I915_WRITE_FW(GEN8_MASTER_IRQ
, 0);
2477 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2478 disable_rpm_wakeref_asserts(dev_priv
);
2480 /* Find, clear, then process each source of interrupt */
2481 ret
= gen8_gt_irq_handler(dev_priv
, master_ctl
);
2482 ret
|= gen8_de_irq_handler(dev_priv
, master_ctl
);
2484 I915_WRITE_FW(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
2485 POSTING_READ_FW(GEN8_MASTER_IRQ
);
2487 enable_rpm_wakeref_asserts(dev_priv
);
2492 static void i915_error_wake_up(struct drm_i915_private
*dev_priv
,
2493 bool reset_completed
)
2495 struct intel_engine_cs
*engine
;
2498 * Notify all waiters for GPU completion events that reset state has
2499 * been changed, and that they need to restart their wait after
2500 * checking for potential errors (and bail out to drop locks if there is
2501 * a gpu reset pending so that i915_error_work_func can acquire them).
2504 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2505 for_each_engine(engine
, dev_priv
)
2506 wake_up_all(&engine
->irq_queue
);
2508 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2509 wake_up_all(&dev_priv
->pending_flip_queue
);
2512 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2513 * reset state is cleared.
2515 if (reset_completed
)
2516 wake_up_all(&dev_priv
->gpu_error
.reset_queue
);
2520 * i915_reset_and_wakeup - do process context error handling work
2523 * Fire an error uevent so userspace can see that a hang or error
2526 static void i915_reset_and_wakeup(struct drm_device
*dev
)
2528 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2529 char *error_event
[] = { I915_ERROR_UEVENT
"=1", NULL
};
2530 char *reset_event
[] = { I915_RESET_UEVENT
"=1", NULL
};
2531 char *reset_done_event
[] = { I915_ERROR_UEVENT
"=0", NULL
};
2534 kobject_uevent_env(&dev
->primary
->kdev
->kobj
, KOBJ_CHANGE
, error_event
);
2537 * Note that there's only one work item which does gpu resets, so we
2538 * need not worry about concurrent gpu resets potentially incrementing
2539 * error->reset_counter twice. We only need to take care of another
2540 * racing irq/hangcheck declaring the gpu dead for a second time. A
2541 * quick check for that is good enough: schedule_work ensures the
2542 * correct ordering between hang detection and this work item, and since
2543 * the reset in-progress bit is only ever set by code outside of this
2544 * work we don't need to worry about any other races.
2546 if (i915_reset_in_progress(&dev_priv
->gpu_error
)) {
2547 DRM_DEBUG_DRIVER("resetting chip\n");
2548 kobject_uevent_env(&dev
->primary
->kdev
->kobj
, KOBJ_CHANGE
,
2552 * In most cases it's guaranteed that we get here with an RPM
2553 * reference held, for example because there is a pending GPU
2554 * request that won't finish until the reset is done. This
2555 * isn't the case at least when we get here by doing a
2556 * simulated reset via debugs, so get an RPM reference.
2558 intel_runtime_pm_get(dev_priv
);
2560 intel_prepare_reset(dev
);
2563 * All state reset _must_ be completed before we update the
2564 * reset counter, for otherwise waiters might miss the reset
2565 * pending state and not properly drop locks, resulting in
2566 * deadlocks with the reset work.
2568 ret
= i915_reset(dev
);
2570 intel_finish_reset(dev
);
2572 intel_runtime_pm_put(dev_priv
);
2575 kobject_uevent_env(&dev
->primary
->kdev
->kobj
,
2576 KOBJ_CHANGE
, reset_done_event
);
2579 * Note: The wake_up also serves as a memory barrier so that
2580 * waiters see the update value of the reset counter atomic_t.
2582 i915_error_wake_up(dev_priv
, true);
2586 static void i915_report_and_clear_eir(struct drm_device
*dev
)
2588 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2589 uint32_t instdone
[I915_NUM_INSTDONE_REG
];
2590 u32 eir
= I915_READ(EIR
);
2596 pr_err("render error detected, EIR: 0x%08x\n", eir
);
2598 i915_get_extra_instdone(dev
, instdone
);
2601 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
2602 u32 ipeir
= I915_READ(IPEIR_I965
);
2604 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
2605 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
2606 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
2607 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
2608 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
2609 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
2610 I915_WRITE(IPEIR_I965
, ipeir
);
2611 POSTING_READ(IPEIR_I965
);
2613 if (eir
& GM45_ERROR_PAGE_TABLE
) {
2614 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
2615 pr_err("page table error\n");
2616 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
2617 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2618 POSTING_READ(PGTBL_ER
);
2622 if (!IS_GEN2(dev
)) {
2623 if (eir
& I915_ERROR_PAGE_TABLE
) {
2624 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
2625 pr_err("page table error\n");
2626 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
2627 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2628 POSTING_READ(PGTBL_ER
);
2632 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
2633 pr_err("memory refresh error:\n");
2634 for_each_pipe(dev_priv
, pipe
)
2635 pr_err("pipe %c stat: 0x%08x\n",
2636 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
2637 /* pipestat has already been acked */
2639 if (eir
& I915_ERROR_INSTRUCTION
) {
2640 pr_err("instruction error\n");
2641 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
2642 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
2643 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
2644 if (INTEL_INFO(dev
)->gen
< 4) {
2645 u32 ipeir
= I915_READ(IPEIR
);
2647 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
2648 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
2649 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
2650 I915_WRITE(IPEIR
, ipeir
);
2651 POSTING_READ(IPEIR
);
2653 u32 ipeir
= I915_READ(IPEIR_I965
);
2655 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
2656 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
2657 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
2658 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
2659 I915_WRITE(IPEIR_I965
, ipeir
);
2660 POSTING_READ(IPEIR_I965
);
2664 I915_WRITE(EIR
, eir
);
2666 eir
= I915_READ(EIR
);
2669 * some errors might have become stuck,
2672 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
2673 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
2674 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2679 * i915_handle_error - handle a gpu error
2681 * @engine_mask: mask representing engines that are hung
2682 * Do some basic checking of register state at error time and
2683 * dump it to the syslog. Also call i915_capture_error_state() to make
2684 * sure we get a record and make it available in debugfs. Fire a uevent
2685 * so userspace knows something bad happened (should trigger collection
2686 * of a ring dump etc.).
2688 void i915_handle_error(struct drm_device
*dev
, u32 engine_mask
,
2689 const char *fmt
, ...)
2691 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2695 va_start(args
, fmt
);
2696 vscnprintf(error_msg
, sizeof(error_msg
), fmt
, args
);
2699 i915_capture_error_state(dev
, engine_mask
, error_msg
);
2700 i915_report_and_clear_eir(dev
);
2703 atomic_or(I915_RESET_IN_PROGRESS_FLAG
,
2704 &dev_priv
->gpu_error
.reset_counter
);
2707 * Wakeup waiting processes so that the reset function
2708 * i915_reset_and_wakeup doesn't deadlock trying to grab
2709 * various locks. By bumping the reset counter first, the woken
2710 * processes will see a reset in progress and back off,
2711 * releasing their locks and then wait for the reset completion.
2712 * We must do this for _all_ gpu waiters that might hold locks
2713 * that the reset work needs to acquire.
2715 * Note: The wake_up serves as the required memory barrier to
2716 * ensure that the waiters see the updated value of the reset
2719 i915_error_wake_up(dev_priv
, false);
2722 i915_reset_and_wakeup(dev
);
2725 /* Called from drm generic code, passed 'crtc' which
2726 * we use as a pipe index
2728 static int i915_enable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2730 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2731 unsigned long irqflags
;
2733 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2734 if (INTEL_INFO(dev
)->gen
>= 4)
2735 i915_enable_pipestat(dev_priv
, pipe
,
2736 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2738 i915_enable_pipestat(dev_priv
, pipe
,
2739 PIPE_VBLANK_INTERRUPT_STATUS
);
2740 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2745 static int ironlake_enable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2747 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2748 unsigned long irqflags
;
2749 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
2750 DE_PIPE_VBLANK(pipe
);
2752 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2753 ilk_enable_display_irq(dev_priv
, bit
);
2754 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2759 static int valleyview_enable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2761 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2762 unsigned long irqflags
;
2764 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2765 i915_enable_pipestat(dev_priv
, pipe
,
2766 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2767 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2772 static int gen8_enable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2774 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2775 unsigned long irqflags
;
2777 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2778 bdw_enable_pipe_irq(dev_priv
, pipe
, GEN8_PIPE_VBLANK
);
2779 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2784 /* Called from drm generic code, passed 'crtc' which
2785 * we use as a pipe index
2787 static void i915_disable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2789 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2790 unsigned long irqflags
;
2792 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2793 i915_disable_pipestat(dev_priv
, pipe
,
2794 PIPE_VBLANK_INTERRUPT_STATUS
|
2795 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2796 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2799 static void ironlake_disable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2801 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2802 unsigned long irqflags
;
2803 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
2804 DE_PIPE_VBLANK(pipe
);
2806 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2807 ilk_disable_display_irq(dev_priv
, bit
);
2808 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2811 static void valleyview_disable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2813 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2814 unsigned long irqflags
;
2816 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2817 i915_disable_pipestat(dev_priv
, pipe
,
2818 PIPE_START_VBLANK_INTERRUPT_STATUS
);
2819 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2822 static void gen8_disable_vblank(struct drm_device
*dev
, unsigned int pipe
)
2824 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2825 unsigned long irqflags
;
2827 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2828 bdw_disable_pipe_irq(dev_priv
, pipe
, GEN8_PIPE_VBLANK
);
2829 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2833 ring_idle(struct intel_engine_cs
*engine
, u32 seqno
)
2835 return i915_seqno_passed(seqno
,
2836 READ_ONCE(engine
->last_submitted_seqno
));
2840 ipehr_is_semaphore_wait(struct drm_device
*dev
, u32 ipehr
)
2842 if (INTEL_INFO(dev
)->gen
>= 8) {
2843 return (ipehr
>> 23) == 0x1c;
2845 ipehr
&= ~MI_SEMAPHORE_SYNC_MASK
;
2846 return ipehr
== (MI_SEMAPHORE_MBOX
| MI_SEMAPHORE_COMPARE
|
2847 MI_SEMAPHORE_REGISTER
);
2851 static struct intel_engine_cs
*
2852 semaphore_wait_to_signaller_ring(struct intel_engine_cs
*engine
, u32 ipehr
,
2855 struct drm_i915_private
*dev_priv
= engine
->dev
->dev_private
;
2856 struct intel_engine_cs
*signaller
;
2858 if (INTEL_INFO(dev_priv
)->gen
>= 8) {
2859 for_each_engine(signaller
, dev_priv
) {
2860 if (engine
== signaller
)
2863 if (offset
== signaller
->semaphore
.signal_ggtt
[engine
->id
])
2867 u32 sync_bits
= ipehr
& MI_SEMAPHORE_SYNC_MASK
;
2869 for_each_engine(signaller
, dev_priv
) {
2870 if(engine
== signaller
)
2873 if (sync_bits
== signaller
->semaphore
.mbox
.wait
[engine
->id
])
2878 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2879 engine
->id
, ipehr
, offset
);
2884 static struct intel_engine_cs
*
2885 semaphore_waits_for(struct intel_engine_cs
*engine
, u32
*seqno
)
2887 struct drm_i915_private
*dev_priv
= engine
->dev
->dev_private
;
2888 u32 cmd
, ipehr
, head
;
2893 * This function does not support execlist mode - any attempt to
2894 * proceed further into this function will result in a kernel panic
2895 * when dereferencing ring->buffer, which is not set up in execlist
2898 * The correct way of doing it would be to derive the currently
2899 * executing ring buffer from the current context, which is derived
2900 * from the currently running request. Unfortunately, to get the
2901 * current request we would have to grab the struct_mutex before doing
2902 * anything else, which would be ill-advised since some other thread
2903 * might have grabbed it already and managed to hang itself, causing
2904 * the hang checker to deadlock.
2906 * Therefore, this function does not support execlist mode in its
2907 * current form. Just return NULL and move on.
2909 if (engine
->buffer
== NULL
)
2912 ipehr
= I915_READ(RING_IPEHR(engine
->mmio_base
));
2913 if (!ipehr_is_semaphore_wait(engine
->dev
, ipehr
))
2917 * HEAD is likely pointing to the dword after the actual command,
2918 * so scan backwards until we find the MBOX. But limit it to just 3
2919 * or 4 dwords depending on the semaphore wait command size.
2920 * Note that we don't care about ACTHD here since that might
2921 * point at at batch, and semaphores are always emitted into the
2922 * ringbuffer itself.
2924 head
= I915_READ_HEAD(engine
) & HEAD_ADDR
;
2925 backwards
= (INTEL_INFO(engine
->dev
)->gen
>= 8) ? 5 : 4;
2927 for (i
= backwards
; i
; --i
) {
2929 * Be paranoid and presume the hw has gone off into the wild -
2930 * our ring is smaller than what the hardware (and hence
2931 * HEAD_ADDR) allows. Also handles wrap-around.
2933 head
&= engine
->buffer
->size
- 1;
2935 /* This here seems to blow up */
2936 cmd
= ioread32(engine
->buffer
->virtual_start
+ head
);
2946 *seqno
= ioread32(engine
->buffer
->virtual_start
+ head
+ 4) + 1;
2947 if (INTEL_INFO(engine
->dev
)->gen
>= 8) {
2948 offset
= ioread32(engine
->buffer
->virtual_start
+ head
+ 12);
2950 offset
= ioread32(engine
->buffer
->virtual_start
+ head
+ 8);
2952 return semaphore_wait_to_signaller_ring(engine
, ipehr
, offset
);
2955 static int semaphore_passed(struct intel_engine_cs
*engine
)
2957 struct drm_i915_private
*dev_priv
= engine
->dev
->dev_private
;
2958 struct intel_engine_cs
*signaller
;
2961 engine
->hangcheck
.deadlock
++;
2963 signaller
= semaphore_waits_for(engine
, &seqno
);
2964 if (signaller
== NULL
)
2967 /* Prevent pathological recursion due to driver bugs */
2968 if (signaller
->hangcheck
.deadlock
>= I915_NUM_ENGINES
)
2971 if (i915_seqno_passed(signaller
->get_seqno(signaller
), seqno
))
2974 /* cursory check for an unkickable deadlock */
2975 if (I915_READ_CTL(signaller
) & RING_WAIT_SEMAPHORE
&&
2976 semaphore_passed(signaller
) < 0)
2982 static void semaphore_clear_deadlocks(struct drm_i915_private
*dev_priv
)
2984 struct intel_engine_cs
*engine
;
2986 for_each_engine(engine
, dev_priv
)
2987 engine
->hangcheck
.deadlock
= 0;
2990 static bool subunits_stuck(struct intel_engine_cs
*engine
)
2992 u32 instdone
[I915_NUM_INSTDONE_REG
];
2996 if (engine
->id
!= RCS
)
2999 i915_get_extra_instdone(engine
->dev
, instdone
);
3001 /* There might be unstable subunit states even when
3002 * actual head is not moving. Filter out the unstable ones by
3003 * accumulating the undone -> done transitions and only
3004 * consider those as progress.
3007 for (i
= 0; i
< I915_NUM_INSTDONE_REG
; i
++) {
3008 const u32 tmp
= instdone
[i
] | engine
->hangcheck
.instdone
[i
];
3010 if (tmp
!= engine
->hangcheck
.instdone
[i
])
3013 engine
->hangcheck
.instdone
[i
] |= tmp
;
3019 static enum intel_ring_hangcheck_action
3020 head_stuck(struct intel_engine_cs
*engine
, u64 acthd
)
3022 if (acthd
!= engine
->hangcheck
.acthd
) {
3024 /* Clear subunit states on head movement */
3025 memset(engine
->hangcheck
.instdone
, 0,
3026 sizeof(engine
->hangcheck
.instdone
));
3028 return HANGCHECK_ACTIVE
;
3031 if (!subunits_stuck(engine
))
3032 return HANGCHECK_ACTIVE
;
3034 return HANGCHECK_HUNG
;
3037 static enum intel_ring_hangcheck_action
3038 ring_stuck(struct intel_engine_cs
*engine
, u64 acthd
)
3040 struct drm_device
*dev
= engine
->dev
;
3041 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3042 enum intel_ring_hangcheck_action ha
;
3045 ha
= head_stuck(engine
, acthd
);
3046 if (ha
!= HANGCHECK_HUNG
)
3050 return HANGCHECK_HUNG
;
3052 /* Is the chip hanging on a WAIT_FOR_EVENT?
3053 * If so we can simply poke the RB_WAIT bit
3054 * and break the hang. This should work on
3055 * all but the second generation chipsets.
3057 tmp
= I915_READ_CTL(engine
);
3058 if (tmp
& RING_WAIT
) {
3059 i915_handle_error(dev
, 0,
3060 "Kicking stuck wait on %s",
3062 I915_WRITE_CTL(engine
, tmp
);
3063 return HANGCHECK_KICK
;
3066 if (INTEL_INFO(dev
)->gen
>= 6 && tmp
& RING_WAIT_SEMAPHORE
) {
3067 switch (semaphore_passed(engine
)) {
3069 return HANGCHECK_HUNG
;
3071 i915_handle_error(dev
, 0,
3072 "Kicking stuck semaphore on %s",
3074 I915_WRITE_CTL(engine
, tmp
);
3075 return HANGCHECK_KICK
;
3077 return HANGCHECK_WAIT
;
3081 return HANGCHECK_HUNG
;
3084 static unsigned kick_waiters(struct intel_engine_cs
*engine
)
3086 struct drm_i915_private
*i915
= to_i915(engine
->dev
);
3087 unsigned user_interrupts
= READ_ONCE(engine
->user_interrupts
);
3089 if (engine
->hangcheck
.user_interrupts
== user_interrupts
&&
3090 !test_and_set_bit(engine
->id
, &i915
->gpu_error
.missed_irq_rings
)) {
3091 if (!(i915
->gpu_error
.test_irq_rings
& intel_engine_flag(engine
)))
3092 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
3095 DRM_INFO("Fake missed irq on %s\n",
3097 wake_up_all(&engine
->irq_queue
);
3100 return user_interrupts
;
3103 * This is called when the chip hasn't reported back with completed
3104 * batchbuffers in a long time. We keep track per ring seqno progress and
3105 * if there are no progress, hangcheck score for that ring is increased.
3106 * Further, acthd is inspected to see if the ring is stuck. On stuck case
3107 * we kick the ring. If we see no progress on three subsequent calls
3108 * we assume chip is wedged and try to fix it by resetting the chip.
3110 static void i915_hangcheck_elapsed(struct work_struct
*work
)
3112 struct drm_i915_private
*dev_priv
=
3113 container_of(work
, typeof(*dev_priv
),
3114 gpu_error
.hangcheck_work
.work
);
3115 struct drm_device
*dev
= dev_priv
->dev
;
3116 struct intel_engine_cs
*engine
;
3117 enum intel_engine_id id
;
3118 int busy_count
= 0, rings_hung
= 0;
3119 bool stuck
[I915_NUM_ENGINES
] = { 0 };
3123 #define ACTIVE_DECAY 15
3125 if (!i915
.enable_hangcheck
)
3129 * The hangcheck work is synced during runtime suspend, we don't
3130 * require a wakeref. TODO: instead of disabling the asserts make
3131 * sure that we hold a reference when this work is running.
3133 DISABLE_RPM_WAKEREF_ASSERTS(dev_priv
);
3135 /* As enabling the GPU requires fairly extensive mmio access,
3136 * periodically arm the mmio checker to see if we are triggering
3137 * any invalid access.
3139 intel_uncore_arm_unclaimed_mmio_detection(dev_priv
);
3141 for_each_engine_id(engine
, dev_priv
, id
) {
3144 unsigned user_interrupts
;
3147 semaphore_clear_deadlocks(dev_priv
);
3149 /* We don't strictly need an irq-barrier here, as we are not
3150 * serving an interrupt request, be paranoid in case the
3151 * barrier has side-effects (such as preventing a broken
3152 * cacheline snoop) and so be sure that we can see the seqno
3153 * advance. If the seqno should stick, due to a stale
3154 * cacheline, we would erroneously declare the GPU hung.
3156 if (engine
->irq_seqno_barrier
)
3157 engine
->irq_seqno_barrier(engine
);
3159 acthd
= intel_ring_get_active_head(engine
);
3160 seqno
= engine
->get_seqno(engine
);
3162 /* Reset stuck interrupts between batch advances */
3163 user_interrupts
= 0;
3165 if (engine
->hangcheck
.seqno
== seqno
) {
3166 if (ring_idle(engine
, seqno
)) {
3167 engine
->hangcheck
.action
= HANGCHECK_IDLE
;
3168 if (waitqueue_active(&engine
->irq_queue
)) {
3169 /* Safeguard against driver failure */
3170 user_interrupts
= kick_waiters(engine
);
3171 engine
->hangcheck
.score
+= BUSY
;
3175 /* We always increment the hangcheck score
3176 * if the ring is busy and still processing
3177 * the same request, so that no single request
3178 * can run indefinitely (such as a chain of
3179 * batches). The only time we do not increment
3180 * the hangcheck score on this ring, if this
3181 * ring is in a legitimate wait for another
3182 * ring. In that case the waiting ring is a
3183 * victim and we want to be sure we catch the
3184 * right culprit. Then every time we do kick
3185 * the ring, add a small increment to the
3186 * score so that we can catch a batch that is
3187 * being repeatedly kicked and so responsible
3188 * for stalling the machine.
3190 engine
->hangcheck
.action
= ring_stuck(engine
,
3193 switch (engine
->hangcheck
.action
) {
3194 case HANGCHECK_IDLE
:
3195 case HANGCHECK_WAIT
:
3197 case HANGCHECK_ACTIVE
:
3198 engine
->hangcheck
.score
+= BUSY
;
3200 case HANGCHECK_KICK
:
3201 engine
->hangcheck
.score
+= KICK
;
3203 case HANGCHECK_HUNG
:
3204 engine
->hangcheck
.score
+= HUNG
;
3210 engine
->hangcheck
.action
= HANGCHECK_ACTIVE
;
3212 /* Gradually reduce the count so that we catch DoS
3213 * attempts across multiple batches.
3215 if (engine
->hangcheck
.score
> 0)
3216 engine
->hangcheck
.score
-= ACTIVE_DECAY
;
3217 if (engine
->hangcheck
.score
< 0)
3218 engine
->hangcheck
.score
= 0;
3220 /* Clear head and subunit states on seqno movement */
3223 memset(engine
->hangcheck
.instdone
, 0,
3224 sizeof(engine
->hangcheck
.instdone
));
3227 engine
->hangcheck
.seqno
= seqno
;
3228 engine
->hangcheck
.acthd
= acthd
;
3229 engine
->hangcheck
.user_interrupts
= user_interrupts
;
3233 for_each_engine_id(engine
, dev_priv
, id
) {
3234 if (engine
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
) {
3235 DRM_INFO("%s on %s\n",
3236 stuck
[id
] ? "stuck" : "no progress",
3238 rings_hung
|= intel_engine_flag(engine
);
3243 i915_handle_error(dev
, rings_hung
, "Engine(s) hung");
3248 /* Reset timer case chip hangs without another request
3250 i915_queue_hangcheck(dev
);
3253 ENABLE_RPM_WAKEREF_ASSERTS(dev_priv
);
3256 void i915_queue_hangcheck(struct drm_device
*dev
)
3258 struct i915_gpu_error
*e
= &to_i915(dev
)->gpu_error
;
3260 if (!i915
.enable_hangcheck
)
3263 /* Don't continually defer the hangcheck so that it is always run at
3264 * least once after work has been scheduled on any ring. Otherwise,
3265 * we will ignore a hung ring if a second ring is kept busy.
3268 queue_delayed_work(e
->hangcheck_wq
, &e
->hangcheck_work
,
3269 round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES
));
3272 static void ibx_irq_reset(struct drm_device
*dev
)
3274 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3276 if (HAS_PCH_NOP(dev
))
3279 GEN5_IRQ_RESET(SDE
);
3281 if (HAS_PCH_CPT(dev
) || HAS_PCH_LPT(dev
))
3282 I915_WRITE(SERR_INT
, 0xffffffff);
3286 * SDEIER is also touched by the interrupt handler to work around missed PCH
3287 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3288 * instead we unconditionally enable all PCH interrupt sources here, but then
3289 * only unmask them as needed with SDEIMR.
3291 * This function needs to be called before interrupts are enabled.
3293 static void ibx_irq_pre_postinstall(struct drm_device
*dev
)
3295 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3297 if (HAS_PCH_NOP(dev
))
3300 WARN_ON(I915_READ(SDEIER
) != 0);
3301 I915_WRITE(SDEIER
, 0xffffffff);
3302 POSTING_READ(SDEIER
);
3305 static void gen5_gt_irq_reset(struct drm_device
*dev
)
3307 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3310 if (INTEL_INFO(dev
)->gen
>= 6)
3311 GEN5_IRQ_RESET(GEN6_PM
);
3314 static void vlv_display_irq_reset(struct drm_i915_private
*dev_priv
)
3318 if (IS_CHERRYVIEW(dev_priv
))
3319 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK_CHV
);
3321 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
3323 i915_hotplug_interrupt_update_locked(dev_priv
, 0xffffffff, 0);
3324 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3326 for_each_pipe(dev_priv
, pipe
) {
3327 I915_WRITE(PIPESTAT(pipe
),
3328 PIPE_FIFO_UNDERRUN_STATUS
|
3329 PIPESTAT_INT_STATUS_MASK
);
3330 dev_priv
->pipestat_irq_mask
[pipe
] = 0;
3333 GEN5_IRQ_RESET(VLV_
);
3334 dev_priv
->irq_mask
= ~0;
3337 static void vlv_display_irq_postinstall(struct drm_i915_private
*dev_priv
)
3343 pipestat_mask
= PLANE_FLIP_DONE_INT_STATUS_VLV
|
3344 PIPE_CRC_DONE_INTERRUPT_STATUS
;
3346 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
3347 for_each_pipe(dev_priv
, pipe
)
3348 i915_enable_pipestat(dev_priv
, pipe
, pipestat_mask
);
3350 enable_mask
= I915_DISPLAY_PORT_INTERRUPT
|
3351 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3352 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
;
3353 if (IS_CHERRYVIEW(dev_priv
))
3354 enable_mask
|= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
;
3356 WARN_ON(dev_priv
->irq_mask
!= ~0);
3358 dev_priv
->irq_mask
= ~enable_mask
;
3360 GEN5_IRQ_INIT(VLV_
, dev_priv
->irq_mask
, enable_mask
);
3365 static void ironlake_irq_reset(struct drm_device
*dev
)
3367 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3369 I915_WRITE(HWSTAM
, 0xffffffff);
3373 I915_WRITE(GEN7_ERR_INT
, 0xffffffff);
3375 gen5_gt_irq_reset(dev
);
3380 static void valleyview_irq_preinstall(struct drm_device
*dev
)
3382 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3384 I915_WRITE(VLV_MASTER_IER
, 0);
3385 POSTING_READ(VLV_MASTER_IER
);
3387 gen5_gt_irq_reset(dev
);
3389 spin_lock_irq(&dev_priv
->irq_lock
);
3390 if (dev_priv
->display_irqs_enabled
)
3391 vlv_display_irq_reset(dev_priv
);
3392 spin_unlock_irq(&dev_priv
->irq_lock
);
3395 static void gen8_gt_irq_reset(struct drm_i915_private
*dev_priv
)
3397 GEN8_IRQ_RESET_NDX(GT
, 0);
3398 GEN8_IRQ_RESET_NDX(GT
, 1);
3399 GEN8_IRQ_RESET_NDX(GT
, 2);
3400 GEN8_IRQ_RESET_NDX(GT
, 3);
3403 static void gen8_irq_reset(struct drm_device
*dev
)
3405 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3408 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3409 POSTING_READ(GEN8_MASTER_IRQ
);
3411 gen8_gt_irq_reset(dev_priv
);
3413 for_each_pipe(dev_priv
, pipe
)
3414 if (intel_display_power_is_enabled(dev_priv
,
3415 POWER_DOMAIN_PIPE(pipe
)))
3416 GEN8_IRQ_RESET_NDX(DE_PIPE
, pipe
);
3418 GEN5_IRQ_RESET(GEN8_DE_PORT_
);
3419 GEN5_IRQ_RESET(GEN8_DE_MISC_
);
3420 GEN5_IRQ_RESET(GEN8_PCU_
);
3422 if (HAS_PCH_SPLIT(dev
))
3426 void gen8_irq_power_well_post_enable(struct drm_i915_private
*dev_priv
,
3427 unsigned int pipe_mask
)
3429 uint32_t extra_ier
= GEN8_PIPE_VBLANK
| GEN8_PIPE_FIFO_UNDERRUN
;
3432 spin_lock_irq(&dev_priv
->irq_lock
);
3433 for_each_pipe_masked(dev_priv
, pipe
, pipe_mask
)
3434 GEN8_IRQ_INIT_NDX(DE_PIPE
, pipe
,
3435 dev_priv
->de_irq_mask
[pipe
],
3436 ~dev_priv
->de_irq_mask
[pipe
] | extra_ier
);
3437 spin_unlock_irq(&dev_priv
->irq_lock
);
3440 void gen8_irq_power_well_pre_disable(struct drm_i915_private
*dev_priv
,
3441 unsigned int pipe_mask
)
3445 spin_lock_irq(&dev_priv
->irq_lock
);
3446 for_each_pipe_masked(dev_priv
, pipe
, pipe_mask
)
3447 GEN8_IRQ_RESET_NDX(DE_PIPE
, pipe
);
3448 spin_unlock_irq(&dev_priv
->irq_lock
);
3450 /* make sure we're done processing display irqs */
3451 synchronize_irq(dev_priv
->dev
->irq
);
3454 static void cherryview_irq_preinstall(struct drm_device
*dev
)
3456 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3458 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3459 POSTING_READ(GEN8_MASTER_IRQ
);
3461 gen8_gt_irq_reset(dev_priv
);
3463 GEN5_IRQ_RESET(GEN8_PCU_
);
3465 spin_lock_irq(&dev_priv
->irq_lock
);
3466 if (dev_priv
->display_irqs_enabled
)
3467 vlv_display_irq_reset(dev_priv
);
3468 spin_unlock_irq(&dev_priv
->irq_lock
);
3471 static u32
intel_hpd_enabled_irqs(struct drm_device
*dev
,
3472 const u32 hpd
[HPD_NUM_PINS
])
3474 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3475 struct intel_encoder
*encoder
;
3476 u32 enabled_irqs
= 0;
3478 for_each_intel_encoder(dev
, encoder
)
3479 if (dev_priv
->hotplug
.stats
[encoder
->hpd_pin
].state
== HPD_ENABLED
)
3480 enabled_irqs
|= hpd
[encoder
->hpd_pin
];
3482 return enabled_irqs
;
3485 static void ibx_hpd_irq_setup(struct drm_device
*dev
)
3487 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3488 u32 hotplug_irqs
, hotplug
, enabled_irqs
;
3490 if (HAS_PCH_IBX(dev
)) {
3491 hotplug_irqs
= SDE_HOTPLUG_MASK
;
3492 enabled_irqs
= intel_hpd_enabled_irqs(dev
, hpd_ibx
);
3494 hotplug_irqs
= SDE_HOTPLUG_MASK_CPT
;
3495 enabled_irqs
= intel_hpd_enabled_irqs(dev
, hpd_cpt
);
3498 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
3501 * Enable digital hotplug on the PCH, and configure the DP short pulse
3502 * duration to 2ms (which is the minimum in the Display Port spec).
3503 * The pulse duration bits are reserved on LPT+.
3505 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
3506 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
3507 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
3508 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
3509 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
3511 * When CPU and PCH are on the same package, port A
3512 * HPD must be enabled in both north and south.
3514 if (HAS_PCH_LPT_LP(dev
))
3515 hotplug
|= PORTA_HOTPLUG_ENABLE
;
3516 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
3519 static void spt_hpd_irq_setup(struct drm_device
*dev
)
3521 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3522 u32 hotplug_irqs
, hotplug
, enabled_irqs
;
3524 hotplug_irqs
= SDE_HOTPLUG_MASK_SPT
;
3525 enabled_irqs
= intel_hpd_enabled_irqs(dev
, hpd_spt
);
3527 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
3529 /* Enable digital hotplug on the PCH */
3530 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
3531 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTC_HOTPLUG_ENABLE
|
3532 PORTB_HOTPLUG_ENABLE
| PORTA_HOTPLUG_ENABLE
;
3533 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
3535 hotplug
= I915_READ(PCH_PORT_HOTPLUG2
);
3536 hotplug
|= PORTE_HOTPLUG_ENABLE
;
3537 I915_WRITE(PCH_PORT_HOTPLUG2
, hotplug
);
3540 static void ilk_hpd_irq_setup(struct drm_device
*dev
)
3542 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3543 u32 hotplug_irqs
, hotplug
, enabled_irqs
;
3545 if (INTEL_INFO(dev
)->gen
>= 8) {
3546 hotplug_irqs
= GEN8_PORT_DP_A_HOTPLUG
;
3547 enabled_irqs
= intel_hpd_enabled_irqs(dev
, hpd_bdw
);
3549 bdw_update_port_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3550 } else if (INTEL_INFO(dev
)->gen
>= 7) {
3551 hotplug_irqs
= DE_DP_A_HOTPLUG_IVB
;
3552 enabled_irqs
= intel_hpd_enabled_irqs(dev
, hpd_ivb
);
3554 ilk_update_display_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3556 hotplug_irqs
= DE_DP_A_HOTPLUG
;
3557 enabled_irqs
= intel_hpd_enabled_irqs(dev
, hpd_ilk
);
3559 ilk_update_display_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3563 * Enable digital hotplug on the CPU, and configure the DP short pulse
3564 * duration to 2ms (which is the minimum in the Display Port spec)
3565 * The pulse duration bits are reserved on HSW+.
3567 hotplug
= I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL
);
3568 hotplug
&= ~DIGITAL_PORTA_PULSE_DURATION_MASK
;
3569 hotplug
|= DIGITAL_PORTA_HOTPLUG_ENABLE
| DIGITAL_PORTA_PULSE_DURATION_2ms
;
3570 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL
, hotplug
);
3572 ibx_hpd_irq_setup(dev
);
3575 static void bxt_hpd_irq_setup(struct drm_device
*dev
)
3577 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3578 u32 hotplug_irqs
, hotplug
, enabled_irqs
;
3580 enabled_irqs
= intel_hpd_enabled_irqs(dev
, hpd_bxt
);
3581 hotplug_irqs
= BXT_DE_PORT_HOTPLUG_MASK
;
3583 bdw_update_port_irq(dev_priv
, hotplug_irqs
, enabled_irqs
);
3585 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
3586 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTB_HOTPLUG_ENABLE
|
3587 PORTA_HOTPLUG_ENABLE
;
3589 DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
3590 hotplug
, enabled_irqs
);
3591 hotplug
&= ~BXT_DDI_HPD_INVERT_MASK
;
3594 * For BXT invert bit has to be set based on AOB design
3595 * for HPD detection logic, update it based on VBT fields.
3598 if ((enabled_irqs
& BXT_DE_PORT_HP_DDIA
) &&
3599 intel_bios_is_port_hpd_inverted(dev_priv
, PORT_A
))
3600 hotplug
|= BXT_DDIA_HPD_INVERT
;
3601 if ((enabled_irqs
& BXT_DE_PORT_HP_DDIB
) &&
3602 intel_bios_is_port_hpd_inverted(dev_priv
, PORT_B
))
3603 hotplug
|= BXT_DDIB_HPD_INVERT
;
3604 if ((enabled_irqs
& BXT_DE_PORT_HP_DDIC
) &&
3605 intel_bios_is_port_hpd_inverted(dev_priv
, PORT_C
))
3606 hotplug
|= BXT_DDIC_HPD_INVERT
;
3608 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
3611 static void ibx_irq_postinstall(struct drm_device
*dev
)
3613 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3616 if (HAS_PCH_NOP(dev
))
3619 if (HAS_PCH_IBX(dev
))
3620 mask
= SDE_GMBUS
| SDE_AUX_MASK
| SDE_POISON
;
3622 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
;
3624 gen5_assert_iir_is_zero(dev_priv
, SDEIIR
);
3625 I915_WRITE(SDEIMR
, ~mask
);
3628 static void gen5_gt_irq_postinstall(struct drm_device
*dev
)
3630 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3631 u32 pm_irqs
, gt_irqs
;
3633 pm_irqs
= gt_irqs
= 0;
3635 dev_priv
->gt_irq_mask
= ~0;
3636 if (HAS_L3_DPF(dev
)) {
3637 /* L3 parity interrupt is always unmasked. */
3638 dev_priv
->gt_irq_mask
= ~GT_PARITY_ERROR(dev
);
3639 gt_irqs
|= GT_PARITY_ERROR(dev
);
3642 gt_irqs
|= GT_RENDER_USER_INTERRUPT
;
3644 gt_irqs
|= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
|
3645 ILK_BSD_USER_INTERRUPT
;
3647 gt_irqs
|= GT_BLT_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
;
3650 GEN5_IRQ_INIT(GT
, dev_priv
->gt_irq_mask
, gt_irqs
);
3652 if (INTEL_INFO(dev
)->gen
>= 6) {
3654 * RPS interrupts will get enabled/disabled on demand when RPS
3655 * itself is enabled/disabled.
3658 pm_irqs
|= PM_VEBOX_USER_INTERRUPT
;
3660 dev_priv
->pm_irq_mask
= 0xffffffff;
3661 GEN5_IRQ_INIT(GEN6_PM
, dev_priv
->pm_irq_mask
, pm_irqs
);
3665 static int ironlake_irq_postinstall(struct drm_device
*dev
)
3667 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3668 u32 display_mask
, extra_mask
;
3670 if (INTEL_INFO(dev
)->gen
>= 7) {
3671 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
|
3672 DE_PCH_EVENT_IVB
| DE_PLANEC_FLIP_DONE_IVB
|
3673 DE_PLANEB_FLIP_DONE_IVB
|
3674 DE_PLANEA_FLIP_DONE_IVB
| DE_AUX_CHANNEL_A_IVB
);
3675 extra_mask
= (DE_PIPEC_VBLANK_IVB
| DE_PIPEB_VBLANK_IVB
|
3676 DE_PIPEA_VBLANK_IVB
| DE_ERR_INT_IVB
|
3677 DE_DP_A_HOTPLUG_IVB
);
3679 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
3680 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
|
3682 DE_PIPEB_CRC_DONE
| DE_PIPEA_CRC_DONE
|
3684 extra_mask
= (DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
| DE_PCU_EVENT
|
3685 DE_PIPEB_FIFO_UNDERRUN
| DE_PIPEA_FIFO_UNDERRUN
|
3689 dev_priv
->irq_mask
= ~display_mask
;
3691 I915_WRITE(HWSTAM
, 0xeffe);
3693 ibx_irq_pre_postinstall(dev
);
3695 GEN5_IRQ_INIT(DE
, dev_priv
->irq_mask
, display_mask
| extra_mask
);
3697 gen5_gt_irq_postinstall(dev
);
3699 ibx_irq_postinstall(dev
);
3701 if (IS_IRONLAKE_M(dev
)) {
3702 /* Enable PCU event interrupts
3704 * spinlocking not required here for correctness since interrupt
3705 * setup is guaranteed to run in single-threaded context. But we
3706 * need it to make the assert_spin_locked happy. */
3707 spin_lock_irq(&dev_priv
->irq_lock
);
3708 ilk_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
3709 spin_unlock_irq(&dev_priv
->irq_lock
);
3715 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
)
3717 assert_spin_locked(&dev_priv
->irq_lock
);
3719 if (dev_priv
->display_irqs_enabled
)
3722 dev_priv
->display_irqs_enabled
= true;
3724 if (intel_irqs_enabled(dev_priv
)) {
3725 vlv_display_irq_reset(dev_priv
);
3726 vlv_display_irq_postinstall(dev_priv
);
3730 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
)
3732 assert_spin_locked(&dev_priv
->irq_lock
);
3734 if (!dev_priv
->display_irqs_enabled
)
3737 dev_priv
->display_irqs_enabled
= false;
3739 if (intel_irqs_enabled(dev_priv
))
3740 vlv_display_irq_reset(dev_priv
);
3744 static int valleyview_irq_postinstall(struct drm_device
*dev
)
3746 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3748 gen5_gt_irq_postinstall(dev
);
3750 spin_lock_irq(&dev_priv
->irq_lock
);
3751 if (dev_priv
->display_irqs_enabled
)
3752 vlv_display_irq_postinstall(dev_priv
);
3753 spin_unlock_irq(&dev_priv
->irq_lock
);
3755 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
3756 POSTING_READ(VLV_MASTER_IER
);
3761 static void gen8_gt_irq_postinstall(struct drm_i915_private
*dev_priv
)
3763 /* These are interrupts we'll toggle with the ring mask register */
3764 uint32_t gt_interrupts
[] = {
3765 GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
3766 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
3767 GT_RENDER_L3_PARITY_ERROR_INTERRUPT
|
3768 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
|
3769 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
,
3770 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
|
3771 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
|
3772 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
|
3773 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
,
3775 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
|
3776 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
3779 dev_priv
->pm_irq_mask
= 0xffffffff;
3780 GEN8_IRQ_INIT_NDX(GT
, 0, ~gt_interrupts
[0], gt_interrupts
[0]);
3781 GEN8_IRQ_INIT_NDX(GT
, 1, ~gt_interrupts
[1], gt_interrupts
[1]);
3783 * RPS interrupts will get enabled/disabled on demand when RPS itself
3784 * is enabled/disabled.
3786 GEN8_IRQ_INIT_NDX(GT
, 2, dev_priv
->pm_irq_mask
, 0);
3787 GEN8_IRQ_INIT_NDX(GT
, 3, ~gt_interrupts
[3], gt_interrupts
[3]);
3790 static void gen8_de_irq_postinstall(struct drm_i915_private
*dev_priv
)
3792 uint32_t de_pipe_masked
= GEN8_PIPE_CDCLK_CRC_DONE
;
3793 uint32_t de_pipe_enables
;
3794 u32 de_port_masked
= GEN8_AUX_CHANNEL_A
;
3795 u32 de_port_enables
;
3798 if (INTEL_INFO(dev_priv
)->gen
>= 9) {
3799 de_pipe_masked
|= GEN9_PIPE_PLANE1_FLIP_DONE
|
3800 GEN9_DE_PIPE_IRQ_FAULT_ERRORS
;
3801 de_port_masked
|= GEN9_AUX_CHANNEL_B
| GEN9_AUX_CHANNEL_C
|
3803 if (IS_BROXTON(dev_priv
))
3804 de_port_masked
|= BXT_DE_PORT_GMBUS
;
3806 de_pipe_masked
|= GEN8_PIPE_PRIMARY_FLIP_DONE
|
3807 GEN8_DE_PIPE_IRQ_FAULT_ERRORS
;
3810 de_pipe_enables
= de_pipe_masked
| GEN8_PIPE_VBLANK
|
3811 GEN8_PIPE_FIFO_UNDERRUN
;
3813 de_port_enables
= de_port_masked
;
3814 if (IS_BROXTON(dev_priv
))
3815 de_port_enables
|= BXT_DE_PORT_HOTPLUG_MASK
;
3816 else if (IS_BROADWELL(dev_priv
))
3817 de_port_enables
|= GEN8_PORT_DP_A_HOTPLUG
;
3819 dev_priv
->de_irq_mask
[PIPE_A
] = ~de_pipe_masked
;
3820 dev_priv
->de_irq_mask
[PIPE_B
] = ~de_pipe_masked
;
3821 dev_priv
->de_irq_mask
[PIPE_C
] = ~de_pipe_masked
;
3823 for_each_pipe(dev_priv
, pipe
)
3824 if (intel_display_power_is_enabled(dev_priv
,
3825 POWER_DOMAIN_PIPE(pipe
)))
3826 GEN8_IRQ_INIT_NDX(DE_PIPE
, pipe
,
3827 dev_priv
->de_irq_mask
[pipe
],
3830 GEN5_IRQ_INIT(GEN8_DE_PORT_
, ~de_port_masked
, de_port_enables
);
3833 static int gen8_irq_postinstall(struct drm_device
*dev
)
3835 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3837 if (HAS_PCH_SPLIT(dev
))
3838 ibx_irq_pre_postinstall(dev
);
3840 gen8_gt_irq_postinstall(dev_priv
);
3841 gen8_de_irq_postinstall(dev_priv
);
3843 if (HAS_PCH_SPLIT(dev
))
3844 ibx_irq_postinstall(dev
);
3846 I915_WRITE(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
3847 POSTING_READ(GEN8_MASTER_IRQ
);
3852 static int cherryview_irq_postinstall(struct drm_device
*dev
)
3854 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3856 gen8_gt_irq_postinstall(dev_priv
);
3858 spin_lock_irq(&dev_priv
->irq_lock
);
3859 if (dev_priv
->display_irqs_enabled
)
3860 vlv_display_irq_postinstall(dev_priv
);
3861 spin_unlock_irq(&dev_priv
->irq_lock
);
3863 I915_WRITE(GEN8_MASTER_IRQ
, GEN8_MASTER_IRQ_CONTROL
);
3864 POSTING_READ(GEN8_MASTER_IRQ
);
3869 static void gen8_irq_uninstall(struct drm_device
*dev
)
3871 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3876 gen8_irq_reset(dev
);
3879 static void valleyview_irq_uninstall(struct drm_device
*dev
)
3881 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3886 I915_WRITE(VLV_MASTER_IER
, 0);
3887 POSTING_READ(VLV_MASTER_IER
);
3889 gen5_gt_irq_reset(dev
);
3891 I915_WRITE(HWSTAM
, 0xffffffff);
3893 spin_lock_irq(&dev_priv
->irq_lock
);
3894 if (dev_priv
->display_irqs_enabled
)
3895 vlv_display_irq_reset(dev_priv
);
3896 spin_unlock_irq(&dev_priv
->irq_lock
);
3899 static void cherryview_irq_uninstall(struct drm_device
*dev
)
3901 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3906 I915_WRITE(GEN8_MASTER_IRQ
, 0);
3907 POSTING_READ(GEN8_MASTER_IRQ
);
3909 gen8_gt_irq_reset(dev_priv
);
3911 GEN5_IRQ_RESET(GEN8_PCU_
);
3913 spin_lock_irq(&dev_priv
->irq_lock
);
3914 if (dev_priv
->display_irqs_enabled
)
3915 vlv_display_irq_reset(dev_priv
);
3916 spin_unlock_irq(&dev_priv
->irq_lock
);
3919 static void ironlake_irq_uninstall(struct drm_device
*dev
)
3921 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3926 ironlake_irq_reset(dev
);
3929 static void i8xx_irq_preinstall(struct drm_device
* dev
)
3931 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3934 for_each_pipe(dev_priv
, pipe
)
3935 I915_WRITE(PIPESTAT(pipe
), 0);
3936 I915_WRITE16(IMR
, 0xffff);
3937 I915_WRITE16(IER
, 0x0);
3938 POSTING_READ16(IER
);
3941 static int i8xx_irq_postinstall(struct drm_device
*dev
)
3943 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3946 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
3948 /* Unmask the interrupts that we always want on. */
3949 dev_priv
->irq_mask
=
3950 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3951 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3952 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3953 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
3954 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
3957 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3958 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3959 I915_USER_INTERRUPT
);
3960 POSTING_READ16(IER
);
3962 /* Interrupt setup is already guaranteed to be single-threaded, this is
3963 * just to make the assert_spin_locked check happy. */
3964 spin_lock_irq(&dev_priv
->irq_lock
);
3965 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3966 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
3967 spin_unlock_irq(&dev_priv
->irq_lock
);
3973 * Returns true when a page flip has completed.
3975 static bool i8xx_handle_vblank(struct drm_device
*dev
,
3976 int plane
, int pipe
, u32 iir
)
3978 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3979 u16 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
3981 if (!intel_pipe_handle_vblank(dev
, pipe
))
3984 if ((iir
& flip_pending
) == 0)
3985 goto check_page_flip
;
3987 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3988 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3989 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3990 * the flip is completed (no longer pending). Since this doesn't raise
3991 * an interrupt per se, we watch for the change at vblank.
3993 if (I915_READ16(ISR
) & flip_pending
)
3994 goto check_page_flip
;
3996 intel_prepare_page_flip(dev
, plane
);
3997 intel_finish_page_flip(dev
, pipe
);
4001 intel_check_page_flip(dev
, pipe
);
4005 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
4007 struct drm_device
*dev
= arg
;
4008 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4013 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4014 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
4017 if (!intel_irqs_enabled(dev_priv
))
4020 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4021 disable_rpm_wakeref_asserts(dev_priv
);
4024 iir
= I915_READ16(IIR
);
4028 while (iir
& ~flip_mask
) {
4029 /* Can't rely on pipestat interrupt bit in iir as it might
4030 * have been cleared after the pipestat interrupt was received.
4031 * It doesn't set the bit in iir again, but it still produces
4032 * interrupts (for non-MSI).
4034 spin_lock(&dev_priv
->irq_lock
);
4035 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
4036 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir
);
4038 for_each_pipe(dev_priv
, pipe
) {
4039 i915_reg_t reg
= PIPESTAT(pipe
);
4040 pipe_stats
[pipe
] = I915_READ(reg
);
4043 * Clear the PIPE*STAT regs before the IIR
4045 if (pipe_stats
[pipe
] & 0x8000ffff)
4046 I915_WRITE(reg
, pipe_stats
[pipe
]);
4048 spin_unlock(&dev_priv
->irq_lock
);
4050 I915_WRITE16(IIR
, iir
& ~flip_mask
);
4051 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
4053 if (iir
& I915_USER_INTERRUPT
)
4054 notify_ring(&dev_priv
->engine
[RCS
]);
4056 for_each_pipe(dev_priv
, pipe
) {
4061 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
4062 i8xx_handle_vblank(dev
, plane
, pipe
, iir
))
4063 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
4065 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
4066 i9xx_pipe_crc_irq_handler(dev
, pipe
);
4068 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
4069 intel_cpu_fifo_underrun_irq_handler(dev_priv
,
4078 enable_rpm_wakeref_asserts(dev_priv
);
4083 static void i8xx_irq_uninstall(struct drm_device
* dev
)
4085 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4088 for_each_pipe(dev_priv
, pipe
) {
4089 /* Clear enable bits; then clear status bits */
4090 I915_WRITE(PIPESTAT(pipe
), 0);
4091 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
4093 I915_WRITE16(IMR
, 0xffff);
4094 I915_WRITE16(IER
, 0x0);
4095 I915_WRITE16(IIR
, I915_READ16(IIR
));
4098 static void i915_irq_preinstall(struct drm_device
* dev
)
4100 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4103 if (I915_HAS_HOTPLUG(dev
)) {
4104 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4105 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4108 I915_WRITE16(HWSTAM
, 0xeffe);
4109 for_each_pipe(dev_priv
, pipe
)
4110 I915_WRITE(PIPESTAT(pipe
), 0);
4111 I915_WRITE(IMR
, 0xffffffff);
4112 I915_WRITE(IER
, 0x0);
4116 static int i915_irq_postinstall(struct drm_device
*dev
)
4118 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4121 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
4123 /* Unmask the interrupts that we always want on. */
4124 dev_priv
->irq_mask
=
4125 ~(I915_ASLE_INTERRUPT
|
4126 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
4127 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
4128 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4129 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
4132 I915_ASLE_INTERRUPT
|
4133 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
4134 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
4135 I915_USER_INTERRUPT
;
4137 if (I915_HAS_HOTPLUG(dev
)) {
4138 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4139 POSTING_READ(PORT_HOTPLUG_EN
);
4141 /* Enable in IER... */
4142 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
4143 /* and unmask in IMR */
4144 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
4147 I915_WRITE(IMR
, dev_priv
->irq_mask
);
4148 I915_WRITE(IER
, enable_mask
);
4151 i915_enable_asle_pipestat(dev
);
4153 /* Interrupt setup is already guaranteed to be single-threaded, this is
4154 * just to make the assert_spin_locked check happy. */
4155 spin_lock_irq(&dev_priv
->irq_lock
);
4156 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4157 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4158 spin_unlock_irq(&dev_priv
->irq_lock
);
4164 * Returns true when a page flip has completed.
4166 static bool i915_handle_vblank(struct drm_device
*dev
,
4167 int plane
, int pipe
, u32 iir
)
4169 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4170 u32 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
4172 if (!intel_pipe_handle_vblank(dev
, pipe
))
4175 if ((iir
& flip_pending
) == 0)
4176 goto check_page_flip
;
4178 /* We detect FlipDone by looking for the change in PendingFlip from '1'
4179 * to '0' on the following vblank, i.e. IIR has the Pendingflip
4180 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
4181 * the flip is completed (no longer pending). Since this doesn't raise
4182 * an interrupt per se, we watch for the change at vblank.
4184 if (I915_READ(ISR
) & flip_pending
)
4185 goto check_page_flip
;
4187 intel_prepare_page_flip(dev
, plane
);
4188 intel_finish_page_flip(dev
, pipe
);
4192 intel_check_page_flip(dev
, pipe
);
4196 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
4198 struct drm_device
*dev
= arg
;
4199 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4200 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
4202 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4203 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
4204 int pipe
, ret
= IRQ_NONE
;
4206 if (!intel_irqs_enabled(dev_priv
))
4209 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4210 disable_rpm_wakeref_asserts(dev_priv
);
4212 iir
= I915_READ(IIR
);
4214 bool irq_received
= (iir
& ~flip_mask
) != 0;
4215 bool blc_event
= false;
4217 /* Can't rely on pipestat interrupt bit in iir as it might
4218 * have been cleared after the pipestat interrupt was received.
4219 * It doesn't set the bit in iir again, but it still produces
4220 * interrupts (for non-MSI).
4222 spin_lock(&dev_priv
->irq_lock
);
4223 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
4224 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir
);
4226 for_each_pipe(dev_priv
, pipe
) {
4227 i915_reg_t reg
= PIPESTAT(pipe
);
4228 pipe_stats
[pipe
] = I915_READ(reg
);
4230 /* Clear the PIPE*STAT regs before the IIR */
4231 if (pipe_stats
[pipe
] & 0x8000ffff) {
4232 I915_WRITE(reg
, pipe_stats
[pipe
]);
4233 irq_received
= true;
4236 spin_unlock(&dev_priv
->irq_lock
);
4241 /* Consume port. Then clear IIR or we'll miss events */
4242 if (I915_HAS_HOTPLUG(dev
) &&
4243 iir
& I915_DISPLAY_PORT_INTERRUPT
)
4244 i9xx_hpd_irq_handler(dev
);
4246 I915_WRITE(IIR
, iir
& ~flip_mask
);
4247 new_iir
= I915_READ(IIR
); /* Flush posted writes */
4249 if (iir
& I915_USER_INTERRUPT
)
4250 notify_ring(&dev_priv
->engine
[RCS
]);
4252 for_each_pipe(dev_priv
, pipe
) {
4257 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
4258 i915_handle_vblank(dev
, plane
, pipe
, iir
))
4259 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
4261 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
4264 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
4265 i9xx_pipe_crc_irq_handler(dev
, pipe
);
4267 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
4268 intel_cpu_fifo_underrun_irq_handler(dev_priv
,
4272 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
4273 intel_opregion_asle_intr(dev
);
4275 /* With MSI, interrupts are only generated when iir
4276 * transitions from zero to nonzero. If another bit got
4277 * set while we were handling the existing iir bits, then
4278 * we would never get another interrupt.
4280 * This is fine on non-MSI as well, as if we hit this path
4281 * we avoid exiting the interrupt handler only to generate
4284 * Note that for MSI this could cause a stray interrupt report
4285 * if an interrupt landed in the time between writing IIR and
4286 * the posting read. This should be rare enough to never
4287 * trigger the 99% of 100,000 interrupts test for disabling
4292 } while (iir
& ~flip_mask
);
4294 enable_rpm_wakeref_asserts(dev_priv
);
4299 static void i915_irq_uninstall(struct drm_device
* dev
)
4301 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4304 if (I915_HAS_HOTPLUG(dev
)) {
4305 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4306 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4309 I915_WRITE16(HWSTAM
, 0xffff);
4310 for_each_pipe(dev_priv
, pipe
) {
4311 /* Clear enable bits; then clear status bits */
4312 I915_WRITE(PIPESTAT(pipe
), 0);
4313 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
4315 I915_WRITE(IMR
, 0xffffffff);
4316 I915_WRITE(IER
, 0x0);
4318 I915_WRITE(IIR
, I915_READ(IIR
));
4321 static void i965_irq_preinstall(struct drm_device
* dev
)
4323 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4326 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4327 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4329 I915_WRITE(HWSTAM
, 0xeffe);
4330 for_each_pipe(dev_priv
, pipe
)
4331 I915_WRITE(PIPESTAT(pipe
), 0);
4332 I915_WRITE(IMR
, 0xffffffff);
4333 I915_WRITE(IER
, 0x0);
4337 static int i965_irq_postinstall(struct drm_device
*dev
)
4339 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4343 /* Unmask the interrupts that we always want on. */
4344 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
4345 I915_DISPLAY_PORT_INTERRUPT
|
4346 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
4347 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
4348 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4349 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
4350 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
4352 enable_mask
= ~dev_priv
->irq_mask
;
4353 enable_mask
&= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4354 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
4355 enable_mask
|= I915_USER_INTERRUPT
;
4358 enable_mask
|= I915_BSD_USER_INTERRUPT
;
4360 /* Interrupt setup is already guaranteed to be single-threaded, this is
4361 * just to make the assert_spin_locked check happy. */
4362 spin_lock_irq(&dev_priv
->irq_lock
);
4363 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_GMBUS_INTERRUPT_STATUS
);
4364 i915_enable_pipestat(dev_priv
, PIPE_A
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4365 i915_enable_pipestat(dev_priv
, PIPE_B
, PIPE_CRC_DONE_INTERRUPT_STATUS
);
4366 spin_unlock_irq(&dev_priv
->irq_lock
);
4369 * Enable some error detection, note the instruction error mask
4370 * bit is reserved, so we leave it masked.
4373 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
4374 GM45_ERROR_MEM_PRIV
|
4375 GM45_ERROR_CP_PRIV
|
4376 I915_ERROR_MEMORY_REFRESH
);
4378 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
4379 I915_ERROR_MEMORY_REFRESH
);
4381 I915_WRITE(EMR
, error_mask
);
4383 I915_WRITE(IMR
, dev_priv
->irq_mask
);
4384 I915_WRITE(IER
, enable_mask
);
4387 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4388 POSTING_READ(PORT_HOTPLUG_EN
);
4390 i915_enable_asle_pipestat(dev
);
4395 static void i915_hpd_irq_setup(struct drm_device
*dev
)
4397 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4400 assert_spin_locked(&dev_priv
->irq_lock
);
4402 /* Note HDMI and DP share hotplug bits */
4403 /* enable bits are the same for all generations */
4404 hotplug_en
= intel_hpd_enabled_irqs(dev
, hpd_mask_i915
);
4405 /* Programming the CRT detection parameters tends
4406 to generate a spurious hotplug event about three
4407 seconds later. So just do it once.
4410 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
4411 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
4413 /* Ignore TV since it's buggy */
4414 i915_hotplug_interrupt_update_locked(dev_priv
,
4415 HOTPLUG_INT_EN_MASK
|
4416 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK
|
4417 CRT_HOTPLUG_ACTIVATION_PERIOD_64
,
4421 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
4423 struct drm_device
*dev
= arg
;
4424 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4426 u32 pipe_stats
[I915_MAX_PIPES
];
4427 int ret
= IRQ_NONE
, pipe
;
4429 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
4430 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
4432 if (!intel_irqs_enabled(dev_priv
))
4435 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4436 disable_rpm_wakeref_asserts(dev_priv
);
4438 iir
= I915_READ(IIR
);
4441 bool irq_received
= (iir
& ~flip_mask
) != 0;
4442 bool blc_event
= false;
4444 /* Can't rely on pipestat interrupt bit in iir as it might
4445 * have been cleared after the pipestat interrupt was received.
4446 * It doesn't set the bit in iir again, but it still produces
4447 * interrupts (for non-MSI).
4449 spin_lock(&dev_priv
->irq_lock
);
4450 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
4451 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir
);
4453 for_each_pipe(dev_priv
, pipe
) {
4454 i915_reg_t reg
= PIPESTAT(pipe
);
4455 pipe_stats
[pipe
] = I915_READ(reg
);
4458 * Clear the PIPE*STAT regs before the IIR
4460 if (pipe_stats
[pipe
] & 0x8000ffff) {
4461 I915_WRITE(reg
, pipe_stats
[pipe
]);
4462 irq_received
= true;
4465 spin_unlock(&dev_priv
->irq_lock
);
4472 /* Consume port. Then clear IIR or we'll miss events */
4473 if (iir
& I915_DISPLAY_PORT_INTERRUPT
)
4474 i9xx_hpd_irq_handler(dev
);
4476 I915_WRITE(IIR
, iir
& ~flip_mask
);
4477 new_iir
= I915_READ(IIR
); /* Flush posted writes */
4479 if (iir
& I915_USER_INTERRUPT
)
4480 notify_ring(&dev_priv
->engine
[RCS
]);
4481 if (iir
& I915_BSD_USER_INTERRUPT
)
4482 notify_ring(&dev_priv
->engine
[VCS
]);
4484 for_each_pipe(dev_priv
, pipe
) {
4485 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
4486 i915_handle_vblank(dev
, pipe
, pipe
, iir
))
4487 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
4489 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
4492 if (pipe_stats
[pipe
] & PIPE_CRC_DONE_INTERRUPT_STATUS
)
4493 i9xx_pipe_crc_irq_handler(dev
, pipe
);
4495 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
4496 intel_cpu_fifo_underrun_irq_handler(dev_priv
, pipe
);
4499 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
4500 intel_opregion_asle_intr(dev
);
4502 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
4503 gmbus_irq_handler(dev
);
4505 /* With MSI, interrupts are only generated when iir
4506 * transitions from zero to nonzero. If another bit got
4507 * set while we were handling the existing iir bits, then
4508 * we would never get another interrupt.
4510 * This is fine on non-MSI as well, as if we hit this path
4511 * we avoid exiting the interrupt handler only to generate
4514 * Note that for MSI this could cause a stray interrupt report
4515 * if an interrupt landed in the time between writing IIR and
4516 * the posting read. This should be rare enough to never
4517 * trigger the 99% of 100,000 interrupts test for disabling
4523 enable_rpm_wakeref_asserts(dev_priv
);
4528 static void i965_irq_uninstall(struct drm_device
* dev
)
4530 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4536 i915_hotplug_interrupt_update(dev_priv
, 0xffffffff, 0);
4537 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
4539 I915_WRITE(HWSTAM
, 0xffffffff);
4540 for_each_pipe(dev_priv
, pipe
)
4541 I915_WRITE(PIPESTAT(pipe
), 0);
4542 I915_WRITE(IMR
, 0xffffffff);
4543 I915_WRITE(IER
, 0x0);
4545 for_each_pipe(dev_priv
, pipe
)
4546 I915_WRITE(PIPESTAT(pipe
),
4547 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
4548 I915_WRITE(IIR
, I915_READ(IIR
));
4552 * intel_irq_init - initializes irq support
4553 * @dev_priv: i915 device instance
4555 * This function initializes all the irq support including work items, timers
4556 * and all the vtables. It does not setup the interrupt itself though.
4558 void intel_irq_init(struct drm_i915_private
*dev_priv
)
4560 struct drm_device
*dev
= dev_priv
->dev
;
4562 intel_hpd_init_work(dev_priv
);
4564 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
4565 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
4567 /* Let's track the enabled rps events */
4568 if (IS_VALLEYVIEW(dev_priv
))
4569 /* WaGsvRC0ResidencyMethod:vlv */
4570 dev_priv
->pm_rps_events
= GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_UP_EI_EXPIRED
;
4572 dev_priv
->pm_rps_events
= GEN6_PM_RPS_EVENTS
;
4574 INIT_DELAYED_WORK(&dev_priv
->gpu_error
.hangcheck_work
,
4575 i915_hangcheck_elapsed
);
4577 if (IS_GEN2(dev_priv
)) {
4578 dev
->max_vblank_count
= 0;
4579 dev
->driver
->get_vblank_counter
= i8xx_get_vblank_counter
;
4580 } else if (IS_G4X(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 5) {
4581 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
4582 dev
->driver
->get_vblank_counter
= g4x_get_vblank_counter
;
4584 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
4585 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
4589 * Opt out of the vblank disable timer on everything except gen2.
4590 * Gen2 doesn't have a hardware frame counter and so depends on
4591 * vblank interrupts to produce sane vblank seuquence numbers.
4593 if (!IS_GEN2(dev_priv
))
4594 dev
->vblank_disable_immediate
= true;
4596 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
4597 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
4599 if (IS_CHERRYVIEW(dev_priv
)) {
4600 dev
->driver
->irq_handler
= cherryview_irq_handler
;
4601 dev
->driver
->irq_preinstall
= cherryview_irq_preinstall
;
4602 dev
->driver
->irq_postinstall
= cherryview_irq_postinstall
;
4603 dev
->driver
->irq_uninstall
= cherryview_irq_uninstall
;
4604 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
4605 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
4606 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4607 } else if (IS_VALLEYVIEW(dev_priv
)) {
4608 dev
->driver
->irq_handler
= valleyview_irq_handler
;
4609 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
4610 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
4611 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
4612 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
4613 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
4614 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4615 } else if (INTEL_INFO(dev_priv
)->gen
>= 8) {
4616 dev
->driver
->irq_handler
= gen8_irq_handler
;
4617 dev
->driver
->irq_preinstall
= gen8_irq_reset
;
4618 dev
->driver
->irq_postinstall
= gen8_irq_postinstall
;
4619 dev
->driver
->irq_uninstall
= gen8_irq_uninstall
;
4620 dev
->driver
->enable_vblank
= gen8_enable_vblank
;
4621 dev
->driver
->disable_vblank
= gen8_disable_vblank
;
4622 if (IS_BROXTON(dev
))
4623 dev_priv
->display
.hpd_irq_setup
= bxt_hpd_irq_setup
;
4624 else if (HAS_PCH_SPT(dev
))
4625 dev_priv
->display
.hpd_irq_setup
= spt_hpd_irq_setup
;
4627 dev_priv
->display
.hpd_irq_setup
= ilk_hpd_irq_setup
;
4628 } else if (HAS_PCH_SPLIT(dev
)) {
4629 dev
->driver
->irq_handler
= ironlake_irq_handler
;
4630 dev
->driver
->irq_preinstall
= ironlake_irq_reset
;
4631 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
4632 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
4633 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
4634 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
4635 dev_priv
->display
.hpd_irq_setup
= ilk_hpd_irq_setup
;
4637 if (INTEL_INFO(dev_priv
)->gen
== 2) {
4638 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
4639 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
4640 dev
->driver
->irq_handler
= i8xx_irq_handler
;
4641 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
4642 } else if (INTEL_INFO(dev_priv
)->gen
== 3) {
4643 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
4644 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
4645 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
4646 dev
->driver
->irq_handler
= i915_irq_handler
;
4648 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
4649 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
4650 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
4651 dev
->driver
->irq_handler
= i965_irq_handler
;
4653 if (I915_HAS_HOTPLUG(dev_priv
))
4654 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
4655 dev
->driver
->enable_vblank
= i915_enable_vblank
;
4656 dev
->driver
->disable_vblank
= i915_disable_vblank
;
4661 * intel_irq_install - enables the hardware interrupt
4662 * @dev_priv: i915 device instance
4664 * This function enables the hardware interrupt handling, but leaves the hotplug
4665 * handling still disabled. It is called after intel_irq_init().
4667 * In the driver load and resume code we need working interrupts in a few places
4668 * but don't want to deal with the hassle of concurrent probe and hotplug
4669 * workers. Hence the split into this two-stage approach.
4671 int intel_irq_install(struct drm_i915_private
*dev_priv
)
4674 * We enable some interrupt sources in our postinstall hooks, so mark
4675 * interrupts as enabled _before_ actually enabling them to avoid
4676 * special cases in our ordering checks.
4678 dev_priv
->pm
.irqs_enabled
= true;
4680 return drm_irq_install(dev_priv
->dev
, dev_priv
->dev
->pdev
->irq
);
4684 * intel_irq_uninstall - finilizes all irq handling
4685 * @dev_priv: i915 device instance
4687 * This stops interrupt and hotplug handling and unregisters and frees all
4688 * resources acquired in the init functions.
4690 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
)
4692 drm_irq_uninstall(dev_priv
->dev
);
4693 intel_hpd_cancel_work(dev_priv
);
4694 dev_priv
->pm
.irqs_enabled
= false;
4698 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4699 * @dev_priv: i915 device instance
4701 * This function is used to disable interrupts at runtime, both in the runtime
4702 * pm and the system suspend/resume code.
4704 void intel_runtime_pm_disable_interrupts(struct drm_i915_private
*dev_priv
)
4706 dev_priv
->dev
->driver
->irq_uninstall(dev_priv
->dev
);
4707 dev_priv
->pm
.irqs_enabled
= false;
4708 synchronize_irq(dev_priv
->dev
->irq
);
4712 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4713 * @dev_priv: i915 device instance
4715 * This function is used to enable interrupts at runtime, both in the runtime
4716 * pm and the system suspend/resume code.
4718 void intel_runtime_pm_enable_interrupts(struct drm_i915_private
*dev_priv
)
4720 dev_priv
->pm
.irqs_enabled
= true;
4721 dev_priv
->dev
->driver
->irq_preinstall(dev_priv
->dev
);
4722 dev_priv
->dev
->driver
->irq_postinstall(dev_priv
->dev
);