1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
34 #include <drm/i915_drm.h>
36 #include "i915_trace.h"
37 #include "intel_drv.h"
39 static const u32 hpd_ibx
[] = {
40 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
41 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
42 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
43 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
44 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
47 static const u32 hpd_cpt
[] = {
48 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
49 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG_CPT
,
50 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
51 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
52 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
55 static const u32 hpd_mask_i915
[] = {
56 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
57 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
58 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
59 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
60 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
61 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
64 static const u32 hpd_status_gen4
[] = {
65 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
66 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
67 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
68 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
69 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
70 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
73 static const u32 hpd_status_i915
[] = { /* i915 and valleyview are the same */
74 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
75 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
76 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
77 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
78 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
79 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
82 /* For display hotplug interrupt */
84 ironlake_enable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
86 assert_spin_locked(&dev_priv
->irq_lock
);
88 if ((dev_priv
->irq_mask
& mask
) != 0) {
89 dev_priv
->irq_mask
&= ~mask
;
90 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
96 ironlake_disable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
98 assert_spin_locked(&dev_priv
->irq_lock
);
100 if ((dev_priv
->irq_mask
& mask
) != mask
) {
101 dev_priv
->irq_mask
|= mask
;
102 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
107 static bool ivb_can_enable_err_int(struct drm_device
*dev
)
109 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
110 struct intel_crtc
*crtc
;
113 assert_spin_locked(&dev_priv
->irq_lock
);
115 for_each_pipe(pipe
) {
116 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
118 if (crtc
->cpu_fifo_underrun_disabled
)
125 static bool cpt_can_enable_serr_int(struct drm_device
*dev
)
127 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
129 struct intel_crtc
*crtc
;
131 assert_spin_locked(&dev_priv
->irq_lock
);
133 for_each_pipe(pipe
) {
134 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
136 if (crtc
->pch_fifo_underrun_disabled
)
143 static void ironlake_set_fifo_underrun_reporting(struct drm_device
*dev
,
144 enum pipe pipe
, bool enable
)
146 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
147 uint32_t bit
= (pipe
== PIPE_A
) ? DE_PIPEA_FIFO_UNDERRUN
:
148 DE_PIPEB_FIFO_UNDERRUN
;
151 ironlake_enable_display_irq(dev_priv
, bit
);
153 ironlake_disable_display_irq(dev_priv
, bit
);
156 static void ivybridge_set_fifo_underrun_reporting(struct drm_device
*dev
,
157 enum pipe pipe
, bool enable
)
159 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
161 I915_WRITE(GEN7_ERR_INT
, ERR_INT_FIFO_UNDERRUN(pipe
));
163 if (!ivb_can_enable_err_int(dev
))
166 ironlake_enable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
168 bool was_enabled
= !(I915_READ(DEIMR
) & DE_ERR_INT_IVB
);
170 /* Change the state _after_ we've read out the current one. */
171 ironlake_disable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
174 (I915_READ(GEN7_ERR_INT
) & ERR_INT_FIFO_UNDERRUN(pipe
))) {
175 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
182 * ibx_display_interrupt_update - update SDEIMR
183 * @dev_priv: driver private
184 * @interrupt_mask: mask of interrupt bits to update
185 * @enabled_irq_mask: mask of interrupt bits to enable
187 static void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
188 uint32_t interrupt_mask
,
189 uint32_t enabled_irq_mask
)
191 uint32_t sdeimr
= I915_READ(SDEIMR
);
192 sdeimr
&= ~interrupt_mask
;
193 sdeimr
|= (~enabled_irq_mask
& interrupt_mask
);
195 assert_spin_locked(&dev_priv
->irq_lock
);
197 I915_WRITE(SDEIMR
, sdeimr
);
198 POSTING_READ(SDEIMR
);
200 #define ibx_enable_display_interrupt(dev_priv, bits) \
201 ibx_display_interrupt_update((dev_priv), (bits), (bits))
202 #define ibx_disable_display_interrupt(dev_priv, bits) \
203 ibx_display_interrupt_update((dev_priv), (bits), 0)
205 static void ibx_set_fifo_underrun_reporting(struct drm_device
*dev
,
206 enum transcoder pch_transcoder
,
209 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
210 uint32_t bit
= (pch_transcoder
== TRANSCODER_A
) ?
211 SDE_TRANSA_FIFO_UNDER
: SDE_TRANSB_FIFO_UNDER
;
214 ibx_enable_display_interrupt(dev_priv
, bit
);
216 ibx_disable_display_interrupt(dev_priv
, bit
);
219 static void cpt_set_fifo_underrun_reporting(struct drm_device
*dev
,
220 enum transcoder pch_transcoder
,
223 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
227 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
));
229 if (!cpt_can_enable_serr_int(dev
))
232 ibx_enable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
234 uint32_t tmp
= I915_READ(SERR_INT
);
235 bool was_enabled
= !(I915_READ(SDEIMR
) & SDE_ERROR_CPT
);
237 /* Change the state _after_ we've read out the current one. */
238 ibx_disable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
241 (tmp
& SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
))) {
242 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
243 transcoder_name(pch_transcoder
));
249 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
252 * @enable: true if we want to report FIFO underrun errors, false otherwise
254 * This function makes us disable or enable CPU fifo underruns for a specific
255 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
256 * reporting for one pipe may also disable all the other CPU error interruts for
257 * the other pipes, due to the fact that there's just one interrupt mask/enable
258 * bit for all the pipes.
260 * Returns the previous state of underrun reporting.
262 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device
*dev
,
263 enum pipe pipe
, bool enable
)
265 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
266 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
267 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
271 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
273 ret
= !intel_crtc
->cpu_fifo_underrun_disabled
;
278 intel_crtc
->cpu_fifo_underrun_disabled
= !enable
;
280 if (IS_GEN5(dev
) || IS_GEN6(dev
))
281 ironlake_set_fifo_underrun_reporting(dev
, pipe
, enable
);
282 else if (IS_GEN7(dev
))
283 ivybridge_set_fifo_underrun_reporting(dev
, pipe
, enable
);
286 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
291 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
293 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
294 * @enable: true if we want to report FIFO underrun errors, false otherwise
296 * This function makes us disable or enable PCH fifo underruns for a specific
297 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
298 * underrun reporting for one transcoder may also disable all the other PCH
299 * error interruts for the other transcoders, due to the fact that there's just
300 * one interrupt mask/enable bit for all the transcoders.
302 * Returns the previous state of underrun reporting.
304 bool intel_set_pch_fifo_underrun_reporting(struct drm_device
*dev
,
305 enum transcoder pch_transcoder
,
308 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
309 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pch_transcoder
];
310 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
315 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
316 * has only one pch transcoder A that all pipes can use. To avoid racy
317 * pch transcoder -> pipe lookups from interrupt code simply store the
318 * underrun statistics in crtc A. Since we never expose this anywhere
319 * nor use it outside of the fifo underrun code here using the "wrong"
320 * crtc on LPT won't cause issues.
323 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
325 ret
= !intel_crtc
->pch_fifo_underrun_disabled
;
330 intel_crtc
->pch_fifo_underrun_disabled
= !enable
;
332 if (HAS_PCH_IBX(dev
))
333 ibx_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
335 cpt_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
338 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
344 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
346 u32 reg
= PIPESTAT(pipe
);
347 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
349 assert_spin_locked(&dev_priv
->irq_lock
);
351 if ((pipestat
& mask
) == mask
)
354 /* Enable the interrupt, clear any pending status */
355 pipestat
|= mask
| (mask
>> 16);
356 I915_WRITE(reg
, pipestat
);
361 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
363 u32 reg
= PIPESTAT(pipe
);
364 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
366 assert_spin_locked(&dev_priv
->irq_lock
);
368 if ((pipestat
& mask
) == 0)
372 I915_WRITE(reg
, pipestat
);
377 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
379 static void i915_enable_asle_pipestat(struct drm_device
*dev
)
381 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
382 unsigned long irqflags
;
384 if (!dev_priv
->opregion
.asle
|| !IS_MOBILE(dev
))
387 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
389 i915_enable_pipestat(dev_priv
, 1, PIPE_LEGACY_BLC_EVENT_ENABLE
);
390 if (INTEL_INFO(dev
)->gen
>= 4)
391 i915_enable_pipestat(dev_priv
, 0, PIPE_LEGACY_BLC_EVENT_ENABLE
);
393 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
397 * i915_pipe_enabled - check if a pipe is enabled
399 * @pipe: pipe to check
401 * Reading certain registers when the pipe is disabled can hang the chip.
402 * Use this routine to make sure the PLL is running and the pipe is active
403 * before reading such registers if unsure.
406 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
408 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
410 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
411 /* Locking is horribly broken here, but whatever. */
412 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
413 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
415 return intel_crtc
->active
;
417 return I915_READ(PIPECONF(pipe
)) & PIPECONF_ENABLE
;
421 /* Called from drm generic code, passed a 'crtc', which
422 * we use as a pipe index
424 static u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
426 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
427 unsigned long high_frame
;
428 unsigned long low_frame
;
429 u32 high1
, high2
, low
;
431 if (!i915_pipe_enabled(dev
, pipe
)) {
432 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
433 "pipe %c\n", pipe_name(pipe
));
437 high_frame
= PIPEFRAME(pipe
);
438 low_frame
= PIPEFRAMEPIXEL(pipe
);
441 * High & low register fields aren't synchronized, so make sure
442 * we get a low value that's stable across two reads of the high
446 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
447 low
= I915_READ(low_frame
) & PIPE_FRAME_LOW_MASK
;
448 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
449 } while (high1
!= high2
);
451 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
452 low
>>= PIPE_FRAME_LOW_SHIFT
;
453 return (high1
<< 8) | low
;
456 static u32
gm45_get_vblank_counter(struct drm_device
*dev
, int pipe
)
458 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
459 int reg
= PIPE_FRMCOUNT_GM45(pipe
);
461 if (!i915_pipe_enabled(dev
, pipe
)) {
462 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
463 "pipe %c\n", pipe_name(pipe
));
467 return I915_READ(reg
);
470 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, int pipe
,
471 int *vpos
, int *hpos
)
473 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
474 u32 vbl
= 0, position
= 0;
475 int vbl_start
, vbl_end
, htotal
, vtotal
;
478 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
481 if (!i915_pipe_enabled(dev
, pipe
)) {
482 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
483 "pipe %c\n", pipe_name(pipe
));
488 vtotal
= 1 + ((I915_READ(VTOTAL(cpu_transcoder
)) >> 16) & 0x1fff);
490 if (INTEL_INFO(dev
)->gen
>= 4) {
491 /* No obvious pixelcount register. Only query vertical
492 * scanout position from Display scan line register.
494 position
= I915_READ(PIPEDSL(pipe
));
496 /* Decode into vertical scanout position. Don't have
497 * horizontal scanout position.
499 *vpos
= position
& 0x1fff;
502 /* Have access to pixelcount since start of frame.
503 * We can split this into vertical and horizontal
506 position
= (I915_READ(PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
508 htotal
= 1 + ((I915_READ(HTOTAL(cpu_transcoder
)) >> 16) & 0x1fff);
509 *vpos
= position
/ htotal
;
510 *hpos
= position
- (*vpos
* htotal
);
513 /* Query vblank area. */
514 vbl
= I915_READ(VBLANK(cpu_transcoder
));
516 /* Test position against vblank region. */
517 vbl_start
= vbl
& 0x1fff;
518 vbl_end
= (vbl
>> 16) & 0x1fff;
520 if ((*vpos
< vbl_start
) || (*vpos
> vbl_end
))
523 /* Inside "upper part" of vblank area? Apply corrective offset: */
524 if (in_vbl
&& (*vpos
>= vbl_start
))
525 *vpos
= *vpos
- vtotal
;
527 /* Readouts valid? */
529 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
533 ret
|= DRM_SCANOUTPOS_INVBL
;
538 static int i915_get_vblank_timestamp(struct drm_device
*dev
, int pipe
,
540 struct timeval
*vblank_time
,
543 struct drm_crtc
*crtc
;
545 if (pipe
< 0 || pipe
>= INTEL_INFO(dev
)->num_pipes
) {
546 DRM_ERROR("Invalid crtc %d\n", pipe
);
550 /* Get drm_crtc to timestamp: */
551 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
553 DRM_ERROR("Invalid crtc %d\n", pipe
);
557 if (!crtc
->enabled
) {
558 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
562 /* Helper routine in DRM core does all the work: */
563 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
568 static int intel_hpd_irq_event(struct drm_device
*dev
, struct drm_connector
*connector
)
570 enum drm_connector_status old_status
;
572 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
573 old_status
= connector
->status
;
575 connector
->status
= connector
->funcs
->detect(connector
, false);
576 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
578 drm_get_connector_name(connector
),
579 old_status
, connector
->status
);
580 return (old_status
!= connector
->status
);
584 * Handle hotplug events outside the interrupt handler proper.
586 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
588 static void i915_hotplug_work_func(struct work_struct
*work
)
590 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
592 struct drm_device
*dev
= dev_priv
->dev
;
593 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
594 struct intel_connector
*intel_connector
;
595 struct intel_encoder
*intel_encoder
;
596 struct drm_connector
*connector
;
597 unsigned long irqflags
;
598 bool hpd_disabled
= false;
599 bool changed
= false;
602 /* HPD irq before everything is fully set up. */
603 if (!dev_priv
->enable_hotplug_processing
)
606 mutex_lock(&mode_config
->mutex
);
607 DRM_DEBUG_KMS("running encoder hotplug functions\n");
609 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
611 hpd_event_bits
= dev_priv
->hpd_event_bits
;
612 dev_priv
->hpd_event_bits
= 0;
613 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
614 intel_connector
= to_intel_connector(connector
);
615 intel_encoder
= intel_connector
->encoder
;
616 if (intel_encoder
->hpd_pin
> HPD_NONE
&&
617 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_MARK_DISABLED
&&
618 connector
->polled
== DRM_CONNECTOR_POLL_HPD
) {
619 DRM_INFO("HPD interrupt storm detected on connector %s: "
620 "switching from hotplug detection to polling\n",
621 drm_get_connector_name(connector
));
622 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
= HPD_DISABLED
;
623 connector
->polled
= DRM_CONNECTOR_POLL_CONNECT
624 | DRM_CONNECTOR_POLL_DISCONNECT
;
627 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
628 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
629 drm_get_connector_name(connector
), intel_encoder
->hpd_pin
);
632 /* if there were no outputs to poll, poll was disabled,
633 * therefore make sure it's enabled when disabling HPD on
636 drm_kms_helper_poll_enable(dev
);
637 mod_timer(&dev_priv
->hotplug_reenable_timer
,
638 jiffies
+ msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY
));
641 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
643 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
644 intel_connector
= to_intel_connector(connector
);
645 intel_encoder
= intel_connector
->encoder
;
646 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
647 if (intel_encoder
->hot_plug
)
648 intel_encoder
->hot_plug(intel_encoder
);
649 if (intel_hpd_irq_event(dev
, connector
))
653 mutex_unlock(&mode_config
->mutex
);
656 drm_kms_helper_hotplug_event(dev
);
659 static void ironlake_rps_change_irq_handler(struct drm_device
*dev
)
661 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
662 u32 busy_up
, busy_down
, max_avg
, min_avg
;
665 spin_lock(&mchdev_lock
);
667 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
669 new_delay
= dev_priv
->ips
.cur_delay
;
671 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
672 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
673 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
674 max_avg
= I915_READ(RCBMAXAVG
);
675 min_avg
= I915_READ(RCBMINAVG
);
677 /* Handle RCS change request from hw */
678 if (busy_up
> max_avg
) {
679 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
680 new_delay
= dev_priv
->ips
.cur_delay
- 1;
681 if (new_delay
< dev_priv
->ips
.max_delay
)
682 new_delay
= dev_priv
->ips
.max_delay
;
683 } else if (busy_down
< min_avg
) {
684 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
685 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
686 if (new_delay
> dev_priv
->ips
.min_delay
)
687 new_delay
= dev_priv
->ips
.min_delay
;
690 if (ironlake_set_drps(dev
, new_delay
))
691 dev_priv
->ips
.cur_delay
= new_delay
;
693 spin_unlock(&mchdev_lock
);
698 static void notify_ring(struct drm_device
*dev
,
699 struct intel_ring_buffer
*ring
)
701 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
703 if (ring
->obj
== NULL
)
706 trace_i915_gem_request_complete(ring
, ring
->get_seqno(ring
, false));
708 wake_up_all(&ring
->irq_queue
);
709 if (i915_enable_hangcheck
) {
710 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
711 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
715 static void gen6_pm_rps_work(struct work_struct
*work
)
717 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
722 spin_lock_irq(&dev_priv
->rps
.lock
);
723 pm_iir
= dev_priv
->rps
.pm_iir
;
724 dev_priv
->rps
.pm_iir
= 0;
725 pm_imr
= I915_READ(GEN6_PMIMR
);
726 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
727 I915_WRITE(GEN6_PMIMR
, pm_imr
& ~GEN6_PM_RPS_EVENTS
);
728 spin_unlock_irq(&dev_priv
->rps
.lock
);
730 if ((pm_iir
& GEN6_PM_RPS_EVENTS
) == 0)
733 mutex_lock(&dev_priv
->rps
.hw_lock
);
735 if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
) {
736 new_delay
= dev_priv
->rps
.cur_delay
+ 1;
739 * For better performance, jump directly
740 * to RPe if we're below it.
742 if (IS_VALLEYVIEW(dev_priv
->dev
) &&
743 dev_priv
->rps
.cur_delay
< dev_priv
->rps
.rpe_delay
)
744 new_delay
= dev_priv
->rps
.rpe_delay
;
746 new_delay
= dev_priv
->rps
.cur_delay
- 1;
748 /* sysfs frequency interfaces may have snuck in while servicing the
751 if (new_delay
>= dev_priv
->rps
.min_delay
&&
752 new_delay
<= dev_priv
->rps
.max_delay
) {
753 if (IS_VALLEYVIEW(dev_priv
->dev
))
754 valleyview_set_rps(dev_priv
->dev
, new_delay
);
756 gen6_set_rps(dev_priv
->dev
, new_delay
);
759 if (IS_VALLEYVIEW(dev_priv
->dev
)) {
761 * On VLV, when we enter RC6 we may not be at the minimum
762 * voltage level, so arm a timer to check. It should only
763 * fire when there's activity or once after we've entered
764 * RC6, and then won't be re-armed until the next RPS interrupt.
766 mod_delayed_work(dev_priv
->wq
, &dev_priv
->rps
.vlv_work
,
767 msecs_to_jiffies(100));
770 mutex_unlock(&dev_priv
->rps
.hw_lock
);
775 * ivybridge_parity_work - Workqueue called when a parity error interrupt
777 * @work: workqueue struct
779 * Doesn't actually do anything except notify userspace. As a consequence of
780 * this event, userspace should try to remap the bad rows since statistically
781 * it is likely the same row is more likely to go bad again.
783 static void ivybridge_parity_work(struct work_struct
*work
)
785 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
786 l3_parity
.error_work
);
787 u32 error_status
, row
, bank
, subbank
;
788 char *parity_event
[5];
792 /* We must turn off DOP level clock gating to access the L3 registers.
793 * In order to prevent a get/put style interface, acquire struct mutex
794 * any time we access those registers.
796 mutex_lock(&dev_priv
->dev
->struct_mutex
);
798 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
799 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
800 POSTING_READ(GEN7_MISCCPCTL
);
802 error_status
= I915_READ(GEN7_L3CDERRST1
);
803 row
= GEN7_PARITY_ERROR_ROW(error_status
);
804 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
805 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
807 I915_WRITE(GEN7_L3CDERRST1
, GEN7_PARITY_ERROR_VALID
|
808 GEN7_L3CDERRST1_ENABLE
);
809 POSTING_READ(GEN7_L3CDERRST1
);
811 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
813 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
814 dev_priv
->gt_irq_mask
&= ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
815 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
816 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
818 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
820 parity_event
[0] = "L3_PARITY_ERROR=1";
821 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
822 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
823 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
824 parity_event
[4] = NULL
;
826 kobject_uevent_env(&dev_priv
->dev
->primary
->kdev
.kobj
,
827 KOBJ_CHANGE
, parity_event
);
829 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
832 kfree(parity_event
[3]);
833 kfree(parity_event
[2]);
834 kfree(parity_event
[1]);
837 static void ivybridge_parity_error_irq_handler(struct drm_device
*dev
)
839 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
841 if (!HAS_L3_GPU_CACHE(dev
))
844 spin_lock(&dev_priv
->irq_lock
);
845 dev_priv
->gt_irq_mask
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
846 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
847 spin_unlock(&dev_priv
->irq_lock
);
849 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
852 static void snb_gt_irq_handler(struct drm_device
*dev
,
853 struct drm_i915_private
*dev_priv
,
858 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
859 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
860 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
861 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
862 if (gt_iir
& GT_BLT_USER_INTERRUPT
)
863 notify_ring(dev
, &dev_priv
->ring
[BCS
]);
865 if (gt_iir
& (GT_BLT_CS_ERROR_INTERRUPT
|
866 GT_BSD_CS_ERROR_INTERRUPT
|
867 GT_RENDER_CS_MASTER_ERROR_INTERRUPT
)) {
868 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir
);
869 i915_handle_error(dev
, false);
872 if (gt_iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT
)
873 ivybridge_parity_error_irq_handler(dev
);
876 /* Legacy way of handling PM interrupts */
877 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
,
881 * IIR bits should never already be set because IMR should
882 * prevent an interrupt from being shown in IIR. The warning
883 * displays a case where we've unsafely cleared
884 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
885 * type is not a problem, it displays a problem in the logic.
887 * The mask bit in IMR is cleared by dev_priv->rps.work.
890 spin_lock(&dev_priv
->rps
.lock
);
891 dev_priv
->rps
.pm_iir
|= pm_iir
;
892 I915_WRITE(GEN6_PMIMR
, dev_priv
->rps
.pm_iir
);
893 POSTING_READ(GEN6_PMIMR
);
894 spin_unlock(&dev_priv
->rps
.lock
);
896 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
899 #define HPD_STORM_DETECT_PERIOD 1000
900 #define HPD_STORM_THRESHOLD 5
902 static inline void intel_hpd_irq_handler(struct drm_device
*dev
,
906 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
908 bool storm_detected
= false;
910 if (!hotplug_trigger
)
913 spin_lock(&dev_priv
->irq_lock
);
914 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
916 if (!(hpd
[i
] & hotplug_trigger
) ||
917 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
)
920 dev_priv
->hpd_event_bits
|= (1 << i
);
921 if (!time_in_range(jiffies
, dev_priv
->hpd_stats
[i
].hpd_last_jiffies
,
922 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
923 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD
))) {
924 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
= jiffies
;
925 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
926 } else if (dev_priv
->hpd_stats
[i
].hpd_cnt
> HPD_STORM_THRESHOLD
) {
927 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_MARK_DISABLED
;
928 dev_priv
->hpd_event_bits
&= ~(1 << i
);
929 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i
);
930 storm_detected
= true;
932 dev_priv
->hpd_stats
[i
].hpd_cnt
++;
937 dev_priv
->display
.hpd_irq_setup(dev
);
938 spin_unlock(&dev_priv
->irq_lock
);
940 queue_work(dev_priv
->wq
,
941 &dev_priv
->hotplug_work
);
944 static void gmbus_irq_handler(struct drm_device
*dev
)
946 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
948 wake_up_all(&dev_priv
->gmbus_wait_queue
);
951 static void dp_aux_irq_handler(struct drm_device
*dev
)
953 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
955 wake_up_all(&dev_priv
->gmbus_wait_queue
);
958 /* Unlike gen6_rps_irq_handler() from which this function is originally derived,
959 * we must be able to deal with other PM interrupts. This is complicated because
960 * of the way in which we use the masks to defer the RPS work (which for
961 * posterity is necessary because of forcewake).
963 static void hsw_pm_irq_handler(struct drm_i915_private
*dev_priv
,
966 if (pm_iir
& GEN6_PM_RPS_EVENTS
) {
967 spin_lock(&dev_priv
->rps
.lock
);
968 dev_priv
->rps
.pm_iir
|= pm_iir
& GEN6_PM_RPS_EVENTS
;
969 I915_WRITE(GEN6_PMIMR
, dev_priv
->rps
.pm_iir
);
970 /* never want to mask useful interrupts. (also posting read) */
971 WARN_ON(I915_READ_NOTRACE(GEN6_PMIMR
) & ~GEN6_PM_RPS_EVENTS
);
972 spin_unlock(&dev_priv
->rps
.lock
);
974 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
977 if (pm_iir
& PM_VEBOX_USER_INTERRUPT
)
978 notify_ring(dev_priv
->dev
, &dev_priv
->ring
[VECS
]);
980 if (pm_iir
& PM_VEBOX_CS_ERROR_INTERRUPT
) {
981 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir
);
982 i915_handle_error(dev_priv
->dev
, false);
986 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
988 struct drm_device
*dev
= (struct drm_device
*) arg
;
989 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
990 u32 iir
, gt_iir
, pm_iir
;
991 irqreturn_t ret
= IRQ_NONE
;
992 unsigned long irqflags
;
994 u32 pipe_stats
[I915_MAX_PIPES
];
996 atomic_inc(&dev_priv
->irq_received
);
999 iir
= I915_READ(VLV_IIR
);
1000 gt_iir
= I915_READ(GTIIR
);
1001 pm_iir
= I915_READ(GEN6_PMIIR
);
1003 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
1008 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1010 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1011 for_each_pipe(pipe
) {
1012 int reg
= PIPESTAT(pipe
);
1013 pipe_stats
[pipe
] = I915_READ(reg
);
1016 * Clear the PIPE*STAT regs before the IIR
1018 if (pipe_stats
[pipe
] & 0x8000ffff) {
1019 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
1020 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1022 I915_WRITE(reg
, pipe_stats
[pipe
]);
1025 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1027 for_each_pipe(pipe
) {
1028 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
)
1029 drm_handle_vblank(dev
, pipe
);
1031 if (pipe_stats
[pipe
] & PLANE_FLIPDONE_INT_STATUS_VLV
) {
1032 intel_prepare_page_flip(dev
, pipe
);
1033 intel_finish_page_flip(dev
, pipe
);
1037 /* Consume port. Then clear IIR or we'll miss events */
1038 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
1039 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1040 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
1042 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1045 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
1047 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1048 I915_READ(PORT_HOTPLUG_STAT
);
1051 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1052 gmbus_irq_handler(dev
);
1054 if (pm_iir
& GEN6_PM_RPS_EVENTS
)
1055 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1057 I915_WRITE(GTIIR
, gt_iir
);
1058 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1059 I915_WRITE(VLV_IIR
, iir
);
1066 static void ibx_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1068 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1070 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK
;
1072 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_ibx
);
1074 if (pch_iir
& SDE_AUDIO_POWER_MASK
) {
1075 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK
) >>
1076 SDE_AUDIO_POWER_SHIFT
);
1077 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1081 if (pch_iir
& SDE_AUX_MASK
)
1082 dp_aux_irq_handler(dev
);
1084 if (pch_iir
& SDE_GMBUS
)
1085 gmbus_irq_handler(dev
);
1087 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
1088 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1090 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
1091 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1093 if (pch_iir
& SDE_POISON
)
1094 DRM_ERROR("PCH poison interrupt\n");
1096 if (pch_iir
& SDE_FDI_MASK
)
1098 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1100 I915_READ(FDI_RX_IIR(pipe
)));
1102 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
1103 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1105 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
1106 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1108 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
1109 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1111 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1113 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
1114 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1116 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1119 static void ivb_err_int_handler(struct drm_device
*dev
)
1121 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1122 u32 err_int
= I915_READ(GEN7_ERR_INT
);
1124 if (err_int
& ERR_INT_POISON
)
1125 DRM_ERROR("Poison interrupt\n");
1127 if (err_int
& ERR_INT_FIFO_UNDERRUN_A
)
1128 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_A
, false))
1129 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1131 if (err_int
& ERR_INT_FIFO_UNDERRUN_B
)
1132 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_B
, false))
1133 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1135 if (err_int
& ERR_INT_FIFO_UNDERRUN_C
)
1136 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_C
, false))
1137 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1139 I915_WRITE(GEN7_ERR_INT
, err_int
);
1142 static void cpt_serr_int_handler(struct drm_device
*dev
)
1144 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1145 u32 serr_int
= I915_READ(SERR_INT
);
1147 if (serr_int
& SERR_INT_POISON
)
1148 DRM_ERROR("PCH poison interrupt\n");
1150 if (serr_int
& SERR_INT_TRANS_A_FIFO_UNDERRUN
)
1151 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1153 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1155 if (serr_int
& SERR_INT_TRANS_B_FIFO_UNDERRUN
)
1156 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1158 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1160 if (serr_int
& SERR_INT_TRANS_C_FIFO_UNDERRUN
)
1161 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_C
,
1163 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1165 I915_WRITE(SERR_INT
, serr_int
);
1168 static void cpt_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1170 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1172 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_CPT
;
1174 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_cpt
);
1176 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) {
1177 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
1178 SDE_AUDIO_POWER_SHIFT_CPT
);
1179 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1183 if (pch_iir
& SDE_AUX_MASK_CPT
)
1184 dp_aux_irq_handler(dev
);
1186 if (pch_iir
& SDE_GMBUS_CPT
)
1187 gmbus_irq_handler(dev
);
1189 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
1190 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1192 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
1193 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1195 if (pch_iir
& SDE_FDI_MASK_CPT
)
1197 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1199 I915_READ(FDI_RX_IIR(pipe
)));
1201 if (pch_iir
& SDE_ERROR_CPT
)
1202 cpt_serr_int_handler(dev
);
1205 static irqreturn_t
ivybridge_irq_handler(int irq
, void *arg
)
1207 struct drm_device
*dev
= (struct drm_device
*) arg
;
1208 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1209 u32 de_iir
, gt_iir
, de_ier
, pm_iir
, sde_ier
= 0;
1210 irqreturn_t ret
= IRQ_NONE
;
1213 atomic_inc(&dev_priv
->irq_received
);
1215 /* We get interrupts on unclaimed registers, so check for this before we
1216 * do any I915_{READ,WRITE}. */
1217 if (IS_HASWELL(dev
) &&
1218 (I915_READ_NOTRACE(FPGA_DBG
) & FPGA_DBG_RM_NOCLAIM
)) {
1219 DRM_ERROR("Unclaimed register before interrupt\n");
1220 I915_WRITE_NOTRACE(FPGA_DBG
, FPGA_DBG_RM_NOCLAIM
);
1223 /* disable master interrupt before clearing iir */
1224 de_ier
= I915_READ(DEIER
);
1225 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
1227 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1228 * interrupts will will be stored on its back queue, and then we'll be
1229 * able to process them after we restore SDEIER (as soon as we restore
1230 * it, we'll get an interrupt if SDEIIR still has something to process
1231 * due to its back queue). */
1232 if (!HAS_PCH_NOP(dev
)) {
1233 sde_ier
= I915_READ(SDEIER
);
1234 I915_WRITE(SDEIER
, 0);
1235 POSTING_READ(SDEIER
);
1238 /* On Haswell, also mask ERR_INT because we don't want to risk
1239 * generating "unclaimed register" interrupts from inside the interrupt
1241 if (IS_HASWELL(dev
)) {
1242 spin_lock(&dev_priv
->irq_lock
);
1243 ironlake_disable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
1244 spin_unlock(&dev_priv
->irq_lock
);
1247 gt_iir
= I915_READ(GTIIR
);
1249 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1250 I915_WRITE(GTIIR
, gt_iir
);
1254 de_iir
= I915_READ(DEIIR
);
1256 if (de_iir
& DE_ERR_INT_IVB
)
1257 ivb_err_int_handler(dev
);
1259 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
1260 dp_aux_irq_handler(dev
);
1262 if (de_iir
& DE_GSE_IVB
)
1263 intel_opregion_asle_intr(dev
);
1265 for (i
= 0; i
< 3; i
++) {
1266 if (de_iir
& (DE_PIPEA_VBLANK_IVB
<< (5 * i
)))
1267 drm_handle_vblank(dev
, i
);
1268 if (de_iir
& (DE_PLANEA_FLIP_DONE_IVB
<< (5 * i
))) {
1269 intel_prepare_page_flip(dev
, i
);
1270 intel_finish_page_flip_plane(dev
, i
);
1274 /* check event from PCH */
1275 if (!HAS_PCH_NOP(dev
) && (de_iir
& DE_PCH_EVENT_IVB
)) {
1276 u32 pch_iir
= I915_READ(SDEIIR
);
1278 cpt_irq_handler(dev
, pch_iir
);
1280 /* clear PCH hotplug event before clear CPU irq */
1281 I915_WRITE(SDEIIR
, pch_iir
);
1284 I915_WRITE(DEIIR
, de_iir
);
1288 pm_iir
= I915_READ(GEN6_PMIIR
);
1290 if (IS_HASWELL(dev
))
1291 hsw_pm_irq_handler(dev_priv
, pm_iir
);
1292 else if (pm_iir
& GEN6_PM_RPS_EVENTS
)
1293 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1294 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1298 if (IS_HASWELL(dev
)) {
1299 spin_lock(&dev_priv
->irq_lock
);
1300 if (ivb_can_enable_err_int(dev
))
1301 ironlake_enable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
1302 spin_unlock(&dev_priv
->irq_lock
);
1305 I915_WRITE(DEIER
, de_ier
);
1306 POSTING_READ(DEIER
);
1307 if (!HAS_PCH_NOP(dev
)) {
1308 I915_WRITE(SDEIER
, sde_ier
);
1309 POSTING_READ(SDEIER
);
1315 static void ilk_gt_irq_handler(struct drm_device
*dev
,
1316 struct drm_i915_private
*dev_priv
,
1320 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1321 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
1322 if (gt_iir
& ILK_BSD_USER_INTERRUPT
)
1323 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1326 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
1328 struct drm_device
*dev
= (struct drm_device
*) arg
;
1329 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1331 u32 de_iir
, gt_iir
, de_ier
, pm_iir
, sde_ier
;
1333 atomic_inc(&dev_priv
->irq_received
);
1335 /* disable master interrupt before clearing iir */
1336 de_ier
= I915_READ(DEIER
);
1337 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
1338 POSTING_READ(DEIER
);
1340 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1341 * interrupts will will be stored on its back queue, and then we'll be
1342 * able to process them after we restore SDEIER (as soon as we restore
1343 * it, we'll get an interrupt if SDEIIR still has something to process
1344 * due to its back queue). */
1345 sde_ier
= I915_READ(SDEIER
);
1346 I915_WRITE(SDEIER
, 0);
1347 POSTING_READ(SDEIER
);
1349 de_iir
= I915_READ(DEIIR
);
1350 gt_iir
= I915_READ(GTIIR
);
1351 pm_iir
= I915_READ(GEN6_PMIIR
);
1353 if (de_iir
== 0 && gt_iir
== 0 && (!IS_GEN6(dev
) || pm_iir
== 0))
1359 ilk_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1361 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1363 if (de_iir
& DE_AUX_CHANNEL_A
)
1364 dp_aux_irq_handler(dev
);
1366 if (de_iir
& DE_GSE
)
1367 intel_opregion_asle_intr(dev
);
1369 if (de_iir
& DE_PIPEA_VBLANK
)
1370 drm_handle_vblank(dev
, 0);
1372 if (de_iir
& DE_PIPEB_VBLANK
)
1373 drm_handle_vblank(dev
, 1);
1375 if (de_iir
& DE_POISON
)
1376 DRM_ERROR("Poison interrupt\n");
1378 if (de_iir
& DE_PIPEA_FIFO_UNDERRUN
)
1379 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_A
, false))
1380 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1382 if (de_iir
& DE_PIPEB_FIFO_UNDERRUN
)
1383 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_B
, false))
1384 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1386 if (de_iir
& DE_PLANEA_FLIP_DONE
) {
1387 intel_prepare_page_flip(dev
, 0);
1388 intel_finish_page_flip_plane(dev
, 0);
1391 if (de_iir
& DE_PLANEB_FLIP_DONE
) {
1392 intel_prepare_page_flip(dev
, 1);
1393 intel_finish_page_flip_plane(dev
, 1);
1396 /* check event from PCH */
1397 if (de_iir
& DE_PCH_EVENT
) {
1398 u32 pch_iir
= I915_READ(SDEIIR
);
1400 if (HAS_PCH_CPT(dev
))
1401 cpt_irq_handler(dev
, pch_iir
);
1403 ibx_irq_handler(dev
, pch_iir
);
1405 /* should clear PCH hotplug event before clear CPU irq */
1406 I915_WRITE(SDEIIR
, pch_iir
);
1409 if (IS_GEN5(dev
) && de_iir
& DE_PCU_EVENT
)
1410 ironlake_rps_change_irq_handler(dev
);
1412 if (IS_GEN6(dev
) && pm_iir
& GEN6_PM_RPS_EVENTS
)
1413 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1415 I915_WRITE(GTIIR
, gt_iir
);
1416 I915_WRITE(DEIIR
, de_iir
);
1417 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1420 I915_WRITE(DEIER
, de_ier
);
1421 POSTING_READ(DEIER
);
1422 I915_WRITE(SDEIER
, sde_ier
);
1423 POSTING_READ(SDEIER
);
1429 * i915_error_work_func - do process context error handling work
1430 * @work: work struct
1432 * Fire an error uevent so userspace can see that a hang or error
1435 static void i915_error_work_func(struct work_struct
*work
)
1437 struct i915_gpu_error
*error
= container_of(work
, struct i915_gpu_error
,
1439 drm_i915_private_t
*dev_priv
= container_of(error
, drm_i915_private_t
,
1441 struct drm_device
*dev
= dev_priv
->dev
;
1442 struct intel_ring_buffer
*ring
;
1443 char *error_event
[] = { "ERROR=1", NULL
};
1444 char *reset_event
[] = { "RESET=1", NULL
};
1445 char *reset_done_event
[] = { "ERROR=0", NULL
};
1448 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
, error_event
);
1451 * Note that there's only one work item which does gpu resets, so we
1452 * need not worry about concurrent gpu resets potentially incrementing
1453 * error->reset_counter twice. We only need to take care of another
1454 * racing irq/hangcheck declaring the gpu dead for a second time. A
1455 * quick check for that is good enough: schedule_work ensures the
1456 * correct ordering between hang detection and this work item, and since
1457 * the reset in-progress bit is only ever set by code outside of this
1458 * work we don't need to worry about any other races.
1460 if (i915_reset_in_progress(error
) && !i915_terminally_wedged(error
)) {
1461 DRM_DEBUG_DRIVER("resetting chip\n");
1462 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
,
1465 ret
= i915_reset(dev
);
1469 * After all the gem state is reset, increment the reset
1470 * counter and wake up everyone waiting for the reset to
1473 * Since unlock operations are a one-sided barrier only,
1474 * we need to insert a barrier here to order any seqno
1476 * the counter increment.
1478 smp_mb__before_atomic_inc();
1479 atomic_inc(&dev_priv
->gpu_error
.reset_counter
);
1481 kobject_uevent_env(&dev
->primary
->kdev
.kobj
,
1482 KOBJ_CHANGE
, reset_done_event
);
1484 atomic_set(&error
->reset_counter
, I915_WEDGED
);
1487 for_each_ring(ring
, dev_priv
, i
)
1488 wake_up_all(&ring
->irq_queue
);
1490 intel_display_handle_reset(dev
);
1492 wake_up_all(&dev_priv
->gpu_error
.reset_queue
);
1496 /* NB: please notice the memset */
1497 static void i915_get_extra_instdone(struct drm_device
*dev
,
1500 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1501 memset(instdone
, 0, sizeof(*instdone
) * I915_NUM_INSTDONE_REG
);
1503 switch(INTEL_INFO(dev
)->gen
) {
1506 instdone
[0] = I915_READ(INSTDONE
);
1511 instdone
[0] = I915_READ(INSTDONE_I965
);
1512 instdone
[1] = I915_READ(INSTDONE1
);
1515 WARN_ONCE(1, "Unsupported platform\n");
1517 instdone
[0] = I915_READ(GEN7_INSTDONE_1
);
1518 instdone
[1] = I915_READ(GEN7_SC_INSTDONE
);
1519 instdone
[2] = I915_READ(GEN7_SAMPLER_INSTDONE
);
1520 instdone
[3] = I915_READ(GEN7_ROW_INSTDONE
);
1525 #ifdef CONFIG_DEBUG_FS
1526 static struct drm_i915_error_object
*
1527 i915_error_object_create_sized(struct drm_i915_private
*dev_priv
,
1528 struct drm_i915_gem_object
*src
,
1529 const int num_pages
)
1531 struct drm_i915_error_object
*dst
;
1535 if (src
== NULL
|| src
->pages
== NULL
)
1538 dst
= kmalloc(sizeof(*dst
) + num_pages
* sizeof(u32
*), GFP_ATOMIC
);
1542 reloc_offset
= dst
->gtt_offset
= i915_gem_obj_ggtt_offset(src
);
1543 for (i
= 0; i
< num_pages
; i
++) {
1544 unsigned long flags
;
1547 d
= kmalloc(PAGE_SIZE
, GFP_ATOMIC
);
1551 local_irq_save(flags
);
1552 if (reloc_offset
< dev_priv
->gtt
.mappable_end
&&
1553 src
->has_global_gtt_mapping
) {
1556 /* Simply ignore tiling or any overlapping fence.
1557 * It's part of the error state, and this hopefully
1558 * captures what the GPU read.
1561 s
= io_mapping_map_atomic_wc(dev_priv
->gtt
.mappable
,
1563 memcpy_fromio(d
, s
, PAGE_SIZE
);
1564 io_mapping_unmap_atomic(s
);
1565 } else if (src
->stolen
) {
1566 unsigned long offset
;
1568 offset
= dev_priv
->mm
.stolen_base
;
1569 offset
+= src
->stolen
->start
;
1570 offset
+= i
<< PAGE_SHIFT
;
1572 memcpy_fromio(d
, (void __iomem
*) offset
, PAGE_SIZE
);
1577 page
= i915_gem_object_get_page(src
, i
);
1579 drm_clflush_pages(&page
, 1);
1581 s
= kmap_atomic(page
);
1582 memcpy(d
, s
, PAGE_SIZE
);
1585 drm_clflush_pages(&page
, 1);
1587 local_irq_restore(flags
);
1591 reloc_offset
+= PAGE_SIZE
;
1593 dst
->page_count
= num_pages
;
1599 kfree(dst
->pages
[i
]);
1603 #define i915_error_object_create(dev_priv, src) \
1604 i915_error_object_create_sized((dev_priv), (src), \
1605 (src)->base.size>>PAGE_SHIFT)
1608 i915_error_object_free(struct drm_i915_error_object
*obj
)
1615 for (page
= 0; page
< obj
->page_count
; page
++)
1616 kfree(obj
->pages
[page
]);
1622 i915_error_state_free(struct kref
*error_ref
)
1624 struct drm_i915_error_state
*error
= container_of(error_ref
,
1625 typeof(*error
), ref
);
1628 for (i
= 0; i
< ARRAY_SIZE(error
->ring
); i
++) {
1629 i915_error_object_free(error
->ring
[i
].batchbuffer
);
1630 i915_error_object_free(error
->ring
[i
].ringbuffer
);
1631 i915_error_object_free(error
->ring
[i
].ctx
);
1632 kfree(error
->ring
[i
].requests
);
1635 kfree(error
->active_bo
);
1636 kfree(error
->overlay
);
1637 kfree(error
->display
);
1640 static void capture_bo(struct drm_i915_error_buffer
*err
,
1641 struct drm_i915_gem_object
*obj
)
1643 err
->size
= obj
->base
.size
;
1644 err
->name
= obj
->base
.name
;
1645 err
->rseqno
= obj
->last_read_seqno
;
1646 err
->wseqno
= obj
->last_write_seqno
;
1647 err
->gtt_offset
= i915_gem_obj_ggtt_offset(obj
);
1648 err
->read_domains
= obj
->base
.read_domains
;
1649 err
->write_domain
= obj
->base
.write_domain
;
1650 err
->fence_reg
= obj
->fence_reg
;
1652 if (obj
->pin_count
> 0)
1654 if (obj
->user_pin_count
> 0)
1656 err
->tiling
= obj
->tiling_mode
;
1657 err
->dirty
= obj
->dirty
;
1658 err
->purgeable
= obj
->madv
!= I915_MADV_WILLNEED
;
1659 err
->ring
= obj
->ring
? obj
->ring
->id
: -1;
1660 err
->cache_level
= obj
->cache_level
;
1663 static u32
capture_active_bo(struct drm_i915_error_buffer
*err
,
1664 int count
, struct list_head
*head
)
1666 struct drm_i915_gem_object
*obj
;
1669 list_for_each_entry(obj
, head
, mm_list
) {
1670 capture_bo(err
++, obj
);
1678 static u32
capture_pinned_bo(struct drm_i915_error_buffer
*err
,
1679 int count
, struct list_head
*head
)
1681 struct drm_i915_gem_object
*obj
;
1684 list_for_each_entry(obj
, head
, global_list
) {
1685 if (obj
->pin_count
== 0)
1688 capture_bo(err
++, obj
);
1696 static void i915_gem_record_fences(struct drm_device
*dev
,
1697 struct drm_i915_error_state
*error
)
1699 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1703 switch (INTEL_INFO(dev
)->gen
) {
1706 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++)
1707 error
->fence
[i
] = I915_READ64(FENCE_REG_SANDYBRIDGE_0
+ (i
* 8));
1711 for (i
= 0; i
< 16; i
++)
1712 error
->fence
[i
] = I915_READ64(FENCE_REG_965_0
+ (i
* 8));
1715 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
1716 for (i
= 0; i
< 8; i
++)
1717 error
->fence
[i
+8] = I915_READ(FENCE_REG_945_8
+ (i
* 4));
1719 for (i
= 0; i
< 8; i
++)
1720 error
->fence
[i
] = I915_READ(FENCE_REG_830_0
+ (i
* 4));
1728 static struct drm_i915_error_object
*
1729 i915_error_first_batchbuffer(struct drm_i915_private
*dev_priv
,
1730 struct intel_ring_buffer
*ring
)
1732 struct drm_i915_gem_object
*obj
;
1735 if (!ring
->get_seqno
)
1738 if (HAS_BROKEN_CS_TLB(dev_priv
->dev
)) {
1739 u32 acthd
= I915_READ(ACTHD
);
1741 if (WARN_ON(ring
->id
!= RCS
))
1744 obj
= ring
->private;
1745 if (acthd
>= i915_gem_obj_ggtt_offset(obj
) &&
1746 acthd
< i915_gem_obj_ggtt_offset(obj
) + obj
->base
.size
)
1747 return i915_error_object_create(dev_priv
, obj
);
1750 seqno
= ring
->get_seqno(ring
, false);
1751 list_for_each_entry(obj
, &dev_priv
->mm
.active_list
, mm_list
) {
1752 if (obj
->ring
!= ring
)
1755 if (i915_seqno_passed(seqno
, obj
->last_read_seqno
))
1758 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_COMMAND
) == 0)
1761 /* We need to copy these to an anonymous buffer as the simplest
1762 * method to avoid being overwritten by userspace.
1764 return i915_error_object_create(dev_priv
, obj
);
1770 static void i915_record_ring_state(struct drm_device
*dev
,
1771 struct drm_i915_error_state
*error
,
1772 struct intel_ring_buffer
*ring
)
1774 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1776 if (INTEL_INFO(dev
)->gen
>= 6) {
1777 error
->rc_psmi
[ring
->id
] = I915_READ(ring
->mmio_base
+ 0x50);
1778 error
->fault_reg
[ring
->id
] = I915_READ(RING_FAULT_REG(ring
));
1779 error
->semaphore_mboxes
[ring
->id
][0]
1780 = I915_READ(RING_SYNC_0(ring
->mmio_base
));
1781 error
->semaphore_mboxes
[ring
->id
][1]
1782 = I915_READ(RING_SYNC_1(ring
->mmio_base
));
1783 error
->semaphore_seqno
[ring
->id
][0] = ring
->sync_seqno
[0];
1784 error
->semaphore_seqno
[ring
->id
][1] = ring
->sync_seqno
[1];
1787 if (INTEL_INFO(dev
)->gen
>= 4) {
1788 error
->faddr
[ring
->id
] = I915_READ(RING_DMA_FADD(ring
->mmio_base
));
1789 error
->ipeir
[ring
->id
] = I915_READ(RING_IPEIR(ring
->mmio_base
));
1790 error
->ipehr
[ring
->id
] = I915_READ(RING_IPEHR(ring
->mmio_base
));
1791 error
->instdone
[ring
->id
] = I915_READ(RING_INSTDONE(ring
->mmio_base
));
1792 error
->instps
[ring
->id
] = I915_READ(RING_INSTPS(ring
->mmio_base
));
1793 if (ring
->id
== RCS
)
1794 error
->bbaddr
= I915_READ64(BB_ADDR
);
1796 error
->faddr
[ring
->id
] = I915_READ(DMA_FADD_I8XX
);
1797 error
->ipeir
[ring
->id
] = I915_READ(IPEIR
);
1798 error
->ipehr
[ring
->id
] = I915_READ(IPEHR
);
1799 error
->instdone
[ring
->id
] = I915_READ(INSTDONE
);
1802 error
->waiting
[ring
->id
] = waitqueue_active(&ring
->irq_queue
);
1803 error
->instpm
[ring
->id
] = I915_READ(RING_INSTPM(ring
->mmio_base
));
1804 error
->seqno
[ring
->id
] = ring
->get_seqno(ring
, false);
1805 error
->acthd
[ring
->id
] = intel_ring_get_active_head(ring
);
1806 error
->head
[ring
->id
] = I915_READ_HEAD(ring
);
1807 error
->tail
[ring
->id
] = I915_READ_TAIL(ring
);
1808 error
->ctl
[ring
->id
] = I915_READ_CTL(ring
);
1810 error
->cpu_ring_head
[ring
->id
] = ring
->head
;
1811 error
->cpu_ring_tail
[ring
->id
] = ring
->tail
;
1815 static void i915_gem_record_active_context(struct intel_ring_buffer
*ring
,
1816 struct drm_i915_error_state
*error
,
1817 struct drm_i915_error_ring
*ering
)
1819 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1820 struct drm_i915_gem_object
*obj
;
1822 /* Currently render ring is the only HW context user */
1823 if (ring
->id
!= RCS
|| !error
->ccid
)
1826 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
1827 if ((error
->ccid
& PAGE_MASK
) == i915_gem_obj_ggtt_offset(obj
)) {
1828 ering
->ctx
= i915_error_object_create_sized(dev_priv
,
1835 static void i915_gem_record_rings(struct drm_device
*dev
,
1836 struct drm_i915_error_state
*error
)
1838 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1839 struct intel_ring_buffer
*ring
;
1840 struct drm_i915_gem_request
*request
;
1843 for_each_ring(ring
, dev_priv
, i
) {
1844 i915_record_ring_state(dev
, error
, ring
);
1846 error
->ring
[i
].batchbuffer
=
1847 i915_error_first_batchbuffer(dev_priv
, ring
);
1849 error
->ring
[i
].ringbuffer
=
1850 i915_error_object_create(dev_priv
, ring
->obj
);
1853 i915_gem_record_active_context(ring
, error
, &error
->ring
[i
]);
1856 list_for_each_entry(request
, &ring
->request_list
, list
)
1859 error
->ring
[i
].num_requests
= count
;
1860 error
->ring
[i
].requests
=
1861 kmalloc(count
*sizeof(struct drm_i915_error_request
),
1863 if (error
->ring
[i
].requests
== NULL
) {
1864 error
->ring
[i
].num_requests
= 0;
1869 list_for_each_entry(request
, &ring
->request_list
, list
) {
1870 struct drm_i915_error_request
*erq
;
1872 erq
= &error
->ring
[i
].requests
[count
++];
1873 erq
->seqno
= request
->seqno
;
1874 erq
->jiffies
= request
->emitted_jiffies
;
1875 erq
->tail
= request
->tail
;
1880 static void i915_gem_capture_buffers(struct drm_i915_private
*dev_priv
,
1881 struct drm_i915_error_state
*error
)
1883 struct drm_i915_gem_object
*obj
;
1887 list_for_each_entry(obj
, &dev_priv
->mm
.active_list
, mm_list
)
1889 error
->active_bo_count
= i
;
1890 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
1893 error
->pinned_bo_count
= i
- error
->active_bo_count
;
1896 error
->active_bo
= kmalloc(sizeof(*error
->active_bo
)*i
,
1898 if (error
->active_bo
)
1900 error
->active_bo
+ error
->active_bo_count
;
1903 if (error
->active_bo
)
1904 error
->active_bo_count
=
1905 capture_active_bo(error
->active_bo
,
1906 error
->active_bo_count
,
1907 &dev_priv
->mm
.active_list
);
1909 if (error
->pinned_bo
)
1910 error
->pinned_bo_count
=
1911 capture_pinned_bo(error
->pinned_bo
,
1912 error
->pinned_bo_count
,
1913 &dev_priv
->mm
.bound_list
);
1917 * i915_capture_error_state - capture an error record for later analysis
1920 * Should be called when an error is detected (either a hang or an error
1921 * interrupt) to capture error state from the time of the error. Fills
1922 * out a structure which becomes available in debugfs for user level tools
1925 static void i915_capture_error_state(struct drm_device
*dev
)
1927 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1928 struct drm_i915_error_state
*error
;
1929 unsigned long flags
;
1932 spin_lock_irqsave(&dev_priv
->gpu_error
.lock
, flags
);
1933 error
= dev_priv
->gpu_error
.first_error
;
1934 spin_unlock_irqrestore(&dev_priv
->gpu_error
.lock
, flags
);
1938 /* Account for pipe specific data like PIPE*STAT */
1939 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
1941 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1945 DRM_INFO("capturing error event; look for more information in "
1946 "/sys/class/drm/card%d/error\n", dev
->primary
->index
);
1948 kref_init(&error
->ref
);
1949 error
->eir
= I915_READ(EIR
);
1950 error
->pgtbl_er
= I915_READ(PGTBL_ER
);
1951 if (HAS_HW_CONTEXTS(dev
))
1952 error
->ccid
= I915_READ(CCID
);
1954 if (HAS_PCH_SPLIT(dev
))
1955 error
->ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
1956 else if (IS_VALLEYVIEW(dev
))
1957 error
->ier
= I915_READ(GTIER
) | I915_READ(VLV_IER
);
1958 else if (IS_GEN2(dev
))
1959 error
->ier
= I915_READ16(IER
);
1961 error
->ier
= I915_READ(IER
);
1963 if (INTEL_INFO(dev
)->gen
>= 6)
1964 error
->derrmr
= I915_READ(DERRMR
);
1966 if (IS_VALLEYVIEW(dev
))
1967 error
->forcewake
= I915_READ(FORCEWAKE_VLV
);
1968 else if (INTEL_INFO(dev
)->gen
>= 7)
1969 error
->forcewake
= I915_READ(FORCEWAKE_MT
);
1970 else if (INTEL_INFO(dev
)->gen
== 6)
1971 error
->forcewake
= I915_READ(FORCEWAKE
);
1973 if (!HAS_PCH_SPLIT(dev
))
1975 error
->pipestat
[pipe
] = I915_READ(PIPESTAT(pipe
));
1977 if (INTEL_INFO(dev
)->gen
>= 6) {
1978 error
->error
= I915_READ(ERROR_GEN6
);
1979 error
->done_reg
= I915_READ(DONE_REG
);
1982 if (INTEL_INFO(dev
)->gen
== 7)
1983 error
->err_int
= I915_READ(GEN7_ERR_INT
);
1985 i915_get_extra_instdone(dev
, error
->extra_instdone
);
1987 i915_gem_capture_buffers(dev_priv
, error
);
1988 i915_gem_record_fences(dev
, error
);
1989 i915_gem_record_rings(dev
, error
);
1991 do_gettimeofday(&error
->time
);
1993 error
->overlay
= intel_overlay_capture_error_state(dev
);
1994 error
->display
= intel_display_capture_error_state(dev
);
1996 spin_lock_irqsave(&dev_priv
->gpu_error
.lock
, flags
);
1997 if (dev_priv
->gpu_error
.first_error
== NULL
) {
1998 dev_priv
->gpu_error
.first_error
= error
;
2001 spin_unlock_irqrestore(&dev_priv
->gpu_error
.lock
, flags
);
2004 i915_error_state_free(&error
->ref
);
2007 void i915_destroy_error_state(struct drm_device
*dev
)
2009 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2010 struct drm_i915_error_state
*error
;
2011 unsigned long flags
;
2013 spin_lock_irqsave(&dev_priv
->gpu_error
.lock
, flags
);
2014 error
= dev_priv
->gpu_error
.first_error
;
2015 dev_priv
->gpu_error
.first_error
= NULL
;
2016 spin_unlock_irqrestore(&dev_priv
->gpu_error
.lock
, flags
);
2019 kref_put(&error
->ref
, i915_error_state_free
);
2022 #define i915_capture_error_state(x)
2025 static void i915_report_and_clear_eir(struct drm_device
*dev
)
2027 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2028 uint32_t instdone
[I915_NUM_INSTDONE_REG
];
2029 u32 eir
= I915_READ(EIR
);
2035 pr_err("render error detected, EIR: 0x%08x\n", eir
);
2037 i915_get_extra_instdone(dev
, instdone
);
2040 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
2041 u32 ipeir
= I915_READ(IPEIR_I965
);
2043 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
2044 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
2045 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
2046 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
2047 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
2048 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
2049 I915_WRITE(IPEIR_I965
, ipeir
);
2050 POSTING_READ(IPEIR_I965
);
2052 if (eir
& GM45_ERROR_PAGE_TABLE
) {
2053 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
2054 pr_err("page table error\n");
2055 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
2056 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2057 POSTING_READ(PGTBL_ER
);
2061 if (!IS_GEN2(dev
)) {
2062 if (eir
& I915_ERROR_PAGE_TABLE
) {
2063 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
2064 pr_err("page table error\n");
2065 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
2066 I915_WRITE(PGTBL_ER
, pgtbl_err
);
2067 POSTING_READ(PGTBL_ER
);
2071 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
2072 pr_err("memory refresh error:\n");
2074 pr_err("pipe %c stat: 0x%08x\n",
2075 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
2076 /* pipestat has already been acked */
2078 if (eir
& I915_ERROR_INSTRUCTION
) {
2079 pr_err("instruction error\n");
2080 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
2081 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
2082 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
2083 if (INTEL_INFO(dev
)->gen
< 4) {
2084 u32 ipeir
= I915_READ(IPEIR
);
2086 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
2087 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
2088 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
2089 I915_WRITE(IPEIR
, ipeir
);
2090 POSTING_READ(IPEIR
);
2092 u32 ipeir
= I915_READ(IPEIR_I965
);
2094 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
2095 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
2096 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
2097 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
2098 I915_WRITE(IPEIR_I965
, ipeir
);
2099 POSTING_READ(IPEIR_I965
);
2103 I915_WRITE(EIR
, eir
);
2105 eir
= I915_READ(EIR
);
2108 * some errors might have become stuck,
2111 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
2112 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
2113 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2118 * i915_handle_error - handle an error interrupt
2121 * Do some basic checking of regsiter state at error interrupt time and
2122 * dump it to the syslog. Also call i915_capture_error_state() to make
2123 * sure we get a record and make it available in debugfs. Fire a uevent
2124 * so userspace knows something bad happened (should trigger collection
2125 * of a ring dump etc.).
2127 void i915_handle_error(struct drm_device
*dev
, bool wedged
)
2129 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2130 struct intel_ring_buffer
*ring
;
2133 i915_capture_error_state(dev
);
2134 i915_report_and_clear_eir(dev
);
2137 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG
,
2138 &dev_priv
->gpu_error
.reset_counter
);
2141 * Wakeup waiting processes so that the reset work item
2142 * doesn't deadlock trying to grab various locks.
2144 for_each_ring(ring
, dev_priv
, i
)
2145 wake_up_all(&ring
->irq_queue
);
2148 queue_work(dev_priv
->wq
, &dev_priv
->gpu_error
.work
);
2151 static void __always_unused
i915_pageflip_stall_check(struct drm_device
*dev
, int pipe
)
2153 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2154 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
2155 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2156 struct drm_i915_gem_object
*obj
;
2157 struct intel_unpin_work
*work
;
2158 unsigned long flags
;
2159 bool stall_detected
;
2161 /* Ignore early vblank irqs */
2162 if (intel_crtc
== NULL
)
2165 spin_lock_irqsave(&dev
->event_lock
, flags
);
2166 work
= intel_crtc
->unpin_work
;
2169 atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
||
2170 !work
->enable_stall_check
) {
2171 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2172 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2176 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2177 obj
= work
->pending_flip_obj
;
2178 if (INTEL_INFO(dev
)->gen
>= 4) {
2179 int dspsurf
= DSPSURF(intel_crtc
->plane
);
2180 stall_detected
= I915_HI_DISPBASE(I915_READ(dspsurf
)) ==
2181 i915_gem_obj_ggtt_offset(obj
);
2183 int dspaddr
= DSPADDR(intel_crtc
->plane
);
2184 stall_detected
= I915_READ(dspaddr
) == (i915_gem_obj_ggtt_offset(obj
) +
2185 crtc
->y
* crtc
->fb
->pitches
[0] +
2186 crtc
->x
* crtc
->fb
->bits_per_pixel
/8);
2189 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2191 if (stall_detected
) {
2192 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2193 intel_prepare_page_flip(dev
, intel_crtc
->plane
);
2197 /* Called from drm generic code, passed 'crtc' which
2198 * we use as a pipe index
2200 static int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
2202 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2203 unsigned long irqflags
;
2205 if (!i915_pipe_enabled(dev
, pipe
))
2208 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2209 if (INTEL_INFO(dev
)->gen
>= 4)
2210 i915_enable_pipestat(dev_priv
, pipe
,
2211 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
2213 i915_enable_pipestat(dev_priv
, pipe
,
2214 PIPE_VBLANK_INTERRUPT_ENABLE
);
2216 /* maintain vblank delivery even in deep C-states */
2217 if (dev_priv
->info
->gen
== 3)
2218 I915_WRITE(INSTPM
, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS
));
2219 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2224 static int ironlake_enable_vblank(struct drm_device
*dev
, int pipe
)
2226 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2227 unsigned long irqflags
;
2229 if (!i915_pipe_enabled(dev
, pipe
))
2232 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2233 ironlake_enable_display_irq(dev_priv
, (pipe
== 0) ?
2234 DE_PIPEA_VBLANK
: DE_PIPEB_VBLANK
);
2235 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2240 static int ivybridge_enable_vblank(struct drm_device
*dev
, int pipe
)
2242 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2243 unsigned long irqflags
;
2245 if (!i915_pipe_enabled(dev
, pipe
))
2248 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2249 ironlake_enable_display_irq(dev_priv
,
2250 DE_PIPEA_VBLANK_IVB
<< (5 * pipe
));
2251 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2256 static int valleyview_enable_vblank(struct drm_device
*dev
, int pipe
)
2258 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2259 unsigned long irqflags
;
2262 if (!i915_pipe_enabled(dev
, pipe
))
2265 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2266 imr
= I915_READ(VLV_IMR
);
2268 imr
&= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
2270 imr
&= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2271 I915_WRITE(VLV_IMR
, imr
);
2272 i915_enable_pipestat(dev_priv
, pipe
,
2273 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
2274 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2279 /* Called from drm generic code, passed 'crtc' which
2280 * we use as a pipe index
2282 static void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
2284 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2285 unsigned long irqflags
;
2287 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2288 if (dev_priv
->info
->gen
== 3)
2289 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS
));
2291 i915_disable_pipestat(dev_priv
, pipe
,
2292 PIPE_VBLANK_INTERRUPT_ENABLE
|
2293 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
2294 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2297 static void ironlake_disable_vblank(struct drm_device
*dev
, int pipe
)
2299 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2300 unsigned long irqflags
;
2302 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2303 ironlake_disable_display_irq(dev_priv
, (pipe
== 0) ?
2304 DE_PIPEA_VBLANK
: DE_PIPEB_VBLANK
);
2305 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2308 static void ivybridge_disable_vblank(struct drm_device
*dev
, int pipe
)
2310 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2311 unsigned long irqflags
;
2313 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2314 ironlake_disable_display_irq(dev_priv
,
2315 DE_PIPEA_VBLANK_IVB
<< (pipe
* 5));
2316 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2319 static void valleyview_disable_vblank(struct drm_device
*dev
, int pipe
)
2321 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2322 unsigned long irqflags
;
2325 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2326 i915_disable_pipestat(dev_priv
, pipe
,
2327 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
2328 imr
= I915_READ(VLV_IMR
);
2330 imr
|= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
2332 imr
|= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2333 I915_WRITE(VLV_IMR
, imr
);
2334 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2338 ring_last_seqno(struct intel_ring_buffer
*ring
)
2340 return list_entry(ring
->request_list
.prev
,
2341 struct drm_i915_gem_request
, list
)->seqno
;
2345 ring_idle(struct intel_ring_buffer
*ring
, u32 seqno
)
2347 return (list_empty(&ring
->request_list
) ||
2348 i915_seqno_passed(seqno
, ring_last_seqno(ring
)));
2351 static struct intel_ring_buffer
*
2352 semaphore_waits_for(struct intel_ring_buffer
*ring
, u32
*seqno
)
2354 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2355 u32 cmd
, ipehr
, acthd
, acthd_min
;
2357 ipehr
= I915_READ(RING_IPEHR(ring
->mmio_base
));
2358 if ((ipehr
& ~(0x3 << 16)) !=
2359 (MI_SEMAPHORE_MBOX
| MI_SEMAPHORE_COMPARE
| MI_SEMAPHORE_REGISTER
))
2362 /* ACTHD is likely pointing to the dword after the actual command,
2363 * so scan backwards until we find the MBOX.
2365 acthd
= intel_ring_get_active_head(ring
) & HEAD_ADDR
;
2366 acthd_min
= max((int)acthd
- 3 * 4, 0);
2368 cmd
= ioread32(ring
->virtual_start
+ acthd
);
2373 if (acthd
< acthd_min
)
2377 *seqno
= ioread32(ring
->virtual_start
+acthd
+4)+1;
2378 return &dev_priv
->ring
[(ring
->id
+ (((ipehr
>> 17) & 1) + 1)) % 3];
2381 static int semaphore_passed(struct intel_ring_buffer
*ring
)
2383 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2384 struct intel_ring_buffer
*signaller
;
2387 ring
->hangcheck
.deadlock
= true;
2389 signaller
= semaphore_waits_for(ring
, &seqno
);
2390 if (signaller
== NULL
|| signaller
->hangcheck
.deadlock
)
2393 /* cursory check for an unkickable deadlock */
2394 ctl
= I915_READ_CTL(signaller
);
2395 if (ctl
& RING_WAIT_SEMAPHORE
&& semaphore_passed(signaller
) < 0)
2398 return i915_seqno_passed(signaller
->get_seqno(signaller
, false), seqno
);
2401 static void semaphore_clear_deadlocks(struct drm_i915_private
*dev_priv
)
2403 struct intel_ring_buffer
*ring
;
2406 for_each_ring(ring
, dev_priv
, i
)
2407 ring
->hangcheck
.deadlock
= false;
2410 static enum intel_ring_hangcheck_action
2411 ring_stuck(struct intel_ring_buffer
*ring
, u32 acthd
)
2413 struct drm_device
*dev
= ring
->dev
;
2414 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2417 if (ring
->hangcheck
.acthd
!= acthd
)
2423 /* Is the chip hanging on a WAIT_FOR_EVENT?
2424 * If so we can simply poke the RB_WAIT bit
2425 * and break the hang. This should work on
2426 * all but the second generation chipsets.
2428 tmp
= I915_READ_CTL(ring
);
2429 if (tmp
& RING_WAIT
) {
2430 DRM_ERROR("Kicking stuck wait on %s\n",
2432 I915_WRITE_CTL(ring
, tmp
);
2436 if (INTEL_INFO(dev
)->gen
>= 6 && tmp
& RING_WAIT_SEMAPHORE
) {
2437 switch (semaphore_passed(ring
)) {
2441 DRM_ERROR("Kicking stuck semaphore on %s\n",
2443 I915_WRITE_CTL(ring
, tmp
);
2454 * This is called when the chip hasn't reported back with completed
2455 * batchbuffers in a long time. We keep track per ring seqno progress and
2456 * if there are no progress, hangcheck score for that ring is increased.
2457 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2458 * we kick the ring. If we see no progress on three subsequent calls
2459 * we assume chip is wedged and try to fix it by resetting the chip.
2461 void i915_hangcheck_elapsed(unsigned long data
)
2463 struct drm_device
*dev
= (struct drm_device
*)data
;
2464 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2465 struct intel_ring_buffer
*ring
;
2467 int busy_count
= 0, rings_hung
= 0;
2468 bool stuck
[I915_NUM_RINGS
] = { 0 };
2474 if (!i915_enable_hangcheck
)
2477 for_each_ring(ring
, dev_priv
, i
) {
2481 semaphore_clear_deadlocks(dev_priv
);
2483 seqno
= ring
->get_seqno(ring
, false);
2484 acthd
= intel_ring_get_active_head(ring
);
2486 if (ring
->hangcheck
.seqno
== seqno
) {
2487 if (ring_idle(ring
, seqno
)) {
2488 if (waitqueue_active(&ring
->irq_queue
)) {
2489 /* Issue a wake-up to catch stuck h/w. */
2490 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2492 wake_up_all(&ring
->irq_queue
);
2493 ring
->hangcheck
.score
+= HUNG
;
2499 /* We always increment the hangcheck score
2500 * if the ring is busy and still processing
2501 * the same request, so that no single request
2502 * can run indefinitely (such as a chain of
2503 * batches). The only time we do not increment
2504 * the hangcheck score on this ring, if this
2505 * ring is in a legitimate wait for another
2506 * ring. In that case the waiting ring is a
2507 * victim and we want to be sure we catch the
2508 * right culprit. Then every time we do kick
2509 * the ring, add a small increment to the
2510 * score so that we can catch a batch that is
2511 * being repeatedly kicked and so responsible
2512 * for stalling the machine.
2514 ring
->hangcheck
.action
= ring_stuck(ring
,
2517 switch (ring
->hangcheck
.action
) {
2532 ring
->hangcheck
.score
+= score
;
2535 /* Gradually reduce the count so that we catch DoS
2536 * attempts across multiple batches.
2538 if (ring
->hangcheck
.score
> 0)
2539 ring
->hangcheck
.score
--;
2542 ring
->hangcheck
.seqno
= seqno
;
2543 ring
->hangcheck
.acthd
= acthd
;
2547 for_each_ring(ring
, dev_priv
, i
) {
2548 if (ring
->hangcheck
.score
> FIRE
) {
2549 DRM_ERROR("%s on %s\n",
2550 stuck
[i
] ? "stuck" : "no progress",
2557 return i915_handle_error(dev
, true);
2560 /* Reset timer case chip hangs without another request
2562 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
2563 round_jiffies_up(jiffies
+
2564 DRM_I915_HANGCHECK_JIFFIES
));
2567 static void ibx_irq_preinstall(struct drm_device
*dev
)
2569 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2571 if (HAS_PCH_NOP(dev
))
2574 /* south display irq */
2575 I915_WRITE(SDEIMR
, 0xffffffff);
2577 * SDEIER is also touched by the interrupt handler to work around missed
2578 * PCH interrupts. Hence we can't update it after the interrupt handler
2579 * is enabled - instead we unconditionally enable all PCH interrupt
2580 * sources here, but then only unmask them as needed with SDEIMR.
2582 I915_WRITE(SDEIER
, 0xffffffff);
2583 POSTING_READ(SDEIER
);
2588 static void ironlake_irq_preinstall(struct drm_device
*dev
)
2590 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2592 atomic_set(&dev_priv
->irq_received
, 0);
2594 I915_WRITE(HWSTAM
, 0xeffe);
2596 /* XXX hotplug from PCH */
2598 I915_WRITE(DEIMR
, 0xffffffff);
2599 I915_WRITE(DEIER
, 0x0);
2600 POSTING_READ(DEIER
);
2603 I915_WRITE(GTIMR
, 0xffffffff);
2604 I915_WRITE(GTIER
, 0x0);
2605 POSTING_READ(GTIER
);
2607 ibx_irq_preinstall(dev
);
2610 static void ivybridge_irq_preinstall(struct drm_device
*dev
)
2612 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2614 atomic_set(&dev_priv
->irq_received
, 0);
2616 I915_WRITE(HWSTAM
, 0xeffe);
2618 /* XXX hotplug from PCH */
2620 I915_WRITE(DEIMR
, 0xffffffff);
2621 I915_WRITE(DEIER
, 0x0);
2622 POSTING_READ(DEIER
);
2625 I915_WRITE(GTIMR
, 0xffffffff);
2626 I915_WRITE(GTIER
, 0x0);
2627 POSTING_READ(GTIER
);
2629 /* Power management */
2630 I915_WRITE(GEN6_PMIMR
, 0xffffffff);
2631 I915_WRITE(GEN6_PMIER
, 0x0);
2632 POSTING_READ(GEN6_PMIER
);
2634 ibx_irq_preinstall(dev
);
2637 static void valleyview_irq_preinstall(struct drm_device
*dev
)
2639 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2642 atomic_set(&dev_priv
->irq_received
, 0);
2645 I915_WRITE(VLV_IMR
, 0);
2646 I915_WRITE(RING_IMR(RENDER_RING_BASE
), 0);
2647 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE
), 0);
2648 I915_WRITE(RING_IMR(BLT_RING_BASE
), 0);
2651 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2652 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2653 I915_WRITE(GTIMR
, 0xffffffff);
2654 I915_WRITE(GTIER
, 0x0);
2655 POSTING_READ(GTIER
);
2657 I915_WRITE(DPINVGTT
, 0xff);
2659 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2660 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2662 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2663 I915_WRITE(VLV_IIR
, 0xffffffff);
2664 I915_WRITE(VLV_IMR
, 0xffffffff);
2665 I915_WRITE(VLV_IER
, 0x0);
2666 POSTING_READ(VLV_IER
);
2669 static void ibx_hpd_irq_setup(struct drm_device
*dev
)
2671 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2672 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2673 struct intel_encoder
*intel_encoder
;
2674 u32 hotplug_irqs
, hotplug
, enabled_irqs
= 0;
2676 if (HAS_PCH_IBX(dev
)) {
2677 hotplug_irqs
= SDE_HOTPLUG_MASK
;
2678 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2679 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2680 enabled_irqs
|= hpd_ibx
[intel_encoder
->hpd_pin
];
2682 hotplug_irqs
= SDE_HOTPLUG_MASK_CPT
;
2683 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2684 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2685 enabled_irqs
|= hpd_cpt
[intel_encoder
->hpd_pin
];
2688 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
2691 * Enable digital hotplug on the PCH, and configure the DP short pulse
2692 * duration to 2ms (which is the minimum in the Display Port spec)
2694 * This register is the same on all known PCH chips.
2696 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
2697 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
2698 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
2699 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
2700 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
2701 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
2704 static void ibx_irq_postinstall(struct drm_device
*dev
)
2706 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2709 if (HAS_PCH_NOP(dev
))
2712 if (HAS_PCH_IBX(dev
)) {
2713 mask
= SDE_GMBUS
| SDE_AUX_MASK
| SDE_TRANSB_FIFO_UNDER
|
2714 SDE_TRANSA_FIFO_UNDER
| SDE_POISON
;
2716 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
| SDE_ERROR_CPT
;
2718 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2721 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2722 I915_WRITE(SDEIMR
, ~mask
);
2725 static int ironlake_irq_postinstall(struct drm_device
*dev
)
2727 unsigned long irqflags
;
2729 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2730 /* enable kind of interrupts always enabled */
2731 u32 display_mask
= DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
2732 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
|
2733 DE_AUX_CHANNEL_A
| DE_PIPEB_FIFO_UNDERRUN
|
2734 DE_PIPEA_FIFO_UNDERRUN
| DE_POISON
;
2737 dev_priv
->irq_mask
= ~display_mask
;
2739 /* should always can generate irq */
2740 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2741 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
2742 I915_WRITE(DEIER
, display_mask
|
2743 DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
| DE_PCU_EVENT
);
2744 POSTING_READ(DEIER
);
2746 dev_priv
->gt_irq_mask
= ~0;
2748 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2749 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
2751 gt_irqs
= GT_RENDER_USER_INTERRUPT
;
2754 gt_irqs
|= GT_BLT_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
;
2756 gt_irqs
|= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
|
2757 ILK_BSD_USER_INTERRUPT
;
2759 I915_WRITE(GTIER
, gt_irqs
);
2760 POSTING_READ(GTIER
);
2762 ibx_irq_postinstall(dev
);
2764 if (IS_IRONLAKE_M(dev
)) {
2765 /* Enable PCU event interrupts
2767 * spinlocking not required here for correctness since interrupt
2768 * setup is guaranteed to run in single-threaded context. But we
2769 * need it to make the assert_spin_locked happy. */
2770 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2771 ironlake_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
2772 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2778 static int ivybridge_irq_postinstall(struct drm_device
*dev
)
2780 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2781 /* enable kind of interrupts always enabled */
2783 DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
| DE_PCH_EVENT_IVB
|
2784 DE_PLANEC_FLIP_DONE_IVB
|
2785 DE_PLANEB_FLIP_DONE_IVB
|
2786 DE_PLANEA_FLIP_DONE_IVB
|
2787 DE_AUX_CHANNEL_A_IVB
|
2789 u32 pm_irqs
= GEN6_PM_RPS_EVENTS
;
2792 dev_priv
->irq_mask
= ~display_mask
;
2794 /* should always can generate irq */
2795 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2796 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2797 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
2800 DE_PIPEC_VBLANK_IVB
|
2801 DE_PIPEB_VBLANK_IVB
|
2802 DE_PIPEA_VBLANK_IVB
);
2803 POSTING_READ(DEIER
);
2805 dev_priv
->gt_irq_mask
= ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
2807 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2808 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
2810 gt_irqs
= GT_RENDER_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
|
2811 GT_BLT_USER_INTERRUPT
| GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
2812 I915_WRITE(GTIER
, gt_irqs
);
2813 POSTING_READ(GTIER
);
2815 I915_WRITE(GEN6_PMIIR
, I915_READ(GEN6_PMIIR
));
2817 pm_irqs
|= PM_VEBOX_USER_INTERRUPT
|
2818 PM_VEBOX_CS_ERROR_INTERRUPT
;
2820 /* Our enable/disable rps functions may touch these registers so
2821 * make sure to set a known state for only the non-RPS bits.
2822 * The RMW is extra paranoia since this should be called after being set
2823 * to a known state in preinstall.
2825 I915_WRITE(GEN6_PMIMR
,
2826 (I915_READ(GEN6_PMIMR
) | ~GEN6_PM_RPS_EVENTS
) & ~pm_irqs
);
2827 I915_WRITE(GEN6_PMIER
,
2828 (I915_READ(GEN6_PMIER
) & GEN6_PM_RPS_EVENTS
) | pm_irqs
);
2829 POSTING_READ(GEN6_PMIER
);
2831 ibx_irq_postinstall(dev
);
2836 static int valleyview_irq_postinstall(struct drm_device
*dev
)
2838 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2841 u32 pipestat_enable
= PLANE_FLIP_DONE_INT_EN_VLV
;
2842 unsigned long irqflags
;
2844 enable_mask
= I915_DISPLAY_PORT_INTERRUPT
;
2845 enable_mask
|= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2846 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2847 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2848 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2851 *Leave vblank interrupts masked initially. enable/disable will
2852 * toggle them based on usage.
2854 dev_priv
->irq_mask
= (~enable_mask
) |
2855 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2856 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2858 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2859 POSTING_READ(PORT_HOTPLUG_EN
);
2861 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
2862 I915_WRITE(VLV_IER
, enable_mask
);
2863 I915_WRITE(VLV_IIR
, 0xffffffff);
2864 I915_WRITE(PIPESTAT(0), 0xffff);
2865 I915_WRITE(PIPESTAT(1), 0xffff);
2866 POSTING_READ(VLV_IER
);
2868 /* Interrupt setup is already guaranteed to be single-threaded, this is
2869 * just to make the assert_spin_locked check happy. */
2870 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2871 i915_enable_pipestat(dev_priv
, 0, pipestat_enable
);
2872 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
2873 i915_enable_pipestat(dev_priv
, 1, pipestat_enable
);
2874 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2876 I915_WRITE(VLV_IIR
, 0xffffffff);
2877 I915_WRITE(VLV_IIR
, 0xffffffff);
2879 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2880 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
2882 gt_irqs
= GT_RENDER_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
|
2883 GT_BLT_USER_INTERRUPT
;
2884 I915_WRITE(GTIER
, gt_irqs
);
2885 POSTING_READ(GTIER
);
2887 /* ack & enable invalid PTE error interrupts */
2888 #if 0 /* FIXME: add support to irq handler for checking these bits */
2889 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
2890 I915_WRITE(DPINVGTT
, DPINVGTT_EN_MASK
);
2893 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
2898 static void valleyview_irq_uninstall(struct drm_device
*dev
)
2900 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2906 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2909 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2911 I915_WRITE(HWSTAM
, 0xffffffff);
2912 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2913 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2915 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2916 I915_WRITE(VLV_IIR
, 0xffffffff);
2917 I915_WRITE(VLV_IMR
, 0xffffffff);
2918 I915_WRITE(VLV_IER
, 0x0);
2919 POSTING_READ(VLV_IER
);
2922 static void ironlake_irq_uninstall(struct drm_device
*dev
)
2924 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2929 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2931 I915_WRITE(HWSTAM
, 0xffffffff);
2933 I915_WRITE(DEIMR
, 0xffffffff);
2934 I915_WRITE(DEIER
, 0x0);
2935 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2937 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2939 I915_WRITE(GTIMR
, 0xffffffff);
2940 I915_WRITE(GTIER
, 0x0);
2941 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2943 if (HAS_PCH_NOP(dev
))
2946 I915_WRITE(SDEIMR
, 0xffffffff);
2947 I915_WRITE(SDEIER
, 0x0);
2948 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2949 if (HAS_PCH_CPT(dev
) || HAS_PCH_LPT(dev
))
2950 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2953 static void i8xx_irq_preinstall(struct drm_device
* dev
)
2955 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2958 atomic_set(&dev_priv
->irq_received
, 0);
2961 I915_WRITE(PIPESTAT(pipe
), 0);
2962 I915_WRITE16(IMR
, 0xffff);
2963 I915_WRITE16(IER
, 0x0);
2964 POSTING_READ16(IER
);
2967 static int i8xx_irq_postinstall(struct drm_device
*dev
)
2969 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2972 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2974 /* Unmask the interrupts that we always want on. */
2975 dev_priv
->irq_mask
=
2976 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2977 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2978 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2979 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2980 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2981 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
2984 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2985 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2986 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2987 I915_USER_INTERRUPT
);
2988 POSTING_READ16(IER
);
2994 * Returns true when a page flip has completed.
2996 static bool i8xx_handle_vblank(struct drm_device
*dev
,
2999 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3000 u16 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(pipe
);
3002 if (!drm_handle_vblank(dev
, pipe
))
3005 if ((iir
& flip_pending
) == 0)
3008 intel_prepare_page_flip(dev
, pipe
);
3010 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3011 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3012 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3013 * the flip is completed (no longer pending). Since this doesn't raise
3014 * an interrupt per se, we watch for the change at vblank.
3016 if (I915_READ16(ISR
) & flip_pending
)
3019 intel_finish_page_flip(dev
, pipe
);
3024 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
3026 struct drm_device
*dev
= (struct drm_device
*) arg
;
3027 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3030 unsigned long irqflags
;
3034 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3035 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3037 atomic_inc(&dev_priv
->irq_received
);
3039 iir
= I915_READ16(IIR
);
3043 while (iir
& ~flip_mask
) {
3044 /* Can't rely on pipestat interrupt bit in iir as it might
3045 * have been cleared after the pipestat interrupt was received.
3046 * It doesn't set the bit in iir again, but it still produces
3047 * interrupts (for non-MSI).
3049 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3050 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3051 i915_handle_error(dev
, false);
3053 for_each_pipe(pipe
) {
3054 int reg
= PIPESTAT(pipe
);
3055 pipe_stats
[pipe
] = I915_READ(reg
);
3058 * Clear the PIPE*STAT regs before the IIR
3060 if (pipe_stats
[pipe
] & 0x8000ffff) {
3061 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
3062 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3064 I915_WRITE(reg
, pipe_stats
[pipe
]);
3068 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3070 I915_WRITE16(IIR
, iir
& ~flip_mask
);
3071 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
3073 i915_update_dri1_breadcrumb(dev
);
3075 if (iir
& I915_USER_INTERRUPT
)
3076 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
3078 if (pipe_stats
[0] & PIPE_VBLANK_INTERRUPT_STATUS
&&
3079 i8xx_handle_vblank(dev
, 0, iir
))
3080 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(0);
3082 if (pipe_stats
[1] & PIPE_VBLANK_INTERRUPT_STATUS
&&
3083 i8xx_handle_vblank(dev
, 1, iir
))
3084 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(1);
3092 static void i8xx_irq_uninstall(struct drm_device
* dev
)
3094 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3097 for_each_pipe(pipe
) {
3098 /* Clear enable bits; then clear status bits */
3099 I915_WRITE(PIPESTAT(pipe
), 0);
3100 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
3102 I915_WRITE16(IMR
, 0xffff);
3103 I915_WRITE16(IER
, 0x0);
3104 I915_WRITE16(IIR
, I915_READ16(IIR
));
3107 static void i915_irq_preinstall(struct drm_device
* dev
)
3109 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3112 atomic_set(&dev_priv
->irq_received
, 0);
3114 if (I915_HAS_HOTPLUG(dev
)) {
3115 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3116 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3119 I915_WRITE16(HWSTAM
, 0xeffe);
3121 I915_WRITE(PIPESTAT(pipe
), 0);
3122 I915_WRITE(IMR
, 0xffffffff);
3123 I915_WRITE(IER
, 0x0);
3127 static int i915_irq_postinstall(struct drm_device
*dev
)
3129 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3132 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
3134 /* Unmask the interrupts that we always want on. */
3135 dev_priv
->irq_mask
=
3136 ~(I915_ASLE_INTERRUPT
|
3137 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3138 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3139 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3140 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
3141 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
3144 I915_ASLE_INTERRUPT
|
3145 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3146 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3147 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
3148 I915_USER_INTERRUPT
;
3150 if (I915_HAS_HOTPLUG(dev
)) {
3151 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3152 POSTING_READ(PORT_HOTPLUG_EN
);
3154 /* Enable in IER... */
3155 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
3156 /* and unmask in IMR */
3157 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
3160 I915_WRITE(IMR
, dev_priv
->irq_mask
);
3161 I915_WRITE(IER
, enable_mask
);
3164 i915_enable_asle_pipestat(dev
);
3170 * Returns true when a page flip has completed.
3172 static bool i915_handle_vblank(struct drm_device
*dev
,
3173 int plane
, int pipe
, u32 iir
)
3175 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3176 u32 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
3178 if (!drm_handle_vblank(dev
, pipe
))
3181 if ((iir
& flip_pending
) == 0)
3184 intel_prepare_page_flip(dev
, plane
);
3186 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3187 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3188 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3189 * the flip is completed (no longer pending). Since this doesn't raise
3190 * an interrupt per se, we watch for the change at vblank.
3192 if (I915_READ(ISR
) & flip_pending
)
3195 intel_finish_page_flip(dev
, pipe
);
3200 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
3202 struct drm_device
*dev
= (struct drm_device
*) arg
;
3203 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3204 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
3205 unsigned long irqflags
;
3207 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3208 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3209 int pipe
, ret
= IRQ_NONE
;
3211 atomic_inc(&dev_priv
->irq_received
);
3213 iir
= I915_READ(IIR
);
3215 bool irq_received
= (iir
& ~flip_mask
) != 0;
3216 bool blc_event
= false;
3218 /* Can't rely on pipestat interrupt bit in iir as it might
3219 * have been cleared after the pipestat interrupt was received.
3220 * It doesn't set the bit in iir again, but it still produces
3221 * interrupts (for non-MSI).
3223 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3224 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3225 i915_handle_error(dev
, false);
3227 for_each_pipe(pipe
) {
3228 int reg
= PIPESTAT(pipe
);
3229 pipe_stats
[pipe
] = I915_READ(reg
);
3231 /* Clear the PIPE*STAT regs before the IIR */
3232 if (pipe_stats
[pipe
] & 0x8000ffff) {
3233 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
3234 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3236 I915_WRITE(reg
, pipe_stats
[pipe
]);
3237 irq_received
= true;
3240 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3245 /* Consume port. Then clear IIR or we'll miss events */
3246 if ((I915_HAS_HOTPLUG(dev
)) &&
3247 (iir
& I915_DISPLAY_PORT_INTERRUPT
)) {
3248 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
3249 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
3251 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3254 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
3256 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
3257 POSTING_READ(PORT_HOTPLUG_STAT
);
3260 I915_WRITE(IIR
, iir
& ~flip_mask
);
3261 new_iir
= I915_READ(IIR
); /* Flush posted writes */
3263 if (iir
& I915_USER_INTERRUPT
)
3264 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
3266 for_each_pipe(pipe
) {
3271 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
3272 i915_handle_vblank(dev
, plane
, pipe
, iir
))
3273 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
3275 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
3279 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
3280 intel_opregion_asle_intr(dev
);
3282 /* With MSI, interrupts are only generated when iir
3283 * transitions from zero to nonzero. If another bit got
3284 * set while we were handling the existing iir bits, then
3285 * we would never get another interrupt.
3287 * This is fine on non-MSI as well, as if we hit this path
3288 * we avoid exiting the interrupt handler only to generate
3291 * Note that for MSI this could cause a stray interrupt report
3292 * if an interrupt landed in the time between writing IIR and
3293 * the posting read. This should be rare enough to never
3294 * trigger the 99% of 100,000 interrupts test for disabling
3299 } while (iir
& ~flip_mask
);
3301 i915_update_dri1_breadcrumb(dev
);
3306 static void i915_irq_uninstall(struct drm_device
* dev
)
3308 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3311 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
3313 if (I915_HAS_HOTPLUG(dev
)) {
3314 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3315 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3318 I915_WRITE16(HWSTAM
, 0xffff);
3319 for_each_pipe(pipe
) {
3320 /* Clear enable bits; then clear status bits */
3321 I915_WRITE(PIPESTAT(pipe
), 0);
3322 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
3324 I915_WRITE(IMR
, 0xffffffff);
3325 I915_WRITE(IER
, 0x0);
3327 I915_WRITE(IIR
, I915_READ(IIR
));
3330 static void i965_irq_preinstall(struct drm_device
* dev
)
3332 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3335 atomic_set(&dev_priv
->irq_received
, 0);
3337 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3338 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3340 I915_WRITE(HWSTAM
, 0xeffe);
3342 I915_WRITE(PIPESTAT(pipe
), 0);
3343 I915_WRITE(IMR
, 0xffffffff);
3344 I915_WRITE(IER
, 0x0);
3348 static int i965_irq_postinstall(struct drm_device
*dev
)
3350 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3353 unsigned long irqflags
;
3355 /* Unmask the interrupts that we always want on. */
3356 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
3357 I915_DISPLAY_PORT_INTERRUPT
|
3358 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
3359 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
3360 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3361 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
3362 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
3364 enable_mask
= ~dev_priv
->irq_mask
;
3365 enable_mask
&= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3366 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
3367 enable_mask
|= I915_USER_INTERRUPT
;
3370 enable_mask
|= I915_BSD_USER_INTERRUPT
;
3372 /* Interrupt setup is already guaranteed to be single-threaded, this is
3373 * just to make the assert_spin_locked check happy. */
3374 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3375 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
3376 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3379 * Enable some error detection, note the instruction error mask
3380 * bit is reserved, so we leave it masked.
3383 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
3384 GM45_ERROR_MEM_PRIV
|
3385 GM45_ERROR_CP_PRIV
|
3386 I915_ERROR_MEMORY_REFRESH
);
3388 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
3389 I915_ERROR_MEMORY_REFRESH
);
3391 I915_WRITE(EMR
, error_mask
);
3393 I915_WRITE(IMR
, dev_priv
->irq_mask
);
3394 I915_WRITE(IER
, enable_mask
);
3397 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3398 POSTING_READ(PORT_HOTPLUG_EN
);
3400 i915_enable_asle_pipestat(dev
);
3405 static void i915_hpd_irq_setup(struct drm_device
*dev
)
3407 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3408 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3409 struct intel_encoder
*intel_encoder
;
3412 assert_spin_locked(&dev_priv
->irq_lock
);
3414 if (I915_HAS_HOTPLUG(dev
)) {
3415 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
3416 hotplug_en
&= ~HOTPLUG_INT_EN_MASK
;
3417 /* Note HDMI and DP share hotplug bits */
3418 /* enable bits are the same for all generations */
3419 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
3420 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
3421 hotplug_en
|= hpd_mask_i915
[intel_encoder
->hpd_pin
];
3422 /* Programming the CRT detection parameters tends
3423 to generate a spurious hotplug event about three
3424 seconds later. So just do it once.
3427 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
3428 hotplug_en
&= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK
;
3429 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
3431 /* Ignore TV since it's buggy */
3432 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
3436 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
3438 struct drm_device
*dev
= (struct drm_device
*) arg
;
3439 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3441 u32 pipe_stats
[I915_MAX_PIPES
];
3442 unsigned long irqflags
;
3444 int ret
= IRQ_NONE
, pipe
;
3446 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3447 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3449 atomic_inc(&dev_priv
->irq_received
);
3451 iir
= I915_READ(IIR
);
3454 bool blc_event
= false;
3456 irq_received
= (iir
& ~flip_mask
) != 0;
3458 /* Can't rely on pipestat interrupt bit in iir as it might
3459 * have been cleared after the pipestat interrupt was received.
3460 * It doesn't set the bit in iir again, but it still produces
3461 * interrupts (for non-MSI).
3463 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3464 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3465 i915_handle_error(dev
, false);
3467 for_each_pipe(pipe
) {
3468 int reg
= PIPESTAT(pipe
);
3469 pipe_stats
[pipe
] = I915_READ(reg
);
3472 * Clear the PIPE*STAT regs before the IIR
3474 if (pipe_stats
[pipe
] & 0x8000ffff) {
3475 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
3476 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3478 I915_WRITE(reg
, pipe_stats
[pipe
]);
3482 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3489 /* Consume port. Then clear IIR or we'll miss events */
3490 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
3491 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
3492 u32 hotplug_trigger
= hotplug_status
& (IS_G4X(dev
) ?
3493 HOTPLUG_INT_STATUS_G4X
:
3494 HOTPLUG_INT_STATUS_I915
);
3496 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3499 intel_hpd_irq_handler(dev
, hotplug_trigger
,
3500 IS_G4X(dev
) ? hpd_status_gen4
: hpd_status_i915
);
3502 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
3503 I915_READ(PORT_HOTPLUG_STAT
);
3506 I915_WRITE(IIR
, iir
& ~flip_mask
);
3507 new_iir
= I915_READ(IIR
); /* Flush posted writes */
3509 if (iir
& I915_USER_INTERRUPT
)
3510 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
3511 if (iir
& I915_BSD_USER_INTERRUPT
)
3512 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
3514 for_each_pipe(pipe
) {
3515 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
3516 i915_handle_vblank(dev
, pipe
, pipe
, iir
))
3517 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
3519 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
3524 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
3525 intel_opregion_asle_intr(dev
);
3527 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
3528 gmbus_irq_handler(dev
);
3530 /* With MSI, interrupts are only generated when iir
3531 * transitions from zero to nonzero. If another bit got
3532 * set while we were handling the existing iir bits, then
3533 * we would never get another interrupt.
3535 * This is fine on non-MSI as well, as if we hit this path
3536 * we avoid exiting the interrupt handler only to generate
3539 * Note that for MSI this could cause a stray interrupt report
3540 * if an interrupt landed in the time between writing IIR and
3541 * the posting read. This should be rare enough to never
3542 * trigger the 99% of 100,000 interrupts test for disabling
3548 i915_update_dri1_breadcrumb(dev
);
3553 static void i965_irq_uninstall(struct drm_device
* dev
)
3555 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3561 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
3563 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3564 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3566 I915_WRITE(HWSTAM
, 0xffffffff);
3568 I915_WRITE(PIPESTAT(pipe
), 0);
3569 I915_WRITE(IMR
, 0xffffffff);
3570 I915_WRITE(IER
, 0x0);
3573 I915_WRITE(PIPESTAT(pipe
),
3574 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
3575 I915_WRITE(IIR
, I915_READ(IIR
));
3578 static void i915_reenable_hotplug_timer_func(unsigned long data
)
3580 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*)data
;
3581 struct drm_device
*dev
= dev_priv
->dev
;
3582 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3583 unsigned long irqflags
;
3586 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3587 for (i
= (HPD_NONE
+ 1); i
< HPD_NUM_PINS
; i
++) {
3588 struct drm_connector
*connector
;
3590 if (dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_DISABLED
)
3593 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3595 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3596 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3598 if (intel_connector
->encoder
->hpd_pin
== i
) {
3599 if (connector
->polled
!= intel_connector
->polled
)
3600 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3601 drm_get_connector_name(connector
));
3602 connector
->polled
= intel_connector
->polled
;
3603 if (!connector
->polled
)
3604 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3608 if (dev_priv
->display
.hpd_irq_setup
)
3609 dev_priv
->display
.hpd_irq_setup(dev
);
3610 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3613 void intel_irq_init(struct drm_device
*dev
)
3615 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3617 INIT_WORK(&dev_priv
->hotplug_work
, i915_hotplug_work_func
);
3618 INIT_WORK(&dev_priv
->gpu_error
.work
, i915_error_work_func
);
3619 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
3620 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
3622 setup_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
3623 i915_hangcheck_elapsed
,
3624 (unsigned long) dev
);
3625 setup_timer(&dev_priv
->hotplug_reenable_timer
, i915_reenable_hotplug_timer_func
,
3626 (unsigned long) dev_priv
);
3628 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
, PM_QOS_DEFAULT_VALUE
);
3630 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
3631 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
3632 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
3633 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
3634 dev
->driver
->get_vblank_counter
= gm45_get_vblank_counter
;
3637 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3638 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
3640 dev
->driver
->get_vblank_timestamp
= NULL
;
3641 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
3643 if (IS_VALLEYVIEW(dev
)) {
3644 dev
->driver
->irq_handler
= valleyview_irq_handler
;
3645 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
3646 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
3647 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
3648 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
3649 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
3650 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3651 } else if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
3652 /* Share uninstall handlers with ILK/SNB */
3653 dev
->driver
->irq_handler
= ivybridge_irq_handler
;
3654 dev
->driver
->irq_preinstall
= ivybridge_irq_preinstall
;
3655 dev
->driver
->irq_postinstall
= ivybridge_irq_postinstall
;
3656 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
3657 dev
->driver
->enable_vblank
= ivybridge_enable_vblank
;
3658 dev
->driver
->disable_vblank
= ivybridge_disable_vblank
;
3659 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
3660 } else if (HAS_PCH_SPLIT(dev
)) {
3661 dev
->driver
->irq_handler
= ironlake_irq_handler
;
3662 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
3663 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
3664 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
3665 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
3666 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
3667 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
3669 if (INTEL_INFO(dev
)->gen
== 2) {
3670 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
3671 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
3672 dev
->driver
->irq_handler
= i8xx_irq_handler
;
3673 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
3674 } else if (INTEL_INFO(dev
)->gen
== 3) {
3675 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
3676 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
3677 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
3678 dev
->driver
->irq_handler
= i915_irq_handler
;
3679 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3681 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
3682 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
3683 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
3684 dev
->driver
->irq_handler
= i965_irq_handler
;
3685 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3687 dev
->driver
->enable_vblank
= i915_enable_vblank
;
3688 dev
->driver
->disable_vblank
= i915_disable_vblank
;
3692 void intel_hpd_init(struct drm_device
*dev
)
3694 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3695 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3696 struct drm_connector
*connector
;
3697 unsigned long irqflags
;
3700 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
3701 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
3702 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3704 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3705 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3706 connector
->polled
= intel_connector
->polled
;
3707 if (!connector
->polled
&& I915_HAS_HOTPLUG(dev
) && intel_connector
->encoder
->hpd_pin
> HPD_NONE
)
3708 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3711 /* Interrupt setup is already guaranteed to be single-threaded, this is
3712 * just to make the assert_spin_locked checks happy. */
3713 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3714 if (dev_priv
->display
.hpd_irq_setup
)
3715 dev_priv
->display
.hpd_irq_setup(dev
);
3716 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);