1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
34 #include <drm/i915_drm.h>
36 #include "i915_trace.h"
37 #include "intel_drv.h"
39 static const u32 hpd_ibx
[] = {
40 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
41 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
42 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
43 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
44 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
47 static const u32 hpd_cpt
[] = {
48 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
49 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG_CPT
,
50 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
51 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
52 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
55 static const u32 hpd_mask_i915
[] = {
56 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
57 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
58 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
59 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
60 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
61 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
64 static const u32 hpd_status_gen4
[] = {
65 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
66 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
67 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
68 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
69 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
70 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
73 static const u32 hpd_status_i915
[] = { /* i915 and valleyview are the same */
74 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
75 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
76 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
77 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
78 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
79 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
82 /* For display hotplug interrupt */
84 ironlake_enable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
86 assert_spin_locked(&dev_priv
->irq_lock
);
88 if (dev_priv
->pc8
.irqs_disabled
) {
89 WARN(1, "IRQs disabled\n");
90 dev_priv
->pc8
.regsave
.deimr
&= ~mask
;
94 if ((dev_priv
->irq_mask
& mask
) != 0) {
95 dev_priv
->irq_mask
&= ~mask
;
96 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
102 ironlake_disable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
104 assert_spin_locked(&dev_priv
->irq_lock
);
106 if (dev_priv
->pc8
.irqs_disabled
) {
107 WARN(1, "IRQs disabled\n");
108 dev_priv
->pc8
.regsave
.deimr
|= mask
;
112 if ((dev_priv
->irq_mask
& mask
) != mask
) {
113 dev_priv
->irq_mask
|= mask
;
114 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
120 * ilk_update_gt_irq - update GTIMR
121 * @dev_priv: driver private
122 * @interrupt_mask: mask of interrupt bits to update
123 * @enabled_irq_mask: mask of interrupt bits to enable
125 static void ilk_update_gt_irq(struct drm_i915_private
*dev_priv
,
126 uint32_t interrupt_mask
,
127 uint32_t enabled_irq_mask
)
129 assert_spin_locked(&dev_priv
->irq_lock
);
131 if (dev_priv
->pc8
.irqs_disabled
) {
132 WARN(1, "IRQs disabled\n");
133 dev_priv
->pc8
.regsave
.gtimr
&= ~interrupt_mask
;
134 dev_priv
->pc8
.regsave
.gtimr
|= (~enabled_irq_mask
&
139 dev_priv
->gt_irq_mask
&= ~interrupt_mask
;
140 dev_priv
->gt_irq_mask
|= (~enabled_irq_mask
& interrupt_mask
);
141 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
145 void ilk_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
147 ilk_update_gt_irq(dev_priv
, mask
, mask
);
150 void ilk_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
152 ilk_update_gt_irq(dev_priv
, mask
, 0);
156 * snb_update_pm_irq - update GEN6_PMIMR
157 * @dev_priv: driver private
158 * @interrupt_mask: mask of interrupt bits to update
159 * @enabled_irq_mask: mask of interrupt bits to enable
161 static void snb_update_pm_irq(struct drm_i915_private
*dev_priv
,
162 uint32_t interrupt_mask
,
163 uint32_t enabled_irq_mask
)
167 assert_spin_locked(&dev_priv
->irq_lock
);
169 if (dev_priv
->pc8
.irqs_disabled
) {
170 WARN(1, "IRQs disabled\n");
171 dev_priv
->pc8
.regsave
.gen6_pmimr
&= ~interrupt_mask
;
172 dev_priv
->pc8
.regsave
.gen6_pmimr
|= (~enabled_irq_mask
&
177 new_val
= dev_priv
->pm_irq_mask
;
178 new_val
&= ~interrupt_mask
;
179 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
181 if (new_val
!= dev_priv
->pm_irq_mask
) {
182 dev_priv
->pm_irq_mask
= new_val
;
183 I915_WRITE(GEN6_PMIMR
, dev_priv
->pm_irq_mask
);
184 POSTING_READ(GEN6_PMIMR
);
188 void snb_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
190 snb_update_pm_irq(dev_priv
, mask
, mask
);
193 void snb_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
195 snb_update_pm_irq(dev_priv
, mask
, 0);
198 static bool ivb_can_enable_err_int(struct drm_device
*dev
)
200 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
201 struct intel_crtc
*crtc
;
204 assert_spin_locked(&dev_priv
->irq_lock
);
206 for_each_pipe(pipe
) {
207 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
209 if (crtc
->cpu_fifo_underrun_disabled
)
216 static bool cpt_can_enable_serr_int(struct drm_device
*dev
)
218 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
220 struct intel_crtc
*crtc
;
222 assert_spin_locked(&dev_priv
->irq_lock
);
224 for_each_pipe(pipe
) {
225 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
227 if (crtc
->pch_fifo_underrun_disabled
)
234 static void ironlake_set_fifo_underrun_reporting(struct drm_device
*dev
,
235 enum pipe pipe
, bool enable
)
237 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
238 uint32_t bit
= (pipe
== PIPE_A
) ? DE_PIPEA_FIFO_UNDERRUN
:
239 DE_PIPEB_FIFO_UNDERRUN
;
242 ironlake_enable_display_irq(dev_priv
, bit
);
244 ironlake_disable_display_irq(dev_priv
, bit
);
247 static void ivybridge_set_fifo_underrun_reporting(struct drm_device
*dev
,
248 enum pipe pipe
, bool enable
)
250 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
252 I915_WRITE(GEN7_ERR_INT
, ERR_INT_FIFO_UNDERRUN(pipe
));
254 if (!ivb_can_enable_err_int(dev
))
257 ironlake_enable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
259 bool was_enabled
= !(I915_READ(DEIMR
) & DE_ERR_INT_IVB
);
261 /* Change the state _after_ we've read out the current one. */
262 ironlake_disable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
265 (I915_READ(GEN7_ERR_INT
) & ERR_INT_FIFO_UNDERRUN(pipe
))) {
266 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
273 * ibx_display_interrupt_update - update SDEIMR
274 * @dev_priv: driver private
275 * @interrupt_mask: mask of interrupt bits to update
276 * @enabled_irq_mask: mask of interrupt bits to enable
278 static void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
279 uint32_t interrupt_mask
,
280 uint32_t enabled_irq_mask
)
282 uint32_t sdeimr
= I915_READ(SDEIMR
);
283 sdeimr
&= ~interrupt_mask
;
284 sdeimr
|= (~enabled_irq_mask
& interrupt_mask
);
286 assert_spin_locked(&dev_priv
->irq_lock
);
288 if (dev_priv
->pc8
.irqs_disabled
&&
289 (interrupt_mask
& SDE_HOTPLUG_MASK_CPT
)) {
290 WARN(1, "IRQs disabled\n");
291 dev_priv
->pc8
.regsave
.sdeimr
&= ~interrupt_mask
;
292 dev_priv
->pc8
.regsave
.sdeimr
|= (~enabled_irq_mask
&
297 I915_WRITE(SDEIMR
, sdeimr
);
298 POSTING_READ(SDEIMR
);
300 #define ibx_enable_display_interrupt(dev_priv, bits) \
301 ibx_display_interrupt_update((dev_priv), (bits), (bits))
302 #define ibx_disable_display_interrupt(dev_priv, bits) \
303 ibx_display_interrupt_update((dev_priv), (bits), 0)
305 static void ibx_set_fifo_underrun_reporting(struct drm_device
*dev
,
306 enum transcoder pch_transcoder
,
309 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
310 uint32_t bit
= (pch_transcoder
== TRANSCODER_A
) ?
311 SDE_TRANSA_FIFO_UNDER
: SDE_TRANSB_FIFO_UNDER
;
314 ibx_enable_display_interrupt(dev_priv
, bit
);
316 ibx_disable_display_interrupt(dev_priv
, bit
);
319 static void cpt_set_fifo_underrun_reporting(struct drm_device
*dev
,
320 enum transcoder pch_transcoder
,
323 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
327 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
));
329 if (!cpt_can_enable_serr_int(dev
))
332 ibx_enable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
334 uint32_t tmp
= I915_READ(SERR_INT
);
335 bool was_enabled
= !(I915_READ(SDEIMR
) & SDE_ERROR_CPT
);
337 /* Change the state _after_ we've read out the current one. */
338 ibx_disable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
341 (tmp
& SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
))) {
342 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
343 transcoder_name(pch_transcoder
));
349 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
352 * @enable: true if we want to report FIFO underrun errors, false otherwise
354 * This function makes us disable or enable CPU fifo underruns for a specific
355 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
356 * reporting for one pipe may also disable all the other CPU error interruts for
357 * the other pipes, due to the fact that there's just one interrupt mask/enable
358 * bit for all the pipes.
360 * Returns the previous state of underrun reporting.
362 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device
*dev
,
363 enum pipe pipe
, bool enable
)
365 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
366 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
367 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
371 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
373 ret
= !intel_crtc
->cpu_fifo_underrun_disabled
;
378 intel_crtc
->cpu_fifo_underrun_disabled
= !enable
;
380 if (IS_GEN5(dev
) || IS_GEN6(dev
))
381 ironlake_set_fifo_underrun_reporting(dev
, pipe
, enable
);
382 else if (IS_GEN7(dev
))
383 ivybridge_set_fifo_underrun_reporting(dev
, pipe
, enable
);
386 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
391 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
393 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
394 * @enable: true if we want to report FIFO underrun errors, false otherwise
396 * This function makes us disable or enable PCH fifo underruns for a specific
397 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
398 * underrun reporting for one transcoder may also disable all the other PCH
399 * error interruts for the other transcoders, due to the fact that there's just
400 * one interrupt mask/enable bit for all the transcoders.
402 * Returns the previous state of underrun reporting.
404 bool intel_set_pch_fifo_underrun_reporting(struct drm_device
*dev
,
405 enum transcoder pch_transcoder
,
408 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
409 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pch_transcoder
];
410 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
415 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
416 * has only one pch transcoder A that all pipes can use. To avoid racy
417 * pch transcoder -> pipe lookups from interrupt code simply store the
418 * underrun statistics in crtc A. Since we never expose this anywhere
419 * nor use it outside of the fifo underrun code here using the "wrong"
420 * crtc on LPT won't cause issues.
423 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
425 ret
= !intel_crtc
->pch_fifo_underrun_disabled
;
430 intel_crtc
->pch_fifo_underrun_disabled
= !enable
;
432 if (HAS_PCH_IBX(dev
))
433 ibx_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
435 cpt_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
438 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
444 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
446 u32 reg
= PIPESTAT(pipe
);
447 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
449 assert_spin_locked(&dev_priv
->irq_lock
);
451 if ((pipestat
& mask
) == mask
)
454 /* Enable the interrupt, clear any pending status */
455 pipestat
|= mask
| (mask
>> 16);
456 I915_WRITE(reg
, pipestat
);
461 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
463 u32 reg
= PIPESTAT(pipe
);
464 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
466 assert_spin_locked(&dev_priv
->irq_lock
);
468 if ((pipestat
& mask
) == 0)
472 I915_WRITE(reg
, pipestat
);
477 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
479 static void i915_enable_asle_pipestat(struct drm_device
*dev
)
481 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
482 unsigned long irqflags
;
484 if (!dev_priv
->opregion
.asle
|| !IS_MOBILE(dev
))
487 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
489 i915_enable_pipestat(dev_priv
, 1, PIPE_LEGACY_BLC_EVENT_ENABLE
);
490 if (INTEL_INFO(dev
)->gen
>= 4)
491 i915_enable_pipestat(dev_priv
, 0, PIPE_LEGACY_BLC_EVENT_ENABLE
);
493 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
497 * i915_pipe_enabled - check if a pipe is enabled
499 * @pipe: pipe to check
501 * Reading certain registers when the pipe is disabled can hang the chip.
502 * Use this routine to make sure the PLL is running and the pipe is active
503 * before reading such registers if unsure.
506 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
508 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
510 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
511 /* Locking is horribly broken here, but whatever. */
512 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
513 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
515 return intel_crtc
->active
;
517 return I915_READ(PIPECONF(pipe
)) & PIPECONF_ENABLE
;
521 /* Called from drm generic code, passed a 'crtc', which
522 * we use as a pipe index
524 static u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
526 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
527 unsigned long high_frame
;
528 unsigned long low_frame
;
529 u32 high1
, high2
, low
, pixel
, vbl_start
;
531 if (!i915_pipe_enabled(dev
, pipe
)) {
532 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
533 "pipe %c\n", pipe_name(pipe
));
537 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
538 struct intel_crtc
*intel_crtc
=
539 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
540 const struct drm_display_mode
*mode
=
541 &intel_crtc
->config
.adjusted_mode
;
543 vbl_start
= mode
->crtc_vblank_start
* mode
->crtc_htotal
;
545 enum transcoder cpu_transcoder
=
546 intel_pipe_to_cpu_transcoder(dev_priv
, pipe
);
549 htotal
= ((I915_READ(HTOTAL(cpu_transcoder
)) >> 16) & 0x1fff) + 1;
550 vbl_start
= (I915_READ(VBLANK(cpu_transcoder
)) & 0x1fff) + 1;
555 high_frame
= PIPEFRAME(pipe
);
556 low_frame
= PIPEFRAMEPIXEL(pipe
);
559 * High & low register fields aren't synchronized, so make sure
560 * we get a low value that's stable across two reads of the high
564 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
565 low
= I915_READ(low_frame
);
566 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
567 } while (high1
!= high2
);
569 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
570 pixel
= low
& PIPE_PIXEL_MASK
;
571 low
>>= PIPE_FRAME_LOW_SHIFT
;
574 * The frame counter increments at beginning of active.
575 * Cook up a vblank counter by also checking the pixel
576 * counter against vblank start.
578 return ((high1
<< 8) | low
) + (pixel
>= vbl_start
);
581 static u32
gm45_get_vblank_counter(struct drm_device
*dev
, int pipe
)
583 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
584 int reg
= PIPE_FRMCOUNT_GM45(pipe
);
586 if (!i915_pipe_enabled(dev
, pipe
)) {
587 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
588 "pipe %c\n", pipe_name(pipe
));
592 return I915_READ(reg
);
595 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, int pipe
,
596 int *vpos
, int *hpos
)
598 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
599 u32 vbl
= 0, position
= 0;
600 int vbl_start
, vbl_end
, htotal
, vtotal
;
603 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
606 if (!i915_pipe_enabled(dev
, pipe
)) {
607 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
608 "pipe %c\n", pipe_name(pipe
));
613 vtotal
= 1 + ((I915_READ(VTOTAL(cpu_transcoder
)) >> 16) & 0x1fff);
615 if (INTEL_INFO(dev
)->gen
>= 4) {
616 /* No obvious pixelcount register. Only query vertical
617 * scanout position from Display scan line register.
619 position
= I915_READ(PIPEDSL(pipe
));
621 /* Decode into vertical scanout position. Don't have
622 * horizontal scanout position.
624 *vpos
= position
& 0x1fff;
627 /* Have access to pixelcount since start of frame.
628 * We can split this into vertical and horizontal
631 position
= (I915_READ(PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
633 htotal
= 1 + ((I915_READ(HTOTAL(cpu_transcoder
)) >> 16) & 0x1fff);
634 *vpos
= position
/ htotal
;
635 *hpos
= position
- (*vpos
* htotal
);
638 /* Query vblank area. */
639 vbl
= I915_READ(VBLANK(cpu_transcoder
));
641 /* Test position against vblank region. */
642 vbl_start
= vbl
& 0x1fff;
643 vbl_end
= (vbl
>> 16) & 0x1fff;
645 if ((*vpos
< vbl_start
) || (*vpos
> vbl_end
))
648 /* Inside "upper part" of vblank area? Apply corrective offset: */
649 if (in_vbl
&& (*vpos
>= vbl_start
))
650 *vpos
= *vpos
- vtotal
;
652 /* Readouts valid? */
654 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
658 ret
|= DRM_SCANOUTPOS_INVBL
;
663 static int i915_get_vblank_timestamp(struct drm_device
*dev
, int pipe
,
665 struct timeval
*vblank_time
,
668 struct drm_crtc
*crtc
;
670 if (pipe
< 0 || pipe
>= INTEL_INFO(dev
)->num_pipes
) {
671 DRM_ERROR("Invalid crtc %d\n", pipe
);
675 /* Get drm_crtc to timestamp: */
676 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
678 DRM_ERROR("Invalid crtc %d\n", pipe
);
682 if (!crtc
->enabled
) {
683 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
687 /* Helper routine in DRM core does all the work: */
688 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
693 static bool intel_hpd_irq_event(struct drm_device
*dev
,
694 struct drm_connector
*connector
)
696 enum drm_connector_status old_status
;
698 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
699 old_status
= connector
->status
;
701 connector
->status
= connector
->funcs
->detect(connector
, false);
702 if (old_status
== connector
->status
)
705 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
707 drm_get_connector_name(connector
),
708 drm_get_connector_status_name(old_status
),
709 drm_get_connector_status_name(connector
->status
));
715 * Handle hotplug events outside the interrupt handler proper.
717 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
719 static void i915_hotplug_work_func(struct work_struct
*work
)
721 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
723 struct drm_device
*dev
= dev_priv
->dev
;
724 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
725 struct intel_connector
*intel_connector
;
726 struct intel_encoder
*intel_encoder
;
727 struct drm_connector
*connector
;
728 unsigned long irqflags
;
729 bool hpd_disabled
= false;
730 bool changed
= false;
733 /* HPD irq before everything is fully set up. */
734 if (!dev_priv
->enable_hotplug_processing
)
737 mutex_lock(&mode_config
->mutex
);
738 DRM_DEBUG_KMS("running encoder hotplug functions\n");
740 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
742 hpd_event_bits
= dev_priv
->hpd_event_bits
;
743 dev_priv
->hpd_event_bits
= 0;
744 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
745 intel_connector
= to_intel_connector(connector
);
746 intel_encoder
= intel_connector
->encoder
;
747 if (intel_encoder
->hpd_pin
> HPD_NONE
&&
748 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_MARK_DISABLED
&&
749 connector
->polled
== DRM_CONNECTOR_POLL_HPD
) {
750 DRM_INFO("HPD interrupt storm detected on connector %s: "
751 "switching from hotplug detection to polling\n",
752 drm_get_connector_name(connector
));
753 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
= HPD_DISABLED
;
754 connector
->polled
= DRM_CONNECTOR_POLL_CONNECT
755 | DRM_CONNECTOR_POLL_DISCONNECT
;
758 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
759 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
760 drm_get_connector_name(connector
), intel_encoder
->hpd_pin
);
763 /* if there were no outputs to poll, poll was disabled,
764 * therefore make sure it's enabled when disabling HPD on
767 drm_kms_helper_poll_enable(dev
);
768 mod_timer(&dev_priv
->hotplug_reenable_timer
,
769 jiffies
+ msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY
));
772 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
774 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
775 intel_connector
= to_intel_connector(connector
);
776 intel_encoder
= intel_connector
->encoder
;
777 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
778 if (intel_encoder
->hot_plug
)
779 intel_encoder
->hot_plug(intel_encoder
);
780 if (intel_hpd_irq_event(dev
, connector
))
784 mutex_unlock(&mode_config
->mutex
);
787 drm_kms_helper_hotplug_event(dev
);
790 static void ironlake_rps_change_irq_handler(struct drm_device
*dev
)
792 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
793 u32 busy_up
, busy_down
, max_avg
, min_avg
;
796 spin_lock(&mchdev_lock
);
798 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
800 new_delay
= dev_priv
->ips
.cur_delay
;
802 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
803 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
804 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
805 max_avg
= I915_READ(RCBMAXAVG
);
806 min_avg
= I915_READ(RCBMINAVG
);
808 /* Handle RCS change request from hw */
809 if (busy_up
> max_avg
) {
810 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
811 new_delay
= dev_priv
->ips
.cur_delay
- 1;
812 if (new_delay
< dev_priv
->ips
.max_delay
)
813 new_delay
= dev_priv
->ips
.max_delay
;
814 } else if (busy_down
< min_avg
) {
815 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
816 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
817 if (new_delay
> dev_priv
->ips
.min_delay
)
818 new_delay
= dev_priv
->ips
.min_delay
;
821 if (ironlake_set_drps(dev
, new_delay
))
822 dev_priv
->ips
.cur_delay
= new_delay
;
824 spin_unlock(&mchdev_lock
);
829 static void notify_ring(struct drm_device
*dev
,
830 struct intel_ring_buffer
*ring
)
832 if (ring
->obj
== NULL
)
835 trace_i915_gem_request_complete(ring
);
837 wake_up_all(&ring
->irq_queue
);
838 i915_queue_hangcheck(dev
);
841 static void gen6_pm_rps_work(struct work_struct
*work
)
843 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
848 spin_lock_irq(&dev_priv
->irq_lock
);
849 pm_iir
= dev_priv
->rps
.pm_iir
;
850 dev_priv
->rps
.pm_iir
= 0;
851 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
852 snb_enable_pm_irq(dev_priv
, GEN6_PM_RPS_EVENTS
);
853 spin_unlock_irq(&dev_priv
->irq_lock
);
855 /* Make sure we didn't queue anything we're not going to process. */
856 WARN_ON(pm_iir
& ~GEN6_PM_RPS_EVENTS
);
858 if ((pm_iir
& GEN6_PM_RPS_EVENTS
) == 0)
861 mutex_lock(&dev_priv
->rps
.hw_lock
);
863 adj
= dev_priv
->rps
.last_adj
;
864 if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
) {
869 new_delay
= dev_priv
->rps
.cur_delay
+ adj
;
872 * For better performance, jump directly
873 * to RPe if we're below it.
875 if (new_delay
< dev_priv
->rps
.rpe_delay
)
876 new_delay
= dev_priv
->rps
.rpe_delay
;
877 } else if (pm_iir
& GEN6_PM_RP_DOWN_TIMEOUT
) {
878 if (dev_priv
->rps
.cur_delay
> dev_priv
->rps
.rpe_delay
)
879 new_delay
= dev_priv
->rps
.rpe_delay
;
881 new_delay
= dev_priv
->rps
.min_delay
;
883 } else if (pm_iir
& GEN6_PM_RP_DOWN_THRESHOLD
) {
888 new_delay
= dev_priv
->rps
.cur_delay
+ adj
;
889 } else { /* unknown event */
890 new_delay
= dev_priv
->rps
.cur_delay
;
893 /* sysfs frequency interfaces may have snuck in while servicing the
896 if (new_delay
< (int)dev_priv
->rps
.min_delay
)
897 new_delay
= dev_priv
->rps
.min_delay
;
898 if (new_delay
> (int)dev_priv
->rps
.max_delay
)
899 new_delay
= dev_priv
->rps
.max_delay
;
900 dev_priv
->rps
.last_adj
= new_delay
- dev_priv
->rps
.cur_delay
;
902 if (IS_VALLEYVIEW(dev_priv
->dev
))
903 valleyview_set_rps(dev_priv
->dev
, new_delay
);
905 gen6_set_rps(dev_priv
->dev
, new_delay
);
907 mutex_unlock(&dev_priv
->rps
.hw_lock
);
912 * ivybridge_parity_work - Workqueue called when a parity error interrupt
914 * @work: workqueue struct
916 * Doesn't actually do anything except notify userspace. As a consequence of
917 * this event, userspace should try to remap the bad rows since statistically
918 * it is likely the same row is more likely to go bad again.
920 static void ivybridge_parity_work(struct work_struct
*work
)
922 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
923 l3_parity
.error_work
);
924 u32 error_status
, row
, bank
, subbank
;
925 char *parity_event
[6];
930 /* We must turn off DOP level clock gating to access the L3 registers.
931 * In order to prevent a get/put style interface, acquire struct mutex
932 * any time we access those registers.
934 mutex_lock(&dev_priv
->dev
->struct_mutex
);
936 /* If we've screwed up tracking, just let the interrupt fire again */
937 if (WARN_ON(!dev_priv
->l3_parity
.which_slice
))
940 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
941 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
942 POSTING_READ(GEN7_MISCCPCTL
);
944 while ((slice
= ffs(dev_priv
->l3_parity
.which_slice
)) != 0) {
948 if (WARN_ON_ONCE(slice
>= NUM_L3_SLICES(dev_priv
->dev
)))
951 dev_priv
->l3_parity
.which_slice
&= ~(1<<slice
);
953 reg
= GEN7_L3CDERRST1
+ (slice
* 0x200);
955 error_status
= I915_READ(reg
);
956 row
= GEN7_PARITY_ERROR_ROW(error_status
);
957 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
958 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
960 I915_WRITE(reg
, GEN7_PARITY_ERROR_VALID
| GEN7_L3CDERRST1_ENABLE
);
963 parity_event
[0] = I915_L3_PARITY_UEVENT
"=1";
964 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
965 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
966 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
967 parity_event
[4] = kasprintf(GFP_KERNEL
, "SLICE=%d", slice
);
968 parity_event
[5] = NULL
;
970 kobject_uevent_env(&dev_priv
->dev
->primary
->kdev
.kobj
,
971 KOBJ_CHANGE
, parity_event
);
973 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
974 slice
, row
, bank
, subbank
);
976 kfree(parity_event
[4]);
977 kfree(parity_event
[3]);
978 kfree(parity_event
[2]);
979 kfree(parity_event
[1]);
982 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
985 WARN_ON(dev_priv
->l3_parity
.which_slice
);
986 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
987 ilk_enable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev_priv
->dev
));
988 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
990 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
993 static void ivybridge_parity_error_irq_handler(struct drm_device
*dev
, u32 iir
)
995 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
997 if (!HAS_L3_DPF(dev
))
1000 spin_lock(&dev_priv
->irq_lock
);
1001 ilk_disable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev
));
1002 spin_unlock(&dev_priv
->irq_lock
);
1004 iir
&= GT_PARITY_ERROR(dev
);
1005 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1
)
1006 dev_priv
->l3_parity
.which_slice
|= 1 << 1;
1008 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT
)
1009 dev_priv
->l3_parity
.which_slice
|= 1 << 0;
1011 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
1014 static void ilk_gt_irq_handler(struct drm_device
*dev
,
1015 struct drm_i915_private
*dev_priv
,
1019 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1020 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
1021 if (gt_iir
& ILK_BSD_USER_INTERRUPT
)
1022 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1025 static void snb_gt_irq_handler(struct drm_device
*dev
,
1026 struct drm_i915_private
*dev_priv
,
1031 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1032 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
1033 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
1034 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1035 if (gt_iir
& GT_BLT_USER_INTERRUPT
)
1036 notify_ring(dev
, &dev_priv
->ring
[BCS
]);
1038 if (gt_iir
& (GT_BLT_CS_ERROR_INTERRUPT
|
1039 GT_BSD_CS_ERROR_INTERRUPT
|
1040 GT_RENDER_CS_MASTER_ERROR_INTERRUPT
)) {
1041 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir
);
1042 i915_handle_error(dev
, false);
1045 if (gt_iir
& GT_PARITY_ERROR(dev
))
1046 ivybridge_parity_error_irq_handler(dev
, gt_iir
);
1049 #define HPD_STORM_DETECT_PERIOD 1000
1050 #define HPD_STORM_THRESHOLD 5
1052 static inline void intel_hpd_irq_handler(struct drm_device
*dev
,
1053 u32 hotplug_trigger
,
1056 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1058 bool storm_detected
= false;
1060 if (!hotplug_trigger
)
1063 spin_lock(&dev_priv
->irq_lock
);
1064 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
1066 WARN(((hpd
[i
] & hotplug_trigger
) &&
1067 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
),
1068 "Received HPD interrupt although disabled\n");
1070 if (!(hpd
[i
] & hotplug_trigger
) ||
1071 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
)
1074 dev_priv
->hpd_event_bits
|= (1 << i
);
1075 if (!time_in_range(jiffies
, dev_priv
->hpd_stats
[i
].hpd_last_jiffies
,
1076 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
1077 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD
))) {
1078 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
= jiffies
;
1079 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
1080 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i
);
1081 } else if (dev_priv
->hpd_stats
[i
].hpd_cnt
> HPD_STORM_THRESHOLD
) {
1082 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_MARK_DISABLED
;
1083 dev_priv
->hpd_event_bits
&= ~(1 << i
);
1084 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i
);
1085 storm_detected
= true;
1087 dev_priv
->hpd_stats
[i
].hpd_cnt
++;
1088 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i
,
1089 dev_priv
->hpd_stats
[i
].hpd_cnt
);
1094 dev_priv
->display
.hpd_irq_setup(dev
);
1095 spin_unlock(&dev_priv
->irq_lock
);
1098 * Our hotplug handler can grab modeset locks (by calling down into the
1099 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1100 * queue for otherwise the flush_work in the pageflip code will
1103 schedule_work(&dev_priv
->hotplug_work
);
1106 static void gmbus_irq_handler(struct drm_device
*dev
)
1108 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1110 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1113 static void dp_aux_irq_handler(struct drm_device
*dev
)
1115 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1117 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1120 /* The RPS events need forcewake, so we add them to a work queue and mask their
1121 * IMR bits until the work is done. Other interrupts can be processed without
1122 * the work queue. */
1123 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1125 if (pm_iir
& GEN6_PM_RPS_EVENTS
) {
1126 spin_lock(&dev_priv
->irq_lock
);
1127 dev_priv
->rps
.pm_iir
|= pm_iir
& GEN6_PM_RPS_EVENTS
;
1128 snb_disable_pm_irq(dev_priv
, pm_iir
& GEN6_PM_RPS_EVENTS
);
1129 spin_unlock(&dev_priv
->irq_lock
);
1131 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
1134 if (HAS_VEBOX(dev_priv
->dev
)) {
1135 if (pm_iir
& PM_VEBOX_USER_INTERRUPT
)
1136 notify_ring(dev_priv
->dev
, &dev_priv
->ring
[VECS
]);
1138 if (pm_iir
& PM_VEBOX_CS_ERROR_INTERRUPT
) {
1139 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir
);
1140 i915_handle_error(dev_priv
->dev
, false);
1145 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
1147 struct drm_device
*dev
= (struct drm_device
*) arg
;
1148 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1149 u32 iir
, gt_iir
, pm_iir
;
1150 irqreturn_t ret
= IRQ_NONE
;
1151 unsigned long irqflags
;
1153 u32 pipe_stats
[I915_MAX_PIPES
];
1155 atomic_inc(&dev_priv
->irq_received
);
1158 iir
= I915_READ(VLV_IIR
);
1159 gt_iir
= I915_READ(GTIIR
);
1160 pm_iir
= I915_READ(GEN6_PMIIR
);
1162 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
1167 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1169 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1170 for_each_pipe(pipe
) {
1171 int reg
= PIPESTAT(pipe
);
1172 pipe_stats
[pipe
] = I915_READ(reg
);
1175 * Clear the PIPE*STAT regs before the IIR
1177 if (pipe_stats
[pipe
] & 0x8000ffff) {
1178 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
1179 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1181 I915_WRITE(reg
, pipe_stats
[pipe
]);
1184 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1186 for_each_pipe(pipe
) {
1187 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
)
1188 drm_handle_vblank(dev
, pipe
);
1190 if (pipe_stats
[pipe
] & PLANE_FLIPDONE_INT_STATUS_VLV
) {
1191 intel_prepare_page_flip(dev
, pipe
);
1192 intel_finish_page_flip(dev
, pipe
);
1196 /* Consume port. Then clear IIR or we'll miss events */
1197 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
1198 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1199 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
1201 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1204 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
1206 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1207 I915_READ(PORT_HOTPLUG_STAT
);
1210 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1211 gmbus_irq_handler(dev
);
1214 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1216 I915_WRITE(GTIIR
, gt_iir
);
1217 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1218 I915_WRITE(VLV_IIR
, iir
);
1225 static void ibx_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1227 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1229 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK
;
1231 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_ibx
);
1233 if (pch_iir
& SDE_AUDIO_POWER_MASK
) {
1234 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK
) >>
1235 SDE_AUDIO_POWER_SHIFT
);
1236 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1240 if (pch_iir
& SDE_AUX_MASK
)
1241 dp_aux_irq_handler(dev
);
1243 if (pch_iir
& SDE_GMBUS
)
1244 gmbus_irq_handler(dev
);
1246 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
1247 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1249 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
1250 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1252 if (pch_iir
& SDE_POISON
)
1253 DRM_ERROR("PCH poison interrupt\n");
1255 if (pch_iir
& SDE_FDI_MASK
)
1257 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1259 I915_READ(FDI_RX_IIR(pipe
)));
1261 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
1262 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1264 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
1265 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1267 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
1268 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1270 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1272 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
1273 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1275 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1278 static void ivb_err_int_handler(struct drm_device
*dev
)
1280 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1281 u32 err_int
= I915_READ(GEN7_ERR_INT
);
1283 if (err_int
& ERR_INT_POISON
)
1284 DRM_ERROR("Poison interrupt\n");
1286 if (err_int
& ERR_INT_FIFO_UNDERRUN_A
)
1287 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_A
, false))
1288 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1290 if (err_int
& ERR_INT_FIFO_UNDERRUN_B
)
1291 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_B
, false))
1292 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1294 if (err_int
& ERR_INT_FIFO_UNDERRUN_C
)
1295 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_C
, false))
1296 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1298 I915_WRITE(GEN7_ERR_INT
, err_int
);
1301 static void cpt_serr_int_handler(struct drm_device
*dev
)
1303 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1304 u32 serr_int
= I915_READ(SERR_INT
);
1306 if (serr_int
& SERR_INT_POISON
)
1307 DRM_ERROR("PCH poison interrupt\n");
1309 if (serr_int
& SERR_INT_TRANS_A_FIFO_UNDERRUN
)
1310 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1312 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1314 if (serr_int
& SERR_INT_TRANS_B_FIFO_UNDERRUN
)
1315 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1317 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1319 if (serr_int
& SERR_INT_TRANS_C_FIFO_UNDERRUN
)
1320 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_C
,
1322 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1324 I915_WRITE(SERR_INT
, serr_int
);
1327 static void cpt_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1329 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1331 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_CPT
;
1333 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_cpt
);
1335 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) {
1336 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
1337 SDE_AUDIO_POWER_SHIFT_CPT
);
1338 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1342 if (pch_iir
& SDE_AUX_MASK_CPT
)
1343 dp_aux_irq_handler(dev
);
1345 if (pch_iir
& SDE_GMBUS_CPT
)
1346 gmbus_irq_handler(dev
);
1348 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
1349 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1351 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
1352 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1354 if (pch_iir
& SDE_FDI_MASK_CPT
)
1356 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1358 I915_READ(FDI_RX_IIR(pipe
)));
1360 if (pch_iir
& SDE_ERROR_CPT
)
1361 cpt_serr_int_handler(dev
);
1364 static void ilk_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
1366 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1368 if (de_iir
& DE_AUX_CHANNEL_A
)
1369 dp_aux_irq_handler(dev
);
1371 if (de_iir
& DE_GSE
)
1372 intel_opregion_asle_intr(dev
);
1374 if (de_iir
& DE_PIPEA_VBLANK
)
1375 drm_handle_vblank(dev
, 0);
1377 if (de_iir
& DE_PIPEB_VBLANK
)
1378 drm_handle_vblank(dev
, 1);
1380 if (de_iir
& DE_POISON
)
1381 DRM_ERROR("Poison interrupt\n");
1383 if (de_iir
& DE_PIPEA_FIFO_UNDERRUN
)
1384 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_A
, false))
1385 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1387 if (de_iir
& DE_PIPEB_FIFO_UNDERRUN
)
1388 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_B
, false))
1389 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1391 if (de_iir
& DE_PLANEA_FLIP_DONE
) {
1392 intel_prepare_page_flip(dev
, 0);
1393 intel_finish_page_flip_plane(dev
, 0);
1396 if (de_iir
& DE_PLANEB_FLIP_DONE
) {
1397 intel_prepare_page_flip(dev
, 1);
1398 intel_finish_page_flip_plane(dev
, 1);
1401 /* check event from PCH */
1402 if (de_iir
& DE_PCH_EVENT
) {
1403 u32 pch_iir
= I915_READ(SDEIIR
);
1405 if (HAS_PCH_CPT(dev
))
1406 cpt_irq_handler(dev
, pch_iir
);
1408 ibx_irq_handler(dev
, pch_iir
);
1410 /* should clear PCH hotplug event before clear CPU irq */
1411 I915_WRITE(SDEIIR
, pch_iir
);
1414 if (IS_GEN5(dev
) && de_iir
& DE_PCU_EVENT
)
1415 ironlake_rps_change_irq_handler(dev
);
1418 static void ivb_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
1420 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1423 if (de_iir
& DE_ERR_INT_IVB
)
1424 ivb_err_int_handler(dev
);
1426 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
1427 dp_aux_irq_handler(dev
);
1429 if (de_iir
& DE_GSE_IVB
)
1430 intel_opregion_asle_intr(dev
);
1432 for (i
= 0; i
< 3; i
++) {
1433 if (de_iir
& (DE_PIPEA_VBLANK_IVB
<< (5 * i
)))
1434 drm_handle_vblank(dev
, i
);
1435 if (de_iir
& (DE_PLANEA_FLIP_DONE_IVB
<< (5 * i
))) {
1436 intel_prepare_page_flip(dev
, i
);
1437 intel_finish_page_flip_plane(dev
, i
);
1441 /* check event from PCH */
1442 if (!HAS_PCH_NOP(dev
) && (de_iir
& DE_PCH_EVENT_IVB
)) {
1443 u32 pch_iir
= I915_READ(SDEIIR
);
1445 cpt_irq_handler(dev
, pch_iir
);
1447 /* clear PCH hotplug event before clear CPU irq */
1448 I915_WRITE(SDEIIR
, pch_iir
);
1452 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
1454 struct drm_device
*dev
= (struct drm_device
*) arg
;
1455 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1456 u32 de_iir
, gt_iir
, de_ier
, sde_ier
= 0;
1457 irqreturn_t ret
= IRQ_NONE
;
1459 atomic_inc(&dev_priv
->irq_received
);
1461 /* We get interrupts on unclaimed registers, so check for this before we
1462 * do any I915_{READ,WRITE}. */
1463 intel_uncore_check_errors(dev
);
1465 /* disable master interrupt before clearing iir */
1466 de_ier
= I915_READ(DEIER
);
1467 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
1468 POSTING_READ(DEIER
);
1470 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1471 * interrupts will will be stored on its back queue, and then we'll be
1472 * able to process them after we restore SDEIER (as soon as we restore
1473 * it, we'll get an interrupt if SDEIIR still has something to process
1474 * due to its back queue). */
1475 if (!HAS_PCH_NOP(dev
)) {
1476 sde_ier
= I915_READ(SDEIER
);
1477 I915_WRITE(SDEIER
, 0);
1478 POSTING_READ(SDEIER
);
1481 gt_iir
= I915_READ(GTIIR
);
1483 if (INTEL_INFO(dev
)->gen
>= 6)
1484 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1486 ilk_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1487 I915_WRITE(GTIIR
, gt_iir
);
1491 de_iir
= I915_READ(DEIIR
);
1493 if (INTEL_INFO(dev
)->gen
>= 7)
1494 ivb_display_irq_handler(dev
, de_iir
);
1496 ilk_display_irq_handler(dev
, de_iir
);
1497 I915_WRITE(DEIIR
, de_iir
);
1501 if (INTEL_INFO(dev
)->gen
>= 6) {
1502 u32 pm_iir
= I915_READ(GEN6_PMIIR
);
1504 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1505 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1510 I915_WRITE(DEIER
, de_ier
);
1511 POSTING_READ(DEIER
);
1512 if (!HAS_PCH_NOP(dev
)) {
1513 I915_WRITE(SDEIER
, sde_ier
);
1514 POSTING_READ(SDEIER
);
1520 static void i915_error_wake_up(struct drm_i915_private
*dev_priv
,
1521 bool reset_completed
)
1523 struct intel_ring_buffer
*ring
;
1527 * Notify all waiters for GPU completion events that reset state has
1528 * been changed, and that they need to restart their wait after
1529 * checking for potential errors (and bail out to drop locks if there is
1530 * a gpu reset pending so that i915_error_work_func can acquire them).
1533 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
1534 for_each_ring(ring
, dev_priv
, i
)
1535 wake_up_all(&ring
->irq_queue
);
1537 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
1538 wake_up_all(&dev_priv
->pending_flip_queue
);
1541 * Signal tasks blocked in i915_gem_wait_for_error that the pending
1542 * reset state is cleared.
1544 if (reset_completed
)
1545 wake_up_all(&dev_priv
->gpu_error
.reset_queue
);
1549 * i915_error_work_func - do process context error handling work
1550 * @work: work struct
1552 * Fire an error uevent so userspace can see that a hang or error
1555 static void i915_error_work_func(struct work_struct
*work
)
1557 struct i915_gpu_error
*error
= container_of(work
, struct i915_gpu_error
,
1559 drm_i915_private_t
*dev_priv
= container_of(error
, drm_i915_private_t
,
1561 struct drm_device
*dev
= dev_priv
->dev
;
1562 char *error_event
[] = { I915_ERROR_UEVENT
"=1", NULL
};
1563 char *reset_event
[] = { I915_RESET_UEVENT
"=1", NULL
};
1564 char *reset_done_event
[] = { I915_ERROR_UEVENT
"=0", NULL
};
1567 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
, error_event
);
1570 * Note that there's only one work item which does gpu resets, so we
1571 * need not worry about concurrent gpu resets potentially incrementing
1572 * error->reset_counter twice. We only need to take care of another
1573 * racing irq/hangcheck declaring the gpu dead for a second time. A
1574 * quick check for that is good enough: schedule_work ensures the
1575 * correct ordering between hang detection and this work item, and since
1576 * the reset in-progress bit is only ever set by code outside of this
1577 * work we don't need to worry about any other races.
1579 if (i915_reset_in_progress(error
) && !i915_terminally_wedged(error
)) {
1580 DRM_DEBUG_DRIVER("resetting chip\n");
1581 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
,
1585 * All state reset _must_ be completed before we update the
1586 * reset counter, for otherwise waiters might miss the reset
1587 * pending state and not properly drop locks, resulting in
1588 * deadlocks with the reset work.
1590 ret
= i915_reset(dev
);
1592 intel_display_handle_reset(dev
);
1596 * After all the gem state is reset, increment the reset
1597 * counter and wake up everyone waiting for the reset to
1600 * Since unlock operations are a one-sided barrier only,
1601 * we need to insert a barrier here to order any seqno
1603 * the counter increment.
1605 smp_mb__before_atomic_inc();
1606 atomic_inc(&dev_priv
->gpu_error
.reset_counter
);
1608 kobject_uevent_env(&dev
->primary
->kdev
.kobj
,
1609 KOBJ_CHANGE
, reset_done_event
);
1611 atomic_set(&error
->reset_counter
, I915_WEDGED
);
1615 * Note: The wake_up also serves as a memory barrier so that
1616 * waiters see the update value of the reset counter atomic_t.
1618 i915_error_wake_up(dev_priv
, true);
1622 static void i915_report_and_clear_eir(struct drm_device
*dev
)
1624 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1625 uint32_t instdone
[I915_NUM_INSTDONE_REG
];
1626 u32 eir
= I915_READ(EIR
);
1632 pr_err("render error detected, EIR: 0x%08x\n", eir
);
1634 i915_get_extra_instdone(dev
, instdone
);
1637 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
1638 u32 ipeir
= I915_READ(IPEIR_I965
);
1640 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1641 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1642 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
1643 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
1644 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1645 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1646 I915_WRITE(IPEIR_I965
, ipeir
);
1647 POSTING_READ(IPEIR_I965
);
1649 if (eir
& GM45_ERROR_PAGE_TABLE
) {
1650 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1651 pr_err("page table error\n");
1652 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1653 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1654 POSTING_READ(PGTBL_ER
);
1658 if (!IS_GEN2(dev
)) {
1659 if (eir
& I915_ERROR_PAGE_TABLE
) {
1660 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1661 pr_err("page table error\n");
1662 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1663 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1664 POSTING_READ(PGTBL_ER
);
1668 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
1669 pr_err("memory refresh error:\n");
1671 pr_err("pipe %c stat: 0x%08x\n",
1672 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
1673 /* pipestat has already been acked */
1675 if (eir
& I915_ERROR_INSTRUCTION
) {
1676 pr_err("instruction error\n");
1677 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
1678 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
1679 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
1680 if (INTEL_INFO(dev
)->gen
< 4) {
1681 u32 ipeir
= I915_READ(IPEIR
);
1683 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
1684 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
1685 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
1686 I915_WRITE(IPEIR
, ipeir
);
1687 POSTING_READ(IPEIR
);
1689 u32 ipeir
= I915_READ(IPEIR_I965
);
1691 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1692 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1693 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1694 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1695 I915_WRITE(IPEIR_I965
, ipeir
);
1696 POSTING_READ(IPEIR_I965
);
1700 I915_WRITE(EIR
, eir
);
1702 eir
= I915_READ(EIR
);
1705 * some errors might have become stuck,
1708 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
1709 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
1710 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
1715 * i915_handle_error - handle an error interrupt
1718 * Do some basic checking of regsiter state at error interrupt time and
1719 * dump it to the syslog. Also call i915_capture_error_state() to make
1720 * sure we get a record and make it available in debugfs. Fire a uevent
1721 * so userspace knows something bad happened (should trigger collection
1722 * of a ring dump etc.).
1724 void i915_handle_error(struct drm_device
*dev
, bool wedged
)
1726 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1728 i915_capture_error_state(dev
);
1729 i915_report_and_clear_eir(dev
);
1732 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG
,
1733 &dev_priv
->gpu_error
.reset_counter
);
1736 * Wakeup waiting processes so that the reset work function
1737 * i915_error_work_func doesn't deadlock trying to grab various
1738 * locks. By bumping the reset counter first, the woken
1739 * processes will see a reset in progress and back off,
1740 * releasing their locks and then wait for the reset completion.
1741 * We must do this for _all_ gpu waiters that might hold locks
1742 * that the reset work needs to acquire.
1744 * Note: The wake_up serves as the required memory barrier to
1745 * ensure that the waiters see the updated value of the reset
1748 i915_error_wake_up(dev_priv
, false);
1752 * Our reset work can grab modeset locks (since it needs to reset the
1753 * state of outstanding pagelips). Hence it must not be run on our own
1754 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
1755 * code will deadlock.
1757 schedule_work(&dev_priv
->gpu_error
.work
);
1760 static void __always_unused
i915_pageflip_stall_check(struct drm_device
*dev
, int pipe
)
1762 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1763 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1764 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1765 struct drm_i915_gem_object
*obj
;
1766 struct intel_unpin_work
*work
;
1767 unsigned long flags
;
1768 bool stall_detected
;
1770 /* Ignore early vblank irqs */
1771 if (intel_crtc
== NULL
)
1774 spin_lock_irqsave(&dev
->event_lock
, flags
);
1775 work
= intel_crtc
->unpin_work
;
1778 atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
||
1779 !work
->enable_stall_check
) {
1780 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1781 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1785 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1786 obj
= work
->pending_flip_obj
;
1787 if (INTEL_INFO(dev
)->gen
>= 4) {
1788 int dspsurf
= DSPSURF(intel_crtc
->plane
);
1789 stall_detected
= I915_HI_DISPBASE(I915_READ(dspsurf
)) ==
1790 i915_gem_obj_ggtt_offset(obj
);
1792 int dspaddr
= DSPADDR(intel_crtc
->plane
);
1793 stall_detected
= I915_READ(dspaddr
) == (i915_gem_obj_ggtt_offset(obj
) +
1794 crtc
->y
* crtc
->fb
->pitches
[0] +
1795 crtc
->x
* crtc
->fb
->bits_per_pixel
/8);
1798 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1800 if (stall_detected
) {
1801 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1802 intel_prepare_page_flip(dev
, intel_crtc
->plane
);
1806 /* Called from drm generic code, passed 'crtc' which
1807 * we use as a pipe index
1809 static int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
1811 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1812 unsigned long irqflags
;
1814 if (!i915_pipe_enabled(dev
, pipe
))
1817 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1818 if (INTEL_INFO(dev
)->gen
>= 4)
1819 i915_enable_pipestat(dev_priv
, pipe
,
1820 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1822 i915_enable_pipestat(dev_priv
, pipe
,
1823 PIPE_VBLANK_INTERRUPT_ENABLE
);
1825 /* maintain vblank delivery even in deep C-states */
1826 if (dev_priv
->info
->gen
== 3)
1827 I915_WRITE(INSTPM
, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS
));
1828 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1833 static int ironlake_enable_vblank(struct drm_device
*dev
, int pipe
)
1835 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1836 unsigned long irqflags
;
1837 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
1838 DE_PIPE_VBLANK_ILK(pipe
);
1840 if (!i915_pipe_enabled(dev
, pipe
))
1843 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1844 ironlake_enable_display_irq(dev_priv
, bit
);
1845 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1850 static int valleyview_enable_vblank(struct drm_device
*dev
, int pipe
)
1852 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1853 unsigned long irqflags
;
1856 if (!i915_pipe_enabled(dev
, pipe
))
1859 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1860 imr
= I915_READ(VLV_IMR
);
1862 imr
&= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
1864 imr
&= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1865 I915_WRITE(VLV_IMR
, imr
);
1866 i915_enable_pipestat(dev_priv
, pipe
,
1867 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1868 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1873 /* Called from drm generic code, passed 'crtc' which
1874 * we use as a pipe index
1876 static void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
1878 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1879 unsigned long irqflags
;
1881 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1882 if (dev_priv
->info
->gen
== 3)
1883 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS
));
1885 i915_disable_pipestat(dev_priv
, pipe
,
1886 PIPE_VBLANK_INTERRUPT_ENABLE
|
1887 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1888 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1891 static void ironlake_disable_vblank(struct drm_device
*dev
, int pipe
)
1893 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1894 unsigned long irqflags
;
1895 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
1896 DE_PIPE_VBLANK_ILK(pipe
);
1898 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1899 ironlake_disable_display_irq(dev_priv
, bit
);
1900 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1903 static void valleyview_disable_vblank(struct drm_device
*dev
, int pipe
)
1905 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1906 unsigned long irqflags
;
1909 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1910 i915_disable_pipestat(dev_priv
, pipe
,
1911 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1912 imr
= I915_READ(VLV_IMR
);
1914 imr
|= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
1916 imr
|= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1917 I915_WRITE(VLV_IMR
, imr
);
1918 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1922 ring_last_seqno(struct intel_ring_buffer
*ring
)
1924 return list_entry(ring
->request_list
.prev
,
1925 struct drm_i915_gem_request
, list
)->seqno
;
1929 ring_idle(struct intel_ring_buffer
*ring
, u32 seqno
)
1931 return (list_empty(&ring
->request_list
) ||
1932 i915_seqno_passed(seqno
, ring_last_seqno(ring
)));
1935 static struct intel_ring_buffer
*
1936 semaphore_waits_for(struct intel_ring_buffer
*ring
, u32
*seqno
)
1938 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1939 u32 cmd
, ipehr
, acthd
, acthd_min
;
1941 ipehr
= I915_READ(RING_IPEHR(ring
->mmio_base
));
1942 if ((ipehr
& ~(0x3 << 16)) !=
1943 (MI_SEMAPHORE_MBOX
| MI_SEMAPHORE_COMPARE
| MI_SEMAPHORE_REGISTER
))
1946 /* ACTHD is likely pointing to the dword after the actual command,
1947 * so scan backwards until we find the MBOX.
1949 acthd
= intel_ring_get_active_head(ring
) & HEAD_ADDR
;
1950 acthd_min
= max((int)acthd
- 3 * 4, 0);
1952 cmd
= ioread32(ring
->virtual_start
+ acthd
);
1957 if (acthd
< acthd_min
)
1961 *seqno
= ioread32(ring
->virtual_start
+acthd
+4)+1;
1962 return &dev_priv
->ring
[(ring
->id
+ (((ipehr
>> 17) & 1) + 1)) % 3];
1965 static int semaphore_passed(struct intel_ring_buffer
*ring
)
1967 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1968 struct intel_ring_buffer
*signaller
;
1971 ring
->hangcheck
.deadlock
= true;
1973 signaller
= semaphore_waits_for(ring
, &seqno
);
1974 if (signaller
== NULL
|| signaller
->hangcheck
.deadlock
)
1977 /* cursory check for an unkickable deadlock */
1978 ctl
= I915_READ_CTL(signaller
);
1979 if (ctl
& RING_WAIT_SEMAPHORE
&& semaphore_passed(signaller
) < 0)
1982 return i915_seqno_passed(signaller
->get_seqno(signaller
, false), seqno
);
1985 static void semaphore_clear_deadlocks(struct drm_i915_private
*dev_priv
)
1987 struct intel_ring_buffer
*ring
;
1990 for_each_ring(ring
, dev_priv
, i
)
1991 ring
->hangcheck
.deadlock
= false;
1994 static enum intel_ring_hangcheck_action
1995 ring_stuck(struct intel_ring_buffer
*ring
, u32 acthd
)
1997 struct drm_device
*dev
= ring
->dev
;
1998 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2001 if (ring
->hangcheck
.acthd
!= acthd
)
2002 return HANGCHECK_ACTIVE
;
2005 return HANGCHECK_HUNG
;
2007 /* Is the chip hanging on a WAIT_FOR_EVENT?
2008 * If so we can simply poke the RB_WAIT bit
2009 * and break the hang. This should work on
2010 * all but the second generation chipsets.
2012 tmp
= I915_READ_CTL(ring
);
2013 if (tmp
& RING_WAIT
) {
2014 DRM_ERROR("Kicking stuck wait on %s\n",
2016 i915_handle_error(dev
, false);
2017 I915_WRITE_CTL(ring
, tmp
);
2018 return HANGCHECK_KICK
;
2021 if (INTEL_INFO(dev
)->gen
>= 6 && tmp
& RING_WAIT_SEMAPHORE
) {
2022 switch (semaphore_passed(ring
)) {
2024 return HANGCHECK_HUNG
;
2026 DRM_ERROR("Kicking stuck semaphore on %s\n",
2028 i915_handle_error(dev
, false);
2029 I915_WRITE_CTL(ring
, tmp
);
2030 return HANGCHECK_KICK
;
2032 return HANGCHECK_WAIT
;
2036 return HANGCHECK_HUNG
;
2040 * This is called when the chip hasn't reported back with completed
2041 * batchbuffers in a long time. We keep track per ring seqno progress and
2042 * if there are no progress, hangcheck score for that ring is increased.
2043 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2044 * we kick the ring. If we see no progress on three subsequent calls
2045 * we assume chip is wedged and try to fix it by resetting the chip.
2047 static void i915_hangcheck_elapsed(unsigned long data
)
2049 struct drm_device
*dev
= (struct drm_device
*)data
;
2050 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2051 struct intel_ring_buffer
*ring
;
2053 int busy_count
= 0, rings_hung
= 0;
2054 bool stuck
[I915_NUM_RINGS
] = { 0 };
2060 if (!i915_enable_hangcheck
)
2063 for_each_ring(ring
, dev_priv
, i
) {
2067 semaphore_clear_deadlocks(dev_priv
);
2069 seqno
= ring
->get_seqno(ring
, false);
2070 acthd
= intel_ring_get_active_head(ring
);
2072 if (ring
->hangcheck
.seqno
== seqno
) {
2073 if (ring_idle(ring
, seqno
)) {
2074 ring
->hangcheck
.action
= HANGCHECK_IDLE
;
2076 if (waitqueue_active(&ring
->irq_queue
)) {
2077 /* Issue a wake-up to catch stuck h/w. */
2078 if (!test_and_set_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
)) {
2079 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2081 wake_up_all(&ring
->irq_queue
);
2083 /* Safeguard against driver failure */
2084 ring
->hangcheck
.score
+= BUSY
;
2088 /* We always increment the hangcheck score
2089 * if the ring is busy and still processing
2090 * the same request, so that no single request
2091 * can run indefinitely (such as a chain of
2092 * batches). The only time we do not increment
2093 * the hangcheck score on this ring, if this
2094 * ring is in a legitimate wait for another
2095 * ring. In that case the waiting ring is a
2096 * victim and we want to be sure we catch the
2097 * right culprit. Then every time we do kick
2098 * the ring, add a small increment to the
2099 * score so that we can catch a batch that is
2100 * being repeatedly kicked and so responsible
2101 * for stalling the machine.
2103 ring
->hangcheck
.action
= ring_stuck(ring
,
2106 switch (ring
->hangcheck
.action
) {
2107 case HANGCHECK_IDLE
:
2108 case HANGCHECK_WAIT
:
2110 case HANGCHECK_ACTIVE
:
2111 ring
->hangcheck
.score
+= BUSY
;
2113 case HANGCHECK_KICK
:
2114 ring
->hangcheck
.score
+= KICK
;
2116 case HANGCHECK_HUNG
:
2117 ring
->hangcheck
.score
+= HUNG
;
2123 ring
->hangcheck
.action
= HANGCHECK_ACTIVE
;
2125 /* Gradually reduce the count so that we catch DoS
2126 * attempts across multiple batches.
2128 if (ring
->hangcheck
.score
> 0)
2129 ring
->hangcheck
.score
--;
2132 ring
->hangcheck
.seqno
= seqno
;
2133 ring
->hangcheck
.acthd
= acthd
;
2137 for_each_ring(ring
, dev_priv
, i
) {
2138 if (ring
->hangcheck
.score
> FIRE
) {
2139 DRM_INFO("%s on %s\n",
2140 stuck
[i
] ? "stuck" : "no progress",
2147 return i915_handle_error(dev
, true);
2150 /* Reset timer case chip hangs without another request
2152 i915_queue_hangcheck(dev
);
2155 void i915_queue_hangcheck(struct drm_device
*dev
)
2157 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2158 if (!i915_enable_hangcheck
)
2161 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
2162 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
2165 static void ibx_irq_preinstall(struct drm_device
*dev
)
2167 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2169 if (HAS_PCH_NOP(dev
))
2172 /* south display irq */
2173 I915_WRITE(SDEIMR
, 0xffffffff);
2175 * SDEIER is also touched by the interrupt handler to work around missed
2176 * PCH interrupts. Hence we can't update it after the interrupt handler
2177 * is enabled - instead we unconditionally enable all PCH interrupt
2178 * sources here, but then only unmask them as needed with SDEIMR.
2180 I915_WRITE(SDEIER
, 0xffffffff);
2181 POSTING_READ(SDEIER
);
2184 static void gen5_gt_irq_preinstall(struct drm_device
*dev
)
2186 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2189 I915_WRITE(GTIMR
, 0xffffffff);
2190 I915_WRITE(GTIER
, 0x0);
2191 POSTING_READ(GTIER
);
2193 if (INTEL_INFO(dev
)->gen
>= 6) {
2195 I915_WRITE(GEN6_PMIMR
, 0xffffffff);
2196 I915_WRITE(GEN6_PMIER
, 0x0);
2197 POSTING_READ(GEN6_PMIER
);
2203 static void ironlake_irq_preinstall(struct drm_device
*dev
)
2205 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2207 atomic_set(&dev_priv
->irq_received
, 0);
2209 I915_WRITE(HWSTAM
, 0xeffe);
2211 I915_WRITE(DEIMR
, 0xffffffff);
2212 I915_WRITE(DEIER
, 0x0);
2213 POSTING_READ(DEIER
);
2215 gen5_gt_irq_preinstall(dev
);
2217 ibx_irq_preinstall(dev
);
2220 static void valleyview_irq_preinstall(struct drm_device
*dev
)
2222 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2225 atomic_set(&dev_priv
->irq_received
, 0);
2228 I915_WRITE(VLV_IMR
, 0);
2229 I915_WRITE(RING_IMR(RENDER_RING_BASE
), 0);
2230 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE
), 0);
2231 I915_WRITE(RING_IMR(BLT_RING_BASE
), 0);
2234 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2235 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2237 gen5_gt_irq_preinstall(dev
);
2239 I915_WRITE(DPINVGTT
, 0xff);
2241 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2242 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2244 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2245 I915_WRITE(VLV_IIR
, 0xffffffff);
2246 I915_WRITE(VLV_IMR
, 0xffffffff);
2247 I915_WRITE(VLV_IER
, 0x0);
2248 POSTING_READ(VLV_IER
);
2251 static void ibx_hpd_irq_setup(struct drm_device
*dev
)
2253 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2254 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2255 struct intel_encoder
*intel_encoder
;
2256 u32 hotplug_irqs
, hotplug
, enabled_irqs
= 0;
2258 if (HAS_PCH_IBX(dev
)) {
2259 hotplug_irqs
= SDE_HOTPLUG_MASK
;
2260 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2261 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2262 enabled_irqs
|= hpd_ibx
[intel_encoder
->hpd_pin
];
2264 hotplug_irqs
= SDE_HOTPLUG_MASK_CPT
;
2265 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2266 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2267 enabled_irqs
|= hpd_cpt
[intel_encoder
->hpd_pin
];
2270 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
2273 * Enable digital hotplug on the PCH, and configure the DP short pulse
2274 * duration to 2ms (which is the minimum in the Display Port spec)
2276 * This register is the same on all known PCH chips.
2278 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
2279 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
2280 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
2281 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
2282 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
2283 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
2286 static void ibx_irq_postinstall(struct drm_device
*dev
)
2288 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2291 if (HAS_PCH_NOP(dev
))
2294 if (HAS_PCH_IBX(dev
)) {
2295 mask
= SDE_GMBUS
| SDE_AUX_MASK
| SDE_TRANSB_FIFO_UNDER
|
2296 SDE_TRANSA_FIFO_UNDER
| SDE_POISON
;
2298 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
| SDE_ERROR_CPT
;
2300 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2303 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2304 I915_WRITE(SDEIMR
, ~mask
);
2307 static void gen5_gt_irq_postinstall(struct drm_device
*dev
)
2309 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2310 u32 pm_irqs
, gt_irqs
;
2312 pm_irqs
= gt_irqs
= 0;
2314 dev_priv
->gt_irq_mask
= ~0;
2315 if (HAS_L3_DPF(dev
)) {
2316 /* L3 parity interrupt is always unmasked. */
2317 dev_priv
->gt_irq_mask
= ~GT_PARITY_ERROR(dev
);
2318 gt_irqs
|= GT_PARITY_ERROR(dev
);
2321 gt_irqs
|= GT_RENDER_USER_INTERRUPT
;
2323 gt_irqs
|= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
|
2324 ILK_BSD_USER_INTERRUPT
;
2326 gt_irqs
|= GT_BLT_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
;
2329 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2330 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
2331 I915_WRITE(GTIER
, gt_irqs
);
2332 POSTING_READ(GTIER
);
2334 if (INTEL_INFO(dev
)->gen
>= 6) {
2335 pm_irqs
|= GEN6_PM_RPS_EVENTS
;
2338 pm_irqs
|= PM_VEBOX_USER_INTERRUPT
;
2340 dev_priv
->pm_irq_mask
= 0xffffffff;
2341 I915_WRITE(GEN6_PMIIR
, I915_READ(GEN6_PMIIR
));
2342 I915_WRITE(GEN6_PMIMR
, dev_priv
->pm_irq_mask
);
2343 I915_WRITE(GEN6_PMIER
, pm_irqs
);
2344 POSTING_READ(GEN6_PMIER
);
2348 static int ironlake_irq_postinstall(struct drm_device
*dev
)
2350 unsigned long irqflags
;
2351 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2352 u32 display_mask
, extra_mask
;
2354 if (INTEL_INFO(dev
)->gen
>= 7) {
2355 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
|
2356 DE_PCH_EVENT_IVB
| DE_PLANEC_FLIP_DONE_IVB
|
2357 DE_PLANEB_FLIP_DONE_IVB
|
2358 DE_PLANEA_FLIP_DONE_IVB
| DE_AUX_CHANNEL_A_IVB
|
2360 extra_mask
= (DE_PIPEC_VBLANK_IVB
| DE_PIPEB_VBLANK_IVB
|
2361 DE_PIPEA_VBLANK_IVB
);
2363 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2365 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
2366 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
|
2367 DE_AUX_CHANNEL_A
| DE_PIPEB_FIFO_UNDERRUN
|
2368 DE_PIPEA_FIFO_UNDERRUN
| DE_POISON
);
2369 extra_mask
= DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
| DE_PCU_EVENT
;
2372 dev_priv
->irq_mask
= ~display_mask
;
2374 /* should always can generate irq */
2375 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2376 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
2377 I915_WRITE(DEIER
, display_mask
| extra_mask
);
2378 POSTING_READ(DEIER
);
2380 gen5_gt_irq_postinstall(dev
);
2382 ibx_irq_postinstall(dev
);
2384 if (IS_IRONLAKE_M(dev
)) {
2385 /* Enable PCU event interrupts
2387 * spinlocking not required here for correctness since interrupt
2388 * setup is guaranteed to run in single-threaded context. But we
2389 * need it to make the assert_spin_locked happy. */
2390 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2391 ironlake_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
2392 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2398 static int valleyview_irq_postinstall(struct drm_device
*dev
)
2400 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2402 u32 pipestat_enable
= PLANE_FLIP_DONE_INT_EN_VLV
;
2403 unsigned long irqflags
;
2405 enable_mask
= I915_DISPLAY_PORT_INTERRUPT
;
2406 enable_mask
|= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2407 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2408 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2409 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2412 *Leave vblank interrupts masked initially. enable/disable will
2413 * toggle them based on usage.
2415 dev_priv
->irq_mask
= (~enable_mask
) |
2416 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2417 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2419 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2420 POSTING_READ(PORT_HOTPLUG_EN
);
2422 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
2423 I915_WRITE(VLV_IER
, enable_mask
);
2424 I915_WRITE(VLV_IIR
, 0xffffffff);
2425 I915_WRITE(PIPESTAT(0), 0xffff);
2426 I915_WRITE(PIPESTAT(1), 0xffff);
2427 POSTING_READ(VLV_IER
);
2429 /* Interrupt setup is already guaranteed to be single-threaded, this is
2430 * just to make the assert_spin_locked check happy. */
2431 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2432 i915_enable_pipestat(dev_priv
, 0, pipestat_enable
);
2433 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
2434 i915_enable_pipestat(dev_priv
, 1, pipestat_enable
);
2435 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2437 I915_WRITE(VLV_IIR
, 0xffffffff);
2438 I915_WRITE(VLV_IIR
, 0xffffffff);
2440 gen5_gt_irq_postinstall(dev
);
2442 /* ack & enable invalid PTE error interrupts */
2443 #if 0 /* FIXME: add support to irq handler for checking these bits */
2444 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
2445 I915_WRITE(DPINVGTT
, DPINVGTT_EN_MASK
);
2448 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
2453 static void valleyview_irq_uninstall(struct drm_device
*dev
)
2455 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2461 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2464 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2466 I915_WRITE(HWSTAM
, 0xffffffff);
2467 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2468 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2470 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2471 I915_WRITE(VLV_IIR
, 0xffffffff);
2472 I915_WRITE(VLV_IMR
, 0xffffffff);
2473 I915_WRITE(VLV_IER
, 0x0);
2474 POSTING_READ(VLV_IER
);
2477 static void ironlake_irq_uninstall(struct drm_device
*dev
)
2479 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2484 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2486 I915_WRITE(HWSTAM
, 0xffffffff);
2488 I915_WRITE(DEIMR
, 0xffffffff);
2489 I915_WRITE(DEIER
, 0x0);
2490 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2492 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2494 I915_WRITE(GTIMR
, 0xffffffff);
2495 I915_WRITE(GTIER
, 0x0);
2496 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2498 if (HAS_PCH_NOP(dev
))
2501 I915_WRITE(SDEIMR
, 0xffffffff);
2502 I915_WRITE(SDEIER
, 0x0);
2503 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2504 if (HAS_PCH_CPT(dev
) || HAS_PCH_LPT(dev
))
2505 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2508 static void i8xx_irq_preinstall(struct drm_device
* dev
)
2510 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2513 atomic_set(&dev_priv
->irq_received
, 0);
2516 I915_WRITE(PIPESTAT(pipe
), 0);
2517 I915_WRITE16(IMR
, 0xffff);
2518 I915_WRITE16(IER
, 0x0);
2519 POSTING_READ16(IER
);
2522 static int i8xx_irq_postinstall(struct drm_device
*dev
)
2524 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2527 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2529 /* Unmask the interrupts that we always want on. */
2530 dev_priv
->irq_mask
=
2531 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2532 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2533 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2534 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2535 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2536 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
2539 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2540 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2541 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2542 I915_USER_INTERRUPT
);
2543 POSTING_READ16(IER
);
2549 * Returns true when a page flip has completed.
2551 static bool i8xx_handle_vblank(struct drm_device
*dev
,
2554 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2555 u16 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(pipe
);
2557 if (!drm_handle_vblank(dev
, pipe
))
2560 if ((iir
& flip_pending
) == 0)
2563 intel_prepare_page_flip(dev
, pipe
);
2565 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2566 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2567 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2568 * the flip is completed (no longer pending). Since this doesn't raise
2569 * an interrupt per se, we watch for the change at vblank.
2571 if (I915_READ16(ISR
) & flip_pending
)
2574 intel_finish_page_flip(dev
, pipe
);
2579 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
2581 struct drm_device
*dev
= (struct drm_device
*) arg
;
2582 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2585 unsigned long irqflags
;
2588 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2589 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2591 atomic_inc(&dev_priv
->irq_received
);
2593 iir
= I915_READ16(IIR
);
2597 while (iir
& ~flip_mask
) {
2598 /* Can't rely on pipestat interrupt bit in iir as it might
2599 * have been cleared after the pipestat interrupt was received.
2600 * It doesn't set the bit in iir again, but it still produces
2601 * interrupts (for non-MSI).
2603 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2604 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2605 i915_handle_error(dev
, false);
2607 for_each_pipe(pipe
) {
2608 int reg
= PIPESTAT(pipe
);
2609 pipe_stats
[pipe
] = I915_READ(reg
);
2612 * Clear the PIPE*STAT regs before the IIR
2614 if (pipe_stats
[pipe
] & 0x8000ffff) {
2615 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2616 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2618 I915_WRITE(reg
, pipe_stats
[pipe
]);
2621 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2623 I915_WRITE16(IIR
, iir
& ~flip_mask
);
2624 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
2626 i915_update_dri1_breadcrumb(dev
);
2628 if (iir
& I915_USER_INTERRUPT
)
2629 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2631 if (pipe_stats
[0] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2632 i8xx_handle_vblank(dev
, 0, iir
))
2633 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(0);
2635 if (pipe_stats
[1] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2636 i8xx_handle_vblank(dev
, 1, iir
))
2637 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(1);
2645 static void i8xx_irq_uninstall(struct drm_device
* dev
)
2647 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2650 for_each_pipe(pipe
) {
2651 /* Clear enable bits; then clear status bits */
2652 I915_WRITE(PIPESTAT(pipe
), 0);
2653 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
2655 I915_WRITE16(IMR
, 0xffff);
2656 I915_WRITE16(IER
, 0x0);
2657 I915_WRITE16(IIR
, I915_READ16(IIR
));
2660 static void i915_irq_preinstall(struct drm_device
* dev
)
2662 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2665 atomic_set(&dev_priv
->irq_received
, 0);
2667 if (I915_HAS_HOTPLUG(dev
)) {
2668 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2669 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2672 I915_WRITE16(HWSTAM
, 0xeffe);
2674 I915_WRITE(PIPESTAT(pipe
), 0);
2675 I915_WRITE(IMR
, 0xffffffff);
2676 I915_WRITE(IER
, 0x0);
2680 static int i915_irq_postinstall(struct drm_device
*dev
)
2682 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2685 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2687 /* Unmask the interrupts that we always want on. */
2688 dev_priv
->irq_mask
=
2689 ~(I915_ASLE_INTERRUPT
|
2690 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2691 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2692 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2693 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2694 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2697 I915_ASLE_INTERRUPT
|
2698 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2699 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2700 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2701 I915_USER_INTERRUPT
;
2703 if (I915_HAS_HOTPLUG(dev
)) {
2704 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2705 POSTING_READ(PORT_HOTPLUG_EN
);
2707 /* Enable in IER... */
2708 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
2709 /* and unmask in IMR */
2710 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
2713 I915_WRITE(IMR
, dev_priv
->irq_mask
);
2714 I915_WRITE(IER
, enable_mask
);
2717 i915_enable_asle_pipestat(dev
);
2723 * Returns true when a page flip has completed.
2725 static bool i915_handle_vblank(struct drm_device
*dev
,
2726 int plane
, int pipe
, u32 iir
)
2728 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2729 u32 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
2731 if (!drm_handle_vblank(dev
, pipe
))
2734 if ((iir
& flip_pending
) == 0)
2737 intel_prepare_page_flip(dev
, plane
);
2739 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2740 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2741 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2742 * the flip is completed (no longer pending). Since this doesn't raise
2743 * an interrupt per se, we watch for the change at vblank.
2745 if (I915_READ(ISR
) & flip_pending
)
2748 intel_finish_page_flip(dev
, pipe
);
2753 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
2755 struct drm_device
*dev
= (struct drm_device
*) arg
;
2756 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2757 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
2758 unsigned long irqflags
;
2760 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2761 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2762 int pipe
, ret
= IRQ_NONE
;
2764 atomic_inc(&dev_priv
->irq_received
);
2766 iir
= I915_READ(IIR
);
2768 bool irq_received
= (iir
& ~flip_mask
) != 0;
2769 bool blc_event
= false;
2771 /* Can't rely on pipestat interrupt bit in iir as it might
2772 * have been cleared after the pipestat interrupt was received.
2773 * It doesn't set the bit in iir again, but it still produces
2774 * interrupts (for non-MSI).
2776 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2777 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2778 i915_handle_error(dev
, false);
2780 for_each_pipe(pipe
) {
2781 int reg
= PIPESTAT(pipe
);
2782 pipe_stats
[pipe
] = I915_READ(reg
);
2784 /* Clear the PIPE*STAT regs before the IIR */
2785 if (pipe_stats
[pipe
] & 0x8000ffff) {
2786 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2787 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2789 I915_WRITE(reg
, pipe_stats
[pipe
]);
2790 irq_received
= true;
2793 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2798 /* Consume port. Then clear IIR or we'll miss events */
2799 if ((I915_HAS_HOTPLUG(dev
)) &&
2800 (iir
& I915_DISPLAY_PORT_INTERRUPT
)) {
2801 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
2802 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
2804 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2807 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
2809 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
2810 POSTING_READ(PORT_HOTPLUG_STAT
);
2813 I915_WRITE(IIR
, iir
& ~flip_mask
);
2814 new_iir
= I915_READ(IIR
); /* Flush posted writes */
2816 if (iir
& I915_USER_INTERRUPT
)
2817 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2819 for_each_pipe(pipe
) {
2824 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2825 i915_handle_vblank(dev
, plane
, pipe
, iir
))
2826 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
2828 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
2832 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
2833 intel_opregion_asle_intr(dev
);
2835 /* With MSI, interrupts are only generated when iir
2836 * transitions from zero to nonzero. If another bit got
2837 * set while we were handling the existing iir bits, then
2838 * we would never get another interrupt.
2840 * This is fine on non-MSI as well, as if we hit this path
2841 * we avoid exiting the interrupt handler only to generate
2844 * Note that for MSI this could cause a stray interrupt report
2845 * if an interrupt landed in the time between writing IIR and
2846 * the posting read. This should be rare enough to never
2847 * trigger the 99% of 100,000 interrupts test for disabling
2852 } while (iir
& ~flip_mask
);
2854 i915_update_dri1_breadcrumb(dev
);
2859 static void i915_irq_uninstall(struct drm_device
* dev
)
2861 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2864 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2866 if (I915_HAS_HOTPLUG(dev
)) {
2867 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2868 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2871 I915_WRITE16(HWSTAM
, 0xffff);
2872 for_each_pipe(pipe
) {
2873 /* Clear enable bits; then clear status bits */
2874 I915_WRITE(PIPESTAT(pipe
), 0);
2875 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
2877 I915_WRITE(IMR
, 0xffffffff);
2878 I915_WRITE(IER
, 0x0);
2880 I915_WRITE(IIR
, I915_READ(IIR
));
2883 static void i965_irq_preinstall(struct drm_device
* dev
)
2885 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2888 atomic_set(&dev_priv
->irq_received
, 0);
2890 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2891 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2893 I915_WRITE(HWSTAM
, 0xeffe);
2895 I915_WRITE(PIPESTAT(pipe
), 0);
2896 I915_WRITE(IMR
, 0xffffffff);
2897 I915_WRITE(IER
, 0x0);
2901 static int i965_irq_postinstall(struct drm_device
*dev
)
2903 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2906 unsigned long irqflags
;
2908 /* Unmask the interrupts that we always want on. */
2909 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
2910 I915_DISPLAY_PORT_INTERRUPT
|
2911 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2912 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2913 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2914 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2915 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2917 enable_mask
= ~dev_priv
->irq_mask
;
2918 enable_mask
&= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2919 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
2920 enable_mask
|= I915_USER_INTERRUPT
;
2923 enable_mask
|= I915_BSD_USER_INTERRUPT
;
2925 /* Interrupt setup is already guaranteed to be single-threaded, this is
2926 * just to make the assert_spin_locked check happy. */
2927 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2928 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
2929 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2932 * Enable some error detection, note the instruction error mask
2933 * bit is reserved, so we leave it masked.
2936 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
2937 GM45_ERROR_MEM_PRIV
|
2938 GM45_ERROR_CP_PRIV
|
2939 I915_ERROR_MEMORY_REFRESH
);
2941 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
2942 I915_ERROR_MEMORY_REFRESH
);
2944 I915_WRITE(EMR
, error_mask
);
2946 I915_WRITE(IMR
, dev_priv
->irq_mask
);
2947 I915_WRITE(IER
, enable_mask
);
2950 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2951 POSTING_READ(PORT_HOTPLUG_EN
);
2953 i915_enable_asle_pipestat(dev
);
2958 static void i915_hpd_irq_setup(struct drm_device
*dev
)
2960 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2961 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2962 struct intel_encoder
*intel_encoder
;
2965 assert_spin_locked(&dev_priv
->irq_lock
);
2967 if (I915_HAS_HOTPLUG(dev
)) {
2968 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
2969 hotplug_en
&= ~HOTPLUG_INT_EN_MASK
;
2970 /* Note HDMI and DP share hotplug bits */
2971 /* enable bits are the same for all generations */
2972 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2973 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2974 hotplug_en
|= hpd_mask_i915
[intel_encoder
->hpd_pin
];
2975 /* Programming the CRT detection parameters tends
2976 to generate a spurious hotplug event about three
2977 seconds later. So just do it once.
2980 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
2981 hotplug_en
&= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK
;
2982 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
2984 /* Ignore TV since it's buggy */
2985 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
2989 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
2991 struct drm_device
*dev
= (struct drm_device
*) arg
;
2992 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2994 u32 pipe_stats
[I915_MAX_PIPES
];
2995 unsigned long irqflags
;
2997 int ret
= IRQ_NONE
, pipe
;
2999 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3000 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3002 atomic_inc(&dev_priv
->irq_received
);
3004 iir
= I915_READ(IIR
);
3007 bool blc_event
= false;
3009 irq_received
= (iir
& ~flip_mask
) != 0;
3011 /* Can't rely on pipestat interrupt bit in iir as it might
3012 * have been cleared after the pipestat interrupt was received.
3013 * It doesn't set the bit in iir again, but it still produces
3014 * interrupts (for non-MSI).
3016 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3017 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3018 i915_handle_error(dev
, false);
3020 for_each_pipe(pipe
) {
3021 int reg
= PIPESTAT(pipe
);
3022 pipe_stats
[pipe
] = I915_READ(reg
);
3025 * Clear the PIPE*STAT regs before the IIR
3027 if (pipe_stats
[pipe
] & 0x8000ffff) {
3028 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
3029 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3031 I915_WRITE(reg
, pipe_stats
[pipe
]);
3035 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3042 /* Consume port. Then clear IIR or we'll miss events */
3043 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
3044 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
3045 u32 hotplug_trigger
= hotplug_status
& (IS_G4X(dev
) ?
3046 HOTPLUG_INT_STATUS_G4X
:
3047 HOTPLUG_INT_STATUS_I915
);
3049 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3052 intel_hpd_irq_handler(dev
, hotplug_trigger
,
3053 IS_G4X(dev
) ? hpd_status_gen4
: hpd_status_i915
);
3055 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
3056 I915_READ(PORT_HOTPLUG_STAT
);
3059 I915_WRITE(IIR
, iir
& ~flip_mask
);
3060 new_iir
= I915_READ(IIR
); /* Flush posted writes */
3062 if (iir
& I915_USER_INTERRUPT
)
3063 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
3064 if (iir
& I915_BSD_USER_INTERRUPT
)
3065 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
3067 for_each_pipe(pipe
) {
3068 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
3069 i915_handle_vblank(dev
, pipe
, pipe
, iir
))
3070 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
3072 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
3077 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
3078 intel_opregion_asle_intr(dev
);
3080 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
3081 gmbus_irq_handler(dev
);
3083 /* With MSI, interrupts are only generated when iir
3084 * transitions from zero to nonzero. If another bit got
3085 * set while we were handling the existing iir bits, then
3086 * we would never get another interrupt.
3088 * This is fine on non-MSI as well, as if we hit this path
3089 * we avoid exiting the interrupt handler only to generate
3092 * Note that for MSI this could cause a stray interrupt report
3093 * if an interrupt landed in the time between writing IIR and
3094 * the posting read. This should be rare enough to never
3095 * trigger the 99% of 100,000 interrupts test for disabling
3101 i915_update_dri1_breadcrumb(dev
);
3106 static void i965_irq_uninstall(struct drm_device
* dev
)
3108 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3114 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
3116 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3117 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3119 I915_WRITE(HWSTAM
, 0xffffffff);
3121 I915_WRITE(PIPESTAT(pipe
), 0);
3122 I915_WRITE(IMR
, 0xffffffff);
3123 I915_WRITE(IER
, 0x0);
3126 I915_WRITE(PIPESTAT(pipe
),
3127 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
3128 I915_WRITE(IIR
, I915_READ(IIR
));
3131 static void i915_reenable_hotplug_timer_func(unsigned long data
)
3133 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*)data
;
3134 struct drm_device
*dev
= dev_priv
->dev
;
3135 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3136 unsigned long irqflags
;
3139 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3140 for (i
= (HPD_NONE
+ 1); i
< HPD_NUM_PINS
; i
++) {
3141 struct drm_connector
*connector
;
3143 if (dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_DISABLED
)
3146 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3148 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3149 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3151 if (intel_connector
->encoder
->hpd_pin
== i
) {
3152 if (connector
->polled
!= intel_connector
->polled
)
3153 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3154 drm_get_connector_name(connector
));
3155 connector
->polled
= intel_connector
->polled
;
3156 if (!connector
->polled
)
3157 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3161 if (dev_priv
->display
.hpd_irq_setup
)
3162 dev_priv
->display
.hpd_irq_setup(dev
);
3163 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3166 void intel_irq_init(struct drm_device
*dev
)
3168 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3170 INIT_WORK(&dev_priv
->hotplug_work
, i915_hotplug_work_func
);
3171 INIT_WORK(&dev_priv
->gpu_error
.work
, i915_error_work_func
);
3172 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
3173 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
3175 setup_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
3176 i915_hangcheck_elapsed
,
3177 (unsigned long) dev
);
3178 setup_timer(&dev_priv
->hotplug_reenable_timer
, i915_reenable_hotplug_timer_func
,
3179 (unsigned long) dev_priv
);
3181 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
, PM_QOS_DEFAULT_VALUE
);
3183 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
3184 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
3185 dev
->driver
->get_vblank_counter
= gm45_get_vblank_counter
;
3187 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
3188 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
3191 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3192 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
3194 dev
->driver
->get_vblank_timestamp
= NULL
;
3195 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
3197 if (IS_VALLEYVIEW(dev
)) {
3198 dev
->driver
->irq_handler
= valleyview_irq_handler
;
3199 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
3200 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
3201 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
3202 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
3203 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
3204 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3205 } else if (HAS_PCH_SPLIT(dev
)) {
3206 dev
->driver
->irq_handler
= ironlake_irq_handler
;
3207 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
3208 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
3209 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
3210 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
3211 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
3212 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
3214 if (INTEL_INFO(dev
)->gen
== 2) {
3215 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
3216 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
3217 dev
->driver
->irq_handler
= i8xx_irq_handler
;
3218 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
3219 } else if (INTEL_INFO(dev
)->gen
== 3) {
3220 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
3221 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
3222 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
3223 dev
->driver
->irq_handler
= i915_irq_handler
;
3224 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3226 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
3227 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
3228 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
3229 dev
->driver
->irq_handler
= i965_irq_handler
;
3230 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3232 dev
->driver
->enable_vblank
= i915_enable_vblank
;
3233 dev
->driver
->disable_vblank
= i915_disable_vblank
;
3237 void intel_hpd_init(struct drm_device
*dev
)
3239 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3240 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3241 struct drm_connector
*connector
;
3242 unsigned long irqflags
;
3245 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
3246 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
3247 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3249 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3250 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3251 connector
->polled
= intel_connector
->polled
;
3252 if (!connector
->polled
&& I915_HAS_HOTPLUG(dev
) && intel_connector
->encoder
->hpd_pin
> HPD_NONE
)
3253 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3256 /* Interrupt setup is already guaranteed to be single-threaded, this is
3257 * just to make the assert_spin_locked checks happy. */
3258 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3259 if (dev_priv
->display
.hpd_irq_setup
)
3260 dev_priv
->display
.hpd_irq_setup(dev
);
3261 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3264 /* Disable interrupts so we can allow Package C8+. */
3265 void hsw_pc8_disable_interrupts(struct drm_device
*dev
)
3267 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3268 unsigned long irqflags
;
3270 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3272 dev_priv
->pc8
.regsave
.deimr
= I915_READ(DEIMR
);
3273 dev_priv
->pc8
.regsave
.sdeimr
= I915_READ(SDEIMR
);
3274 dev_priv
->pc8
.regsave
.gtimr
= I915_READ(GTIMR
);
3275 dev_priv
->pc8
.regsave
.gtier
= I915_READ(GTIER
);
3276 dev_priv
->pc8
.regsave
.gen6_pmimr
= I915_READ(GEN6_PMIMR
);
3278 ironlake_disable_display_irq(dev_priv
, ~DE_PCH_EVENT_IVB
);
3279 ibx_disable_display_interrupt(dev_priv
, ~SDE_HOTPLUG_MASK_CPT
);
3280 ilk_disable_gt_irq(dev_priv
, 0xffffffff);
3281 snb_disable_pm_irq(dev_priv
, 0xffffffff);
3283 dev_priv
->pc8
.irqs_disabled
= true;
3285 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3288 /* Restore interrupts so we can recover from Package C8+. */
3289 void hsw_pc8_restore_interrupts(struct drm_device
*dev
)
3291 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3292 unsigned long irqflags
;
3293 uint32_t val
, expected
;
3295 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3297 val
= I915_READ(DEIMR
);
3298 expected
= ~DE_PCH_EVENT_IVB
;
3299 WARN(val
!= expected
, "DEIMR is 0x%08x, not 0x%08x\n", val
, expected
);
3301 val
= I915_READ(SDEIMR
) & ~SDE_HOTPLUG_MASK_CPT
;
3302 expected
= ~SDE_HOTPLUG_MASK_CPT
;
3303 WARN(val
!= expected
, "SDEIMR non-HPD bits are 0x%08x, not 0x%08x\n",
3306 val
= I915_READ(GTIMR
);
3307 expected
= 0xffffffff;
3308 WARN(val
!= expected
, "GTIMR is 0x%08x, not 0x%08x\n", val
, expected
);
3310 val
= I915_READ(GEN6_PMIMR
);
3311 expected
= 0xffffffff;
3312 WARN(val
!= expected
, "GEN6_PMIMR is 0x%08x, not 0x%08x\n", val
,
3315 dev_priv
->pc8
.irqs_disabled
= false;
3317 ironlake_enable_display_irq(dev_priv
, ~dev_priv
->pc8
.regsave
.deimr
);
3318 ibx_enable_display_interrupt(dev_priv
,
3319 ~dev_priv
->pc8
.regsave
.sdeimr
&
3320 ~SDE_HOTPLUG_MASK_CPT
);
3321 ilk_enable_gt_irq(dev_priv
, ~dev_priv
->pc8
.regsave
.gtimr
);
3322 snb_enable_pm_irq(dev_priv
, ~dev_priv
->pc8
.regsave
.gen6_pmimr
);
3323 I915_WRITE(GTIER
, dev_priv
->pc8
.regsave
.gtier
);
3325 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);