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drm/i915: Don't pretend that gen2 has a hardware frame counter
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <drm/drmP.h>
34 #include <drm/i915_drm.h>
35 #include "i915_drv.h"
36 #include "i915_trace.h"
37 #include "intel_drv.h"
38
39 static const u32 hpd_ibx[] = {
40 [HPD_CRT] = SDE_CRT_HOTPLUG,
41 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
42 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
43 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
44 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
45 };
46
47 static const u32 hpd_cpt[] = {
48 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
49 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
50 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
51 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
52 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
53 };
54
55 static const u32 hpd_mask_i915[] = {
56 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
57 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
58 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
59 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
60 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
61 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
62 };
63
64 static const u32 hpd_status_gen4[] = {
65 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
66 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
67 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
68 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
69 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
70 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
71 };
72
73 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
74 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
75 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
76 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
77 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
78 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
79 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
80 };
81
82 /* For display hotplug interrupt */
83 static void
84 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
85 {
86 assert_spin_locked(&dev_priv->irq_lock);
87
88 if (dev_priv->pc8.irqs_disabled) {
89 WARN(1, "IRQs disabled\n");
90 dev_priv->pc8.regsave.deimr &= ~mask;
91 return;
92 }
93
94 if ((dev_priv->irq_mask & mask) != 0) {
95 dev_priv->irq_mask &= ~mask;
96 I915_WRITE(DEIMR, dev_priv->irq_mask);
97 POSTING_READ(DEIMR);
98 }
99 }
100
101 static void
102 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
103 {
104 assert_spin_locked(&dev_priv->irq_lock);
105
106 if (dev_priv->pc8.irqs_disabled) {
107 WARN(1, "IRQs disabled\n");
108 dev_priv->pc8.regsave.deimr |= mask;
109 return;
110 }
111
112 if ((dev_priv->irq_mask & mask) != mask) {
113 dev_priv->irq_mask |= mask;
114 I915_WRITE(DEIMR, dev_priv->irq_mask);
115 POSTING_READ(DEIMR);
116 }
117 }
118
119 /**
120 * ilk_update_gt_irq - update GTIMR
121 * @dev_priv: driver private
122 * @interrupt_mask: mask of interrupt bits to update
123 * @enabled_irq_mask: mask of interrupt bits to enable
124 */
125 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
126 uint32_t interrupt_mask,
127 uint32_t enabled_irq_mask)
128 {
129 assert_spin_locked(&dev_priv->irq_lock);
130
131 if (dev_priv->pc8.irqs_disabled) {
132 WARN(1, "IRQs disabled\n");
133 dev_priv->pc8.regsave.gtimr &= ~interrupt_mask;
134 dev_priv->pc8.regsave.gtimr |= (~enabled_irq_mask &
135 interrupt_mask);
136 return;
137 }
138
139 dev_priv->gt_irq_mask &= ~interrupt_mask;
140 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
141 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
142 POSTING_READ(GTIMR);
143 }
144
145 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
146 {
147 ilk_update_gt_irq(dev_priv, mask, mask);
148 }
149
150 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
151 {
152 ilk_update_gt_irq(dev_priv, mask, 0);
153 }
154
155 /**
156 * snb_update_pm_irq - update GEN6_PMIMR
157 * @dev_priv: driver private
158 * @interrupt_mask: mask of interrupt bits to update
159 * @enabled_irq_mask: mask of interrupt bits to enable
160 */
161 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
162 uint32_t interrupt_mask,
163 uint32_t enabled_irq_mask)
164 {
165 uint32_t new_val;
166
167 assert_spin_locked(&dev_priv->irq_lock);
168
169 if (dev_priv->pc8.irqs_disabled) {
170 WARN(1, "IRQs disabled\n");
171 dev_priv->pc8.regsave.gen6_pmimr &= ~interrupt_mask;
172 dev_priv->pc8.regsave.gen6_pmimr |= (~enabled_irq_mask &
173 interrupt_mask);
174 return;
175 }
176
177 new_val = dev_priv->pm_irq_mask;
178 new_val &= ~interrupt_mask;
179 new_val |= (~enabled_irq_mask & interrupt_mask);
180
181 if (new_val != dev_priv->pm_irq_mask) {
182 dev_priv->pm_irq_mask = new_val;
183 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
184 POSTING_READ(GEN6_PMIMR);
185 }
186 }
187
188 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
189 {
190 snb_update_pm_irq(dev_priv, mask, mask);
191 }
192
193 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
194 {
195 snb_update_pm_irq(dev_priv, mask, 0);
196 }
197
198 static bool ivb_can_enable_err_int(struct drm_device *dev)
199 {
200 struct drm_i915_private *dev_priv = dev->dev_private;
201 struct intel_crtc *crtc;
202 enum pipe pipe;
203
204 assert_spin_locked(&dev_priv->irq_lock);
205
206 for_each_pipe(pipe) {
207 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
208
209 if (crtc->cpu_fifo_underrun_disabled)
210 return false;
211 }
212
213 return true;
214 }
215
216 static bool cpt_can_enable_serr_int(struct drm_device *dev)
217 {
218 struct drm_i915_private *dev_priv = dev->dev_private;
219 enum pipe pipe;
220 struct intel_crtc *crtc;
221
222 assert_spin_locked(&dev_priv->irq_lock);
223
224 for_each_pipe(pipe) {
225 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
226
227 if (crtc->pch_fifo_underrun_disabled)
228 return false;
229 }
230
231 return true;
232 }
233
234 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
235 enum pipe pipe, bool enable)
236 {
237 struct drm_i915_private *dev_priv = dev->dev_private;
238 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
239 DE_PIPEB_FIFO_UNDERRUN;
240
241 if (enable)
242 ironlake_enable_display_irq(dev_priv, bit);
243 else
244 ironlake_disable_display_irq(dev_priv, bit);
245 }
246
247 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
248 enum pipe pipe, bool enable)
249 {
250 struct drm_i915_private *dev_priv = dev->dev_private;
251 if (enable) {
252 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
253
254 if (!ivb_can_enable_err_int(dev))
255 return;
256
257 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
258 } else {
259 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
260
261 /* Change the state _after_ we've read out the current one. */
262 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
263
264 if (!was_enabled &&
265 (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
266 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
267 pipe_name(pipe));
268 }
269 }
270 }
271
272 /**
273 * ibx_display_interrupt_update - update SDEIMR
274 * @dev_priv: driver private
275 * @interrupt_mask: mask of interrupt bits to update
276 * @enabled_irq_mask: mask of interrupt bits to enable
277 */
278 static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
279 uint32_t interrupt_mask,
280 uint32_t enabled_irq_mask)
281 {
282 uint32_t sdeimr = I915_READ(SDEIMR);
283 sdeimr &= ~interrupt_mask;
284 sdeimr |= (~enabled_irq_mask & interrupt_mask);
285
286 assert_spin_locked(&dev_priv->irq_lock);
287
288 if (dev_priv->pc8.irqs_disabled &&
289 (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) {
290 WARN(1, "IRQs disabled\n");
291 dev_priv->pc8.regsave.sdeimr &= ~interrupt_mask;
292 dev_priv->pc8.regsave.sdeimr |= (~enabled_irq_mask &
293 interrupt_mask);
294 return;
295 }
296
297 I915_WRITE(SDEIMR, sdeimr);
298 POSTING_READ(SDEIMR);
299 }
300 #define ibx_enable_display_interrupt(dev_priv, bits) \
301 ibx_display_interrupt_update((dev_priv), (bits), (bits))
302 #define ibx_disable_display_interrupt(dev_priv, bits) \
303 ibx_display_interrupt_update((dev_priv), (bits), 0)
304
305 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
306 enum transcoder pch_transcoder,
307 bool enable)
308 {
309 struct drm_i915_private *dev_priv = dev->dev_private;
310 uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
311 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
312
313 if (enable)
314 ibx_enable_display_interrupt(dev_priv, bit);
315 else
316 ibx_disable_display_interrupt(dev_priv, bit);
317 }
318
319 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
320 enum transcoder pch_transcoder,
321 bool enable)
322 {
323 struct drm_i915_private *dev_priv = dev->dev_private;
324
325 if (enable) {
326 I915_WRITE(SERR_INT,
327 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
328
329 if (!cpt_can_enable_serr_int(dev))
330 return;
331
332 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
333 } else {
334 uint32_t tmp = I915_READ(SERR_INT);
335 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
336
337 /* Change the state _after_ we've read out the current one. */
338 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
339
340 if (!was_enabled &&
341 (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
342 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
343 transcoder_name(pch_transcoder));
344 }
345 }
346 }
347
348 /**
349 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
350 * @dev: drm device
351 * @pipe: pipe
352 * @enable: true if we want to report FIFO underrun errors, false otherwise
353 *
354 * This function makes us disable or enable CPU fifo underruns for a specific
355 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
356 * reporting for one pipe may also disable all the other CPU error interruts for
357 * the other pipes, due to the fact that there's just one interrupt mask/enable
358 * bit for all the pipes.
359 *
360 * Returns the previous state of underrun reporting.
361 */
362 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
363 enum pipe pipe, bool enable)
364 {
365 struct drm_i915_private *dev_priv = dev->dev_private;
366 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
368 unsigned long flags;
369 bool ret;
370
371 spin_lock_irqsave(&dev_priv->irq_lock, flags);
372
373 ret = !intel_crtc->cpu_fifo_underrun_disabled;
374
375 if (enable == ret)
376 goto done;
377
378 intel_crtc->cpu_fifo_underrun_disabled = !enable;
379
380 if (IS_GEN5(dev) || IS_GEN6(dev))
381 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
382 else if (IS_GEN7(dev))
383 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
384
385 done:
386 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
387 return ret;
388 }
389
390 /**
391 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
392 * @dev: drm device
393 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
394 * @enable: true if we want to report FIFO underrun errors, false otherwise
395 *
396 * This function makes us disable or enable PCH fifo underruns for a specific
397 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
398 * underrun reporting for one transcoder may also disable all the other PCH
399 * error interruts for the other transcoders, due to the fact that there's just
400 * one interrupt mask/enable bit for all the transcoders.
401 *
402 * Returns the previous state of underrun reporting.
403 */
404 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
405 enum transcoder pch_transcoder,
406 bool enable)
407 {
408 struct drm_i915_private *dev_priv = dev->dev_private;
409 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
411 unsigned long flags;
412 bool ret;
413
414 /*
415 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
416 * has only one pch transcoder A that all pipes can use. To avoid racy
417 * pch transcoder -> pipe lookups from interrupt code simply store the
418 * underrun statistics in crtc A. Since we never expose this anywhere
419 * nor use it outside of the fifo underrun code here using the "wrong"
420 * crtc on LPT won't cause issues.
421 */
422
423 spin_lock_irqsave(&dev_priv->irq_lock, flags);
424
425 ret = !intel_crtc->pch_fifo_underrun_disabled;
426
427 if (enable == ret)
428 goto done;
429
430 intel_crtc->pch_fifo_underrun_disabled = !enable;
431
432 if (HAS_PCH_IBX(dev))
433 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
434 else
435 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
436
437 done:
438 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
439 return ret;
440 }
441
442
443 void
444 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
445 {
446 u32 reg = PIPESTAT(pipe);
447 u32 pipestat = I915_READ(reg) & 0x7fff0000;
448
449 assert_spin_locked(&dev_priv->irq_lock);
450
451 if ((pipestat & mask) == mask)
452 return;
453
454 /* Enable the interrupt, clear any pending status */
455 pipestat |= mask | (mask >> 16);
456 I915_WRITE(reg, pipestat);
457 POSTING_READ(reg);
458 }
459
460 void
461 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
462 {
463 u32 reg = PIPESTAT(pipe);
464 u32 pipestat = I915_READ(reg) & 0x7fff0000;
465
466 assert_spin_locked(&dev_priv->irq_lock);
467
468 if ((pipestat & mask) == 0)
469 return;
470
471 pipestat &= ~mask;
472 I915_WRITE(reg, pipestat);
473 POSTING_READ(reg);
474 }
475
476 /**
477 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
478 */
479 static void i915_enable_asle_pipestat(struct drm_device *dev)
480 {
481 drm_i915_private_t *dev_priv = dev->dev_private;
482 unsigned long irqflags;
483
484 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
485 return;
486
487 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
488
489 i915_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE);
490 if (INTEL_INFO(dev)->gen >= 4)
491 i915_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE);
492
493 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
494 }
495
496 /**
497 * i915_pipe_enabled - check if a pipe is enabled
498 * @dev: DRM device
499 * @pipe: pipe to check
500 *
501 * Reading certain registers when the pipe is disabled can hang the chip.
502 * Use this routine to make sure the PLL is running and the pipe is active
503 * before reading such registers if unsure.
504 */
505 static int
506 i915_pipe_enabled(struct drm_device *dev, int pipe)
507 {
508 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
509
510 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
511 /* Locking is horribly broken here, but whatever. */
512 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
514
515 return intel_crtc->active;
516 } else {
517 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
518 }
519 }
520
521 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
522 {
523 /* Gen2 doesn't have a hardware frame counter */
524 return 0;
525 }
526
527 /* Called from drm generic code, passed a 'crtc', which
528 * we use as a pipe index
529 */
530 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
531 {
532 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
533 unsigned long high_frame;
534 unsigned long low_frame;
535 u32 high1, high2, low, pixel, vbl_start;
536
537 if (!i915_pipe_enabled(dev, pipe)) {
538 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
539 "pipe %c\n", pipe_name(pipe));
540 return 0;
541 }
542
543 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
544 struct intel_crtc *intel_crtc =
545 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
546 const struct drm_display_mode *mode =
547 &intel_crtc->config.adjusted_mode;
548
549 vbl_start = mode->crtc_vblank_start * mode->crtc_htotal;
550 } else {
551 enum transcoder cpu_transcoder =
552 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
553 u32 htotal;
554
555 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
556 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
557
558 vbl_start *= htotal;
559 }
560
561 high_frame = PIPEFRAME(pipe);
562 low_frame = PIPEFRAMEPIXEL(pipe);
563
564 /*
565 * High & low register fields aren't synchronized, so make sure
566 * we get a low value that's stable across two reads of the high
567 * register.
568 */
569 do {
570 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
571 low = I915_READ(low_frame);
572 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
573 } while (high1 != high2);
574
575 high1 >>= PIPE_FRAME_HIGH_SHIFT;
576 pixel = low & PIPE_PIXEL_MASK;
577 low >>= PIPE_FRAME_LOW_SHIFT;
578
579 /*
580 * The frame counter increments at beginning of active.
581 * Cook up a vblank counter by also checking the pixel
582 * counter against vblank start.
583 */
584 return ((high1 << 8) | low) + (pixel >= vbl_start);
585 }
586
587 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
588 {
589 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
590 int reg = PIPE_FRMCOUNT_GM45(pipe);
591
592 if (!i915_pipe_enabled(dev, pipe)) {
593 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
594 "pipe %c\n", pipe_name(pipe));
595 return 0;
596 }
597
598 return I915_READ(reg);
599 }
600
601 static bool intel_pipe_in_vblank(struct drm_device *dev, enum pipe pipe)
602 {
603 struct drm_i915_private *dev_priv = dev->dev_private;
604 uint32_t status;
605
606 if (IS_VALLEYVIEW(dev)) {
607 status = pipe == PIPE_A ?
608 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT :
609 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
610
611 return I915_READ(VLV_ISR) & status;
612 } else if (IS_GEN2(dev)) {
613 status = pipe == PIPE_A ?
614 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT :
615 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
616
617 return I915_READ16(ISR) & status;
618 } else if (INTEL_INFO(dev)->gen < 5) {
619 status = pipe == PIPE_A ?
620 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT :
621 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
622
623 return I915_READ(ISR) & status;
624 } else if (INTEL_INFO(dev)->gen < 7) {
625 status = pipe == PIPE_A ?
626 DE_PIPEA_VBLANK :
627 DE_PIPEB_VBLANK;
628
629 return I915_READ(DEISR) & status;
630 } else {
631 switch (pipe) {
632 default:
633 case PIPE_A:
634 status = DE_PIPEA_VBLANK_IVB;
635 break;
636 case PIPE_B:
637 status = DE_PIPEB_VBLANK_IVB;
638 break;
639 case PIPE_C:
640 status = DE_PIPEC_VBLANK_IVB;
641 break;
642 }
643
644 return I915_READ(DEISR) & status;
645 }
646 }
647
648 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
649 int *vpos, int *hpos)
650 {
651 struct drm_i915_private *dev_priv = dev->dev_private;
652 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
654 const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
655 int position;
656 int vbl_start, vbl_end, htotal, vtotal;
657 bool in_vbl = true;
658 int ret = 0;
659
660 if (!intel_crtc->active) {
661 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
662 "pipe %c\n", pipe_name(pipe));
663 return 0;
664 }
665
666 htotal = mode->crtc_htotal;
667 vtotal = mode->crtc_vtotal;
668 vbl_start = mode->crtc_vblank_start;
669 vbl_end = mode->crtc_vblank_end;
670
671 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
672
673 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
674 /* No obvious pixelcount register. Only query vertical
675 * scanout position from Display scan line register.
676 */
677 if (IS_GEN2(dev))
678 position = I915_READ(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
679 else
680 position = I915_READ(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
681
682 /*
683 * The scanline counter increments at the leading edge
684 * of hsync, ie. it completely misses the active portion
685 * of the line. Fix up the counter at both edges of vblank
686 * to get a more accurate picture whether we're in vblank
687 * or not.
688 */
689 in_vbl = intel_pipe_in_vblank(dev, pipe);
690 if ((in_vbl && position == vbl_start - 1) ||
691 (!in_vbl && position == vbl_end - 1))
692 position = (position + 1) % vtotal;
693 } else {
694 /* Have access to pixelcount since start of frame.
695 * We can split this into vertical and horizontal
696 * scanout position.
697 */
698 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
699
700 /* convert to pixel counts */
701 vbl_start *= htotal;
702 vbl_end *= htotal;
703 vtotal *= htotal;
704 }
705
706 in_vbl = position >= vbl_start && position < vbl_end;
707
708 /*
709 * While in vblank, position will be negative
710 * counting up towards 0 at vbl_end. And outside
711 * vblank, position will be positive counting
712 * up since vbl_end.
713 */
714 if (position >= vbl_start)
715 position -= vbl_end;
716 else
717 position += vtotal - vbl_end;
718
719 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
720 *vpos = position;
721 *hpos = 0;
722 } else {
723 *vpos = position / htotal;
724 *hpos = position - (*vpos * htotal);
725 }
726
727 /* In vblank? */
728 if (in_vbl)
729 ret |= DRM_SCANOUTPOS_INVBL;
730
731 return ret;
732 }
733
734 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
735 int *max_error,
736 struct timeval *vblank_time,
737 unsigned flags)
738 {
739 struct drm_crtc *crtc;
740
741 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
742 DRM_ERROR("Invalid crtc %d\n", pipe);
743 return -EINVAL;
744 }
745
746 /* Get drm_crtc to timestamp: */
747 crtc = intel_get_crtc_for_pipe(dev, pipe);
748 if (crtc == NULL) {
749 DRM_ERROR("Invalid crtc %d\n", pipe);
750 return -EINVAL;
751 }
752
753 if (!crtc->enabled) {
754 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
755 return -EBUSY;
756 }
757
758 /* Helper routine in DRM core does all the work: */
759 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
760 vblank_time, flags,
761 crtc);
762 }
763
764 static bool intel_hpd_irq_event(struct drm_device *dev,
765 struct drm_connector *connector)
766 {
767 enum drm_connector_status old_status;
768
769 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
770 old_status = connector->status;
771
772 connector->status = connector->funcs->detect(connector, false);
773 if (old_status == connector->status)
774 return false;
775
776 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
777 connector->base.id,
778 drm_get_connector_name(connector),
779 drm_get_connector_status_name(old_status),
780 drm_get_connector_status_name(connector->status));
781
782 return true;
783 }
784
785 /*
786 * Handle hotplug events outside the interrupt handler proper.
787 */
788 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
789
790 static void i915_hotplug_work_func(struct work_struct *work)
791 {
792 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
793 hotplug_work);
794 struct drm_device *dev = dev_priv->dev;
795 struct drm_mode_config *mode_config = &dev->mode_config;
796 struct intel_connector *intel_connector;
797 struct intel_encoder *intel_encoder;
798 struct drm_connector *connector;
799 unsigned long irqflags;
800 bool hpd_disabled = false;
801 bool changed = false;
802 u32 hpd_event_bits;
803
804 /* HPD irq before everything is fully set up. */
805 if (!dev_priv->enable_hotplug_processing)
806 return;
807
808 mutex_lock(&mode_config->mutex);
809 DRM_DEBUG_KMS("running encoder hotplug functions\n");
810
811 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
812
813 hpd_event_bits = dev_priv->hpd_event_bits;
814 dev_priv->hpd_event_bits = 0;
815 list_for_each_entry(connector, &mode_config->connector_list, head) {
816 intel_connector = to_intel_connector(connector);
817 intel_encoder = intel_connector->encoder;
818 if (intel_encoder->hpd_pin > HPD_NONE &&
819 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
820 connector->polled == DRM_CONNECTOR_POLL_HPD) {
821 DRM_INFO("HPD interrupt storm detected on connector %s: "
822 "switching from hotplug detection to polling\n",
823 drm_get_connector_name(connector));
824 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
825 connector->polled = DRM_CONNECTOR_POLL_CONNECT
826 | DRM_CONNECTOR_POLL_DISCONNECT;
827 hpd_disabled = true;
828 }
829 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
830 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
831 drm_get_connector_name(connector), intel_encoder->hpd_pin);
832 }
833 }
834 /* if there were no outputs to poll, poll was disabled,
835 * therefore make sure it's enabled when disabling HPD on
836 * some connectors */
837 if (hpd_disabled) {
838 drm_kms_helper_poll_enable(dev);
839 mod_timer(&dev_priv->hotplug_reenable_timer,
840 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
841 }
842
843 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
844
845 list_for_each_entry(connector, &mode_config->connector_list, head) {
846 intel_connector = to_intel_connector(connector);
847 intel_encoder = intel_connector->encoder;
848 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
849 if (intel_encoder->hot_plug)
850 intel_encoder->hot_plug(intel_encoder);
851 if (intel_hpd_irq_event(dev, connector))
852 changed = true;
853 }
854 }
855 mutex_unlock(&mode_config->mutex);
856
857 if (changed)
858 drm_kms_helper_hotplug_event(dev);
859 }
860
861 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
862 {
863 drm_i915_private_t *dev_priv = dev->dev_private;
864 u32 busy_up, busy_down, max_avg, min_avg;
865 u8 new_delay;
866
867 spin_lock(&mchdev_lock);
868
869 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
870
871 new_delay = dev_priv->ips.cur_delay;
872
873 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
874 busy_up = I915_READ(RCPREVBSYTUPAVG);
875 busy_down = I915_READ(RCPREVBSYTDNAVG);
876 max_avg = I915_READ(RCBMAXAVG);
877 min_avg = I915_READ(RCBMINAVG);
878
879 /* Handle RCS change request from hw */
880 if (busy_up > max_avg) {
881 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
882 new_delay = dev_priv->ips.cur_delay - 1;
883 if (new_delay < dev_priv->ips.max_delay)
884 new_delay = dev_priv->ips.max_delay;
885 } else if (busy_down < min_avg) {
886 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
887 new_delay = dev_priv->ips.cur_delay + 1;
888 if (new_delay > dev_priv->ips.min_delay)
889 new_delay = dev_priv->ips.min_delay;
890 }
891
892 if (ironlake_set_drps(dev, new_delay))
893 dev_priv->ips.cur_delay = new_delay;
894
895 spin_unlock(&mchdev_lock);
896
897 return;
898 }
899
900 static void notify_ring(struct drm_device *dev,
901 struct intel_ring_buffer *ring)
902 {
903 if (ring->obj == NULL)
904 return;
905
906 trace_i915_gem_request_complete(ring);
907
908 wake_up_all(&ring->irq_queue);
909 i915_queue_hangcheck(dev);
910 }
911
912 static void gen6_pm_rps_work(struct work_struct *work)
913 {
914 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
915 rps.work);
916 u32 pm_iir;
917 int new_delay, adj;
918
919 spin_lock_irq(&dev_priv->irq_lock);
920 pm_iir = dev_priv->rps.pm_iir;
921 dev_priv->rps.pm_iir = 0;
922 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
923 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
924 spin_unlock_irq(&dev_priv->irq_lock);
925
926 /* Make sure we didn't queue anything we're not going to process. */
927 WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS);
928
929 if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
930 return;
931
932 mutex_lock(&dev_priv->rps.hw_lock);
933
934 adj = dev_priv->rps.last_adj;
935 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
936 if (adj > 0)
937 adj *= 2;
938 else
939 adj = 1;
940 new_delay = dev_priv->rps.cur_delay + adj;
941
942 /*
943 * For better performance, jump directly
944 * to RPe if we're below it.
945 */
946 if (new_delay < dev_priv->rps.rpe_delay)
947 new_delay = dev_priv->rps.rpe_delay;
948 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
949 if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
950 new_delay = dev_priv->rps.rpe_delay;
951 else
952 new_delay = dev_priv->rps.min_delay;
953 adj = 0;
954 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
955 if (adj < 0)
956 adj *= 2;
957 else
958 adj = -1;
959 new_delay = dev_priv->rps.cur_delay + adj;
960 } else { /* unknown event */
961 new_delay = dev_priv->rps.cur_delay;
962 }
963
964 /* sysfs frequency interfaces may have snuck in while servicing the
965 * interrupt
966 */
967 if (new_delay < (int)dev_priv->rps.min_delay)
968 new_delay = dev_priv->rps.min_delay;
969 if (new_delay > (int)dev_priv->rps.max_delay)
970 new_delay = dev_priv->rps.max_delay;
971 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay;
972
973 if (IS_VALLEYVIEW(dev_priv->dev))
974 valleyview_set_rps(dev_priv->dev, new_delay);
975 else
976 gen6_set_rps(dev_priv->dev, new_delay);
977
978 mutex_unlock(&dev_priv->rps.hw_lock);
979 }
980
981
982 /**
983 * ivybridge_parity_work - Workqueue called when a parity error interrupt
984 * occurred.
985 * @work: workqueue struct
986 *
987 * Doesn't actually do anything except notify userspace. As a consequence of
988 * this event, userspace should try to remap the bad rows since statistically
989 * it is likely the same row is more likely to go bad again.
990 */
991 static void ivybridge_parity_work(struct work_struct *work)
992 {
993 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
994 l3_parity.error_work);
995 u32 error_status, row, bank, subbank;
996 char *parity_event[6];
997 uint32_t misccpctl;
998 unsigned long flags;
999 uint8_t slice = 0;
1000
1001 /* We must turn off DOP level clock gating to access the L3 registers.
1002 * In order to prevent a get/put style interface, acquire struct mutex
1003 * any time we access those registers.
1004 */
1005 mutex_lock(&dev_priv->dev->struct_mutex);
1006
1007 /* If we've screwed up tracking, just let the interrupt fire again */
1008 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1009 goto out;
1010
1011 misccpctl = I915_READ(GEN7_MISCCPCTL);
1012 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1013 POSTING_READ(GEN7_MISCCPCTL);
1014
1015 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1016 u32 reg;
1017
1018 slice--;
1019 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1020 break;
1021
1022 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1023
1024 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1025
1026 error_status = I915_READ(reg);
1027 row = GEN7_PARITY_ERROR_ROW(error_status);
1028 bank = GEN7_PARITY_ERROR_BANK(error_status);
1029 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1030
1031 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1032 POSTING_READ(reg);
1033
1034 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1035 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1036 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1037 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1038 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1039 parity_event[5] = NULL;
1040
1041 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
1042 KOBJ_CHANGE, parity_event);
1043
1044 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1045 slice, row, bank, subbank);
1046
1047 kfree(parity_event[4]);
1048 kfree(parity_event[3]);
1049 kfree(parity_event[2]);
1050 kfree(parity_event[1]);
1051 }
1052
1053 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1054
1055 out:
1056 WARN_ON(dev_priv->l3_parity.which_slice);
1057 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1058 ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1059 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1060
1061 mutex_unlock(&dev_priv->dev->struct_mutex);
1062 }
1063
1064 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1065 {
1066 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1067
1068 if (!HAS_L3_DPF(dev))
1069 return;
1070
1071 spin_lock(&dev_priv->irq_lock);
1072 ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1073 spin_unlock(&dev_priv->irq_lock);
1074
1075 iir &= GT_PARITY_ERROR(dev);
1076 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1077 dev_priv->l3_parity.which_slice |= 1 << 1;
1078
1079 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1080 dev_priv->l3_parity.which_slice |= 1 << 0;
1081
1082 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1083 }
1084
1085 static void ilk_gt_irq_handler(struct drm_device *dev,
1086 struct drm_i915_private *dev_priv,
1087 u32 gt_iir)
1088 {
1089 if (gt_iir &
1090 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1091 notify_ring(dev, &dev_priv->ring[RCS]);
1092 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1093 notify_ring(dev, &dev_priv->ring[VCS]);
1094 }
1095
1096 static void snb_gt_irq_handler(struct drm_device *dev,
1097 struct drm_i915_private *dev_priv,
1098 u32 gt_iir)
1099 {
1100
1101 if (gt_iir &
1102 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1103 notify_ring(dev, &dev_priv->ring[RCS]);
1104 if (gt_iir & GT_BSD_USER_INTERRUPT)
1105 notify_ring(dev, &dev_priv->ring[VCS]);
1106 if (gt_iir & GT_BLT_USER_INTERRUPT)
1107 notify_ring(dev, &dev_priv->ring[BCS]);
1108
1109 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1110 GT_BSD_CS_ERROR_INTERRUPT |
1111 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
1112 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
1113 i915_handle_error(dev, false);
1114 }
1115
1116 if (gt_iir & GT_PARITY_ERROR(dev))
1117 ivybridge_parity_error_irq_handler(dev, gt_iir);
1118 }
1119
1120 #define HPD_STORM_DETECT_PERIOD 1000
1121 #define HPD_STORM_THRESHOLD 5
1122
1123 static inline void intel_hpd_irq_handler(struct drm_device *dev,
1124 u32 hotplug_trigger,
1125 const u32 *hpd)
1126 {
1127 drm_i915_private_t *dev_priv = dev->dev_private;
1128 int i;
1129 bool storm_detected = false;
1130
1131 if (!hotplug_trigger)
1132 return;
1133
1134 spin_lock(&dev_priv->irq_lock);
1135 for (i = 1; i < HPD_NUM_PINS; i++) {
1136
1137 WARN(((hpd[i] & hotplug_trigger) &&
1138 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED),
1139 "Received HPD interrupt although disabled\n");
1140
1141 if (!(hpd[i] & hotplug_trigger) ||
1142 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1143 continue;
1144
1145 dev_priv->hpd_event_bits |= (1 << i);
1146 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1147 dev_priv->hpd_stats[i].hpd_last_jiffies
1148 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1149 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1150 dev_priv->hpd_stats[i].hpd_cnt = 0;
1151 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1152 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1153 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1154 dev_priv->hpd_event_bits &= ~(1 << i);
1155 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1156 storm_detected = true;
1157 } else {
1158 dev_priv->hpd_stats[i].hpd_cnt++;
1159 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1160 dev_priv->hpd_stats[i].hpd_cnt);
1161 }
1162 }
1163
1164 if (storm_detected)
1165 dev_priv->display.hpd_irq_setup(dev);
1166 spin_unlock(&dev_priv->irq_lock);
1167
1168 /*
1169 * Our hotplug handler can grab modeset locks (by calling down into the
1170 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1171 * queue for otherwise the flush_work in the pageflip code will
1172 * deadlock.
1173 */
1174 schedule_work(&dev_priv->hotplug_work);
1175 }
1176
1177 static void gmbus_irq_handler(struct drm_device *dev)
1178 {
1179 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1180
1181 wake_up_all(&dev_priv->gmbus_wait_queue);
1182 }
1183
1184 static void dp_aux_irq_handler(struct drm_device *dev)
1185 {
1186 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1187
1188 wake_up_all(&dev_priv->gmbus_wait_queue);
1189 }
1190
1191 /* The RPS events need forcewake, so we add them to a work queue and mask their
1192 * IMR bits until the work is done. Other interrupts can be processed without
1193 * the work queue. */
1194 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1195 {
1196 if (pm_iir & GEN6_PM_RPS_EVENTS) {
1197 spin_lock(&dev_priv->irq_lock);
1198 dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
1199 snb_disable_pm_irq(dev_priv, pm_iir & GEN6_PM_RPS_EVENTS);
1200 spin_unlock(&dev_priv->irq_lock);
1201
1202 queue_work(dev_priv->wq, &dev_priv->rps.work);
1203 }
1204
1205 if (HAS_VEBOX(dev_priv->dev)) {
1206 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1207 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1208
1209 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1210 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
1211 i915_handle_error(dev_priv->dev, false);
1212 }
1213 }
1214 }
1215
1216 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1217 {
1218 struct drm_device *dev = (struct drm_device *) arg;
1219 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1220 u32 iir, gt_iir, pm_iir;
1221 irqreturn_t ret = IRQ_NONE;
1222 unsigned long irqflags;
1223 int pipe;
1224 u32 pipe_stats[I915_MAX_PIPES];
1225
1226 atomic_inc(&dev_priv->irq_received);
1227
1228 while (true) {
1229 iir = I915_READ(VLV_IIR);
1230 gt_iir = I915_READ(GTIIR);
1231 pm_iir = I915_READ(GEN6_PMIIR);
1232
1233 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1234 goto out;
1235
1236 ret = IRQ_HANDLED;
1237
1238 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1239
1240 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1241 for_each_pipe(pipe) {
1242 int reg = PIPESTAT(pipe);
1243 pipe_stats[pipe] = I915_READ(reg);
1244
1245 /*
1246 * Clear the PIPE*STAT regs before the IIR
1247 */
1248 if (pipe_stats[pipe] & 0x8000ffff) {
1249 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1250 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1251 pipe_name(pipe));
1252 I915_WRITE(reg, pipe_stats[pipe]);
1253 }
1254 }
1255 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1256
1257 for_each_pipe(pipe) {
1258 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1259 drm_handle_vblank(dev, pipe);
1260
1261 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
1262 intel_prepare_page_flip(dev, pipe);
1263 intel_finish_page_flip(dev, pipe);
1264 }
1265 }
1266
1267 /* Consume port. Then clear IIR or we'll miss events */
1268 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
1269 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1270 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1271
1272 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1273 hotplug_status);
1274
1275 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1276
1277 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1278 I915_READ(PORT_HOTPLUG_STAT);
1279 }
1280
1281 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1282 gmbus_irq_handler(dev);
1283
1284 if (pm_iir)
1285 gen6_rps_irq_handler(dev_priv, pm_iir);
1286
1287 I915_WRITE(GTIIR, gt_iir);
1288 I915_WRITE(GEN6_PMIIR, pm_iir);
1289 I915_WRITE(VLV_IIR, iir);
1290 }
1291
1292 out:
1293 return ret;
1294 }
1295
1296 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1297 {
1298 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1299 int pipe;
1300 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1301
1302 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1303
1304 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1305 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1306 SDE_AUDIO_POWER_SHIFT);
1307 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1308 port_name(port));
1309 }
1310
1311 if (pch_iir & SDE_AUX_MASK)
1312 dp_aux_irq_handler(dev);
1313
1314 if (pch_iir & SDE_GMBUS)
1315 gmbus_irq_handler(dev);
1316
1317 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1318 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1319
1320 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1321 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1322
1323 if (pch_iir & SDE_POISON)
1324 DRM_ERROR("PCH poison interrupt\n");
1325
1326 if (pch_iir & SDE_FDI_MASK)
1327 for_each_pipe(pipe)
1328 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1329 pipe_name(pipe),
1330 I915_READ(FDI_RX_IIR(pipe)));
1331
1332 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1333 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1334
1335 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1336 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1337
1338 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1339 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1340 false))
1341 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1342
1343 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1344 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1345 false))
1346 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1347 }
1348
1349 static void ivb_err_int_handler(struct drm_device *dev)
1350 {
1351 struct drm_i915_private *dev_priv = dev->dev_private;
1352 u32 err_int = I915_READ(GEN7_ERR_INT);
1353
1354 if (err_int & ERR_INT_POISON)
1355 DRM_ERROR("Poison interrupt\n");
1356
1357 if (err_int & ERR_INT_FIFO_UNDERRUN_A)
1358 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1359 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1360
1361 if (err_int & ERR_INT_FIFO_UNDERRUN_B)
1362 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1363 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1364
1365 if (err_int & ERR_INT_FIFO_UNDERRUN_C)
1366 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false))
1367 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1368
1369 I915_WRITE(GEN7_ERR_INT, err_int);
1370 }
1371
1372 static void cpt_serr_int_handler(struct drm_device *dev)
1373 {
1374 struct drm_i915_private *dev_priv = dev->dev_private;
1375 u32 serr_int = I915_READ(SERR_INT);
1376
1377 if (serr_int & SERR_INT_POISON)
1378 DRM_ERROR("PCH poison interrupt\n");
1379
1380 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1381 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1382 false))
1383 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1384
1385 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1386 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1387 false))
1388 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1389
1390 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1391 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1392 false))
1393 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1394
1395 I915_WRITE(SERR_INT, serr_int);
1396 }
1397
1398 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1399 {
1400 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1401 int pipe;
1402 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1403
1404 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1405
1406 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1407 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1408 SDE_AUDIO_POWER_SHIFT_CPT);
1409 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1410 port_name(port));
1411 }
1412
1413 if (pch_iir & SDE_AUX_MASK_CPT)
1414 dp_aux_irq_handler(dev);
1415
1416 if (pch_iir & SDE_GMBUS_CPT)
1417 gmbus_irq_handler(dev);
1418
1419 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1420 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1421
1422 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1423 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1424
1425 if (pch_iir & SDE_FDI_MASK_CPT)
1426 for_each_pipe(pipe)
1427 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1428 pipe_name(pipe),
1429 I915_READ(FDI_RX_IIR(pipe)));
1430
1431 if (pch_iir & SDE_ERROR_CPT)
1432 cpt_serr_int_handler(dev);
1433 }
1434
1435 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1436 {
1437 struct drm_i915_private *dev_priv = dev->dev_private;
1438
1439 if (de_iir & DE_AUX_CHANNEL_A)
1440 dp_aux_irq_handler(dev);
1441
1442 if (de_iir & DE_GSE)
1443 intel_opregion_asle_intr(dev);
1444
1445 if (de_iir & DE_PIPEA_VBLANK)
1446 drm_handle_vblank(dev, 0);
1447
1448 if (de_iir & DE_PIPEB_VBLANK)
1449 drm_handle_vblank(dev, 1);
1450
1451 if (de_iir & DE_POISON)
1452 DRM_ERROR("Poison interrupt\n");
1453
1454 if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
1455 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1456 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1457
1458 if (de_iir & DE_PIPEB_FIFO_UNDERRUN)
1459 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1460 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1461
1462 if (de_iir & DE_PLANEA_FLIP_DONE) {
1463 intel_prepare_page_flip(dev, 0);
1464 intel_finish_page_flip_plane(dev, 0);
1465 }
1466
1467 if (de_iir & DE_PLANEB_FLIP_DONE) {
1468 intel_prepare_page_flip(dev, 1);
1469 intel_finish_page_flip_plane(dev, 1);
1470 }
1471
1472 /* check event from PCH */
1473 if (de_iir & DE_PCH_EVENT) {
1474 u32 pch_iir = I915_READ(SDEIIR);
1475
1476 if (HAS_PCH_CPT(dev))
1477 cpt_irq_handler(dev, pch_iir);
1478 else
1479 ibx_irq_handler(dev, pch_iir);
1480
1481 /* should clear PCH hotplug event before clear CPU irq */
1482 I915_WRITE(SDEIIR, pch_iir);
1483 }
1484
1485 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1486 ironlake_rps_change_irq_handler(dev);
1487 }
1488
1489 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
1490 {
1491 struct drm_i915_private *dev_priv = dev->dev_private;
1492 int i;
1493
1494 if (de_iir & DE_ERR_INT_IVB)
1495 ivb_err_int_handler(dev);
1496
1497 if (de_iir & DE_AUX_CHANNEL_A_IVB)
1498 dp_aux_irq_handler(dev);
1499
1500 if (de_iir & DE_GSE_IVB)
1501 intel_opregion_asle_intr(dev);
1502
1503 for (i = 0; i < 3; i++) {
1504 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
1505 drm_handle_vblank(dev, i);
1506 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
1507 intel_prepare_page_flip(dev, i);
1508 intel_finish_page_flip_plane(dev, i);
1509 }
1510 }
1511
1512 /* check event from PCH */
1513 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1514 u32 pch_iir = I915_READ(SDEIIR);
1515
1516 cpt_irq_handler(dev, pch_iir);
1517
1518 /* clear PCH hotplug event before clear CPU irq */
1519 I915_WRITE(SDEIIR, pch_iir);
1520 }
1521 }
1522
1523 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
1524 {
1525 struct drm_device *dev = (struct drm_device *) arg;
1526 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1527 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
1528 irqreturn_t ret = IRQ_NONE;
1529
1530 atomic_inc(&dev_priv->irq_received);
1531
1532 /* We get interrupts on unclaimed registers, so check for this before we
1533 * do any I915_{READ,WRITE}. */
1534 intel_uncore_check_errors(dev);
1535
1536 /* disable master interrupt before clearing iir */
1537 de_ier = I915_READ(DEIER);
1538 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
1539 POSTING_READ(DEIER);
1540
1541 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1542 * interrupts will will be stored on its back queue, and then we'll be
1543 * able to process them after we restore SDEIER (as soon as we restore
1544 * it, we'll get an interrupt if SDEIIR still has something to process
1545 * due to its back queue). */
1546 if (!HAS_PCH_NOP(dev)) {
1547 sde_ier = I915_READ(SDEIER);
1548 I915_WRITE(SDEIER, 0);
1549 POSTING_READ(SDEIER);
1550 }
1551
1552 gt_iir = I915_READ(GTIIR);
1553 if (gt_iir) {
1554 if (INTEL_INFO(dev)->gen >= 6)
1555 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1556 else
1557 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1558 I915_WRITE(GTIIR, gt_iir);
1559 ret = IRQ_HANDLED;
1560 }
1561
1562 de_iir = I915_READ(DEIIR);
1563 if (de_iir) {
1564 if (INTEL_INFO(dev)->gen >= 7)
1565 ivb_display_irq_handler(dev, de_iir);
1566 else
1567 ilk_display_irq_handler(dev, de_iir);
1568 I915_WRITE(DEIIR, de_iir);
1569 ret = IRQ_HANDLED;
1570 }
1571
1572 if (INTEL_INFO(dev)->gen >= 6) {
1573 u32 pm_iir = I915_READ(GEN6_PMIIR);
1574 if (pm_iir) {
1575 gen6_rps_irq_handler(dev_priv, pm_iir);
1576 I915_WRITE(GEN6_PMIIR, pm_iir);
1577 ret = IRQ_HANDLED;
1578 }
1579 }
1580
1581 I915_WRITE(DEIER, de_ier);
1582 POSTING_READ(DEIER);
1583 if (!HAS_PCH_NOP(dev)) {
1584 I915_WRITE(SDEIER, sde_ier);
1585 POSTING_READ(SDEIER);
1586 }
1587
1588 return ret;
1589 }
1590
1591 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
1592 bool reset_completed)
1593 {
1594 struct intel_ring_buffer *ring;
1595 int i;
1596
1597 /*
1598 * Notify all waiters for GPU completion events that reset state has
1599 * been changed, and that they need to restart their wait after
1600 * checking for potential errors (and bail out to drop locks if there is
1601 * a gpu reset pending so that i915_error_work_func can acquire them).
1602 */
1603
1604 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
1605 for_each_ring(ring, dev_priv, i)
1606 wake_up_all(&ring->irq_queue);
1607
1608 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
1609 wake_up_all(&dev_priv->pending_flip_queue);
1610
1611 /*
1612 * Signal tasks blocked in i915_gem_wait_for_error that the pending
1613 * reset state is cleared.
1614 */
1615 if (reset_completed)
1616 wake_up_all(&dev_priv->gpu_error.reset_queue);
1617 }
1618
1619 /**
1620 * i915_error_work_func - do process context error handling work
1621 * @work: work struct
1622 *
1623 * Fire an error uevent so userspace can see that a hang or error
1624 * was detected.
1625 */
1626 static void i915_error_work_func(struct work_struct *work)
1627 {
1628 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
1629 work);
1630 drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
1631 gpu_error);
1632 struct drm_device *dev = dev_priv->dev;
1633 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
1634 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
1635 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
1636 int ret;
1637
1638 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
1639
1640 /*
1641 * Note that there's only one work item which does gpu resets, so we
1642 * need not worry about concurrent gpu resets potentially incrementing
1643 * error->reset_counter twice. We only need to take care of another
1644 * racing irq/hangcheck declaring the gpu dead for a second time. A
1645 * quick check for that is good enough: schedule_work ensures the
1646 * correct ordering between hang detection and this work item, and since
1647 * the reset in-progress bit is only ever set by code outside of this
1648 * work we don't need to worry about any other races.
1649 */
1650 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
1651 DRM_DEBUG_DRIVER("resetting chip\n");
1652 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
1653 reset_event);
1654
1655 /*
1656 * All state reset _must_ be completed before we update the
1657 * reset counter, for otherwise waiters might miss the reset
1658 * pending state and not properly drop locks, resulting in
1659 * deadlocks with the reset work.
1660 */
1661 ret = i915_reset(dev);
1662
1663 intel_display_handle_reset(dev);
1664
1665 if (ret == 0) {
1666 /*
1667 * After all the gem state is reset, increment the reset
1668 * counter and wake up everyone waiting for the reset to
1669 * complete.
1670 *
1671 * Since unlock operations are a one-sided barrier only,
1672 * we need to insert a barrier here to order any seqno
1673 * updates before
1674 * the counter increment.
1675 */
1676 smp_mb__before_atomic_inc();
1677 atomic_inc(&dev_priv->gpu_error.reset_counter);
1678
1679 kobject_uevent_env(&dev->primary->kdev.kobj,
1680 KOBJ_CHANGE, reset_done_event);
1681 } else {
1682 atomic_set(&error->reset_counter, I915_WEDGED);
1683 }
1684
1685 /*
1686 * Note: The wake_up also serves as a memory barrier so that
1687 * waiters see the update value of the reset counter atomic_t.
1688 */
1689 i915_error_wake_up(dev_priv, true);
1690 }
1691 }
1692
1693 static void i915_report_and_clear_eir(struct drm_device *dev)
1694 {
1695 struct drm_i915_private *dev_priv = dev->dev_private;
1696 uint32_t instdone[I915_NUM_INSTDONE_REG];
1697 u32 eir = I915_READ(EIR);
1698 int pipe, i;
1699
1700 if (!eir)
1701 return;
1702
1703 pr_err("render error detected, EIR: 0x%08x\n", eir);
1704
1705 i915_get_extra_instdone(dev, instdone);
1706
1707 if (IS_G4X(dev)) {
1708 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1709 u32 ipeir = I915_READ(IPEIR_I965);
1710
1711 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1712 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1713 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1714 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1715 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1716 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1717 I915_WRITE(IPEIR_I965, ipeir);
1718 POSTING_READ(IPEIR_I965);
1719 }
1720 if (eir & GM45_ERROR_PAGE_TABLE) {
1721 u32 pgtbl_err = I915_READ(PGTBL_ER);
1722 pr_err("page table error\n");
1723 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
1724 I915_WRITE(PGTBL_ER, pgtbl_err);
1725 POSTING_READ(PGTBL_ER);
1726 }
1727 }
1728
1729 if (!IS_GEN2(dev)) {
1730 if (eir & I915_ERROR_PAGE_TABLE) {
1731 u32 pgtbl_err = I915_READ(PGTBL_ER);
1732 pr_err("page table error\n");
1733 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
1734 I915_WRITE(PGTBL_ER, pgtbl_err);
1735 POSTING_READ(PGTBL_ER);
1736 }
1737 }
1738
1739 if (eir & I915_ERROR_MEMORY_REFRESH) {
1740 pr_err("memory refresh error:\n");
1741 for_each_pipe(pipe)
1742 pr_err("pipe %c stat: 0x%08x\n",
1743 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1744 /* pipestat has already been acked */
1745 }
1746 if (eir & I915_ERROR_INSTRUCTION) {
1747 pr_err("instruction error\n");
1748 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
1749 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1750 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1751 if (INTEL_INFO(dev)->gen < 4) {
1752 u32 ipeir = I915_READ(IPEIR);
1753
1754 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1755 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
1756 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
1757 I915_WRITE(IPEIR, ipeir);
1758 POSTING_READ(IPEIR);
1759 } else {
1760 u32 ipeir = I915_READ(IPEIR_I965);
1761
1762 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1763 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1764 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1765 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1766 I915_WRITE(IPEIR_I965, ipeir);
1767 POSTING_READ(IPEIR_I965);
1768 }
1769 }
1770
1771 I915_WRITE(EIR, eir);
1772 POSTING_READ(EIR);
1773 eir = I915_READ(EIR);
1774 if (eir) {
1775 /*
1776 * some errors might have become stuck,
1777 * mask them.
1778 */
1779 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1780 I915_WRITE(EMR, I915_READ(EMR) | eir);
1781 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1782 }
1783 }
1784
1785 /**
1786 * i915_handle_error - handle an error interrupt
1787 * @dev: drm device
1788 *
1789 * Do some basic checking of regsiter state at error interrupt time and
1790 * dump it to the syslog. Also call i915_capture_error_state() to make
1791 * sure we get a record and make it available in debugfs. Fire a uevent
1792 * so userspace knows something bad happened (should trigger collection
1793 * of a ring dump etc.).
1794 */
1795 void i915_handle_error(struct drm_device *dev, bool wedged)
1796 {
1797 struct drm_i915_private *dev_priv = dev->dev_private;
1798
1799 i915_capture_error_state(dev);
1800 i915_report_and_clear_eir(dev);
1801
1802 if (wedged) {
1803 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
1804 &dev_priv->gpu_error.reset_counter);
1805
1806 /*
1807 * Wakeup waiting processes so that the reset work function
1808 * i915_error_work_func doesn't deadlock trying to grab various
1809 * locks. By bumping the reset counter first, the woken
1810 * processes will see a reset in progress and back off,
1811 * releasing their locks and then wait for the reset completion.
1812 * We must do this for _all_ gpu waiters that might hold locks
1813 * that the reset work needs to acquire.
1814 *
1815 * Note: The wake_up serves as the required memory barrier to
1816 * ensure that the waiters see the updated value of the reset
1817 * counter atomic_t.
1818 */
1819 i915_error_wake_up(dev_priv, false);
1820 }
1821
1822 /*
1823 * Our reset work can grab modeset locks (since it needs to reset the
1824 * state of outstanding pagelips). Hence it must not be run on our own
1825 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
1826 * code will deadlock.
1827 */
1828 schedule_work(&dev_priv->gpu_error.work);
1829 }
1830
1831 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1832 {
1833 drm_i915_private_t *dev_priv = dev->dev_private;
1834 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1835 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1836 struct drm_i915_gem_object *obj;
1837 struct intel_unpin_work *work;
1838 unsigned long flags;
1839 bool stall_detected;
1840
1841 /* Ignore early vblank irqs */
1842 if (intel_crtc == NULL)
1843 return;
1844
1845 spin_lock_irqsave(&dev->event_lock, flags);
1846 work = intel_crtc->unpin_work;
1847
1848 if (work == NULL ||
1849 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
1850 !work->enable_stall_check) {
1851 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1852 spin_unlock_irqrestore(&dev->event_lock, flags);
1853 return;
1854 }
1855
1856 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1857 obj = work->pending_flip_obj;
1858 if (INTEL_INFO(dev)->gen >= 4) {
1859 int dspsurf = DSPSURF(intel_crtc->plane);
1860 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1861 i915_gem_obj_ggtt_offset(obj);
1862 } else {
1863 int dspaddr = DSPADDR(intel_crtc->plane);
1864 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
1865 crtc->y * crtc->fb->pitches[0] +
1866 crtc->x * crtc->fb->bits_per_pixel/8);
1867 }
1868
1869 spin_unlock_irqrestore(&dev->event_lock, flags);
1870
1871 if (stall_detected) {
1872 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1873 intel_prepare_page_flip(dev, intel_crtc->plane);
1874 }
1875 }
1876
1877 /* Called from drm generic code, passed 'crtc' which
1878 * we use as a pipe index
1879 */
1880 static int i915_enable_vblank(struct drm_device *dev, int pipe)
1881 {
1882 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1883 unsigned long irqflags;
1884
1885 if (!i915_pipe_enabled(dev, pipe))
1886 return -EINVAL;
1887
1888 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1889 if (INTEL_INFO(dev)->gen >= 4)
1890 i915_enable_pipestat(dev_priv, pipe,
1891 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1892 else
1893 i915_enable_pipestat(dev_priv, pipe,
1894 PIPE_VBLANK_INTERRUPT_ENABLE);
1895
1896 /* maintain vblank delivery even in deep C-states */
1897 if (dev_priv->info->gen == 3)
1898 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1899 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1900
1901 return 0;
1902 }
1903
1904 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1905 {
1906 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1907 unsigned long irqflags;
1908 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
1909 DE_PIPE_VBLANK_ILK(pipe);
1910
1911 if (!i915_pipe_enabled(dev, pipe))
1912 return -EINVAL;
1913
1914 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1915 ironlake_enable_display_irq(dev_priv, bit);
1916 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1917
1918 return 0;
1919 }
1920
1921 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1922 {
1923 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1924 unsigned long irqflags;
1925 u32 imr;
1926
1927 if (!i915_pipe_enabled(dev, pipe))
1928 return -EINVAL;
1929
1930 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1931 imr = I915_READ(VLV_IMR);
1932 if (pipe == 0)
1933 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1934 else
1935 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1936 I915_WRITE(VLV_IMR, imr);
1937 i915_enable_pipestat(dev_priv, pipe,
1938 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1939 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1940
1941 return 0;
1942 }
1943
1944 /* Called from drm generic code, passed 'crtc' which
1945 * we use as a pipe index
1946 */
1947 static void i915_disable_vblank(struct drm_device *dev, int pipe)
1948 {
1949 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1950 unsigned long irqflags;
1951
1952 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1953 if (dev_priv->info->gen == 3)
1954 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
1955
1956 i915_disable_pipestat(dev_priv, pipe,
1957 PIPE_VBLANK_INTERRUPT_ENABLE |
1958 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1959 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1960 }
1961
1962 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1963 {
1964 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1965 unsigned long irqflags;
1966 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
1967 DE_PIPE_VBLANK_ILK(pipe);
1968
1969 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1970 ironlake_disable_display_irq(dev_priv, bit);
1971 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1972 }
1973
1974 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1975 {
1976 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1977 unsigned long irqflags;
1978 u32 imr;
1979
1980 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1981 i915_disable_pipestat(dev_priv, pipe,
1982 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1983 imr = I915_READ(VLV_IMR);
1984 if (pipe == 0)
1985 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1986 else
1987 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1988 I915_WRITE(VLV_IMR, imr);
1989 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1990 }
1991
1992 static u32
1993 ring_last_seqno(struct intel_ring_buffer *ring)
1994 {
1995 return list_entry(ring->request_list.prev,
1996 struct drm_i915_gem_request, list)->seqno;
1997 }
1998
1999 static bool
2000 ring_idle(struct intel_ring_buffer *ring, u32 seqno)
2001 {
2002 return (list_empty(&ring->request_list) ||
2003 i915_seqno_passed(seqno, ring_last_seqno(ring)));
2004 }
2005
2006 static struct intel_ring_buffer *
2007 semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
2008 {
2009 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2010 u32 cmd, ipehr, acthd, acthd_min;
2011
2012 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2013 if ((ipehr & ~(0x3 << 16)) !=
2014 (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
2015 return NULL;
2016
2017 /* ACTHD is likely pointing to the dword after the actual command,
2018 * so scan backwards until we find the MBOX.
2019 */
2020 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
2021 acthd_min = max((int)acthd - 3 * 4, 0);
2022 do {
2023 cmd = ioread32(ring->virtual_start + acthd);
2024 if (cmd == ipehr)
2025 break;
2026
2027 acthd -= 4;
2028 if (acthd < acthd_min)
2029 return NULL;
2030 } while (1);
2031
2032 *seqno = ioread32(ring->virtual_start+acthd+4)+1;
2033 return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
2034 }
2035
2036 static int semaphore_passed(struct intel_ring_buffer *ring)
2037 {
2038 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2039 struct intel_ring_buffer *signaller;
2040 u32 seqno, ctl;
2041
2042 ring->hangcheck.deadlock = true;
2043
2044 signaller = semaphore_waits_for(ring, &seqno);
2045 if (signaller == NULL || signaller->hangcheck.deadlock)
2046 return -1;
2047
2048 /* cursory check for an unkickable deadlock */
2049 ctl = I915_READ_CTL(signaller);
2050 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2051 return -1;
2052
2053 return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
2054 }
2055
2056 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2057 {
2058 struct intel_ring_buffer *ring;
2059 int i;
2060
2061 for_each_ring(ring, dev_priv, i)
2062 ring->hangcheck.deadlock = false;
2063 }
2064
2065 static enum intel_ring_hangcheck_action
2066 ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
2067 {
2068 struct drm_device *dev = ring->dev;
2069 struct drm_i915_private *dev_priv = dev->dev_private;
2070 u32 tmp;
2071
2072 if (ring->hangcheck.acthd != acthd)
2073 return HANGCHECK_ACTIVE;
2074
2075 if (IS_GEN2(dev))
2076 return HANGCHECK_HUNG;
2077
2078 /* Is the chip hanging on a WAIT_FOR_EVENT?
2079 * If so we can simply poke the RB_WAIT bit
2080 * and break the hang. This should work on
2081 * all but the second generation chipsets.
2082 */
2083 tmp = I915_READ_CTL(ring);
2084 if (tmp & RING_WAIT) {
2085 DRM_ERROR("Kicking stuck wait on %s\n",
2086 ring->name);
2087 i915_handle_error(dev, false);
2088 I915_WRITE_CTL(ring, tmp);
2089 return HANGCHECK_KICK;
2090 }
2091
2092 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2093 switch (semaphore_passed(ring)) {
2094 default:
2095 return HANGCHECK_HUNG;
2096 case 1:
2097 DRM_ERROR("Kicking stuck semaphore on %s\n",
2098 ring->name);
2099 i915_handle_error(dev, false);
2100 I915_WRITE_CTL(ring, tmp);
2101 return HANGCHECK_KICK;
2102 case 0:
2103 return HANGCHECK_WAIT;
2104 }
2105 }
2106
2107 return HANGCHECK_HUNG;
2108 }
2109
2110 /**
2111 * This is called when the chip hasn't reported back with completed
2112 * batchbuffers in a long time. We keep track per ring seqno progress and
2113 * if there are no progress, hangcheck score for that ring is increased.
2114 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2115 * we kick the ring. If we see no progress on three subsequent calls
2116 * we assume chip is wedged and try to fix it by resetting the chip.
2117 */
2118 static void i915_hangcheck_elapsed(unsigned long data)
2119 {
2120 struct drm_device *dev = (struct drm_device *)data;
2121 drm_i915_private_t *dev_priv = dev->dev_private;
2122 struct intel_ring_buffer *ring;
2123 int i;
2124 int busy_count = 0, rings_hung = 0;
2125 bool stuck[I915_NUM_RINGS] = { 0 };
2126 #define BUSY 1
2127 #define KICK 5
2128 #define HUNG 20
2129 #define FIRE 30
2130
2131 if (!i915_enable_hangcheck)
2132 return;
2133
2134 for_each_ring(ring, dev_priv, i) {
2135 u32 seqno, acthd;
2136 bool busy = true;
2137
2138 semaphore_clear_deadlocks(dev_priv);
2139
2140 seqno = ring->get_seqno(ring, false);
2141 acthd = intel_ring_get_active_head(ring);
2142
2143 if (ring->hangcheck.seqno == seqno) {
2144 if (ring_idle(ring, seqno)) {
2145 ring->hangcheck.action = HANGCHECK_IDLE;
2146
2147 if (waitqueue_active(&ring->irq_queue)) {
2148 /* Issue a wake-up to catch stuck h/w. */
2149 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2150 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2151 ring->name);
2152 wake_up_all(&ring->irq_queue);
2153 }
2154 /* Safeguard against driver failure */
2155 ring->hangcheck.score += BUSY;
2156 } else
2157 busy = false;
2158 } else {
2159 /* We always increment the hangcheck score
2160 * if the ring is busy and still processing
2161 * the same request, so that no single request
2162 * can run indefinitely (such as a chain of
2163 * batches). The only time we do not increment
2164 * the hangcheck score on this ring, if this
2165 * ring is in a legitimate wait for another
2166 * ring. In that case the waiting ring is a
2167 * victim and we want to be sure we catch the
2168 * right culprit. Then every time we do kick
2169 * the ring, add a small increment to the
2170 * score so that we can catch a batch that is
2171 * being repeatedly kicked and so responsible
2172 * for stalling the machine.
2173 */
2174 ring->hangcheck.action = ring_stuck(ring,
2175 acthd);
2176
2177 switch (ring->hangcheck.action) {
2178 case HANGCHECK_IDLE:
2179 case HANGCHECK_WAIT:
2180 break;
2181 case HANGCHECK_ACTIVE:
2182 ring->hangcheck.score += BUSY;
2183 break;
2184 case HANGCHECK_KICK:
2185 ring->hangcheck.score += KICK;
2186 break;
2187 case HANGCHECK_HUNG:
2188 ring->hangcheck.score += HUNG;
2189 stuck[i] = true;
2190 break;
2191 }
2192 }
2193 } else {
2194 ring->hangcheck.action = HANGCHECK_ACTIVE;
2195
2196 /* Gradually reduce the count so that we catch DoS
2197 * attempts across multiple batches.
2198 */
2199 if (ring->hangcheck.score > 0)
2200 ring->hangcheck.score--;
2201 }
2202
2203 ring->hangcheck.seqno = seqno;
2204 ring->hangcheck.acthd = acthd;
2205 busy_count += busy;
2206 }
2207
2208 for_each_ring(ring, dev_priv, i) {
2209 if (ring->hangcheck.score > FIRE) {
2210 DRM_INFO("%s on %s\n",
2211 stuck[i] ? "stuck" : "no progress",
2212 ring->name);
2213 rings_hung++;
2214 }
2215 }
2216
2217 if (rings_hung)
2218 return i915_handle_error(dev, true);
2219
2220 if (busy_count)
2221 /* Reset timer case chip hangs without another request
2222 * being added */
2223 i915_queue_hangcheck(dev);
2224 }
2225
2226 void i915_queue_hangcheck(struct drm_device *dev)
2227 {
2228 struct drm_i915_private *dev_priv = dev->dev_private;
2229 if (!i915_enable_hangcheck)
2230 return;
2231
2232 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2233 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2234 }
2235
2236 static void ibx_irq_preinstall(struct drm_device *dev)
2237 {
2238 struct drm_i915_private *dev_priv = dev->dev_private;
2239
2240 if (HAS_PCH_NOP(dev))
2241 return;
2242
2243 /* south display irq */
2244 I915_WRITE(SDEIMR, 0xffffffff);
2245 /*
2246 * SDEIER is also touched by the interrupt handler to work around missed
2247 * PCH interrupts. Hence we can't update it after the interrupt handler
2248 * is enabled - instead we unconditionally enable all PCH interrupt
2249 * sources here, but then only unmask them as needed with SDEIMR.
2250 */
2251 I915_WRITE(SDEIER, 0xffffffff);
2252 POSTING_READ(SDEIER);
2253 }
2254
2255 static void gen5_gt_irq_preinstall(struct drm_device *dev)
2256 {
2257 struct drm_i915_private *dev_priv = dev->dev_private;
2258
2259 /* and GT */
2260 I915_WRITE(GTIMR, 0xffffffff);
2261 I915_WRITE(GTIER, 0x0);
2262 POSTING_READ(GTIER);
2263
2264 if (INTEL_INFO(dev)->gen >= 6) {
2265 /* and PM */
2266 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2267 I915_WRITE(GEN6_PMIER, 0x0);
2268 POSTING_READ(GEN6_PMIER);
2269 }
2270 }
2271
2272 /* drm_dma.h hooks
2273 */
2274 static void ironlake_irq_preinstall(struct drm_device *dev)
2275 {
2276 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2277
2278 atomic_set(&dev_priv->irq_received, 0);
2279
2280 I915_WRITE(HWSTAM, 0xeffe);
2281
2282 I915_WRITE(DEIMR, 0xffffffff);
2283 I915_WRITE(DEIER, 0x0);
2284 POSTING_READ(DEIER);
2285
2286 gen5_gt_irq_preinstall(dev);
2287
2288 ibx_irq_preinstall(dev);
2289 }
2290
2291 static void valleyview_irq_preinstall(struct drm_device *dev)
2292 {
2293 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2294 int pipe;
2295
2296 atomic_set(&dev_priv->irq_received, 0);
2297
2298 /* VLV magic */
2299 I915_WRITE(VLV_IMR, 0);
2300 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2301 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2302 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2303
2304 /* and GT */
2305 I915_WRITE(GTIIR, I915_READ(GTIIR));
2306 I915_WRITE(GTIIR, I915_READ(GTIIR));
2307
2308 gen5_gt_irq_preinstall(dev);
2309
2310 I915_WRITE(DPINVGTT, 0xff);
2311
2312 I915_WRITE(PORT_HOTPLUG_EN, 0);
2313 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2314 for_each_pipe(pipe)
2315 I915_WRITE(PIPESTAT(pipe), 0xffff);
2316 I915_WRITE(VLV_IIR, 0xffffffff);
2317 I915_WRITE(VLV_IMR, 0xffffffff);
2318 I915_WRITE(VLV_IER, 0x0);
2319 POSTING_READ(VLV_IER);
2320 }
2321
2322 static void ibx_hpd_irq_setup(struct drm_device *dev)
2323 {
2324 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2325 struct drm_mode_config *mode_config = &dev->mode_config;
2326 struct intel_encoder *intel_encoder;
2327 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
2328
2329 if (HAS_PCH_IBX(dev)) {
2330 hotplug_irqs = SDE_HOTPLUG_MASK;
2331 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2332 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2333 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
2334 } else {
2335 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
2336 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2337 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2338 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
2339 }
2340
2341 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
2342
2343 /*
2344 * Enable digital hotplug on the PCH, and configure the DP short pulse
2345 * duration to 2ms (which is the minimum in the Display Port spec)
2346 *
2347 * This register is the same on all known PCH chips.
2348 */
2349 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2350 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2351 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2352 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2353 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2354 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2355 }
2356
2357 static void ibx_irq_postinstall(struct drm_device *dev)
2358 {
2359 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2360 u32 mask;
2361
2362 if (HAS_PCH_NOP(dev))
2363 return;
2364
2365 if (HAS_PCH_IBX(dev)) {
2366 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
2367 SDE_TRANSA_FIFO_UNDER | SDE_POISON;
2368 } else {
2369 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2370
2371 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2372 }
2373
2374 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2375 I915_WRITE(SDEIMR, ~mask);
2376 }
2377
2378 static void gen5_gt_irq_postinstall(struct drm_device *dev)
2379 {
2380 struct drm_i915_private *dev_priv = dev->dev_private;
2381 u32 pm_irqs, gt_irqs;
2382
2383 pm_irqs = gt_irqs = 0;
2384
2385 dev_priv->gt_irq_mask = ~0;
2386 if (HAS_L3_DPF(dev)) {
2387 /* L3 parity interrupt is always unmasked. */
2388 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
2389 gt_irqs |= GT_PARITY_ERROR(dev);
2390 }
2391
2392 gt_irqs |= GT_RENDER_USER_INTERRUPT;
2393 if (IS_GEN5(dev)) {
2394 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
2395 ILK_BSD_USER_INTERRUPT;
2396 } else {
2397 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
2398 }
2399
2400 I915_WRITE(GTIIR, I915_READ(GTIIR));
2401 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2402 I915_WRITE(GTIER, gt_irqs);
2403 POSTING_READ(GTIER);
2404
2405 if (INTEL_INFO(dev)->gen >= 6) {
2406 pm_irqs |= GEN6_PM_RPS_EVENTS;
2407
2408 if (HAS_VEBOX(dev))
2409 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
2410
2411 dev_priv->pm_irq_mask = 0xffffffff;
2412 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2413 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
2414 I915_WRITE(GEN6_PMIER, pm_irqs);
2415 POSTING_READ(GEN6_PMIER);
2416 }
2417 }
2418
2419 static int ironlake_irq_postinstall(struct drm_device *dev)
2420 {
2421 unsigned long irqflags;
2422 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2423 u32 display_mask, extra_mask;
2424
2425 if (INTEL_INFO(dev)->gen >= 7) {
2426 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
2427 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
2428 DE_PLANEB_FLIP_DONE_IVB |
2429 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB |
2430 DE_ERR_INT_IVB);
2431 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
2432 DE_PIPEA_VBLANK_IVB);
2433
2434 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2435 } else {
2436 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2437 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
2438 DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
2439 DE_PIPEA_FIFO_UNDERRUN | DE_POISON);
2440 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT;
2441 }
2442
2443 dev_priv->irq_mask = ~display_mask;
2444
2445 /* should always can generate irq */
2446 I915_WRITE(DEIIR, I915_READ(DEIIR));
2447 I915_WRITE(DEIMR, dev_priv->irq_mask);
2448 I915_WRITE(DEIER, display_mask | extra_mask);
2449 POSTING_READ(DEIER);
2450
2451 gen5_gt_irq_postinstall(dev);
2452
2453 ibx_irq_postinstall(dev);
2454
2455 if (IS_IRONLAKE_M(dev)) {
2456 /* Enable PCU event interrupts
2457 *
2458 * spinlocking not required here for correctness since interrupt
2459 * setup is guaranteed to run in single-threaded context. But we
2460 * need it to make the assert_spin_locked happy. */
2461 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2462 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2463 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2464 }
2465
2466 return 0;
2467 }
2468
2469 static int valleyview_irq_postinstall(struct drm_device *dev)
2470 {
2471 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2472 u32 enable_mask;
2473 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
2474 unsigned long irqflags;
2475
2476 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
2477 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2478 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2479 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2480 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2481
2482 /*
2483 *Leave vblank interrupts masked initially. enable/disable will
2484 * toggle them based on usage.
2485 */
2486 dev_priv->irq_mask = (~enable_mask) |
2487 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2488 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2489
2490 I915_WRITE(PORT_HOTPLUG_EN, 0);
2491 POSTING_READ(PORT_HOTPLUG_EN);
2492
2493 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2494 I915_WRITE(VLV_IER, enable_mask);
2495 I915_WRITE(VLV_IIR, 0xffffffff);
2496 I915_WRITE(PIPESTAT(0), 0xffff);
2497 I915_WRITE(PIPESTAT(1), 0xffff);
2498 POSTING_READ(VLV_IER);
2499
2500 /* Interrupt setup is already guaranteed to be single-threaded, this is
2501 * just to make the assert_spin_locked check happy. */
2502 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2503 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
2504 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
2505 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
2506 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2507
2508 I915_WRITE(VLV_IIR, 0xffffffff);
2509 I915_WRITE(VLV_IIR, 0xffffffff);
2510
2511 gen5_gt_irq_postinstall(dev);
2512
2513 /* ack & enable invalid PTE error interrupts */
2514 #if 0 /* FIXME: add support to irq handler for checking these bits */
2515 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2516 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2517 #endif
2518
2519 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2520
2521 return 0;
2522 }
2523
2524 static void valleyview_irq_uninstall(struct drm_device *dev)
2525 {
2526 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2527 int pipe;
2528
2529 if (!dev_priv)
2530 return;
2531
2532 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2533
2534 for_each_pipe(pipe)
2535 I915_WRITE(PIPESTAT(pipe), 0xffff);
2536
2537 I915_WRITE(HWSTAM, 0xffffffff);
2538 I915_WRITE(PORT_HOTPLUG_EN, 0);
2539 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2540 for_each_pipe(pipe)
2541 I915_WRITE(PIPESTAT(pipe), 0xffff);
2542 I915_WRITE(VLV_IIR, 0xffffffff);
2543 I915_WRITE(VLV_IMR, 0xffffffff);
2544 I915_WRITE(VLV_IER, 0x0);
2545 POSTING_READ(VLV_IER);
2546 }
2547
2548 static void ironlake_irq_uninstall(struct drm_device *dev)
2549 {
2550 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2551
2552 if (!dev_priv)
2553 return;
2554
2555 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2556
2557 I915_WRITE(HWSTAM, 0xffffffff);
2558
2559 I915_WRITE(DEIMR, 0xffffffff);
2560 I915_WRITE(DEIER, 0x0);
2561 I915_WRITE(DEIIR, I915_READ(DEIIR));
2562 if (IS_GEN7(dev))
2563 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2564
2565 I915_WRITE(GTIMR, 0xffffffff);
2566 I915_WRITE(GTIER, 0x0);
2567 I915_WRITE(GTIIR, I915_READ(GTIIR));
2568
2569 if (HAS_PCH_NOP(dev))
2570 return;
2571
2572 I915_WRITE(SDEIMR, 0xffffffff);
2573 I915_WRITE(SDEIER, 0x0);
2574 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2575 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
2576 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2577 }
2578
2579 static void i8xx_irq_preinstall(struct drm_device * dev)
2580 {
2581 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2582 int pipe;
2583
2584 atomic_set(&dev_priv->irq_received, 0);
2585
2586 for_each_pipe(pipe)
2587 I915_WRITE(PIPESTAT(pipe), 0);
2588 I915_WRITE16(IMR, 0xffff);
2589 I915_WRITE16(IER, 0x0);
2590 POSTING_READ16(IER);
2591 }
2592
2593 static int i8xx_irq_postinstall(struct drm_device *dev)
2594 {
2595 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2596
2597 I915_WRITE16(EMR,
2598 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2599
2600 /* Unmask the interrupts that we always want on. */
2601 dev_priv->irq_mask =
2602 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2603 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2604 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2605 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2606 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2607 I915_WRITE16(IMR, dev_priv->irq_mask);
2608
2609 I915_WRITE16(IER,
2610 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2611 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2612 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2613 I915_USER_INTERRUPT);
2614 POSTING_READ16(IER);
2615
2616 return 0;
2617 }
2618
2619 /*
2620 * Returns true when a page flip has completed.
2621 */
2622 static bool i8xx_handle_vblank(struct drm_device *dev,
2623 int pipe, u16 iir)
2624 {
2625 drm_i915_private_t *dev_priv = dev->dev_private;
2626 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
2627
2628 if (!drm_handle_vblank(dev, pipe))
2629 return false;
2630
2631 if ((iir & flip_pending) == 0)
2632 return false;
2633
2634 intel_prepare_page_flip(dev, pipe);
2635
2636 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2637 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2638 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2639 * the flip is completed (no longer pending). Since this doesn't raise
2640 * an interrupt per se, we watch for the change at vblank.
2641 */
2642 if (I915_READ16(ISR) & flip_pending)
2643 return false;
2644
2645 intel_finish_page_flip(dev, pipe);
2646
2647 return true;
2648 }
2649
2650 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
2651 {
2652 struct drm_device *dev = (struct drm_device *) arg;
2653 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2654 u16 iir, new_iir;
2655 u32 pipe_stats[2];
2656 unsigned long irqflags;
2657 int pipe;
2658 u16 flip_mask =
2659 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2660 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2661
2662 atomic_inc(&dev_priv->irq_received);
2663
2664 iir = I915_READ16(IIR);
2665 if (iir == 0)
2666 return IRQ_NONE;
2667
2668 while (iir & ~flip_mask) {
2669 /* Can't rely on pipestat interrupt bit in iir as it might
2670 * have been cleared after the pipestat interrupt was received.
2671 * It doesn't set the bit in iir again, but it still produces
2672 * interrupts (for non-MSI).
2673 */
2674 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2675 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2676 i915_handle_error(dev, false);
2677
2678 for_each_pipe(pipe) {
2679 int reg = PIPESTAT(pipe);
2680 pipe_stats[pipe] = I915_READ(reg);
2681
2682 /*
2683 * Clear the PIPE*STAT regs before the IIR
2684 */
2685 if (pipe_stats[pipe] & 0x8000ffff) {
2686 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2687 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2688 pipe_name(pipe));
2689 I915_WRITE(reg, pipe_stats[pipe]);
2690 }
2691 }
2692 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2693
2694 I915_WRITE16(IIR, iir & ~flip_mask);
2695 new_iir = I915_READ16(IIR); /* Flush posted writes */
2696
2697 i915_update_dri1_breadcrumb(dev);
2698
2699 if (iir & I915_USER_INTERRUPT)
2700 notify_ring(dev, &dev_priv->ring[RCS]);
2701
2702 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2703 i8xx_handle_vblank(dev, 0, iir))
2704 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
2705
2706 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2707 i8xx_handle_vblank(dev, 1, iir))
2708 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
2709
2710 iir = new_iir;
2711 }
2712
2713 return IRQ_HANDLED;
2714 }
2715
2716 static void i8xx_irq_uninstall(struct drm_device * dev)
2717 {
2718 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2719 int pipe;
2720
2721 for_each_pipe(pipe) {
2722 /* Clear enable bits; then clear status bits */
2723 I915_WRITE(PIPESTAT(pipe), 0);
2724 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2725 }
2726 I915_WRITE16(IMR, 0xffff);
2727 I915_WRITE16(IER, 0x0);
2728 I915_WRITE16(IIR, I915_READ16(IIR));
2729 }
2730
2731 static void i915_irq_preinstall(struct drm_device * dev)
2732 {
2733 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2734 int pipe;
2735
2736 atomic_set(&dev_priv->irq_received, 0);
2737
2738 if (I915_HAS_HOTPLUG(dev)) {
2739 I915_WRITE(PORT_HOTPLUG_EN, 0);
2740 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2741 }
2742
2743 I915_WRITE16(HWSTAM, 0xeffe);
2744 for_each_pipe(pipe)
2745 I915_WRITE(PIPESTAT(pipe), 0);
2746 I915_WRITE(IMR, 0xffffffff);
2747 I915_WRITE(IER, 0x0);
2748 POSTING_READ(IER);
2749 }
2750
2751 static int i915_irq_postinstall(struct drm_device *dev)
2752 {
2753 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2754 u32 enable_mask;
2755
2756 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2757
2758 /* Unmask the interrupts that we always want on. */
2759 dev_priv->irq_mask =
2760 ~(I915_ASLE_INTERRUPT |
2761 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2762 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2763 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2764 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2765 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2766
2767 enable_mask =
2768 I915_ASLE_INTERRUPT |
2769 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2770 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2771 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2772 I915_USER_INTERRUPT;
2773
2774 if (I915_HAS_HOTPLUG(dev)) {
2775 I915_WRITE(PORT_HOTPLUG_EN, 0);
2776 POSTING_READ(PORT_HOTPLUG_EN);
2777
2778 /* Enable in IER... */
2779 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2780 /* and unmask in IMR */
2781 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2782 }
2783
2784 I915_WRITE(IMR, dev_priv->irq_mask);
2785 I915_WRITE(IER, enable_mask);
2786 POSTING_READ(IER);
2787
2788 i915_enable_asle_pipestat(dev);
2789
2790 return 0;
2791 }
2792
2793 /*
2794 * Returns true when a page flip has completed.
2795 */
2796 static bool i915_handle_vblank(struct drm_device *dev,
2797 int plane, int pipe, u32 iir)
2798 {
2799 drm_i915_private_t *dev_priv = dev->dev_private;
2800 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
2801
2802 if (!drm_handle_vblank(dev, pipe))
2803 return false;
2804
2805 if ((iir & flip_pending) == 0)
2806 return false;
2807
2808 intel_prepare_page_flip(dev, plane);
2809
2810 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2811 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2812 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2813 * the flip is completed (no longer pending). Since this doesn't raise
2814 * an interrupt per se, we watch for the change at vblank.
2815 */
2816 if (I915_READ(ISR) & flip_pending)
2817 return false;
2818
2819 intel_finish_page_flip(dev, pipe);
2820
2821 return true;
2822 }
2823
2824 static irqreturn_t i915_irq_handler(int irq, void *arg)
2825 {
2826 struct drm_device *dev = (struct drm_device *) arg;
2827 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2828 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
2829 unsigned long irqflags;
2830 u32 flip_mask =
2831 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2832 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2833 int pipe, ret = IRQ_NONE;
2834
2835 atomic_inc(&dev_priv->irq_received);
2836
2837 iir = I915_READ(IIR);
2838 do {
2839 bool irq_received = (iir & ~flip_mask) != 0;
2840 bool blc_event = false;
2841
2842 /* Can't rely on pipestat interrupt bit in iir as it might
2843 * have been cleared after the pipestat interrupt was received.
2844 * It doesn't set the bit in iir again, but it still produces
2845 * interrupts (for non-MSI).
2846 */
2847 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2848 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2849 i915_handle_error(dev, false);
2850
2851 for_each_pipe(pipe) {
2852 int reg = PIPESTAT(pipe);
2853 pipe_stats[pipe] = I915_READ(reg);
2854
2855 /* Clear the PIPE*STAT regs before the IIR */
2856 if (pipe_stats[pipe] & 0x8000ffff) {
2857 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2858 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2859 pipe_name(pipe));
2860 I915_WRITE(reg, pipe_stats[pipe]);
2861 irq_received = true;
2862 }
2863 }
2864 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2865
2866 if (!irq_received)
2867 break;
2868
2869 /* Consume port. Then clear IIR or we'll miss events */
2870 if ((I915_HAS_HOTPLUG(dev)) &&
2871 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2872 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2873 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
2874
2875 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2876 hotplug_status);
2877
2878 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
2879
2880 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2881 POSTING_READ(PORT_HOTPLUG_STAT);
2882 }
2883
2884 I915_WRITE(IIR, iir & ~flip_mask);
2885 new_iir = I915_READ(IIR); /* Flush posted writes */
2886
2887 if (iir & I915_USER_INTERRUPT)
2888 notify_ring(dev, &dev_priv->ring[RCS]);
2889
2890 for_each_pipe(pipe) {
2891 int plane = pipe;
2892 if (IS_MOBILE(dev))
2893 plane = !plane;
2894
2895 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
2896 i915_handle_vblank(dev, plane, pipe, iir))
2897 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
2898
2899 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2900 blc_event = true;
2901 }
2902
2903 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2904 intel_opregion_asle_intr(dev);
2905
2906 /* With MSI, interrupts are only generated when iir
2907 * transitions from zero to nonzero. If another bit got
2908 * set while we were handling the existing iir bits, then
2909 * we would never get another interrupt.
2910 *
2911 * This is fine on non-MSI as well, as if we hit this path
2912 * we avoid exiting the interrupt handler only to generate
2913 * another one.
2914 *
2915 * Note that for MSI this could cause a stray interrupt report
2916 * if an interrupt landed in the time between writing IIR and
2917 * the posting read. This should be rare enough to never
2918 * trigger the 99% of 100,000 interrupts test for disabling
2919 * stray interrupts.
2920 */
2921 ret = IRQ_HANDLED;
2922 iir = new_iir;
2923 } while (iir & ~flip_mask);
2924
2925 i915_update_dri1_breadcrumb(dev);
2926
2927 return ret;
2928 }
2929
2930 static void i915_irq_uninstall(struct drm_device * dev)
2931 {
2932 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2933 int pipe;
2934
2935 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2936
2937 if (I915_HAS_HOTPLUG(dev)) {
2938 I915_WRITE(PORT_HOTPLUG_EN, 0);
2939 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2940 }
2941
2942 I915_WRITE16(HWSTAM, 0xffff);
2943 for_each_pipe(pipe) {
2944 /* Clear enable bits; then clear status bits */
2945 I915_WRITE(PIPESTAT(pipe), 0);
2946 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2947 }
2948 I915_WRITE(IMR, 0xffffffff);
2949 I915_WRITE(IER, 0x0);
2950
2951 I915_WRITE(IIR, I915_READ(IIR));
2952 }
2953
2954 static void i965_irq_preinstall(struct drm_device * dev)
2955 {
2956 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2957 int pipe;
2958
2959 atomic_set(&dev_priv->irq_received, 0);
2960
2961 I915_WRITE(PORT_HOTPLUG_EN, 0);
2962 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2963
2964 I915_WRITE(HWSTAM, 0xeffe);
2965 for_each_pipe(pipe)
2966 I915_WRITE(PIPESTAT(pipe), 0);
2967 I915_WRITE(IMR, 0xffffffff);
2968 I915_WRITE(IER, 0x0);
2969 POSTING_READ(IER);
2970 }
2971
2972 static int i965_irq_postinstall(struct drm_device *dev)
2973 {
2974 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2975 u32 enable_mask;
2976 u32 error_mask;
2977 unsigned long irqflags;
2978
2979 /* Unmask the interrupts that we always want on. */
2980 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
2981 I915_DISPLAY_PORT_INTERRUPT |
2982 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2983 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2984 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2985 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2986 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2987
2988 enable_mask = ~dev_priv->irq_mask;
2989 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2990 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
2991 enable_mask |= I915_USER_INTERRUPT;
2992
2993 if (IS_G4X(dev))
2994 enable_mask |= I915_BSD_USER_INTERRUPT;
2995
2996 /* Interrupt setup is already guaranteed to be single-threaded, this is
2997 * just to make the assert_spin_locked check happy. */
2998 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2999 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
3000 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3001
3002 /*
3003 * Enable some error detection, note the instruction error mask
3004 * bit is reserved, so we leave it masked.
3005 */
3006 if (IS_G4X(dev)) {
3007 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3008 GM45_ERROR_MEM_PRIV |
3009 GM45_ERROR_CP_PRIV |
3010 I915_ERROR_MEMORY_REFRESH);
3011 } else {
3012 error_mask = ~(I915_ERROR_PAGE_TABLE |
3013 I915_ERROR_MEMORY_REFRESH);
3014 }
3015 I915_WRITE(EMR, error_mask);
3016
3017 I915_WRITE(IMR, dev_priv->irq_mask);
3018 I915_WRITE(IER, enable_mask);
3019 POSTING_READ(IER);
3020
3021 I915_WRITE(PORT_HOTPLUG_EN, 0);
3022 POSTING_READ(PORT_HOTPLUG_EN);
3023
3024 i915_enable_asle_pipestat(dev);
3025
3026 return 0;
3027 }
3028
3029 static void i915_hpd_irq_setup(struct drm_device *dev)
3030 {
3031 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3032 struct drm_mode_config *mode_config = &dev->mode_config;
3033 struct intel_encoder *intel_encoder;
3034 u32 hotplug_en;
3035
3036 assert_spin_locked(&dev_priv->irq_lock);
3037
3038 if (I915_HAS_HOTPLUG(dev)) {
3039 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3040 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3041 /* Note HDMI and DP share hotplug bits */
3042 /* enable bits are the same for all generations */
3043 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3044 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3045 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
3046 /* Programming the CRT detection parameters tends
3047 to generate a spurious hotplug event about three
3048 seconds later. So just do it once.
3049 */
3050 if (IS_G4X(dev))
3051 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
3052 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
3053 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
3054
3055 /* Ignore TV since it's buggy */
3056 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3057 }
3058 }
3059
3060 static irqreturn_t i965_irq_handler(int irq, void *arg)
3061 {
3062 struct drm_device *dev = (struct drm_device *) arg;
3063 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3064 u32 iir, new_iir;
3065 u32 pipe_stats[I915_MAX_PIPES];
3066 unsigned long irqflags;
3067 int irq_received;
3068 int ret = IRQ_NONE, pipe;
3069 u32 flip_mask =
3070 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3071 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3072
3073 atomic_inc(&dev_priv->irq_received);
3074
3075 iir = I915_READ(IIR);
3076
3077 for (;;) {
3078 bool blc_event = false;
3079
3080 irq_received = (iir & ~flip_mask) != 0;
3081
3082 /* Can't rely on pipestat interrupt bit in iir as it might
3083 * have been cleared after the pipestat interrupt was received.
3084 * It doesn't set the bit in iir again, but it still produces
3085 * interrupts (for non-MSI).
3086 */
3087 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3088 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3089 i915_handle_error(dev, false);
3090
3091 for_each_pipe(pipe) {
3092 int reg = PIPESTAT(pipe);
3093 pipe_stats[pipe] = I915_READ(reg);
3094
3095 /*
3096 * Clear the PIPE*STAT regs before the IIR
3097 */
3098 if (pipe_stats[pipe] & 0x8000ffff) {
3099 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3100 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3101 pipe_name(pipe));
3102 I915_WRITE(reg, pipe_stats[pipe]);
3103 irq_received = 1;
3104 }
3105 }
3106 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3107
3108 if (!irq_received)
3109 break;
3110
3111 ret = IRQ_HANDLED;
3112
3113 /* Consume port. Then clear IIR or we'll miss events */
3114 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
3115 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3116 u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
3117 HOTPLUG_INT_STATUS_G4X :
3118 HOTPLUG_INT_STATUS_I915);
3119
3120 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3121 hotplug_status);
3122
3123 intel_hpd_irq_handler(dev, hotplug_trigger,
3124 IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915);
3125
3126 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3127 I915_READ(PORT_HOTPLUG_STAT);
3128 }
3129
3130 I915_WRITE(IIR, iir & ~flip_mask);
3131 new_iir = I915_READ(IIR); /* Flush posted writes */
3132
3133 if (iir & I915_USER_INTERRUPT)
3134 notify_ring(dev, &dev_priv->ring[RCS]);
3135 if (iir & I915_BSD_USER_INTERRUPT)
3136 notify_ring(dev, &dev_priv->ring[VCS]);
3137
3138 for_each_pipe(pipe) {
3139 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
3140 i915_handle_vblank(dev, pipe, pipe, iir))
3141 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
3142
3143 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3144 blc_event = true;
3145 }
3146
3147
3148 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3149 intel_opregion_asle_intr(dev);
3150
3151 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3152 gmbus_irq_handler(dev);
3153
3154 /* With MSI, interrupts are only generated when iir
3155 * transitions from zero to nonzero. If another bit got
3156 * set while we were handling the existing iir bits, then
3157 * we would never get another interrupt.
3158 *
3159 * This is fine on non-MSI as well, as if we hit this path
3160 * we avoid exiting the interrupt handler only to generate
3161 * another one.
3162 *
3163 * Note that for MSI this could cause a stray interrupt report
3164 * if an interrupt landed in the time between writing IIR and
3165 * the posting read. This should be rare enough to never
3166 * trigger the 99% of 100,000 interrupts test for disabling
3167 * stray interrupts.
3168 */
3169 iir = new_iir;
3170 }
3171
3172 i915_update_dri1_breadcrumb(dev);
3173
3174 return ret;
3175 }
3176
3177 static void i965_irq_uninstall(struct drm_device * dev)
3178 {
3179 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3180 int pipe;
3181
3182 if (!dev_priv)
3183 return;
3184
3185 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3186
3187 I915_WRITE(PORT_HOTPLUG_EN, 0);
3188 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3189
3190 I915_WRITE(HWSTAM, 0xffffffff);
3191 for_each_pipe(pipe)
3192 I915_WRITE(PIPESTAT(pipe), 0);
3193 I915_WRITE(IMR, 0xffffffff);
3194 I915_WRITE(IER, 0x0);
3195
3196 for_each_pipe(pipe)
3197 I915_WRITE(PIPESTAT(pipe),
3198 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3199 I915_WRITE(IIR, I915_READ(IIR));
3200 }
3201
3202 static void i915_reenable_hotplug_timer_func(unsigned long data)
3203 {
3204 drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
3205 struct drm_device *dev = dev_priv->dev;
3206 struct drm_mode_config *mode_config = &dev->mode_config;
3207 unsigned long irqflags;
3208 int i;
3209
3210 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3211 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3212 struct drm_connector *connector;
3213
3214 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3215 continue;
3216
3217 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3218
3219 list_for_each_entry(connector, &mode_config->connector_list, head) {
3220 struct intel_connector *intel_connector = to_intel_connector(connector);
3221
3222 if (intel_connector->encoder->hpd_pin == i) {
3223 if (connector->polled != intel_connector->polled)
3224 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3225 drm_get_connector_name(connector));
3226 connector->polled = intel_connector->polled;
3227 if (!connector->polled)
3228 connector->polled = DRM_CONNECTOR_POLL_HPD;
3229 }
3230 }
3231 }
3232 if (dev_priv->display.hpd_irq_setup)
3233 dev_priv->display.hpd_irq_setup(dev);
3234 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3235 }
3236
3237 void intel_irq_init(struct drm_device *dev)
3238 {
3239 struct drm_i915_private *dev_priv = dev->dev_private;
3240
3241 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
3242 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
3243 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
3244 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
3245
3246 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3247 i915_hangcheck_elapsed,
3248 (unsigned long) dev);
3249 setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
3250 (unsigned long) dev_priv);
3251
3252 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
3253
3254 if (IS_GEN2(dev)) {
3255 dev->max_vblank_count = 0;
3256 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
3257 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
3258 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3259 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
3260 } else {
3261 dev->driver->get_vblank_counter = i915_get_vblank_counter;
3262 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
3263 }
3264
3265 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
3266 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
3267 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3268 }
3269
3270 if (IS_VALLEYVIEW(dev)) {
3271 dev->driver->irq_handler = valleyview_irq_handler;
3272 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3273 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3274 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3275 dev->driver->enable_vblank = valleyview_enable_vblank;
3276 dev->driver->disable_vblank = valleyview_disable_vblank;
3277 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3278 } else if (HAS_PCH_SPLIT(dev)) {
3279 dev->driver->irq_handler = ironlake_irq_handler;
3280 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3281 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3282 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3283 dev->driver->enable_vblank = ironlake_enable_vblank;
3284 dev->driver->disable_vblank = ironlake_disable_vblank;
3285 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3286 } else {
3287 if (INTEL_INFO(dev)->gen == 2) {
3288 dev->driver->irq_preinstall = i8xx_irq_preinstall;
3289 dev->driver->irq_postinstall = i8xx_irq_postinstall;
3290 dev->driver->irq_handler = i8xx_irq_handler;
3291 dev->driver->irq_uninstall = i8xx_irq_uninstall;
3292 } else if (INTEL_INFO(dev)->gen == 3) {
3293 dev->driver->irq_preinstall = i915_irq_preinstall;
3294 dev->driver->irq_postinstall = i915_irq_postinstall;
3295 dev->driver->irq_uninstall = i915_irq_uninstall;
3296 dev->driver->irq_handler = i915_irq_handler;
3297 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3298 } else {
3299 dev->driver->irq_preinstall = i965_irq_preinstall;
3300 dev->driver->irq_postinstall = i965_irq_postinstall;
3301 dev->driver->irq_uninstall = i965_irq_uninstall;
3302 dev->driver->irq_handler = i965_irq_handler;
3303 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3304 }
3305 dev->driver->enable_vblank = i915_enable_vblank;
3306 dev->driver->disable_vblank = i915_disable_vblank;
3307 }
3308 }
3309
3310 void intel_hpd_init(struct drm_device *dev)
3311 {
3312 struct drm_i915_private *dev_priv = dev->dev_private;
3313 struct drm_mode_config *mode_config = &dev->mode_config;
3314 struct drm_connector *connector;
3315 unsigned long irqflags;
3316 int i;
3317
3318 for (i = 1; i < HPD_NUM_PINS; i++) {
3319 dev_priv->hpd_stats[i].hpd_cnt = 0;
3320 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3321 }
3322 list_for_each_entry(connector, &mode_config->connector_list, head) {
3323 struct intel_connector *intel_connector = to_intel_connector(connector);
3324 connector->polled = intel_connector->polled;
3325 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3326 connector->polled = DRM_CONNECTOR_POLL_HPD;
3327 }
3328
3329 /* Interrupt setup is already guaranteed to be single-threaded, this is
3330 * just to make the assert_spin_locked checks happy. */
3331 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3332 if (dev_priv->display.hpd_irq_setup)
3333 dev_priv->display.hpd_irq_setup(dev);
3334 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3335 }
3336
3337 /* Disable interrupts so we can allow Package C8+. */
3338 void hsw_pc8_disable_interrupts(struct drm_device *dev)
3339 {
3340 struct drm_i915_private *dev_priv = dev->dev_private;
3341 unsigned long irqflags;
3342
3343 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3344
3345 dev_priv->pc8.regsave.deimr = I915_READ(DEIMR);
3346 dev_priv->pc8.regsave.sdeimr = I915_READ(SDEIMR);
3347 dev_priv->pc8.regsave.gtimr = I915_READ(GTIMR);
3348 dev_priv->pc8.regsave.gtier = I915_READ(GTIER);
3349 dev_priv->pc8.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR);
3350
3351 ironlake_disable_display_irq(dev_priv, ~DE_PCH_EVENT_IVB);
3352 ibx_disable_display_interrupt(dev_priv, ~SDE_HOTPLUG_MASK_CPT);
3353 ilk_disable_gt_irq(dev_priv, 0xffffffff);
3354 snb_disable_pm_irq(dev_priv, 0xffffffff);
3355
3356 dev_priv->pc8.irqs_disabled = true;
3357
3358 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3359 }
3360
3361 /* Restore interrupts so we can recover from Package C8+. */
3362 void hsw_pc8_restore_interrupts(struct drm_device *dev)
3363 {
3364 struct drm_i915_private *dev_priv = dev->dev_private;
3365 unsigned long irqflags;
3366 uint32_t val, expected;
3367
3368 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3369
3370 val = I915_READ(DEIMR);
3371 expected = ~DE_PCH_EVENT_IVB;
3372 WARN(val != expected, "DEIMR is 0x%08x, not 0x%08x\n", val, expected);
3373
3374 val = I915_READ(SDEIMR) & ~SDE_HOTPLUG_MASK_CPT;
3375 expected = ~SDE_HOTPLUG_MASK_CPT;
3376 WARN(val != expected, "SDEIMR non-HPD bits are 0x%08x, not 0x%08x\n",
3377 val, expected);
3378
3379 val = I915_READ(GTIMR);
3380 expected = 0xffffffff;
3381 WARN(val != expected, "GTIMR is 0x%08x, not 0x%08x\n", val, expected);
3382
3383 val = I915_READ(GEN6_PMIMR);
3384 expected = 0xffffffff;
3385 WARN(val != expected, "GEN6_PMIMR is 0x%08x, not 0x%08x\n", val,
3386 expected);
3387
3388 dev_priv->pc8.irqs_disabled = false;
3389
3390 ironlake_enable_display_irq(dev_priv, ~dev_priv->pc8.regsave.deimr);
3391 ibx_enable_display_interrupt(dev_priv,
3392 ~dev_priv->pc8.regsave.sdeimr &
3393 ~SDE_HOTPLUG_MASK_CPT);
3394 ilk_enable_gt_irq(dev_priv, ~dev_priv->pc8.regsave.gtimr);
3395 snb_enable_pm_irq(dev_priv, ~dev_priv->pc8.regsave.gen6_pmimr);
3396 I915_WRITE(GTIER, dev_priv->pc8.regsave.gtier);
3397
3398 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3399 }
Linux kernel - Deliverables
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