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drm/fb-helper: Fix hpd vs. initial config races
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
34 #include <drm/drmP.h>
35 #include <drm/i915_drm.h>
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "intel_drv.h"
39
40 static const u32 hpd_ibx[] = {
41 [HPD_CRT] = SDE_CRT_HOTPLUG,
42 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
43 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
44 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
45 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
46 };
47
48 static const u32 hpd_cpt[] = {
49 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
50 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
51 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
52 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
53 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
54 };
55
56 static const u32 hpd_mask_i915[] = {
57 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
58 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
59 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
60 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
61 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
62 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
63 };
64
65 static const u32 hpd_status_g4x[] = {
66 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
67 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
68 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
69 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
70 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
71 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
72 };
73
74 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
75 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
76 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
77 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
78 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
79 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
80 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
81 };
82
83 /* IIR can theoretically queue up two events. Be paranoid. */
84 #define GEN8_IRQ_RESET_NDX(type, which) do { \
85 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
86 POSTING_READ(GEN8_##type##_IMR(which)); \
87 I915_WRITE(GEN8_##type##_IER(which), 0); \
88 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
89 POSTING_READ(GEN8_##type##_IIR(which)); \
90 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
91 POSTING_READ(GEN8_##type##_IIR(which)); \
92 } while (0)
93
94 #define GEN5_IRQ_RESET(type) do { \
95 I915_WRITE(type##IMR, 0xffffffff); \
96 POSTING_READ(type##IMR); \
97 I915_WRITE(type##IER, 0); \
98 I915_WRITE(type##IIR, 0xffffffff); \
99 POSTING_READ(type##IIR); \
100 I915_WRITE(type##IIR, 0xffffffff); \
101 POSTING_READ(type##IIR); \
102 } while (0)
103
104 /*
105 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
106 */
107 #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
108 u32 val = I915_READ(reg); \
109 if (val) { \
110 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
111 (reg), val); \
112 I915_WRITE((reg), 0xffffffff); \
113 POSTING_READ(reg); \
114 I915_WRITE((reg), 0xffffffff); \
115 POSTING_READ(reg); \
116 } \
117 } while (0)
118
119 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
120 GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
121 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
122 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
123 POSTING_READ(GEN8_##type##_IER(which)); \
124 } while (0)
125
126 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
127 GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
128 I915_WRITE(type##IMR, (imr_val)); \
129 I915_WRITE(type##IER, (ier_val)); \
130 POSTING_READ(type##IER); \
131 } while (0)
132
133 /* For display hotplug interrupt */
134 static void
135 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
136 {
137 assert_spin_locked(&dev_priv->irq_lock);
138
139 if (WARN_ON(dev_priv->pm.irqs_disabled))
140 return;
141
142 if ((dev_priv->irq_mask & mask) != 0) {
143 dev_priv->irq_mask &= ~mask;
144 I915_WRITE(DEIMR, dev_priv->irq_mask);
145 POSTING_READ(DEIMR);
146 }
147 }
148
149 static void
150 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
151 {
152 assert_spin_locked(&dev_priv->irq_lock);
153
154 if (WARN_ON(dev_priv->pm.irqs_disabled))
155 return;
156
157 if ((dev_priv->irq_mask & mask) != mask) {
158 dev_priv->irq_mask |= mask;
159 I915_WRITE(DEIMR, dev_priv->irq_mask);
160 POSTING_READ(DEIMR);
161 }
162 }
163
164 /**
165 * ilk_update_gt_irq - update GTIMR
166 * @dev_priv: driver private
167 * @interrupt_mask: mask of interrupt bits to update
168 * @enabled_irq_mask: mask of interrupt bits to enable
169 */
170 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
171 uint32_t interrupt_mask,
172 uint32_t enabled_irq_mask)
173 {
174 assert_spin_locked(&dev_priv->irq_lock);
175
176 if (WARN_ON(dev_priv->pm.irqs_disabled))
177 return;
178
179 dev_priv->gt_irq_mask &= ~interrupt_mask;
180 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
181 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
182 POSTING_READ(GTIMR);
183 }
184
185 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
186 {
187 ilk_update_gt_irq(dev_priv, mask, mask);
188 }
189
190 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
191 {
192 ilk_update_gt_irq(dev_priv, mask, 0);
193 }
194
195 /**
196 * snb_update_pm_irq - update GEN6_PMIMR
197 * @dev_priv: driver private
198 * @interrupt_mask: mask of interrupt bits to update
199 * @enabled_irq_mask: mask of interrupt bits to enable
200 */
201 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
202 uint32_t interrupt_mask,
203 uint32_t enabled_irq_mask)
204 {
205 uint32_t new_val;
206
207 assert_spin_locked(&dev_priv->irq_lock);
208
209 if (WARN_ON(dev_priv->pm.irqs_disabled))
210 return;
211
212 new_val = dev_priv->pm_irq_mask;
213 new_val &= ~interrupt_mask;
214 new_val |= (~enabled_irq_mask & interrupt_mask);
215
216 if (new_val != dev_priv->pm_irq_mask) {
217 dev_priv->pm_irq_mask = new_val;
218 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
219 POSTING_READ(GEN6_PMIMR);
220 }
221 }
222
223 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
224 {
225 snb_update_pm_irq(dev_priv, mask, mask);
226 }
227
228 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
229 {
230 snb_update_pm_irq(dev_priv, mask, 0);
231 }
232
233 static bool ivb_can_enable_err_int(struct drm_device *dev)
234 {
235 struct drm_i915_private *dev_priv = dev->dev_private;
236 struct intel_crtc *crtc;
237 enum pipe pipe;
238
239 assert_spin_locked(&dev_priv->irq_lock);
240
241 for_each_pipe(pipe) {
242 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
243
244 if (crtc->cpu_fifo_underrun_disabled)
245 return false;
246 }
247
248 return true;
249 }
250
251 /**
252 * bdw_update_pm_irq - update GT interrupt 2
253 * @dev_priv: driver private
254 * @interrupt_mask: mask of interrupt bits to update
255 * @enabled_irq_mask: mask of interrupt bits to enable
256 *
257 * Copied from the snb function, updated with relevant register offsets
258 */
259 static void bdw_update_pm_irq(struct drm_i915_private *dev_priv,
260 uint32_t interrupt_mask,
261 uint32_t enabled_irq_mask)
262 {
263 uint32_t new_val;
264
265 assert_spin_locked(&dev_priv->irq_lock);
266
267 if (WARN_ON(dev_priv->pm.irqs_disabled))
268 return;
269
270 new_val = dev_priv->pm_irq_mask;
271 new_val &= ~interrupt_mask;
272 new_val |= (~enabled_irq_mask & interrupt_mask);
273
274 if (new_val != dev_priv->pm_irq_mask) {
275 dev_priv->pm_irq_mask = new_val;
276 I915_WRITE(GEN8_GT_IMR(2), dev_priv->pm_irq_mask);
277 POSTING_READ(GEN8_GT_IMR(2));
278 }
279 }
280
281 void bdw_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
282 {
283 bdw_update_pm_irq(dev_priv, mask, mask);
284 }
285
286 void bdw_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
287 {
288 bdw_update_pm_irq(dev_priv, mask, 0);
289 }
290
291 static bool cpt_can_enable_serr_int(struct drm_device *dev)
292 {
293 struct drm_i915_private *dev_priv = dev->dev_private;
294 enum pipe pipe;
295 struct intel_crtc *crtc;
296
297 assert_spin_locked(&dev_priv->irq_lock);
298
299 for_each_pipe(pipe) {
300 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
301
302 if (crtc->pch_fifo_underrun_disabled)
303 return false;
304 }
305
306 return true;
307 }
308
309 void i9xx_check_fifo_underruns(struct drm_device *dev)
310 {
311 struct drm_i915_private *dev_priv = dev->dev_private;
312 struct intel_crtc *crtc;
313 unsigned long flags;
314
315 spin_lock_irqsave(&dev_priv->irq_lock, flags);
316
317 for_each_intel_crtc(dev, crtc) {
318 u32 reg = PIPESTAT(crtc->pipe);
319 u32 pipestat;
320
321 if (crtc->cpu_fifo_underrun_disabled)
322 continue;
323
324 pipestat = I915_READ(reg) & 0xffff0000;
325 if ((pipestat & PIPE_FIFO_UNDERRUN_STATUS) == 0)
326 continue;
327
328 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
329 POSTING_READ(reg);
330
331 DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe));
332 }
333
334 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
335 }
336
337 static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
338 enum pipe pipe,
339 bool enable, bool old)
340 {
341 struct drm_i915_private *dev_priv = dev->dev_private;
342 u32 reg = PIPESTAT(pipe);
343 u32 pipestat = I915_READ(reg) & 0xffff0000;
344
345 assert_spin_locked(&dev_priv->irq_lock);
346
347 if (enable) {
348 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
349 POSTING_READ(reg);
350 } else {
351 if (old && pipestat & PIPE_FIFO_UNDERRUN_STATUS)
352 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
353 }
354 }
355
356 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
357 enum pipe pipe, bool enable)
358 {
359 struct drm_i915_private *dev_priv = dev->dev_private;
360 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
361 DE_PIPEB_FIFO_UNDERRUN;
362
363 if (enable)
364 ironlake_enable_display_irq(dev_priv, bit);
365 else
366 ironlake_disable_display_irq(dev_priv, bit);
367 }
368
369 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
370 enum pipe pipe,
371 bool enable, bool old)
372 {
373 struct drm_i915_private *dev_priv = dev->dev_private;
374 if (enable) {
375 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
376
377 if (!ivb_can_enable_err_int(dev))
378 return;
379
380 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
381 } else {
382 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
383
384 if (old &&
385 I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {
386 DRM_ERROR("uncleared fifo underrun on pipe %c\n",
387 pipe_name(pipe));
388 }
389 }
390 }
391
392 static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
393 enum pipe pipe, bool enable)
394 {
395 struct drm_i915_private *dev_priv = dev->dev_private;
396
397 assert_spin_locked(&dev_priv->irq_lock);
398
399 if (enable)
400 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;
401 else
402 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
403 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
404 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
405 }
406
407 /**
408 * ibx_display_interrupt_update - update SDEIMR
409 * @dev_priv: driver private
410 * @interrupt_mask: mask of interrupt bits to update
411 * @enabled_irq_mask: mask of interrupt bits to enable
412 */
413 static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
414 uint32_t interrupt_mask,
415 uint32_t enabled_irq_mask)
416 {
417 uint32_t sdeimr = I915_READ(SDEIMR);
418 sdeimr &= ~interrupt_mask;
419 sdeimr |= (~enabled_irq_mask & interrupt_mask);
420
421 assert_spin_locked(&dev_priv->irq_lock);
422
423 if (WARN_ON(dev_priv->pm.irqs_disabled))
424 return;
425
426 I915_WRITE(SDEIMR, sdeimr);
427 POSTING_READ(SDEIMR);
428 }
429 #define ibx_enable_display_interrupt(dev_priv, bits) \
430 ibx_display_interrupt_update((dev_priv), (bits), (bits))
431 #define ibx_disable_display_interrupt(dev_priv, bits) \
432 ibx_display_interrupt_update((dev_priv), (bits), 0)
433
434 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
435 enum transcoder pch_transcoder,
436 bool enable)
437 {
438 struct drm_i915_private *dev_priv = dev->dev_private;
439 uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
440 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
441
442 if (enable)
443 ibx_enable_display_interrupt(dev_priv, bit);
444 else
445 ibx_disable_display_interrupt(dev_priv, bit);
446 }
447
448 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
449 enum transcoder pch_transcoder,
450 bool enable, bool old)
451 {
452 struct drm_i915_private *dev_priv = dev->dev_private;
453
454 if (enable) {
455 I915_WRITE(SERR_INT,
456 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
457
458 if (!cpt_can_enable_serr_int(dev))
459 return;
460
461 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
462 } else {
463 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
464
465 if (old && I915_READ(SERR_INT) &
466 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) {
467 DRM_ERROR("uncleared pch fifo underrun on pch transcoder %c\n",
468 transcoder_name(pch_transcoder));
469 }
470 }
471 }
472
473 /**
474 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
475 * @dev: drm device
476 * @pipe: pipe
477 * @enable: true if we want to report FIFO underrun errors, false otherwise
478 *
479 * This function makes us disable or enable CPU fifo underruns for a specific
480 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
481 * reporting for one pipe may also disable all the other CPU error interruts for
482 * the other pipes, due to the fact that there's just one interrupt mask/enable
483 * bit for all the pipes.
484 *
485 * Returns the previous state of underrun reporting.
486 */
487 static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
488 enum pipe pipe, bool enable)
489 {
490 struct drm_i915_private *dev_priv = dev->dev_private;
491 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
493 bool old;
494
495 assert_spin_locked(&dev_priv->irq_lock);
496
497 old = !intel_crtc->cpu_fifo_underrun_disabled;
498 intel_crtc->cpu_fifo_underrun_disabled = !enable;
499
500 if (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
501 i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
502 else if (IS_GEN5(dev) || IS_GEN6(dev))
503 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
504 else if (IS_GEN7(dev))
505 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old);
506 else if (IS_GEN8(dev))
507 broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
508
509 return old;
510 }
511
512 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
513 enum pipe pipe, bool enable)
514 {
515 struct drm_i915_private *dev_priv = dev->dev_private;
516 unsigned long flags;
517 bool ret;
518
519 spin_lock_irqsave(&dev_priv->irq_lock, flags);
520 ret = __intel_set_cpu_fifo_underrun_reporting(dev, pipe, enable);
521 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
522
523 return ret;
524 }
525
526 static bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev,
527 enum pipe pipe)
528 {
529 struct drm_i915_private *dev_priv = dev->dev_private;
530 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
531 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
532
533 return !intel_crtc->cpu_fifo_underrun_disabled;
534 }
535
536 /**
537 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
538 * @dev: drm device
539 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
540 * @enable: true if we want to report FIFO underrun errors, false otherwise
541 *
542 * This function makes us disable or enable PCH fifo underruns for a specific
543 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
544 * underrun reporting for one transcoder may also disable all the other PCH
545 * error interruts for the other transcoders, due to the fact that there's just
546 * one interrupt mask/enable bit for all the transcoders.
547 *
548 * Returns the previous state of underrun reporting.
549 */
550 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
551 enum transcoder pch_transcoder,
552 bool enable)
553 {
554 struct drm_i915_private *dev_priv = dev->dev_private;
555 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
556 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
557 unsigned long flags;
558 bool old;
559
560 /*
561 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
562 * has only one pch transcoder A that all pipes can use. To avoid racy
563 * pch transcoder -> pipe lookups from interrupt code simply store the
564 * underrun statistics in crtc A. Since we never expose this anywhere
565 * nor use it outside of the fifo underrun code here using the "wrong"
566 * crtc on LPT won't cause issues.
567 */
568
569 spin_lock_irqsave(&dev_priv->irq_lock, flags);
570
571 old = !intel_crtc->pch_fifo_underrun_disabled;
572 intel_crtc->pch_fifo_underrun_disabled = !enable;
573
574 if (HAS_PCH_IBX(dev))
575 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
576 else
577 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable, old);
578
579 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
580 return old;
581 }
582
583
584 static void
585 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
586 u32 enable_mask, u32 status_mask)
587 {
588 u32 reg = PIPESTAT(pipe);
589 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
590
591 assert_spin_locked(&dev_priv->irq_lock);
592
593 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
594 status_mask & ~PIPESTAT_INT_STATUS_MASK,
595 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
596 pipe_name(pipe), enable_mask, status_mask))
597 return;
598
599 if ((pipestat & enable_mask) == enable_mask)
600 return;
601
602 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
603
604 /* Enable the interrupt, clear any pending status */
605 pipestat |= enable_mask | status_mask;
606 I915_WRITE(reg, pipestat);
607 POSTING_READ(reg);
608 }
609
610 static void
611 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
612 u32 enable_mask, u32 status_mask)
613 {
614 u32 reg = PIPESTAT(pipe);
615 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
616
617 assert_spin_locked(&dev_priv->irq_lock);
618
619 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
620 status_mask & ~PIPESTAT_INT_STATUS_MASK,
621 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
622 pipe_name(pipe), enable_mask, status_mask))
623 return;
624
625 if ((pipestat & enable_mask) == 0)
626 return;
627
628 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
629
630 pipestat &= ~enable_mask;
631 I915_WRITE(reg, pipestat);
632 POSTING_READ(reg);
633 }
634
635 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
636 {
637 u32 enable_mask = status_mask << 16;
638
639 /*
640 * On pipe A we don't support the PSR interrupt yet,
641 * on pipe B and C the same bit MBZ.
642 */
643 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
644 return 0;
645 /*
646 * On pipe B and C we don't support the PSR interrupt yet, on pipe
647 * A the same bit is for perf counters which we don't use either.
648 */
649 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
650 return 0;
651
652 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
653 SPRITE0_FLIP_DONE_INT_EN_VLV |
654 SPRITE1_FLIP_DONE_INT_EN_VLV);
655 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
656 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
657 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
658 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
659
660 return enable_mask;
661 }
662
663 void
664 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
665 u32 status_mask)
666 {
667 u32 enable_mask;
668
669 if (IS_VALLEYVIEW(dev_priv->dev))
670 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
671 status_mask);
672 else
673 enable_mask = status_mask << 16;
674 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
675 }
676
677 void
678 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
679 u32 status_mask)
680 {
681 u32 enable_mask;
682
683 if (IS_VALLEYVIEW(dev_priv->dev))
684 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
685 status_mask);
686 else
687 enable_mask = status_mask << 16;
688 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
689 }
690
691 /**
692 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
693 */
694 static void i915_enable_asle_pipestat(struct drm_device *dev)
695 {
696 struct drm_i915_private *dev_priv = dev->dev_private;
697 unsigned long irqflags;
698
699 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
700 return;
701
702 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
703
704 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
705 if (INTEL_INFO(dev)->gen >= 4)
706 i915_enable_pipestat(dev_priv, PIPE_A,
707 PIPE_LEGACY_BLC_EVENT_STATUS);
708
709 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
710 }
711
712 /**
713 * i915_pipe_enabled - check if a pipe is enabled
714 * @dev: DRM device
715 * @pipe: pipe to check
716 *
717 * Reading certain registers when the pipe is disabled can hang the chip.
718 * Use this routine to make sure the PLL is running and the pipe is active
719 * before reading such registers if unsure.
720 */
721 static int
722 i915_pipe_enabled(struct drm_device *dev, int pipe)
723 {
724 struct drm_i915_private *dev_priv = dev->dev_private;
725
726 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
727 /* Locking is horribly broken here, but whatever. */
728 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
730
731 return intel_crtc->active;
732 } else {
733 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
734 }
735 }
736
737 /*
738 * This timing diagram depicts the video signal in and
739 * around the vertical blanking period.
740 *
741 * Assumptions about the fictitious mode used in this example:
742 * vblank_start >= 3
743 * vsync_start = vblank_start + 1
744 * vsync_end = vblank_start + 2
745 * vtotal = vblank_start + 3
746 *
747 * start of vblank:
748 * latch double buffered registers
749 * increment frame counter (ctg+)
750 * generate start of vblank interrupt (gen4+)
751 * |
752 * | frame start:
753 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
754 * | may be shifted forward 1-3 extra lines via PIPECONF
755 * | |
756 * | | start of vsync:
757 * | | generate vsync interrupt
758 * | | |
759 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
760 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
761 * ----va---> <-----------------vb--------------------> <--------va-------------
762 * | | <----vs-----> |
763 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
764 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
765 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
766 * | | |
767 * last visible pixel first visible pixel
768 * | increment frame counter (gen3/4)
769 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
770 *
771 * x = horizontal active
772 * _ = horizontal blanking
773 * hs = horizontal sync
774 * va = vertical active
775 * vb = vertical blanking
776 * vs = vertical sync
777 * vbs = vblank_start (number)
778 *
779 * Summary:
780 * - most events happen at the start of horizontal sync
781 * - frame start happens at the start of horizontal blank, 1-4 lines
782 * (depending on PIPECONF settings) after the start of vblank
783 * - gen3/4 pixel and frame counter are synchronized with the start
784 * of horizontal active on the first line of vertical active
785 */
786
787 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
788 {
789 /* Gen2 doesn't have a hardware frame counter */
790 return 0;
791 }
792
793 /* Called from drm generic code, passed a 'crtc', which
794 * we use as a pipe index
795 */
796 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
797 {
798 struct drm_i915_private *dev_priv = dev->dev_private;
799 unsigned long high_frame;
800 unsigned long low_frame;
801 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
802
803 if (!i915_pipe_enabled(dev, pipe)) {
804 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
805 "pipe %c\n", pipe_name(pipe));
806 return 0;
807 }
808
809 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
810 struct intel_crtc *intel_crtc =
811 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
812 const struct drm_display_mode *mode =
813 &intel_crtc->config.adjusted_mode;
814
815 htotal = mode->crtc_htotal;
816 hsync_start = mode->crtc_hsync_start;
817 vbl_start = mode->crtc_vblank_start;
818 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
819 vbl_start = DIV_ROUND_UP(vbl_start, 2);
820 } else {
821 enum transcoder cpu_transcoder = (enum transcoder) pipe;
822
823 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
824 hsync_start = (I915_READ(HSYNC(cpu_transcoder)) & 0x1fff) + 1;
825 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
826 if ((I915_READ(PIPECONF(cpu_transcoder)) &
827 PIPECONF_INTERLACE_MASK) != PIPECONF_PROGRESSIVE)
828 vbl_start = DIV_ROUND_UP(vbl_start, 2);
829 }
830
831 /* Convert to pixel count */
832 vbl_start *= htotal;
833
834 /* Start of vblank event occurs at start of hsync */
835 vbl_start -= htotal - hsync_start;
836
837 high_frame = PIPEFRAME(pipe);
838 low_frame = PIPEFRAMEPIXEL(pipe);
839
840 /*
841 * High & low register fields aren't synchronized, so make sure
842 * we get a low value that's stable across two reads of the high
843 * register.
844 */
845 do {
846 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
847 low = I915_READ(low_frame);
848 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
849 } while (high1 != high2);
850
851 high1 >>= PIPE_FRAME_HIGH_SHIFT;
852 pixel = low & PIPE_PIXEL_MASK;
853 low >>= PIPE_FRAME_LOW_SHIFT;
854
855 /*
856 * The frame counter increments at beginning of active.
857 * Cook up a vblank counter by also checking the pixel
858 * counter against vblank start.
859 */
860 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
861 }
862
863 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
864 {
865 struct drm_i915_private *dev_priv = dev->dev_private;
866 int reg = PIPE_FRMCOUNT_GM45(pipe);
867
868 if (!i915_pipe_enabled(dev, pipe)) {
869 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
870 "pipe %c\n", pipe_name(pipe));
871 return 0;
872 }
873
874 return I915_READ(reg);
875 }
876
877 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
878 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
879
880 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
881 {
882 struct drm_device *dev = crtc->base.dev;
883 struct drm_i915_private *dev_priv = dev->dev_private;
884 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
885 enum pipe pipe = crtc->pipe;
886 int position, vtotal;
887
888 vtotal = mode->crtc_vtotal;
889 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
890 vtotal /= 2;
891
892 if (IS_GEN2(dev))
893 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
894 else
895 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
896
897 /*
898 * See update_scanline_offset() for the details on the
899 * scanline_offset adjustment.
900 */
901 return (position + crtc->scanline_offset) % vtotal;
902 }
903
904 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
905 unsigned int flags, int *vpos, int *hpos,
906 ktime_t *stime, ktime_t *etime)
907 {
908 struct drm_i915_private *dev_priv = dev->dev_private;
909 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
910 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
911 const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
912 int position;
913 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
914 bool in_vbl = true;
915 int ret = 0;
916 unsigned long irqflags;
917
918 if (!intel_crtc->active) {
919 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
920 "pipe %c\n", pipe_name(pipe));
921 return 0;
922 }
923
924 htotal = mode->crtc_htotal;
925 hsync_start = mode->crtc_hsync_start;
926 vtotal = mode->crtc_vtotal;
927 vbl_start = mode->crtc_vblank_start;
928 vbl_end = mode->crtc_vblank_end;
929
930 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
931 vbl_start = DIV_ROUND_UP(vbl_start, 2);
932 vbl_end /= 2;
933 vtotal /= 2;
934 }
935
936 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
937
938 /*
939 * Lock uncore.lock, as we will do multiple timing critical raw
940 * register reads, potentially with preemption disabled, so the
941 * following code must not block on uncore.lock.
942 */
943 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
944
945 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
946
947 /* Get optional system timestamp before query. */
948 if (stime)
949 *stime = ktime_get();
950
951 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
952 /* No obvious pixelcount register. Only query vertical
953 * scanout position from Display scan line register.
954 */
955 position = __intel_get_crtc_scanline(intel_crtc);
956 } else {
957 /* Have access to pixelcount since start of frame.
958 * We can split this into vertical and horizontal
959 * scanout position.
960 */
961 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
962
963 /* convert to pixel counts */
964 vbl_start *= htotal;
965 vbl_end *= htotal;
966 vtotal *= htotal;
967
968 /*
969 * In interlaced modes, the pixel counter counts all pixels,
970 * so one field will have htotal more pixels. In order to avoid
971 * the reported position from jumping backwards when the pixel
972 * counter is beyond the length of the shorter field, just
973 * clamp the position the length of the shorter field. This
974 * matches how the scanline counter based position works since
975 * the scanline counter doesn't count the two half lines.
976 */
977 if (position >= vtotal)
978 position = vtotal - 1;
979
980 /*
981 * Start of vblank interrupt is triggered at start of hsync,
982 * just prior to the first active line of vblank. However we
983 * consider lines to start at the leading edge of horizontal
984 * active. So, should we get here before we've crossed into
985 * the horizontal active of the first line in vblank, we would
986 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
987 * always add htotal-hsync_start to the current pixel position.
988 */
989 position = (position + htotal - hsync_start) % vtotal;
990 }
991
992 /* Get optional system timestamp after query. */
993 if (etime)
994 *etime = ktime_get();
995
996 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
997
998 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
999
1000 in_vbl = position >= vbl_start && position < vbl_end;
1001
1002 /*
1003 * While in vblank, position will be negative
1004 * counting up towards 0 at vbl_end. And outside
1005 * vblank, position will be positive counting
1006 * up since vbl_end.
1007 */
1008 if (position >= vbl_start)
1009 position -= vbl_end;
1010 else
1011 position += vtotal - vbl_end;
1012
1013 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
1014 *vpos = position;
1015 *hpos = 0;
1016 } else {
1017 *vpos = position / htotal;
1018 *hpos = position - (*vpos * htotal);
1019 }
1020
1021 /* In vblank? */
1022 if (in_vbl)
1023 ret |= DRM_SCANOUTPOS_INVBL;
1024
1025 return ret;
1026 }
1027
1028 int intel_get_crtc_scanline(struct intel_crtc *crtc)
1029 {
1030 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1031 unsigned long irqflags;
1032 int position;
1033
1034 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1035 position = __intel_get_crtc_scanline(crtc);
1036 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1037
1038 return position;
1039 }
1040
1041 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
1042 int *max_error,
1043 struct timeval *vblank_time,
1044 unsigned flags)
1045 {
1046 struct drm_crtc *crtc;
1047
1048 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
1049 DRM_ERROR("Invalid crtc %d\n", pipe);
1050 return -EINVAL;
1051 }
1052
1053 /* Get drm_crtc to timestamp: */
1054 crtc = intel_get_crtc_for_pipe(dev, pipe);
1055 if (crtc == NULL) {
1056 DRM_ERROR("Invalid crtc %d\n", pipe);
1057 return -EINVAL;
1058 }
1059
1060 if (!crtc->enabled) {
1061 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
1062 return -EBUSY;
1063 }
1064
1065 /* Helper routine in DRM core does all the work: */
1066 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
1067 vblank_time, flags,
1068 crtc,
1069 &to_intel_crtc(crtc)->config.adjusted_mode);
1070 }
1071
1072 static bool intel_hpd_irq_event(struct drm_device *dev,
1073 struct drm_connector *connector)
1074 {
1075 enum drm_connector_status old_status;
1076
1077 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1078 old_status = connector->status;
1079
1080 connector->status = connector->funcs->detect(connector, false);
1081 if (old_status == connector->status)
1082 return false;
1083
1084 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
1085 connector->base.id,
1086 connector->name,
1087 drm_get_connector_status_name(old_status),
1088 drm_get_connector_status_name(connector->status));
1089
1090 return true;
1091 }
1092
1093 /*
1094 * Handle hotplug events outside the interrupt handler proper.
1095 */
1096 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
1097
1098 static void i915_hotplug_work_func(struct work_struct *work)
1099 {
1100 struct drm_i915_private *dev_priv =
1101 container_of(work, struct drm_i915_private, hotplug_work);
1102 struct drm_device *dev = dev_priv->dev;
1103 struct drm_mode_config *mode_config = &dev->mode_config;
1104 struct intel_connector *intel_connector;
1105 struct intel_encoder *intel_encoder;
1106 struct drm_connector *connector;
1107 unsigned long irqflags;
1108 bool hpd_disabled = false;
1109 bool changed = false;
1110 u32 hpd_event_bits;
1111
1112 mutex_lock(&mode_config->mutex);
1113 DRM_DEBUG_KMS("running encoder hotplug functions\n");
1114
1115 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1116
1117 hpd_event_bits = dev_priv->hpd_event_bits;
1118 dev_priv->hpd_event_bits = 0;
1119 list_for_each_entry(connector, &mode_config->connector_list, head) {
1120 intel_connector = to_intel_connector(connector);
1121 intel_encoder = intel_connector->encoder;
1122 if (intel_encoder->hpd_pin > HPD_NONE &&
1123 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
1124 connector->polled == DRM_CONNECTOR_POLL_HPD) {
1125 DRM_INFO("HPD interrupt storm detected on connector %s: "
1126 "switching from hotplug detection to polling\n",
1127 connector->name);
1128 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
1129 connector->polled = DRM_CONNECTOR_POLL_CONNECT
1130 | DRM_CONNECTOR_POLL_DISCONNECT;
1131 hpd_disabled = true;
1132 }
1133 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
1134 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
1135 connector->name, intel_encoder->hpd_pin);
1136 }
1137 }
1138 /* if there were no outputs to poll, poll was disabled,
1139 * therefore make sure it's enabled when disabling HPD on
1140 * some connectors */
1141 if (hpd_disabled) {
1142 drm_kms_helper_poll_enable(dev);
1143 mod_timer(&dev_priv->hotplug_reenable_timer,
1144 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
1145 }
1146
1147 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1148
1149 list_for_each_entry(connector, &mode_config->connector_list, head) {
1150 intel_connector = to_intel_connector(connector);
1151 intel_encoder = intel_connector->encoder;
1152 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
1153 if (intel_encoder->hot_plug)
1154 intel_encoder->hot_plug(intel_encoder);
1155 if (intel_hpd_irq_event(dev, connector))
1156 changed = true;
1157 }
1158 }
1159 mutex_unlock(&mode_config->mutex);
1160
1161 if (changed)
1162 drm_kms_helper_hotplug_event(dev);
1163 }
1164
1165 static void intel_hpd_irq_uninstall(struct drm_i915_private *dev_priv)
1166 {
1167 del_timer_sync(&dev_priv->hotplug_reenable_timer);
1168 }
1169
1170 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
1171 {
1172 struct drm_i915_private *dev_priv = dev->dev_private;
1173 u32 busy_up, busy_down, max_avg, min_avg;
1174 u8 new_delay;
1175
1176 spin_lock(&mchdev_lock);
1177
1178 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
1179
1180 new_delay = dev_priv->ips.cur_delay;
1181
1182 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
1183 busy_up = I915_READ(RCPREVBSYTUPAVG);
1184 busy_down = I915_READ(RCPREVBSYTDNAVG);
1185 max_avg = I915_READ(RCBMAXAVG);
1186 min_avg = I915_READ(RCBMINAVG);
1187
1188 /* Handle RCS change request from hw */
1189 if (busy_up > max_avg) {
1190 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
1191 new_delay = dev_priv->ips.cur_delay - 1;
1192 if (new_delay < dev_priv->ips.max_delay)
1193 new_delay = dev_priv->ips.max_delay;
1194 } else if (busy_down < min_avg) {
1195 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
1196 new_delay = dev_priv->ips.cur_delay + 1;
1197 if (new_delay > dev_priv->ips.min_delay)
1198 new_delay = dev_priv->ips.min_delay;
1199 }
1200
1201 if (ironlake_set_drps(dev, new_delay))
1202 dev_priv->ips.cur_delay = new_delay;
1203
1204 spin_unlock(&mchdev_lock);
1205
1206 return;
1207 }
1208
1209 static void notify_ring(struct drm_device *dev,
1210 struct intel_engine_cs *ring)
1211 {
1212 if (!intel_ring_initialized(ring))
1213 return;
1214
1215 trace_i915_gem_request_complete(ring);
1216
1217 wake_up_all(&ring->irq_queue);
1218 i915_queue_hangcheck(dev);
1219 }
1220
1221 static void gen6_pm_rps_work(struct work_struct *work)
1222 {
1223 struct drm_i915_private *dev_priv =
1224 container_of(work, struct drm_i915_private, rps.work);
1225 u32 pm_iir;
1226 int new_delay, adj;
1227
1228 spin_lock_irq(&dev_priv->irq_lock);
1229 pm_iir = dev_priv->rps.pm_iir;
1230 dev_priv->rps.pm_iir = 0;
1231 if (IS_BROADWELL(dev_priv->dev))
1232 bdw_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1233 else {
1234 /* Make sure not to corrupt PMIMR state used by ringbuffer */
1235 snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1236 }
1237 spin_unlock_irq(&dev_priv->irq_lock);
1238
1239 /* Make sure we didn't queue anything we're not going to process. */
1240 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1241
1242 if ((pm_iir & dev_priv->pm_rps_events) == 0)
1243 return;
1244
1245 mutex_lock(&dev_priv->rps.hw_lock);
1246
1247 adj = dev_priv->rps.last_adj;
1248 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1249 if (adj > 0)
1250 adj *= 2;
1251 else
1252 adj = 1;
1253 new_delay = dev_priv->rps.cur_freq + adj;
1254
1255 /*
1256 * For better performance, jump directly
1257 * to RPe if we're below it.
1258 */
1259 if (new_delay < dev_priv->rps.efficient_freq)
1260 new_delay = dev_priv->rps.efficient_freq;
1261 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1262 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1263 new_delay = dev_priv->rps.efficient_freq;
1264 else
1265 new_delay = dev_priv->rps.min_freq_softlimit;
1266 adj = 0;
1267 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1268 if (adj < 0)
1269 adj *= 2;
1270 else
1271 adj = -1;
1272 new_delay = dev_priv->rps.cur_freq + adj;
1273 } else { /* unknown event */
1274 new_delay = dev_priv->rps.cur_freq;
1275 }
1276
1277 /* sysfs frequency interfaces may have snuck in while servicing the
1278 * interrupt
1279 */
1280 new_delay = clamp_t(int, new_delay,
1281 dev_priv->rps.min_freq_softlimit,
1282 dev_priv->rps.max_freq_softlimit);
1283
1284 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq;
1285
1286 if (IS_VALLEYVIEW(dev_priv->dev))
1287 valleyview_set_rps(dev_priv->dev, new_delay);
1288 else
1289 gen6_set_rps(dev_priv->dev, new_delay);
1290
1291 mutex_unlock(&dev_priv->rps.hw_lock);
1292 }
1293
1294
1295 /**
1296 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1297 * occurred.
1298 * @work: workqueue struct
1299 *
1300 * Doesn't actually do anything except notify userspace. As a consequence of
1301 * this event, userspace should try to remap the bad rows since statistically
1302 * it is likely the same row is more likely to go bad again.
1303 */
1304 static void ivybridge_parity_work(struct work_struct *work)
1305 {
1306 struct drm_i915_private *dev_priv =
1307 container_of(work, struct drm_i915_private, l3_parity.error_work);
1308 u32 error_status, row, bank, subbank;
1309 char *parity_event[6];
1310 uint32_t misccpctl;
1311 unsigned long flags;
1312 uint8_t slice = 0;
1313
1314 /* We must turn off DOP level clock gating to access the L3 registers.
1315 * In order to prevent a get/put style interface, acquire struct mutex
1316 * any time we access those registers.
1317 */
1318 mutex_lock(&dev_priv->dev->struct_mutex);
1319
1320 /* If we've screwed up tracking, just let the interrupt fire again */
1321 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1322 goto out;
1323
1324 misccpctl = I915_READ(GEN7_MISCCPCTL);
1325 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1326 POSTING_READ(GEN7_MISCCPCTL);
1327
1328 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1329 u32 reg;
1330
1331 slice--;
1332 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1333 break;
1334
1335 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1336
1337 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1338
1339 error_status = I915_READ(reg);
1340 row = GEN7_PARITY_ERROR_ROW(error_status);
1341 bank = GEN7_PARITY_ERROR_BANK(error_status);
1342 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1343
1344 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1345 POSTING_READ(reg);
1346
1347 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1348 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1349 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1350 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1351 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1352 parity_event[5] = NULL;
1353
1354 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1355 KOBJ_CHANGE, parity_event);
1356
1357 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1358 slice, row, bank, subbank);
1359
1360 kfree(parity_event[4]);
1361 kfree(parity_event[3]);
1362 kfree(parity_event[2]);
1363 kfree(parity_event[1]);
1364 }
1365
1366 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1367
1368 out:
1369 WARN_ON(dev_priv->l3_parity.which_slice);
1370 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1371 ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1372 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1373
1374 mutex_unlock(&dev_priv->dev->struct_mutex);
1375 }
1376
1377 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1378 {
1379 struct drm_i915_private *dev_priv = dev->dev_private;
1380
1381 if (!HAS_L3_DPF(dev))
1382 return;
1383
1384 spin_lock(&dev_priv->irq_lock);
1385 ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1386 spin_unlock(&dev_priv->irq_lock);
1387
1388 iir &= GT_PARITY_ERROR(dev);
1389 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1390 dev_priv->l3_parity.which_slice |= 1 << 1;
1391
1392 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1393 dev_priv->l3_parity.which_slice |= 1 << 0;
1394
1395 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1396 }
1397
1398 static void ilk_gt_irq_handler(struct drm_device *dev,
1399 struct drm_i915_private *dev_priv,
1400 u32 gt_iir)
1401 {
1402 if (gt_iir &
1403 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1404 notify_ring(dev, &dev_priv->ring[RCS]);
1405 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1406 notify_ring(dev, &dev_priv->ring[VCS]);
1407 }
1408
1409 static void snb_gt_irq_handler(struct drm_device *dev,
1410 struct drm_i915_private *dev_priv,
1411 u32 gt_iir)
1412 {
1413
1414 if (gt_iir &
1415 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1416 notify_ring(dev, &dev_priv->ring[RCS]);
1417 if (gt_iir & GT_BSD_USER_INTERRUPT)
1418 notify_ring(dev, &dev_priv->ring[VCS]);
1419 if (gt_iir & GT_BLT_USER_INTERRUPT)
1420 notify_ring(dev, &dev_priv->ring[BCS]);
1421
1422 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1423 GT_BSD_CS_ERROR_INTERRUPT |
1424 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
1425 i915_handle_error(dev, false, "GT error interrupt 0x%08x",
1426 gt_iir);
1427 }
1428
1429 if (gt_iir & GT_PARITY_ERROR(dev))
1430 ivybridge_parity_error_irq_handler(dev, gt_iir);
1431 }
1432
1433 static void gen8_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1434 {
1435 if ((pm_iir & dev_priv->pm_rps_events) == 0)
1436 return;
1437
1438 spin_lock(&dev_priv->irq_lock);
1439 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1440 bdw_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1441 spin_unlock(&dev_priv->irq_lock);
1442
1443 queue_work(dev_priv->wq, &dev_priv->rps.work);
1444 }
1445
1446 static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1447 struct drm_i915_private *dev_priv,
1448 u32 master_ctl)
1449 {
1450 u32 rcs, bcs, vcs;
1451 uint32_t tmp = 0;
1452 irqreturn_t ret = IRQ_NONE;
1453
1454 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1455 tmp = I915_READ(GEN8_GT_IIR(0));
1456 if (tmp) {
1457 ret = IRQ_HANDLED;
1458 rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1459 bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1460 if (rcs & GT_RENDER_USER_INTERRUPT)
1461 notify_ring(dev, &dev_priv->ring[RCS]);
1462 if (bcs & GT_RENDER_USER_INTERRUPT)
1463 notify_ring(dev, &dev_priv->ring[BCS]);
1464 I915_WRITE(GEN8_GT_IIR(0), tmp);
1465 } else
1466 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1467 }
1468
1469 if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1470 tmp = I915_READ(GEN8_GT_IIR(1));
1471 if (tmp) {
1472 ret = IRQ_HANDLED;
1473 vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1474 if (vcs & GT_RENDER_USER_INTERRUPT)
1475 notify_ring(dev, &dev_priv->ring[VCS]);
1476 vcs = tmp >> GEN8_VCS2_IRQ_SHIFT;
1477 if (vcs & GT_RENDER_USER_INTERRUPT)
1478 notify_ring(dev, &dev_priv->ring[VCS2]);
1479 I915_WRITE(GEN8_GT_IIR(1), tmp);
1480 } else
1481 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1482 }
1483
1484 if (master_ctl & GEN8_GT_PM_IRQ) {
1485 tmp = I915_READ(GEN8_GT_IIR(2));
1486 if (tmp & dev_priv->pm_rps_events) {
1487 ret = IRQ_HANDLED;
1488 gen8_rps_irq_handler(dev_priv, tmp);
1489 I915_WRITE(GEN8_GT_IIR(2),
1490 tmp & dev_priv->pm_rps_events);
1491 } else
1492 DRM_ERROR("The master control interrupt lied (PM)!\n");
1493 }
1494
1495 if (master_ctl & GEN8_GT_VECS_IRQ) {
1496 tmp = I915_READ(GEN8_GT_IIR(3));
1497 if (tmp) {
1498 ret = IRQ_HANDLED;
1499 vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1500 if (vcs & GT_RENDER_USER_INTERRUPT)
1501 notify_ring(dev, &dev_priv->ring[VECS]);
1502 I915_WRITE(GEN8_GT_IIR(3), tmp);
1503 } else
1504 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1505 }
1506
1507 return ret;
1508 }
1509
1510 #define HPD_STORM_DETECT_PERIOD 1000
1511 #define HPD_STORM_THRESHOLD 5
1512
1513 static inline void intel_hpd_irq_handler(struct drm_device *dev,
1514 u32 hotplug_trigger,
1515 const u32 *hpd)
1516 {
1517 struct drm_i915_private *dev_priv = dev->dev_private;
1518 int i;
1519 bool storm_detected = false;
1520
1521 if (!hotplug_trigger)
1522 return;
1523
1524 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1525 hotplug_trigger);
1526
1527 spin_lock(&dev_priv->irq_lock);
1528 for (i = 1; i < HPD_NUM_PINS; i++) {
1529
1530 if (hpd[i] & hotplug_trigger &&
1531 dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) {
1532 /*
1533 * On GMCH platforms the interrupt mask bits only
1534 * prevent irq generation, not the setting of the
1535 * hotplug bits itself. So only WARN about unexpected
1536 * interrupts on saner platforms.
1537 */
1538 WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
1539 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1540 hotplug_trigger, i, hpd[i]);
1541
1542 continue;
1543 }
1544
1545 if (!(hpd[i] & hotplug_trigger) ||
1546 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1547 continue;
1548
1549 dev_priv->hpd_event_bits |= (1 << i);
1550 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1551 dev_priv->hpd_stats[i].hpd_last_jiffies
1552 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1553 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1554 dev_priv->hpd_stats[i].hpd_cnt = 0;
1555 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1556 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1557 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1558 dev_priv->hpd_event_bits &= ~(1 << i);
1559 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1560 storm_detected = true;
1561 } else {
1562 dev_priv->hpd_stats[i].hpd_cnt++;
1563 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1564 dev_priv->hpd_stats[i].hpd_cnt);
1565 }
1566 }
1567
1568 if (storm_detected)
1569 dev_priv->display.hpd_irq_setup(dev);
1570 spin_unlock(&dev_priv->irq_lock);
1571
1572 /*
1573 * Our hotplug handler can grab modeset locks (by calling down into the
1574 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1575 * queue for otherwise the flush_work in the pageflip code will
1576 * deadlock.
1577 */
1578 schedule_work(&dev_priv->hotplug_work);
1579 }
1580
1581 static void gmbus_irq_handler(struct drm_device *dev)
1582 {
1583 struct drm_i915_private *dev_priv = dev->dev_private;
1584
1585 wake_up_all(&dev_priv->gmbus_wait_queue);
1586 }
1587
1588 static void dp_aux_irq_handler(struct drm_device *dev)
1589 {
1590 struct drm_i915_private *dev_priv = dev->dev_private;
1591
1592 wake_up_all(&dev_priv->gmbus_wait_queue);
1593 }
1594
1595 #if defined(CONFIG_DEBUG_FS)
1596 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1597 uint32_t crc0, uint32_t crc1,
1598 uint32_t crc2, uint32_t crc3,
1599 uint32_t crc4)
1600 {
1601 struct drm_i915_private *dev_priv = dev->dev_private;
1602 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1603 struct intel_pipe_crc_entry *entry;
1604 int head, tail;
1605
1606 spin_lock(&pipe_crc->lock);
1607
1608 if (!pipe_crc->entries) {
1609 spin_unlock(&pipe_crc->lock);
1610 DRM_ERROR("spurious interrupt\n");
1611 return;
1612 }
1613
1614 head = pipe_crc->head;
1615 tail = pipe_crc->tail;
1616
1617 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1618 spin_unlock(&pipe_crc->lock);
1619 DRM_ERROR("CRC buffer overflowing\n");
1620 return;
1621 }
1622
1623 entry = &pipe_crc->entries[head];
1624
1625 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1626 entry->crc[0] = crc0;
1627 entry->crc[1] = crc1;
1628 entry->crc[2] = crc2;
1629 entry->crc[3] = crc3;
1630 entry->crc[4] = crc4;
1631
1632 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1633 pipe_crc->head = head;
1634
1635 spin_unlock(&pipe_crc->lock);
1636
1637 wake_up_interruptible(&pipe_crc->wq);
1638 }
1639 #else
1640 static inline void
1641 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1642 uint32_t crc0, uint32_t crc1,
1643 uint32_t crc2, uint32_t crc3,
1644 uint32_t crc4) {}
1645 #endif
1646
1647
1648 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1649 {
1650 struct drm_i915_private *dev_priv = dev->dev_private;
1651
1652 display_pipe_crc_irq_handler(dev, pipe,
1653 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1654 0, 0, 0, 0);
1655 }
1656
1657 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1658 {
1659 struct drm_i915_private *dev_priv = dev->dev_private;
1660
1661 display_pipe_crc_irq_handler(dev, pipe,
1662 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1663 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1664 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1665 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1666 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1667 }
1668
1669 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1670 {
1671 struct drm_i915_private *dev_priv = dev->dev_private;
1672 uint32_t res1, res2;
1673
1674 if (INTEL_INFO(dev)->gen >= 3)
1675 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1676 else
1677 res1 = 0;
1678
1679 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1680 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1681 else
1682 res2 = 0;
1683
1684 display_pipe_crc_irq_handler(dev, pipe,
1685 I915_READ(PIPE_CRC_RES_RED(pipe)),
1686 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1687 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1688 res1, res2);
1689 }
1690
1691 /* The RPS events need forcewake, so we add them to a work queue and mask their
1692 * IMR bits until the work is done. Other interrupts can be processed without
1693 * the work queue. */
1694 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1695 {
1696 if (pm_iir & dev_priv->pm_rps_events) {
1697 spin_lock(&dev_priv->irq_lock);
1698 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1699 snb_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1700 spin_unlock(&dev_priv->irq_lock);
1701
1702 queue_work(dev_priv->wq, &dev_priv->rps.work);
1703 }
1704
1705 if (HAS_VEBOX(dev_priv->dev)) {
1706 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1707 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1708
1709 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1710 i915_handle_error(dev_priv->dev, false,
1711 "VEBOX CS error interrupt 0x%08x",
1712 pm_iir);
1713 }
1714 }
1715 }
1716
1717 static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
1718 {
1719 struct intel_crtc *crtc;
1720
1721 if (!drm_handle_vblank(dev, pipe))
1722 return false;
1723
1724 crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
1725 wake_up(&crtc->vbl_wait);
1726
1727 return true;
1728 }
1729
1730 static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1731 {
1732 struct drm_i915_private *dev_priv = dev->dev_private;
1733 u32 pipe_stats[I915_MAX_PIPES] = { };
1734 int pipe;
1735
1736 spin_lock(&dev_priv->irq_lock);
1737 for_each_pipe(pipe) {
1738 int reg;
1739 u32 mask, iir_bit = 0;
1740
1741 /*
1742 * PIPESTAT bits get signalled even when the interrupt is
1743 * disabled with the mask bits, and some of the status bits do
1744 * not generate interrupts at all (like the underrun bit). Hence
1745 * we need to be careful that we only handle what we want to
1746 * handle.
1747 */
1748 mask = 0;
1749 if (__cpu_fifo_underrun_reporting_enabled(dev, pipe))
1750 mask |= PIPE_FIFO_UNDERRUN_STATUS;
1751
1752 switch (pipe) {
1753 case PIPE_A:
1754 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1755 break;
1756 case PIPE_B:
1757 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1758 break;
1759 case PIPE_C:
1760 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1761 break;
1762 }
1763 if (iir & iir_bit)
1764 mask |= dev_priv->pipestat_irq_mask[pipe];
1765
1766 if (!mask)
1767 continue;
1768
1769 reg = PIPESTAT(pipe);
1770 mask |= PIPESTAT_INT_ENABLE_MASK;
1771 pipe_stats[pipe] = I915_READ(reg) & mask;
1772
1773 /*
1774 * Clear the PIPE*STAT regs before the IIR
1775 */
1776 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1777 PIPESTAT_INT_STATUS_MASK))
1778 I915_WRITE(reg, pipe_stats[pipe]);
1779 }
1780 spin_unlock(&dev_priv->irq_lock);
1781
1782 for_each_pipe(pipe) {
1783 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1784 intel_pipe_handle_vblank(dev, pipe);
1785
1786 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
1787 intel_prepare_page_flip(dev, pipe);
1788 intel_finish_page_flip(dev, pipe);
1789 }
1790
1791 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1792 i9xx_pipe_crc_irq_handler(dev, pipe);
1793
1794 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
1795 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1796 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
1797 }
1798
1799 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1800 gmbus_irq_handler(dev);
1801 }
1802
1803 static void i9xx_hpd_irq_handler(struct drm_device *dev)
1804 {
1805 struct drm_i915_private *dev_priv = dev->dev_private;
1806 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1807
1808 if (IS_G4X(dev)) {
1809 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1810
1811 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_g4x);
1812 } else {
1813 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1814
1815 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1816 }
1817
1818 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) &&
1819 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1820 dp_aux_irq_handler(dev);
1821
1822 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1823 /*
1824 * Make sure hotplug status is cleared before we clear IIR, or else we
1825 * may miss hotplug events.
1826 */
1827 POSTING_READ(PORT_HOTPLUG_STAT);
1828 }
1829
1830 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1831 {
1832 struct drm_device *dev = arg;
1833 struct drm_i915_private *dev_priv = dev->dev_private;
1834 u32 iir, gt_iir, pm_iir;
1835 irqreturn_t ret = IRQ_NONE;
1836
1837 while (true) {
1838 iir = I915_READ(VLV_IIR);
1839 gt_iir = I915_READ(GTIIR);
1840 pm_iir = I915_READ(GEN6_PMIIR);
1841
1842 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1843 goto out;
1844
1845 ret = IRQ_HANDLED;
1846
1847 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1848
1849 valleyview_pipestat_irq_handler(dev, iir);
1850
1851 /* Consume port. Then clear IIR or we'll miss events */
1852 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1853 i9xx_hpd_irq_handler(dev);
1854
1855 if (pm_iir)
1856 gen6_rps_irq_handler(dev_priv, pm_iir);
1857
1858 I915_WRITE(GTIIR, gt_iir);
1859 I915_WRITE(GEN6_PMIIR, pm_iir);
1860 I915_WRITE(VLV_IIR, iir);
1861 }
1862
1863 out:
1864 return ret;
1865 }
1866
1867 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1868 {
1869 struct drm_device *dev = arg;
1870 struct drm_i915_private *dev_priv = dev->dev_private;
1871 u32 master_ctl, iir;
1872 irqreturn_t ret = IRQ_NONE;
1873
1874 for (;;) {
1875 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1876 iir = I915_READ(VLV_IIR);
1877
1878 if (master_ctl == 0 && iir == 0)
1879 break;
1880
1881 I915_WRITE(GEN8_MASTER_IRQ, 0);
1882
1883 gen8_gt_irq_handler(dev, dev_priv, master_ctl);
1884
1885 valleyview_pipestat_irq_handler(dev, iir);
1886
1887 /* Consume port. Then clear IIR or we'll miss events */
1888 i9xx_hpd_irq_handler(dev);
1889
1890 I915_WRITE(VLV_IIR, iir);
1891
1892 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
1893 POSTING_READ(GEN8_MASTER_IRQ);
1894
1895 ret = IRQ_HANDLED;
1896 }
1897
1898 return ret;
1899 }
1900
1901 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1902 {
1903 struct drm_i915_private *dev_priv = dev->dev_private;
1904 int pipe;
1905 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1906
1907 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1908
1909 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1910 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1911 SDE_AUDIO_POWER_SHIFT);
1912 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1913 port_name(port));
1914 }
1915
1916 if (pch_iir & SDE_AUX_MASK)
1917 dp_aux_irq_handler(dev);
1918
1919 if (pch_iir & SDE_GMBUS)
1920 gmbus_irq_handler(dev);
1921
1922 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1923 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1924
1925 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1926 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1927
1928 if (pch_iir & SDE_POISON)
1929 DRM_ERROR("PCH poison interrupt\n");
1930
1931 if (pch_iir & SDE_FDI_MASK)
1932 for_each_pipe(pipe)
1933 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1934 pipe_name(pipe),
1935 I915_READ(FDI_RX_IIR(pipe)));
1936
1937 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1938 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1939
1940 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1941 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1942
1943 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1944 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1945 false))
1946 DRM_ERROR("PCH transcoder A FIFO underrun\n");
1947
1948 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1949 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1950 false))
1951 DRM_ERROR("PCH transcoder B FIFO underrun\n");
1952 }
1953
1954 static void ivb_err_int_handler(struct drm_device *dev)
1955 {
1956 struct drm_i915_private *dev_priv = dev->dev_private;
1957 u32 err_int = I915_READ(GEN7_ERR_INT);
1958 enum pipe pipe;
1959
1960 if (err_int & ERR_INT_POISON)
1961 DRM_ERROR("Poison interrupt\n");
1962
1963 for_each_pipe(pipe) {
1964 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
1965 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1966 false))
1967 DRM_ERROR("Pipe %c FIFO underrun\n",
1968 pipe_name(pipe));
1969 }
1970
1971 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1972 if (IS_IVYBRIDGE(dev))
1973 ivb_pipe_crc_irq_handler(dev, pipe);
1974 else
1975 hsw_pipe_crc_irq_handler(dev, pipe);
1976 }
1977 }
1978
1979 I915_WRITE(GEN7_ERR_INT, err_int);
1980 }
1981
1982 static void cpt_serr_int_handler(struct drm_device *dev)
1983 {
1984 struct drm_i915_private *dev_priv = dev->dev_private;
1985 u32 serr_int = I915_READ(SERR_INT);
1986
1987 if (serr_int & SERR_INT_POISON)
1988 DRM_ERROR("PCH poison interrupt\n");
1989
1990 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1991 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1992 false))
1993 DRM_ERROR("PCH transcoder A FIFO underrun\n");
1994
1995 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1996 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1997 false))
1998 DRM_ERROR("PCH transcoder B FIFO underrun\n");
1999
2000 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2001 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
2002 false))
2003 DRM_ERROR("PCH transcoder C FIFO underrun\n");
2004
2005 I915_WRITE(SERR_INT, serr_int);
2006 }
2007
2008 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
2009 {
2010 struct drm_i915_private *dev_priv = dev->dev_private;
2011 int pipe;
2012 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2013
2014 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
2015
2016 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2017 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2018 SDE_AUDIO_POWER_SHIFT_CPT);
2019 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2020 port_name(port));
2021 }
2022
2023 if (pch_iir & SDE_AUX_MASK_CPT)
2024 dp_aux_irq_handler(dev);
2025
2026 if (pch_iir & SDE_GMBUS_CPT)
2027 gmbus_irq_handler(dev);
2028
2029 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2030 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2031
2032 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2033 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2034
2035 if (pch_iir & SDE_FDI_MASK_CPT)
2036 for_each_pipe(pipe)
2037 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2038 pipe_name(pipe),
2039 I915_READ(FDI_RX_IIR(pipe)));
2040
2041 if (pch_iir & SDE_ERROR_CPT)
2042 cpt_serr_int_handler(dev);
2043 }
2044
2045 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
2046 {
2047 struct drm_i915_private *dev_priv = dev->dev_private;
2048 enum pipe pipe;
2049
2050 if (de_iir & DE_AUX_CHANNEL_A)
2051 dp_aux_irq_handler(dev);
2052
2053 if (de_iir & DE_GSE)
2054 intel_opregion_asle_intr(dev);
2055
2056 if (de_iir & DE_POISON)
2057 DRM_ERROR("Poison interrupt\n");
2058
2059 for_each_pipe(pipe) {
2060 if (de_iir & DE_PIPE_VBLANK(pipe))
2061 intel_pipe_handle_vblank(dev, pipe);
2062
2063 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2064 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
2065 DRM_ERROR("Pipe %c FIFO underrun\n",
2066 pipe_name(pipe));
2067
2068 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2069 i9xx_pipe_crc_irq_handler(dev, pipe);
2070
2071 /* plane/pipes map 1:1 on ilk+ */
2072 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
2073 intel_prepare_page_flip(dev, pipe);
2074 intel_finish_page_flip_plane(dev, pipe);
2075 }
2076 }
2077
2078 /* check event from PCH */
2079 if (de_iir & DE_PCH_EVENT) {
2080 u32 pch_iir = I915_READ(SDEIIR);
2081
2082 if (HAS_PCH_CPT(dev))
2083 cpt_irq_handler(dev, pch_iir);
2084 else
2085 ibx_irq_handler(dev, pch_iir);
2086
2087 /* should clear PCH hotplug event before clear CPU irq */
2088 I915_WRITE(SDEIIR, pch_iir);
2089 }
2090
2091 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
2092 ironlake_rps_change_irq_handler(dev);
2093 }
2094
2095 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
2096 {
2097 struct drm_i915_private *dev_priv = dev->dev_private;
2098 enum pipe pipe;
2099
2100 if (de_iir & DE_ERR_INT_IVB)
2101 ivb_err_int_handler(dev);
2102
2103 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2104 dp_aux_irq_handler(dev);
2105
2106 if (de_iir & DE_GSE_IVB)
2107 intel_opregion_asle_intr(dev);
2108
2109 for_each_pipe(pipe) {
2110 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
2111 intel_pipe_handle_vblank(dev, pipe);
2112
2113 /* plane/pipes map 1:1 on ilk+ */
2114 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
2115 intel_prepare_page_flip(dev, pipe);
2116 intel_finish_page_flip_plane(dev, pipe);
2117 }
2118 }
2119
2120 /* check event from PCH */
2121 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
2122 u32 pch_iir = I915_READ(SDEIIR);
2123
2124 cpt_irq_handler(dev, pch_iir);
2125
2126 /* clear PCH hotplug event before clear CPU irq */
2127 I915_WRITE(SDEIIR, pch_iir);
2128 }
2129 }
2130
2131 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2132 {
2133 struct drm_device *dev = arg;
2134 struct drm_i915_private *dev_priv = dev->dev_private;
2135 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2136 irqreturn_t ret = IRQ_NONE;
2137
2138 /* We get interrupts on unclaimed registers, so check for this before we
2139 * do any I915_{READ,WRITE}. */
2140 intel_uncore_check_errors(dev);
2141
2142 /* disable master interrupt before clearing iir */
2143 de_ier = I915_READ(DEIER);
2144 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2145 POSTING_READ(DEIER);
2146
2147 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2148 * interrupts will will be stored on its back queue, and then we'll be
2149 * able to process them after we restore SDEIER (as soon as we restore
2150 * it, we'll get an interrupt if SDEIIR still has something to process
2151 * due to its back queue). */
2152 if (!HAS_PCH_NOP(dev)) {
2153 sde_ier = I915_READ(SDEIER);
2154 I915_WRITE(SDEIER, 0);
2155 POSTING_READ(SDEIER);
2156 }
2157
2158 gt_iir = I915_READ(GTIIR);
2159 if (gt_iir) {
2160 if (INTEL_INFO(dev)->gen >= 6)
2161 snb_gt_irq_handler(dev, dev_priv, gt_iir);
2162 else
2163 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
2164 I915_WRITE(GTIIR, gt_iir);
2165 ret = IRQ_HANDLED;
2166 }
2167
2168 de_iir = I915_READ(DEIIR);
2169 if (de_iir) {
2170 if (INTEL_INFO(dev)->gen >= 7)
2171 ivb_display_irq_handler(dev, de_iir);
2172 else
2173 ilk_display_irq_handler(dev, de_iir);
2174 I915_WRITE(DEIIR, de_iir);
2175 ret = IRQ_HANDLED;
2176 }
2177
2178 if (INTEL_INFO(dev)->gen >= 6) {
2179 u32 pm_iir = I915_READ(GEN6_PMIIR);
2180 if (pm_iir) {
2181 gen6_rps_irq_handler(dev_priv, pm_iir);
2182 I915_WRITE(GEN6_PMIIR, pm_iir);
2183 ret = IRQ_HANDLED;
2184 }
2185 }
2186
2187 I915_WRITE(DEIER, de_ier);
2188 POSTING_READ(DEIER);
2189 if (!HAS_PCH_NOP(dev)) {
2190 I915_WRITE(SDEIER, sde_ier);
2191 POSTING_READ(SDEIER);
2192 }
2193
2194 return ret;
2195 }
2196
2197 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2198 {
2199 struct drm_device *dev = arg;
2200 struct drm_i915_private *dev_priv = dev->dev_private;
2201 u32 master_ctl;
2202 irqreturn_t ret = IRQ_NONE;
2203 uint32_t tmp = 0;
2204 enum pipe pipe;
2205
2206 master_ctl = I915_READ(GEN8_MASTER_IRQ);
2207 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2208 if (!master_ctl)
2209 return IRQ_NONE;
2210
2211 I915_WRITE(GEN8_MASTER_IRQ, 0);
2212 POSTING_READ(GEN8_MASTER_IRQ);
2213
2214 ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
2215
2216 if (master_ctl & GEN8_DE_MISC_IRQ) {
2217 tmp = I915_READ(GEN8_DE_MISC_IIR);
2218 if (tmp & GEN8_DE_MISC_GSE)
2219 intel_opregion_asle_intr(dev);
2220 else if (tmp)
2221 DRM_ERROR("Unexpected DE Misc interrupt\n");
2222 else
2223 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2224
2225 if (tmp) {
2226 I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2227 ret = IRQ_HANDLED;
2228 }
2229 }
2230
2231 if (master_ctl & GEN8_DE_PORT_IRQ) {
2232 tmp = I915_READ(GEN8_DE_PORT_IIR);
2233 if (tmp & GEN8_AUX_CHANNEL_A)
2234 dp_aux_irq_handler(dev);
2235 else if (tmp)
2236 DRM_ERROR("Unexpected DE Port interrupt\n");
2237 else
2238 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2239
2240 if (tmp) {
2241 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2242 ret = IRQ_HANDLED;
2243 }
2244 }
2245
2246 for_each_pipe(pipe) {
2247 uint32_t pipe_iir;
2248
2249 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2250 continue;
2251
2252 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2253 if (pipe_iir & GEN8_PIPE_VBLANK)
2254 intel_pipe_handle_vblank(dev, pipe);
2255
2256 if (pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE) {
2257 intel_prepare_page_flip(dev, pipe);
2258 intel_finish_page_flip_plane(dev, pipe);
2259 }
2260
2261 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2262 hsw_pipe_crc_irq_handler(dev, pipe);
2263
2264 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
2265 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
2266 false))
2267 DRM_ERROR("Pipe %c FIFO underrun\n",
2268 pipe_name(pipe));
2269 }
2270
2271 if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
2272 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2273 pipe_name(pipe),
2274 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2275 }
2276
2277 if (pipe_iir) {
2278 ret = IRQ_HANDLED;
2279 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2280 } else
2281 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2282 }
2283
2284 if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
2285 /*
2286 * FIXME(BDW): Assume for now that the new interrupt handling
2287 * scheme also closed the SDE interrupt handling race we've seen
2288 * on older pch-split platforms. But this needs testing.
2289 */
2290 u32 pch_iir = I915_READ(SDEIIR);
2291
2292 cpt_irq_handler(dev, pch_iir);
2293
2294 if (pch_iir) {
2295 I915_WRITE(SDEIIR, pch_iir);
2296 ret = IRQ_HANDLED;
2297 }
2298 }
2299
2300 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2301 POSTING_READ(GEN8_MASTER_IRQ);
2302
2303 return ret;
2304 }
2305
2306 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2307 bool reset_completed)
2308 {
2309 struct intel_engine_cs *ring;
2310 int i;
2311
2312 /*
2313 * Notify all waiters for GPU completion events that reset state has
2314 * been changed, and that they need to restart their wait after
2315 * checking for potential errors (and bail out to drop locks if there is
2316 * a gpu reset pending so that i915_error_work_func can acquire them).
2317 */
2318
2319 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2320 for_each_ring(ring, dev_priv, i)
2321 wake_up_all(&ring->irq_queue);
2322
2323 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2324 wake_up_all(&dev_priv->pending_flip_queue);
2325
2326 /*
2327 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2328 * reset state is cleared.
2329 */
2330 if (reset_completed)
2331 wake_up_all(&dev_priv->gpu_error.reset_queue);
2332 }
2333
2334 /**
2335 * i915_error_work_func - do process context error handling work
2336 * @work: work struct
2337 *
2338 * Fire an error uevent so userspace can see that a hang or error
2339 * was detected.
2340 */
2341 static void i915_error_work_func(struct work_struct *work)
2342 {
2343 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
2344 work);
2345 struct drm_i915_private *dev_priv =
2346 container_of(error, struct drm_i915_private, gpu_error);
2347 struct drm_device *dev = dev_priv->dev;
2348 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2349 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2350 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2351 int ret;
2352
2353 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2354
2355 /*
2356 * Note that there's only one work item which does gpu resets, so we
2357 * need not worry about concurrent gpu resets potentially incrementing
2358 * error->reset_counter twice. We only need to take care of another
2359 * racing irq/hangcheck declaring the gpu dead for a second time. A
2360 * quick check for that is good enough: schedule_work ensures the
2361 * correct ordering between hang detection and this work item, and since
2362 * the reset in-progress bit is only ever set by code outside of this
2363 * work we don't need to worry about any other races.
2364 */
2365 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2366 DRM_DEBUG_DRIVER("resetting chip\n");
2367 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2368 reset_event);
2369
2370 /*
2371 * In most cases it's guaranteed that we get here with an RPM
2372 * reference held, for example because there is a pending GPU
2373 * request that won't finish until the reset is done. This
2374 * isn't the case at least when we get here by doing a
2375 * simulated reset via debugs, so get an RPM reference.
2376 */
2377 intel_runtime_pm_get(dev_priv);
2378 /*
2379 * All state reset _must_ be completed before we update the
2380 * reset counter, for otherwise waiters might miss the reset
2381 * pending state and not properly drop locks, resulting in
2382 * deadlocks with the reset work.
2383 */
2384 ret = i915_reset(dev);
2385
2386 intel_display_handle_reset(dev);
2387
2388 intel_runtime_pm_put(dev_priv);
2389
2390 if (ret == 0) {
2391 /*
2392 * After all the gem state is reset, increment the reset
2393 * counter and wake up everyone waiting for the reset to
2394 * complete.
2395 *
2396 * Since unlock operations are a one-sided barrier only,
2397 * we need to insert a barrier here to order any seqno
2398 * updates before
2399 * the counter increment.
2400 */
2401 smp_mb__before_atomic();
2402 atomic_inc(&dev_priv->gpu_error.reset_counter);
2403
2404 kobject_uevent_env(&dev->primary->kdev->kobj,
2405 KOBJ_CHANGE, reset_done_event);
2406 } else {
2407 atomic_set_mask(I915_WEDGED, &error->reset_counter);
2408 }
2409
2410 /*
2411 * Note: The wake_up also serves as a memory barrier so that
2412 * waiters see the update value of the reset counter atomic_t.
2413 */
2414 i915_error_wake_up(dev_priv, true);
2415 }
2416 }
2417
2418 static void i915_report_and_clear_eir(struct drm_device *dev)
2419 {
2420 struct drm_i915_private *dev_priv = dev->dev_private;
2421 uint32_t instdone[I915_NUM_INSTDONE_REG];
2422 u32 eir = I915_READ(EIR);
2423 int pipe, i;
2424
2425 if (!eir)
2426 return;
2427
2428 pr_err("render error detected, EIR: 0x%08x\n", eir);
2429
2430 i915_get_extra_instdone(dev, instdone);
2431
2432 if (IS_G4X(dev)) {
2433 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2434 u32 ipeir = I915_READ(IPEIR_I965);
2435
2436 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2437 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2438 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2439 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2440 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2441 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2442 I915_WRITE(IPEIR_I965, ipeir);
2443 POSTING_READ(IPEIR_I965);
2444 }
2445 if (eir & GM45_ERROR_PAGE_TABLE) {
2446 u32 pgtbl_err = I915_READ(PGTBL_ER);
2447 pr_err("page table error\n");
2448 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2449 I915_WRITE(PGTBL_ER, pgtbl_err);
2450 POSTING_READ(PGTBL_ER);
2451 }
2452 }
2453
2454 if (!IS_GEN2(dev)) {
2455 if (eir & I915_ERROR_PAGE_TABLE) {
2456 u32 pgtbl_err = I915_READ(PGTBL_ER);
2457 pr_err("page table error\n");
2458 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2459 I915_WRITE(PGTBL_ER, pgtbl_err);
2460 POSTING_READ(PGTBL_ER);
2461 }
2462 }
2463
2464 if (eir & I915_ERROR_MEMORY_REFRESH) {
2465 pr_err("memory refresh error:\n");
2466 for_each_pipe(pipe)
2467 pr_err("pipe %c stat: 0x%08x\n",
2468 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2469 /* pipestat has already been acked */
2470 }
2471 if (eir & I915_ERROR_INSTRUCTION) {
2472 pr_err("instruction error\n");
2473 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
2474 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2475 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2476 if (INTEL_INFO(dev)->gen < 4) {
2477 u32 ipeir = I915_READ(IPEIR);
2478
2479 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2480 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
2481 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
2482 I915_WRITE(IPEIR, ipeir);
2483 POSTING_READ(IPEIR);
2484 } else {
2485 u32 ipeir = I915_READ(IPEIR_I965);
2486
2487 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2488 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2489 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2490 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2491 I915_WRITE(IPEIR_I965, ipeir);
2492 POSTING_READ(IPEIR_I965);
2493 }
2494 }
2495
2496 I915_WRITE(EIR, eir);
2497 POSTING_READ(EIR);
2498 eir = I915_READ(EIR);
2499 if (eir) {
2500 /*
2501 * some errors might have become stuck,
2502 * mask them.
2503 */
2504 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2505 I915_WRITE(EMR, I915_READ(EMR) | eir);
2506 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2507 }
2508 }
2509
2510 /**
2511 * i915_handle_error - handle an error interrupt
2512 * @dev: drm device
2513 *
2514 * Do some basic checking of regsiter state at error interrupt time and
2515 * dump it to the syslog. Also call i915_capture_error_state() to make
2516 * sure we get a record and make it available in debugfs. Fire a uevent
2517 * so userspace knows something bad happened (should trigger collection
2518 * of a ring dump etc.).
2519 */
2520 void i915_handle_error(struct drm_device *dev, bool wedged,
2521 const char *fmt, ...)
2522 {
2523 struct drm_i915_private *dev_priv = dev->dev_private;
2524 va_list args;
2525 char error_msg[80];
2526
2527 va_start(args, fmt);
2528 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2529 va_end(args);
2530
2531 i915_capture_error_state(dev, wedged, error_msg);
2532 i915_report_and_clear_eir(dev);
2533
2534 if (wedged) {
2535 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2536 &dev_priv->gpu_error.reset_counter);
2537
2538 /*
2539 * Wakeup waiting processes so that the reset work function
2540 * i915_error_work_func doesn't deadlock trying to grab various
2541 * locks. By bumping the reset counter first, the woken
2542 * processes will see a reset in progress and back off,
2543 * releasing their locks and then wait for the reset completion.
2544 * We must do this for _all_ gpu waiters that might hold locks
2545 * that the reset work needs to acquire.
2546 *
2547 * Note: The wake_up serves as the required memory barrier to
2548 * ensure that the waiters see the updated value of the reset
2549 * counter atomic_t.
2550 */
2551 i915_error_wake_up(dev_priv, false);
2552 }
2553
2554 /*
2555 * Our reset work can grab modeset locks (since it needs to reset the
2556 * state of outstanding pagelips). Hence it must not be run on our own
2557 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2558 * code will deadlock.
2559 */
2560 schedule_work(&dev_priv->gpu_error.work);
2561 }
2562
2563 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
2564 {
2565 struct drm_i915_private *dev_priv = dev->dev_private;
2566 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2567 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2568 struct drm_i915_gem_object *obj;
2569 struct intel_unpin_work *work;
2570 unsigned long flags;
2571 bool stall_detected;
2572
2573 /* Ignore early vblank irqs */
2574 if (intel_crtc == NULL)
2575 return;
2576
2577 spin_lock_irqsave(&dev->event_lock, flags);
2578 work = intel_crtc->unpin_work;
2579
2580 if (work == NULL ||
2581 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2582 !work->enable_stall_check) {
2583 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2584 spin_unlock_irqrestore(&dev->event_lock, flags);
2585 return;
2586 }
2587
2588 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2589 obj = work->pending_flip_obj;
2590 if (INTEL_INFO(dev)->gen >= 4) {
2591 int dspsurf = DSPSURF(intel_crtc->plane);
2592 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
2593 i915_gem_obj_ggtt_offset(obj);
2594 } else {
2595 int dspaddr = DSPADDR(intel_crtc->plane);
2596 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
2597 crtc->y * crtc->primary->fb->pitches[0] +
2598 crtc->x * crtc->primary->fb->bits_per_pixel/8);
2599 }
2600
2601 spin_unlock_irqrestore(&dev->event_lock, flags);
2602
2603 if (stall_detected) {
2604 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2605 intel_prepare_page_flip(dev, intel_crtc->plane);
2606 }
2607 }
2608
2609 /* Called from drm generic code, passed 'crtc' which
2610 * we use as a pipe index
2611 */
2612 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2613 {
2614 struct drm_i915_private *dev_priv = dev->dev_private;
2615 unsigned long irqflags;
2616
2617 if (!i915_pipe_enabled(dev, pipe))
2618 return -EINVAL;
2619
2620 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2621 if (INTEL_INFO(dev)->gen >= 4)
2622 i915_enable_pipestat(dev_priv, pipe,
2623 PIPE_START_VBLANK_INTERRUPT_STATUS);
2624 else
2625 i915_enable_pipestat(dev_priv, pipe,
2626 PIPE_VBLANK_INTERRUPT_STATUS);
2627 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2628
2629 return 0;
2630 }
2631
2632 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2633 {
2634 struct drm_i915_private *dev_priv = dev->dev_private;
2635 unsigned long irqflags;
2636 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2637 DE_PIPE_VBLANK(pipe);
2638
2639 if (!i915_pipe_enabled(dev, pipe))
2640 return -EINVAL;
2641
2642 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2643 ironlake_enable_display_irq(dev_priv, bit);
2644 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2645
2646 return 0;
2647 }
2648
2649 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2650 {
2651 struct drm_i915_private *dev_priv = dev->dev_private;
2652 unsigned long irqflags;
2653
2654 if (!i915_pipe_enabled(dev, pipe))
2655 return -EINVAL;
2656
2657 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2658 i915_enable_pipestat(dev_priv, pipe,
2659 PIPE_START_VBLANK_INTERRUPT_STATUS);
2660 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2661
2662 return 0;
2663 }
2664
2665 static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2666 {
2667 struct drm_i915_private *dev_priv = dev->dev_private;
2668 unsigned long irqflags;
2669
2670 if (!i915_pipe_enabled(dev, pipe))
2671 return -EINVAL;
2672
2673 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2674 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2675 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2676 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2677 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2678 return 0;
2679 }
2680
2681 /* Called from drm generic code, passed 'crtc' which
2682 * we use as a pipe index
2683 */
2684 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2685 {
2686 struct drm_i915_private *dev_priv = dev->dev_private;
2687 unsigned long irqflags;
2688
2689 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2690 i915_disable_pipestat(dev_priv, pipe,
2691 PIPE_VBLANK_INTERRUPT_STATUS |
2692 PIPE_START_VBLANK_INTERRUPT_STATUS);
2693 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2694 }
2695
2696 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2697 {
2698 struct drm_i915_private *dev_priv = dev->dev_private;
2699 unsigned long irqflags;
2700 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2701 DE_PIPE_VBLANK(pipe);
2702
2703 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2704 ironlake_disable_display_irq(dev_priv, bit);
2705 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2706 }
2707
2708 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2709 {
2710 struct drm_i915_private *dev_priv = dev->dev_private;
2711 unsigned long irqflags;
2712
2713 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2714 i915_disable_pipestat(dev_priv, pipe,
2715 PIPE_START_VBLANK_INTERRUPT_STATUS);
2716 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2717 }
2718
2719 static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2720 {
2721 struct drm_i915_private *dev_priv = dev->dev_private;
2722 unsigned long irqflags;
2723
2724 if (!i915_pipe_enabled(dev, pipe))
2725 return;
2726
2727 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2728 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2729 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2730 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2731 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2732 }
2733
2734 static u32
2735 ring_last_seqno(struct intel_engine_cs *ring)
2736 {
2737 return list_entry(ring->request_list.prev,
2738 struct drm_i915_gem_request, list)->seqno;
2739 }
2740
2741 static bool
2742 ring_idle(struct intel_engine_cs *ring, u32 seqno)
2743 {
2744 return (list_empty(&ring->request_list) ||
2745 i915_seqno_passed(seqno, ring_last_seqno(ring)));
2746 }
2747
2748 static bool
2749 ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
2750 {
2751 if (INTEL_INFO(dev)->gen >= 8) {
2752 /*
2753 * FIXME: gen8 semaphore support - currently we don't emit
2754 * semaphores on bdw anyway, but this needs to be addressed when
2755 * we merge that code.
2756 */
2757 return false;
2758 } else {
2759 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2760 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2761 MI_SEMAPHORE_REGISTER);
2762 }
2763 }
2764
2765 static struct intel_engine_cs *
2766 semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr)
2767 {
2768 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2769 struct intel_engine_cs *signaller;
2770 int i;
2771
2772 if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
2773 /*
2774 * FIXME: gen8 semaphore support - currently we don't emit
2775 * semaphores on bdw anyway, but this needs to be addressed when
2776 * we merge that code.
2777 */
2778 return NULL;
2779 } else {
2780 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2781
2782 for_each_ring(signaller, dev_priv, i) {
2783 if(ring == signaller)
2784 continue;
2785
2786 if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
2787 return signaller;
2788 }
2789 }
2790
2791 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x\n",
2792 ring->id, ipehr);
2793
2794 return NULL;
2795 }
2796
2797 static struct intel_engine_cs *
2798 semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
2799 {
2800 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2801 u32 cmd, ipehr, head;
2802 int i;
2803
2804 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2805 if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
2806 return NULL;
2807
2808 /*
2809 * HEAD is likely pointing to the dword after the actual command,
2810 * so scan backwards until we find the MBOX. But limit it to just 3
2811 * dwords. Note that we don't care about ACTHD here since that might
2812 * point at at batch, and semaphores are always emitted into the
2813 * ringbuffer itself.
2814 */
2815 head = I915_READ_HEAD(ring) & HEAD_ADDR;
2816
2817 for (i = 4; i; --i) {
2818 /*
2819 * Be paranoid and presume the hw has gone off into the wild -
2820 * our ring is smaller than what the hardware (and hence
2821 * HEAD_ADDR) allows. Also handles wrap-around.
2822 */
2823 head &= ring->buffer->size - 1;
2824
2825 /* This here seems to blow up */
2826 cmd = ioread32(ring->buffer->virtual_start + head);
2827 if (cmd == ipehr)
2828 break;
2829
2830 head -= 4;
2831 }
2832
2833 if (!i)
2834 return NULL;
2835
2836 *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
2837 return semaphore_wait_to_signaller_ring(ring, ipehr);
2838 }
2839
2840 static int semaphore_passed(struct intel_engine_cs *ring)
2841 {
2842 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2843 struct intel_engine_cs *signaller;
2844 u32 seqno, ctl;
2845
2846 ring->hangcheck.deadlock++;
2847
2848 signaller = semaphore_waits_for(ring, &seqno);
2849 if (signaller == NULL)
2850 return -1;
2851
2852 /* Prevent pathological recursion due to driver bugs */
2853 if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
2854 return -1;
2855
2856 /* cursory check for an unkickable deadlock */
2857 ctl = I915_READ_CTL(signaller);
2858 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2859 return -1;
2860
2861 if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
2862 return 1;
2863
2864 if (signaller->hangcheck.deadlock)
2865 return -1;
2866
2867 return 0;
2868 }
2869
2870 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2871 {
2872 struct intel_engine_cs *ring;
2873 int i;
2874
2875 for_each_ring(ring, dev_priv, i)
2876 ring->hangcheck.deadlock = 0;
2877 }
2878
2879 static enum intel_ring_hangcheck_action
2880 ring_stuck(struct intel_engine_cs *ring, u64 acthd)
2881 {
2882 struct drm_device *dev = ring->dev;
2883 struct drm_i915_private *dev_priv = dev->dev_private;
2884 u32 tmp;
2885
2886 if (ring->hangcheck.acthd != acthd)
2887 return HANGCHECK_ACTIVE;
2888
2889 if (IS_GEN2(dev))
2890 return HANGCHECK_HUNG;
2891
2892 /* Is the chip hanging on a WAIT_FOR_EVENT?
2893 * If so we can simply poke the RB_WAIT bit
2894 * and break the hang. This should work on
2895 * all but the second generation chipsets.
2896 */
2897 tmp = I915_READ_CTL(ring);
2898 if (tmp & RING_WAIT) {
2899 i915_handle_error(dev, false,
2900 "Kicking stuck wait on %s",
2901 ring->name);
2902 I915_WRITE_CTL(ring, tmp);
2903 return HANGCHECK_KICK;
2904 }
2905
2906 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2907 switch (semaphore_passed(ring)) {
2908 default:
2909 return HANGCHECK_HUNG;
2910 case 1:
2911 i915_handle_error(dev, false,
2912 "Kicking stuck semaphore on %s",
2913 ring->name);
2914 I915_WRITE_CTL(ring, tmp);
2915 return HANGCHECK_KICK;
2916 case 0:
2917 return HANGCHECK_WAIT;
2918 }
2919 }
2920
2921 return HANGCHECK_HUNG;
2922 }
2923
2924 /**
2925 * This is called when the chip hasn't reported back with completed
2926 * batchbuffers in a long time. We keep track per ring seqno progress and
2927 * if there are no progress, hangcheck score for that ring is increased.
2928 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2929 * we kick the ring. If we see no progress on three subsequent calls
2930 * we assume chip is wedged and try to fix it by resetting the chip.
2931 */
2932 static void i915_hangcheck_elapsed(unsigned long data)
2933 {
2934 struct drm_device *dev = (struct drm_device *)data;
2935 struct drm_i915_private *dev_priv = dev->dev_private;
2936 struct intel_engine_cs *ring;
2937 int i;
2938 int busy_count = 0, rings_hung = 0;
2939 bool stuck[I915_NUM_RINGS] = { 0 };
2940 #define BUSY 1
2941 #define KICK 5
2942 #define HUNG 20
2943
2944 if (!i915.enable_hangcheck)
2945 return;
2946
2947 for_each_ring(ring, dev_priv, i) {
2948 u64 acthd;
2949 u32 seqno;
2950 bool busy = true;
2951
2952 semaphore_clear_deadlocks(dev_priv);
2953
2954 seqno = ring->get_seqno(ring, false);
2955 acthd = intel_ring_get_active_head(ring);
2956
2957 if (ring->hangcheck.seqno == seqno) {
2958 if (ring_idle(ring, seqno)) {
2959 ring->hangcheck.action = HANGCHECK_IDLE;
2960
2961 if (waitqueue_active(&ring->irq_queue)) {
2962 /* Issue a wake-up to catch stuck h/w. */
2963 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2964 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2965 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2966 ring->name);
2967 else
2968 DRM_INFO("Fake missed irq on %s\n",
2969 ring->name);
2970 wake_up_all(&ring->irq_queue);
2971 }
2972 /* Safeguard against driver failure */
2973 ring->hangcheck.score += BUSY;
2974 } else
2975 busy = false;
2976 } else {
2977 /* We always increment the hangcheck score
2978 * if the ring is busy and still processing
2979 * the same request, so that no single request
2980 * can run indefinitely (such as a chain of
2981 * batches). The only time we do not increment
2982 * the hangcheck score on this ring, if this
2983 * ring is in a legitimate wait for another
2984 * ring. In that case the waiting ring is a
2985 * victim and we want to be sure we catch the
2986 * right culprit. Then every time we do kick
2987 * the ring, add a small increment to the
2988 * score so that we can catch a batch that is
2989 * being repeatedly kicked and so responsible
2990 * for stalling the machine.
2991 */
2992 ring->hangcheck.action = ring_stuck(ring,
2993 acthd);
2994
2995 switch (ring->hangcheck.action) {
2996 case HANGCHECK_IDLE:
2997 case HANGCHECK_WAIT:
2998 break;
2999 case HANGCHECK_ACTIVE:
3000 ring->hangcheck.score += BUSY;
3001 break;
3002 case HANGCHECK_KICK:
3003 ring->hangcheck.score += KICK;
3004 break;
3005 case HANGCHECK_HUNG:
3006 ring->hangcheck.score += HUNG;
3007 stuck[i] = true;
3008 break;
3009 }
3010 }
3011 } else {
3012 ring->hangcheck.action = HANGCHECK_ACTIVE;
3013
3014 /* Gradually reduce the count so that we catch DoS
3015 * attempts across multiple batches.
3016 */
3017 if (ring->hangcheck.score > 0)
3018 ring->hangcheck.score--;
3019 }
3020
3021 ring->hangcheck.seqno = seqno;
3022 ring->hangcheck.acthd = acthd;
3023 busy_count += busy;
3024 }
3025
3026 for_each_ring(ring, dev_priv, i) {
3027 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3028 DRM_INFO("%s on %s\n",
3029 stuck[i] ? "stuck" : "no progress",
3030 ring->name);
3031 rings_hung++;
3032 }
3033 }
3034
3035 if (rings_hung)
3036 return i915_handle_error(dev, true, "Ring hung");
3037
3038 if (busy_count)
3039 /* Reset timer case chip hangs without another request
3040 * being added */
3041 i915_queue_hangcheck(dev);
3042 }
3043
3044 void i915_queue_hangcheck(struct drm_device *dev)
3045 {
3046 struct drm_i915_private *dev_priv = dev->dev_private;
3047 if (!i915.enable_hangcheck)
3048 return;
3049
3050 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
3051 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
3052 }
3053
3054 static void ibx_irq_reset(struct drm_device *dev)
3055 {
3056 struct drm_i915_private *dev_priv = dev->dev_private;
3057
3058 if (HAS_PCH_NOP(dev))
3059 return;
3060
3061 GEN5_IRQ_RESET(SDE);
3062
3063 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3064 I915_WRITE(SERR_INT, 0xffffffff);
3065 }
3066
3067 /*
3068 * SDEIER is also touched by the interrupt handler to work around missed PCH
3069 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3070 * instead we unconditionally enable all PCH interrupt sources here, but then
3071 * only unmask them as needed with SDEIMR.
3072 *
3073 * This function needs to be called before interrupts are enabled.
3074 */
3075 static void ibx_irq_pre_postinstall(struct drm_device *dev)
3076 {
3077 struct drm_i915_private *dev_priv = dev->dev_private;
3078
3079 if (HAS_PCH_NOP(dev))
3080 return;
3081
3082 WARN_ON(I915_READ(SDEIER) != 0);
3083 I915_WRITE(SDEIER, 0xffffffff);
3084 POSTING_READ(SDEIER);
3085 }
3086
3087 static void gen5_gt_irq_reset(struct drm_device *dev)
3088 {
3089 struct drm_i915_private *dev_priv = dev->dev_private;
3090
3091 GEN5_IRQ_RESET(GT);
3092 if (INTEL_INFO(dev)->gen >= 6)
3093 GEN5_IRQ_RESET(GEN6_PM);
3094 }
3095
3096 /* drm_dma.h hooks
3097 */
3098 static void ironlake_irq_reset(struct drm_device *dev)
3099 {
3100 struct drm_i915_private *dev_priv = dev->dev_private;
3101
3102 I915_WRITE(HWSTAM, 0xffffffff);
3103
3104 GEN5_IRQ_RESET(DE);
3105 if (IS_GEN7(dev))
3106 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3107
3108 gen5_gt_irq_reset(dev);
3109
3110 ibx_irq_reset(dev);
3111 }
3112
3113 static void valleyview_irq_preinstall(struct drm_device *dev)
3114 {
3115 struct drm_i915_private *dev_priv = dev->dev_private;
3116 int pipe;
3117
3118 /* VLV magic */
3119 I915_WRITE(VLV_IMR, 0);
3120 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
3121 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
3122 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
3123
3124 /* and GT */
3125 I915_WRITE(GTIIR, I915_READ(GTIIR));
3126 I915_WRITE(GTIIR, I915_READ(GTIIR));
3127
3128 gen5_gt_irq_reset(dev);
3129
3130 I915_WRITE(DPINVGTT, 0xff);
3131
3132 I915_WRITE(PORT_HOTPLUG_EN, 0);
3133 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3134 for_each_pipe(pipe)
3135 I915_WRITE(PIPESTAT(pipe), 0xffff);
3136 I915_WRITE(VLV_IIR, 0xffffffff);
3137 I915_WRITE(VLV_IMR, 0xffffffff);
3138 I915_WRITE(VLV_IER, 0x0);
3139 POSTING_READ(VLV_IER);
3140 }
3141
3142 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3143 {
3144 GEN8_IRQ_RESET_NDX(GT, 0);
3145 GEN8_IRQ_RESET_NDX(GT, 1);
3146 GEN8_IRQ_RESET_NDX(GT, 2);
3147 GEN8_IRQ_RESET_NDX(GT, 3);
3148 }
3149
3150 static void gen8_irq_reset(struct drm_device *dev)
3151 {
3152 struct drm_i915_private *dev_priv = dev->dev_private;
3153 int pipe;
3154
3155 I915_WRITE(GEN8_MASTER_IRQ, 0);
3156 POSTING_READ(GEN8_MASTER_IRQ);
3157
3158 gen8_gt_irq_reset(dev_priv);
3159
3160 for_each_pipe(pipe)
3161 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3162
3163 GEN5_IRQ_RESET(GEN8_DE_PORT_);
3164 GEN5_IRQ_RESET(GEN8_DE_MISC_);
3165 GEN5_IRQ_RESET(GEN8_PCU_);
3166
3167 ibx_irq_reset(dev);
3168 }
3169
3170 static void cherryview_irq_preinstall(struct drm_device *dev)
3171 {
3172 struct drm_i915_private *dev_priv = dev->dev_private;
3173 int pipe;
3174
3175 I915_WRITE(GEN8_MASTER_IRQ, 0);
3176 POSTING_READ(GEN8_MASTER_IRQ);
3177
3178 gen8_gt_irq_reset(dev_priv);
3179
3180 GEN5_IRQ_RESET(GEN8_PCU_);
3181
3182 POSTING_READ(GEN8_PCU_IIR);
3183
3184 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3185
3186 I915_WRITE(PORT_HOTPLUG_EN, 0);
3187 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3188
3189 for_each_pipe(pipe)
3190 I915_WRITE(PIPESTAT(pipe), 0xffff);
3191
3192 I915_WRITE(VLV_IMR, 0xffffffff);
3193 I915_WRITE(VLV_IER, 0x0);
3194 I915_WRITE(VLV_IIR, 0xffffffff);
3195 POSTING_READ(VLV_IIR);
3196 }
3197
3198 static void ibx_hpd_irq_setup(struct drm_device *dev)
3199 {
3200 struct drm_i915_private *dev_priv = dev->dev_private;
3201 struct drm_mode_config *mode_config = &dev->mode_config;
3202 struct intel_encoder *intel_encoder;
3203 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
3204
3205 if (HAS_PCH_IBX(dev)) {
3206 hotplug_irqs = SDE_HOTPLUG_MASK;
3207 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3208 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3209 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
3210 } else {
3211 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3212 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3213 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3214 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
3215 }
3216
3217 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3218
3219 /*
3220 * Enable digital hotplug on the PCH, and configure the DP short pulse
3221 * duration to 2ms (which is the minimum in the Display Port spec)
3222 *
3223 * This register is the same on all known PCH chips.
3224 */
3225 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3226 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3227 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3228 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3229 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3230 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3231 }
3232
3233 static void ibx_irq_postinstall(struct drm_device *dev)
3234 {
3235 struct drm_i915_private *dev_priv = dev->dev_private;
3236 u32 mask;
3237
3238 if (HAS_PCH_NOP(dev))
3239 return;
3240
3241 if (HAS_PCH_IBX(dev))
3242 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3243 else
3244 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3245
3246 GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
3247 I915_WRITE(SDEIMR, ~mask);
3248 }
3249
3250 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3251 {
3252 struct drm_i915_private *dev_priv = dev->dev_private;
3253 u32 pm_irqs, gt_irqs;
3254
3255 pm_irqs = gt_irqs = 0;
3256
3257 dev_priv->gt_irq_mask = ~0;
3258 if (HAS_L3_DPF(dev)) {
3259 /* L3 parity interrupt is always unmasked. */
3260 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3261 gt_irqs |= GT_PARITY_ERROR(dev);
3262 }
3263
3264 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3265 if (IS_GEN5(dev)) {
3266 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3267 ILK_BSD_USER_INTERRUPT;
3268 } else {
3269 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3270 }
3271
3272 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3273
3274 if (INTEL_INFO(dev)->gen >= 6) {
3275 pm_irqs |= dev_priv->pm_rps_events;
3276
3277 if (HAS_VEBOX(dev))
3278 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3279
3280 dev_priv->pm_irq_mask = 0xffffffff;
3281 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3282 }
3283 }
3284
3285 static int ironlake_irq_postinstall(struct drm_device *dev)
3286 {
3287 unsigned long irqflags;
3288 struct drm_i915_private *dev_priv = dev->dev_private;
3289 u32 display_mask, extra_mask;
3290
3291 if (INTEL_INFO(dev)->gen >= 7) {
3292 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3293 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3294 DE_PLANEB_FLIP_DONE_IVB |
3295 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3296 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3297 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
3298 } else {
3299 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3300 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3301 DE_AUX_CHANNEL_A |
3302 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3303 DE_POISON);
3304 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3305 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
3306 }
3307
3308 dev_priv->irq_mask = ~display_mask;
3309
3310 I915_WRITE(HWSTAM, 0xeffe);
3311
3312 ibx_irq_pre_postinstall(dev);
3313
3314 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3315
3316 gen5_gt_irq_postinstall(dev);
3317
3318 ibx_irq_postinstall(dev);
3319
3320 if (IS_IRONLAKE_M(dev)) {
3321 /* Enable PCU event interrupts
3322 *
3323 * spinlocking not required here for correctness since interrupt
3324 * setup is guaranteed to run in single-threaded context. But we
3325 * need it to make the assert_spin_locked happy. */
3326 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3327 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
3328 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3329 }
3330
3331 return 0;
3332 }
3333
3334 static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3335 {
3336 u32 pipestat_mask;
3337 u32 iir_mask;
3338
3339 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3340 PIPE_FIFO_UNDERRUN_STATUS;
3341
3342 I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3343 I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3344 POSTING_READ(PIPESTAT(PIPE_A));
3345
3346 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3347 PIPE_CRC_DONE_INTERRUPT_STATUS;
3348
3349 i915_enable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3350 PIPE_GMBUS_INTERRUPT_STATUS);
3351 i915_enable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3352
3353 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3354 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3355 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3356 dev_priv->irq_mask &= ~iir_mask;
3357
3358 I915_WRITE(VLV_IIR, iir_mask);
3359 I915_WRITE(VLV_IIR, iir_mask);
3360 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3361 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3362 POSTING_READ(VLV_IER);
3363 }
3364
3365 static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3366 {
3367 u32 pipestat_mask;
3368 u32 iir_mask;
3369
3370 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3371 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3372 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3373
3374 dev_priv->irq_mask |= iir_mask;
3375 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3376 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3377 I915_WRITE(VLV_IIR, iir_mask);
3378 I915_WRITE(VLV_IIR, iir_mask);
3379 POSTING_READ(VLV_IIR);
3380
3381 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3382 PIPE_CRC_DONE_INTERRUPT_STATUS;
3383
3384 i915_disable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3385 PIPE_GMBUS_INTERRUPT_STATUS);
3386 i915_disable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3387
3388 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3389 PIPE_FIFO_UNDERRUN_STATUS;
3390 I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3391 I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3392 POSTING_READ(PIPESTAT(PIPE_A));
3393 }
3394
3395 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3396 {
3397 assert_spin_locked(&dev_priv->irq_lock);
3398
3399 if (dev_priv->display_irqs_enabled)
3400 return;
3401
3402 dev_priv->display_irqs_enabled = true;
3403
3404 if (dev_priv->dev->irq_enabled)
3405 valleyview_display_irqs_install(dev_priv);
3406 }
3407
3408 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3409 {
3410 assert_spin_locked(&dev_priv->irq_lock);
3411
3412 if (!dev_priv->display_irqs_enabled)
3413 return;
3414
3415 dev_priv->display_irqs_enabled = false;
3416
3417 if (dev_priv->dev->irq_enabled)
3418 valleyview_display_irqs_uninstall(dev_priv);
3419 }
3420
3421 static int valleyview_irq_postinstall(struct drm_device *dev)
3422 {
3423 struct drm_i915_private *dev_priv = dev->dev_private;
3424 unsigned long irqflags;
3425
3426 dev_priv->irq_mask = ~0;
3427
3428 I915_WRITE(PORT_HOTPLUG_EN, 0);
3429 POSTING_READ(PORT_HOTPLUG_EN);
3430
3431 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3432 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3433 I915_WRITE(VLV_IIR, 0xffffffff);
3434 POSTING_READ(VLV_IER);
3435
3436 /* Interrupt setup is already guaranteed to be single-threaded, this is
3437 * just to make the assert_spin_locked check happy. */
3438 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3439 if (dev_priv->display_irqs_enabled)
3440 valleyview_display_irqs_install(dev_priv);
3441 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3442
3443 I915_WRITE(VLV_IIR, 0xffffffff);
3444 I915_WRITE(VLV_IIR, 0xffffffff);
3445
3446 gen5_gt_irq_postinstall(dev);
3447
3448 /* ack & enable invalid PTE error interrupts */
3449 #if 0 /* FIXME: add support to irq handler for checking these bits */
3450 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3451 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3452 #endif
3453
3454 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3455
3456 return 0;
3457 }
3458
3459 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3460 {
3461 int i;
3462
3463 /* These are interrupts we'll toggle with the ring mask register */
3464 uint32_t gt_interrupts[] = {
3465 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3466 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3467 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3468 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3469 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3470 0,
3471 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3472 };
3473
3474 for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++)
3475 GEN8_IRQ_INIT_NDX(GT, i, ~gt_interrupts[i], gt_interrupts[i]);
3476
3477 dev_priv->pm_irq_mask = 0xffffffff;
3478 }
3479
3480 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3481 {
3482 struct drm_device *dev = dev_priv->dev;
3483 uint32_t de_pipe_masked = GEN8_PIPE_PRIMARY_FLIP_DONE |
3484 GEN8_PIPE_CDCLK_CRC_DONE |
3485 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3486 uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3487 GEN8_PIPE_FIFO_UNDERRUN;
3488 int pipe;
3489 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3490 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3491 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3492
3493 for_each_pipe(pipe)
3494 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, dev_priv->de_irq_mask[pipe],
3495 de_pipe_enables);
3496
3497 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~GEN8_AUX_CHANNEL_A, GEN8_AUX_CHANNEL_A);
3498 }
3499
3500 static int gen8_irq_postinstall(struct drm_device *dev)
3501 {
3502 struct drm_i915_private *dev_priv = dev->dev_private;
3503
3504 ibx_irq_pre_postinstall(dev);
3505
3506 gen8_gt_irq_postinstall(dev_priv);
3507 gen8_de_irq_postinstall(dev_priv);
3508
3509 ibx_irq_postinstall(dev);
3510
3511 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3512 POSTING_READ(GEN8_MASTER_IRQ);
3513
3514 return 0;
3515 }
3516
3517 static int cherryview_irq_postinstall(struct drm_device *dev)
3518 {
3519 struct drm_i915_private *dev_priv = dev->dev_private;
3520 u32 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
3521 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3522 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3523 I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3524 u32 pipestat_enable = PLANE_FLIP_DONE_INT_STATUS_VLV |
3525 PIPE_CRC_DONE_INTERRUPT_STATUS;
3526 unsigned long irqflags;
3527 int pipe;
3528
3529 /*
3530 * Leave vblank interrupts masked initially. enable/disable will
3531 * toggle them based on usage.
3532 */
3533 dev_priv->irq_mask = ~enable_mask;
3534
3535 for_each_pipe(pipe)
3536 I915_WRITE(PIPESTAT(pipe), 0xffff);
3537
3538 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3539 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3540 for_each_pipe(pipe)
3541 i915_enable_pipestat(dev_priv, pipe, pipestat_enable);
3542 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3543
3544 I915_WRITE(VLV_IIR, 0xffffffff);
3545 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3546 I915_WRITE(VLV_IER, enable_mask);
3547
3548 gen8_gt_irq_postinstall(dev_priv);
3549
3550 I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
3551 POSTING_READ(GEN8_MASTER_IRQ);
3552
3553 return 0;
3554 }
3555
3556 static void gen8_irq_uninstall(struct drm_device *dev)
3557 {
3558 struct drm_i915_private *dev_priv = dev->dev_private;
3559
3560 if (!dev_priv)
3561 return;
3562
3563 intel_hpd_irq_uninstall(dev_priv);
3564
3565 gen8_irq_reset(dev);
3566 }
3567
3568 static void valleyview_irq_uninstall(struct drm_device *dev)
3569 {
3570 struct drm_i915_private *dev_priv = dev->dev_private;
3571 unsigned long irqflags;
3572 int pipe;
3573
3574 if (!dev_priv)
3575 return;
3576
3577 I915_WRITE(VLV_MASTER_IER, 0);
3578
3579 intel_hpd_irq_uninstall(dev_priv);
3580
3581 for_each_pipe(pipe)
3582 I915_WRITE(PIPESTAT(pipe), 0xffff);
3583
3584 I915_WRITE(HWSTAM, 0xffffffff);
3585 I915_WRITE(PORT_HOTPLUG_EN, 0);
3586 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3587
3588 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3589 if (dev_priv->display_irqs_enabled)
3590 valleyview_display_irqs_uninstall(dev_priv);
3591 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3592
3593 dev_priv->irq_mask = 0;
3594
3595 I915_WRITE(VLV_IIR, 0xffffffff);
3596 I915_WRITE(VLV_IMR, 0xffffffff);
3597 I915_WRITE(VLV_IER, 0x0);
3598 POSTING_READ(VLV_IER);
3599 }
3600
3601 static void cherryview_irq_uninstall(struct drm_device *dev)
3602 {
3603 struct drm_i915_private *dev_priv = dev->dev_private;
3604 int pipe;
3605
3606 if (!dev_priv)
3607 return;
3608
3609 I915_WRITE(GEN8_MASTER_IRQ, 0);
3610 POSTING_READ(GEN8_MASTER_IRQ);
3611
3612 #define GEN8_IRQ_FINI_NDX(type, which) \
3613 do { \
3614 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
3615 I915_WRITE(GEN8_##type##_IER(which), 0); \
3616 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
3617 POSTING_READ(GEN8_##type##_IIR(which)); \
3618 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
3619 } while (0)
3620
3621 #define GEN8_IRQ_FINI(type) \
3622 do { \
3623 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
3624 I915_WRITE(GEN8_##type##_IER, 0); \
3625 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
3626 POSTING_READ(GEN8_##type##_IIR); \
3627 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
3628 } while (0)
3629
3630 GEN8_IRQ_FINI_NDX(GT, 0);
3631 GEN8_IRQ_FINI_NDX(GT, 1);
3632 GEN8_IRQ_FINI_NDX(GT, 2);
3633 GEN8_IRQ_FINI_NDX(GT, 3);
3634
3635 GEN8_IRQ_FINI(PCU);
3636
3637 #undef GEN8_IRQ_FINI
3638 #undef GEN8_IRQ_FINI_NDX
3639
3640 I915_WRITE(PORT_HOTPLUG_EN, 0);
3641 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3642
3643 for_each_pipe(pipe)
3644 I915_WRITE(PIPESTAT(pipe), 0xffff);
3645
3646 I915_WRITE(VLV_IMR, 0xffffffff);
3647 I915_WRITE(VLV_IER, 0x0);
3648 I915_WRITE(VLV_IIR, 0xffffffff);
3649 POSTING_READ(VLV_IIR);
3650 }
3651
3652 static void ironlake_irq_uninstall(struct drm_device *dev)
3653 {
3654 struct drm_i915_private *dev_priv = dev->dev_private;
3655
3656 if (!dev_priv)
3657 return;
3658
3659 intel_hpd_irq_uninstall(dev_priv);
3660
3661 ironlake_irq_reset(dev);
3662 }
3663
3664 static void i8xx_irq_preinstall(struct drm_device * dev)
3665 {
3666 struct drm_i915_private *dev_priv = dev->dev_private;
3667 int pipe;
3668
3669 for_each_pipe(pipe)
3670 I915_WRITE(PIPESTAT(pipe), 0);
3671 I915_WRITE16(IMR, 0xffff);
3672 I915_WRITE16(IER, 0x0);
3673 POSTING_READ16(IER);
3674 }
3675
3676 static int i8xx_irq_postinstall(struct drm_device *dev)
3677 {
3678 struct drm_i915_private *dev_priv = dev->dev_private;
3679 unsigned long irqflags;
3680
3681 I915_WRITE16(EMR,
3682 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3683
3684 /* Unmask the interrupts that we always want on. */
3685 dev_priv->irq_mask =
3686 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3687 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3688 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3689 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3690 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3691 I915_WRITE16(IMR, dev_priv->irq_mask);
3692
3693 I915_WRITE16(IER,
3694 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3695 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3696 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3697 I915_USER_INTERRUPT);
3698 POSTING_READ16(IER);
3699
3700 /* Interrupt setup is already guaranteed to be single-threaded, this is
3701 * just to make the assert_spin_locked check happy. */
3702 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3703 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3704 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3705 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3706
3707 return 0;
3708 }
3709
3710 /*
3711 * Returns true when a page flip has completed.
3712 */
3713 static bool i8xx_handle_vblank(struct drm_device *dev,
3714 int plane, int pipe, u32 iir)
3715 {
3716 struct drm_i915_private *dev_priv = dev->dev_private;
3717 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3718
3719 if (!intel_pipe_handle_vblank(dev, pipe))
3720 return false;
3721
3722 if ((iir & flip_pending) == 0)
3723 return false;
3724
3725 intel_prepare_page_flip(dev, plane);
3726
3727 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3728 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3729 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3730 * the flip is completed (no longer pending). Since this doesn't raise
3731 * an interrupt per se, we watch for the change at vblank.
3732 */
3733 if (I915_READ16(ISR) & flip_pending)
3734 return false;
3735
3736 intel_finish_page_flip(dev, pipe);
3737
3738 return true;
3739 }
3740
3741 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3742 {
3743 struct drm_device *dev = arg;
3744 struct drm_i915_private *dev_priv = dev->dev_private;
3745 u16 iir, new_iir;
3746 u32 pipe_stats[2];
3747 unsigned long irqflags;
3748 int pipe;
3749 u16 flip_mask =
3750 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3751 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3752
3753 iir = I915_READ16(IIR);
3754 if (iir == 0)
3755 return IRQ_NONE;
3756
3757 while (iir & ~flip_mask) {
3758 /* Can't rely on pipestat interrupt bit in iir as it might
3759 * have been cleared after the pipestat interrupt was received.
3760 * It doesn't set the bit in iir again, but it still produces
3761 * interrupts (for non-MSI).
3762 */
3763 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3764 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3765 i915_handle_error(dev, false,
3766 "Command parser error, iir 0x%08x",
3767 iir);
3768
3769 for_each_pipe(pipe) {
3770 int reg = PIPESTAT(pipe);
3771 pipe_stats[pipe] = I915_READ(reg);
3772
3773 /*
3774 * Clear the PIPE*STAT regs before the IIR
3775 */
3776 if (pipe_stats[pipe] & 0x8000ffff)
3777 I915_WRITE(reg, pipe_stats[pipe]);
3778 }
3779 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3780
3781 I915_WRITE16(IIR, iir & ~flip_mask);
3782 new_iir = I915_READ16(IIR); /* Flush posted writes */
3783
3784 i915_update_dri1_breadcrumb(dev);
3785
3786 if (iir & I915_USER_INTERRUPT)
3787 notify_ring(dev, &dev_priv->ring[RCS]);
3788
3789 for_each_pipe(pipe) {
3790 int plane = pipe;
3791 if (HAS_FBC(dev))
3792 plane = !plane;
3793
3794 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3795 i8xx_handle_vblank(dev, plane, pipe, iir))
3796 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3797
3798 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3799 i9xx_pipe_crc_irq_handler(dev, pipe);
3800
3801 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3802 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3803 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3804 }
3805
3806 iir = new_iir;
3807 }
3808
3809 return IRQ_HANDLED;
3810 }
3811
3812 static void i8xx_irq_uninstall(struct drm_device * dev)
3813 {
3814 struct drm_i915_private *dev_priv = dev->dev_private;
3815 int pipe;
3816
3817 for_each_pipe(pipe) {
3818 /* Clear enable bits; then clear status bits */
3819 I915_WRITE(PIPESTAT(pipe), 0);
3820 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3821 }
3822 I915_WRITE16(IMR, 0xffff);
3823 I915_WRITE16(IER, 0x0);
3824 I915_WRITE16(IIR, I915_READ16(IIR));
3825 }
3826
3827 static void i915_irq_preinstall(struct drm_device * dev)
3828 {
3829 struct drm_i915_private *dev_priv = dev->dev_private;
3830 int pipe;
3831
3832 if (I915_HAS_HOTPLUG(dev)) {
3833 I915_WRITE(PORT_HOTPLUG_EN, 0);
3834 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3835 }
3836
3837 I915_WRITE16(HWSTAM, 0xeffe);
3838 for_each_pipe(pipe)
3839 I915_WRITE(PIPESTAT(pipe), 0);
3840 I915_WRITE(IMR, 0xffffffff);
3841 I915_WRITE(IER, 0x0);
3842 POSTING_READ(IER);
3843 }
3844
3845 static int i915_irq_postinstall(struct drm_device *dev)
3846 {
3847 struct drm_i915_private *dev_priv = dev->dev_private;
3848 u32 enable_mask;
3849 unsigned long irqflags;
3850
3851 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3852
3853 /* Unmask the interrupts that we always want on. */
3854 dev_priv->irq_mask =
3855 ~(I915_ASLE_INTERRUPT |
3856 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3857 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3858 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3859 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3860 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3861
3862 enable_mask =
3863 I915_ASLE_INTERRUPT |
3864 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3865 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3866 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3867 I915_USER_INTERRUPT;
3868
3869 if (I915_HAS_HOTPLUG(dev)) {
3870 I915_WRITE(PORT_HOTPLUG_EN, 0);
3871 POSTING_READ(PORT_HOTPLUG_EN);
3872
3873 /* Enable in IER... */
3874 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3875 /* and unmask in IMR */
3876 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3877 }
3878
3879 I915_WRITE(IMR, dev_priv->irq_mask);
3880 I915_WRITE(IER, enable_mask);
3881 POSTING_READ(IER);
3882
3883 i915_enable_asle_pipestat(dev);
3884
3885 /* Interrupt setup is already guaranteed to be single-threaded, this is
3886 * just to make the assert_spin_locked check happy. */
3887 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3888 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3889 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3890 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3891
3892 return 0;
3893 }
3894
3895 /*
3896 * Returns true when a page flip has completed.
3897 */
3898 static bool i915_handle_vblank(struct drm_device *dev,
3899 int plane, int pipe, u32 iir)
3900 {
3901 struct drm_i915_private *dev_priv = dev->dev_private;
3902 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3903
3904 if (!intel_pipe_handle_vblank(dev, pipe))
3905 return false;
3906
3907 if ((iir & flip_pending) == 0)
3908 return false;
3909
3910 intel_prepare_page_flip(dev, plane);
3911
3912 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3913 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3914 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3915 * the flip is completed (no longer pending). Since this doesn't raise
3916 * an interrupt per se, we watch for the change at vblank.
3917 */
3918 if (I915_READ(ISR) & flip_pending)
3919 return false;
3920
3921 intel_finish_page_flip(dev, pipe);
3922
3923 return true;
3924 }
3925
3926 static irqreturn_t i915_irq_handler(int irq, void *arg)
3927 {
3928 struct drm_device *dev = arg;
3929 struct drm_i915_private *dev_priv = dev->dev_private;
3930 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3931 unsigned long irqflags;
3932 u32 flip_mask =
3933 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3934 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3935 int pipe, ret = IRQ_NONE;
3936
3937 iir = I915_READ(IIR);
3938 do {
3939 bool irq_received = (iir & ~flip_mask) != 0;
3940 bool blc_event = false;
3941
3942 /* Can't rely on pipestat interrupt bit in iir as it might
3943 * have been cleared after the pipestat interrupt was received.
3944 * It doesn't set the bit in iir again, but it still produces
3945 * interrupts (for non-MSI).
3946 */
3947 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3948 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3949 i915_handle_error(dev, false,
3950 "Command parser error, iir 0x%08x",
3951 iir);
3952
3953 for_each_pipe(pipe) {
3954 int reg = PIPESTAT(pipe);
3955 pipe_stats[pipe] = I915_READ(reg);
3956
3957 /* Clear the PIPE*STAT regs before the IIR */
3958 if (pipe_stats[pipe] & 0x8000ffff) {
3959 I915_WRITE(reg, pipe_stats[pipe]);
3960 irq_received = true;
3961 }
3962 }
3963 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3964
3965 if (!irq_received)
3966 break;
3967
3968 /* Consume port. Then clear IIR or we'll miss events */
3969 if (I915_HAS_HOTPLUG(dev) &&
3970 iir & I915_DISPLAY_PORT_INTERRUPT)
3971 i9xx_hpd_irq_handler(dev);
3972
3973 I915_WRITE(IIR, iir & ~flip_mask);
3974 new_iir = I915_READ(IIR); /* Flush posted writes */
3975
3976 if (iir & I915_USER_INTERRUPT)
3977 notify_ring(dev, &dev_priv->ring[RCS]);
3978
3979 for_each_pipe(pipe) {
3980 int plane = pipe;
3981 if (HAS_FBC(dev))
3982 plane = !plane;
3983
3984 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3985 i915_handle_vblank(dev, plane, pipe, iir))
3986 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3987
3988 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3989 blc_event = true;
3990
3991 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3992 i9xx_pipe_crc_irq_handler(dev, pipe);
3993
3994 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3995 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3996 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3997 }
3998
3999 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4000 intel_opregion_asle_intr(dev);
4001
4002 /* With MSI, interrupts are only generated when iir
4003 * transitions from zero to nonzero. If another bit got
4004 * set while we were handling the existing iir bits, then
4005 * we would never get another interrupt.
4006 *
4007 * This is fine on non-MSI as well, as if we hit this path
4008 * we avoid exiting the interrupt handler only to generate
4009 * another one.
4010 *
4011 * Note that for MSI this could cause a stray interrupt report
4012 * if an interrupt landed in the time between writing IIR and
4013 * the posting read. This should be rare enough to never
4014 * trigger the 99% of 100,000 interrupts test for disabling
4015 * stray interrupts.
4016 */
4017 ret = IRQ_HANDLED;
4018 iir = new_iir;
4019 } while (iir & ~flip_mask);
4020
4021 i915_update_dri1_breadcrumb(dev);
4022
4023 return ret;
4024 }
4025
4026 static void i915_irq_uninstall(struct drm_device * dev)
4027 {
4028 struct drm_i915_private *dev_priv = dev->dev_private;
4029 int pipe;
4030
4031 intel_hpd_irq_uninstall(dev_priv);
4032
4033 if (I915_HAS_HOTPLUG(dev)) {
4034 I915_WRITE(PORT_HOTPLUG_EN, 0);
4035 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4036 }
4037
4038 I915_WRITE16(HWSTAM, 0xffff);
4039 for_each_pipe(pipe) {
4040 /* Clear enable bits; then clear status bits */
4041 I915_WRITE(PIPESTAT(pipe), 0);
4042 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4043 }
4044 I915_WRITE(IMR, 0xffffffff);
4045 I915_WRITE(IER, 0x0);
4046
4047 I915_WRITE(IIR, I915_READ(IIR));
4048 }
4049
4050 static void i965_irq_preinstall(struct drm_device * dev)
4051 {
4052 struct drm_i915_private *dev_priv = dev->dev_private;
4053 int pipe;
4054
4055 I915_WRITE(PORT_HOTPLUG_EN, 0);
4056 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4057
4058 I915_WRITE(HWSTAM, 0xeffe);
4059 for_each_pipe(pipe)
4060 I915_WRITE(PIPESTAT(pipe), 0);
4061 I915_WRITE(IMR, 0xffffffff);
4062 I915_WRITE(IER, 0x0);
4063 POSTING_READ(IER);
4064 }
4065
4066 static int i965_irq_postinstall(struct drm_device *dev)
4067 {
4068 struct drm_i915_private *dev_priv = dev->dev_private;
4069 u32 enable_mask;
4070 u32 error_mask;
4071 unsigned long irqflags;
4072
4073 /* Unmask the interrupts that we always want on. */
4074 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4075 I915_DISPLAY_PORT_INTERRUPT |
4076 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4077 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4078 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4079 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4080 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4081
4082 enable_mask = ~dev_priv->irq_mask;
4083 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4084 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4085 enable_mask |= I915_USER_INTERRUPT;
4086
4087 if (IS_G4X(dev))
4088 enable_mask |= I915_BSD_USER_INTERRUPT;
4089
4090 /* Interrupt setup is already guaranteed to be single-threaded, this is
4091 * just to make the assert_spin_locked check happy. */
4092 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4093 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4094 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4095 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4096 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4097
4098 /*
4099 * Enable some error detection, note the instruction error mask
4100 * bit is reserved, so we leave it masked.
4101 */
4102 if (IS_G4X(dev)) {
4103 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4104 GM45_ERROR_MEM_PRIV |
4105 GM45_ERROR_CP_PRIV |
4106 I915_ERROR_MEMORY_REFRESH);
4107 } else {
4108 error_mask = ~(I915_ERROR_PAGE_TABLE |
4109 I915_ERROR_MEMORY_REFRESH);
4110 }
4111 I915_WRITE(EMR, error_mask);
4112
4113 I915_WRITE(IMR, dev_priv->irq_mask);
4114 I915_WRITE(IER, enable_mask);
4115 POSTING_READ(IER);
4116
4117 I915_WRITE(PORT_HOTPLUG_EN, 0);
4118 POSTING_READ(PORT_HOTPLUG_EN);
4119
4120 i915_enable_asle_pipestat(dev);
4121
4122 return 0;
4123 }
4124
4125 static void i915_hpd_irq_setup(struct drm_device *dev)
4126 {
4127 struct drm_i915_private *dev_priv = dev->dev_private;
4128 struct drm_mode_config *mode_config = &dev->mode_config;
4129 struct intel_encoder *intel_encoder;
4130 u32 hotplug_en;
4131
4132 assert_spin_locked(&dev_priv->irq_lock);
4133
4134 if (I915_HAS_HOTPLUG(dev)) {
4135 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
4136 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
4137 /* Note HDMI and DP share hotplug bits */
4138 /* enable bits are the same for all generations */
4139 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
4140 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
4141 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
4142 /* Programming the CRT detection parameters tends
4143 to generate a spurious hotplug event about three
4144 seconds later. So just do it once.
4145 */
4146 if (IS_G4X(dev))
4147 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4148 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
4149 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4150
4151 /* Ignore TV since it's buggy */
4152 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
4153 }
4154 }
4155
4156 static irqreturn_t i965_irq_handler(int irq, void *arg)
4157 {
4158 struct drm_device *dev = arg;
4159 struct drm_i915_private *dev_priv = dev->dev_private;
4160 u32 iir, new_iir;
4161 u32 pipe_stats[I915_MAX_PIPES];
4162 unsigned long irqflags;
4163 int ret = IRQ_NONE, pipe;
4164 u32 flip_mask =
4165 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4166 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4167
4168 iir = I915_READ(IIR);
4169
4170 for (;;) {
4171 bool irq_received = (iir & ~flip_mask) != 0;
4172 bool blc_event = false;
4173
4174 /* Can't rely on pipestat interrupt bit in iir as it might
4175 * have been cleared after the pipestat interrupt was received.
4176 * It doesn't set the bit in iir again, but it still produces
4177 * interrupts (for non-MSI).
4178 */
4179 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4180 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4181 i915_handle_error(dev, false,
4182 "Command parser error, iir 0x%08x",
4183 iir);
4184
4185 for_each_pipe(pipe) {
4186 int reg = PIPESTAT(pipe);
4187 pipe_stats[pipe] = I915_READ(reg);
4188
4189 /*
4190 * Clear the PIPE*STAT regs before the IIR
4191 */
4192 if (pipe_stats[pipe] & 0x8000ffff) {
4193 I915_WRITE(reg, pipe_stats[pipe]);
4194 irq_received = true;
4195 }
4196 }
4197 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4198
4199 if (!irq_received)
4200 break;
4201
4202 ret = IRQ_HANDLED;
4203
4204 /* Consume port. Then clear IIR or we'll miss events */
4205 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4206 i9xx_hpd_irq_handler(dev);
4207
4208 I915_WRITE(IIR, iir & ~flip_mask);
4209 new_iir = I915_READ(IIR); /* Flush posted writes */
4210
4211 if (iir & I915_USER_INTERRUPT)
4212 notify_ring(dev, &dev_priv->ring[RCS]);
4213 if (iir & I915_BSD_USER_INTERRUPT)
4214 notify_ring(dev, &dev_priv->ring[VCS]);
4215
4216 for_each_pipe(pipe) {
4217 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4218 i915_handle_vblank(dev, pipe, pipe, iir))
4219 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4220
4221 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4222 blc_event = true;
4223
4224 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4225 i9xx_pipe_crc_irq_handler(dev, pipe);
4226
4227 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
4228 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
4229 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
4230 }
4231
4232 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4233 intel_opregion_asle_intr(dev);
4234
4235 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4236 gmbus_irq_handler(dev);
4237
4238 /* With MSI, interrupts are only generated when iir
4239 * transitions from zero to nonzero. If another bit got
4240 * set while we were handling the existing iir bits, then
4241 * we would never get another interrupt.
4242 *
4243 * This is fine on non-MSI as well, as if we hit this path
4244 * we avoid exiting the interrupt handler only to generate
4245 * another one.
4246 *
4247 * Note that for MSI this could cause a stray interrupt report
4248 * if an interrupt landed in the time between writing IIR and
4249 * the posting read. This should be rare enough to never
4250 * trigger the 99% of 100,000 interrupts test for disabling
4251 * stray interrupts.
4252 */
4253 iir = new_iir;
4254 }
4255
4256 i915_update_dri1_breadcrumb(dev);
4257
4258 return ret;
4259 }
4260
4261 static void i965_irq_uninstall(struct drm_device * dev)
4262 {
4263 struct drm_i915_private *dev_priv = dev->dev_private;
4264 int pipe;
4265
4266 if (!dev_priv)
4267 return;
4268
4269 intel_hpd_irq_uninstall(dev_priv);
4270
4271 I915_WRITE(PORT_HOTPLUG_EN, 0);
4272 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4273
4274 I915_WRITE(HWSTAM, 0xffffffff);
4275 for_each_pipe(pipe)
4276 I915_WRITE(PIPESTAT(pipe), 0);
4277 I915_WRITE(IMR, 0xffffffff);
4278 I915_WRITE(IER, 0x0);
4279
4280 for_each_pipe(pipe)
4281 I915_WRITE(PIPESTAT(pipe),
4282 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4283 I915_WRITE(IIR, I915_READ(IIR));
4284 }
4285
4286 static void intel_hpd_irq_reenable(unsigned long data)
4287 {
4288 struct drm_i915_private *dev_priv = (struct drm_i915_private *)data;
4289 struct drm_device *dev = dev_priv->dev;
4290 struct drm_mode_config *mode_config = &dev->mode_config;
4291 unsigned long irqflags;
4292 int i;
4293
4294 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4295 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
4296 struct drm_connector *connector;
4297
4298 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
4299 continue;
4300
4301 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4302
4303 list_for_each_entry(connector, &mode_config->connector_list, head) {
4304 struct intel_connector *intel_connector = to_intel_connector(connector);
4305
4306 if (intel_connector->encoder->hpd_pin == i) {
4307 if (connector->polled != intel_connector->polled)
4308 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
4309 connector->name);
4310 connector->polled = intel_connector->polled;
4311 if (!connector->polled)
4312 connector->polled = DRM_CONNECTOR_POLL_HPD;
4313 }
4314 }
4315 }
4316 if (dev_priv->display.hpd_irq_setup)
4317 dev_priv->display.hpd_irq_setup(dev);
4318 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4319 }
4320
4321 void intel_irq_init(struct drm_device *dev)
4322 {
4323 struct drm_i915_private *dev_priv = dev->dev_private;
4324
4325 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
4326 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
4327 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4328 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4329
4330 /* Let's track the enabled rps events */
4331 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4332
4333 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
4334 i915_hangcheck_elapsed,
4335 (unsigned long) dev);
4336 setup_timer(&dev_priv->hotplug_reenable_timer, intel_hpd_irq_reenable,
4337 (unsigned long) dev_priv);
4338
4339 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4340
4341 if (IS_GEN2(dev)) {
4342 dev->max_vblank_count = 0;
4343 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4344 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
4345 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4346 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
4347 } else {
4348 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4349 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4350 }
4351
4352 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
4353 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4354 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4355 }
4356
4357 if (IS_CHERRYVIEW(dev)) {
4358 dev->driver->irq_handler = cherryview_irq_handler;
4359 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4360 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4361 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4362 dev->driver->enable_vblank = valleyview_enable_vblank;
4363 dev->driver->disable_vblank = valleyview_disable_vblank;
4364 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4365 } else if (IS_VALLEYVIEW(dev)) {
4366 dev->driver->irq_handler = valleyview_irq_handler;
4367 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4368 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4369 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4370 dev->driver->enable_vblank = valleyview_enable_vblank;
4371 dev->driver->disable_vblank = valleyview_disable_vblank;
4372 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4373 } else if (IS_GEN8(dev)) {
4374 dev->driver->irq_handler = gen8_irq_handler;
4375 dev->driver->irq_preinstall = gen8_irq_reset;
4376 dev->driver->irq_postinstall = gen8_irq_postinstall;
4377 dev->driver->irq_uninstall = gen8_irq_uninstall;
4378 dev->driver->enable_vblank = gen8_enable_vblank;
4379 dev->driver->disable_vblank = gen8_disable_vblank;
4380 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4381 } else if (HAS_PCH_SPLIT(dev)) {
4382 dev->driver->irq_handler = ironlake_irq_handler;
4383 dev->driver->irq_preinstall = ironlake_irq_reset;
4384 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4385 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4386 dev->driver->enable_vblank = ironlake_enable_vblank;
4387 dev->driver->disable_vblank = ironlake_disable_vblank;
4388 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4389 } else {
4390 if (INTEL_INFO(dev)->gen == 2) {
4391 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4392 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4393 dev->driver->irq_handler = i8xx_irq_handler;
4394 dev->driver->irq_uninstall = i8xx_irq_uninstall;
4395 } else if (INTEL_INFO(dev)->gen == 3) {
4396 dev->driver->irq_preinstall = i915_irq_preinstall;
4397 dev->driver->irq_postinstall = i915_irq_postinstall;
4398 dev->driver->irq_uninstall = i915_irq_uninstall;
4399 dev->driver->irq_handler = i915_irq_handler;
4400 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4401 } else {
4402 dev->driver->irq_preinstall = i965_irq_preinstall;
4403 dev->driver->irq_postinstall = i965_irq_postinstall;
4404 dev->driver->irq_uninstall = i965_irq_uninstall;
4405 dev->driver->irq_handler = i965_irq_handler;
4406 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4407 }
4408 dev->driver->enable_vblank = i915_enable_vblank;
4409 dev->driver->disable_vblank = i915_disable_vblank;
4410 }
4411 }
4412
4413 void intel_hpd_init(struct drm_device *dev)
4414 {
4415 struct drm_i915_private *dev_priv = dev->dev_private;
4416 struct drm_mode_config *mode_config = &dev->mode_config;
4417 struct drm_connector *connector;
4418 unsigned long irqflags;
4419 int i;
4420
4421 for (i = 1; i < HPD_NUM_PINS; i++) {
4422 dev_priv->hpd_stats[i].hpd_cnt = 0;
4423 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4424 }
4425 list_for_each_entry(connector, &mode_config->connector_list, head) {
4426 struct intel_connector *intel_connector = to_intel_connector(connector);
4427 connector->polled = intel_connector->polled;
4428 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
4429 connector->polled = DRM_CONNECTOR_POLL_HPD;
4430 }
4431
4432 /* Interrupt setup is already guaranteed to be single-threaded, this is
4433 * just to make the assert_spin_locked checks happy. */
4434 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4435 if (dev_priv->display.hpd_irq_setup)
4436 dev_priv->display.hpd_irq_setup(dev);
4437 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4438 }
4439
4440 /* Disable interrupts so we can allow runtime PM. */
4441 void intel_runtime_pm_disable_interrupts(struct drm_device *dev)
4442 {
4443 struct drm_i915_private *dev_priv = dev->dev_private;
4444
4445 dev->driver->irq_uninstall(dev);
4446 dev_priv->pm.irqs_disabled = true;
4447 }
4448
4449 /* Restore interrupts so we can recover from runtime PM. */
4450 void intel_runtime_pm_restore_interrupts(struct drm_device *dev)
4451 {
4452 struct drm_i915_private *dev_priv = dev->dev_private;
4453
4454 dev_priv->pm.irqs_disabled = false;
4455 dev->driver->irq_preinstall(dev);
4456 dev->driver->irq_postinstall(dev);
4457 }
Linux kernel - Deliverables
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