1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
34 #include <drm/i915_drm.h>
36 #include "i915_trace.h"
37 #include "intel_drv.h"
39 static const u32 hpd_ibx
[] = {
40 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
41 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
42 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
43 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
44 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
47 static const u32 hpd_cpt
[] = {
48 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
49 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG_CPT
,
50 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
51 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
52 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
55 static const u32 hpd_mask_i915
[] = {
56 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
57 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
58 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
59 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
60 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
61 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
64 static const u32 hpd_status_gen4
[] = {
65 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
66 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
67 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
68 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
69 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
70 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
73 static const u32 hpd_status_i915
[] = { /* i915 and valleyview are the same */
74 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
75 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
76 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
77 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
78 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
79 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
82 /* For display hotplug interrupt */
84 ironlake_enable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
86 assert_spin_locked(&dev_priv
->irq_lock
);
88 if (dev_priv
->pc8
.irqs_disabled
) {
89 WARN(1, "IRQs disabled\n");
90 dev_priv
->pc8
.regsave
.deimr
&= ~mask
;
94 if ((dev_priv
->irq_mask
& mask
) != 0) {
95 dev_priv
->irq_mask
&= ~mask
;
96 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
102 ironlake_disable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
104 assert_spin_locked(&dev_priv
->irq_lock
);
106 if (dev_priv
->pc8
.irqs_disabled
) {
107 WARN(1, "IRQs disabled\n");
108 dev_priv
->pc8
.regsave
.deimr
|= mask
;
112 if ((dev_priv
->irq_mask
& mask
) != mask
) {
113 dev_priv
->irq_mask
|= mask
;
114 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
120 * ilk_update_gt_irq - update GTIMR
121 * @dev_priv: driver private
122 * @interrupt_mask: mask of interrupt bits to update
123 * @enabled_irq_mask: mask of interrupt bits to enable
125 static void ilk_update_gt_irq(struct drm_i915_private
*dev_priv
,
126 uint32_t interrupt_mask
,
127 uint32_t enabled_irq_mask
)
129 assert_spin_locked(&dev_priv
->irq_lock
);
131 if (dev_priv
->pc8
.irqs_disabled
) {
132 WARN(1, "IRQs disabled\n");
133 dev_priv
->pc8
.regsave
.gtimr
&= ~interrupt_mask
;
134 dev_priv
->pc8
.regsave
.gtimr
|= (~enabled_irq_mask
&
139 dev_priv
->gt_irq_mask
&= ~interrupt_mask
;
140 dev_priv
->gt_irq_mask
|= (~enabled_irq_mask
& interrupt_mask
);
141 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
145 void ilk_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
147 ilk_update_gt_irq(dev_priv
, mask
, mask
);
150 void ilk_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
152 ilk_update_gt_irq(dev_priv
, mask
, 0);
156 * snb_update_pm_irq - update GEN6_PMIMR
157 * @dev_priv: driver private
158 * @interrupt_mask: mask of interrupt bits to update
159 * @enabled_irq_mask: mask of interrupt bits to enable
161 static void snb_update_pm_irq(struct drm_i915_private
*dev_priv
,
162 uint32_t interrupt_mask
,
163 uint32_t enabled_irq_mask
)
167 assert_spin_locked(&dev_priv
->irq_lock
);
169 if (dev_priv
->pc8
.irqs_disabled
) {
170 WARN(1, "IRQs disabled\n");
171 dev_priv
->pc8
.regsave
.gen6_pmimr
&= ~interrupt_mask
;
172 dev_priv
->pc8
.regsave
.gen6_pmimr
|= (~enabled_irq_mask
&
177 new_val
= dev_priv
->pm_irq_mask
;
178 new_val
&= ~interrupt_mask
;
179 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
181 if (new_val
!= dev_priv
->pm_irq_mask
) {
182 dev_priv
->pm_irq_mask
= new_val
;
183 I915_WRITE(GEN6_PMIMR
, dev_priv
->pm_irq_mask
);
184 POSTING_READ(GEN6_PMIMR
);
188 void snb_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
190 snb_update_pm_irq(dev_priv
, mask
, mask
);
193 void snb_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
195 snb_update_pm_irq(dev_priv
, mask
, 0);
198 static bool ivb_can_enable_err_int(struct drm_device
*dev
)
200 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
201 struct intel_crtc
*crtc
;
204 assert_spin_locked(&dev_priv
->irq_lock
);
206 for_each_pipe(pipe
) {
207 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
209 if (crtc
->cpu_fifo_underrun_disabled
)
216 static bool cpt_can_enable_serr_int(struct drm_device
*dev
)
218 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
220 struct intel_crtc
*crtc
;
222 assert_spin_locked(&dev_priv
->irq_lock
);
224 for_each_pipe(pipe
) {
225 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
227 if (crtc
->pch_fifo_underrun_disabled
)
234 static void ironlake_set_fifo_underrun_reporting(struct drm_device
*dev
,
235 enum pipe pipe
, bool enable
)
237 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
238 uint32_t bit
= (pipe
== PIPE_A
) ? DE_PIPEA_FIFO_UNDERRUN
:
239 DE_PIPEB_FIFO_UNDERRUN
;
242 ironlake_enable_display_irq(dev_priv
, bit
);
244 ironlake_disable_display_irq(dev_priv
, bit
);
247 static void ivybridge_set_fifo_underrun_reporting(struct drm_device
*dev
,
248 enum pipe pipe
, bool enable
)
250 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
252 I915_WRITE(GEN7_ERR_INT
, ERR_INT_FIFO_UNDERRUN(pipe
));
254 if (!ivb_can_enable_err_int(dev
))
257 ironlake_enable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
259 bool was_enabled
= !(I915_READ(DEIMR
) & DE_ERR_INT_IVB
);
261 /* Change the state _after_ we've read out the current one. */
262 ironlake_disable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
265 (I915_READ(GEN7_ERR_INT
) & ERR_INT_FIFO_UNDERRUN(pipe
))) {
266 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
273 * ibx_display_interrupt_update - update SDEIMR
274 * @dev_priv: driver private
275 * @interrupt_mask: mask of interrupt bits to update
276 * @enabled_irq_mask: mask of interrupt bits to enable
278 static void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
279 uint32_t interrupt_mask
,
280 uint32_t enabled_irq_mask
)
282 uint32_t sdeimr
= I915_READ(SDEIMR
);
283 sdeimr
&= ~interrupt_mask
;
284 sdeimr
|= (~enabled_irq_mask
& interrupt_mask
);
286 assert_spin_locked(&dev_priv
->irq_lock
);
288 if (dev_priv
->pc8
.irqs_disabled
&&
289 (interrupt_mask
& SDE_HOTPLUG_MASK_CPT
)) {
290 WARN(1, "IRQs disabled\n");
291 dev_priv
->pc8
.regsave
.sdeimr
&= ~interrupt_mask
;
292 dev_priv
->pc8
.regsave
.sdeimr
|= (~enabled_irq_mask
&
297 I915_WRITE(SDEIMR
, sdeimr
);
298 POSTING_READ(SDEIMR
);
300 #define ibx_enable_display_interrupt(dev_priv, bits) \
301 ibx_display_interrupt_update((dev_priv), (bits), (bits))
302 #define ibx_disable_display_interrupt(dev_priv, bits) \
303 ibx_display_interrupt_update((dev_priv), (bits), 0)
305 static void ibx_set_fifo_underrun_reporting(struct drm_device
*dev
,
306 enum transcoder pch_transcoder
,
309 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
310 uint32_t bit
= (pch_transcoder
== TRANSCODER_A
) ?
311 SDE_TRANSA_FIFO_UNDER
: SDE_TRANSB_FIFO_UNDER
;
314 ibx_enable_display_interrupt(dev_priv
, bit
);
316 ibx_disable_display_interrupt(dev_priv
, bit
);
319 static void cpt_set_fifo_underrun_reporting(struct drm_device
*dev
,
320 enum transcoder pch_transcoder
,
323 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
327 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
));
329 if (!cpt_can_enable_serr_int(dev
))
332 ibx_enable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
334 uint32_t tmp
= I915_READ(SERR_INT
);
335 bool was_enabled
= !(I915_READ(SDEIMR
) & SDE_ERROR_CPT
);
337 /* Change the state _after_ we've read out the current one. */
338 ibx_disable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
341 (tmp
& SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
))) {
342 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
343 transcoder_name(pch_transcoder
));
349 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
352 * @enable: true if we want to report FIFO underrun errors, false otherwise
354 * This function makes us disable or enable CPU fifo underruns for a specific
355 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
356 * reporting for one pipe may also disable all the other CPU error interruts for
357 * the other pipes, due to the fact that there's just one interrupt mask/enable
358 * bit for all the pipes.
360 * Returns the previous state of underrun reporting.
362 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device
*dev
,
363 enum pipe pipe
, bool enable
)
365 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
366 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
367 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
371 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
373 ret
= !intel_crtc
->cpu_fifo_underrun_disabled
;
378 intel_crtc
->cpu_fifo_underrun_disabled
= !enable
;
380 if (IS_GEN5(dev
) || IS_GEN6(dev
))
381 ironlake_set_fifo_underrun_reporting(dev
, pipe
, enable
);
382 else if (IS_GEN7(dev
))
383 ivybridge_set_fifo_underrun_reporting(dev
, pipe
, enable
);
386 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
391 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
393 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
394 * @enable: true if we want to report FIFO underrun errors, false otherwise
396 * This function makes us disable or enable PCH fifo underruns for a specific
397 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
398 * underrun reporting for one transcoder may also disable all the other PCH
399 * error interruts for the other transcoders, due to the fact that there's just
400 * one interrupt mask/enable bit for all the transcoders.
402 * Returns the previous state of underrun reporting.
404 bool intel_set_pch_fifo_underrun_reporting(struct drm_device
*dev
,
405 enum transcoder pch_transcoder
,
408 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
409 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pch_transcoder
];
410 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
415 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
416 * has only one pch transcoder A that all pipes can use. To avoid racy
417 * pch transcoder -> pipe lookups from interrupt code simply store the
418 * underrun statistics in crtc A. Since we never expose this anywhere
419 * nor use it outside of the fifo underrun code here using the "wrong"
420 * crtc on LPT won't cause issues.
423 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
425 ret
= !intel_crtc
->pch_fifo_underrun_disabled
;
430 intel_crtc
->pch_fifo_underrun_disabled
= !enable
;
432 if (HAS_PCH_IBX(dev
))
433 ibx_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
435 cpt_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
438 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
444 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
446 u32 reg
= PIPESTAT(pipe
);
447 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
449 assert_spin_locked(&dev_priv
->irq_lock
);
451 if ((pipestat
& mask
) == mask
)
454 /* Enable the interrupt, clear any pending status */
455 pipestat
|= mask
| (mask
>> 16);
456 I915_WRITE(reg
, pipestat
);
461 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
463 u32 reg
= PIPESTAT(pipe
);
464 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
466 assert_spin_locked(&dev_priv
->irq_lock
);
468 if ((pipestat
& mask
) == 0)
472 I915_WRITE(reg
, pipestat
);
477 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
479 static void i915_enable_asle_pipestat(struct drm_device
*dev
)
481 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
482 unsigned long irqflags
;
484 if (!dev_priv
->opregion
.asle
|| !IS_MOBILE(dev
))
487 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
489 i915_enable_pipestat(dev_priv
, 1, PIPE_LEGACY_BLC_EVENT_ENABLE
);
490 if (INTEL_INFO(dev
)->gen
>= 4)
491 i915_enable_pipestat(dev_priv
, 0, PIPE_LEGACY_BLC_EVENT_ENABLE
);
493 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
497 * i915_pipe_enabled - check if a pipe is enabled
499 * @pipe: pipe to check
501 * Reading certain registers when the pipe is disabled can hang the chip.
502 * Use this routine to make sure the PLL is running and the pipe is active
503 * before reading such registers if unsure.
506 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
508 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
510 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
511 /* Locking is horribly broken here, but whatever. */
512 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
513 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
515 return intel_crtc
->active
;
517 return I915_READ(PIPECONF(pipe
)) & PIPECONF_ENABLE
;
521 /* Called from drm generic code, passed a 'crtc', which
522 * we use as a pipe index
524 static u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
526 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
527 unsigned long high_frame
;
528 unsigned long low_frame
;
529 u32 high1
, high2
, low
, pixel
, vbl_start
;
531 if (!i915_pipe_enabled(dev
, pipe
)) {
532 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
533 "pipe %c\n", pipe_name(pipe
));
537 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
538 struct intel_crtc
*intel_crtc
=
539 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
540 const struct drm_display_mode
*mode
=
541 &intel_crtc
->config
.adjusted_mode
;
543 vbl_start
= mode
->crtc_vblank_start
* mode
->crtc_htotal
;
545 enum transcoder cpu_transcoder
=
546 intel_pipe_to_cpu_transcoder(dev_priv
, pipe
);
549 htotal
= ((I915_READ(HTOTAL(cpu_transcoder
)) >> 16) & 0x1fff) + 1;
550 vbl_start
= (I915_READ(VBLANK(cpu_transcoder
)) & 0x1fff) + 1;
555 high_frame
= PIPEFRAME(pipe
);
556 low_frame
= PIPEFRAMEPIXEL(pipe
);
559 * High & low register fields aren't synchronized, so make sure
560 * we get a low value that's stable across two reads of the high
564 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
565 low
= I915_READ(low_frame
);
566 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
567 } while (high1
!= high2
);
569 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
570 pixel
= low
& PIPE_PIXEL_MASK
;
571 low
>>= PIPE_FRAME_LOW_SHIFT
;
574 * The frame counter increments at beginning of active.
575 * Cook up a vblank counter by also checking the pixel
576 * counter against vblank start.
578 return ((high1
<< 8) | low
) + (pixel
>= vbl_start
);
581 static u32
gm45_get_vblank_counter(struct drm_device
*dev
, int pipe
)
583 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
584 int reg
= PIPE_FRMCOUNT_GM45(pipe
);
586 if (!i915_pipe_enabled(dev
, pipe
)) {
587 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
588 "pipe %c\n", pipe_name(pipe
));
592 return I915_READ(reg
);
595 static bool g4x_pipe_in_vblank(struct drm_device
*dev
, enum pipe pipe
)
597 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
600 if (IS_VALLEYVIEW(dev
)) {
601 status
= pipe
== PIPE_A
?
602 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
:
603 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
605 return I915_READ(VLV_ISR
) & status
;
606 } else if (IS_G4X(dev
)) {
607 status
= pipe
== PIPE_A
?
608 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
:
609 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
611 return I915_READ(ISR
) & status
;
612 } else if (INTEL_INFO(dev
)->gen
< 7) {
613 status
= pipe
== PIPE_A
?
617 return I915_READ(DEISR
) & status
;
622 status
= DE_PIPEA_VBLANK_IVB
;
625 status
= DE_PIPEB_VBLANK_IVB
;
628 status
= DE_PIPEC_VBLANK_IVB
;
632 return I915_READ(DEISR
) & status
;
636 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, int pipe
,
637 int *vpos
, int *hpos
)
639 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
640 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
641 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
642 const struct drm_display_mode
*mode
= &intel_crtc
->config
.adjusted_mode
;
644 int vbl_start
, vbl_end
, htotal
, vtotal
;
648 if (!intel_crtc
->active
) {
649 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
650 "pipe %c\n", pipe_name(pipe
));
654 htotal
= mode
->crtc_htotal
;
655 vtotal
= mode
->crtc_vtotal
;
656 vbl_start
= mode
->crtc_vblank_start
;
657 vbl_end
= mode
->crtc_vblank_end
;
659 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
661 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
662 /* No obvious pixelcount register. Only query vertical
663 * scanout position from Display scan line register.
665 position
= I915_READ(PIPEDSL(pipe
)) & 0x1fff;
668 * The scanline counter increments at the leading edge
669 * of hsync, ie. it completely misses the active portion
670 * of the line. Fix up the counter at both edges of vblank
671 * to get a more accurate picture whether we're in vblank
674 in_vbl
= g4x_pipe_in_vblank(dev
, pipe
);
675 if ((in_vbl
&& position
== vbl_start
- 1) ||
676 (!in_vbl
&& position
== vbl_end
- 1))
677 position
= (position
+ 1) % vtotal
;
679 /* Have access to pixelcount since start of frame.
680 * We can split this into vertical and horizontal
683 position
= (I915_READ(PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
685 /* convert to pixel counts */
691 in_vbl
= position
>= vbl_start
&& position
< vbl_end
;
694 * While in vblank, position will be negative
695 * counting up towards 0 at vbl_end. And outside
696 * vblank, position will be positive counting
699 if (position
>= vbl_start
)
702 position
+= vtotal
- vbl_end
;
704 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
708 *vpos
= position
/ htotal
;
709 *hpos
= position
- (*vpos
* htotal
);
714 ret
|= DRM_SCANOUTPOS_INVBL
;
719 static int i915_get_vblank_timestamp(struct drm_device
*dev
, int pipe
,
721 struct timeval
*vblank_time
,
724 struct drm_crtc
*crtc
;
726 if (pipe
< 0 || pipe
>= INTEL_INFO(dev
)->num_pipes
) {
727 DRM_ERROR("Invalid crtc %d\n", pipe
);
731 /* Get drm_crtc to timestamp: */
732 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
734 DRM_ERROR("Invalid crtc %d\n", pipe
);
738 if (!crtc
->enabled
) {
739 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
743 /* Helper routine in DRM core does all the work: */
744 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
749 static bool intel_hpd_irq_event(struct drm_device
*dev
,
750 struct drm_connector
*connector
)
752 enum drm_connector_status old_status
;
754 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
755 old_status
= connector
->status
;
757 connector
->status
= connector
->funcs
->detect(connector
, false);
758 if (old_status
== connector
->status
)
761 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
763 drm_get_connector_name(connector
),
764 drm_get_connector_status_name(old_status
),
765 drm_get_connector_status_name(connector
->status
));
771 * Handle hotplug events outside the interrupt handler proper.
773 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
775 static void i915_hotplug_work_func(struct work_struct
*work
)
777 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
779 struct drm_device
*dev
= dev_priv
->dev
;
780 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
781 struct intel_connector
*intel_connector
;
782 struct intel_encoder
*intel_encoder
;
783 struct drm_connector
*connector
;
784 unsigned long irqflags
;
785 bool hpd_disabled
= false;
786 bool changed
= false;
789 /* HPD irq before everything is fully set up. */
790 if (!dev_priv
->enable_hotplug_processing
)
793 mutex_lock(&mode_config
->mutex
);
794 DRM_DEBUG_KMS("running encoder hotplug functions\n");
796 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
798 hpd_event_bits
= dev_priv
->hpd_event_bits
;
799 dev_priv
->hpd_event_bits
= 0;
800 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
801 intel_connector
= to_intel_connector(connector
);
802 intel_encoder
= intel_connector
->encoder
;
803 if (intel_encoder
->hpd_pin
> HPD_NONE
&&
804 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_MARK_DISABLED
&&
805 connector
->polled
== DRM_CONNECTOR_POLL_HPD
) {
806 DRM_INFO("HPD interrupt storm detected on connector %s: "
807 "switching from hotplug detection to polling\n",
808 drm_get_connector_name(connector
));
809 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
= HPD_DISABLED
;
810 connector
->polled
= DRM_CONNECTOR_POLL_CONNECT
811 | DRM_CONNECTOR_POLL_DISCONNECT
;
814 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
815 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
816 drm_get_connector_name(connector
), intel_encoder
->hpd_pin
);
819 /* if there were no outputs to poll, poll was disabled,
820 * therefore make sure it's enabled when disabling HPD on
823 drm_kms_helper_poll_enable(dev
);
824 mod_timer(&dev_priv
->hotplug_reenable_timer
,
825 jiffies
+ msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY
));
828 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
830 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
831 intel_connector
= to_intel_connector(connector
);
832 intel_encoder
= intel_connector
->encoder
;
833 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
834 if (intel_encoder
->hot_plug
)
835 intel_encoder
->hot_plug(intel_encoder
);
836 if (intel_hpd_irq_event(dev
, connector
))
840 mutex_unlock(&mode_config
->mutex
);
843 drm_kms_helper_hotplug_event(dev
);
846 static void ironlake_rps_change_irq_handler(struct drm_device
*dev
)
848 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
849 u32 busy_up
, busy_down
, max_avg
, min_avg
;
852 spin_lock(&mchdev_lock
);
854 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
856 new_delay
= dev_priv
->ips
.cur_delay
;
858 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
859 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
860 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
861 max_avg
= I915_READ(RCBMAXAVG
);
862 min_avg
= I915_READ(RCBMINAVG
);
864 /* Handle RCS change request from hw */
865 if (busy_up
> max_avg
) {
866 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
867 new_delay
= dev_priv
->ips
.cur_delay
- 1;
868 if (new_delay
< dev_priv
->ips
.max_delay
)
869 new_delay
= dev_priv
->ips
.max_delay
;
870 } else if (busy_down
< min_avg
) {
871 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
872 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
873 if (new_delay
> dev_priv
->ips
.min_delay
)
874 new_delay
= dev_priv
->ips
.min_delay
;
877 if (ironlake_set_drps(dev
, new_delay
))
878 dev_priv
->ips
.cur_delay
= new_delay
;
880 spin_unlock(&mchdev_lock
);
885 static void notify_ring(struct drm_device
*dev
,
886 struct intel_ring_buffer
*ring
)
888 if (ring
->obj
== NULL
)
891 trace_i915_gem_request_complete(ring
);
893 wake_up_all(&ring
->irq_queue
);
894 i915_queue_hangcheck(dev
);
897 static void gen6_pm_rps_work(struct work_struct
*work
)
899 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
904 spin_lock_irq(&dev_priv
->irq_lock
);
905 pm_iir
= dev_priv
->rps
.pm_iir
;
906 dev_priv
->rps
.pm_iir
= 0;
907 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
908 snb_enable_pm_irq(dev_priv
, GEN6_PM_RPS_EVENTS
);
909 spin_unlock_irq(&dev_priv
->irq_lock
);
911 /* Make sure we didn't queue anything we're not going to process. */
912 WARN_ON(pm_iir
& ~GEN6_PM_RPS_EVENTS
);
914 if ((pm_iir
& GEN6_PM_RPS_EVENTS
) == 0)
917 mutex_lock(&dev_priv
->rps
.hw_lock
);
919 adj
= dev_priv
->rps
.last_adj
;
920 if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
) {
925 new_delay
= dev_priv
->rps
.cur_delay
+ adj
;
928 * For better performance, jump directly
929 * to RPe if we're below it.
931 if (new_delay
< dev_priv
->rps
.rpe_delay
)
932 new_delay
= dev_priv
->rps
.rpe_delay
;
933 } else if (pm_iir
& GEN6_PM_RP_DOWN_TIMEOUT
) {
934 if (dev_priv
->rps
.cur_delay
> dev_priv
->rps
.rpe_delay
)
935 new_delay
= dev_priv
->rps
.rpe_delay
;
937 new_delay
= dev_priv
->rps
.min_delay
;
939 } else if (pm_iir
& GEN6_PM_RP_DOWN_THRESHOLD
) {
944 new_delay
= dev_priv
->rps
.cur_delay
+ adj
;
945 } else { /* unknown event */
946 new_delay
= dev_priv
->rps
.cur_delay
;
949 /* sysfs frequency interfaces may have snuck in while servicing the
952 if (new_delay
< (int)dev_priv
->rps
.min_delay
)
953 new_delay
= dev_priv
->rps
.min_delay
;
954 if (new_delay
> (int)dev_priv
->rps
.max_delay
)
955 new_delay
= dev_priv
->rps
.max_delay
;
956 dev_priv
->rps
.last_adj
= new_delay
- dev_priv
->rps
.cur_delay
;
958 if (IS_VALLEYVIEW(dev_priv
->dev
))
959 valleyview_set_rps(dev_priv
->dev
, new_delay
);
961 gen6_set_rps(dev_priv
->dev
, new_delay
);
963 mutex_unlock(&dev_priv
->rps
.hw_lock
);
968 * ivybridge_parity_work - Workqueue called when a parity error interrupt
970 * @work: workqueue struct
972 * Doesn't actually do anything except notify userspace. As a consequence of
973 * this event, userspace should try to remap the bad rows since statistically
974 * it is likely the same row is more likely to go bad again.
976 static void ivybridge_parity_work(struct work_struct
*work
)
978 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
979 l3_parity
.error_work
);
980 u32 error_status
, row
, bank
, subbank
;
981 char *parity_event
[6];
986 /* We must turn off DOP level clock gating to access the L3 registers.
987 * In order to prevent a get/put style interface, acquire struct mutex
988 * any time we access those registers.
990 mutex_lock(&dev_priv
->dev
->struct_mutex
);
992 /* If we've screwed up tracking, just let the interrupt fire again */
993 if (WARN_ON(!dev_priv
->l3_parity
.which_slice
))
996 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
997 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
998 POSTING_READ(GEN7_MISCCPCTL
);
1000 while ((slice
= ffs(dev_priv
->l3_parity
.which_slice
)) != 0) {
1004 if (WARN_ON_ONCE(slice
>= NUM_L3_SLICES(dev_priv
->dev
)))
1007 dev_priv
->l3_parity
.which_slice
&= ~(1<<slice
);
1009 reg
= GEN7_L3CDERRST1
+ (slice
* 0x200);
1011 error_status
= I915_READ(reg
);
1012 row
= GEN7_PARITY_ERROR_ROW(error_status
);
1013 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
1014 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
1016 I915_WRITE(reg
, GEN7_PARITY_ERROR_VALID
| GEN7_L3CDERRST1_ENABLE
);
1019 parity_event
[0] = I915_L3_PARITY_UEVENT
"=1";
1020 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
1021 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
1022 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
1023 parity_event
[4] = kasprintf(GFP_KERNEL
, "SLICE=%d", slice
);
1024 parity_event
[5] = NULL
;
1026 kobject_uevent_env(&dev_priv
->dev
->primary
->kdev
.kobj
,
1027 KOBJ_CHANGE
, parity_event
);
1029 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1030 slice
, row
, bank
, subbank
);
1032 kfree(parity_event
[4]);
1033 kfree(parity_event
[3]);
1034 kfree(parity_event
[2]);
1035 kfree(parity_event
[1]);
1038 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
1041 WARN_ON(dev_priv
->l3_parity
.which_slice
);
1042 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1043 ilk_enable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev_priv
->dev
));
1044 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1046 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
1049 static void ivybridge_parity_error_irq_handler(struct drm_device
*dev
, u32 iir
)
1051 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1053 if (!HAS_L3_DPF(dev
))
1056 spin_lock(&dev_priv
->irq_lock
);
1057 ilk_disable_gt_irq(dev_priv
, GT_PARITY_ERROR(dev
));
1058 spin_unlock(&dev_priv
->irq_lock
);
1060 iir
&= GT_PARITY_ERROR(dev
);
1061 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1
)
1062 dev_priv
->l3_parity
.which_slice
|= 1 << 1;
1064 if (iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT
)
1065 dev_priv
->l3_parity
.which_slice
|= 1 << 0;
1067 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
1070 static void ilk_gt_irq_handler(struct drm_device
*dev
,
1071 struct drm_i915_private
*dev_priv
,
1075 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1076 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
1077 if (gt_iir
& ILK_BSD_USER_INTERRUPT
)
1078 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1081 static void snb_gt_irq_handler(struct drm_device
*dev
,
1082 struct drm_i915_private
*dev_priv
,
1087 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1088 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
1089 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
1090 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1091 if (gt_iir
& GT_BLT_USER_INTERRUPT
)
1092 notify_ring(dev
, &dev_priv
->ring
[BCS
]);
1094 if (gt_iir
& (GT_BLT_CS_ERROR_INTERRUPT
|
1095 GT_BSD_CS_ERROR_INTERRUPT
|
1096 GT_RENDER_CS_MASTER_ERROR_INTERRUPT
)) {
1097 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir
);
1098 i915_handle_error(dev
, false);
1101 if (gt_iir
& GT_PARITY_ERROR(dev
))
1102 ivybridge_parity_error_irq_handler(dev
, gt_iir
);
1105 #define HPD_STORM_DETECT_PERIOD 1000
1106 #define HPD_STORM_THRESHOLD 5
1108 static inline void intel_hpd_irq_handler(struct drm_device
*dev
,
1109 u32 hotplug_trigger
,
1112 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1114 bool storm_detected
= false;
1116 if (!hotplug_trigger
)
1119 spin_lock(&dev_priv
->irq_lock
);
1120 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
1122 WARN(((hpd
[i
] & hotplug_trigger
) &&
1123 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
),
1124 "Received HPD interrupt although disabled\n");
1126 if (!(hpd
[i
] & hotplug_trigger
) ||
1127 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
)
1130 dev_priv
->hpd_event_bits
|= (1 << i
);
1131 if (!time_in_range(jiffies
, dev_priv
->hpd_stats
[i
].hpd_last_jiffies
,
1132 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
1133 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD
))) {
1134 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
= jiffies
;
1135 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
1136 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i
);
1137 } else if (dev_priv
->hpd_stats
[i
].hpd_cnt
> HPD_STORM_THRESHOLD
) {
1138 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_MARK_DISABLED
;
1139 dev_priv
->hpd_event_bits
&= ~(1 << i
);
1140 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i
);
1141 storm_detected
= true;
1143 dev_priv
->hpd_stats
[i
].hpd_cnt
++;
1144 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i
,
1145 dev_priv
->hpd_stats
[i
].hpd_cnt
);
1150 dev_priv
->display
.hpd_irq_setup(dev
);
1151 spin_unlock(&dev_priv
->irq_lock
);
1154 * Our hotplug handler can grab modeset locks (by calling down into the
1155 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1156 * queue for otherwise the flush_work in the pageflip code will
1159 schedule_work(&dev_priv
->hotplug_work
);
1162 static void gmbus_irq_handler(struct drm_device
*dev
)
1164 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1166 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1169 static void dp_aux_irq_handler(struct drm_device
*dev
)
1171 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1173 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1176 /* The RPS events need forcewake, so we add them to a work queue and mask their
1177 * IMR bits until the work is done. Other interrupts can be processed without
1178 * the work queue. */
1179 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1181 if (pm_iir
& GEN6_PM_RPS_EVENTS
) {
1182 spin_lock(&dev_priv
->irq_lock
);
1183 dev_priv
->rps
.pm_iir
|= pm_iir
& GEN6_PM_RPS_EVENTS
;
1184 snb_disable_pm_irq(dev_priv
, pm_iir
& GEN6_PM_RPS_EVENTS
);
1185 spin_unlock(&dev_priv
->irq_lock
);
1187 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
1190 if (HAS_VEBOX(dev_priv
->dev
)) {
1191 if (pm_iir
& PM_VEBOX_USER_INTERRUPT
)
1192 notify_ring(dev_priv
->dev
, &dev_priv
->ring
[VECS
]);
1194 if (pm_iir
& PM_VEBOX_CS_ERROR_INTERRUPT
) {
1195 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir
);
1196 i915_handle_error(dev_priv
->dev
, false);
1201 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
1203 struct drm_device
*dev
= (struct drm_device
*) arg
;
1204 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1205 u32 iir
, gt_iir
, pm_iir
;
1206 irqreturn_t ret
= IRQ_NONE
;
1207 unsigned long irqflags
;
1209 u32 pipe_stats
[I915_MAX_PIPES
];
1211 atomic_inc(&dev_priv
->irq_received
);
1214 iir
= I915_READ(VLV_IIR
);
1215 gt_iir
= I915_READ(GTIIR
);
1216 pm_iir
= I915_READ(GEN6_PMIIR
);
1218 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
1223 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1225 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1226 for_each_pipe(pipe
) {
1227 int reg
= PIPESTAT(pipe
);
1228 pipe_stats
[pipe
] = I915_READ(reg
);
1231 * Clear the PIPE*STAT regs before the IIR
1233 if (pipe_stats
[pipe
] & 0x8000ffff) {
1234 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
1235 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1237 I915_WRITE(reg
, pipe_stats
[pipe
]);
1240 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1242 for_each_pipe(pipe
) {
1243 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
)
1244 drm_handle_vblank(dev
, pipe
);
1246 if (pipe_stats
[pipe
] & PLANE_FLIPDONE_INT_STATUS_VLV
) {
1247 intel_prepare_page_flip(dev
, pipe
);
1248 intel_finish_page_flip(dev
, pipe
);
1252 /* Consume port. Then clear IIR or we'll miss events */
1253 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
1254 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1255 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
1257 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1260 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
1262 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1263 I915_READ(PORT_HOTPLUG_STAT
);
1266 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1267 gmbus_irq_handler(dev
);
1270 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1272 I915_WRITE(GTIIR
, gt_iir
);
1273 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1274 I915_WRITE(VLV_IIR
, iir
);
1281 static void ibx_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1283 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1285 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK
;
1287 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_ibx
);
1289 if (pch_iir
& SDE_AUDIO_POWER_MASK
) {
1290 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK
) >>
1291 SDE_AUDIO_POWER_SHIFT
);
1292 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1296 if (pch_iir
& SDE_AUX_MASK
)
1297 dp_aux_irq_handler(dev
);
1299 if (pch_iir
& SDE_GMBUS
)
1300 gmbus_irq_handler(dev
);
1302 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
1303 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1305 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
1306 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1308 if (pch_iir
& SDE_POISON
)
1309 DRM_ERROR("PCH poison interrupt\n");
1311 if (pch_iir
& SDE_FDI_MASK
)
1313 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1315 I915_READ(FDI_RX_IIR(pipe
)));
1317 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
1318 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1320 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
1321 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1323 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
1324 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1326 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1328 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
1329 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1331 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1334 static void ivb_err_int_handler(struct drm_device
*dev
)
1336 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1337 u32 err_int
= I915_READ(GEN7_ERR_INT
);
1339 if (err_int
& ERR_INT_POISON
)
1340 DRM_ERROR("Poison interrupt\n");
1342 if (err_int
& ERR_INT_FIFO_UNDERRUN_A
)
1343 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_A
, false))
1344 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1346 if (err_int
& ERR_INT_FIFO_UNDERRUN_B
)
1347 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_B
, false))
1348 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1350 if (err_int
& ERR_INT_FIFO_UNDERRUN_C
)
1351 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_C
, false))
1352 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1354 I915_WRITE(GEN7_ERR_INT
, err_int
);
1357 static void cpt_serr_int_handler(struct drm_device
*dev
)
1359 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1360 u32 serr_int
= I915_READ(SERR_INT
);
1362 if (serr_int
& SERR_INT_POISON
)
1363 DRM_ERROR("PCH poison interrupt\n");
1365 if (serr_int
& SERR_INT_TRANS_A_FIFO_UNDERRUN
)
1366 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1368 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1370 if (serr_int
& SERR_INT_TRANS_B_FIFO_UNDERRUN
)
1371 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1373 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1375 if (serr_int
& SERR_INT_TRANS_C_FIFO_UNDERRUN
)
1376 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_C
,
1378 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1380 I915_WRITE(SERR_INT
, serr_int
);
1383 static void cpt_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1385 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1387 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_CPT
;
1389 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_cpt
);
1391 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) {
1392 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
1393 SDE_AUDIO_POWER_SHIFT_CPT
);
1394 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1398 if (pch_iir
& SDE_AUX_MASK_CPT
)
1399 dp_aux_irq_handler(dev
);
1401 if (pch_iir
& SDE_GMBUS_CPT
)
1402 gmbus_irq_handler(dev
);
1404 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
1405 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1407 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
1408 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1410 if (pch_iir
& SDE_FDI_MASK_CPT
)
1412 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1414 I915_READ(FDI_RX_IIR(pipe
)));
1416 if (pch_iir
& SDE_ERROR_CPT
)
1417 cpt_serr_int_handler(dev
);
1420 static void ilk_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
1422 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1424 if (de_iir
& DE_AUX_CHANNEL_A
)
1425 dp_aux_irq_handler(dev
);
1427 if (de_iir
& DE_GSE
)
1428 intel_opregion_asle_intr(dev
);
1430 if (de_iir
& DE_PIPEA_VBLANK
)
1431 drm_handle_vblank(dev
, 0);
1433 if (de_iir
& DE_PIPEB_VBLANK
)
1434 drm_handle_vblank(dev
, 1);
1436 if (de_iir
& DE_POISON
)
1437 DRM_ERROR("Poison interrupt\n");
1439 if (de_iir
& DE_PIPEA_FIFO_UNDERRUN
)
1440 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_A
, false))
1441 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1443 if (de_iir
& DE_PIPEB_FIFO_UNDERRUN
)
1444 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_B
, false))
1445 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1447 if (de_iir
& DE_PLANEA_FLIP_DONE
) {
1448 intel_prepare_page_flip(dev
, 0);
1449 intel_finish_page_flip_plane(dev
, 0);
1452 if (de_iir
& DE_PLANEB_FLIP_DONE
) {
1453 intel_prepare_page_flip(dev
, 1);
1454 intel_finish_page_flip_plane(dev
, 1);
1457 /* check event from PCH */
1458 if (de_iir
& DE_PCH_EVENT
) {
1459 u32 pch_iir
= I915_READ(SDEIIR
);
1461 if (HAS_PCH_CPT(dev
))
1462 cpt_irq_handler(dev
, pch_iir
);
1464 ibx_irq_handler(dev
, pch_iir
);
1466 /* should clear PCH hotplug event before clear CPU irq */
1467 I915_WRITE(SDEIIR
, pch_iir
);
1470 if (IS_GEN5(dev
) && de_iir
& DE_PCU_EVENT
)
1471 ironlake_rps_change_irq_handler(dev
);
1474 static void ivb_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
1476 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1479 if (de_iir
& DE_ERR_INT_IVB
)
1480 ivb_err_int_handler(dev
);
1482 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
1483 dp_aux_irq_handler(dev
);
1485 if (de_iir
& DE_GSE_IVB
)
1486 intel_opregion_asle_intr(dev
);
1488 for (i
= 0; i
< 3; i
++) {
1489 if (de_iir
& (DE_PIPEA_VBLANK_IVB
<< (5 * i
)))
1490 drm_handle_vblank(dev
, i
);
1491 if (de_iir
& (DE_PLANEA_FLIP_DONE_IVB
<< (5 * i
))) {
1492 intel_prepare_page_flip(dev
, i
);
1493 intel_finish_page_flip_plane(dev
, i
);
1497 /* check event from PCH */
1498 if (!HAS_PCH_NOP(dev
) && (de_iir
& DE_PCH_EVENT_IVB
)) {
1499 u32 pch_iir
= I915_READ(SDEIIR
);
1501 cpt_irq_handler(dev
, pch_iir
);
1503 /* clear PCH hotplug event before clear CPU irq */
1504 I915_WRITE(SDEIIR
, pch_iir
);
1508 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
1510 struct drm_device
*dev
= (struct drm_device
*) arg
;
1511 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1512 u32 de_iir
, gt_iir
, de_ier
, sde_ier
= 0;
1513 irqreturn_t ret
= IRQ_NONE
;
1515 atomic_inc(&dev_priv
->irq_received
);
1517 /* We get interrupts on unclaimed registers, so check for this before we
1518 * do any I915_{READ,WRITE}. */
1519 intel_uncore_check_errors(dev
);
1521 /* disable master interrupt before clearing iir */
1522 de_ier
= I915_READ(DEIER
);
1523 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
1524 POSTING_READ(DEIER
);
1526 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1527 * interrupts will will be stored on its back queue, and then we'll be
1528 * able to process them after we restore SDEIER (as soon as we restore
1529 * it, we'll get an interrupt if SDEIIR still has something to process
1530 * due to its back queue). */
1531 if (!HAS_PCH_NOP(dev
)) {
1532 sde_ier
= I915_READ(SDEIER
);
1533 I915_WRITE(SDEIER
, 0);
1534 POSTING_READ(SDEIER
);
1537 gt_iir
= I915_READ(GTIIR
);
1539 if (INTEL_INFO(dev
)->gen
>= 6)
1540 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1542 ilk_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1543 I915_WRITE(GTIIR
, gt_iir
);
1547 de_iir
= I915_READ(DEIIR
);
1549 if (INTEL_INFO(dev
)->gen
>= 7)
1550 ivb_display_irq_handler(dev
, de_iir
);
1552 ilk_display_irq_handler(dev
, de_iir
);
1553 I915_WRITE(DEIIR
, de_iir
);
1557 if (INTEL_INFO(dev
)->gen
>= 6) {
1558 u32 pm_iir
= I915_READ(GEN6_PMIIR
);
1560 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1561 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1566 I915_WRITE(DEIER
, de_ier
);
1567 POSTING_READ(DEIER
);
1568 if (!HAS_PCH_NOP(dev
)) {
1569 I915_WRITE(SDEIER
, sde_ier
);
1570 POSTING_READ(SDEIER
);
1576 static void i915_error_wake_up(struct drm_i915_private
*dev_priv
,
1577 bool reset_completed
)
1579 struct intel_ring_buffer
*ring
;
1583 * Notify all waiters for GPU completion events that reset state has
1584 * been changed, and that they need to restart their wait after
1585 * checking for potential errors (and bail out to drop locks if there is
1586 * a gpu reset pending so that i915_error_work_func can acquire them).
1589 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
1590 for_each_ring(ring
, dev_priv
, i
)
1591 wake_up_all(&ring
->irq_queue
);
1593 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
1594 wake_up_all(&dev_priv
->pending_flip_queue
);
1597 * Signal tasks blocked in i915_gem_wait_for_error that the pending
1598 * reset state is cleared.
1600 if (reset_completed
)
1601 wake_up_all(&dev_priv
->gpu_error
.reset_queue
);
1605 * i915_error_work_func - do process context error handling work
1606 * @work: work struct
1608 * Fire an error uevent so userspace can see that a hang or error
1611 static void i915_error_work_func(struct work_struct
*work
)
1613 struct i915_gpu_error
*error
= container_of(work
, struct i915_gpu_error
,
1615 drm_i915_private_t
*dev_priv
= container_of(error
, drm_i915_private_t
,
1617 struct drm_device
*dev
= dev_priv
->dev
;
1618 char *error_event
[] = { I915_ERROR_UEVENT
"=1", NULL
};
1619 char *reset_event
[] = { I915_RESET_UEVENT
"=1", NULL
};
1620 char *reset_done_event
[] = { I915_ERROR_UEVENT
"=0", NULL
};
1623 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
, error_event
);
1626 * Note that there's only one work item which does gpu resets, so we
1627 * need not worry about concurrent gpu resets potentially incrementing
1628 * error->reset_counter twice. We only need to take care of another
1629 * racing irq/hangcheck declaring the gpu dead for a second time. A
1630 * quick check for that is good enough: schedule_work ensures the
1631 * correct ordering between hang detection and this work item, and since
1632 * the reset in-progress bit is only ever set by code outside of this
1633 * work we don't need to worry about any other races.
1635 if (i915_reset_in_progress(error
) && !i915_terminally_wedged(error
)) {
1636 DRM_DEBUG_DRIVER("resetting chip\n");
1637 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
,
1641 * All state reset _must_ be completed before we update the
1642 * reset counter, for otherwise waiters might miss the reset
1643 * pending state and not properly drop locks, resulting in
1644 * deadlocks with the reset work.
1646 ret
= i915_reset(dev
);
1648 intel_display_handle_reset(dev
);
1652 * After all the gem state is reset, increment the reset
1653 * counter and wake up everyone waiting for the reset to
1656 * Since unlock operations are a one-sided barrier only,
1657 * we need to insert a barrier here to order any seqno
1659 * the counter increment.
1661 smp_mb__before_atomic_inc();
1662 atomic_inc(&dev_priv
->gpu_error
.reset_counter
);
1664 kobject_uevent_env(&dev
->primary
->kdev
.kobj
,
1665 KOBJ_CHANGE
, reset_done_event
);
1667 atomic_set(&error
->reset_counter
, I915_WEDGED
);
1671 * Note: The wake_up also serves as a memory barrier so that
1672 * waiters see the update value of the reset counter atomic_t.
1674 i915_error_wake_up(dev_priv
, true);
1678 static void i915_report_and_clear_eir(struct drm_device
*dev
)
1680 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1681 uint32_t instdone
[I915_NUM_INSTDONE_REG
];
1682 u32 eir
= I915_READ(EIR
);
1688 pr_err("render error detected, EIR: 0x%08x\n", eir
);
1690 i915_get_extra_instdone(dev
, instdone
);
1693 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
1694 u32 ipeir
= I915_READ(IPEIR_I965
);
1696 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1697 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1698 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
1699 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
1700 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1701 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1702 I915_WRITE(IPEIR_I965
, ipeir
);
1703 POSTING_READ(IPEIR_I965
);
1705 if (eir
& GM45_ERROR_PAGE_TABLE
) {
1706 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1707 pr_err("page table error\n");
1708 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1709 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1710 POSTING_READ(PGTBL_ER
);
1714 if (!IS_GEN2(dev
)) {
1715 if (eir
& I915_ERROR_PAGE_TABLE
) {
1716 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1717 pr_err("page table error\n");
1718 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1719 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1720 POSTING_READ(PGTBL_ER
);
1724 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
1725 pr_err("memory refresh error:\n");
1727 pr_err("pipe %c stat: 0x%08x\n",
1728 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
1729 /* pipestat has already been acked */
1731 if (eir
& I915_ERROR_INSTRUCTION
) {
1732 pr_err("instruction error\n");
1733 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
1734 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
1735 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
1736 if (INTEL_INFO(dev
)->gen
< 4) {
1737 u32 ipeir
= I915_READ(IPEIR
);
1739 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
1740 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
1741 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
1742 I915_WRITE(IPEIR
, ipeir
);
1743 POSTING_READ(IPEIR
);
1745 u32 ipeir
= I915_READ(IPEIR_I965
);
1747 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1748 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1749 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1750 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1751 I915_WRITE(IPEIR_I965
, ipeir
);
1752 POSTING_READ(IPEIR_I965
);
1756 I915_WRITE(EIR
, eir
);
1758 eir
= I915_READ(EIR
);
1761 * some errors might have become stuck,
1764 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
1765 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
1766 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
1771 * i915_handle_error - handle an error interrupt
1774 * Do some basic checking of regsiter state at error interrupt time and
1775 * dump it to the syslog. Also call i915_capture_error_state() to make
1776 * sure we get a record and make it available in debugfs. Fire a uevent
1777 * so userspace knows something bad happened (should trigger collection
1778 * of a ring dump etc.).
1780 void i915_handle_error(struct drm_device
*dev
, bool wedged
)
1782 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1784 i915_capture_error_state(dev
);
1785 i915_report_and_clear_eir(dev
);
1788 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG
,
1789 &dev_priv
->gpu_error
.reset_counter
);
1792 * Wakeup waiting processes so that the reset work function
1793 * i915_error_work_func doesn't deadlock trying to grab various
1794 * locks. By bumping the reset counter first, the woken
1795 * processes will see a reset in progress and back off,
1796 * releasing their locks and then wait for the reset completion.
1797 * We must do this for _all_ gpu waiters that might hold locks
1798 * that the reset work needs to acquire.
1800 * Note: The wake_up serves as the required memory barrier to
1801 * ensure that the waiters see the updated value of the reset
1804 i915_error_wake_up(dev_priv
, false);
1808 * Our reset work can grab modeset locks (since it needs to reset the
1809 * state of outstanding pagelips). Hence it must not be run on our own
1810 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
1811 * code will deadlock.
1813 schedule_work(&dev_priv
->gpu_error
.work
);
1816 static void __always_unused
i915_pageflip_stall_check(struct drm_device
*dev
, int pipe
)
1818 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1819 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1820 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1821 struct drm_i915_gem_object
*obj
;
1822 struct intel_unpin_work
*work
;
1823 unsigned long flags
;
1824 bool stall_detected
;
1826 /* Ignore early vblank irqs */
1827 if (intel_crtc
== NULL
)
1830 spin_lock_irqsave(&dev
->event_lock
, flags
);
1831 work
= intel_crtc
->unpin_work
;
1834 atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
||
1835 !work
->enable_stall_check
) {
1836 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1837 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1841 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1842 obj
= work
->pending_flip_obj
;
1843 if (INTEL_INFO(dev
)->gen
>= 4) {
1844 int dspsurf
= DSPSURF(intel_crtc
->plane
);
1845 stall_detected
= I915_HI_DISPBASE(I915_READ(dspsurf
)) ==
1846 i915_gem_obj_ggtt_offset(obj
);
1848 int dspaddr
= DSPADDR(intel_crtc
->plane
);
1849 stall_detected
= I915_READ(dspaddr
) == (i915_gem_obj_ggtt_offset(obj
) +
1850 crtc
->y
* crtc
->fb
->pitches
[0] +
1851 crtc
->x
* crtc
->fb
->bits_per_pixel
/8);
1854 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1856 if (stall_detected
) {
1857 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1858 intel_prepare_page_flip(dev
, intel_crtc
->plane
);
1862 /* Called from drm generic code, passed 'crtc' which
1863 * we use as a pipe index
1865 static int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
1867 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1868 unsigned long irqflags
;
1870 if (!i915_pipe_enabled(dev
, pipe
))
1873 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1874 if (INTEL_INFO(dev
)->gen
>= 4)
1875 i915_enable_pipestat(dev_priv
, pipe
,
1876 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1878 i915_enable_pipestat(dev_priv
, pipe
,
1879 PIPE_VBLANK_INTERRUPT_ENABLE
);
1881 /* maintain vblank delivery even in deep C-states */
1882 if (dev_priv
->info
->gen
== 3)
1883 I915_WRITE(INSTPM
, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS
));
1884 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1889 static int ironlake_enable_vblank(struct drm_device
*dev
, int pipe
)
1891 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1892 unsigned long irqflags
;
1893 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
1894 DE_PIPE_VBLANK_ILK(pipe
);
1896 if (!i915_pipe_enabled(dev
, pipe
))
1899 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1900 ironlake_enable_display_irq(dev_priv
, bit
);
1901 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1906 static int valleyview_enable_vblank(struct drm_device
*dev
, int pipe
)
1908 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1909 unsigned long irqflags
;
1912 if (!i915_pipe_enabled(dev
, pipe
))
1915 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1916 imr
= I915_READ(VLV_IMR
);
1918 imr
&= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
1920 imr
&= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1921 I915_WRITE(VLV_IMR
, imr
);
1922 i915_enable_pipestat(dev_priv
, pipe
,
1923 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1924 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1929 /* Called from drm generic code, passed 'crtc' which
1930 * we use as a pipe index
1932 static void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
1934 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1935 unsigned long irqflags
;
1937 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1938 if (dev_priv
->info
->gen
== 3)
1939 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS
));
1941 i915_disable_pipestat(dev_priv
, pipe
,
1942 PIPE_VBLANK_INTERRUPT_ENABLE
|
1943 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1944 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1947 static void ironlake_disable_vblank(struct drm_device
*dev
, int pipe
)
1949 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1950 unsigned long irqflags
;
1951 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
1952 DE_PIPE_VBLANK_ILK(pipe
);
1954 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1955 ironlake_disable_display_irq(dev_priv
, bit
);
1956 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1959 static void valleyview_disable_vblank(struct drm_device
*dev
, int pipe
)
1961 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1962 unsigned long irqflags
;
1965 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1966 i915_disable_pipestat(dev_priv
, pipe
,
1967 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1968 imr
= I915_READ(VLV_IMR
);
1970 imr
|= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
1972 imr
|= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1973 I915_WRITE(VLV_IMR
, imr
);
1974 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1978 ring_last_seqno(struct intel_ring_buffer
*ring
)
1980 return list_entry(ring
->request_list
.prev
,
1981 struct drm_i915_gem_request
, list
)->seqno
;
1985 ring_idle(struct intel_ring_buffer
*ring
, u32 seqno
)
1987 return (list_empty(&ring
->request_list
) ||
1988 i915_seqno_passed(seqno
, ring_last_seqno(ring
)));
1991 static struct intel_ring_buffer
*
1992 semaphore_waits_for(struct intel_ring_buffer
*ring
, u32
*seqno
)
1994 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1995 u32 cmd
, ipehr
, acthd
, acthd_min
;
1997 ipehr
= I915_READ(RING_IPEHR(ring
->mmio_base
));
1998 if ((ipehr
& ~(0x3 << 16)) !=
1999 (MI_SEMAPHORE_MBOX
| MI_SEMAPHORE_COMPARE
| MI_SEMAPHORE_REGISTER
))
2002 /* ACTHD is likely pointing to the dword after the actual command,
2003 * so scan backwards until we find the MBOX.
2005 acthd
= intel_ring_get_active_head(ring
) & HEAD_ADDR
;
2006 acthd_min
= max((int)acthd
- 3 * 4, 0);
2008 cmd
= ioread32(ring
->virtual_start
+ acthd
);
2013 if (acthd
< acthd_min
)
2017 *seqno
= ioread32(ring
->virtual_start
+acthd
+4)+1;
2018 return &dev_priv
->ring
[(ring
->id
+ (((ipehr
>> 17) & 1) + 1)) % 3];
2021 static int semaphore_passed(struct intel_ring_buffer
*ring
)
2023 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2024 struct intel_ring_buffer
*signaller
;
2027 ring
->hangcheck
.deadlock
= true;
2029 signaller
= semaphore_waits_for(ring
, &seqno
);
2030 if (signaller
== NULL
|| signaller
->hangcheck
.deadlock
)
2033 /* cursory check for an unkickable deadlock */
2034 ctl
= I915_READ_CTL(signaller
);
2035 if (ctl
& RING_WAIT_SEMAPHORE
&& semaphore_passed(signaller
) < 0)
2038 return i915_seqno_passed(signaller
->get_seqno(signaller
, false), seqno
);
2041 static void semaphore_clear_deadlocks(struct drm_i915_private
*dev_priv
)
2043 struct intel_ring_buffer
*ring
;
2046 for_each_ring(ring
, dev_priv
, i
)
2047 ring
->hangcheck
.deadlock
= false;
2050 static enum intel_ring_hangcheck_action
2051 ring_stuck(struct intel_ring_buffer
*ring
, u32 acthd
)
2053 struct drm_device
*dev
= ring
->dev
;
2054 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2057 if (ring
->hangcheck
.acthd
!= acthd
)
2058 return HANGCHECK_ACTIVE
;
2061 return HANGCHECK_HUNG
;
2063 /* Is the chip hanging on a WAIT_FOR_EVENT?
2064 * If so we can simply poke the RB_WAIT bit
2065 * and break the hang. This should work on
2066 * all but the second generation chipsets.
2068 tmp
= I915_READ_CTL(ring
);
2069 if (tmp
& RING_WAIT
) {
2070 DRM_ERROR("Kicking stuck wait on %s\n",
2072 i915_handle_error(dev
, false);
2073 I915_WRITE_CTL(ring
, tmp
);
2074 return HANGCHECK_KICK
;
2077 if (INTEL_INFO(dev
)->gen
>= 6 && tmp
& RING_WAIT_SEMAPHORE
) {
2078 switch (semaphore_passed(ring
)) {
2080 return HANGCHECK_HUNG
;
2082 DRM_ERROR("Kicking stuck semaphore on %s\n",
2084 i915_handle_error(dev
, false);
2085 I915_WRITE_CTL(ring
, tmp
);
2086 return HANGCHECK_KICK
;
2088 return HANGCHECK_WAIT
;
2092 return HANGCHECK_HUNG
;
2096 * This is called when the chip hasn't reported back with completed
2097 * batchbuffers in a long time. We keep track per ring seqno progress and
2098 * if there are no progress, hangcheck score for that ring is increased.
2099 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2100 * we kick the ring. If we see no progress on three subsequent calls
2101 * we assume chip is wedged and try to fix it by resetting the chip.
2103 static void i915_hangcheck_elapsed(unsigned long data
)
2105 struct drm_device
*dev
= (struct drm_device
*)data
;
2106 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2107 struct intel_ring_buffer
*ring
;
2109 int busy_count
= 0, rings_hung
= 0;
2110 bool stuck
[I915_NUM_RINGS
] = { 0 };
2116 if (!i915_enable_hangcheck
)
2119 for_each_ring(ring
, dev_priv
, i
) {
2123 semaphore_clear_deadlocks(dev_priv
);
2125 seqno
= ring
->get_seqno(ring
, false);
2126 acthd
= intel_ring_get_active_head(ring
);
2128 if (ring
->hangcheck
.seqno
== seqno
) {
2129 if (ring_idle(ring
, seqno
)) {
2130 ring
->hangcheck
.action
= HANGCHECK_IDLE
;
2132 if (waitqueue_active(&ring
->irq_queue
)) {
2133 /* Issue a wake-up to catch stuck h/w. */
2134 if (!test_and_set_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
)) {
2135 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2137 wake_up_all(&ring
->irq_queue
);
2139 /* Safeguard against driver failure */
2140 ring
->hangcheck
.score
+= BUSY
;
2144 /* We always increment the hangcheck score
2145 * if the ring is busy and still processing
2146 * the same request, so that no single request
2147 * can run indefinitely (such as a chain of
2148 * batches). The only time we do not increment
2149 * the hangcheck score on this ring, if this
2150 * ring is in a legitimate wait for another
2151 * ring. In that case the waiting ring is a
2152 * victim and we want to be sure we catch the
2153 * right culprit. Then every time we do kick
2154 * the ring, add a small increment to the
2155 * score so that we can catch a batch that is
2156 * being repeatedly kicked and so responsible
2157 * for stalling the machine.
2159 ring
->hangcheck
.action
= ring_stuck(ring
,
2162 switch (ring
->hangcheck
.action
) {
2163 case HANGCHECK_IDLE
:
2164 case HANGCHECK_WAIT
:
2166 case HANGCHECK_ACTIVE
:
2167 ring
->hangcheck
.score
+= BUSY
;
2169 case HANGCHECK_KICK
:
2170 ring
->hangcheck
.score
+= KICK
;
2172 case HANGCHECK_HUNG
:
2173 ring
->hangcheck
.score
+= HUNG
;
2179 ring
->hangcheck
.action
= HANGCHECK_ACTIVE
;
2181 /* Gradually reduce the count so that we catch DoS
2182 * attempts across multiple batches.
2184 if (ring
->hangcheck
.score
> 0)
2185 ring
->hangcheck
.score
--;
2188 ring
->hangcheck
.seqno
= seqno
;
2189 ring
->hangcheck
.acthd
= acthd
;
2193 for_each_ring(ring
, dev_priv
, i
) {
2194 if (ring
->hangcheck
.score
> FIRE
) {
2195 DRM_INFO("%s on %s\n",
2196 stuck
[i
] ? "stuck" : "no progress",
2203 return i915_handle_error(dev
, true);
2206 /* Reset timer case chip hangs without another request
2208 i915_queue_hangcheck(dev
);
2211 void i915_queue_hangcheck(struct drm_device
*dev
)
2213 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2214 if (!i915_enable_hangcheck
)
2217 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
2218 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
2221 static void ibx_irq_preinstall(struct drm_device
*dev
)
2223 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2225 if (HAS_PCH_NOP(dev
))
2228 /* south display irq */
2229 I915_WRITE(SDEIMR
, 0xffffffff);
2231 * SDEIER is also touched by the interrupt handler to work around missed
2232 * PCH interrupts. Hence we can't update it after the interrupt handler
2233 * is enabled - instead we unconditionally enable all PCH interrupt
2234 * sources here, but then only unmask them as needed with SDEIMR.
2236 I915_WRITE(SDEIER
, 0xffffffff);
2237 POSTING_READ(SDEIER
);
2240 static void gen5_gt_irq_preinstall(struct drm_device
*dev
)
2242 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2245 I915_WRITE(GTIMR
, 0xffffffff);
2246 I915_WRITE(GTIER
, 0x0);
2247 POSTING_READ(GTIER
);
2249 if (INTEL_INFO(dev
)->gen
>= 6) {
2251 I915_WRITE(GEN6_PMIMR
, 0xffffffff);
2252 I915_WRITE(GEN6_PMIER
, 0x0);
2253 POSTING_READ(GEN6_PMIER
);
2259 static void ironlake_irq_preinstall(struct drm_device
*dev
)
2261 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2263 atomic_set(&dev_priv
->irq_received
, 0);
2265 I915_WRITE(HWSTAM
, 0xeffe);
2267 I915_WRITE(DEIMR
, 0xffffffff);
2268 I915_WRITE(DEIER
, 0x0);
2269 POSTING_READ(DEIER
);
2271 gen5_gt_irq_preinstall(dev
);
2273 ibx_irq_preinstall(dev
);
2276 static void valleyview_irq_preinstall(struct drm_device
*dev
)
2278 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2281 atomic_set(&dev_priv
->irq_received
, 0);
2284 I915_WRITE(VLV_IMR
, 0);
2285 I915_WRITE(RING_IMR(RENDER_RING_BASE
), 0);
2286 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE
), 0);
2287 I915_WRITE(RING_IMR(BLT_RING_BASE
), 0);
2290 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2291 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2293 gen5_gt_irq_preinstall(dev
);
2295 I915_WRITE(DPINVGTT
, 0xff);
2297 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2298 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2300 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2301 I915_WRITE(VLV_IIR
, 0xffffffff);
2302 I915_WRITE(VLV_IMR
, 0xffffffff);
2303 I915_WRITE(VLV_IER
, 0x0);
2304 POSTING_READ(VLV_IER
);
2307 static void ibx_hpd_irq_setup(struct drm_device
*dev
)
2309 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2310 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2311 struct intel_encoder
*intel_encoder
;
2312 u32 hotplug_irqs
, hotplug
, enabled_irqs
= 0;
2314 if (HAS_PCH_IBX(dev
)) {
2315 hotplug_irqs
= SDE_HOTPLUG_MASK
;
2316 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2317 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2318 enabled_irqs
|= hpd_ibx
[intel_encoder
->hpd_pin
];
2320 hotplug_irqs
= SDE_HOTPLUG_MASK_CPT
;
2321 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2322 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2323 enabled_irqs
|= hpd_cpt
[intel_encoder
->hpd_pin
];
2326 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
2329 * Enable digital hotplug on the PCH, and configure the DP short pulse
2330 * duration to 2ms (which is the minimum in the Display Port spec)
2332 * This register is the same on all known PCH chips.
2334 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
2335 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
2336 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
2337 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
2338 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
2339 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
2342 static void ibx_irq_postinstall(struct drm_device
*dev
)
2344 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2347 if (HAS_PCH_NOP(dev
))
2350 if (HAS_PCH_IBX(dev
)) {
2351 mask
= SDE_GMBUS
| SDE_AUX_MASK
| SDE_TRANSB_FIFO_UNDER
|
2352 SDE_TRANSA_FIFO_UNDER
| SDE_POISON
;
2354 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
| SDE_ERROR_CPT
;
2356 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2359 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2360 I915_WRITE(SDEIMR
, ~mask
);
2363 static void gen5_gt_irq_postinstall(struct drm_device
*dev
)
2365 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2366 u32 pm_irqs
, gt_irqs
;
2368 pm_irqs
= gt_irqs
= 0;
2370 dev_priv
->gt_irq_mask
= ~0;
2371 if (HAS_L3_DPF(dev
)) {
2372 /* L3 parity interrupt is always unmasked. */
2373 dev_priv
->gt_irq_mask
= ~GT_PARITY_ERROR(dev
);
2374 gt_irqs
|= GT_PARITY_ERROR(dev
);
2377 gt_irqs
|= GT_RENDER_USER_INTERRUPT
;
2379 gt_irqs
|= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
|
2380 ILK_BSD_USER_INTERRUPT
;
2382 gt_irqs
|= GT_BLT_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
;
2385 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2386 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
2387 I915_WRITE(GTIER
, gt_irqs
);
2388 POSTING_READ(GTIER
);
2390 if (INTEL_INFO(dev
)->gen
>= 6) {
2391 pm_irqs
|= GEN6_PM_RPS_EVENTS
;
2394 pm_irqs
|= PM_VEBOX_USER_INTERRUPT
;
2396 dev_priv
->pm_irq_mask
= 0xffffffff;
2397 I915_WRITE(GEN6_PMIIR
, I915_READ(GEN6_PMIIR
));
2398 I915_WRITE(GEN6_PMIMR
, dev_priv
->pm_irq_mask
);
2399 I915_WRITE(GEN6_PMIER
, pm_irqs
);
2400 POSTING_READ(GEN6_PMIER
);
2404 static int ironlake_irq_postinstall(struct drm_device
*dev
)
2406 unsigned long irqflags
;
2407 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2408 u32 display_mask
, extra_mask
;
2410 if (INTEL_INFO(dev
)->gen
>= 7) {
2411 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
|
2412 DE_PCH_EVENT_IVB
| DE_PLANEC_FLIP_DONE_IVB
|
2413 DE_PLANEB_FLIP_DONE_IVB
|
2414 DE_PLANEA_FLIP_DONE_IVB
| DE_AUX_CHANNEL_A_IVB
|
2416 extra_mask
= (DE_PIPEC_VBLANK_IVB
| DE_PIPEB_VBLANK_IVB
|
2417 DE_PIPEA_VBLANK_IVB
);
2419 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2421 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
2422 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
|
2423 DE_AUX_CHANNEL_A
| DE_PIPEB_FIFO_UNDERRUN
|
2424 DE_PIPEA_FIFO_UNDERRUN
| DE_POISON
);
2425 extra_mask
= DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
| DE_PCU_EVENT
;
2428 dev_priv
->irq_mask
= ~display_mask
;
2430 /* should always can generate irq */
2431 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2432 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
2433 I915_WRITE(DEIER
, display_mask
| extra_mask
);
2434 POSTING_READ(DEIER
);
2436 gen5_gt_irq_postinstall(dev
);
2438 ibx_irq_postinstall(dev
);
2440 if (IS_IRONLAKE_M(dev
)) {
2441 /* Enable PCU event interrupts
2443 * spinlocking not required here for correctness since interrupt
2444 * setup is guaranteed to run in single-threaded context. But we
2445 * need it to make the assert_spin_locked happy. */
2446 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2447 ironlake_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
2448 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2454 static int valleyview_irq_postinstall(struct drm_device
*dev
)
2456 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2458 u32 pipestat_enable
= PLANE_FLIP_DONE_INT_EN_VLV
;
2459 unsigned long irqflags
;
2461 enable_mask
= I915_DISPLAY_PORT_INTERRUPT
;
2462 enable_mask
|= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2463 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2464 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2465 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2468 *Leave vblank interrupts masked initially. enable/disable will
2469 * toggle them based on usage.
2471 dev_priv
->irq_mask
= (~enable_mask
) |
2472 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2473 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2475 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2476 POSTING_READ(PORT_HOTPLUG_EN
);
2478 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
2479 I915_WRITE(VLV_IER
, enable_mask
);
2480 I915_WRITE(VLV_IIR
, 0xffffffff);
2481 I915_WRITE(PIPESTAT(0), 0xffff);
2482 I915_WRITE(PIPESTAT(1), 0xffff);
2483 POSTING_READ(VLV_IER
);
2485 /* Interrupt setup is already guaranteed to be single-threaded, this is
2486 * just to make the assert_spin_locked check happy. */
2487 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2488 i915_enable_pipestat(dev_priv
, 0, pipestat_enable
);
2489 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
2490 i915_enable_pipestat(dev_priv
, 1, pipestat_enable
);
2491 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2493 I915_WRITE(VLV_IIR
, 0xffffffff);
2494 I915_WRITE(VLV_IIR
, 0xffffffff);
2496 gen5_gt_irq_postinstall(dev
);
2498 /* ack & enable invalid PTE error interrupts */
2499 #if 0 /* FIXME: add support to irq handler for checking these bits */
2500 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
2501 I915_WRITE(DPINVGTT
, DPINVGTT_EN_MASK
);
2504 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
2509 static void valleyview_irq_uninstall(struct drm_device
*dev
)
2511 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2517 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2520 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2522 I915_WRITE(HWSTAM
, 0xffffffff);
2523 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2524 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2526 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2527 I915_WRITE(VLV_IIR
, 0xffffffff);
2528 I915_WRITE(VLV_IMR
, 0xffffffff);
2529 I915_WRITE(VLV_IER
, 0x0);
2530 POSTING_READ(VLV_IER
);
2533 static void ironlake_irq_uninstall(struct drm_device
*dev
)
2535 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2540 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2542 I915_WRITE(HWSTAM
, 0xffffffff);
2544 I915_WRITE(DEIMR
, 0xffffffff);
2545 I915_WRITE(DEIER
, 0x0);
2546 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2548 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2550 I915_WRITE(GTIMR
, 0xffffffff);
2551 I915_WRITE(GTIER
, 0x0);
2552 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2554 if (HAS_PCH_NOP(dev
))
2557 I915_WRITE(SDEIMR
, 0xffffffff);
2558 I915_WRITE(SDEIER
, 0x0);
2559 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2560 if (HAS_PCH_CPT(dev
) || HAS_PCH_LPT(dev
))
2561 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2564 static void i8xx_irq_preinstall(struct drm_device
* dev
)
2566 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2569 atomic_set(&dev_priv
->irq_received
, 0);
2572 I915_WRITE(PIPESTAT(pipe
), 0);
2573 I915_WRITE16(IMR
, 0xffff);
2574 I915_WRITE16(IER
, 0x0);
2575 POSTING_READ16(IER
);
2578 static int i8xx_irq_postinstall(struct drm_device
*dev
)
2580 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2583 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2585 /* Unmask the interrupts that we always want on. */
2586 dev_priv
->irq_mask
=
2587 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2588 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2589 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2590 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2591 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2592 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
2595 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2596 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2597 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2598 I915_USER_INTERRUPT
);
2599 POSTING_READ16(IER
);
2605 * Returns true when a page flip has completed.
2607 static bool i8xx_handle_vblank(struct drm_device
*dev
,
2610 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2611 u16 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(pipe
);
2613 if (!drm_handle_vblank(dev
, pipe
))
2616 if ((iir
& flip_pending
) == 0)
2619 intel_prepare_page_flip(dev
, pipe
);
2621 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2622 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2623 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2624 * the flip is completed (no longer pending). Since this doesn't raise
2625 * an interrupt per se, we watch for the change at vblank.
2627 if (I915_READ16(ISR
) & flip_pending
)
2630 intel_finish_page_flip(dev
, pipe
);
2635 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
2637 struct drm_device
*dev
= (struct drm_device
*) arg
;
2638 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2641 unsigned long irqflags
;
2644 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2645 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2647 atomic_inc(&dev_priv
->irq_received
);
2649 iir
= I915_READ16(IIR
);
2653 while (iir
& ~flip_mask
) {
2654 /* Can't rely on pipestat interrupt bit in iir as it might
2655 * have been cleared after the pipestat interrupt was received.
2656 * It doesn't set the bit in iir again, but it still produces
2657 * interrupts (for non-MSI).
2659 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2660 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2661 i915_handle_error(dev
, false);
2663 for_each_pipe(pipe
) {
2664 int reg
= PIPESTAT(pipe
);
2665 pipe_stats
[pipe
] = I915_READ(reg
);
2668 * Clear the PIPE*STAT regs before the IIR
2670 if (pipe_stats
[pipe
] & 0x8000ffff) {
2671 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2672 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2674 I915_WRITE(reg
, pipe_stats
[pipe
]);
2677 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2679 I915_WRITE16(IIR
, iir
& ~flip_mask
);
2680 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
2682 i915_update_dri1_breadcrumb(dev
);
2684 if (iir
& I915_USER_INTERRUPT
)
2685 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2687 if (pipe_stats
[0] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2688 i8xx_handle_vblank(dev
, 0, iir
))
2689 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(0);
2691 if (pipe_stats
[1] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2692 i8xx_handle_vblank(dev
, 1, iir
))
2693 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(1);
2701 static void i8xx_irq_uninstall(struct drm_device
* dev
)
2703 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2706 for_each_pipe(pipe
) {
2707 /* Clear enable bits; then clear status bits */
2708 I915_WRITE(PIPESTAT(pipe
), 0);
2709 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
2711 I915_WRITE16(IMR
, 0xffff);
2712 I915_WRITE16(IER
, 0x0);
2713 I915_WRITE16(IIR
, I915_READ16(IIR
));
2716 static void i915_irq_preinstall(struct drm_device
* dev
)
2718 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2721 atomic_set(&dev_priv
->irq_received
, 0);
2723 if (I915_HAS_HOTPLUG(dev
)) {
2724 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2725 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2728 I915_WRITE16(HWSTAM
, 0xeffe);
2730 I915_WRITE(PIPESTAT(pipe
), 0);
2731 I915_WRITE(IMR
, 0xffffffff);
2732 I915_WRITE(IER
, 0x0);
2736 static int i915_irq_postinstall(struct drm_device
*dev
)
2738 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2741 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2743 /* Unmask the interrupts that we always want on. */
2744 dev_priv
->irq_mask
=
2745 ~(I915_ASLE_INTERRUPT
|
2746 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2747 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2748 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2749 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2750 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2753 I915_ASLE_INTERRUPT
|
2754 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2755 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2756 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2757 I915_USER_INTERRUPT
;
2759 if (I915_HAS_HOTPLUG(dev
)) {
2760 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2761 POSTING_READ(PORT_HOTPLUG_EN
);
2763 /* Enable in IER... */
2764 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
2765 /* and unmask in IMR */
2766 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
2769 I915_WRITE(IMR
, dev_priv
->irq_mask
);
2770 I915_WRITE(IER
, enable_mask
);
2773 i915_enable_asle_pipestat(dev
);
2779 * Returns true when a page flip has completed.
2781 static bool i915_handle_vblank(struct drm_device
*dev
,
2782 int plane
, int pipe
, u32 iir
)
2784 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2785 u32 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
2787 if (!drm_handle_vblank(dev
, pipe
))
2790 if ((iir
& flip_pending
) == 0)
2793 intel_prepare_page_flip(dev
, plane
);
2795 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2796 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2797 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2798 * the flip is completed (no longer pending). Since this doesn't raise
2799 * an interrupt per se, we watch for the change at vblank.
2801 if (I915_READ(ISR
) & flip_pending
)
2804 intel_finish_page_flip(dev
, pipe
);
2809 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
2811 struct drm_device
*dev
= (struct drm_device
*) arg
;
2812 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2813 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
2814 unsigned long irqflags
;
2816 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2817 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2818 int pipe
, ret
= IRQ_NONE
;
2820 atomic_inc(&dev_priv
->irq_received
);
2822 iir
= I915_READ(IIR
);
2824 bool irq_received
= (iir
& ~flip_mask
) != 0;
2825 bool blc_event
= false;
2827 /* Can't rely on pipestat interrupt bit in iir as it might
2828 * have been cleared after the pipestat interrupt was received.
2829 * It doesn't set the bit in iir again, but it still produces
2830 * interrupts (for non-MSI).
2832 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2833 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2834 i915_handle_error(dev
, false);
2836 for_each_pipe(pipe
) {
2837 int reg
= PIPESTAT(pipe
);
2838 pipe_stats
[pipe
] = I915_READ(reg
);
2840 /* Clear the PIPE*STAT regs before the IIR */
2841 if (pipe_stats
[pipe
] & 0x8000ffff) {
2842 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2843 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2845 I915_WRITE(reg
, pipe_stats
[pipe
]);
2846 irq_received
= true;
2849 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2854 /* Consume port. Then clear IIR or we'll miss events */
2855 if ((I915_HAS_HOTPLUG(dev
)) &&
2856 (iir
& I915_DISPLAY_PORT_INTERRUPT
)) {
2857 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
2858 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
2860 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2863 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
2865 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
2866 POSTING_READ(PORT_HOTPLUG_STAT
);
2869 I915_WRITE(IIR
, iir
& ~flip_mask
);
2870 new_iir
= I915_READ(IIR
); /* Flush posted writes */
2872 if (iir
& I915_USER_INTERRUPT
)
2873 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2875 for_each_pipe(pipe
) {
2880 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2881 i915_handle_vblank(dev
, plane
, pipe
, iir
))
2882 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
2884 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
2888 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
2889 intel_opregion_asle_intr(dev
);
2891 /* With MSI, interrupts are only generated when iir
2892 * transitions from zero to nonzero. If another bit got
2893 * set while we were handling the existing iir bits, then
2894 * we would never get another interrupt.
2896 * This is fine on non-MSI as well, as if we hit this path
2897 * we avoid exiting the interrupt handler only to generate
2900 * Note that for MSI this could cause a stray interrupt report
2901 * if an interrupt landed in the time between writing IIR and
2902 * the posting read. This should be rare enough to never
2903 * trigger the 99% of 100,000 interrupts test for disabling
2908 } while (iir
& ~flip_mask
);
2910 i915_update_dri1_breadcrumb(dev
);
2915 static void i915_irq_uninstall(struct drm_device
* dev
)
2917 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2920 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2922 if (I915_HAS_HOTPLUG(dev
)) {
2923 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2924 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2927 I915_WRITE16(HWSTAM
, 0xffff);
2928 for_each_pipe(pipe
) {
2929 /* Clear enable bits; then clear status bits */
2930 I915_WRITE(PIPESTAT(pipe
), 0);
2931 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
2933 I915_WRITE(IMR
, 0xffffffff);
2934 I915_WRITE(IER
, 0x0);
2936 I915_WRITE(IIR
, I915_READ(IIR
));
2939 static void i965_irq_preinstall(struct drm_device
* dev
)
2941 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2944 atomic_set(&dev_priv
->irq_received
, 0);
2946 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2947 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2949 I915_WRITE(HWSTAM
, 0xeffe);
2951 I915_WRITE(PIPESTAT(pipe
), 0);
2952 I915_WRITE(IMR
, 0xffffffff);
2953 I915_WRITE(IER
, 0x0);
2957 static int i965_irq_postinstall(struct drm_device
*dev
)
2959 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2962 unsigned long irqflags
;
2964 /* Unmask the interrupts that we always want on. */
2965 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
2966 I915_DISPLAY_PORT_INTERRUPT
|
2967 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2968 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2969 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2970 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2971 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2973 enable_mask
= ~dev_priv
->irq_mask
;
2974 enable_mask
&= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2975 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
2976 enable_mask
|= I915_USER_INTERRUPT
;
2979 enable_mask
|= I915_BSD_USER_INTERRUPT
;
2981 /* Interrupt setup is already guaranteed to be single-threaded, this is
2982 * just to make the assert_spin_locked check happy. */
2983 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2984 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
2985 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2988 * Enable some error detection, note the instruction error mask
2989 * bit is reserved, so we leave it masked.
2992 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
2993 GM45_ERROR_MEM_PRIV
|
2994 GM45_ERROR_CP_PRIV
|
2995 I915_ERROR_MEMORY_REFRESH
);
2997 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
2998 I915_ERROR_MEMORY_REFRESH
);
3000 I915_WRITE(EMR
, error_mask
);
3002 I915_WRITE(IMR
, dev_priv
->irq_mask
);
3003 I915_WRITE(IER
, enable_mask
);
3006 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3007 POSTING_READ(PORT_HOTPLUG_EN
);
3009 i915_enable_asle_pipestat(dev
);
3014 static void i915_hpd_irq_setup(struct drm_device
*dev
)
3016 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3017 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3018 struct intel_encoder
*intel_encoder
;
3021 assert_spin_locked(&dev_priv
->irq_lock
);
3023 if (I915_HAS_HOTPLUG(dev
)) {
3024 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
3025 hotplug_en
&= ~HOTPLUG_INT_EN_MASK
;
3026 /* Note HDMI and DP share hotplug bits */
3027 /* enable bits are the same for all generations */
3028 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
3029 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
3030 hotplug_en
|= hpd_mask_i915
[intel_encoder
->hpd_pin
];
3031 /* Programming the CRT detection parameters tends
3032 to generate a spurious hotplug event about three
3033 seconds later. So just do it once.
3036 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
3037 hotplug_en
&= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK
;
3038 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
3040 /* Ignore TV since it's buggy */
3041 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
3045 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
3047 struct drm_device
*dev
= (struct drm_device
*) arg
;
3048 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3050 u32 pipe_stats
[I915_MAX_PIPES
];
3051 unsigned long irqflags
;
3053 int ret
= IRQ_NONE
, pipe
;
3055 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
3056 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
3058 atomic_inc(&dev_priv
->irq_received
);
3060 iir
= I915_READ(IIR
);
3063 bool blc_event
= false;
3065 irq_received
= (iir
& ~flip_mask
) != 0;
3067 /* Can't rely on pipestat interrupt bit in iir as it might
3068 * have been cleared after the pipestat interrupt was received.
3069 * It doesn't set the bit in iir again, but it still produces
3070 * interrupts (for non-MSI).
3072 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3073 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
3074 i915_handle_error(dev
, false);
3076 for_each_pipe(pipe
) {
3077 int reg
= PIPESTAT(pipe
);
3078 pipe_stats
[pipe
] = I915_READ(reg
);
3081 * Clear the PIPE*STAT regs before the IIR
3083 if (pipe_stats
[pipe
] & 0x8000ffff) {
3084 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
3085 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3087 I915_WRITE(reg
, pipe_stats
[pipe
]);
3091 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3098 /* Consume port. Then clear IIR or we'll miss events */
3099 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
3100 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
3101 u32 hotplug_trigger
= hotplug_status
& (IS_G4X(dev
) ?
3102 HOTPLUG_INT_STATUS_G4X
:
3103 HOTPLUG_INT_STATUS_I915
);
3105 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3108 intel_hpd_irq_handler(dev
, hotplug_trigger
,
3109 IS_G4X(dev
) ? hpd_status_gen4
: hpd_status_i915
);
3111 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
3112 I915_READ(PORT_HOTPLUG_STAT
);
3115 I915_WRITE(IIR
, iir
& ~flip_mask
);
3116 new_iir
= I915_READ(IIR
); /* Flush posted writes */
3118 if (iir
& I915_USER_INTERRUPT
)
3119 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
3120 if (iir
& I915_BSD_USER_INTERRUPT
)
3121 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
3123 for_each_pipe(pipe
) {
3124 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
3125 i915_handle_vblank(dev
, pipe
, pipe
, iir
))
3126 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
3128 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
3133 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
3134 intel_opregion_asle_intr(dev
);
3136 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
3137 gmbus_irq_handler(dev
);
3139 /* With MSI, interrupts are only generated when iir
3140 * transitions from zero to nonzero. If another bit got
3141 * set while we were handling the existing iir bits, then
3142 * we would never get another interrupt.
3144 * This is fine on non-MSI as well, as if we hit this path
3145 * we avoid exiting the interrupt handler only to generate
3148 * Note that for MSI this could cause a stray interrupt report
3149 * if an interrupt landed in the time between writing IIR and
3150 * the posting read. This should be rare enough to never
3151 * trigger the 99% of 100,000 interrupts test for disabling
3157 i915_update_dri1_breadcrumb(dev
);
3162 static void i965_irq_uninstall(struct drm_device
* dev
)
3164 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3170 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
3172 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3173 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3175 I915_WRITE(HWSTAM
, 0xffffffff);
3177 I915_WRITE(PIPESTAT(pipe
), 0);
3178 I915_WRITE(IMR
, 0xffffffff);
3179 I915_WRITE(IER
, 0x0);
3182 I915_WRITE(PIPESTAT(pipe
),
3183 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
3184 I915_WRITE(IIR
, I915_READ(IIR
));
3187 static void i915_reenable_hotplug_timer_func(unsigned long data
)
3189 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*)data
;
3190 struct drm_device
*dev
= dev_priv
->dev
;
3191 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3192 unsigned long irqflags
;
3195 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3196 for (i
= (HPD_NONE
+ 1); i
< HPD_NUM_PINS
; i
++) {
3197 struct drm_connector
*connector
;
3199 if (dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_DISABLED
)
3202 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3204 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3205 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3207 if (intel_connector
->encoder
->hpd_pin
== i
) {
3208 if (connector
->polled
!= intel_connector
->polled
)
3209 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3210 drm_get_connector_name(connector
));
3211 connector
->polled
= intel_connector
->polled
;
3212 if (!connector
->polled
)
3213 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3217 if (dev_priv
->display
.hpd_irq_setup
)
3218 dev_priv
->display
.hpd_irq_setup(dev
);
3219 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3222 void intel_irq_init(struct drm_device
*dev
)
3224 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3226 INIT_WORK(&dev_priv
->hotplug_work
, i915_hotplug_work_func
);
3227 INIT_WORK(&dev_priv
->gpu_error
.work
, i915_error_work_func
);
3228 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
3229 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
3231 setup_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
3232 i915_hangcheck_elapsed
,
3233 (unsigned long) dev
);
3234 setup_timer(&dev_priv
->hotplug_reenable_timer
, i915_reenable_hotplug_timer_func
,
3235 (unsigned long) dev_priv
);
3237 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
, PM_QOS_DEFAULT_VALUE
);
3239 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
3240 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
3241 dev
->driver
->get_vblank_counter
= gm45_get_vblank_counter
;
3243 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
3244 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
3247 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
3248 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
3249 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
3252 if (IS_VALLEYVIEW(dev
)) {
3253 dev
->driver
->irq_handler
= valleyview_irq_handler
;
3254 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
3255 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
3256 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
3257 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
3258 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
3259 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3260 } else if (HAS_PCH_SPLIT(dev
)) {
3261 dev
->driver
->irq_handler
= ironlake_irq_handler
;
3262 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
3263 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
3264 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
3265 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
3266 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
3267 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
3269 if (INTEL_INFO(dev
)->gen
== 2) {
3270 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
3271 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
3272 dev
->driver
->irq_handler
= i8xx_irq_handler
;
3273 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
3274 } else if (INTEL_INFO(dev
)->gen
== 3) {
3275 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
3276 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
3277 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
3278 dev
->driver
->irq_handler
= i915_irq_handler
;
3279 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3281 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
3282 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
3283 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
3284 dev
->driver
->irq_handler
= i965_irq_handler
;
3285 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3287 dev
->driver
->enable_vblank
= i915_enable_vblank
;
3288 dev
->driver
->disable_vblank
= i915_disable_vblank
;
3292 void intel_hpd_init(struct drm_device
*dev
)
3294 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3295 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3296 struct drm_connector
*connector
;
3297 unsigned long irqflags
;
3300 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
3301 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
3302 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3304 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3305 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3306 connector
->polled
= intel_connector
->polled
;
3307 if (!connector
->polled
&& I915_HAS_HOTPLUG(dev
) && intel_connector
->encoder
->hpd_pin
> HPD_NONE
)
3308 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3311 /* Interrupt setup is already guaranteed to be single-threaded, this is
3312 * just to make the assert_spin_locked checks happy. */
3313 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3314 if (dev_priv
->display
.hpd_irq_setup
)
3315 dev_priv
->display
.hpd_irq_setup(dev
);
3316 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3319 /* Disable interrupts so we can allow Package C8+. */
3320 void hsw_pc8_disable_interrupts(struct drm_device
*dev
)
3322 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3323 unsigned long irqflags
;
3325 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3327 dev_priv
->pc8
.regsave
.deimr
= I915_READ(DEIMR
);
3328 dev_priv
->pc8
.regsave
.sdeimr
= I915_READ(SDEIMR
);
3329 dev_priv
->pc8
.regsave
.gtimr
= I915_READ(GTIMR
);
3330 dev_priv
->pc8
.regsave
.gtier
= I915_READ(GTIER
);
3331 dev_priv
->pc8
.regsave
.gen6_pmimr
= I915_READ(GEN6_PMIMR
);
3333 ironlake_disable_display_irq(dev_priv
, ~DE_PCH_EVENT_IVB
);
3334 ibx_disable_display_interrupt(dev_priv
, ~SDE_HOTPLUG_MASK_CPT
);
3335 ilk_disable_gt_irq(dev_priv
, 0xffffffff);
3336 snb_disable_pm_irq(dev_priv
, 0xffffffff);
3338 dev_priv
->pc8
.irqs_disabled
= true;
3340 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3343 /* Restore interrupts so we can recover from Package C8+. */
3344 void hsw_pc8_restore_interrupts(struct drm_device
*dev
)
3346 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3347 unsigned long irqflags
;
3348 uint32_t val
, expected
;
3350 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3352 val
= I915_READ(DEIMR
);
3353 expected
= ~DE_PCH_EVENT_IVB
;
3354 WARN(val
!= expected
, "DEIMR is 0x%08x, not 0x%08x\n", val
, expected
);
3356 val
= I915_READ(SDEIMR
) & ~SDE_HOTPLUG_MASK_CPT
;
3357 expected
= ~SDE_HOTPLUG_MASK_CPT
;
3358 WARN(val
!= expected
, "SDEIMR non-HPD bits are 0x%08x, not 0x%08x\n",
3361 val
= I915_READ(GTIMR
);
3362 expected
= 0xffffffff;
3363 WARN(val
!= expected
, "GTIMR is 0x%08x, not 0x%08x\n", val
, expected
);
3365 val
= I915_READ(GEN6_PMIMR
);
3366 expected
= 0xffffffff;
3367 WARN(val
!= expected
, "GEN6_PMIMR is 0x%08x, not 0x%08x\n", val
,
3370 dev_priv
->pc8
.irqs_disabled
= false;
3372 ironlake_enable_display_irq(dev_priv
, ~dev_priv
->pc8
.regsave
.deimr
);
3373 ibx_enable_display_interrupt(dev_priv
,
3374 ~dev_priv
->pc8
.regsave
.sdeimr
&
3375 ~SDE_HOTPLUG_MASK_CPT
);
3376 ilk_enable_gt_irq(dev_priv
, ~dev_priv
->pc8
.regsave
.gtimr
);
3377 snb_enable_pm_irq(dev_priv
, ~dev_priv
->pc8
.regsave
.gen6_pmimr
);
3378 I915_WRITE(GTIER
, dev_priv
->pc8
.regsave
.gtier
);
3380 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);