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drm/i915: fix HW lockup due to missing RPS IRQ workaround on GEN6
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
34 #include <drm/drmP.h>
35 #include <drm/i915_drm.h>
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "intel_drv.h"
39
40 /**
41 * DOC: interrupt handling
42 *
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
46 */
47
48 static const u32 hpd_ibx[] = {
49 [HPD_CRT] = SDE_CRT_HOTPLUG,
50 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
51 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
52 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
53 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
54 };
55
56 static const u32 hpd_cpt[] = {
57 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
58 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
59 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
60 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
61 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
62 };
63
64 static const u32 hpd_mask_i915[] = {
65 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
66 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
67 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
68 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
69 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
70 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
71 };
72
73 static const u32 hpd_status_g4x[] = {
74 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
75 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
76 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
77 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
78 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
79 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
80 };
81
82 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
83 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
84 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
85 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
86 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
87 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
88 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
89 };
90
91 /* IIR can theoretically queue up two events. Be paranoid. */
92 #define GEN8_IRQ_RESET_NDX(type, which) do { \
93 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
94 POSTING_READ(GEN8_##type##_IMR(which)); \
95 I915_WRITE(GEN8_##type##_IER(which), 0); \
96 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
97 POSTING_READ(GEN8_##type##_IIR(which)); \
98 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
99 POSTING_READ(GEN8_##type##_IIR(which)); \
100 } while (0)
101
102 #define GEN5_IRQ_RESET(type) do { \
103 I915_WRITE(type##IMR, 0xffffffff); \
104 POSTING_READ(type##IMR); \
105 I915_WRITE(type##IER, 0); \
106 I915_WRITE(type##IIR, 0xffffffff); \
107 POSTING_READ(type##IIR); \
108 I915_WRITE(type##IIR, 0xffffffff); \
109 POSTING_READ(type##IIR); \
110 } while (0)
111
112 /*
113 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
114 */
115 #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
116 u32 val = I915_READ(reg); \
117 if (val) { \
118 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
119 (reg), val); \
120 I915_WRITE((reg), 0xffffffff); \
121 POSTING_READ(reg); \
122 I915_WRITE((reg), 0xffffffff); \
123 POSTING_READ(reg); \
124 } \
125 } while (0)
126
127 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
128 GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
129 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
130 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
131 POSTING_READ(GEN8_##type##_IMR(which)); \
132 } while (0)
133
134 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
135 GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
136 I915_WRITE(type##IER, (ier_val)); \
137 I915_WRITE(type##IMR, (imr_val)); \
138 POSTING_READ(type##IMR); \
139 } while (0)
140
141 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
142
143 /* For display hotplug interrupt */
144 void
145 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
146 {
147 assert_spin_locked(&dev_priv->irq_lock);
148
149 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
150 return;
151
152 if ((dev_priv->irq_mask & mask) != 0) {
153 dev_priv->irq_mask &= ~mask;
154 I915_WRITE(DEIMR, dev_priv->irq_mask);
155 POSTING_READ(DEIMR);
156 }
157 }
158
159 void
160 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
161 {
162 assert_spin_locked(&dev_priv->irq_lock);
163
164 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
165 return;
166
167 if ((dev_priv->irq_mask & mask) != mask) {
168 dev_priv->irq_mask |= mask;
169 I915_WRITE(DEIMR, dev_priv->irq_mask);
170 POSTING_READ(DEIMR);
171 }
172 }
173
174 /**
175 * ilk_update_gt_irq - update GTIMR
176 * @dev_priv: driver private
177 * @interrupt_mask: mask of interrupt bits to update
178 * @enabled_irq_mask: mask of interrupt bits to enable
179 */
180 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
181 uint32_t interrupt_mask,
182 uint32_t enabled_irq_mask)
183 {
184 assert_spin_locked(&dev_priv->irq_lock);
185
186 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
187 return;
188
189 dev_priv->gt_irq_mask &= ~interrupt_mask;
190 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
191 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
192 POSTING_READ(GTIMR);
193 }
194
195 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
196 {
197 ilk_update_gt_irq(dev_priv, mask, mask);
198 }
199
200 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
201 {
202 ilk_update_gt_irq(dev_priv, mask, 0);
203 }
204
205 static u32 gen6_pm_iir(struct drm_i915_private *dev_priv)
206 {
207 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
208 }
209
210 static u32 gen6_pm_imr(struct drm_i915_private *dev_priv)
211 {
212 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
213 }
214
215 static u32 gen6_pm_ier(struct drm_i915_private *dev_priv)
216 {
217 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
218 }
219
220 /**
221 * snb_update_pm_irq - update GEN6_PMIMR
222 * @dev_priv: driver private
223 * @interrupt_mask: mask of interrupt bits to update
224 * @enabled_irq_mask: mask of interrupt bits to enable
225 */
226 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
227 uint32_t interrupt_mask,
228 uint32_t enabled_irq_mask)
229 {
230 uint32_t new_val;
231
232 assert_spin_locked(&dev_priv->irq_lock);
233
234 new_val = dev_priv->pm_irq_mask;
235 new_val &= ~interrupt_mask;
236 new_val |= (~enabled_irq_mask & interrupt_mask);
237
238 if (new_val != dev_priv->pm_irq_mask) {
239 dev_priv->pm_irq_mask = new_val;
240 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
241 POSTING_READ(gen6_pm_imr(dev_priv));
242 }
243 }
244
245 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
246 {
247 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
248 return;
249
250 snb_update_pm_irq(dev_priv, mask, mask);
251 }
252
253 static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
254 uint32_t mask)
255 {
256 snb_update_pm_irq(dev_priv, mask, 0);
257 }
258
259 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
260 {
261 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
262 return;
263
264 __gen6_disable_pm_irq(dev_priv, mask);
265 }
266
267 void gen6_reset_rps_interrupts(struct drm_device *dev)
268 {
269 struct drm_i915_private *dev_priv = dev->dev_private;
270 uint32_t reg = gen6_pm_iir(dev_priv);
271
272 spin_lock_irq(&dev_priv->irq_lock);
273 I915_WRITE(reg, dev_priv->pm_rps_events);
274 I915_WRITE(reg, dev_priv->pm_rps_events);
275 POSTING_READ(reg);
276 spin_unlock_irq(&dev_priv->irq_lock);
277 }
278
279 void gen6_enable_rps_interrupts(struct drm_device *dev)
280 {
281 struct drm_i915_private *dev_priv = dev->dev_private;
282
283 spin_lock_irq(&dev_priv->irq_lock);
284
285 WARN_ON(dev_priv->rps.pm_iir);
286 WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
287 dev_priv->rps.interrupts_enabled = true;
288 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
289 dev_priv->pm_rps_events);
290 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
291
292 spin_unlock_irq(&dev_priv->irq_lock);
293 }
294
295 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
296 {
297 /*
298 * IVB and SNB hard hangs on looping batchbuffer
299 * if GEN6_PM_UP_EI_EXPIRED is masked.
300 */
301 if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
302 mask &= ~GEN6_PM_RP_UP_EI_EXPIRED;
303
304 if (INTEL_INFO(dev_priv)->gen >= 8)
305 mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
306
307 return mask;
308 }
309
310 void gen6_disable_rps_interrupts(struct drm_device *dev)
311 {
312 struct drm_i915_private *dev_priv = dev->dev_private;
313
314 spin_lock_irq(&dev_priv->irq_lock);
315 dev_priv->rps.interrupts_enabled = false;
316 spin_unlock_irq(&dev_priv->irq_lock);
317
318 cancel_work_sync(&dev_priv->rps.work);
319
320 spin_lock_irq(&dev_priv->irq_lock);
321
322 I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
323
324 __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
325 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
326 ~dev_priv->pm_rps_events);
327 I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events);
328 I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events);
329
330 dev_priv->rps.pm_iir = 0;
331
332 spin_unlock_irq(&dev_priv->irq_lock);
333 }
334
335 /**
336 * ibx_display_interrupt_update - update SDEIMR
337 * @dev_priv: driver private
338 * @interrupt_mask: mask of interrupt bits to update
339 * @enabled_irq_mask: mask of interrupt bits to enable
340 */
341 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
342 uint32_t interrupt_mask,
343 uint32_t enabled_irq_mask)
344 {
345 uint32_t sdeimr = I915_READ(SDEIMR);
346 sdeimr &= ~interrupt_mask;
347 sdeimr |= (~enabled_irq_mask & interrupt_mask);
348
349 assert_spin_locked(&dev_priv->irq_lock);
350
351 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
352 return;
353
354 I915_WRITE(SDEIMR, sdeimr);
355 POSTING_READ(SDEIMR);
356 }
357
358 static void
359 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
360 u32 enable_mask, u32 status_mask)
361 {
362 u32 reg = PIPESTAT(pipe);
363 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
364
365 assert_spin_locked(&dev_priv->irq_lock);
366 WARN_ON(!intel_irqs_enabled(dev_priv));
367
368 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
369 status_mask & ~PIPESTAT_INT_STATUS_MASK,
370 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
371 pipe_name(pipe), enable_mask, status_mask))
372 return;
373
374 if ((pipestat & enable_mask) == enable_mask)
375 return;
376
377 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
378
379 /* Enable the interrupt, clear any pending status */
380 pipestat |= enable_mask | status_mask;
381 I915_WRITE(reg, pipestat);
382 POSTING_READ(reg);
383 }
384
385 static void
386 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
387 u32 enable_mask, u32 status_mask)
388 {
389 u32 reg = PIPESTAT(pipe);
390 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
391
392 assert_spin_locked(&dev_priv->irq_lock);
393 WARN_ON(!intel_irqs_enabled(dev_priv));
394
395 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
396 status_mask & ~PIPESTAT_INT_STATUS_MASK,
397 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
398 pipe_name(pipe), enable_mask, status_mask))
399 return;
400
401 if ((pipestat & enable_mask) == 0)
402 return;
403
404 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
405
406 pipestat &= ~enable_mask;
407 I915_WRITE(reg, pipestat);
408 POSTING_READ(reg);
409 }
410
411 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
412 {
413 u32 enable_mask = status_mask << 16;
414
415 /*
416 * On pipe A we don't support the PSR interrupt yet,
417 * on pipe B and C the same bit MBZ.
418 */
419 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
420 return 0;
421 /*
422 * On pipe B and C we don't support the PSR interrupt yet, on pipe
423 * A the same bit is for perf counters which we don't use either.
424 */
425 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
426 return 0;
427
428 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
429 SPRITE0_FLIP_DONE_INT_EN_VLV |
430 SPRITE1_FLIP_DONE_INT_EN_VLV);
431 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
432 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
433 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
434 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
435
436 return enable_mask;
437 }
438
439 void
440 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
441 u32 status_mask)
442 {
443 u32 enable_mask;
444
445 if (IS_VALLEYVIEW(dev_priv->dev))
446 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
447 status_mask);
448 else
449 enable_mask = status_mask << 16;
450 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
451 }
452
453 void
454 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
455 u32 status_mask)
456 {
457 u32 enable_mask;
458
459 if (IS_VALLEYVIEW(dev_priv->dev))
460 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
461 status_mask);
462 else
463 enable_mask = status_mask << 16;
464 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
465 }
466
467 /**
468 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
469 */
470 static void i915_enable_asle_pipestat(struct drm_device *dev)
471 {
472 struct drm_i915_private *dev_priv = dev->dev_private;
473
474 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
475 return;
476
477 spin_lock_irq(&dev_priv->irq_lock);
478
479 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
480 if (INTEL_INFO(dev)->gen >= 4)
481 i915_enable_pipestat(dev_priv, PIPE_A,
482 PIPE_LEGACY_BLC_EVENT_STATUS);
483
484 spin_unlock_irq(&dev_priv->irq_lock);
485 }
486
487 /**
488 * i915_pipe_enabled - check if a pipe is enabled
489 * @dev: DRM device
490 * @pipe: pipe to check
491 *
492 * Reading certain registers when the pipe is disabled can hang the chip.
493 * Use this routine to make sure the PLL is running and the pipe is active
494 * before reading such registers if unsure.
495 */
496 static int
497 i915_pipe_enabled(struct drm_device *dev, int pipe)
498 {
499 struct drm_i915_private *dev_priv = dev->dev_private;
500
501 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
502 /* Locking is horribly broken here, but whatever. */
503 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
504 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
505
506 return intel_crtc->active;
507 } else {
508 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
509 }
510 }
511
512 /*
513 * This timing diagram depicts the video signal in and
514 * around the vertical blanking period.
515 *
516 * Assumptions about the fictitious mode used in this example:
517 * vblank_start >= 3
518 * vsync_start = vblank_start + 1
519 * vsync_end = vblank_start + 2
520 * vtotal = vblank_start + 3
521 *
522 * start of vblank:
523 * latch double buffered registers
524 * increment frame counter (ctg+)
525 * generate start of vblank interrupt (gen4+)
526 * |
527 * | frame start:
528 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
529 * | may be shifted forward 1-3 extra lines via PIPECONF
530 * | |
531 * | | start of vsync:
532 * | | generate vsync interrupt
533 * | | |
534 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
535 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
536 * ----va---> <-----------------vb--------------------> <--------va-------------
537 * | | <----vs-----> |
538 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
539 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
540 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
541 * | | |
542 * last visible pixel first visible pixel
543 * | increment frame counter (gen3/4)
544 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
545 *
546 * x = horizontal active
547 * _ = horizontal blanking
548 * hs = horizontal sync
549 * va = vertical active
550 * vb = vertical blanking
551 * vs = vertical sync
552 * vbs = vblank_start (number)
553 *
554 * Summary:
555 * - most events happen at the start of horizontal sync
556 * - frame start happens at the start of horizontal blank, 1-4 lines
557 * (depending on PIPECONF settings) after the start of vblank
558 * - gen3/4 pixel and frame counter are synchronized with the start
559 * of horizontal active on the first line of vertical active
560 */
561
562 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
563 {
564 /* Gen2 doesn't have a hardware frame counter */
565 return 0;
566 }
567
568 /* Called from drm generic code, passed a 'crtc', which
569 * we use as a pipe index
570 */
571 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
572 {
573 struct drm_i915_private *dev_priv = dev->dev_private;
574 unsigned long high_frame;
575 unsigned long low_frame;
576 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
577
578 if (!i915_pipe_enabled(dev, pipe)) {
579 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
580 "pipe %c\n", pipe_name(pipe));
581 return 0;
582 }
583
584 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
585 struct intel_crtc *intel_crtc =
586 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
587 const struct drm_display_mode *mode =
588 &intel_crtc->config.adjusted_mode;
589
590 htotal = mode->crtc_htotal;
591 hsync_start = mode->crtc_hsync_start;
592 vbl_start = mode->crtc_vblank_start;
593 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
594 vbl_start = DIV_ROUND_UP(vbl_start, 2);
595 } else {
596 enum transcoder cpu_transcoder = (enum transcoder) pipe;
597
598 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
599 hsync_start = (I915_READ(HSYNC(cpu_transcoder)) & 0x1fff) + 1;
600 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
601 if ((I915_READ(PIPECONF(cpu_transcoder)) &
602 PIPECONF_INTERLACE_MASK) != PIPECONF_PROGRESSIVE)
603 vbl_start = DIV_ROUND_UP(vbl_start, 2);
604 }
605
606 /* Convert to pixel count */
607 vbl_start *= htotal;
608
609 /* Start of vblank event occurs at start of hsync */
610 vbl_start -= htotal - hsync_start;
611
612 high_frame = PIPEFRAME(pipe);
613 low_frame = PIPEFRAMEPIXEL(pipe);
614
615 /*
616 * High & low register fields aren't synchronized, so make sure
617 * we get a low value that's stable across two reads of the high
618 * register.
619 */
620 do {
621 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
622 low = I915_READ(low_frame);
623 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
624 } while (high1 != high2);
625
626 high1 >>= PIPE_FRAME_HIGH_SHIFT;
627 pixel = low & PIPE_PIXEL_MASK;
628 low >>= PIPE_FRAME_LOW_SHIFT;
629
630 /*
631 * The frame counter increments at beginning of active.
632 * Cook up a vblank counter by also checking the pixel
633 * counter against vblank start.
634 */
635 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
636 }
637
638 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
639 {
640 struct drm_i915_private *dev_priv = dev->dev_private;
641 int reg = PIPE_FRMCOUNT_GM45(pipe);
642
643 if (!i915_pipe_enabled(dev, pipe)) {
644 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
645 "pipe %c\n", pipe_name(pipe));
646 return 0;
647 }
648
649 return I915_READ(reg);
650 }
651
652 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
653 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
654
655 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
656 {
657 struct drm_device *dev = crtc->base.dev;
658 struct drm_i915_private *dev_priv = dev->dev_private;
659 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
660 enum pipe pipe = crtc->pipe;
661 int position, vtotal;
662
663 vtotal = mode->crtc_vtotal;
664 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
665 vtotal /= 2;
666
667 if (IS_GEN2(dev))
668 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
669 else
670 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
671
672 /*
673 * See update_scanline_offset() for the details on the
674 * scanline_offset adjustment.
675 */
676 return (position + crtc->scanline_offset) % vtotal;
677 }
678
679 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
680 unsigned int flags, int *vpos, int *hpos,
681 ktime_t *stime, ktime_t *etime)
682 {
683 struct drm_i915_private *dev_priv = dev->dev_private;
684 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
685 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
686 const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
687 int position;
688 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
689 bool in_vbl = true;
690 int ret = 0;
691 unsigned long irqflags;
692
693 if (!intel_crtc->active) {
694 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
695 "pipe %c\n", pipe_name(pipe));
696 return 0;
697 }
698
699 htotal = mode->crtc_htotal;
700 hsync_start = mode->crtc_hsync_start;
701 vtotal = mode->crtc_vtotal;
702 vbl_start = mode->crtc_vblank_start;
703 vbl_end = mode->crtc_vblank_end;
704
705 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
706 vbl_start = DIV_ROUND_UP(vbl_start, 2);
707 vbl_end /= 2;
708 vtotal /= 2;
709 }
710
711 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
712
713 /*
714 * Lock uncore.lock, as we will do multiple timing critical raw
715 * register reads, potentially with preemption disabled, so the
716 * following code must not block on uncore.lock.
717 */
718 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
719
720 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
721
722 /* Get optional system timestamp before query. */
723 if (stime)
724 *stime = ktime_get();
725
726 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
727 /* No obvious pixelcount register. Only query vertical
728 * scanout position from Display scan line register.
729 */
730 position = __intel_get_crtc_scanline(intel_crtc);
731 } else {
732 /* Have access to pixelcount since start of frame.
733 * We can split this into vertical and horizontal
734 * scanout position.
735 */
736 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
737
738 /* convert to pixel counts */
739 vbl_start *= htotal;
740 vbl_end *= htotal;
741 vtotal *= htotal;
742
743 /*
744 * In interlaced modes, the pixel counter counts all pixels,
745 * so one field will have htotal more pixels. In order to avoid
746 * the reported position from jumping backwards when the pixel
747 * counter is beyond the length of the shorter field, just
748 * clamp the position the length of the shorter field. This
749 * matches how the scanline counter based position works since
750 * the scanline counter doesn't count the two half lines.
751 */
752 if (position >= vtotal)
753 position = vtotal - 1;
754
755 /*
756 * Start of vblank interrupt is triggered at start of hsync,
757 * just prior to the first active line of vblank. However we
758 * consider lines to start at the leading edge of horizontal
759 * active. So, should we get here before we've crossed into
760 * the horizontal active of the first line in vblank, we would
761 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
762 * always add htotal-hsync_start to the current pixel position.
763 */
764 position = (position + htotal - hsync_start) % vtotal;
765 }
766
767 /* Get optional system timestamp after query. */
768 if (etime)
769 *etime = ktime_get();
770
771 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
772
773 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
774
775 in_vbl = position >= vbl_start && position < vbl_end;
776
777 /*
778 * While in vblank, position will be negative
779 * counting up towards 0 at vbl_end. And outside
780 * vblank, position will be positive counting
781 * up since vbl_end.
782 */
783 if (position >= vbl_start)
784 position -= vbl_end;
785 else
786 position += vtotal - vbl_end;
787
788 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
789 *vpos = position;
790 *hpos = 0;
791 } else {
792 *vpos = position / htotal;
793 *hpos = position - (*vpos * htotal);
794 }
795
796 /* In vblank? */
797 if (in_vbl)
798 ret |= DRM_SCANOUTPOS_IN_VBLANK;
799
800 return ret;
801 }
802
803 int intel_get_crtc_scanline(struct intel_crtc *crtc)
804 {
805 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
806 unsigned long irqflags;
807 int position;
808
809 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
810 position = __intel_get_crtc_scanline(crtc);
811 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
812
813 return position;
814 }
815
816 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
817 int *max_error,
818 struct timeval *vblank_time,
819 unsigned flags)
820 {
821 struct drm_crtc *crtc;
822
823 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
824 DRM_ERROR("Invalid crtc %d\n", pipe);
825 return -EINVAL;
826 }
827
828 /* Get drm_crtc to timestamp: */
829 crtc = intel_get_crtc_for_pipe(dev, pipe);
830 if (crtc == NULL) {
831 DRM_ERROR("Invalid crtc %d\n", pipe);
832 return -EINVAL;
833 }
834
835 if (!crtc->enabled) {
836 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
837 return -EBUSY;
838 }
839
840 /* Helper routine in DRM core does all the work: */
841 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
842 vblank_time, flags,
843 crtc,
844 &to_intel_crtc(crtc)->config.adjusted_mode);
845 }
846
847 static bool intel_hpd_irq_event(struct drm_device *dev,
848 struct drm_connector *connector)
849 {
850 enum drm_connector_status old_status;
851
852 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
853 old_status = connector->status;
854
855 connector->status = connector->funcs->detect(connector, false);
856 if (old_status == connector->status)
857 return false;
858
859 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
860 connector->base.id,
861 connector->name,
862 drm_get_connector_status_name(old_status),
863 drm_get_connector_status_name(connector->status));
864
865 return true;
866 }
867
868 static void i915_digport_work_func(struct work_struct *work)
869 {
870 struct drm_i915_private *dev_priv =
871 container_of(work, struct drm_i915_private, dig_port_work);
872 u32 long_port_mask, short_port_mask;
873 struct intel_digital_port *intel_dig_port;
874 int i, ret;
875 u32 old_bits = 0;
876
877 spin_lock_irq(&dev_priv->irq_lock);
878 long_port_mask = dev_priv->long_hpd_port_mask;
879 dev_priv->long_hpd_port_mask = 0;
880 short_port_mask = dev_priv->short_hpd_port_mask;
881 dev_priv->short_hpd_port_mask = 0;
882 spin_unlock_irq(&dev_priv->irq_lock);
883
884 for (i = 0; i < I915_MAX_PORTS; i++) {
885 bool valid = false;
886 bool long_hpd = false;
887 intel_dig_port = dev_priv->hpd_irq_port[i];
888 if (!intel_dig_port || !intel_dig_port->hpd_pulse)
889 continue;
890
891 if (long_port_mask & (1 << i)) {
892 valid = true;
893 long_hpd = true;
894 } else if (short_port_mask & (1 << i))
895 valid = true;
896
897 if (valid) {
898 ret = intel_dig_port->hpd_pulse(intel_dig_port, long_hpd);
899 if (ret == true) {
900 /* if we get true fallback to old school hpd */
901 old_bits |= (1 << intel_dig_port->base.hpd_pin);
902 }
903 }
904 }
905
906 if (old_bits) {
907 spin_lock_irq(&dev_priv->irq_lock);
908 dev_priv->hpd_event_bits |= old_bits;
909 spin_unlock_irq(&dev_priv->irq_lock);
910 schedule_work(&dev_priv->hotplug_work);
911 }
912 }
913
914 /*
915 * Handle hotplug events outside the interrupt handler proper.
916 */
917 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
918
919 static void i915_hotplug_work_func(struct work_struct *work)
920 {
921 struct drm_i915_private *dev_priv =
922 container_of(work, struct drm_i915_private, hotplug_work);
923 struct drm_device *dev = dev_priv->dev;
924 struct drm_mode_config *mode_config = &dev->mode_config;
925 struct intel_connector *intel_connector;
926 struct intel_encoder *intel_encoder;
927 struct drm_connector *connector;
928 bool hpd_disabled = false;
929 bool changed = false;
930 u32 hpd_event_bits;
931
932 mutex_lock(&mode_config->mutex);
933 DRM_DEBUG_KMS("running encoder hotplug functions\n");
934
935 spin_lock_irq(&dev_priv->irq_lock);
936
937 hpd_event_bits = dev_priv->hpd_event_bits;
938 dev_priv->hpd_event_bits = 0;
939 list_for_each_entry(connector, &mode_config->connector_list, head) {
940 intel_connector = to_intel_connector(connector);
941 if (!intel_connector->encoder)
942 continue;
943 intel_encoder = intel_connector->encoder;
944 if (intel_encoder->hpd_pin > HPD_NONE &&
945 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
946 connector->polled == DRM_CONNECTOR_POLL_HPD) {
947 DRM_INFO("HPD interrupt storm detected on connector %s: "
948 "switching from hotplug detection to polling\n",
949 connector->name);
950 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
951 connector->polled = DRM_CONNECTOR_POLL_CONNECT
952 | DRM_CONNECTOR_POLL_DISCONNECT;
953 hpd_disabled = true;
954 }
955 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
956 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
957 connector->name, intel_encoder->hpd_pin);
958 }
959 }
960 /* if there were no outputs to poll, poll was disabled,
961 * therefore make sure it's enabled when disabling HPD on
962 * some connectors */
963 if (hpd_disabled) {
964 drm_kms_helper_poll_enable(dev);
965 mod_delayed_work(system_wq, &dev_priv->hotplug_reenable_work,
966 msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
967 }
968
969 spin_unlock_irq(&dev_priv->irq_lock);
970
971 list_for_each_entry(connector, &mode_config->connector_list, head) {
972 intel_connector = to_intel_connector(connector);
973 if (!intel_connector->encoder)
974 continue;
975 intel_encoder = intel_connector->encoder;
976 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
977 if (intel_encoder->hot_plug)
978 intel_encoder->hot_plug(intel_encoder);
979 if (intel_hpd_irq_event(dev, connector))
980 changed = true;
981 }
982 }
983 mutex_unlock(&mode_config->mutex);
984
985 if (changed)
986 drm_kms_helper_hotplug_event(dev);
987 }
988
989 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
990 {
991 struct drm_i915_private *dev_priv = dev->dev_private;
992 u32 busy_up, busy_down, max_avg, min_avg;
993 u8 new_delay;
994
995 spin_lock(&mchdev_lock);
996
997 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
998
999 new_delay = dev_priv->ips.cur_delay;
1000
1001 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
1002 busy_up = I915_READ(RCPREVBSYTUPAVG);
1003 busy_down = I915_READ(RCPREVBSYTDNAVG);
1004 max_avg = I915_READ(RCBMAXAVG);
1005 min_avg = I915_READ(RCBMINAVG);
1006
1007 /* Handle RCS change request from hw */
1008 if (busy_up > max_avg) {
1009 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
1010 new_delay = dev_priv->ips.cur_delay - 1;
1011 if (new_delay < dev_priv->ips.max_delay)
1012 new_delay = dev_priv->ips.max_delay;
1013 } else if (busy_down < min_avg) {
1014 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
1015 new_delay = dev_priv->ips.cur_delay + 1;
1016 if (new_delay > dev_priv->ips.min_delay)
1017 new_delay = dev_priv->ips.min_delay;
1018 }
1019
1020 if (ironlake_set_drps(dev, new_delay))
1021 dev_priv->ips.cur_delay = new_delay;
1022
1023 spin_unlock(&mchdev_lock);
1024
1025 return;
1026 }
1027
1028 static void notify_ring(struct drm_device *dev,
1029 struct intel_engine_cs *ring)
1030 {
1031 if (!intel_ring_initialized(ring))
1032 return;
1033
1034 trace_i915_gem_request_complete(ring);
1035
1036 wake_up_all(&ring->irq_queue);
1037 }
1038
1039 static u32 vlv_c0_residency(struct drm_i915_private *dev_priv,
1040 struct intel_rps_ei *rps_ei)
1041 {
1042 u32 cz_ts, cz_freq_khz;
1043 u32 render_count, media_count;
1044 u32 elapsed_render, elapsed_media, elapsed_time;
1045 u32 residency = 0;
1046
1047 cz_ts = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
1048 cz_freq_khz = DIV_ROUND_CLOSEST(dev_priv->mem_freq * 1000, 4);
1049
1050 render_count = I915_READ(VLV_RENDER_C0_COUNT_REG);
1051 media_count = I915_READ(VLV_MEDIA_C0_COUNT_REG);
1052
1053 if (rps_ei->cz_clock == 0) {
1054 rps_ei->cz_clock = cz_ts;
1055 rps_ei->render_c0 = render_count;
1056 rps_ei->media_c0 = media_count;
1057
1058 return dev_priv->rps.cur_freq;
1059 }
1060
1061 elapsed_time = cz_ts - rps_ei->cz_clock;
1062 rps_ei->cz_clock = cz_ts;
1063
1064 elapsed_render = render_count - rps_ei->render_c0;
1065 rps_ei->render_c0 = render_count;
1066
1067 elapsed_media = media_count - rps_ei->media_c0;
1068 rps_ei->media_c0 = media_count;
1069
1070 /* Convert all the counters into common unit of milli sec */
1071 elapsed_time /= VLV_CZ_CLOCK_TO_MILLI_SEC;
1072 elapsed_render /= cz_freq_khz;
1073 elapsed_media /= cz_freq_khz;
1074
1075 /*
1076 * Calculate overall C0 residency percentage
1077 * only if elapsed time is non zero
1078 */
1079 if (elapsed_time) {
1080 residency =
1081 ((max(elapsed_render, elapsed_media) * 100)
1082 / elapsed_time);
1083 }
1084
1085 return residency;
1086 }
1087
1088 /**
1089 * vlv_calc_delay_from_C0_counters - Increase/Decrease freq based on GPU
1090 * busy-ness calculated from C0 counters of render & media power wells
1091 * @dev_priv: DRM device private
1092 *
1093 */
1094 static int vlv_calc_delay_from_C0_counters(struct drm_i915_private *dev_priv)
1095 {
1096 u32 residency_C0_up = 0, residency_C0_down = 0;
1097 int new_delay, adj;
1098
1099 dev_priv->rps.ei_interrupt_count++;
1100
1101 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
1102
1103
1104 if (dev_priv->rps.up_ei.cz_clock == 0) {
1105 vlv_c0_residency(dev_priv, &dev_priv->rps.up_ei);
1106 vlv_c0_residency(dev_priv, &dev_priv->rps.down_ei);
1107 return dev_priv->rps.cur_freq;
1108 }
1109
1110
1111 /*
1112 * To down throttle, C0 residency should be less than down threshold
1113 * for continous EI intervals. So calculate down EI counters
1114 * once in VLV_INT_COUNT_FOR_DOWN_EI
1115 */
1116 if (dev_priv->rps.ei_interrupt_count == VLV_INT_COUNT_FOR_DOWN_EI) {
1117
1118 dev_priv->rps.ei_interrupt_count = 0;
1119
1120 residency_C0_down = vlv_c0_residency(dev_priv,
1121 &dev_priv->rps.down_ei);
1122 } else {
1123 residency_C0_up = vlv_c0_residency(dev_priv,
1124 &dev_priv->rps.up_ei);
1125 }
1126
1127 new_delay = dev_priv->rps.cur_freq;
1128
1129 adj = dev_priv->rps.last_adj;
1130 /* C0 residency is greater than UP threshold. Increase Frequency */
1131 if (residency_C0_up >= VLV_RP_UP_EI_THRESHOLD) {
1132 if (adj > 0)
1133 adj *= 2;
1134 else
1135 adj = 1;
1136
1137 if (dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit)
1138 new_delay = dev_priv->rps.cur_freq + adj;
1139
1140 /*
1141 * For better performance, jump directly
1142 * to RPe if we're below it.
1143 */
1144 if (new_delay < dev_priv->rps.efficient_freq)
1145 new_delay = dev_priv->rps.efficient_freq;
1146
1147 } else if (!dev_priv->rps.ei_interrupt_count &&
1148 (residency_C0_down < VLV_RP_DOWN_EI_THRESHOLD)) {
1149 if (adj < 0)
1150 adj *= 2;
1151 else
1152 adj = -1;
1153 /*
1154 * This means, C0 residency is less than down threshold over
1155 * a period of VLV_INT_COUNT_FOR_DOWN_EI. So, reduce the freq
1156 */
1157 if (dev_priv->rps.cur_freq > dev_priv->rps.min_freq_softlimit)
1158 new_delay = dev_priv->rps.cur_freq + adj;
1159 }
1160
1161 return new_delay;
1162 }
1163
1164 static void gen6_pm_rps_work(struct work_struct *work)
1165 {
1166 struct drm_i915_private *dev_priv =
1167 container_of(work, struct drm_i915_private, rps.work);
1168 u32 pm_iir;
1169 int new_delay, adj;
1170
1171 spin_lock_irq(&dev_priv->irq_lock);
1172 /* Speed up work cancelation during disabling rps interrupts. */
1173 if (!dev_priv->rps.interrupts_enabled) {
1174 spin_unlock_irq(&dev_priv->irq_lock);
1175 return;
1176 }
1177 pm_iir = dev_priv->rps.pm_iir;
1178 dev_priv->rps.pm_iir = 0;
1179 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1180 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1181 spin_unlock_irq(&dev_priv->irq_lock);
1182
1183 /* Make sure we didn't queue anything we're not going to process. */
1184 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1185
1186 if ((pm_iir & dev_priv->pm_rps_events) == 0)
1187 return;
1188
1189 mutex_lock(&dev_priv->rps.hw_lock);
1190
1191 adj = dev_priv->rps.last_adj;
1192 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1193 if (adj > 0)
1194 adj *= 2;
1195 else {
1196 /* CHV needs even encode values */
1197 adj = IS_CHERRYVIEW(dev_priv->dev) ? 2 : 1;
1198 }
1199 new_delay = dev_priv->rps.cur_freq + adj;
1200
1201 /*
1202 * For better performance, jump directly
1203 * to RPe if we're below it.
1204 */
1205 if (new_delay < dev_priv->rps.efficient_freq)
1206 new_delay = dev_priv->rps.efficient_freq;
1207 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1208 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1209 new_delay = dev_priv->rps.efficient_freq;
1210 else
1211 new_delay = dev_priv->rps.min_freq_softlimit;
1212 adj = 0;
1213 } else if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1214 new_delay = vlv_calc_delay_from_C0_counters(dev_priv);
1215 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1216 if (adj < 0)
1217 adj *= 2;
1218 else {
1219 /* CHV needs even encode values */
1220 adj = IS_CHERRYVIEW(dev_priv->dev) ? -2 : -1;
1221 }
1222 new_delay = dev_priv->rps.cur_freq + adj;
1223 } else { /* unknown event */
1224 new_delay = dev_priv->rps.cur_freq;
1225 }
1226
1227 /* sysfs frequency interfaces may have snuck in while servicing the
1228 * interrupt
1229 */
1230 new_delay = clamp_t(int, new_delay,
1231 dev_priv->rps.min_freq_softlimit,
1232 dev_priv->rps.max_freq_softlimit);
1233
1234 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq;
1235
1236 if (IS_VALLEYVIEW(dev_priv->dev))
1237 valleyview_set_rps(dev_priv->dev, new_delay);
1238 else
1239 gen6_set_rps(dev_priv->dev, new_delay);
1240
1241 mutex_unlock(&dev_priv->rps.hw_lock);
1242 }
1243
1244
1245 /**
1246 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1247 * occurred.
1248 * @work: workqueue struct
1249 *
1250 * Doesn't actually do anything except notify userspace. As a consequence of
1251 * this event, userspace should try to remap the bad rows since statistically
1252 * it is likely the same row is more likely to go bad again.
1253 */
1254 static void ivybridge_parity_work(struct work_struct *work)
1255 {
1256 struct drm_i915_private *dev_priv =
1257 container_of(work, struct drm_i915_private, l3_parity.error_work);
1258 u32 error_status, row, bank, subbank;
1259 char *parity_event[6];
1260 uint32_t misccpctl;
1261 uint8_t slice = 0;
1262
1263 /* We must turn off DOP level clock gating to access the L3 registers.
1264 * In order to prevent a get/put style interface, acquire struct mutex
1265 * any time we access those registers.
1266 */
1267 mutex_lock(&dev_priv->dev->struct_mutex);
1268
1269 /* If we've screwed up tracking, just let the interrupt fire again */
1270 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1271 goto out;
1272
1273 misccpctl = I915_READ(GEN7_MISCCPCTL);
1274 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1275 POSTING_READ(GEN7_MISCCPCTL);
1276
1277 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1278 u32 reg;
1279
1280 slice--;
1281 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1282 break;
1283
1284 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1285
1286 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1287
1288 error_status = I915_READ(reg);
1289 row = GEN7_PARITY_ERROR_ROW(error_status);
1290 bank = GEN7_PARITY_ERROR_BANK(error_status);
1291 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1292
1293 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1294 POSTING_READ(reg);
1295
1296 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1297 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1298 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1299 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1300 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1301 parity_event[5] = NULL;
1302
1303 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1304 KOBJ_CHANGE, parity_event);
1305
1306 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1307 slice, row, bank, subbank);
1308
1309 kfree(parity_event[4]);
1310 kfree(parity_event[3]);
1311 kfree(parity_event[2]);
1312 kfree(parity_event[1]);
1313 }
1314
1315 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1316
1317 out:
1318 WARN_ON(dev_priv->l3_parity.which_slice);
1319 spin_lock_irq(&dev_priv->irq_lock);
1320 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1321 spin_unlock_irq(&dev_priv->irq_lock);
1322
1323 mutex_unlock(&dev_priv->dev->struct_mutex);
1324 }
1325
1326 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1327 {
1328 struct drm_i915_private *dev_priv = dev->dev_private;
1329
1330 if (!HAS_L3_DPF(dev))
1331 return;
1332
1333 spin_lock(&dev_priv->irq_lock);
1334 gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1335 spin_unlock(&dev_priv->irq_lock);
1336
1337 iir &= GT_PARITY_ERROR(dev);
1338 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1339 dev_priv->l3_parity.which_slice |= 1 << 1;
1340
1341 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1342 dev_priv->l3_parity.which_slice |= 1 << 0;
1343
1344 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1345 }
1346
1347 static void ilk_gt_irq_handler(struct drm_device *dev,
1348 struct drm_i915_private *dev_priv,
1349 u32 gt_iir)
1350 {
1351 if (gt_iir &
1352 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1353 notify_ring(dev, &dev_priv->ring[RCS]);
1354 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1355 notify_ring(dev, &dev_priv->ring[VCS]);
1356 }
1357
1358 static void snb_gt_irq_handler(struct drm_device *dev,
1359 struct drm_i915_private *dev_priv,
1360 u32 gt_iir)
1361 {
1362
1363 if (gt_iir &
1364 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1365 notify_ring(dev, &dev_priv->ring[RCS]);
1366 if (gt_iir & GT_BSD_USER_INTERRUPT)
1367 notify_ring(dev, &dev_priv->ring[VCS]);
1368 if (gt_iir & GT_BLT_USER_INTERRUPT)
1369 notify_ring(dev, &dev_priv->ring[BCS]);
1370
1371 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1372 GT_BSD_CS_ERROR_INTERRUPT |
1373 GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1374 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1375
1376 if (gt_iir & GT_PARITY_ERROR(dev))
1377 ivybridge_parity_error_irq_handler(dev, gt_iir);
1378 }
1379
1380 static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1381 struct drm_i915_private *dev_priv,
1382 u32 master_ctl)
1383 {
1384 struct intel_engine_cs *ring;
1385 u32 rcs, bcs, vcs;
1386 uint32_t tmp = 0;
1387 irqreturn_t ret = IRQ_NONE;
1388
1389 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1390 tmp = I915_READ(GEN8_GT_IIR(0));
1391 if (tmp) {
1392 I915_WRITE(GEN8_GT_IIR(0), tmp);
1393 ret = IRQ_HANDLED;
1394
1395 rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1396 ring = &dev_priv->ring[RCS];
1397 if (rcs & GT_RENDER_USER_INTERRUPT)
1398 notify_ring(dev, ring);
1399 if (rcs & GT_CONTEXT_SWITCH_INTERRUPT)
1400 intel_execlists_handle_ctx_events(ring);
1401
1402 bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1403 ring = &dev_priv->ring[BCS];
1404 if (bcs & GT_RENDER_USER_INTERRUPT)
1405 notify_ring(dev, ring);
1406 if (bcs & GT_CONTEXT_SWITCH_INTERRUPT)
1407 intel_execlists_handle_ctx_events(ring);
1408 } else
1409 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1410 }
1411
1412 if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1413 tmp = I915_READ(GEN8_GT_IIR(1));
1414 if (tmp) {
1415 I915_WRITE(GEN8_GT_IIR(1), tmp);
1416 ret = IRQ_HANDLED;
1417
1418 vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1419 ring = &dev_priv->ring[VCS];
1420 if (vcs & GT_RENDER_USER_INTERRUPT)
1421 notify_ring(dev, ring);
1422 if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1423 intel_execlists_handle_ctx_events(ring);
1424
1425 vcs = tmp >> GEN8_VCS2_IRQ_SHIFT;
1426 ring = &dev_priv->ring[VCS2];
1427 if (vcs & GT_RENDER_USER_INTERRUPT)
1428 notify_ring(dev, ring);
1429 if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1430 intel_execlists_handle_ctx_events(ring);
1431 } else
1432 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1433 }
1434
1435 if (master_ctl & GEN8_GT_PM_IRQ) {
1436 tmp = I915_READ(GEN8_GT_IIR(2));
1437 if (tmp & dev_priv->pm_rps_events) {
1438 I915_WRITE(GEN8_GT_IIR(2),
1439 tmp & dev_priv->pm_rps_events);
1440 ret = IRQ_HANDLED;
1441 gen6_rps_irq_handler(dev_priv, tmp);
1442 } else
1443 DRM_ERROR("The master control interrupt lied (PM)!\n");
1444 }
1445
1446 if (master_ctl & GEN8_GT_VECS_IRQ) {
1447 tmp = I915_READ(GEN8_GT_IIR(3));
1448 if (tmp) {
1449 I915_WRITE(GEN8_GT_IIR(3), tmp);
1450 ret = IRQ_HANDLED;
1451
1452 vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1453 ring = &dev_priv->ring[VECS];
1454 if (vcs & GT_RENDER_USER_INTERRUPT)
1455 notify_ring(dev, ring);
1456 if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1457 intel_execlists_handle_ctx_events(ring);
1458 } else
1459 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1460 }
1461
1462 return ret;
1463 }
1464
1465 #define HPD_STORM_DETECT_PERIOD 1000
1466 #define HPD_STORM_THRESHOLD 5
1467
1468 static int pch_port_to_hotplug_shift(enum port port)
1469 {
1470 switch (port) {
1471 case PORT_A:
1472 case PORT_E:
1473 default:
1474 return -1;
1475 case PORT_B:
1476 return 0;
1477 case PORT_C:
1478 return 8;
1479 case PORT_D:
1480 return 16;
1481 }
1482 }
1483
1484 static int i915_port_to_hotplug_shift(enum port port)
1485 {
1486 switch (port) {
1487 case PORT_A:
1488 case PORT_E:
1489 default:
1490 return -1;
1491 case PORT_B:
1492 return 17;
1493 case PORT_C:
1494 return 19;
1495 case PORT_D:
1496 return 21;
1497 }
1498 }
1499
1500 static inline enum port get_port_from_pin(enum hpd_pin pin)
1501 {
1502 switch (pin) {
1503 case HPD_PORT_B:
1504 return PORT_B;
1505 case HPD_PORT_C:
1506 return PORT_C;
1507 case HPD_PORT_D:
1508 return PORT_D;
1509 default:
1510 return PORT_A; /* no hpd */
1511 }
1512 }
1513
1514 static inline void intel_hpd_irq_handler(struct drm_device *dev,
1515 u32 hotplug_trigger,
1516 u32 dig_hotplug_reg,
1517 const u32 *hpd)
1518 {
1519 struct drm_i915_private *dev_priv = dev->dev_private;
1520 int i;
1521 enum port port;
1522 bool storm_detected = false;
1523 bool queue_dig = false, queue_hp = false;
1524 u32 dig_shift;
1525 u32 dig_port_mask = 0;
1526
1527 if (!hotplug_trigger)
1528 return;
1529
1530 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x\n",
1531 hotplug_trigger, dig_hotplug_reg);
1532
1533 spin_lock(&dev_priv->irq_lock);
1534 for (i = 1; i < HPD_NUM_PINS; i++) {
1535 if (!(hpd[i] & hotplug_trigger))
1536 continue;
1537
1538 port = get_port_from_pin(i);
1539 if (port && dev_priv->hpd_irq_port[port]) {
1540 bool long_hpd;
1541
1542 if (HAS_PCH_SPLIT(dev)) {
1543 dig_shift = pch_port_to_hotplug_shift(port);
1544 long_hpd = (dig_hotplug_reg >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
1545 } else {
1546 dig_shift = i915_port_to_hotplug_shift(port);
1547 long_hpd = (hotplug_trigger >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
1548 }
1549
1550 DRM_DEBUG_DRIVER("digital hpd port %c - %s\n",
1551 port_name(port),
1552 long_hpd ? "long" : "short");
1553 /* for long HPD pulses we want to have the digital queue happen,
1554 but we still want HPD storm detection to function. */
1555 if (long_hpd) {
1556 dev_priv->long_hpd_port_mask |= (1 << port);
1557 dig_port_mask |= hpd[i];
1558 } else {
1559 /* for short HPD just trigger the digital queue */
1560 dev_priv->short_hpd_port_mask |= (1 << port);
1561 hotplug_trigger &= ~hpd[i];
1562 }
1563 queue_dig = true;
1564 }
1565 }
1566
1567 for (i = 1; i < HPD_NUM_PINS; i++) {
1568 if (hpd[i] & hotplug_trigger &&
1569 dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) {
1570 /*
1571 * On GMCH platforms the interrupt mask bits only
1572 * prevent irq generation, not the setting of the
1573 * hotplug bits itself. So only WARN about unexpected
1574 * interrupts on saner platforms.
1575 */
1576 WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
1577 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1578 hotplug_trigger, i, hpd[i]);
1579
1580 continue;
1581 }
1582
1583 if (!(hpd[i] & hotplug_trigger) ||
1584 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1585 continue;
1586
1587 if (!(dig_port_mask & hpd[i])) {
1588 dev_priv->hpd_event_bits |= (1 << i);
1589 queue_hp = true;
1590 }
1591
1592 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1593 dev_priv->hpd_stats[i].hpd_last_jiffies
1594 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1595 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1596 dev_priv->hpd_stats[i].hpd_cnt = 0;
1597 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1598 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1599 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1600 dev_priv->hpd_event_bits &= ~(1 << i);
1601 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1602 storm_detected = true;
1603 } else {
1604 dev_priv->hpd_stats[i].hpd_cnt++;
1605 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1606 dev_priv->hpd_stats[i].hpd_cnt);
1607 }
1608 }
1609
1610 if (storm_detected)
1611 dev_priv->display.hpd_irq_setup(dev);
1612 spin_unlock(&dev_priv->irq_lock);
1613
1614 /*
1615 * Our hotplug handler can grab modeset locks (by calling down into the
1616 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1617 * queue for otherwise the flush_work in the pageflip code will
1618 * deadlock.
1619 */
1620 if (queue_dig)
1621 queue_work(dev_priv->dp_wq, &dev_priv->dig_port_work);
1622 if (queue_hp)
1623 schedule_work(&dev_priv->hotplug_work);
1624 }
1625
1626 static void gmbus_irq_handler(struct drm_device *dev)
1627 {
1628 struct drm_i915_private *dev_priv = dev->dev_private;
1629
1630 wake_up_all(&dev_priv->gmbus_wait_queue);
1631 }
1632
1633 static void dp_aux_irq_handler(struct drm_device *dev)
1634 {
1635 struct drm_i915_private *dev_priv = dev->dev_private;
1636
1637 wake_up_all(&dev_priv->gmbus_wait_queue);
1638 }
1639
1640 #if defined(CONFIG_DEBUG_FS)
1641 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1642 uint32_t crc0, uint32_t crc1,
1643 uint32_t crc2, uint32_t crc3,
1644 uint32_t crc4)
1645 {
1646 struct drm_i915_private *dev_priv = dev->dev_private;
1647 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1648 struct intel_pipe_crc_entry *entry;
1649 int head, tail;
1650
1651 spin_lock(&pipe_crc->lock);
1652
1653 if (!pipe_crc->entries) {
1654 spin_unlock(&pipe_crc->lock);
1655 DRM_DEBUG_KMS("spurious interrupt\n");
1656 return;
1657 }
1658
1659 head = pipe_crc->head;
1660 tail = pipe_crc->tail;
1661
1662 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1663 spin_unlock(&pipe_crc->lock);
1664 DRM_ERROR("CRC buffer overflowing\n");
1665 return;
1666 }
1667
1668 entry = &pipe_crc->entries[head];
1669
1670 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1671 entry->crc[0] = crc0;
1672 entry->crc[1] = crc1;
1673 entry->crc[2] = crc2;
1674 entry->crc[3] = crc3;
1675 entry->crc[4] = crc4;
1676
1677 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1678 pipe_crc->head = head;
1679
1680 spin_unlock(&pipe_crc->lock);
1681
1682 wake_up_interruptible(&pipe_crc->wq);
1683 }
1684 #else
1685 static inline void
1686 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1687 uint32_t crc0, uint32_t crc1,
1688 uint32_t crc2, uint32_t crc3,
1689 uint32_t crc4) {}
1690 #endif
1691
1692
1693 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1694 {
1695 struct drm_i915_private *dev_priv = dev->dev_private;
1696
1697 display_pipe_crc_irq_handler(dev, pipe,
1698 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1699 0, 0, 0, 0);
1700 }
1701
1702 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1703 {
1704 struct drm_i915_private *dev_priv = dev->dev_private;
1705
1706 display_pipe_crc_irq_handler(dev, pipe,
1707 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1708 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1709 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1710 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1711 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1712 }
1713
1714 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1715 {
1716 struct drm_i915_private *dev_priv = dev->dev_private;
1717 uint32_t res1, res2;
1718
1719 if (INTEL_INFO(dev)->gen >= 3)
1720 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1721 else
1722 res1 = 0;
1723
1724 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1725 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1726 else
1727 res2 = 0;
1728
1729 display_pipe_crc_irq_handler(dev, pipe,
1730 I915_READ(PIPE_CRC_RES_RED(pipe)),
1731 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1732 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1733 res1, res2);
1734 }
1735
1736 /* The RPS events need forcewake, so we add them to a work queue and mask their
1737 * IMR bits until the work is done. Other interrupts can be processed without
1738 * the work queue. */
1739 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1740 {
1741 /* TODO: RPS on GEN9+ is not supported yet. */
1742 if (WARN_ONCE(INTEL_INFO(dev_priv)->gen >= 9,
1743 "GEN9+: unexpected RPS IRQ\n"))
1744 return;
1745
1746 if (pm_iir & dev_priv->pm_rps_events) {
1747 spin_lock(&dev_priv->irq_lock);
1748 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1749 if (dev_priv->rps.interrupts_enabled) {
1750 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1751 queue_work(dev_priv->wq, &dev_priv->rps.work);
1752 }
1753 spin_unlock(&dev_priv->irq_lock);
1754 }
1755
1756 if (INTEL_INFO(dev_priv)->gen >= 8)
1757 return;
1758
1759 if (HAS_VEBOX(dev_priv->dev)) {
1760 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1761 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1762
1763 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1764 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1765 }
1766 }
1767
1768 static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
1769 {
1770 if (!drm_handle_vblank(dev, pipe))
1771 return false;
1772
1773 return true;
1774 }
1775
1776 static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1777 {
1778 struct drm_i915_private *dev_priv = dev->dev_private;
1779 u32 pipe_stats[I915_MAX_PIPES] = { };
1780 int pipe;
1781
1782 spin_lock(&dev_priv->irq_lock);
1783 for_each_pipe(dev_priv, pipe) {
1784 int reg;
1785 u32 mask, iir_bit = 0;
1786
1787 /*
1788 * PIPESTAT bits get signalled even when the interrupt is
1789 * disabled with the mask bits, and some of the status bits do
1790 * not generate interrupts at all (like the underrun bit). Hence
1791 * we need to be careful that we only handle what we want to
1792 * handle.
1793 */
1794
1795 /* fifo underruns are filterered in the underrun handler. */
1796 mask = PIPE_FIFO_UNDERRUN_STATUS;
1797
1798 switch (pipe) {
1799 case PIPE_A:
1800 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1801 break;
1802 case PIPE_B:
1803 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1804 break;
1805 case PIPE_C:
1806 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1807 break;
1808 }
1809 if (iir & iir_bit)
1810 mask |= dev_priv->pipestat_irq_mask[pipe];
1811
1812 if (!mask)
1813 continue;
1814
1815 reg = PIPESTAT(pipe);
1816 mask |= PIPESTAT_INT_ENABLE_MASK;
1817 pipe_stats[pipe] = I915_READ(reg) & mask;
1818
1819 /*
1820 * Clear the PIPE*STAT regs before the IIR
1821 */
1822 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1823 PIPESTAT_INT_STATUS_MASK))
1824 I915_WRITE(reg, pipe_stats[pipe]);
1825 }
1826 spin_unlock(&dev_priv->irq_lock);
1827
1828 for_each_pipe(dev_priv, pipe) {
1829 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1830 intel_pipe_handle_vblank(dev, pipe))
1831 intel_check_page_flip(dev, pipe);
1832
1833 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
1834 intel_prepare_page_flip(dev, pipe);
1835 intel_finish_page_flip(dev, pipe);
1836 }
1837
1838 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1839 i9xx_pipe_crc_irq_handler(dev, pipe);
1840
1841 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1842 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1843 }
1844
1845 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1846 gmbus_irq_handler(dev);
1847 }
1848
1849 static void i9xx_hpd_irq_handler(struct drm_device *dev)
1850 {
1851 struct drm_i915_private *dev_priv = dev->dev_private;
1852 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1853
1854 if (hotplug_status) {
1855 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1856 /*
1857 * Make sure hotplug status is cleared before we clear IIR, or else we
1858 * may miss hotplug events.
1859 */
1860 POSTING_READ(PORT_HOTPLUG_STAT);
1861
1862 if (IS_G4X(dev)) {
1863 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1864
1865 intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_g4x);
1866 } else {
1867 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1868
1869 intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_i915);
1870 }
1871
1872 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) &&
1873 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1874 dp_aux_irq_handler(dev);
1875 }
1876 }
1877
1878 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1879 {
1880 struct drm_device *dev = arg;
1881 struct drm_i915_private *dev_priv = dev->dev_private;
1882 u32 iir, gt_iir, pm_iir;
1883 irqreturn_t ret = IRQ_NONE;
1884
1885 while (true) {
1886 /* Find, clear, then process each source of interrupt */
1887
1888 gt_iir = I915_READ(GTIIR);
1889 if (gt_iir)
1890 I915_WRITE(GTIIR, gt_iir);
1891
1892 pm_iir = I915_READ(GEN6_PMIIR);
1893 if (pm_iir)
1894 I915_WRITE(GEN6_PMIIR, pm_iir);
1895
1896 iir = I915_READ(VLV_IIR);
1897 if (iir) {
1898 /* Consume port before clearing IIR or we'll miss events */
1899 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1900 i9xx_hpd_irq_handler(dev);
1901 I915_WRITE(VLV_IIR, iir);
1902 }
1903
1904 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1905 goto out;
1906
1907 ret = IRQ_HANDLED;
1908
1909 if (gt_iir)
1910 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1911 if (pm_iir)
1912 gen6_rps_irq_handler(dev_priv, pm_iir);
1913 /* Call regardless, as some status bits might not be
1914 * signalled in iir */
1915 valleyview_pipestat_irq_handler(dev, iir);
1916 }
1917
1918 out:
1919 return ret;
1920 }
1921
1922 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1923 {
1924 struct drm_device *dev = arg;
1925 struct drm_i915_private *dev_priv = dev->dev_private;
1926 u32 master_ctl, iir;
1927 irqreturn_t ret = IRQ_NONE;
1928
1929 for (;;) {
1930 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1931 iir = I915_READ(VLV_IIR);
1932
1933 if (master_ctl == 0 && iir == 0)
1934 break;
1935
1936 ret = IRQ_HANDLED;
1937
1938 I915_WRITE(GEN8_MASTER_IRQ, 0);
1939
1940 /* Find, clear, then process each source of interrupt */
1941
1942 if (iir) {
1943 /* Consume port before clearing IIR or we'll miss events */
1944 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1945 i9xx_hpd_irq_handler(dev);
1946 I915_WRITE(VLV_IIR, iir);
1947 }
1948
1949 gen8_gt_irq_handler(dev, dev_priv, master_ctl);
1950
1951 /* Call regardless, as some status bits might not be
1952 * signalled in iir */
1953 valleyview_pipestat_irq_handler(dev, iir);
1954
1955 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
1956 POSTING_READ(GEN8_MASTER_IRQ);
1957 }
1958
1959 return ret;
1960 }
1961
1962 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1963 {
1964 struct drm_i915_private *dev_priv = dev->dev_private;
1965 int pipe;
1966 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1967 u32 dig_hotplug_reg;
1968
1969 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1970 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1971
1972 intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_ibx);
1973
1974 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1975 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1976 SDE_AUDIO_POWER_SHIFT);
1977 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1978 port_name(port));
1979 }
1980
1981 if (pch_iir & SDE_AUX_MASK)
1982 dp_aux_irq_handler(dev);
1983
1984 if (pch_iir & SDE_GMBUS)
1985 gmbus_irq_handler(dev);
1986
1987 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1988 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1989
1990 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1991 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1992
1993 if (pch_iir & SDE_POISON)
1994 DRM_ERROR("PCH poison interrupt\n");
1995
1996 if (pch_iir & SDE_FDI_MASK)
1997 for_each_pipe(dev_priv, pipe)
1998 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1999 pipe_name(pipe),
2000 I915_READ(FDI_RX_IIR(pipe)));
2001
2002 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
2003 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
2004
2005 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
2006 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
2007
2008 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
2009 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2010
2011 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
2012 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2013 }
2014
2015 static void ivb_err_int_handler(struct drm_device *dev)
2016 {
2017 struct drm_i915_private *dev_priv = dev->dev_private;
2018 u32 err_int = I915_READ(GEN7_ERR_INT);
2019 enum pipe pipe;
2020
2021 if (err_int & ERR_INT_POISON)
2022 DRM_ERROR("Poison interrupt\n");
2023
2024 for_each_pipe(dev_priv, pipe) {
2025 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
2026 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2027
2028 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
2029 if (IS_IVYBRIDGE(dev))
2030 ivb_pipe_crc_irq_handler(dev, pipe);
2031 else
2032 hsw_pipe_crc_irq_handler(dev, pipe);
2033 }
2034 }
2035
2036 I915_WRITE(GEN7_ERR_INT, err_int);
2037 }
2038
2039 static void cpt_serr_int_handler(struct drm_device *dev)
2040 {
2041 struct drm_i915_private *dev_priv = dev->dev_private;
2042 u32 serr_int = I915_READ(SERR_INT);
2043
2044 if (serr_int & SERR_INT_POISON)
2045 DRM_ERROR("PCH poison interrupt\n");
2046
2047 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2048 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2049
2050 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2051 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2052
2053 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2054 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
2055
2056 I915_WRITE(SERR_INT, serr_int);
2057 }
2058
2059 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
2060 {
2061 struct drm_i915_private *dev_priv = dev->dev_private;
2062 int pipe;
2063 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2064 u32 dig_hotplug_reg;
2065
2066 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2067 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2068
2069 intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_cpt);
2070
2071 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2072 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2073 SDE_AUDIO_POWER_SHIFT_CPT);
2074 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2075 port_name(port));
2076 }
2077
2078 if (pch_iir & SDE_AUX_MASK_CPT)
2079 dp_aux_irq_handler(dev);
2080
2081 if (pch_iir & SDE_GMBUS_CPT)
2082 gmbus_irq_handler(dev);
2083
2084 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2085 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2086
2087 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2088 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2089
2090 if (pch_iir & SDE_FDI_MASK_CPT)
2091 for_each_pipe(dev_priv, pipe)
2092 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2093 pipe_name(pipe),
2094 I915_READ(FDI_RX_IIR(pipe)));
2095
2096 if (pch_iir & SDE_ERROR_CPT)
2097 cpt_serr_int_handler(dev);
2098 }
2099
2100 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
2101 {
2102 struct drm_i915_private *dev_priv = dev->dev_private;
2103 enum pipe pipe;
2104
2105 if (de_iir & DE_AUX_CHANNEL_A)
2106 dp_aux_irq_handler(dev);
2107
2108 if (de_iir & DE_GSE)
2109 intel_opregion_asle_intr(dev);
2110
2111 if (de_iir & DE_POISON)
2112 DRM_ERROR("Poison interrupt\n");
2113
2114 for_each_pipe(dev_priv, pipe) {
2115 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2116 intel_pipe_handle_vblank(dev, pipe))
2117 intel_check_page_flip(dev, pipe);
2118
2119 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2120 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2121
2122 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2123 i9xx_pipe_crc_irq_handler(dev, pipe);
2124
2125 /* plane/pipes map 1:1 on ilk+ */
2126 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
2127 intel_prepare_page_flip(dev, pipe);
2128 intel_finish_page_flip_plane(dev, pipe);
2129 }
2130 }
2131
2132 /* check event from PCH */
2133 if (de_iir & DE_PCH_EVENT) {
2134 u32 pch_iir = I915_READ(SDEIIR);
2135
2136 if (HAS_PCH_CPT(dev))
2137 cpt_irq_handler(dev, pch_iir);
2138 else
2139 ibx_irq_handler(dev, pch_iir);
2140
2141 /* should clear PCH hotplug event before clear CPU irq */
2142 I915_WRITE(SDEIIR, pch_iir);
2143 }
2144
2145 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
2146 ironlake_rps_change_irq_handler(dev);
2147 }
2148
2149 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
2150 {
2151 struct drm_i915_private *dev_priv = dev->dev_private;
2152 enum pipe pipe;
2153
2154 if (de_iir & DE_ERR_INT_IVB)
2155 ivb_err_int_handler(dev);
2156
2157 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2158 dp_aux_irq_handler(dev);
2159
2160 if (de_iir & DE_GSE_IVB)
2161 intel_opregion_asle_intr(dev);
2162
2163 for_each_pipe(dev_priv, pipe) {
2164 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2165 intel_pipe_handle_vblank(dev, pipe))
2166 intel_check_page_flip(dev, pipe);
2167
2168 /* plane/pipes map 1:1 on ilk+ */
2169 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
2170 intel_prepare_page_flip(dev, pipe);
2171 intel_finish_page_flip_plane(dev, pipe);
2172 }
2173 }
2174
2175 /* check event from PCH */
2176 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
2177 u32 pch_iir = I915_READ(SDEIIR);
2178
2179 cpt_irq_handler(dev, pch_iir);
2180
2181 /* clear PCH hotplug event before clear CPU irq */
2182 I915_WRITE(SDEIIR, pch_iir);
2183 }
2184 }
2185
2186 /*
2187 * To handle irqs with the minimum potential races with fresh interrupts, we:
2188 * 1 - Disable Master Interrupt Control.
2189 * 2 - Find the source(s) of the interrupt.
2190 * 3 - Clear the Interrupt Identity bits (IIR).
2191 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2192 * 5 - Re-enable Master Interrupt Control.
2193 */
2194 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2195 {
2196 struct drm_device *dev = arg;
2197 struct drm_i915_private *dev_priv = dev->dev_private;
2198 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2199 irqreturn_t ret = IRQ_NONE;
2200
2201 /* We get interrupts on unclaimed registers, so check for this before we
2202 * do any I915_{READ,WRITE}. */
2203 intel_uncore_check_errors(dev);
2204
2205 /* disable master interrupt before clearing iir */
2206 de_ier = I915_READ(DEIER);
2207 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2208 POSTING_READ(DEIER);
2209
2210 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2211 * interrupts will will be stored on its back queue, and then we'll be
2212 * able to process them after we restore SDEIER (as soon as we restore
2213 * it, we'll get an interrupt if SDEIIR still has something to process
2214 * due to its back queue). */
2215 if (!HAS_PCH_NOP(dev)) {
2216 sde_ier = I915_READ(SDEIER);
2217 I915_WRITE(SDEIER, 0);
2218 POSTING_READ(SDEIER);
2219 }
2220
2221 /* Find, clear, then process each source of interrupt */
2222
2223 gt_iir = I915_READ(GTIIR);
2224 if (gt_iir) {
2225 I915_WRITE(GTIIR, gt_iir);
2226 ret = IRQ_HANDLED;
2227 if (INTEL_INFO(dev)->gen >= 6)
2228 snb_gt_irq_handler(dev, dev_priv, gt_iir);
2229 else
2230 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
2231 }
2232
2233 de_iir = I915_READ(DEIIR);
2234 if (de_iir) {
2235 I915_WRITE(DEIIR, de_iir);
2236 ret = IRQ_HANDLED;
2237 if (INTEL_INFO(dev)->gen >= 7)
2238 ivb_display_irq_handler(dev, de_iir);
2239 else
2240 ilk_display_irq_handler(dev, de_iir);
2241 }
2242
2243 if (INTEL_INFO(dev)->gen >= 6) {
2244 u32 pm_iir = I915_READ(GEN6_PMIIR);
2245 if (pm_iir) {
2246 I915_WRITE(GEN6_PMIIR, pm_iir);
2247 ret = IRQ_HANDLED;
2248 gen6_rps_irq_handler(dev_priv, pm_iir);
2249 }
2250 }
2251
2252 I915_WRITE(DEIER, de_ier);
2253 POSTING_READ(DEIER);
2254 if (!HAS_PCH_NOP(dev)) {
2255 I915_WRITE(SDEIER, sde_ier);
2256 POSTING_READ(SDEIER);
2257 }
2258
2259 return ret;
2260 }
2261
2262 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2263 {
2264 struct drm_device *dev = arg;
2265 struct drm_i915_private *dev_priv = dev->dev_private;
2266 u32 master_ctl;
2267 irqreturn_t ret = IRQ_NONE;
2268 uint32_t tmp = 0;
2269 enum pipe pipe;
2270 u32 aux_mask = GEN8_AUX_CHANNEL_A;
2271
2272 if (IS_GEN9(dev))
2273 aux_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
2274 GEN9_AUX_CHANNEL_D;
2275
2276 master_ctl = I915_READ(GEN8_MASTER_IRQ);
2277 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2278 if (!master_ctl)
2279 return IRQ_NONE;
2280
2281 I915_WRITE(GEN8_MASTER_IRQ, 0);
2282 POSTING_READ(GEN8_MASTER_IRQ);
2283
2284 /* Find, clear, then process each source of interrupt */
2285
2286 ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
2287
2288 if (master_ctl & GEN8_DE_MISC_IRQ) {
2289 tmp = I915_READ(GEN8_DE_MISC_IIR);
2290 if (tmp) {
2291 I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2292 ret = IRQ_HANDLED;
2293 if (tmp & GEN8_DE_MISC_GSE)
2294 intel_opregion_asle_intr(dev);
2295 else
2296 DRM_ERROR("Unexpected DE Misc interrupt\n");
2297 }
2298 else
2299 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2300 }
2301
2302 if (master_ctl & GEN8_DE_PORT_IRQ) {
2303 tmp = I915_READ(GEN8_DE_PORT_IIR);
2304 if (tmp) {
2305 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2306 ret = IRQ_HANDLED;
2307
2308 if (tmp & aux_mask)
2309 dp_aux_irq_handler(dev);
2310 else
2311 DRM_ERROR("Unexpected DE Port interrupt\n");
2312 }
2313 else
2314 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2315 }
2316
2317 for_each_pipe(dev_priv, pipe) {
2318 uint32_t pipe_iir, flip_done = 0, fault_errors = 0;
2319
2320 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2321 continue;
2322
2323 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2324 if (pipe_iir) {
2325 ret = IRQ_HANDLED;
2326 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2327
2328 if (pipe_iir & GEN8_PIPE_VBLANK &&
2329 intel_pipe_handle_vblank(dev, pipe))
2330 intel_check_page_flip(dev, pipe);
2331
2332 if (IS_GEN9(dev))
2333 flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE;
2334 else
2335 flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE;
2336
2337 if (flip_done) {
2338 intel_prepare_page_flip(dev, pipe);
2339 intel_finish_page_flip_plane(dev, pipe);
2340 }
2341
2342 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2343 hsw_pipe_crc_irq_handler(dev, pipe);
2344
2345 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN)
2346 intel_cpu_fifo_underrun_irq_handler(dev_priv,
2347 pipe);
2348
2349
2350 if (IS_GEN9(dev))
2351 fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2352 else
2353 fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2354
2355 if (fault_errors)
2356 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2357 pipe_name(pipe),
2358 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2359 } else
2360 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2361 }
2362
2363 if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
2364 /*
2365 * FIXME(BDW): Assume for now that the new interrupt handling
2366 * scheme also closed the SDE interrupt handling race we've seen
2367 * on older pch-split platforms. But this needs testing.
2368 */
2369 u32 pch_iir = I915_READ(SDEIIR);
2370 if (pch_iir) {
2371 I915_WRITE(SDEIIR, pch_iir);
2372 ret = IRQ_HANDLED;
2373 cpt_irq_handler(dev, pch_iir);
2374 } else
2375 DRM_ERROR("The master control interrupt lied (SDE)!\n");
2376
2377 }
2378
2379 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2380 POSTING_READ(GEN8_MASTER_IRQ);
2381
2382 return ret;
2383 }
2384
2385 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2386 bool reset_completed)
2387 {
2388 struct intel_engine_cs *ring;
2389 int i;
2390
2391 /*
2392 * Notify all waiters for GPU completion events that reset state has
2393 * been changed, and that they need to restart their wait after
2394 * checking for potential errors (and bail out to drop locks if there is
2395 * a gpu reset pending so that i915_error_work_func can acquire them).
2396 */
2397
2398 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2399 for_each_ring(ring, dev_priv, i)
2400 wake_up_all(&ring->irq_queue);
2401
2402 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2403 wake_up_all(&dev_priv->pending_flip_queue);
2404
2405 /*
2406 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2407 * reset state is cleared.
2408 */
2409 if (reset_completed)
2410 wake_up_all(&dev_priv->gpu_error.reset_queue);
2411 }
2412
2413 /**
2414 * i915_error_work_func - do process context error handling work
2415 * @work: work struct
2416 *
2417 * Fire an error uevent so userspace can see that a hang or error
2418 * was detected.
2419 */
2420 static void i915_error_work_func(struct work_struct *work)
2421 {
2422 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
2423 work);
2424 struct drm_i915_private *dev_priv =
2425 container_of(error, struct drm_i915_private, gpu_error);
2426 struct drm_device *dev = dev_priv->dev;
2427 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2428 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2429 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2430 int ret;
2431
2432 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2433
2434 /*
2435 * Note that there's only one work item which does gpu resets, so we
2436 * need not worry about concurrent gpu resets potentially incrementing
2437 * error->reset_counter twice. We only need to take care of another
2438 * racing irq/hangcheck declaring the gpu dead for a second time. A
2439 * quick check for that is good enough: schedule_work ensures the
2440 * correct ordering between hang detection and this work item, and since
2441 * the reset in-progress bit is only ever set by code outside of this
2442 * work we don't need to worry about any other races.
2443 */
2444 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2445 DRM_DEBUG_DRIVER("resetting chip\n");
2446 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2447 reset_event);
2448
2449 /*
2450 * In most cases it's guaranteed that we get here with an RPM
2451 * reference held, for example because there is a pending GPU
2452 * request that won't finish until the reset is done. This
2453 * isn't the case at least when we get here by doing a
2454 * simulated reset via debugs, so get an RPM reference.
2455 */
2456 intel_runtime_pm_get(dev_priv);
2457
2458 intel_prepare_reset(dev);
2459
2460 /*
2461 * All state reset _must_ be completed before we update the
2462 * reset counter, for otherwise waiters might miss the reset
2463 * pending state and not properly drop locks, resulting in
2464 * deadlocks with the reset work.
2465 */
2466 ret = i915_reset(dev);
2467
2468 intel_finish_reset(dev);
2469
2470 intel_runtime_pm_put(dev_priv);
2471
2472 if (ret == 0) {
2473 /*
2474 * After all the gem state is reset, increment the reset
2475 * counter and wake up everyone waiting for the reset to
2476 * complete.
2477 *
2478 * Since unlock operations are a one-sided barrier only,
2479 * we need to insert a barrier here to order any seqno
2480 * updates before
2481 * the counter increment.
2482 */
2483 smp_mb__before_atomic();
2484 atomic_inc(&dev_priv->gpu_error.reset_counter);
2485
2486 kobject_uevent_env(&dev->primary->kdev->kobj,
2487 KOBJ_CHANGE, reset_done_event);
2488 } else {
2489 atomic_set_mask(I915_WEDGED, &error->reset_counter);
2490 }
2491
2492 /*
2493 * Note: The wake_up also serves as a memory barrier so that
2494 * waiters see the update value of the reset counter atomic_t.
2495 */
2496 i915_error_wake_up(dev_priv, true);
2497 }
2498 }
2499
2500 static void i915_report_and_clear_eir(struct drm_device *dev)
2501 {
2502 struct drm_i915_private *dev_priv = dev->dev_private;
2503 uint32_t instdone[I915_NUM_INSTDONE_REG];
2504 u32 eir = I915_READ(EIR);
2505 int pipe, i;
2506
2507 if (!eir)
2508 return;
2509
2510 pr_err("render error detected, EIR: 0x%08x\n", eir);
2511
2512 i915_get_extra_instdone(dev, instdone);
2513
2514 if (IS_G4X(dev)) {
2515 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2516 u32 ipeir = I915_READ(IPEIR_I965);
2517
2518 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2519 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2520 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2521 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2522 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2523 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2524 I915_WRITE(IPEIR_I965, ipeir);
2525 POSTING_READ(IPEIR_I965);
2526 }
2527 if (eir & GM45_ERROR_PAGE_TABLE) {
2528 u32 pgtbl_err = I915_READ(PGTBL_ER);
2529 pr_err("page table error\n");
2530 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2531 I915_WRITE(PGTBL_ER, pgtbl_err);
2532 POSTING_READ(PGTBL_ER);
2533 }
2534 }
2535
2536 if (!IS_GEN2(dev)) {
2537 if (eir & I915_ERROR_PAGE_TABLE) {
2538 u32 pgtbl_err = I915_READ(PGTBL_ER);
2539 pr_err("page table error\n");
2540 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2541 I915_WRITE(PGTBL_ER, pgtbl_err);
2542 POSTING_READ(PGTBL_ER);
2543 }
2544 }
2545
2546 if (eir & I915_ERROR_MEMORY_REFRESH) {
2547 pr_err("memory refresh error:\n");
2548 for_each_pipe(dev_priv, pipe)
2549 pr_err("pipe %c stat: 0x%08x\n",
2550 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2551 /* pipestat has already been acked */
2552 }
2553 if (eir & I915_ERROR_INSTRUCTION) {
2554 pr_err("instruction error\n");
2555 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
2556 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2557 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2558 if (INTEL_INFO(dev)->gen < 4) {
2559 u32 ipeir = I915_READ(IPEIR);
2560
2561 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2562 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
2563 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
2564 I915_WRITE(IPEIR, ipeir);
2565 POSTING_READ(IPEIR);
2566 } else {
2567 u32 ipeir = I915_READ(IPEIR_I965);
2568
2569 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2570 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2571 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2572 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2573 I915_WRITE(IPEIR_I965, ipeir);
2574 POSTING_READ(IPEIR_I965);
2575 }
2576 }
2577
2578 I915_WRITE(EIR, eir);
2579 POSTING_READ(EIR);
2580 eir = I915_READ(EIR);
2581 if (eir) {
2582 /*
2583 * some errors might have become stuck,
2584 * mask them.
2585 */
2586 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2587 I915_WRITE(EMR, I915_READ(EMR) | eir);
2588 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2589 }
2590 }
2591
2592 /**
2593 * i915_handle_error - handle an error interrupt
2594 * @dev: drm device
2595 *
2596 * Do some basic checking of regsiter state at error interrupt time and
2597 * dump it to the syslog. Also call i915_capture_error_state() to make
2598 * sure we get a record and make it available in debugfs. Fire a uevent
2599 * so userspace knows something bad happened (should trigger collection
2600 * of a ring dump etc.).
2601 */
2602 void i915_handle_error(struct drm_device *dev, bool wedged,
2603 const char *fmt, ...)
2604 {
2605 struct drm_i915_private *dev_priv = dev->dev_private;
2606 va_list args;
2607 char error_msg[80];
2608
2609 va_start(args, fmt);
2610 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2611 va_end(args);
2612
2613 i915_capture_error_state(dev, wedged, error_msg);
2614 i915_report_and_clear_eir(dev);
2615
2616 if (wedged) {
2617 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2618 &dev_priv->gpu_error.reset_counter);
2619
2620 /*
2621 * Wakeup waiting processes so that the reset work function
2622 * i915_error_work_func doesn't deadlock trying to grab various
2623 * locks. By bumping the reset counter first, the woken
2624 * processes will see a reset in progress and back off,
2625 * releasing their locks and then wait for the reset completion.
2626 * We must do this for _all_ gpu waiters that might hold locks
2627 * that the reset work needs to acquire.
2628 *
2629 * Note: The wake_up serves as the required memory barrier to
2630 * ensure that the waiters see the updated value of the reset
2631 * counter atomic_t.
2632 */
2633 i915_error_wake_up(dev_priv, false);
2634 }
2635
2636 /*
2637 * Our reset work can grab modeset locks (since it needs to reset the
2638 * state of outstanding pagelips). Hence it must not be run on our own
2639 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2640 * code will deadlock.
2641 */
2642 schedule_work(&dev_priv->gpu_error.work);
2643 }
2644
2645 /* Called from drm generic code, passed 'crtc' which
2646 * we use as a pipe index
2647 */
2648 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2649 {
2650 struct drm_i915_private *dev_priv = dev->dev_private;
2651 unsigned long irqflags;
2652
2653 if (!i915_pipe_enabled(dev, pipe))
2654 return -EINVAL;
2655
2656 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2657 if (INTEL_INFO(dev)->gen >= 4)
2658 i915_enable_pipestat(dev_priv, pipe,
2659 PIPE_START_VBLANK_INTERRUPT_STATUS);
2660 else
2661 i915_enable_pipestat(dev_priv, pipe,
2662 PIPE_VBLANK_INTERRUPT_STATUS);
2663 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2664
2665 return 0;
2666 }
2667
2668 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2669 {
2670 struct drm_i915_private *dev_priv = dev->dev_private;
2671 unsigned long irqflags;
2672 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2673 DE_PIPE_VBLANK(pipe);
2674
2675 if (!i915_pipe_enabled(dev, pipe))
2676 return -EINVAL;
2677
2678 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2679 ironlake_enable_display_irq(dev_priv, bit);
2680 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2681
2682 return 0;
2683 }
2684
2685 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2686 {
2687 struct drm_i915_private *dev_priv = dev->dev_private;
2688 unsigned long irqflags;
2689
2690 if (!i915_pipe_enabled(dev, pipe))
2691 return -EINVAL;
2692
2693 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2694 i915_enable_pipestat(dev_priv, pipe,
2695 PIPE_START_VBLANK_INTERRUPT_STATUS);
2696 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2697
2698 return 0;
2699 }
2700
2701 static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2702 {
2703 struct drm_i915_private *dev_priv = dev->dev_private;
2704 unsigned long irqflags;
2705
2706 if (!i915_pipe_enabled(dev, pipe))
2707 return -EINVAL;
2708
2709 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2710 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2711 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2712 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2713 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2714 return 0;
2715 }
2716
2717 /* Called from drm generic code, passed 'crtc' which
2718 * we use as a pipe index
2719 */
2720 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2721 {
2722 struct drm_i915_private *dev_priv = dev->dev_private;
2723 unsigned long irqflags;
2724
2725 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2726 i915_disable_pipestat(dev_priv, pipe,
2727 PIPE_VBLANK_INTERRUPT_STATUS |
2728 PIPE_START_VBLANK_INTERRUPT_STATUS);
2729 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2730 }
2731
2732 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2733 {
2734 struct drm_i915_private *dev_priv = dev->dev_private;
2735 unsigned long irqflags;
2736 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2737 DE_PIPE_VBLANK(pipe);
2738
2739 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2740 ironlake_disable_display_irq(dev_priv, bit);
2741 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2742 }
2743
2744 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2745 {
2746 struct drm_i915_private *dev_priv = dev->dev_private;
2747 unsigned long irqflags;
2748
2749 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2750 i915_disable_pipestat(dev_priv, pipe,
2751 PIPE_START_VBLANK_INTERRUPT_STATUS);
2752 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2753 }
2754
2755 static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2756 {
2757 struct drm_i915_private *dev_priv = dev->dev_private;
2758 unsigned long irqflags;
2759
2760 if (!i915_pipe_enabled(dev, pipe))
2761 return;
2762
2763 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2764 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2765 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2766 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2767 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2768 }
2769
2770 static u32
2771 ring_last_seqno(struct intel_engine_cs *ring)
2772 {
2773 return list_entry(ring->request_list.prev,
2774 struct drm_i915_gem_request, list)->seqno;
2775 }
2776
2777 static bool
2778 ring_idle(struct intel_engine_cs *ring, u32 seqno)
2779 {
2780 return (list_empty(&ring->request_list) ||
2781 i915_seqno_passed(seqno, ring_last_seqno(ring)));
2782 }
2783
2784 static bool
2785 ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
2786 {
2787 if (INTEL_INFO(dev)->gen >= 8) {
2788 return (ipehr >> 23) == 0x1c;
2789 } else {
2790 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2791 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2792 MI_SEMAPHORE_REGISTER);
2793 }
2794 }
2795
2796 static struct intel_engine_cs *
2797 semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset)
2798 {
2799 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2800 struct intel_engine_cs *signaller;
2801 int i;
2802
2803 if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
2804 for_each_ring(signaller, dev_priv, i) {
2805 if (ring == signaller)
2806 continue;
2807
2808 if (offset == signaller->semaphore.signal_ggtt[ring->id])
2809 return signaller;
2810 }
2811 } else {
2812 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2813
2814 for_each_ring(signaller, dev_priv, i) {
2815 if(ring == signaller)
2816 continue;
2817
2818 if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
2819 return signaller;
2820 }
2821 }
2822
2823 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2824 ring->id, ipehr, offset);
2825
2826 return NULL;
2827 }
2828
2829 static struct intel_engine_cs *
2830 semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
2831 {
2832 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2833 u32 cmd, ipehr, head;
2834 u64 offset = 0;
2835 int i, backwards;
2836
2837 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2838 if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
2839 return NULL;
2840
2841 /*
2842 * HEAD is likely pointing to the dword after the actual command,
2843 * so scan backwards until we find the MBOX. But limit it to just 3
2844 * or 4 dwords depending on the semaphore wait command size.
2845 * Note that we don't care about ACTHD here since that might
2846 * point at at batch, and semaphores are always emitted into the
2847 * ringbuffer itself.
2848 */
2849 head = I915_READ_HEAD(ring) & HEAD_ADDR;
2850 backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4;
2851
2852 for (i = backwards; i; --i) {
2853 /*
2854 * Be paranoid and presume the hw has gone off into the wild -
2855 * our ring is smaller than what the hardware (and hence
2856 * HEAD_ADDR) allows. Also handles wrap-around.
2857 */
2858 head &= ring->buffer->size - 1;
2859
2860 /* This here seems to blow up */
2861 cmd = ioread32(ring->buffer->virtual_start + head);
2862 if (cmd == ipehr)
2863 break;
2864
2865 head -= 4;
2866 }
2867
2868 if (!i)
2869 return NULL;
2870
2871 *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
2872 if (INTEL_INFO(ring->dev)->gen >= 8) {
2873 offset = ioread32(ring->buffer->virtual_start + head + 12);
2874 offset <<= 32;
2875 offset = ioread32(ring->buffer->virtual_start + head + 8);
2876 }
2877 return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
2878 }
2879
2880 static int semaphore_passed(struct intel_engine_cs *ring)
2881 {
2882 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2883 struct intel_engine_cs *signaller;
2884 u32 seqno;
2885
2886 ring->hangcheck.deadlock++;
2887
2888 signaller = semaphore_waits_for(ring, &seqno);
2889 if (signaller == NULL)
2890 return -1;
2891
2892 /* Prevent pathological recursion due to driver bugs */
2893 if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
2894 return -1;
2895
2896 if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
2897 return 1;
2898
2899 /* cursory check for an unkickable deadlock */
2900 if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
2901 semaphore_passed(signaller) < 0)
2902 return -1;
2903
2904 return 0;
2905 }
2906
2907 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2908 {
2909 struct intel_engine_cs *ring;
2910 int i;
2911
2912 for_each_ring(ring, dev_priv, i)
2913 ring->hangcheck.deadlock = 0;
2914 }
2915
2916 static enum intel_ring_hangcheck_action
2917 ring_stuck(struct intel_engine_cs *ring, u64 acthd)
2918 {
2919 struct drm_device *dev = ring->dev;
2920 struct drm_i915_private *dev_priv = dev->dev_private;
2921 u32 tmp;
2922
2923 if (acthd != ring->hangcheck.acthd) {
2924 if (acthd > ring->hangcheck.max_acthd) {
2925 ring->hangcheck.max_acthd = acthd;
2926 return HANGCHECK_ACTIVE;
2927 }
2928
2929 return HANGCHECK_ACTIVE_LOOP;
2930 }
2931
2932 if (IS_GEN2(dev))
2933 return HANGCHECK_HUNG;
2934
2935 /* Is the chip hanging on a WAIT_FOR_EVENT?
2936 * If so we can simply poke the RB_WAIT bit
2937 * and break the hang. This should work on
2938 * all but the second generation chipsets.
2939 */
2940 tmp = I915_READ_CTL(ring);
2941 if (tmp & RING_WAIT) {
2942 i915_handle_error(dev, false,
2943 "Kicking stuck wait on %s",
2944 ring->name);
2945 I915_WRITE_CTL(ring, tmp);
2946 return HANGCHECK_KICK;
2947 }
2948
2949 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2950 switch (semaphore_passed(ring)) {
2951 default:
2952 return HANGCHECK_HUNG;
2953 case 1:
2954 i915_handle_error(dev, false,
2955 "Kicking stuck semaphore on %s",
2956 ring->name);
2957 I915_WRITE_CTL(ring, tmp);
2958 return HANGCHECK_KICK;
2959 case 0:
2960 return HANGCHECK_WAIT;
2961 }
2962 }
2963
2964 return HANGCHECK_HUNG;
2965 }
2966
2967 /**
2968 * This is called when the chip hasn't reported back with completed
2969 * batchbuffers in a long time. We keep track per ring seqno progress and
2970 * if there are no progress, hangcheck score for that ring is increased.
2971 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2972 * we kick the ring. If we see no progress on three subsequent calls
2973 * we assume chip is wedged and try to fix it by resetting the chip.
2974 */
2975 static void i915_hangcheck_elapsed(unsigned long data)
2976 {
2977 struct drm_device *dev = (struct drm_device *)data;
2978 struct drm_i915_private *dev_priv = dev->dev_private;
2979 struct intel_engine_cs *ring;
2980 int i;
2981 int busy_count = 0, rings_hung = 0;
2982 bool stuck[I915_NUM_RINGS] = { 0 };
2983 #define BUSY 1
2984 #define KICK 5
2985 #define HUNG 20
2986
2987 if (!i915.enable_hangcheck)
2988 return;
2989
2990 for_each_ring(ring, dev_priv, i) {
2991 u64 acthd;
2992 u32 seqno;
2993 bool busy = true;
2994
2995 semaphore_clear_deadlocks(dev_priv);
2996
2997 seqno = ring->get_seqno(ring, false);
2998 acthd = intel_ring_get_active_head(ring);
2999
3000 if (ring->hangcheck.seqno == seqno) {
3001 if (ring_idle(ring, seqno)) {
3002 ring->hangcheck.action = HANGCHECK_IDLE;
3003
3004 if (waitqueue_active(&ring->irq_queue)) {
3005 /* Issue a wake-up to catch stuck h/w. */
3006 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
3007 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
3008 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
3009 ring->name);
3010 else
3011 DRM_INFO("Fake missed irq on %s\n",
3012 ring->name);
3013 wake_up_all(&ring->irq_queue);
3014 }
3015 /* Safeguard against driver failure */
3016 ring->hangcheck.score += BUSY;
3017 } else
3018 busy = false;
3019 } else {
3020 /* We always increment the hangcheck score
3021 * if the ring is busy and still processing
3022 * the same request, so that no single request
3023 * can run indefinitely (such as a chain of
3024 * batches). The only time we do not increment
3025 * the hangcheck score on this ring, if this
3026 * ring is in a legitimate wait for another
3027 * ring. In that case the waiting ring is a
3028 * victim and we want to be sure we catch the
3029 * right culprit. Then every time we do kick
3030 * the ring, add a small increment to the
3031 * score so that we can catch a batch that is
3032 * being repeatedly kicked and so responsible
3033 * for stalling the machine.
3034 */
3035 ring->hangcheck.action = ring_stuck(ring,
3036 acthd);
3037
3038 switch (ring->hangcheck.action) {
3039 case HANGCHECK_IDLE:
3040 case HANGCHECK_WAIT:
3041 case HANGCHECK_ACTIVE:
3042 break;
3043 case HANGCHECK_ACTIVE_LOOP:
3044 ring->hangcheck.score += BUSY;
3045 break;
3046 case HANGCHECK_KICK:
3047 ring->hangcheck.score += KICK;
3048 break;
3049 case HANGCHECK_HUNG:
3050 ring->hangcheck.score += HUNG;
3051 stuck[i] = true;
3052 break;
3053 }
3054 }
3055 } else {
3056 ring->hangcheck.action = HANGCHECK_ACTIVE;
3057
3058 /* Gradually reduce the count so that we catch DoS
3059 * attempts across multiple batches.
3060 */
3061 if (ring->hangcheck.score > 0)
3062 ring->hangcheck.score--;
3063
3064 ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0;
3065 }
3066
3067 ring->hangcheck.seqno = seqno;
3068 ring->hangcheck.acthd = acthd;
3069 busy_count += busy;
3070 }
3071
3072 for_each_ring(ring, dev_priv, i) {
3073 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3074 DRM_INFO("%s on %s\n",
3075 stuck[i] ? "stuck" : "no progress",
3076 ring->name);
3077 rings_hung++;
3078 }
3079 }
3080
3081 if (rings_hung)
3082 return i915_handle_error(dev, true, "Ring hung");
3083
3084 if (busy_count)
3085 /* Reset timer case chip hangs without another request
3086 * being added */
3087 i915_queue_hangcheck(dev);
3088 }
3089
3090 void i915_queue_hangcheck(struct drm_device *dev)
3091 {
3092 struct drm_i915_private *dev_priv = dev->dev_private;
3093 struct timer_list *timer = &dev_priv->gpu_error.hangcheck_timer;
3094
3095 if (!i915.enable_hangcheck)
3096 return;
3097
3098 /* Don't continually defer the hangcheck, but make sure it is active */
3099 if (timer_pending(timer))
3100 return;
3101 mod_timer(timer,
3102 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
3103 }
3104
3105 static void ibx_irq_reset(struct drm_device *dev)
3106 {
3107 struct drm_i915_private *dev_priv = dev->dev_private;
3108
3109 if (HAS_PCH_NOP(dev))
3110 return;
3111
3112 GEN5_IRQ_RESET(SDE);
3113
3114 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3115 I915_WRITE(SERR_INT, 0xffffffff);
3116 }
3117
3118 /*
3119 * SDEIER is also touched by the interrupt handler to work around missed PCH
3120 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3121 * instead we unconditionally enable all PCH interrupt sources here, but then
3122 * only unmask them as needed with SDEIMR.
3123 *
3124 * This function needs to be called before interrupts are enabled.
3125 */
3126 static void ibx_irq_pre_postinstall(struct drm_device *dev)
3127 {
3128 struct drm_i915_private *dev_priv = dev->dev_private;
3129
3130 if (HAS_PCH_NOP(dev))
3131 return;
3132
3133 WARN_ON(I915_READ(SDEIER) != 0);
3134 I915_WRITE(SDEIER, 0xffffffff);
3135 POSTING_READ(SDEIER);
3136 }
3137
3138 static void gen5_gt_irq_reset(struct drm_device *dev)
3139 {
3140 struct drm_i915_private *dev_priv = dev->dev_private;
3141
3142 GEN5_IRQ_RESET(GT);
3143 if (INTEL_INFO(dev)->gen >= 6)
3144 GEN5_IRQ_RESET(GEN6_PM);
3145 }
3146
3147 /* drm_dma.h hooks
3148 */
3149 static void ironlake_irq_reset(struct drm_device *dev)
3150 {
3151 struct drm_i915_private *dev_priv = dev->dev_private;
3152
3153 I915_WRITE(HWSTAM, 0xffffffff);
3154
3155 GEN5_IRQ_RESET(DE);
3156 if (IS_GEN7(dev))
3157 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3158
3159 gen5_gt_irq_reset(dev);
3160
3161 ibx_irq_reset(dev);
3162 }
3163
3164 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3165 {
3166 enum pipe pipe;
3167
3168 I915_WRITE(PORT_HOTPLUG_EN, 0);
3169 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3170
3171 for_each_pipe(dev_priv, pipe)
3172 I915_WRITE(PIPESTAT(pipe), 0xffff);
3173
3174 GEN5_IRQ_RESET(VLV_);
3175 }
3176
3177 static void valleyview_irq_preinstall(struct drm_device *dev)
3178 {
3179 struct drm_i915_private *dev_priv = dev->dev_private;
3180
3181 /* VLV magic */
3182 I915_WRITE(VLV_IMR, 0);
3183 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
3184 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
3185 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
3186
3187 gen5_gt_irq_reset(dev);
3188
3189 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3190
3191 vlv_display_irq_reset(dev_priv);
3192 }
3193
3194 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3195 {
3196 GEN8_IRQ_RESET_NDX(GT, 0);
3197 GEN8_IRQ_RESET_NDX(GT, 1);
3198 GEN8_IRQ_RESET_NDX(GT, 2);
3199 GEN8_IRQ_RESET_NDX(GT, 3);
3200 }
3201
3202 static void gen8_irq_reset(struct drm_device *dev)
3203 {
3204 struct drm_i915_private *dev_priv = dev->dev_private;
3205 int pipe;
3206
3207 I915_WRITE(GEN8_MASTER_IRQ, 0);
3208 POSTING_READ(GEN8_MASTER_IRQ);
3209
3210 gen8_gt_irq_reset(dev_priv);
3211
3212 for_each_pipe(dev_priv, pipe)
3213 if (intel_display_power_is_enabled(dev_priv,
3214 POWER_DOMAIN_PIPE(pipe)))
3215 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3216
3217 GEN5_IRQ_RESET(GEN8_DE_PORT_);
3218 GEN5_IRQ_RESET(GEN8_DE_MISC_);
3219 GEN5_IRQ_RESET(GEN8_PCU_);
3220
3221 ibx_irq_reset(dev);
3222 }
3223
3224 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv)
3225 {
3226 uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3227
3228 spin_lock_irq(&dev_priv->irq_lock);
3229 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B],
3230 ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
3231 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C],
3232 ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
3233 spin_unlock_irq(&dev_priv->irq_lock);
3234 }
3235
3236 static void cherryview_irq_preinstall(struct drm_device *dev)
3237 {
3238 struct drm_i915_private *dev_priv = dev->dev_private;
3239
3240 I915_WRITE(GEN8_MASTER_IRQ, 0);
3241 POSTING_READ(GEN8_MASTER_IRQ);
3242
3243 gen8_gt_irq_reset(dev_priv);
3244
3245 GEN5_IRQ_RESET(GEN8_PCU_);
3246
3247 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3248
3249 vlv_display_irq_reset(dev_priv);
3250 }
3251
3252 static void ibx_hpd_irq_setup(struct drm_device *dev)
3253 {
3254 struct drm_i915_private *dev_priv = dev->dev_private;
3255 struct intel_encoder *intel_encoder;
3256 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
3257
3258 if (HAS_PCH_IBX(dev)) {
3259 hotplug_irqs = SDE_HOTPLUG_MASK;
3260 for_each_intel_encoder(dev, intel_encoder)
3261 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3262 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
3263 } else {
3264 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3265 for_each_intel_encoder(dev, intel_encoder)
3266 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3267 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
3268 }
3269
3270 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3271
3272 /*
3273 * Enable digital hotplug on the PCH, and configure the DP short pulse
3274 * duration to 2ms (which is the minimum in the Display Port spec)
3275 *
3276 * This register is the same on all known PCH chips.
3277 */
3278 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3279 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3280 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3281 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3282 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3283 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3284 }
3285
3286 static void ibx_irq_postinstall(struct drm_device *dev)
3287 {
3288 struct drm_i915_private *dev_priv = dev->dev_private;
3289 u32 mask;
3290
3291 if (HAS_PCH_NOP(dev))
3292 return;
3293
3294 if (HAS_PCH_IBX(dev))
3295 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3296 else
3297 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3298
3299 GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
3300 I915_WRITE(SDEIMR, ~mask);
3301 }
3302
3303 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3304 {
3305 struct drm_i915_private *dev_priv = dev->dev_private;
3306 u32 pm_irqs, gt_irqs;
3307
3308 pm_irqs = gt_irqs = 0;
3309
3310 dev_priv->gt_irq_mask = ~0;
3311 if (HAS_L3_DPF(dev)) {
3312 /* L3 parity interrupt is always unmasked. */
3313 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3314 gt_irqs |= GT_PARITY_ERROR(dev);
3315 }
3316
3317 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3318 if (IS_GEN5(dev)) {
3319 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3320 ILK_BSD_USER_INTERRUPT;
3321 } else {
3322 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3323 }
3324
3325 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3326
3327 if (INTEL_INFO(dev)->gen >= 6) {
3328 /*
3329 * RPS interrupts will get enabled/disabled on demand when RPS
3330 * itself is enabled/disabled.
3331 */
3332 if (HAS_VEBOX(dev))
3333 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3334
3335 dev_priv->pm_irq_mask = 0xffffffff;
3336 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3337 }
3338 }
3339
3340 static int ironlake_irq_postinstall(struct drm_device *dev)
3341 {
3342 struct drm_i915_private *dev_priv = dev->dev_private;
3343 u32 display_mask, extra_mask;
3344
3345 if (INTEL_INFO(dev)->gen >= 7) {
3346 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3347 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3348 DE_PLANEB_FLIP_DONE_IVB |
3349 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3350 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3351 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
3352 } else {
3353 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3354 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3355 DE_AUX_CHANNEL_A |
3356 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3357 DE_POISON);
3358 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3359 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
3360 }
3361
3362 dev_priv->irq_mask = ~display_mask;
3363
3364 I915_WRITE(HWSTAM, 0xeffe);
3365
3366 ibx_irq_pre_postinstall(dev);
3367
3368 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3369
3370 gen5_gt_irq_postinstall(dev);
3371
3372 ibx_irq_postinstall(dev);
3373
3374 if (IS_IRONLAKE_M(dev)) {
3375 /* Enable PCU event interrupts
3376 *
3377 * spinlocking not required here for correctness since interrupt
3378 * setup is guaranteed to run in single-threaded context. But we
3379 * need it to make the assert_spin_locked happy. */
3380 spin_lock_irq(&dev_priv->irq_lock);
3381 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
3382 spin_unlock_irq(&dev_priv->irq_lock);
3383 }
3384
3385 return 0;
3386 }
3387
3388 static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3389 {
3390 u32 pipestat_mask;
3391 u32 iir_mask;
3392 enum pipe pipe;
3393
3394 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3395 PIPE_FIFO_UNDERRUN_STATUS;
3396
3397 for_each_pipe(dev_priv, pipe)
3398 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3399 POSTING_READ(PIPESTAT(PIPE_A));
3400
3401 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3402 PIPE_CRC_DONE_INTERRUPT_STATUS;
3403
3404 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3405 for_each_pipe(dev_priv, pipe)
3406 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3407
3408 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3409 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3410 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3411 if (IS_CHERRYVIEW(dev_priv))
3412 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3413 dev_priv->irq_mask &= ~iir_mask;
3414
3415 I915_WRITE(VLV_IIR, iir_mask);
3416 I915_WRITE(VLV_IIR, iir_mask);
3417 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3418 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3419 POSTING_READ(VLV_IMR);
3420 }
3421
3422 static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3423 {
3424 u32 pipestat_mask;
3425 u32 iir_mask;
3426 enum pipe pipe;
3427
3428 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3429 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3430 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3431 if (IS_CHERRYVIEW(dev_priv))
3432 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3433
3434 dev_priv->irq_mask |= iir_mask;
3435 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3436 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3437 I915_WRITE(VLV_IIR, iir_mask);
3438 I915_WRITE(VLV_IIR, iir_mask);
3439 POSTING_READ(VLV_IIR);
3440
3441 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3442 PIPE_CRC_DONE_INTERRUPT_STATUS;
3443
3444 i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3445 for_each_pipe(dev_priv, pipe)
3446 i915_disable_pipestat(dev_priv, pipe, pipestat_mask);
3447
3448 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3449 PIPE_FIFO_UNDERRUN_STATUS;
3450
3451 for_each_pipe(dev_priv, pipe)
3452 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3453 POSTING_READ(PIPESTAT(PIPE_A));
3454 }
3455
3456 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3457 {
3458 assert_spin_locked(&dev_priv->irq_lock);
3459
3460 if (dev_priv->display_irqs_enabled)
3461 return;
3462
3463 dev_priv->display_irqs_enabled = true;
3464
3465 if (intel_irqs_enabled(dev_priv))
3466 valleyview_display_irqs_install(dev_priv);
3467 }
3468
3469 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3470 {
3471 assert_spin_locked(&dev_priv->irq_lock);
3472
3473 if (!dev_priv->display_irqs_enabled)
3474 return;
3475
3476 dev_priv->display_irqs_enabled = false;
3477
3478 if (intel_irqs_enabled(dev_priv))
3479 valleyview_display_irqs_uninstall(dev_priv);
3480 }
3481
3482 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3483 {
3484 dev_priv->irq_mask = ~0;
3485
3486 I915_WRITE(PORT_HOTPLUG_EN, 0);
3487 POSTING_READ(PORT_HOTPLUG_EN);
3488
3489 I915_WRITE(VLV_IIR, 0xffffffff);
3490 I915_WRITE(VLV_IIR, 0xffffffff);
3491 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3492 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3493 POSTING_READ(VLV_IMR);
3494
3495 /* Interrupt setup is already guaranteed to be single-threaded, this is
3496 * just to make the assert_spin_locked check happy. */
3497 spin_lock_irq(&dev_priv->irq_lock);
3498 if (dev_priv->display_irqs_enabled)
3499 valleyview_display_irqs_install(dev_priv);
3500 spin_unlock_irq(&dev_priv->irq_lock);
3501 }
3502
3503 static int valleyview_irq_postinstall(struct drm_device *dev)
3504 {
3505 struct drm_i915_private *dev_priv = dev->dev_private;
3506
3507 vlv_display_irq_postinstall(dev_priv);
3508
3509 gen5_gt_irq_postinstall(dev);
3510
3511 /* ack & enable invalid PTE error interrupts */
3512 #if 0 /* FIXME: add support to irq handler for checking these bits */
3513 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3514 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3515 #endif
3516
3517 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3518
3519 return 0;
3520 }
3521
3522 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3523 {
3524 /* These are interrupts we'll toggle with the ring mask register */
3525 uint32_t gt_interrupts[] = {
3526 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3527 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3528 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3529 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3530 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3531 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3532 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3533 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3534 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3535 0,
3536 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3537 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3538 };
3539
3540 dev_priv->pm_irq_mask = 0xffffffff;
3541 GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3542 GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3543 /*
3544 * RPS interrupts will get enabled/disabled on demand when RPS itself
3545 * is enabled/disabled.
3546 */
3547 GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
3548 GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3549 }
3550
3551 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3552 {
3553 uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3554 uint32_t de_pipe_enables;
3555 int pipe;
3556 u32 aux_en = GEN8_AUX_CHANNEL_A;
3557
3558 if (IS_GEN9(dev_priv)) {
3559 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3560 GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3561 aux_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3562 GEN9_AUX_CHANNEL_D;
3563 } else
3564 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3565 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3566
3567 de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3568 GEN8_PIPE_FIFO_UNDERRUN;
3569
3570 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3571 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3572 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3573
3574 for_each_pipe(dev_priv, pipe)
3575 if (intel_display_power_is_enabled(dev_priv,
3576 POWER_DOMAIN_PIPE(pipe)))
3577 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3578 dev_priv->de_irq_mask[pipe],
3579 de_pipe_enables);
3580
3581 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~aux_en, aux_en);
3582 }
3583
3584 static int gen8_irq_postinstall(struct drm_device *dev)
3585 {
3586 struct drm_i915_private *dev_priv = dev->dev_private;
3587
3588 ibx_irq_pre_postinstall(dev);
3589
3590 gen8_gt_irq_postinstall(dev_priv);
3591 gen8_de_irq_postinstall(dev_priv);
3592
3593 ibx_irq_postinstall(dev);
3594
3595 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3596 POSTING_READ(GEN8_MASTER_IRQ);
3597
3598 return 0;
3599 }
3600
3601 static int cherryview_irq_postinstall(struct drm_device *dev)
3602 {
3603 struct drm_i915_private *dev_priv = dev->dev_private;
3604
3605 vlv_display_irq_postinstall(dev_priv);
3606
3607 gen8_gt_irq_postinstall(dev_priv);
3608
3609 I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
3610 POSTING_READ(GEN8_MASTER_IRQ);
3611
3612 return 0;
3613 }
3614
3615 static void gen8_irq_uninstall(struct drm_device *dev)
3616 {
3617 struct drm_i915_private *dev_priv = dev->dev_private;
3618
3619 if (!dev_priv)
3620 return;
3621
3622 gen8_irq_reset(dev);
3623 }
3624
3625 static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv)
3626 {
3627 /* Interrupt setup is already guaranteed to be single-threaded, this is
3628 * just to make the assert_spin_locked check happy. */
3629 spin_lock_irq(&dev_priv->irq_lock);
3630 if (dev_priv->display_irqs_enabled)
3631 valleyview_display_irqs_uninstall(dev_priv);
3632 spin_unlock_irq(&dev_priv->irq_lock);
3633
3634 vlv_display_irq_reset(dev_priv);
3635
3636 dev_priv->irq_mask = ~0;
3637 }
3638
3639 static void valleyview_irq_uninstall(struct drm_device *dev)
3640 {
3641 struct drm_i915_private *dev_priv = dev->dev_private;
3642
3643 if (!dev_priv)
3644 return;
3645
3646 I915_WRITE(VLV_MASTER_IER, 0);
3647
3648 gen5_gt_irq_reset(dev);
3649
3650 I915_WRITE(HWSTAM, 0xffffffff);
3651
3652 vlv_display_irq_uninstall(dev_priv);
3653 }
3654
3655 static void cherryview_irq_uninstall(struct drm_device *dev)
3656 {
3657 struct drm_i915_private *dev_priv = dev->dev_private;
3658
3659 if (!dev_priv)
3660 return;
3661
3662 I915_WRITE(GEN8_MASTER_IRQ, 0);
3663 POSTING_READ(GEN8_MASTER_IRQ);
3664
3665 gen8_gt_irq_reset(dev_priv);
3666
3667 GEN5_IRQ_RESET(GEN8_PCU_);
3668
3669 vlv_display_irq_uninstall(dev_priv);
3670 }
3671
3672 static void ironlake_irq_uninstall(struct drm_device *dev)
3673 {
3674 struct drm_i915_private *dev_priv = dev->dev_private;
3675
3676 if (!dev_priv)
3677 return;
3678
3679 ironlake_irq_reset(dev);
3680 }
3681
3682 static void i8xx_irq_preinstall(struct drm_device * dev)
3683 {
3684 struct drm_i915_private *dev_priv = dev->dev_private;
3685 int pipe;
3686
3687 for_each_pipe(dev_priv, pipe)
3688 I915_WRITE(PIPESTAT(pipe), 0);
3689 I915_WRITE16(IMR, 0xffff);
3690 I915_WRITE16(IER, 0x0);
3691 POSTING_READ16(IER);
3692 }
3693
3694 static int i8xx_irq_postinstall(struct drm_device *dev)
3695 {
3696 struct drm_i915_private *dev_priv = dev->dev_private;
3697
3698 I915_WRITE16(EMR,
3699 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3700
3701 /* Unmask the interrupts that we always want on. */
3702 dev_priv->irq_mask =
3703 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3704 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3705 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3706 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3707 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3708 I915_WRITE16(IMR, dev_priv->irq_mask);
3709
3710 I915_WRITE16(IER,
3711 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3712 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3713 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3714 I915_USER_INTERRUPT);
3715 POSTING_READ16(IER);
3716
3717 /* Interrupt setup is already guaranteed to be single-threaded, this is
3718 * just to make the assert_spin_locked check happy. */
3719 spin_lock_irq(&dev_priv->irq_lock);
3720 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3721 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3722 spin_unlock_irq(&dev_priv->irq_lock);
3723
3724 return 0;
3725 }
3726
3727 /*
3728 * Returns true when a page flip has completed.
3729 */
3730 static bool i8xx_handle_vblank(struct drm_device *dev,
3731 int plane, int pipe, u32 iir)
3732 {
3733 struct drm_i915_private *dev_priv = dev->dev_private;
3734 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3735
3736 if (!intel_pipe_handle_vblank(dev, pipe))
3737 return false;
3738
3739 if ((iir & flip_pending) == 0)
3740 goto check_page_flip;
3741
3742 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3743 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3744 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3745 * the flip is completed (no longer pending). Since this doesn't raise
3746 * an interrupt per se, we watch for the change at vblank.
3747 */
3748 if (I915_READ16(ISR) & flip_pending)
3749 goto check_page_flip;
3750
3751 intel_prepare_page_flip(dev, plane);
3752 intel_finish_page_flip(dev, pipe);
3753 return true;
3754
3755 check_page_flip:
3756 intel_check_page_flip(dev, pipe);
3757 return false;
3758 }
3759
3760 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3761 {
3762 struct drm_device *dev = arg;
3763 struct drm_i915_private *dev_priv = dev->dev_private;
3764 u16 iir, new_iir;
3765 u32 pipe_stats[2];
3766 int pipe;
3767 u16 flip_mask =
3768 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3769 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3770
3771 iir = I915_READ16(IIR);
3772 if (iir == 0)
3773 return IRQ_NONE;
3774
3775 while (iir & ~flip_mask) {
3776 /* Can't rely on pipestat interrupt bit in iir as it might
3777 * have been cleared after the pipestat interrupt was received.
3778 * It doesn't set the bit in iir again, but it still produces
3779 * interrupts (for non-MSI).
3780 */
3781 spin_lock(&dev_priv->irq_lock);
3782 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3783 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3784
3785 for_each_pipe(dev_priv, pipe) {
3786 int reg = PIPESTAT(pipe);
3787 pipe_stats[pipe] = I915_READ(reg);
3788
3789 /*
3790 * Clear the PIPE*STAT regs before the IIR
3791 */
3792 if (pipe_stats[pipe] & 0x8000ffff)
3793 I915_WRITE(reg, pipe_stats[pipe]);
3794 }
3795 spin_unlock(&dev_priv->irq_lock);
3796
3797 I915_WRITE16(IIR, iir & ~flip_mask);
3798 new_iir = I915_READ16(IIR); /* Flush posted writes */
3799
3800 if (iir & I915_USER_INTERRUPT)
3801 notify_ring(dev, &dev_priv->ring[RCS]);
3802
3803 for_each_pipe(dev_priv, pipe) {
3804 int plane = pipe;
3805 if (HAS_FBC(dev))
3806 plane = !plane;
3807
3808 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3809 i8xx_handle_vblank(dev, plane, pipe, iir))
3810 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3811
3812 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3813 i9xx_pipe_crc_irq_handler(dev, pipe);
3814
3815 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3816 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3817 pipe);
3818 }
3819
3820 iir = new_iir;
3821 }
3822
3823 return IRQ_HANDLED;
3824 }
3825
3826 static void i8xx_irq_uninstall(struct drm_device * dev)
3827 {
3828 struct drm_i915_private *dev_priv = dev->dev_private;
3829 int pipe;
3830
3831 for_each_pipe(dev_priv, pipe) {
3832 /* Clear enable bits; then clear status bits */
3833 I915_WRITE(PIPESTAT(pipe), 0);
3834 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3835 }
3836 I915_WRITE16(IMR, 0xffff);
3837 I915_WRITE16(IER, 0x0);
3838 I915_WRITE16(IIR, I915_READ16(IIR));
3839 }
3840
3841 static void i915_irq_preinstall(struct drm_device * dev)
3842 {
3843 struct drm_i915_private *dev_priv = dev->dev_private;
3844 int pipe;
3845
3846 if (I915_HAS_HOTPLUG(dev)) {
3847 I915_WRITE(PORT_HOTPLUG_EN, 0);
3848 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3849 }
3850
3851 I915_WRITE16(HWSTAM, 0xeffe);
3852 for_each_pipe(dev_priv, pipe)
3853 I915_WRITE(PIPESTAT(pipe), 0);
3854 I915_WRITE(IMR, 0xffffffff);
3855 I915_WRITE(IER, 0x0);
3856 POSTING_READ(IER);
3857 }
3858
3859 static int i915_irq_postinstall(struct drm_device *dev)
3860 {
3861 struct drm_i915_private *dev_priv = dev->dev_private;
3862 u32 enable_mask;
3863
3864 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3865
3866 /* Unmask the interrupts that we always want on. */
3867 dev_priv->irq_mask =
3868 ~(I915_ASLE_INTERRUPT |
3869 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3870 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3871 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3872 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3873 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3874
3875 enable_mask =
3876 I915_ASLE_INTERRUPT |
3877 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3878 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3879 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3880 I915_USER_INTERRUPT;
3881
3882 if (I915_HAS_HOTPLUG(dev)) {
3883 I915_WRITE(PORT_HOTPLUG_EN, 0);
3884 POSTING_READ(PORT_HOTPLUG_EN);
3885
3886 /* Enable in IER... */
3887 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3888 /* and unmask in IMR */
3889 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3890 }
3891
3892 I915_WRITE(IMR, dev_priv->irq_mask);
3893 I915_WRITE(IER, enable_mask);
3894 POSTING_READ(IER);
3895
3896 i915_enable_asle_pipestat(dev);
3897
3898 /* Interrupt setup is already guaranteed to be single-threaded, this is
3899 * just to make the assert_spin_locked check happy. */
3900 spin_lock_irq(&dev_priv->irq_lock);
3901 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3902 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3903 spin_unlock_irq(&dev_priv->irq_lock);
3904
3905 return 0;
3906 }
3907
3908 /*
3909 * Returns true when a page flip has completed.
3910 */
3911 static bool i915_handle_vblank(struct drm_device *dev,
3912 int plane, int pipe, u32 iir)
3913 {
3914 struct drm_i915_private *dev_priv = dev->dev_private;
3915 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3916
3917 if (!intel_pipe_handle_vblank(dev, pipe))
3918 return false;
3919
3920 if ((iir & flip_pending) == 0)
3921 goto check_page_flip;
3922
3923 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3924 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3925 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3926 * the flip is completed (no longer pending). Since this doesn't raise
3927 * an interrupt per se, we watch for the change at vblank.
3928 */
3929 if (I915_READ(ISR) & flip_pending)
3930 goto check_page_flip;
3931
3932 intel_prepare_page_flip(dev, plane);
3933 intel_finish_page_flip(dev, pipe);
3934 return true;
3935
3936 check_page_flip:
3937 intel_check_page_flip(dev, pipe);
3938 return false;
3939 }
3940
3941 static irqreturn_t i915_irq_handler(int irq, void *arg)
3942 {
3943 struct drm_device *dev = arg;
3944 struct drm_i915_private *dev_priv = dev->dev_private;
3945 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3946 u32 flip_mask =
3947 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3948 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3949 int pipe, ret = IRQ_NONE;
3950
3951 iir = I915_READ(IIR);
3952 do {
3953 bool irq_received = (iir & ~flip_mask) != 0;
3954 bool blc_event = false;
3955
3956 /* Can't rely on pipestat interrupt bit in iir as it might
3957 * have been cleared after the pipestat interrupt was received.
3958 * It doesn't set the bit in iir again, but it still produces
3959 * interrupts (for non-MSI).
3960 */
3961 spin_lock(&dev_priv->irq_lock);
3962 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3963 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3964
3965 for_each_pipe(dev_priv, pipe) {
3966 int reg = PIPESTAT(pipe);
3967 pipe_stats[pipe] = I915_READ(reg);
3968
3969 /* Clear the PIPE*STAT regs before the IIR */
3970 if (pipe_stats[pipe] & 0x8000ffff) {
3971 I915_WRITE(reg, pipe_stats[pipe]);
3972 irq_received = true;
3973 }
3974 }
3975 spin_unlock(&dev_priv->irq_lock);
3976
3977 if (!irq_received)
3978 break;
3979
3980 /* Consume port. Then clear IIR or we'll miss events */
3981 if (I915_HAS_HOTPLUG(dev) &&
3982 iir & I915_DISPLAY_PORT_INTERRUPT)
3983 i9xx_hpd_irq_handler(dev);
3984
3985 I915_WRITE(IIR, iir & ~flip_mask);
3986 new_iir = I915_READ(IIR); /* Flush posted writes */
3987
3988 if (iir & I915_USER_INTERRUPT)
3989 notify_ring(dev, &dev_priv->ring[RCS]);
3990
3991 for_each_pipe(dev_priv, pipe) {
3992 int plane = pipe;
3993 if (HAS_FBC(dev))
3994 plane = !plane;
3995
3996 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3997 i915_handle_vblank(dev, plane, pipe, iir))
3998 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3999
4000 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4001 blc_event = true;
4002
4003 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4004 i9xx_pipe_crc_irq_handler(dev, pipe);
4005
4006 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4007 intel_cpu_fifo_underrun_irq_handler(dev_priv,
4008 pipe);
4009 }
4010
4011 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4012 intel_opregion_asle_intr(dev);
4013
4014 /* With MSI, interrupts are only generated when iir
4015 * transitions from zero to nonzero. If another bit got
4016 * set while we were handling the existing iir bits, then
4017 * we would never get another interrupt.
4018 *
4019 * This is fine on non-MSI as well, as if we hit this path
4020 * we avoid exiting the interrupt handler only to generate
4021 * another one.
4022 *
4023 * Note that for MSI this could cause a stray interrupt report
4024 * if an interrupt landed in the time between writing IIR and
4025 * the posting read. This should be rare enough to never
4026 * trigger the 99% of 100,000 interrupts test for disabling
4027 * stray interrupts.
4028 */
4029 ret = IRQ_HANDLED;
4030 iir = new_iir;
4031 } while (iir & ~flip_mask);
4032
4033 return ret;
4034 }
4035
4036 static void i915_irq_uninstall(struct drm_device * dev)
4037 {
4038 struct drm_i915_private *dev_priv = dev->dev_private;
4039 int pipe;
4040
4041 if (I915_HAS_HOTPLUG(dev)) {
4042 I915_WRITE(PORT_HOTPLUG_EN, 0);
4043 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4044 }
4045
4046 I915_WRITE16(HWSTAM, 0xffff);
4047 for_each_pipe(dev_priv, pipe) {
4048 /* Clear enable bits; then clear status bits */
4049 I915_WRITE(PIPESTAT(pipe), 0);
4050 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4051 }
4052 I915_WRITE(IMR, 0xffffffff);
4053 I915_WRITE(IER, 0x0);
4054
4055 I915_WRITE(IIR, I915_READ(IIR));
4056 }
4057
4058 static void i965_irq_preinstall(struct drm_device * dev)
4059 {
4060 struct drm_i915_private *dev_priv = dev->dev_private;
4061 int pipe;
4062
4063 I915_WRITE(PORT_HOTPLUG_EN, 0);
4064 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4065
4066 I915_WRITE(HWSTAM, 0xeffe);
4067 for_each_pipe(dev_priv, pipe)
4068 I915_WRITE(PIPESTAT(pipe), 0);
4069 I915_WRITE(IMR, 0xffffffff);
4070 I915_WRITE(IER, 0x0);
4071 POSTING_READ(IER);
4072 }
4073
4074 static int i965_irq_postinstall(struct drm_device *dev)
4075 {
4076 struct drm_i915_private *dev_priv = dev->dev_private;
4077 u32 enable_mask;
4078 u32 error_mask;
4079
4080 /* Unmask the interrupts that we always want on. */
4081 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4082 I915_DISPLAY_PORT_INTERRUPT |
4083 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4084 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4085 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4086 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4087 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4088
4089 enable_mask = ~dev_priv->irq_mask;
4090 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4091 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4092 enable_mask |= I915_USER_INTERRUPT;
4093
4094 if (IS_G4X(dev))
4095 enable_mask |= I915_BSD_USER_INTERRUPT;
4096
4097 /* Interrupt setup is already guaranteed to be single-threaded, this is
4098 * just to make the assert_spin_locked check happy. */
4099 spin_lock_irq(&dev_priv->irq_lock);
4100 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4101 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4102 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4103 spin_unlock_irq(&dev_priv->irq_lock);
4104
4105 /*
4106 * Enable some error detection, note the instruction error mask
4107 * bit is reserved, so we leave it masked.
4108 */
4109 if (IS_G4X(dev)) {
4110 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4111 GM45_ERROR_MEM_PRIV |
4112 GM45_ERROR_CP_PRIV |
4113 I915_ERROR_MEMORY_REFRESH);
4114 } else {
4115 error_mask = ~(I915_ERROR_PAGE_TABLE |
4116 I915_ERROR_MEMORY_REFRESH);
4117 }
4118 I915_WRITE(EMR, error_mask);
4119
4120 I915_WRITE(IMR, dev_priv->irq_mask);
4121 I915_WRITE(IER, enable_mask);
4122 POSTING_READ(IER);
4123
4124 I915_WRITE(PORT_HOTPLUG_EN, 0);
4125 POSTING_READ(PORT_HOTPLUG_EN);
4126
4127 i915_enable_asle_pipestat(dev);
4128
4129 return 0;
4130 }
4131
4132 static void i915_hpd_irq_setup(struct drm_device *dev)
4133 {
4134 struct drm_i915_private *dev_priv = dev->dev_private;
4135 struct intel_encoder *intel_encoder;
4136 u32 hotplug_en;
4137
4138 assert_spin_locked(&dev_priv->irq_lock);
4139
4140 if (I915_HAS_HOTPLUG(dev)) {
4141 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
4142 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
4143 /* Note HDMI and DP share hotplug bits */
4144 /* enable bits are the same for all generations */
4145 for_each_intel_encoder(dev, intel_encoder)
4146 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
4147 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
4148 /* Programming the CRT detection parameters tends
4149 to generate a spurious hotplug event about three
4150 seconds later. So just do it once.
4151 */
4152 if (IS_G4X(dev))
4153 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4154 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
4155 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4156
4157 /* Ignore TV since it's buggy */
4158 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
4159 }
4160 }
4161
4162 static irqreturn_t i965_irq_handler(int irq, void *arg)
4163 {
4164 struct drm_device *dev = arg;
4165 struct drm_i915_private *dev_priv = dev->dev_private;
4166 u32 iir, new_iir;
4167 u32 pipe_stats[I915_MAX_PIPES];
4168 int ret = IRQ_NONE, pipe;
4169 u32 flip_mask =
4170 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4171 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4172
4173 iir = I915_READ(IIR);
4174
4175 for (;;) {
4176 bool irq_received = (iir & ~flip_mask) != 0;
4177 bool blc_event = false;
4178
4179 /* Can't rely on pipestat interrupt bit in iir as it might
4180 * have been cleared after the pipestat interrupt was received.
4181 * It doesn't set the bit in iir again, but it still produces
4182 * interrupts (for non-MSI).
4183 */
4184 spin_lock(&dev_priv->irq_lock);
4185 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4186 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4187
4188 for_each_pipe(dev_priv, pipe) {
4189 int reg = PIPESTAT(pipe);
4190 pipe_stats[pipe] = I915_READ(reg);
4191
4192 /*
4193 * Clear the PIPE*STAT regs before the IIR
4194 */
4195 if (pipe_stats[pipe] & 0x8000ffff) {
4196 I915_WRITE(reg, pipe_stats[pipe]);
4197 irq_received = true;
4198 }
4199 }
4200 spin_unlock(&dev_priv->irq_lock);
4201
4202 if (!irq_received)
4203 break;
4204
4205 ret = IRQ_HANDLED;
4206
4207 /* Consume port. Then clear IIR or we'll miss events */
4208 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4209 i9xx_hpd_irq_handler(dev);
4210
4211 I915_WRITE(IIR, iir & ~flip_mask);
4212 new_iir = I915_READ(IIR); /* Flush posted writes */
4213
4214 if (iir & I915_USER_INTERRUPT)
4215 notify_ring(dev, &dev_priv->ring[RCS]);
4216 if (iir & I915_BSD_USER_INTERRUPT)
4217 notify_ring(dev, &dev_priv->ring[VCS]);
4218
4219 for_each_pipe(dev_priv, pipe) {
4220 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4221 i915_handle_vblank(dev, pipe, pipe, iir))
4222 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4223
4224 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4225 blc_event = true;
4226
4227 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4228 i9xx_pipe_crc_irq_handler(dev, pipe);
4229
4230 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4231 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4232 }
4233
4234 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4235 intel_opregion_asle_intr(dev);
4236
4237 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4238 gmbus_irq_handler(dev);
4239
4240 /* With MSI, interrupts are only generated when iir
4241 * transitions from zero to nonzero. If another bit got
4242 * set while we were handling the existing iir bits, then
4243 * we would never get another interrupt.
4244 *
4245 * This is fine on non-MSI as well, as if we hit this path
4246 * we avoid exiting the interrupt handler only to generate
4247 * another one.
4248 *
4249 * Note that for MSI this could cause a stray interrupt report
4250 * if an interrupt landed in the time between writing IIR and
4251 * the posting read. This should be rare enough to never
4252 * trigger the 99% of 100,000 interrupts test for disabling
4253 * stray interrupts.
4254 */
4255 iir = new_iir;
4256 }
4257
4258 return ret;
4259 }
4260
4261 static void i965_irq_uninstall(struct drm_device * dev)
4262 {
4263 struct drm_i915_private *dev_priv = dev->dev_private;
4264 int pipe;
4265
4266 if (!dev_priv)
4267 return;
4268
4269 I915_WRITE(PORT_HOTPLUG_EN, 0);
4270 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4271
4272 I915_WRITE(HWSTAM, 0xffffffff);
4273 for_each_pipe(dev_priv, pipe)
4274 I915_WRITE(PIPESTAT(pipe), 0);
4275 I915_WRITE(IMR, 0xffffffff);
4276 I915_WRITE(IER, 0x0);
4277
4278 for_each_pipe(dev_priv, pipe)
4279 I915_WRITE(PIPESTAT(pipe),
4280 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4281 I915_WRITE(IIR, I915_READ(IIR));
4282 }
4283
4284 static void intel_hpd_irq_reenable_work(struct work_struct *work)
4285 {
4286 struct drm_i915_private *dev_priv =
4287 container_of(work, typeof(*dev_priv),
4288 hotplug_reenable_work.work);
4289 struct drm_device *dev = dev_priv->dev;
4290 struct drm_mode_config *mode_config = &dev->mode_config;
4291 int i;
4292
4293 intel_runtime_pm_get(dev_priv);
4294
4295 spin_lock_irq(&dev_priv->irq_lock);
4296 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
4297 struct drm_connector *connector;
4298
4299 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
4300 continue;
4301
4302 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4303
4304 list_for_each_entry(connector, &mode_config->connector_list, head) {
4305 struct intel_connector *intel_connector = to_intel_connector(connector);
4306
4307 if (intel_connector->encoder->hpd_pin == i) {
4308 if (connector->polled != intel_connector->polled)
4309 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
4310 connector->name);
4311 connector->polled = intel_connector->polled;
4312 if (!connector->polled)
4313 connector->polled = DRM_CONNECTOR_POLL_HPD;
4314 }
4315 }
4316 }
4317 if (dev_priv->display.hpd_irq_setup)
4318 dev_priv->display.hpd_irq_setup(dev);
4319 spin_unlock_irq(&dev_priv->irq_lock);
4320
4321 intel_runtime_pm_put(dev_priv);
4322 }
4323
4324 /**
4325 * intel_irq_init - initializes irq support
4326 * @dev_priv: i915 device instance
4327 *
4328 * This function initializes all the irq support including work items, timers
4329 * and all the vtables. It does not setup the interrupt itself though.
4330 */
4331 void intel_irq_init(struct drm_i915_private *dev_priv)
4332 {
4333 struct drm_device *dev = dev_priv->dev;
4334
4335 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
4336 INIT_WORK(&dev_priv->dig_port_work, i915_digport_work_func);
4337 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
4338 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4339 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4340
4341 /* Let's track the enabled rps events */
4342 if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
4343 /* WaGsvRC0ResidencyMethod:vlv */
4344 dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
4345 else
4346 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4347
4348 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
4349 i915_hangcheck_elapsed,
4350 (unsigned long) dev);
4351 INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work,
4352 intel_hpd_irq_reenable_work);
4353
4354 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4355
4356 if (IS_GEN2(dev_priv)) {
4357 dev->max_vblank_count = 0;
4358 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4359 } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4360 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4361 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
4362 } else {
4363 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4364 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4365 }
4366
4367 /*
4368 * Opt out of the vblank disable timer on everything except gen2.
4369 * Gen2 doesn't have a hardware frame counter and so depends on
4370 * vblank interrupts to produce sane vblank seuquence numbers.
4371 */
4372 if (!IS_GEN2(dev_priv))
4373 dev->vblank_disable_immediate = true;
4374
4375 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
4376 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4377 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4378 }
4379
4380 if (IS_CHERRYVIEW(dev_priv)) {
4381 dev->driver->irq_handler = cherryview_irq_handler;
4382 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4383 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4384 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4385 dev->driver->enable_vblank = valleyview_enable_vblank;
4386 dev->driver->disable_vblank = valleyview_disable_vblank;
4387 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4388 } else if (IS_VALLEYVIEW(dev_priv)) {
4389 dev->driver->irq_handler = valleyview_irq_handler;
4390 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4391 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4392 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4393 dev->driver->enable_vblank = valleyview_enable_vblank;
4394 dev->driver->disable_vblank = valleyview_disable_vblank;
4395 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4396 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
4397 dev->driver->irq_handler = gen8_irq_handler;
4398 dev->driver->irq_preinstall = gen8_irq_reset;
4399 dev->driver->irq_postinstall = gen8_irq_postinstall;
4400 dev->driver->irq_uninstall = gen8_irq_uninstall;
4401 dev->driver->enable_vblank = gen8_enable_vblank;
4402 dev->driver->disable_vblank = gen8_disable_vblank;
4403 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4404 } else if (HAS_PCH_SPLIT(dev)) {
4405 dev->driver->irq_handler = ironlake_irq_handler;
4406 dev->driver->irq_preinstall = ironlake_irq_reset;
4407 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4408 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4409 dev->driver->enable_vblank = ironlake_enable_vblank;
4410 dev->driver->disable_vblank = ironlake_disable_vblank;
4411 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4412 } else {
4413 if (INTEL_INFO(dev_priv)->gen == 2) {
4414 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4415 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4416 dev->driver->irq_handler = i8xx_irq_handler;
4417 dev->driver->irq_uninstall = i8xx_irq_uninstall;
4418 } else if (INTEL_INFO(dev_priv)->gen == 3) {
4419 dev->driver->irq_preinstall = i915_irq_preinstall;
4420 dev->driver->irq_postinstall = i915_irq_postinstall;
4421 dev->driver->irq_uninstall = i915_irq_uninstall;
4422 dev->driver->irq_handler = i915_irq_handler;
4423 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4424 } else {
4425 dev->driver->irq_preinstall = i965_irq_preinstall;
4426 dev->driver->irq_postinstall = i965_irq_postinstall;
4427 dev->driver->irq_uninstall = i965_irq_uninstall;
4428 dev->driver->irq_handler = i965_irq_handler;
4429 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4430 }
4431 dev->driver->enable_vblank = i915_enable_vblank;
4432 dev->driver->disable_vblank = i915_disable_vblank;
4433 }
4434 }
4435
4436 /**
4437 * intel_hpd_init - initializes and enables hpd support
4438 * @dev_priv: i915 device instance
4439 *
4440 * This function enables the hotplug support. It requires that interrupts have
4441 * already been enabled with intel_irq_init_hw(). From this point on hotplug and
4442 * poll request can run concurrently to other code, so locking rules must be
4443 * obeyed.
4444 *
4445 * This is a separate step from interrupt enabling to simplify the locking rules
4446 * in the driver load and resume code.
4447 */
4448 void intel_hpd_init(struct drm_i915_private *dev_priv)
4449 {
4450 struct drm_device *dev = dev_priv->dev;
4451 struct drm_mode_config *mode_config = &dev->mode_config;
4452 struct drm_connector *connector;
4453 int i;
4454
4455 for (i = 1; i < HPD_NUM_PINS; i++) {
4456 dev_priv->hpd_stats[i].hpd_cnt = 0;
4457 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4458 }
4459 list_for_each_entry(connector, &mode_config->connector_list, head) {
4460 struct intel_connector *intel_connector = to_intel_connector(connector);
4461 connector->polled = intel_connector->polled;
4462 if (connector->encoder && !connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
4463 connector->polled = DRM_CONNECTOR_POLL_HPD;
4464 if (intel_connector->mst_port)
4465 connector->polled = DRM_CONNECTOR_POLL_HPD;
4466 }
4467
4468 /* Interrupt setup is already guaranteed to be single-threaded, this is
4469 * just to make the assert_spin_locked checks happy. */
4470 spin_lock_irq(&dev_priv->irq_lock);
4471 if (dev_priv->display.hpd_irq_setup)
4472 dev_priv->display.hpd_irq_setup(dev);
4473 spin_unlock_irq(&dev_priv->irq_lock);
4474 }
4475
4476 /**
4477 * intel_irq_install - enables the hardware interrupt
4478 * @dev_priv: i915 device instance
4479 *
4480 * This function enables the hardware interrupt handling, but leaves the hotplug
4481 * handling still disabled. It is called after intel_irq_init().
4482 *
4483 * In the driver load and resume code we need working interrupts in a few places
4484 * but don't want to deal with the hassle of concurrent probe and hotplug
4485 * workers. Hence the split into this two-stage approach.
4486 */
4487 int intel_irq_install(struct drm_i915_private *dev_priv)
4488 {
4489 /*
4490 * We enable some interrupt sources in our postinstall hooks, so mark
4491 * interrupts as enabled _before_ actually enabling them to avoid
4492 * special cases in our ordering checks.
4493 */
4494 dev_priv->pm.irqs_enabled = true;
4495
4496 return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
4497 }
4498
4499 /**
4500 * intel_irq_uninstall - finilizes all irq handling
4501 * @dev_priv: i915 device instance
4502 *
4503 * This stops interrupt and hotplug handling and unregisters and frees all
4504 * resources acquired in the init functions.
4505 */
4506 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4507 {
4508 drm_irq_uninstall(dev_priv->dev);
4509 intel_hpd_cancel_work(dev_priv);
4510 dev_priv->pm.irqs_enabled = false;
4511 }
4512
4513 /**
4514 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4515 * @dev_priv: i915 device instance
4516 *
4517 * This function is used to disable interrupts at runtime, both in the runtime
4518 * pm and the system suspend/resume code.
4519 */
4520 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4521 {
4522 dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
4523 dev_priv->pm.irqs_enabled = false;
4524 }
4525
4526 /**
4527 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4528 * @dev_priv: i915 device instance
4529 *
4530 * This function is used to enable interrupts at runtime, both in the runtime
4531 * pm and the system suspend/resume code.
4532 */
4533 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4534 {
4535 dev_priv->pm.irqs_enabled = true;
4536 dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
4537 dev_priv->dev->driver->irq_postinstall(dev_priv->dev);
4538 }
Linux kernel - Deliverables
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