1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
34 #include <drm/i915_drm.h>
36 #include "i915_trace.h"
37 #include "intel_drv.h"
39 static const u32 hpd_ibx
[] = {
40 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
41 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
42 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
43 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
44 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
47 static const u32 hpd_cpt
[] = {
48 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
49 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG_CPT
,
50 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
51 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
52 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
55 static const u32 hpd_mask_i915
[] = {
56 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
57 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
58 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
59 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
60 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
61 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
64 static const u32 hpd_status_gen4
[] = {
65 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
66 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
67 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
68 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
69 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
70 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
73 static const u32 hpd_status_i915
[] = { /* i915 and valleyview are the same */
74 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
75 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
76 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
77 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
78 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
79 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
82 /* For display hotplug interrupt */
84 ironlake_enable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
86 assert_spin_locked(&dev_priv
->irq_lock
);
88 if (dev_priv
->pc8
.irqs_disabled
) {
89 WARN(1, "IRQs disabled\n");
90 dev_priv
->pc8
.regsave
.deimr
&= ~mask
;
94 if ((dev_priv
->irq_mask
& mask
) != 0) {
95 dev_priv
->irq_mask
&= ~mask
;
96 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
102 ironlake_disable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
104 assert_spin_locked(&dev_priv
->irq_lock
);
106 if (dev_priv
->pc8
.irqs_disabled
) {
107 WARN(1, "IRQs disabled\n");
108 dev_priv
->pc8
.regsave
.deimr
|= mask
;
112 if ((dev_priv
->irq_mask
& mask
) != mask
) {
113 dev_priv
->irq_mask
|= mask
;
114 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
120 * ilk_update_gt_irq - update GTIMR
121 * @dev_priv: driver private
122 * @interrupt_mask: mask of interrupt bits to update
123 * @enabled_irq_mask: mask of interrupt bits to enable
125 static void ilk_update_gt_irq(struct drm_i915_private
*dev_priv
,
126 uint32_t interrupt_mask
,
127 uint32_t enabled_irq_mask
)
129 assert_spin_locked(&dev_priv
->irq_lock
);
131 if (dev_priv
->pc8
.irqs_disabled
) {
132 WARN(1, "IRQs disabled\n");
133 dev_priv
->pc8
.regsave
.gtimr
&= ~interrupt_mask
;
134 dev_priv
->pc8
.regsave
.gtimr
|= (~enabled_irq_mask
&
139 dev_priv
->gt_irq_mask
&= ~interrupt_mask
;
140 dev_priv
->gt_irq_mask
|= (~enabled_irq_mask
& interrupt_mask
);
141 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
145 void ilk_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
147 ilk_update_gt_irq(dev_priv
, mask
, mask
);
150 void ilk_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
152 ilk_update_gt_irq(dev_priv
, mask
, 0);
156 * snb_update_pm_irq - update GEN6_PMIMR
157 * @dev_priv: driver private
158 * @interrupt_mask: mask of interrupt bits to update
159 * @enabled_irq_mask: mask of interrupt bits to enable
161 static void snb_update_pm_irq(struct drm_i915_private
*dev_priv
,
162 uint32_t interrupt_mask
,
163 uint32_t enabled_irq_mask
)
167 assert_spin_locked(&dev_priv
->irq_lock
);
169 if (dev_priv
->pc8
.irqs_disabled
) {
170 WARN(1, "IRQs disabled\n");
171 dev_priv
->pc8
.regsave
.gen6_pmimr
&= ~interrupt_mask
;
172 dev_priv
->pc8
.regsave
.gen6_pmimr
|= (~enabled_irq_mask
&
177 new_val
= dev_priv
->pm_irq_mask
;
178 new_val
&= ~interrupt_mask
;
179 new_val
|= (~enabled_irq_mask
& interrupt_mask
);
181 if (new_val
!= dev_priv
->pm_irq_mask
) {
182 dev_priv
->pm_irq_mask
= new_val
;
183 I915_WRITE(GEN6_PMIMR
, dev_priv
->pm_irq_mask
);
184 POSTING_READ(GEN6_PMIMR
);
188 void snb_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
190 snb_update_pm_irq(dev_priv
, mask
, mask
);
193 void snb_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
)
195 snb_update_pm_irq(dev_priv
, mask
, 0);
198 static bool ivb_can_enable_err_int(struct drm_device
*dev
)
200 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
201 struct intel_crtc
*crtc
;
204 assert_spin_locked(&dev_priv
->irq_lock
);
206 for_each_pipe(pipe
) {
207 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
209 if (crtc
->cpu_fifo_underrun_disabled
)
216 static bool cpt_can_enable_serr_int(struct drm_device
*dev
)
218 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
220 struct intel_crtc
*crtc
;
222 assert_spin_locked(&dev_priv
->irq_lock
);
224 for_each_pipe(pipe
) {
225 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
227 if (crtc
->pch_fifo_underrun_disabled
)
234 static void ironlake_set_fifo_underrun_reporting(struct drm_device
*dev
,
235 enum pipe pipe
, bool enable
)
237 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
238 uint32_t bit
= (pipe
== PIPE_A
) ? DE_PIPEA_FIFO_UNDERRUN
:
239 DE_PIPEB_FIFO_UNDERRUN
;
242 ironlake_enable_display_irq(dev_priv
, bit
);
244 ironlake_disable_display_irq(dev_priv
, bit
);
247 static void ivybridge_set_fifo_underrun_reporting(struct drm_device
*dev
,
248 enum pipe pipe
, bool enable
)
250 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
252 I915_WRITE(GEN7_ERR_INT
, ERR_INT_FIFO_UNDERRUN(pipe
));
254 if (!ivb_can_enable_err_int(dev
))
257 ironlake_enable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
259 bool was_enabled
= !(I915_READ(DEIMR
) & DE_ERR_INT_IVB
);
261 /* Change the state _after_ we've read out the current one. */
262 ironlake_disable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
265 (I915_READ(GEN7_ERR_INT
) & ERR_INT_FIFO_UNDERRUN(pipe
))) {
266 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
273 * ibx_display_interrupt_update - update SDEIMR
274 * @dev_priv: driver private
275 * @interrupt_mask: mask of interrupt bits to update
276 * @enabled_irq_mask: mask of interrupt bits to enable
278 static void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
279 uint32_t interrupt_mask
,
280 uint32_t enabled_irq_mask
)
282 uint32_t sdeimr
= I915_READ(SDEIMR
);
283 sdeimr
&= ~interrupt_mask
;
284 sdeimr
|= (~enabled_irq_mask
& interrupt_mask
);
286 assert_spin_locked(&dev_priv
->irq_lock
);
288 if (dev_priv
->pc8
.irqs_disabled
&&
289 (interrupt_mask
& SDE_HOTPLUG_MASK_CPT
)) {
290 WARN(1, "IRQs disabled\n");
291 dev_priv
->pc8
.regsave
.sdeimr
&= ~interrupt_mask
;
292 dev_priv
->pc8
.regsave
.sdeimr
|= (~enabled_irq_mask
&
297 I915_WRITE(SDEIMR
, sdeimr
);
298 POSTING_READ(SDEIMR
);
300 #define ibx_enable_display_interrupt(dev_priv, bits) \
301 ibx_display_interrupt_update((dev_priv), (bits), (bits))
302 #define ibx_disable_display_interrupt(dev_priv, bits) \
303 ibx_display_interrupt_update((dev_priv), (bits), 0)
305 static void ibx_set_fifo_underrun_reporting(struct drm_device
*dev
,
306 enum transcoder pch_transcoder
,
309 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
310 uint32_t bit
= (pch_transcoder
== TRANSCODER_A
) ?
311 SDE_TRANSA_FIFO_UNDER
: SDE_TRANSB_FIFO_UNDER
;
314 ibx_enable_display_interrupt(dev_priv
, bit
);
316 ibx_disable_display_interrupt(dev_priv
, bit
);
319 static void cpt_set_fifo_underrun_reporting(struct drm_device
*dev
,
320 enum transcoder pch_transcoder
,
323 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
327 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
));
329 if (!cpt_can_enable_serr_int(dev
))
332 ibx_enable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
334 uint32_t tmp
= I915_READ(SERR_INT
);
335 bool was_enabled
= !(I915_READ(SDEIMR
) & SDE_ERROR_CPT
);
337 /* Change the state _after_ we've read out the current one. */
338 ibx_disable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
341 (tmp
& SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
))) {
342 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
343 transcoder_name(pch_transcoder
));
349 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
352 * @enable: true if we want to report FIFO underrun errors, false otherwise
354 * This function makes us disable or enable CPU fifo underruns for a specific
355 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
356 * reporting for one pipe may also disable all the other CPU error interruts for
357 * the other pipes, due to the fact that there's just one interrupt mask/enable
358 * bit for all the pipes.
360 * Returns the previous state of underrun reporting.
362 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device
*dev
,
363 enum pipe pipe
, bool enable
)
365 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
366 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
367 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
371 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
373 ret
= !intel_crtc
->cpu_fifo_underrun_disabled
;
378 intel_crtc
->cpu_fifo_underrun_disabled
= !enable
;
380 if (IS_GEN5(dev
) || IS_GEN6(dev
))
381 ironlake_set_fifo_underrun_reporting(dev
, pipe
, enable
);
382 else if (IS_GEN7(dev
))
383 ivybridge_set_fifo_underrun_reporting(dev
, pipe
, enable
);
386 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
391 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
393 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
394 * @enable: true if we want to report FIFO underrun errors, false otherwise
396 * This function makes us disable or enable PCH fifo underruns for a specific
397 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
398 * underrun reporting for one transcoder may also disable all the other PCH
399 * error interruts for the other transcoders, due to the fact that there's just
400 * one interrupt mask/enable bit for all the transcoders.
402 * Returns the previous state of underrun reporting.
404 bool intel_set_pch_fifo_underrun_reporting(struct drm_device
*dev
,
405 enum transcoder pch_transcoder
,
408 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
409 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pch_transcoder
];
410 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
415 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
416 * has only one pch transcoder A that all pipes can use. To avoid racy
417 * pch transcoder -> pipe lookups from interrupt code simply store the
418 * underrun statistics in crtc A. Since we never expose this anywhere
419 * nor use it outside of the fifo underrun code here using the "wrong"
420 * crtc on LPT won't cause issues.
423 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
425 ret
= !intel_crtc
->pch_fifo_underrun_disabled
;
430 intel_crtc
->pch_fifo_underrun_disabled
= !enable
;
432 if (HAS_PCH_IBX(dev
))
433 ibx_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
435 cpt_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
438 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
444 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
446 u32 reg
= PIPESTAT(pipe
);
447 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
449 assert_spin_locked(&dev_priv
->irq_lock
);
451 if ((pipestat
& mask
) == mask
)
454 /* Enable the interrupt, clear any pending status */
455 pipestat
|= mask
| (mask
>> 16);
456 I915_WRITE(reg
, pipestat
);
461 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
463 u32 reg
= PIPESTAT(pipe
);
464 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
466 assert_spin_locked(&dev_priv
->irq_lock
);
468 if ((pipestat
& mask
) == 0)
472 I915_WRITE(reg
, pipestat
);
477 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
479 static void i915_enable_asle_pipestat(struct drm_device
*dev
)
481 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
482 unsigned long irqflags
;
484 if (!dev_priv
->opregion
.asle
|| !IS_MOBILE(dev
))
487 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
489 i915_enable_pipestat(dev_priv
, 1, PIPE_LEGACY_BLC_EVENT_ENABLE
);
490 if (INTEL_INFO(dev
)->gen
>= 4)
491 i915_enable_pipestat(dev_priv
, 0, PIPE_LEGACY_BLC_EVENT_ENABLE
);
493 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
497 * i915_pipe_enabled - check if a pipe is enabled
499 * @pipe: pipe to check
501 * Reading certain registers when the pipe is disabled can hang the chip.
502 * Use this routine to make sure the PLL is running and the pipe is active
503 * before reading such registers if unsure.
506 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
508 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
510 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
511 /* Locking is horribly broken here, but whatever. */
512 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
513 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
515 return intel_crtc
->active
;
517 return I915_READ(PIPECONF(pipe
)) & PIPECONF_ENABLE
;
521 /* Called from drm generic code, passed a 'crtc', which
522 * we use as a pipe index
524 static u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
526 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
527 unsigned long high_frame
;
528 unsigned long low_frame
;
529 u32 high1
, high2
, low
;
531 if (!i915_pipe_enabled(dev
, pipe
)) {
532 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
533 "pipe %c\n", pipe_name(pipe
));
537 high_frame
= PIPEFRAME(pipe
);
538 low_frame
= PIPEFRAMEPIXEL(pipe
);
541 * High & low register fields aren't synchronized, so make sure
542 * we get a low value that's stable across two reads of the high
546 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
547 low
= I915_READ(low_frame
) & PIPE_FRAME_LOW_MASK
;
548 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
549 } while (high1
!= high2
);
551 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
552 low
>>= PIPE_FRAME_LOW_SHIFT
;
553 return (high1
<< 8) | low
;
556 static u32
gm45_get_vblank_counter(struct drm_device
*dev
, int pipe
)
558 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
559 int reg
= PIPE_FRMCOUNT_GM45(pipe
);
561 if (!i915_pipe_enabled(dev
, pipe
)) {
562 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
563 "pipe %c\n", pipe_name(pipe
));
567 return I915_READ(reg
);
570 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, int pipe
,
571 int *vpos
, int *hpos
)
573 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
574 u32 vbl
= 0, position
= 0;
575 int vbl_start
, vbl_end
, htotal
, vtotal
;
578 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
581 if (!i915_pipe_enabled(dev
, pipe
)) {
582 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
583 "pipe %c\n", pipe_name(pipe
));
588 vtotal
= 1 + ((I915_READ(VTOTAL(cpu_transcoder
)) >> 16) & 0x1fff);
590 if (INTEL_INFO(dev
)->gen
>= 4) {
591 /* No obvious pixelcount register. Only query vertical
592 * scanout position from Display scan line register.
594 position
= I915_READ(PIPEDSL(pipe
));
596 /* Decode into vertical scanout position. Don't have
597 * horizontal scanout position.
599 *vpos
= position
& 0x1fff;
602 /* Have access to pixelcount since start of frame.
603 * We can split this into vertical and horizontal
606 position
= (I915_READ(PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
608 htotal
= 1 + ((I915_READ(HTOTAL(cpu_transcoder
)) >> 16) & 0x1fff);
609 *vpos
= position
/ htotal
;
610 *hpos
= position
- (*vpos
* htotal
);
613 /* Query vblank area. */
614 vbl
= I915_READ(VBLANK(cpu_transcoder
));
616 /* Test position against vblank region. */
617 vbl_start
= vbl
& 0x1fff;
618 vbl_end
= (vbl
>> 16) & 0x1fff;
620 if ((*vpos
< vbl_start
) || (*vpos
> vbl_end
))
623 /* Inside "upper part" of vblank area? Apply corrective offset: */
624 if (in_vbl
&& (*vpos
>= vbl_start
))
625 *vpos
= *vpos
- vtotal
;
627 /* Readouts valid? */
629 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
633 ret
|= DRM_SCANOUTPOS_INVBL
;
638 static int i915_get_vblank_timestamp(struct drm_device
*dev
, int pipe
,
640 struct timeval
*vblank_time
,
643 struct drm_crtc
*crtc
;
645 if (pipe
< 0 || pipe
>= INTEL_INFO(dev
)->num_pipes
) {
646 DRM_ERROR("Invalid crtc %d\n", pipe
);
650 /* Get drm_crtc to timestamp: */
651 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
653 DRM_ERROR("Invalid crtc %d\n", pipe
);
657 if (!crtc
->enabled
) {
658 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
662 /* Helper routine in DRM core does all the work: */
663 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
668 static bool intel_hpd_irq_event(struct drm_device
*dev
,
669 struct drm_connector
*connector
)
671 enum drm_connector_status old_status
;
673 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
674 old_status
= connector
->status
;
676 connector
->status
= connector
->funcs
->detect(connector
, false);
677 if (old_status
== connector
->status
)
680 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
682 drm_get_connector_name(connector
),
683 drm_get_connector_status_name(old_status
),
684 drm_get_connector_status_name(connector
->status
));
690 * Handle hotplug events outside the interrupt handler proper.
692 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
694 static void i915_hotplug_work_func(struct work_struct
*work
)
696 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
698 struct drm_device
*dev
= dev_priv
->dev
;
699 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
700 struct intel_connector
*intel_connector
;
701 struct intel_encoder
*intel_encoder
;
702 struct drm_connector
*connector
;
703 unsigned long irqflags
;
704 bool hpd_disabled
= false;
705 bool changed
= false;
708 /* HPD irq before everything is fully set up. */
709 if (!dev_priv
->enable_hotplug_processing
)
712 mutex_lock(&mode_config
->mutex
);
713 DRM_DEBUG_KMS("running encoder hotplug functions\n");
715 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
717 hpd_event_bits
= dev_priv
->hpd_event_bits
;
718 dev_priv
->hpd_event_bits
= 0;
719 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
720 intel_connector
= to_intel_connector(connector
);
721 intel_encoder
= intel_connector
->encoder
;
722 if (intel_encoder
->hpd_pin
> HPD_NONE
&&
723 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_MARK_DISABLED
&&
724 connector
->polled
== DRM_CONNECTOR_POLL_HPD
) {
725 DRM_INFO("HPD interrupt storm detected on connector %s: "
726 "switching from hotplug detection to polling\n",
727 drm_get_connector_name(connector
));
728 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
= HPD_DISABLED
;
729 connector
->polled
= DRM_CONNECTOR_POLL_CONNECT
730 | DRM_CONNECTOR_POLL_DISCONNECT
;
733 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
734 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
735 drm_get_connector_name(connector
), intel_encoder
->hpd_pin
);
738 /* if there were no outputs to poll, poll was disabled,
739 * therefore make sure it's enabled when disabling HPD on
742 drm_kms_helper_poll_enable(dev
);
743 mod_timer(&dev_priv
->hotplug_reenable_timer
,
744 jiffies
+ msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY
));
747 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
749 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
750 intel_connector
= to_intel_connector(connector
);
751 intel_encoder
= intel_connector
->encoder
;
752 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
753 if (intel_encoder
->hot_plug
)
754 intel_encoder
->hot_plug(intel_encoder
);
755 if (intel_hpd_irq_event(dev
, connector
))
759 mutex_unlock(&mode_config
->mutex
);
762 drm_kms_helper_hotplug_event(dev
);
765 static void ironlake_rps_change_irq_handler(struct drm_device
*dev
)
767 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
768 u32 busy_up
, busy_down
, max_avg
, min_avg
;
771 spin_lock(&mchdev_lock
);
773 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
775 new_delay
= dev_priv
->ips
.cur_delay
;
777 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
778 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
779 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
780 max_avg
= I915_READ(RCBMAXAVG
);
781 min_avg
= I915_READ(RCBMINAVG
);
783 /* Handle RCS change request from hw */
784 if (busy_up
> max_avg
) {
785 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
786 new_delay
= dev_priv
->ips
.cur_delay
- 1;
787 if (new_delay
< dev_priv
->ips
.max_delay
)
788 new_delay
= dev_priv
->ips
.max_delay
;
789 } else if (busy_down
< min_avg
) {
790 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
791 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
792 if (new_delay
> dev_priv
->ips
.min_delay
)
793 new_delay
= dev_priv
->ips
.min_delay
;
796 if (ironlake_set_drps(dev
, new_delay
))
797 dev_priv
->ips
.cur_delay
= new_delay
;
799 spin_unlock(&mchdev_lock
);
804 static void notify_ring(struct drm_device
*dev
,
805 struct intel_ring_buffer
*ring
)
807 if (ring
->obj
== NULL
)
810 trace_i915_gem_request_complete(ring
, ring
->get_seqno(ring
, false));
812 wake_up_all(&ring
->irq_queue
);
813 i915_queue_hangcheck(dev
);
816 static void gen6_pm_rps_work(struct work_struct
*work
)
818 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
823 spin_lock_irq(&dev_priv
->irq_lock
);
824 pm_iir
= dev_priv
->rps
.pm_iir
;
825 dev_priv
->rps
.pm_iir
= 0;
826 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
827 snb_enable_pm_irq(dev_priv
, GEN6_PM_RPS_EVENTS
);
828 spin_unlock_irq(&dev_priv
->irq_lock
);
830 /* Make sure we didn't queue anything we're not going to process. */
831 WARN_ON(pm_iir
& ~GEN6_PM_RPS_EVENTS
);
833 if ((pm_iir
& GEN6_PM_RPS_EVENTS
) == 0)
836 mutex_lock(&dev_priv
->rps
.hw_lock
);
838 if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
) {
839 new_delay
= dev_priv
->rps
.cur_delay
+ 1;
842 * For better performance, jump directly
843 * to RPe if we're below it.
845 if (IS_VALLEYVIEW(dev_priv
->dev
) &&
846 dev_priv
->rps
.cur_delay
< dev_priv
->rps
.rpe_delay
)
847 new_delay
= dev_priv
->rps
.rpe_delay
;
849 new_delay
= dev_priv
->rps
.cur_delay
- 1;
851 /* sysfs frequency interfaces may have snuck in while servicing the
854 if (new_delay
>= dev_priv
->rps
.min_delay
&&
855 new_delay
<= dev_priv
->rps
.max_delay
) {
856 if (IS_VALLEYVIEW(dev_priv
->dev
))
857 valleyview_set_rps(dev_priv
->dev
, new_delay
);
859 gen6_set_rps(dev_priv
->dev
, new_delay
);
862 if (IS_VALLEYVIEW(dev_priv
->dev
)) {
864 * On VLV, when we enter RC6 we may not be at the minimum
865 * voltage level, so arm a timer to check. It should only
866 * fire when there's activity or once after we've entered
867 * RC6, and then won't be re-armed until the next RPS interrupt.
869 mod_delayed_work(dev_priv
->wq
, &dev_priv
->rps
.vlv_work
,
870 msecs_to_jiffies(100));
873 mutex_unlock(&dev_priv
->rps
.hw_lock
);
878 * ivybridge_parity_work - Workqueue called when a parity error interrupt
880 * @work: workqueue struct
882 * Doesn't actually do anything except notify userspace. As a consequence of
883 * this event, userspace should try to remap the bad rows since statistically
884 * it is likely the same row is more likely to go bad again.
886 static void ivybridge_parity_work(struct work_struct
*work
)
888 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
889 l3_parity
.error_work
);
890 u32 error_status
, row
, bank
, subbank
;
891 char *parity_event
[5];
895 /* We must turn off DOP level clock gating to access the L3 registers.
896 * In order to prevent a get/put style interface, acquire struct mutex
897 * any time we access those registers.
899 mutex_lock(&dev_priv
->dev
->struct_mutex
);
901 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
902 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
903 POSTING_READ(GEN7_MISCCPCTL
);
905 error_status
= I915_READ(GEN7_L3CDERRST1
);
906 row
= GEN7_PARITY_ERROR_ROW(error_status
);
907 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
908 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
910 I915_WRITE(GEN7_L3CDERRST1
, GEN7_PARITY_ERROR_VALID
|
911 GEN7_L3CDERRST1_ENABLE
);
912 POSTING_READ(GEN7_L3CDERRST1
);
914 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
916 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
917 ilk_enable_gt_irq(dev_priv
, GT_RENDER_L3_PARITY_ERROR_INTERRUPT
);
918 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
920 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
922 parity_event
[0] = I915_L3_PARITY_UEVENT
"=1";
923 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
924 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
925 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
926 parity_event
[4] = NULL
;
928 kobject_uevent_env(&dev_priv
->dev
->primary
->kdev
.kobj
,
929 KOBJ_CHANGE
, parity_event
);
931 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
934 kfree(parity_event
[3]);
935 kfree(parity_event
[2]);
936 kfree(parity_event
[1]);
939 static void ivybridge_parity_error_irq_handler(struct drm_device
*dev
)
941 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
943 if (!HAS_L3_GPU_CACHE(dev
))
946 spin_lock(&dev_priv
->irq_lock
);
947 ilk_disable_gt_irq(dev_priv
, GT_RENDER_L3_PARITY_ERROR_INTERRUPT
);
948 spin_unlock(&dev_priv
->irq_lock
);
950 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
953 static void ilk_gt_irq_handler(struct drm_device
*dev
,
954 struct drm_i915_private
*dev_priv
,
958 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
959 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
960 if (gt_iir
& ILK_BSD_USER_INTERRUPT
)
961 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
964 static void snb_gt_irq_handler(struct drm_device
*dev
,
965 struct drm_i915_private
*dev_priv
,
970 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
971 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
972 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
973 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
974 if (gt_iir
& GT_BLT_USER_INTERRUPT
)
975 notify_ring(dev
, &dev_priv
->ring
[BCS
]);
977 if (gt_iir
& (GT_BLT_CS_ERROR_INTERRUPT
|
978 GT_BSD_CS_ERROR_INTERRUPT
|
979 GT_RENDER_CS_MASTER_ERROR_INTERRUPT
)) {
980 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir
);
981 i915_handle_error(dev
, false);
984 if (gt_iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT
)
985 ivybridge_parity_error_irq_handler(dev
);
988 #define HPD_STORM_DETECT_PERIOD 1000
989 #define HPD_STORM_THRESHOLD 5
991 static inline void intel_hpd_irq_handler(struct drm_device
*dev
,
995 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
997 bool storm_detected
= false;
999 if (!hotplug_trigger
)
1002 spin_lock(&dev_priv
->irq_lock
);
1003 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
1005 WARN(((hpd
[i
] & hotplug_trigger
) &&
1006 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
),
1007 "Received HPD interrupt although disabled\n");
1009 if (!(hpd
[i
] & hotplug_trigger
) ||
1010 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
)
1013 dev_priv
->hpd_event_bits
|= (1 << i
);
1014 if (!time_in_range(jiffies
, dev_priv
->hpd_stats
[i
].hpd_last_jiffies
,
1015 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
1016 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD
))) {
1017 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
= jiffies
;
1018 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
1019 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i
);
1020 } else if (dev_priv
->hpd_stats
[i
].hpd_cnt
> HPD_STORM_THRESHOLD
) {
1021 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_MARK_DISABLED
;
1022 dev_priv
->hpd_event_bits
&= ~(1 << i
);
1023 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i
);
1024 storm_detected
= true;
1026 dev_priv
->hpd_stats
[i
].hpd_cnt
++;
1027 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i
,
1028 dev_priv
->hpd_stats
[i
].hpd_cnt
);
1033 dev_priv
->display
.hpd_irq_setup(dev
);
1034 spin_unlock(&dev_priv
->irq_lock
);
1037 * Our hotplug handler can grab modeset locks (by calling down into the
1038 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1039 * queue for otherwise the flush_work in the pageflip code will
1042 schedule_work(&dev_priv
->hotplug_work
);
1045 static void gmbus_irq_handler(struct drm_device
*dev
)
1047 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1049 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1052 static void dp_aux_irq_handler(struct drm_device
*dev
)
1054 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1056 wake_up_all(&dev_priv
->gmbus_wait_queue
);
1059 /* The RPS events need forcewake, so we add them to a work queue and mask their
1060 * IMR bits until the work is done. Other interrupts can be processed without
1061 * the work queue. */
1062 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
, u32 pm_iir
)
1064 if (pm_iir
& GEN6_PM_RPS_EVENTS
) {
1065 spin_lock(&dev_priv
->irq_lock
);
1066 dev_priv
->rps
.pm_iir
|= pm_iir
& GEN6_PM_RPS_EVENTS
;
1067 snb_disable_pm_irq(dev_priv
, pm_iir
& GEN6_PM_RPS_EVENTS
);
1068 spin_unlock(&dev_priv
->irq_lock
);
1070 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
1073 if (HAS_VEBOX(dev_priv
->dev
)) {
1074 if (pm_iir
& PM_VEBOX_USER_INTERRUPT
)
1075 notify_ring(dev_priv
->dev
, &dev_priv
->ring
[VECS
]);
1077 if (pm_iir
& PM_VEBOX_CS_ERROR_INTERRUPT
) {
1078 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir
);
1079 i915_handle_error(dev_priv
->dev
, false);
1084 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
1086 struct drm_device
*dev
= (struct drm_device
*) arg
;
1087 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1088 u32 iir
, gt_iir
, pm_iir
;
1089 irqreturn_t ret
= IRQ_NONE
;
1090 unsigned long irqflags
;
1092 u32 pipe_stats
[I915_MAX_PIPES
];
1094 atomic_inc(&dev_priv
->irq_received
);
1097 iir
= I915_READ(VLV_IIR
);
1098 gt_iir
= I915_READ(GTIIR
);
1099 pm_iir
= I915_READ(GEN6_PMIIR
);
1101 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
1106 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1108 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1109 for_each_pipe(pipe
) {
1110 int reg
= PIPESTAT(pipe
);
1111 pipe_stats
[pipe
] = I915_READ(reg
);
1114 * Clear the PIPE*STAT regs before the IIR
1116 if (pipe_stats
[pipe
] & 0x8000ffff) {
1117 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
1118 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1120 I915_WRITE(reg
, pipe_stats
[pipe
]);
1123 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1125 for_each_pipe(pipe
) {
1126 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
)
1127 drm_handle_vblank(dev
, pipe
);
1129 if (pipe_stats
[pipe
] & PLANE_FLIPDONE_INT_STATUS_VLV
) {
1130 intel_prepare_page_flip(dev
, pipe
);
1131 intel_finish_page_flip(dev
, pipe
);
1135 /* Consume port. Then clear IIR or we'll miss events */
1136 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
1137 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1138 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
1140 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1143 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
1145 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1146 I915_READ(PORT_HOTPLUG_STAT
);
1149 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1150 gmbus_irq_handler(dev
);
1153 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1155 I915_WRITE(GTIIR
, gt_iir
);
1156 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1157 I915_WRITE(VLV_IIR
, iir
);
1164 static void ibx_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1166 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1168 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK
;
1170 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_ibx
);
1172 if (pch_iir
& SDE_AUDIO_POWER_MASK
) {
1173 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK
) >>
1174 SDE_AUDIO_POWER_SHIFT
);
1175 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1179 if (pch_iir
& SDE_AUX_MASK
)
1180 dp_aux_irq_handler(dev
);
1182 if (pch_iir
& SDE_GMBUS
)
1183 gmbus_irq_handler(dev
);
1185 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
1186 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1188 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
1189 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1191 if (pch_iir
& SDE_POISON
)
1192 DRM_ERROR("PCH poison interrupt\n");
1194 if (pch_iir
& SDE_FDI_MASK
)
1196 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1198 I915_READ(FDI_RX_IIR(pipe
)));
1200 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
1201 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1203 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
1204 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1206 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
1207 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1209 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1211 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
1212 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1214 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1217 static void ivb_err_int_handler(struct drm_device
*dev
)
1219 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1220 u32 err_int
= I915_READ(GEN7_ERR_INT
);
1222 if (err_int
& ERR_INT_POISON
)
1223 DRM_ERROR("Poison interrupt\n");
1225 if (err_int
& ERR_INT_FIFO_UNDERRUN_A
)
1226 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_A
, false))
1227 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1229 if (err_int
& ERR_INT_FIFO_UNDERRUN_B
)
1230 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_B
, false))
1231 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1233 if (err_int
& ERR_INT_FIFO_UNDERRUN_C
)
1234 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_C
, false))
1235 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1237 I915_WRITE(GEN7_ERR_INT
, err_int
);
1240 static void cpt_serr_int_handler(struct drm_device
*dev
)
1242 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1243 u32 serr_int
= I915_READ(SERR_INT
);
1245 if (serr_int
& SERR_INT_POISON
)
1246 DRM_ERROR("PCH poison interrupt\n");
1248 if (serr_int
& SERR_INT_TRANS_A_FIFO_UNDERRUN
)
1249 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1251 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1253 if (serr_int
& SERR_INT_TRANS_B_FIFO_UNDERRUN
)
1254 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1256 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1258 if (serr_int
& SERR_INT_TRANS_C_FIFO_UNDERRUN
)
1259 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_C
,
1261 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1263 I915_WRITE(SERR_INT
, serr_int
);
1266 static void cpt_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1268 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1270 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_CPT
;
1272 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_cpt
);
1274 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) {
1275 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
1276 SDE_AUDIO_POWER_SHIFT_CPT
);
1277 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1281 if (pch_iir
& SDE_AUX_MASK_CPT
)
1282 dp_aux_irq_handler(dev
);
1284 if (pch_iir
& SDE_GMBUS_CPT
)
1285 gmbus_irq_handler(dev
);
1287 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
1288 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1290 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
1291 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1293 if (pch_iir
& SDE_FDI_MASK_CPT
)
1295 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1297 I915_READ(FDI_RX_IIR(pipe
)));
1299 if (pch_iir
& SDE_ERROR_CPT
)
1300 cpt_serr_int_handler(dev
);
1303 static void ilk_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
1305 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1307 if (de_iir
& DE_AUX_CHANNEL_A
)
1308 dp_aux_irq_handler(dev
);
1310 if (de_iir
& DE_GSE
)
1311 intel_opregion_asle_intr(dev
);
1313 if (de_iir
& DE_PIPEA_VBLANK
)
1314 drm_handle_vblank(dev
, 0);
1316 if (de_iir
& DE_PIPEB_VBLANK
)
1317 drm_handle_vblank(dev
, 1);
1319 if (de_iir
& DE_POISON
)
1320 DRM_ERROR("Poison interrupt\n");
1322 if (de_iir
& DE_PIPEA_FIFO_UNDERRUN
)
1323 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_A
, false))
1324 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1326 if (de_iir
& DE_PIPEB_FIFO_UNDERRUN
)
1327 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_B
, false))
1328 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1330 if (de_iir
& DE_PLANEA_FLIP_DONE
) {
1331 intel_prepare_page_flip(dev
, 0);
1332 intel_finish_page_flip_plane(dev
, 0);
1335 if (de_iir
& DE_PLANEB_FLIP_DONE
) {
1336 intel_prepare_page_flip(dev
, 1);
1337 intel_finish_page_flip_plane(dev
, 1);
1340 /* check event from PCH */
1341 if (de_iir
& DE_PCH_EVENT
) {
1342 u32 pch_iir
= I915_READ(SDEIIR
);
1344 if (HAS_PCH_CPT(dev
))
1345 cpt_irq_handler(dev
, pch_iir
);
1347 ibx_irq_handler(dev
, pch_iir
);
1349 /* should clear PCH hotplug event before clear CPU irq */
1350 I915_WRITE(SDEIIR
, pch_iir
);
1353 if (IS_GEN5(dev
) && de_iir
& DE_PCU_EVENT
)
1354 ironlake_rps_change_irq_handler(dev
);
1357 static void ivb_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
1359 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1362 if (de_iir
& DE_ERR_INT_IVB
)
1363 ivb_err_int_handler(dev
);
1365 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
1366 dp_aux_irq_handler(dev
);
1368 if (de_iir
& DE_GSE_IVB
)
1369 intel_opregion_asle_intr(dev
);
1371 for (i
= 0; i
< 3; i
++) {
1372 if (de_iir
& (DE_PIPEA_VBLANK_IVB
<< (5 * i
)))
1373 drm_handle_vblank(dev
, i
);
1374 if (de_iir
& (DE_PLANEA_FLIP_DONE_IVB
<< (5 * i
))) {
1375 intel_prepare_page_flip(dev
, i
);
1376 intel_finish_page_flip_plane(dev
, i
);
1380 /* check event from PCH */
1381 if (!HAS_PCH_NOP(dev
) && (de_iir
& DE_PCH_EVENT_IVB
)) {
1382 u32 pch_iir
= I915_READ(SDEIIR
);
1384 cpt_irq_handler(dev
, pch_iir
);
1386 /* clear PCH hotplug event before clear CPU irq */
1387 I915_WRITE(SDEIIR
, pch_iir
);
1391 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
1393 struct drm_device
*dev
= (struct drm_device
*) arg
;
1394 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1395 u32 de_iir
, gt_iir
, de_ier
, sde_ier
= 0;
1396 irqreturn_t ret
= IRQ_NONE
;
1397 bool err_int_reenable
= false;
1399 atomic_inc(&dev_priv
->irq_received
);
1401 /* We get interrupts on unclaimed registers, so check for this before we
1402 * do any I915_{READ,WRITE}. */
1403 intel_uncore_check_errors(dev
);
1405 /* disable master interrupt before clearing iir */
1406 de_ier
= I915_READ(DEIER
);
1407 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
1408 POSTING_READ(DEIER
);
1410 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1411 * interrupts will will be stored on its back queue, and then we'll be
1412 * able to process them after we restore SDEIER (as soon as we restore
1413 * it, we'll get an interrupt if SDEIIR still has something to process
1414 * due to its back queue). */
1415 if (!HAS_PCH_NOP(dev
)) {
1416 sde_ier
= I915_READ(SDEIER
);
1417 I915_WRITE(SDEIER
, 0);
1418 POSTING_READ(SDEIER
);
1421 /* On Haswell, also mask ERR_INT because we don't want to risk
1422 * generating "unclaimed register" interrupts from inside the interrupt
1424 if (IS_HASWELL(dev
)) {
1425 spin_lock(&dev_priv
->irq_lock
);
1426 err_int_reenable
= ~dev_priv
->irq_mask
& DE_ERR_INT_IVB
;
1427 if (err_int_reenable
)
1428 ironlake_disable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
1429 spin_unlock(&dev_priv
->irq_lock
);
1432 gt_iir
= I915_READ(GTIIR
);
1434 if (INTEL_INFO(dev
)->gen
>= 6)
1435 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1437 ilk_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1438 I915_WRITE(GTIIR
, gt_iir
);
1442 de_iir
= I915_READ(DEIIR
);
1444 if (INTEL_INFO(dev
)->gen
>= 7)
1445 ivb_display_irq_handler(dev
, de_iir
);
1447 ilk_display_irq_handler(dev
, de_iir
);
1448 I915_WRITE(DEIIR
, de_iir
);
1452 if (INTEL_INFO(dev
)->gen
>= 6) {
1453 u32 pm_iir
= I915_READ(GEN6_PMIIR
);
1455 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1456 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1461 if (err_int_reenable
) {
1462 spin_lock(&dev_priv
->irq_lock
);
1463 if (ivb_can_enable_err_int(dev
))
1464 ironlake_enable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
1465 spin_unlock(&dev_priv
->irq_lock
);
1468 I915_WRITE(DEIER
, de_ier
);
1469 POSTING_READ(DEIER
);
1470 if (!HAS_PCH_NOP(dev
)) {
1471 I915_WRITE(SDEIER
, sde_ier
);
1472 POSTING_READ(SDEIER
);
1479 * i915_error_work_func - do process context error handling work
1480 * @work: work struct
1482 * Fire an error uevent so userspace can see that a hang or error
1485 static void i915_error_work_func(struct work_struct
*work
)
1487 struct i915_gpu_error
*error
= container_of(work
, struct i915_gpu_error
,
1489 drm_i915_private_t
*dev_priv
= container_of(error
, drm_i915_private_t
,
1491 struct drm_device
*dev
= dev_priv
->dev
;
1492 struct intel_ring_buffer
*ring
;
1493 char *error_event
[] = { I915_ERROR_UEVENT
"=1", NULL
};
1494 char *reset_event
[] = { I915_RESET_UEVENT
"=1", NULL
};
1495 char *reset_done_event
[] = { I915_ERROR_UEVENT
"=0", NULL
};
1498 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
, error_event
);
1501 * Note that there's only one work item which does gpu resets, so we
1502 * need not worry about concurrent gpu resets potentially incrementing
1503 * error->reset_counter twice. We only need to take care of another
1504 * racing irq/hangcheck declaring the gpu dead for a second time. A
1505 * quick check for that is good enough: schedule_work ensures the
1506 * correct ordering between hang detection and this work item, and since
1507 * the reset in-progress bit is only ever set by code outside of this
1508 * work we don't need to worry about any other races.
1510 if (i915_reset_in_progress(error
) && !i915_terminally_wedged(error
)) {
1511 DRM_DEBUG_DRIVER("resetting chip\n");
1512 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
,
1515 ret
= i915_reset(dev
);
1519 * After all the gem state is reset, increment the reset
1520 * counter and wake up everyone waiting for the reset to
1523 * Since unlock operations are a one-sided barrier only,
1524 * we need to insert a barrier here to order any seqno
1526 * the counter increment.
1528 smp_mb__before_atomic_inc();
1529 atomic_inc(&dev_priv
->gpu_error
.reset_counter
);
1531 kobject_uevent_env(&dev
->primary
->kdev
.kobj
,
1532 KOBJ_CHANGE
, reset_done_event
);
1534 atomic_set(&error
->reset_counter
, I915_WEDGED
);
1537 for_each_ring(ring
, dev_priv
, i
)
1538 wake_up_all(&ring
->irq_queue
);
1540 intel_display_handle_reset(dev
);
1542 wake_up_all(&dev_priv
->gpu_error
.reset_queue
);
1546 static void i915_report_and_clear_eir(struct drm_device
*dev
)
1548 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1549 uint32_t instdone
[I915_NUM_INSTDONE_REG
];
1550 u32 eir
= I915_READ(EIR
);
1556 pr_err("render error detected, EIR: 0x%08x\n", eir
);
1558 i915_get_extra_instdone(dev
, instdone
);
1561 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
1562 u32 ipeir
= I915_READ(IPEIR_I965
);
1564 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1565 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1566 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
1567 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
1568 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1569 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1570 I915_WRITE(IPEIR_I965
, ipeir
);
1571 POSTING_READ(IPEIR_I965
);
1573 if (eir
& GM45_ERROR_PAGE_TABLE
) {
1574 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1575 pr_err("page table error\n");
1576 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1577 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1578 POSTING_READ(PGTBL_ER
);
1582 if (!IS_GEN2(dev
)) {
1583 if (eir
& I915_ERROR_PAGE_TABLE
) {
1584 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1585 pr_err("page table error\n");
1586 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1587 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1588 POSTING_READ(PGTBL_ER
);
1592 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
1593 pr_err("memory refresh error:\n");
1595 pr_err("pipe %c stat: 0x%08x\n",
1596 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
1597 /* pipestat has already been acked */
1599 if (eir
& I915_ERROR_INSTRUCTION
) {
1600 pr_err("instruction error\n");
1601 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
1602 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
1603 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
1604 if (INTEL_INFO(dev
)->gen
< 4) {
1605 u32 ipeir
= I915_READ(IPEIR
);
1607 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
1608 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
1609 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
1610 I915_WRITE(IPEIR
, ipeir
);
1611 POSTING_READ(IPEIR
);
1613 u32 ipeir
= I915_READ(IPEIR_I965
);
1615 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1616 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1617 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1618 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1619 I915_WRITE(IPEIR_I965
, ipeir
);
1620 POSTING_READ(IPEIR_I965
);
1624 I915_WRITE(EIR
, eir
);
1626 eir
= I915_READ(EIR
);
1629 * some errors might have become stuck,
1632 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
1633 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
1634 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
1639 * i915_handle_error - handle an error interrupt
1642 * Do some basic checking of regsiter state at error interrupt time and
1643 * dump it to the syslog. Also call i915_capture_error_state() to make
1644 * sure we get a record and make it available in debugfs. Fire a uevent
1645 * so userspace knows something bad happened (should trigger collection
1646 * of a ring dump etc.).
1648 void i915_handle_error(struct drm_device
*dev
, bool wedged
)
1650 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1651 struct intel_ring_buffer
*ring
;
1654 i915_capture_error_state(dev
);
1655 i915_report_and_clear_eir(dev
);
1658 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG
,
1659 &dev_priv
->gpu_error
.reset_counter
);
1662 * Wakeup waiting processes so that the reset work item
1663 * doesn't deadlock trying to grab various locks.
1665 for_each_ring(ring
, dev_priv
, i
)
1666 wake_up_all(&ring
->irq_queue
);
1669 queue_work(dev_priv
->wq
, &dev_priv
->gpu_error
.work
);
1672 static void __always_unused
i915_pageflip_stall_check(struct drm_device
*dev
, int pipe
)
1674 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1675 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1676 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1677 struct drm_i915_gem_object
*obj
;
1678 struct intel_unpin_work
*work
;
1679 unsigned long flags
;
1680 bool stall_detected
;
1682 /* Ignore early vblank irqs */
1683 if (intel_crtc
== NULL
)
1686 spin_lock_irqsave(&dev
->event_lock
, flags
);
1687 work
= intel_crtc
->unpin_work
;
1690 atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
||
1691 !work
->enable_stall_check
) {
1692 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1693 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1697 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1698 obj
= work
->pending_flip_obj
;
1699 if (INTEL_INFO(dev
)->gen
>= 4) {
1700 int dspsurf
= DSPSURF(intel_crtc
->plane
);
1701 stall_detected
= I915_HI_DISPBASE(I915_READ(dspsurf
)) ==
1702 i915_gem_obj_ggtt_offset(obj
);
1704 int dspaddr
= DSPADDR(intel_crtc
->plane
);
1705 stall_detected
= I915_READ(dspaddr
) == (i915_gem_obj_ggtt_offset(obj
) +
1706 crtc
->y
* crtc
->fb
->pitches
[0] +
1707 crtc
->x
* crtc
->fb
->bits_per_pixel
/8);
1710 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1712 if (stall_detected
) {
1713 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1714 intel_prepare_page_flip(dev
, intel_crtc
->plane
);
1718 /* Called from drm generic code, passed 'crtc' which
1719 * we use as a pipe index
1721 static int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
1723 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1724 unsigned long irqflags
;
1726 if (!i915_pipe_enabled(dev
, pipe
))
1729 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1730 if (INTEL_INFO(dev
)->gen
>= 4)
1731 i915_enable_pipestat(dev_priv
, pipe
,
1732 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1734 i915_enable_pipestat(dev_priv
, pipe
,
1735 PIPE_VBLANK_INTERRUPT_ENABLE
);
1737 /* maintain vblank delivery even in deep C-states */
1738 if (dev_priv
->info
->gen
== 3)
1739 I915_WRITE(INSTPM
, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS
));
1740 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1745 static int ironlake_enable_vblank(struct drm_device
*dev
, int pipe
)
1747 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1748 unsigned long irqflags
;
1749 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
1750 DE_PIPE_VBLANK_ILK(pipe
);
1752 if (!i915_pipe_enabled(dev
, pipe
))
1755 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1756 ironlake_enable_display_irq(dev_priv
, bit
);
1757 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1762 static int valleyview_enable_vblank(struct drm_device
*dev
, int pipe
)
1764 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1765 unsigned long irqflags
;
1768 if (!i915_pipe_enabled(dev
, pipe
))
1771 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1772 imr
= I915_READ(VLV_IMR
);
1774 imr
&= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
1776 imr
&= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1777 I915_WRITE(VLV_IMR
, imr
);
1778 i915_enable_pipestat(dev_priv
, pipe
,
1779 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1780 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1785 /* Called from drm generic code, passed 'crtc' which
1786 * we use as a pipe index
1788 static void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
1790 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1791 unsigned long irqflags
;
1793 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1794 if (dev_priv
->info
->gen
== 3)
1795 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS
));
1797 i915_disable_pipestat(dev_priv
, pipe
,
1798 PIPE_VBLANK_INTERRUPT_ENABLE
|
1799 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1800 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1803 static void ironlake_disable_vblank(struct drm_device
*dev
, int pipe
)
1805 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1806 unsigned long irqflags
;
1807 uint32_t bit
= (INTEL_INFO(dev
)->gen
>= 7) ? DE_PIPE_VBLANK_IVB(pipe
) :
1808 DE_PIPE_VBLANK_ILK(pipe
);
1810 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1811 ironlake_disable_display_irq(dev_priv
, bit
);
1812 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1815 static void valleyview_disable_vblank(struct drm_device
*dev
, int pipe
)
1817 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1818 unsigned long irqflags
;
1821 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1822 i915_disable_pipestat(dev_priv
, pipe
,
1823 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1824 imr
= I915_READ(VLV_IMR
);
1826 imr
|= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
1828 imr
|= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1829 I915_WRITE(VLV_IMR
, imr
);
1830 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1834 ring_last_seqno(struct intel_ring_buffer
*ring
)
1836 return list_entry(ring
->request_list
.prev
,
1837 struct drm_i915_gem_request
, list
)->seqno
;
1841 ring_idle(struct intel_ring_buffer
*ring
, u32 seqno
)
1843 return (list_empty(&ring
->request_list
) ||
1844 i915_seqno_passed(seqno
, ring_last_seqno(ring
)));
1847 static struct intel_ring_buffer
*
1848 semaphore_waits_for(struct intel_ring_buffer
*ring
, u32
*seqno
)
1850 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1851 u32 cmd
, ipehr
, acthd
, acthd_min
;
1853 ipehr
= I915_READ(RING_IPEHR(ring
->mmio_base
));
1854 if ((ipehr
& ~(0x3 << 16)) !=
1855 (MI_SEMAPHORE_MBOX
| MI_SEMAPHORE_COMPARE
| MI_SEMAPHORE_REGISTER
))
1858 /* ACTHD is likely pointing to the dword after the actual command,
1859 * so scan backwards until we find the MBOX.
1861 acthd
= intel_ring_get_active_head(ring
) & HEAD_ADDR
;
1862 acthd_min
= max((int)acthd
- 3 * 4, 0);
1864 cmd
= ioread32(ring
->virtual_start
+ acthd
);
1869 if (acthd
< acthd_min
)
1873 *seqno
= ioread32(ring
->virtual_start
+acthd
+4)+1;
1874 return &dev_priv
->ring
[(ring
->id
+ (((ipehr
>> 17) & 1) + 1)) % 3];
1877 static int semaphore_passed(struct intel_ring_buffer
*ring
)
1879 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1880 struct intel_ring_buffer
*signaller
;
1883 ring
->hangcheck
.deadlock
= true;
1885 signaller
= semaphore_waits_for(ring
, &seqno
);
1886 if (signaller
== NULL
|| signaller
->hangcheck
.deadlock
)
1889 /* cursory check for an unkickable deadlock */
1890 ctl
= I915_READ_CTL(signaller
);
1891 if (ctl
& RING_WAIT_SEMAPHORE
&& semaphore_passed(signaller
) < 0)
1894 return i915_seqno_passed(signaller
->get_seqno(signaller
, false), seqno
);
1897 static void semaphore_clear_deadlocks(struct drm_i915_private
*dev_priv
)
1899 struct intel_ring_buffer
*ring
;
1902 for_each_ring(ring
, dev_priv
, i
)
1903 ring
->hangcheck
.deadlock
= false;
1906 static enum intel_ring_hangcheck_action
1907 ring_stuck(struct intel_ring_buffer
*ring
, u32 acthd
)
1909 struct drm_device
*dev
= ring
->dev
;
1910 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1913 if (ring
->hangcheck
.acthd
!= acthd
)
1914 return HANGCHECK_ACTIVE
;
1917 return HANGCHECK_HUNG
;
1919 /* Is the chip hanging on a WAIT_FOR_EVENT?
1920 * If so we can simply poke the RB_WAIT bit
1921 * and break the hang. This should work on
1922 * all but the second generation chipsets.
1924 tmp
= I915_READ_CTL(ring
);
1925 if (tmp
& RING_WAIT
) {
1926 DRM_ERROR("Kicking stuck wait on %s\n",
1928 I915_WRITE_CTL(ring
, tmp
);
1929 return HANGCHECK_KICK
;
1932 if (INTEL_INFO(dev
)->gen
>= 6 && tmp
& RING_WAIT_SEMAPHORE
) {
1933 switch (semaphore_passed(ring
)) {
1935 return HANGCHECK_HUNG
;
1937 DRM_ERROR("Kicking stuck semaphore on %s\n",
1939 I915_WRITE_CTL(ring
, tmp
);
1940 return HANGCHECK_KICK
;
1942 return HANGCHECK_WAIT
;
1946 return HANGCHECK_HUNG
;
1950 * This is called when the chip hasn't reported back with completed
1951 * batchbuffers in a long time. We keep track per ring seqno progress and
1952 * if there are no progress, hangcheck score for that ring is increased.
1953 * Further, acthd is inspected to see if the ring is stuck. On stuck case
1954 * we kick the ring. If we see no progress on three subsequent calls
1955 * we assume chip is wedged and try to fix it by resetting the chip.
1957 static void i915_hangcheck_elapsed(unsigned long data
)
1959 struct drm_device
*dev
= (struct drm_device
*)data
;
1960 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1961 struct intel_ring_buffer
*ring
;
1963 int busy_count
= 0, rings_hung
= 0;
1964 bool stuck
[I915_NUM_RINGS
] = { 0 };
1970 if (!i915_enable_hangcheck
)
1973 for_each_ring(ring
, dev_priv
, i
) {
1977 semaphore_clear_deadlocks(dev_priv
);
1979 seqno
= ring
->get_seqno(ring
, false);
1980 acthd
= intel_ring_get_active_head(ring
);
1982 if (ring
->hangcheck
.seqno
== seqno
) {
1983 if (ring_idle(ring
, seqno
)) {
1984 ring
->hangcheck
.action
= HANGCHECK_IDLE
;
1986 if (waitqueue_active(&ring
->irq_queue
)) {
1987 /* Issue a wake-up to catch stuck h/w. */
1988 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1990 wake_up_all(&ring
->irq_queue
);
1991 ring
->hangcheck
.score
+= HUNG
;
1995 /* We always increment the hangcheck score
1996 * if the ring is busy and still processing
1997 * the same request, so that no single request
1998 * can run indefinitely (such as a chain of
1999 * batches). The only time we do not increment
2000 * the hangcheck score on this ring, if this
2001 * ring is in a legitimate wait for another
2002 * ring. In that case the waiting ring is a
2003 * victim and we want to be sure we catch the
2004 * right culprit. Then every time we do kick
2005 * the ring, add a small increment to the
2006 * score so that we can catch a batch that is
2007 * being repeatedly kicked and so responsible
2008 * for stalling the machine.
2010 ring
->hangcheck
.action
= ring_stuck(ring
,
2013 switch (ring
->hangcheck
.action
) {
2014 case HANGCHECK_IDLE
:
2015 case HANGCHECK_WAIT
:
2017 case HANGCHECK_ACTIVE
:
2018 ring
->hangcheck
.score
+= BUSY
;
2020 case HANGCHECK_KICK
:
2021 ring
->hangcheck
.score
+= KICK
;
2023 case HANGCHECK_HUNG
:
2024 ring
->hangcheck
.score
+= HUNG
;
2030 ring
->hangcheck
.action
= HANGCHECK_ACTIVE
;
2032 /* Gradually reduce the count so that we catch DoS
2033 * attempts across multiple batches.
2035 if (ring
->hangcheck
.score
> 0)
2036 ring
->hangcheck
.score
--;
2039 ring
->hangcheck
.seqno
= seqno
;
2040 ring
->hangcheck
.acthd
= acthd
;
2044 for_each_ring(ring
, dev_priv
, i
) {
2045 if (ring
->hangcheck
.score
> FIRE
) {
2046 DRM_INFO("%s on %s\n",
2047 stuck
[i
] ? "stuck" : "no progress",
2054 return i915_handle_error(dev
, true);
2057 /* Reset timer case chip hangs without another request
2059 i915_queue_hangcheck(dev
);
2062 void i915_queue_hangcheck(struct drm_device
*dev
)
2064 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2065 if (!i915_enable_hangcheck
)
2068 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
2069 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
2072 static void ibx_irq_preinstall(struct drm_device
*dev
)
2074 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2076 if (HAS_PCH_NOP(dev
))
2079 /* south display irq */
2080 I915_WRITE(SDEIMR
, 0xffffffff);
2082 * SDEIER is also touched by the interrupt handler to work around missed
2083 * PCH interrupts. Hence we can't update it after the interrupt handler
2084 * is enabled - instead we unconditionally enable all PCH interrupt
2085 * sources here, but then only unmask them as needed with SDEIMR.
2087 I915_WRITE(SDEIER
, 0xffffffff);
2088 POSTING_READ(SDEIER
);
2091 static void gen5_gt_irq_preinstall(struct drm_device
*dev
)
2093 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2096 I915_WRITE(GTIMR
, 0xffffffff);
2097 I915_WRITE(GTIER
, 0x0);
2098 POSTING_READ(GTIER
);
2100 if (INTEL_INFO(dev
)->gen
>= 6) {
2102 I915_WRITE(GEN6_PMIMR
, 0xffffffff);
2103 I915_WRITE(GEN6_PMIER
, 0x0);
2104 POSTING_READ(GEN6_PMIER
);
2110 static void ironlake_irq_preinstall(struct drm_device
*dev
)
2112 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2114 atomic_set(&dev_priv
->irq_received
, 0);
2116 I915_WRITE(HWSTAM
, 0xeffe);
2118 I915_WRITE(DEIMR
, 0xffffffff);
2119 I915_WRITE(DEIER
, 0x0);
2120 POSTING_READ(DEIER
);
2122 gen5_gt_irq_preinstall(dev
);
2124 ibx_irq_preinstall(dev
);
2127 static void valleyview_irq_preinstall(struct drm_device
*dev
)
2129 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2132 atomic_set(&dev_priv
->irq_received
, 0);
2135 I915_WRITE(VLV_IMR
, 0);
2136 I915_WRITE(RING_IMR(RENDER_RING_BASE
), 0);
2137 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE
), 0);
2138 I915_WRITE(RING_IMR(BLT_RING_BASE
), 0);
2141 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2142 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2144 gen5_gt_irq_preinstall(dev
);
2146 I915_WRITE(DPINVGTT
, 0xff);
2148 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2149 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2151 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2152 I915_WRITE(VLV_IIR
, 0xffffffff);
2153 I915_WRITE(VLV_IMR
, 0xffffffff);
2154 I915_WRITE(VLV_IER
, 0x0);
2155 POSTING_READ(VLV_IER
);
2158 static void ibx_hpd_irq_setup(struct drm_device
*dev
)
2160 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2161 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2162 struct intel_encoder
*intel_encoder
;
2163 u32 hotplug_irqs
, hotplug
, enabled_irqs
= 0;
2165 if (HAS_PCH_IBX(dev
)) {
2166 hotplug_irqs
= SDE_HOTPLUG_MASK
;
2167 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2168 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2169 enabled_irqs
|= hpd_ibx
[intel_encoder
->hpd_pin
];
2171 hotplug_irqs
= SDE_HOTPLUG_MASK_CPT
;
2172 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2173 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2174 enabled_irqs
|= hpd_cpt
[intel_encoder
->hpd_pin
];
2177 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
2180 * Enable digital hotplug on the PCH, and configure the DP short pulse
2181 * duration to 2ms (which is the minimum in the Display Port spec)
2183 * This register is the same on all known PCH chips.
2185 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
2186 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
2187 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
2188 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
2189 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
2190 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
2193 static void ibx_irq_postinstall(struct drm_device
*dev
)
2195 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2198 if (HAS_PCH_NOP(dev
))
2201 if (HAS_PCH_IBX(dev
)) {
2202 mask
= SDE_GMBUS
| SDE_AUX_MASK
| SDE_TRANSB_FIFO_UNDER
|
2203 SDE_TRANSA_FIFO_UNDER
| SDE_POISON
;
2205 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
| SDE_ERROR_CPT
;
2207 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2210 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2211 I915_WRITE(SDEIMR
, ~mask
);
2214 static void gen5_gt_irq_postinstall(struct drm_device
*dev
)
2216 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2217 u32 pm_irqs
, gt_irqs
;
2219 pm_irqs
= gt_irqs
= 0;
2221 dev_priv
->gt_irq_mask
= ~0;
2222 if (HAS_L3_GPU_CACHE(dev
)) {
2223 /* L3 parity interrupt is always unmasked. */
2224 dev_priv
->gt_irq_mask
= ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
2225 gt_irqs
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
2228 gt_irqs
|= GT_RENDER_USER_INTERRUPT
;
2230 gt_irqs
|= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
|
2231 ILK_BSD_USER_INTERRUPT
;
2233 gt_irqs
|= GT_BLT_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
;
2236 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2237 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
2238 I915_WRITE(GTIER
, gt_irqs
);
2239 POSTING_READ(GTIER
);
2241 if (INTEL_INFO(dev
)->gen
>= 6) {
2242 pm_irqs
|= GEN6_PM_RPS_EVENTS
;
2245 pm_irqs
|= PM_VEBOX_USER_INTERRUPT
;
2247 dev_priv
->pm_irq_mask
= 0xffffffff;
2248 I915_WRITE(GEN6_PMIIR
, I915_READ(GEN6_PMIIR
));
2249 I915_WRITE(GEN6_PMIMR
, dev_priv
->pm_irq_mask
);
2250 I915_WRITE(GEN6_PMIER
, pm_irqs
);
2251 POSTING_READ(GEN6_PMIER
);
2255 static int ironlake_irq_postinstall(struct drm_device
*dev
)
2257 unsigned long irqflags
;
2258 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2259 u32 display_mask
, extra_mask
;
2261 if (INTEL_INFO(dev
)->gen
>= 7) {
2262 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
|
2263 DE_PCH_EVENT_IVB
| DE_PLANEC_FLIP_DONE_IVB
|
2264 DE_PLANEB_FLIP_DONE_IVB
|
2265 DE_PLANEA_FLIP_DONE_IVB
| DE_AUX_CHANNEL_A_IVB
|
2267 extra_mask
= (DE_PIPEC_VBLANK_IVB
| DE_PIPEB_VBLANK_IVB
|
2268 DE_PIPEA_VBLANK_IVB
);
2270 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2272 display_mask
= (DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
2273 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
|
2274 DE_AUX_CHANNEL_A
| DE_PIPEB_FIFO_UNDERRUN
|
2275 DE_PIPEA_FIFO_UNDERRUN
| DE_POISON
);
2276 extra_mask
= DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
| DE_PCU_EVENT
;
2279 dev_priv
->irq_mask
= ~display_mask
;
2281 /* should always can generate irq */
2282 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2283 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
2284 I915_WRITE(DEIER
, display_mask
| extra_mask
);
2285 POSTING_READ(DEIER
);
2287 gen5_gt_irq_postinstall(dev
);
2289 ibx_irq_postinstall(dev
);
2291 if (IS_IRONLAKE_M(dev
)) {
2292 /* Enable PCU event interrupts
2294 * spinlocking not required here for correctness since interrupt
2295 * setup is guaranteed to run in single-threaded context. But we
2296 * need it to make the assert_spin_locked happy. */
2297 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2298 ironlake_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
2299 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2305 static int valleyview_irq_postinstall(struct drm_device
*dev
)
2307 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2309 u32 pipestat_enable
= PLANE_FLIP_DONE_INT_EN_VLV
;
2310 unsigned long irqflags
;
2312 enable_mask
= I915_DISPLAY_PORT_INTERRUPT
;
2313 enable_mask
|= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2314 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2315 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2316 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2319 *Leave vblank interrupts masked initially. enable/disable will
2320 * toggle them based on usage.
2322 dev_priv
->irq_mask
= (~enable_mask
) |
2323 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2324 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2326 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2327 POSTING_READ(PORT_HOTPLUG_EN
);
2329 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
2330 I915_WRITE(VLV_IER
, enable_mask
);
2331 I915_WRITE(VLV_IIR
, 0xffffffff);
2332 I915_WRITE(PIPESTAT(0), 0xffff);
2333 I915_WRITE(PIPESTAT(1), 0xffff);
2334 POSTING_READ(VLV_IER
);
2336 /* Interrupt setup is already guaranteed to be single-threaded, this is
2337 * just to make the assert_spin_locked check happy. */
2338 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2339 i915_enable_pipestat(dev_priv
, 0, pipestat_enable
);
2340 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
2341 i915_enable_pipestat(dev_priv
, 1, pipestat_enable
);
2342 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2344 I915_WRITE(VLV_IIR
, 0xffffffff);
2345 I915_WRITE(VLV_IIR
, 0xffffffff);
2347 gen5_gt_irq_postinstall(dev
);
2349 /* ack & enable invalid PTE error interrupts */
2350 #if 0 /* FIXME: add support to irq handler for checking these bits */
2351 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
2352 I915_WRITE(DPINVGTT
, DPINVGTT_EN_MASK
);
2355 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
2360 static void valleyview_irq_uninstall(struct drm_device
*dev
)
2362 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2368 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2371 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2373 I915_WRITE(HWSTAM
, 0xffffffff);
2374 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2375 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2377 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2378 I915_WRITE(VLV_IIR
, 0xffffffff);
2379 I915_WRITE(VLV_IMR
, 0xffffffff);
2380 I915_WRITE(VLV_IER
, 0x0);
2381 POSTING_READ(VLV_IER
);
2384 static void ironlake_irq_uninstall(struct drm_device
*dev
)
2386 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2391 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2393 I915_WRITE(HWSTAM
, 0xffffffff);
2395 I915_WRITE(DEIMR
, 0xffffffff);
2396 I915_WRITE(DEIER
, 0x0);
2397 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2399 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2401 I915_WRITE(GTIMR
, 0xffffffff);
2402 I915_WRITE(GTIER
, 0x0);
2403 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2405 if (HAS_PCH_NOP(dev
))
2408 I915_WRITE(SDEIMR
, 0xffffffff);
2409 I915_WRITE(SDEIER
, 0x0);
2410 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2411 if (HAS_PCH_CPT(dev
) || HAS_PCH_LPT(dev
))
2412 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2415 static void i8xx_irq_preinstall(struct drm_device
* dev
)
2417 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2420 atomic_set(&dev_priv
->irq_received
, 0);
2423 I915_WRITE(PIPESTAT(pipe
), 0);
2424 I915_WRITE16(IMR
, 0xffff);
2425 I915_WRITE16(IER
, 0x0);
2426 POSTING_READ16(IER
);
2429 static int i8xx_irq_postinstall(struct drm_device
*dev
)
2431 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2434 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2436 /* Unmask the interrupts that we always want on. */
2437 dev_priv
->irq_mask
=
2438 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2439 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2440 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2441 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2442 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2443 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
2446 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2447 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2448 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2449 I915_USER_INTERRUPT
);
2450 POSTING_READ16(IER
);
2456 * Returns true when a page flip has completed.
2458 static bool i8xx_handle_vblank(struct drm_device
*dev
,
2461 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2462 u16 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(pipe
);
2464 if (!drm_handle_vblank(dev
, pipe
))
2467 if ((iir
& flip_pending
) == 0)
2470 intel_prepare_page_flip(dev
, pipe
);
2472 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2473 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2474 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2475 * the flip is completed (no longer pending). Since this doesn't raise
2476 * an interrupt per se, we watch for the change at vblank.
2478 if (I915_READ16(ISR
) & flip_pending
)
2481 intel_finish_page_flip(dev
, pipe
);
2486 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
2488 struct drm_device
*dev
= (struct drm_device
*) arg
;
2489 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2492 unsigned long irqflags
;
2495 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2496 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2498 atomic_inc(&dev_priv
->irq_received
);
2500 iir
= I915_READ16(IIR
);
2504 while (iir
& ~flip_mask
) {
2505 /* Can't rely on pipestat interrupt bit in iir as it might
2506 * have been cleared after the pipestat interrupt was received.
2507 * It doesn't set the bit in iir again, but it still produces
2508 * interrupts (for non-MSI).
2510 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2511 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2512 i915_handle_error(dev
, false);
2514 for_each_pipe(pipe
) {
2515 int reg
= PIPESTAT(pipe
);
2516 pipe_stats
[pipe
] = I915_READ(reg
);
2519 * Clear the PIPE*STAT regs before the IIR
2521 if (pipe_stats
[pipe
] & 0x8000ffff) {
2522 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2523 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2525 I915_WRITE(reg
, pipe_stats
[pipe
]);
2528 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2530 I915_WRITE16(IIR
, iir
& ~flip_mask
);
2531 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
2533 i915_update_dri1_breadcrumb(dev
);
2535 if (iir
& I915_USER_INTERRUPT
)
2536 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2538 if (pipe_stats
[0] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2539 i8xx_handle_vblank(dev
, 0, iir
))
2540 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(0);
2542 if (pipe_stats
[1] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2543 i8xx_handle_vblank(dev
, 1, iir
))
2544 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(1);
2552 static void i8xx_irq_uninstall(struct drm_device
* dev
)
2554 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2557 for_each_pipe(pipe
) {
2558 /* Clear enable bits; then clear status bits */
2559 I915_WRITE(PIPESTAT(pipe
), 0);
2560 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
2562 I915_WRITE16(IMR
, 0xffff);
2563 I915_WRITE16(IER
, 0x0);
2564 I915_WRITE16(IIR
, I915_READ16(IIR
));
2567 static void i915_irq_preinstall(struct drm_device
* dev
)
2569 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2572 atomic_set(&dev_priv
->irq_received
, 0);
2574 if (I915_HAS_HOTPLUG(dev
)) {
2575 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2576 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2579 I915_WRITE16(HWSTAM
, 0xeffe);
2581 I915_WRITE(PIPESTAT(pipe
), 0);
2582 I915_WRITE(IMR
, 0xffffffff);
2583 I915_WRITE(IER
, 0x0);
2587 static int i915_irq_postinstall(struct drm_device
*dev
)
2589 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2592 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2594 /* Unmask the interrupts that we always want on. */
2595 dev_priv
->irq_mask
=
2596 ~(I915_ASLE_INTERRUPT
|
2597 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2598 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2599 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2600 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2601 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2604 I915_ASLE_INTERRUPT
|
2605 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2606 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2607 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2608 I915_USER_INTERRUPT
;
2610 if (I915_HAS_HOTPLUG(dev
)) {
2611 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2612 POSTING_READ(PORT_HOTPLUG_EN
);
2614 /* Enable in IER... */
2615 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
2616 /* and unmask in IMR */
2617 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
2620 I915_WRITE(IMR
, dev_priv
->irq_mask
);
2621 I915_WRITE(IER
, enable_mask
);
2624 i915_enable_asle_pipestat(dev
);
2630 * Returns true when a page flip has completed.
2632 static bool i915_handle_vblank(struct drm_device
*dev
,
2633 int plane
, int pipe
, u32 iir
)
2635 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2636 u32 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
2638 if (!drm_handle_vblank(dev
, pipe
))
2641 if ((iir
& flip_pending
) == 0)
2644 intel_prepare_page_flip(dev
, plane
);
2646 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2647 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2648 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2649 * the flip is completed (no longer pending). Since this doesn't raise
2650 * an interrupt per se, we watch for the change at vblank.
2652 if (I915_READ(ISR
) & flip_pending
)
2655 intel_finish_page_flip(dev
, pipe
);
2660 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
2662 struct drm_device
*dev
= (struct drm_device
*) arg
;
2663 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2664 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
2665 unsigned long irqflags
;
2667 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2668 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2669 int pipe
, ret
= IRQ_NONE
;
2671 atomic_inc(&dev_priv
->irq_received
);
2673 iir
= I915_READ(IIR
);
2675 bool irq_received
= (iir
& ~flip_mask
) != 0;
2676 bool blc_event
= false;
2678 /* Can't rely on pipestat interrupt bit in iir as it might
2679 * have been cleared after the pipestat interrupt was received.
2680 * It doesn't set the bit in iir again, but it still produces
2681 * interrupts (for non-MSI).
2683 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2684 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2685 i915_handle_error(dev
, false);
2687 for_each_pipe(pipe
) {
2688 int reg
= PIPESTAT(pipe
);
2689 pipe_stats
[pipe
] = I915_READ(reg
);
2691 /* Clear the PIPE*STAT regs before the IIR */
2692 if (pipe_stats
[pipe
] & 0x8000ffff) {
2693 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2694 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2696 I915_WRITE(reg
, pipe_stats
[pipe
]);
2697 irq_received
= true;
2700 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2705 /* Consume port. Then clear IIR or we'll miss events */
2706 if ((I915_HAS_HOTPLUG(dev
)) &&
2707 (iir
& I915_DISPLAY_PORT_INTERRUPT
)) {
2708 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
2709 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
2711 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2714 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
2716 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
2717 POSTING_READ(PORT_HOTPLUG_STAT
);
2720 I915_WRITE(IIR
, iir
& ~flip_mask
);
2721 new_iir
= I915_READ(IIR
); /* Flush posted writes */
2723 if (iir
& I915_USER_INTERRUPT
)
2724 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2726 for_each_pipe(pipe
) {
2731 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2732 i915_handle_vblank(dev
, plane
, pipe
, iir
))
2733 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
2735 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
2739 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
2740 intel_opregion_asle_intr(dev
);
2742 /* With MSI, interrupts are only generated when iir
2743 * transitions from zero to nonzero. If another bit got
2744 * set while we were handling the existing iir bits, then
2745 * we would never get another interrupt.
2747 * This is fine on non-MSI as well, as if we hit this path
2748 * we avoid exiting the interrupt handler only to generate
2751 * Note that for MSI this could cause a stray interrupt report
2752 * if an interrupt landed in the time between writing IIR and
2753 * the posting read. This should be rare enough to never
2754 * trigger the 99% of 100,000 interrupts test for disabling
2759 } while (iir
& ~flip_mask
);
2761 i915_update_dri1_breadcrumb(dev
);
2766 static void i915_irq_uninstall(struct drm_device
* dev
)
2768 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2771 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2773 if (I915_HAS_HOTPLUG(dev
)) {
2774 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2775 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2778 I915_WRITE16(HWSTAM
, 0xffff);
2779 for_each_pipe(pipe
) {
2780 /* Clear enable bits; then clear status bits */
2781 I915_WRITE(PIPESTAT(pipe
), 0);
2782 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
2784 I915_WRITE(IMR
, 0xffffffff);
2785 I915_WRITE(IER
, 0x0);
2787 I915_WRITE(IIR
, I915_READ(IIR
));
2790 static void i965_irq_preinstall(struct drm_device
* dev
)
2792 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2795 atomic_set(&dev_priv
->irq_received
, 0);
2797 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2798 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2800 I915_WRITE(HWSTAM
, 0xeffe);
2802 I915_WRITE(PIPESTAT(pipe
), 0);
2803 I915_WRITE(IMR
, 0xffffffff);
2804 I915_WRITE(IER
, 0x0);
2808 static int i965_irq_postinstall(struct drm_device
*dev
)
2810 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2813 unsigned long irqflags
;
2815 /* Unmask the interrupts that we always want on. */
2816 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
2817 I915_DISPLAY_PORT_INTERRUPT
|
2818 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2819 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2820 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2821 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2822 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2824 enable_mask
= ~dev_priv
->irq_mask
;
2825 enable_mask
&= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2826 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
2827 enable_mask
|= I915_USER_INTERRUPT
;
2830 enable_mask
|= I915_BSD_USER_INTERRUPT
;
2832 /* Interrupt setup is already guaranteed to be single-threaded, this is
2833 * just to make the assert_spin_locked check happy. */
2834 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2835 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
2836 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2839 * Enable some error detection, note the instruction error mask
2840 * bit is reserved, so we leave it masked.
2843 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
2844 GM45_ERROR_MEM_PRIV
|
2845 GM45_ERROR_CP_PRIV
|
2846 I915_ERROR_MEMORY_REFRESH
);
2848 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
2849 I915_ERROR_MEMORY_REFRESH
);
2851 I915_WRITE(EMR
, error_mask
);
2853 I915_WRITE(IMR
, dev_priv
->irq_mask
);
2854 I915_WRITE(IER
, enable_mask
);
2857 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2858 POSTING_READ(PORT_HOTPLUG_EN
);
2860 i915_enable_asle_pipestat(dev
);
2865 static void i915_hpd_irq_setup(struct drm_device
*dev
)
2867 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2868 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2869 struct intel_encoder
*intel_encoder
;
2872 assert_spin_locked(&dev_priv
->irq_lock
);
2874 if (I915_HAS_HOTPLUG(dev
)) {
2875 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
2876 hotplug_en
&= ~HOTPLUG_INT_EN_MASK
;
2877 /* Note HDMI and DP share hotplug bits */
2878 /* enable bits are the same for all generations */
2879 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2880 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2881 hotplug_en
|= hpd_mask_i915
[intel_encoder
->hpd_pin
];
2882 /* Programming the CRT detection parameters tends
2883 to generate a spurious hotplug event about three
2884 seconds later. So just do it once.
2887 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
2888 hotplug_en
&= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK
;
2889 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
2891 /* Ignore TV since it's buggy */
2892 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
2896 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
2898 struct drm_device
*dev
= (struct drm_device
*) arg
;
2899 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2901 u32 pipe_stats
[I915_MAX_PIPES
];
2902 unsigned long irqflags
;
2904 int ret
= IRQ_NONE
, pipe
;
2906 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2907 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2909 atomic_inc(&dev_priv
->irq_received
);
2911 iir
= I915_READ(IIR
);
2914 bool blc_event
= false;
2916 irq_received
= (iir
& ~flip_mask
) != 0;
2918 /* Can't rely on pipestat interrupt bit in iir as it might
2919 * have been cleared after the pipestat interrupt was received.
2920 * It doesn't set the bit in iir again, but it still produces
2921 * interrupts (for non-MSI).
2923 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2924 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2925 i915_handle_error(dev
, false);
2927 for_each_pipe(pipe
) {
2928 int reg
= PIPESTAT(pipe
);
2929 pipe_stats
[pipe
] = I915_READ(reg
);
2932 * Clear the PIPE*STAT regs before the IIR
2934 if (pipe_stats
[pipe
] & 0x8000ffff) {
2935 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2936 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2938 I915_WRITE(reg
, pipe_stats
[pipe
]);
2942 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2949 /* Consume port. Then clear IIR or we'll miss events */
2950 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
2951 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
2952 u32 hotplug_trigger
= hotplug_status
& (IS_G4X(dev
) ?
2953 HOTPLUG_INT_STATUS_G4X
:
2954 HOTPLUG_INT_STATUS_I915
);
2956 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2959 intel_hpd_irq_handler(dev
, hotplug_trigger
,
2960 IS_G4X(dev
) ? hpd_status_gen4
: hpd_status_i915
);
2962 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
2963 I915_READ(PORT_HOTPLUG_STAT
);
2966 I915_WRITE(IIR
, iir
& ~flip_mask
);
2967 new_iir
= I915_READ(IIR
); /* Flush posted writes */
2969 if (iir
& I915_USER_INTERRUPT
)
2970 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2971 if (iir
& I915_BSD_USER_INTERRUPT
)
2972 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
2974 for_each_pipe(pipe
) {
2975 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
2976 i915_handle_vblank(dev
, pipe
, pipe
, iir
))
2977 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
2979 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
2984 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
2985 intel_opregion_asle_intr(dev
);
2987 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
2988 gmbus_irq_handler(dev
);
2990 /* With MSI, interrupts are only generated when iir
2991 * transitions from zero to nonzero. If another bit got
2992 * set while we were handling the existing iir bits, then
2993 * we would never get another interrupt.
2995 * This is fine on non-MSI as well, as if we hit this path
2996 * we avoid exiting the interrupt handler only to generate
2999 * Note that for MSI this could cause a stray interrupt report
3000 * if an interrupt landed in the time between writing IIR and
3001 * the posting read. This should be rare enough to never
3002 * trigger the 99% of 100,000 interrupts test for disabling
3008 i915_update_dri1_breadcrumb(dev
);
3013 static void i965_irq_uninstall(struct drm_device
* dev
)
3015 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3021 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
3023 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3024 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3026 I915_WRITE(HWSTAM
, 0xffffffff);
3028 I915_WRITE(PIPESTAT(pipe
), 0);
3029 I915_WRITE(IMR
, 0xffffffff);
3030 I915_WRITE(IER
, 0x0);
3033 I915_WRITE(PIPESTAT(pipe
),
3034 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
3035 I915_WRITE(IIR
, I915_READ(IIR
));
3038 static void i915_reenable_hotplug_timer_func(unsigned long data
)
3040 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*)data
;
3041 struct drm_device
*dev
= dev_priv
->dev
;
3042 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3043 unsigned long irqflags
;
3046 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3047 for (i
= (HPD_NONE
+ 1); i
< HPD_NUM_PINS
; i
++) {
3048 struct drm_connector
*connector
;
3050 if (dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_DISABLED
)
3053 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3055 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3056 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3058 if (intel_connector
->encoder
->hpd_pin
== i
) {
3059 if (connector
->polled
!= intel_connector
->polled
)
3060 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3061 drm_get_connector_name(connector
));
3062 connector
->polled
= intel_connector
->polled
;
3063 if (!connector
->polled
)
3064 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3068 if (dev_priv
->display
.hpd_irq_setup
)
3069 dev_priv
->display
.hpd_irq_setup(dev
);
3070 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3073 void intel_irq_init(struct drm_device
*dev
)
3075 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3077 INIT_WORK(&dev_priv
->hotplug_work
, i915_hotplug_work_func
);
3078 INIT_WORK(&dev_priv
->gpu_error
.work
, i915_error_work_func
);
3079 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
3080 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
3082 setup_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
3083 i915_hangcheck_elapsed
,
3084 (unsigned long) dev
);
3085 setup_timer(&dev_priv
->hotplug_reenable_timer
, i915_reenable_hotplug_timer_func
,
3086 (unsigned long) dev_priv
);
3088 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
, PM_QOS_DEFAULT_VALUE
);
3090 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
3091 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
3092 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
3093 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
3094 dev
->driver
->get_vblank_counter
= gm45_get_vblank_counter
;
3097 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3098 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
3100 dev
->driver
->get_vblank_timestamp
= NULL
;
3101 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
3103 if (IS_VALLEYVIEW(dev
)) {
3104 dev
->driver
->irq_handler
= valleyview_irq_handler
;
3105 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
3106 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
3107 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
3108 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
3109 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
3110 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3111 } else if (HAS_PCH_SPLIT(dev
)) {
3112 dev
->driver
->irq_handler
= ironlake_irq_handler
;
3113 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
3114 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
3115 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
3116 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
3117 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
3118 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
3120 if (INTEL_INFO(dev
)->gen
== 2) {
3121 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
3122 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
3123 dev
->driver
->irq_handler
= i8xx_irq_handler
;
3124 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
3125 } else if (INTEL_INFO(dev
)->gen
== 3) {
3126 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
3127 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
3128 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
3129 dev
->driver
->irq_handler
= i915_irq_handler
;
3130 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3132 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
3133 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
3134 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
3135 dev
->driver
->irq_handler
= i965_irq_handler
;
3136 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3138 dev
->driver
->enable_vblank
= i915_enable_vblank
;
3139 dev
->driver
->disable_vblank
= i915_disable_vblank
;
3143 void intel_hpd_init(struct drm_device
*dev
)
3145 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3146 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3147 struct drm_connector
*connector
;
3148 unsigned long irqflags
;
3151 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
3152 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
3153 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3155 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3156 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3157 connector
->polled
= intel_connector
->polled
;
3158 if (!connector
->polled
&& I915_HAS_HOTPLUG(dev
) && intel_connector
->encoder
->hpd_pin
> HPD_NONE
)
3159 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3162 /* Interrupt setup is already guaranteed to be single-threaded, this is
3163 * just to make the assert_spin_locked checks happy. */
3164 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3165 if (dev_priv
->display
.hpd_irq_setup
)
3166 dev_priv
->display
.hpd_irq_setup(dev
);
3167 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3170 /* Disable interrupts so we can allow Package C8+. */
3171 void hsw_pc8_disable_interrupts(struct drm_device
*dev
)
3173 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3174 unsigned long irqflags
;
3176 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3178 dev_priv
->pc8
.regsave
.deimr
= I915_READ(DEIMR
);
3179 dev_priv
->pc8
.regsave
.sdeimr
= I915_READ(SDEIMR
);
3180 dev_priv
->pc8
.regsave
.gtimr
= I915_READ(GTIMR
);
3181 dev_priv
->pc8
.regsave
.gtier
= I915_READ(GTIER
);
3182 dev_priv
->pc8
.regsave
.gen6_pmimr
= I915_READ(GEN6_PMIMR
);
3184 ironlake_disable_display_irq(dev_priv
, ~DE_PCH_EVENT_IVB
);
3185 ibx_disable_display_interrupt(dev_priv
, ~SDE_HOTPLUG_MASK_CPT
);
3186 ilk_disable_gt_irq(dev_priv
, 0xffffffff);
3187 snb_disable_pm_irq(dev_priv
, 0xffffffff);
3189 dev_priv
->pc8
.irqs_disabled
= true;
3191 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3194 /* Restore interrupts so we can recover from Package C8+. */
3195 void hsw_pc8_restore_interrupts(struct drm_device
*dev
)
3197 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3198 unsigned long irqflags
;
3199 uint32_t val
, expected
;
3201 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3203 val
= I915_READ(DEIMR
);
3204 expected
= ~DE_PCH_EVENT_IVB
;
3205 WARN(val
!= expected
, "DEIMR is 0x%08x, not 0x%08x\n", val
, expected
);
3207 val
= I915_READ(SDEIMR
) & ~SDE_HOTPLUG_MASK_CPT
;
3208 expected
= ~SDE_HOTPLUG_MASK_CPT
;
3209 WARN(val
!= expected
, "SDEIMR non-HPD bits are 0x%08x, not 0x%08x\n",
3212 val
= I915_READ(GTIMR
);
3213 expected
= 0xffffffff;
3214 WARN(val
!= expected
, "GTIMR is 0x%08x, not 0x%08x\n", val
, expected
);
3216 val
= I915_READ(GEN6_PMIMR
);
3217 expected
= 0xffffffff;
3218 WARN(val
!= expected
, "GEN6_PMIMR is 0x%08x, not 0x%08x\n", val
,
3221 dev_priv
->pc8
.irqs_disabled
= false;
3223 ironlake_enable_display_irq(dev_priv
, ~dev_priv
->pc8
.regsave
.deimr
);
3224 ibx_enable_display_interrupt(dev_priv
,
3225 ~dev_priv
->pc8
.regsave
.sdeimr
&
3226 ~SDE_HOTPLUG_MASK_CPT
);
3227 ilk_enable_gt_irq(dev_priv
, ~dev_priv
->pc8
.regsave
.gtimr
);
3228 snb_enable_pm_irq(dev_priv
, ~dev_priv
->pc8
.regsave
.gen6_pmimr
);
3229 I915_WRITE(GTIER
, dev_priv
->pc8
.regsave
.gtier
);
3231 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);