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drm/i915: add a new BSD ring buffer for Sandybridge
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #include <linux/sysrq.h>
30 #include <linux/slab.h>
31 #include "drmP.h"
32 #include "drm.h"
33 #include "i915_drm.h"
34 #include "i915_drv.h"
35 #include "i915_trace.h"
36 #include "intel_drv.h"
37
38 #define MAX_NOPID ((u32)~0)
39
40 /**
41 * Interrupts that are always left unmasked.
42 *
43 * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
44 * we leave them always unmasked in IMR and then control enabling them through
45 * PIPESTAT alone.
46 */
47 #define I915_INTERRUPT_ENABLE_FIX \
48 (I915_ASLE_INTERRUPT | \
49 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
50 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
51 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \
52 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \
53 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
54
55 /** Interrupts that we mask and unmask at runtime. */
56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
57
58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
59 PIPE_VBLANK_INTERRUPT_STATUS)
60
61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
62 PIPE_VBLANK_INTERRUPT_ENABLE)
63
64 #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
65 DRM_I915_VBLANK_PIPE_B)
66
67 void
68 ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
69 {
70 if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
71 dev_priv->gt_irq_mask_reg &= ~mask;
72 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
73 (void) I915_READ(GTIMR);
74 }
75 }
76
77 void
78 ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
79 {
80 if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
81 dev_priv->gt_irq_mask_reg |= mask;
82 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
83 (void) I915_READ(GTIMR);
84 }
85 }
86
87 /* For display hotplug interrupt */
88 static void
89 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
90 {
91 if ((dev_priv->irq_mask_reg & mask) != 0) {
92 dev_priv->irq_mask_reg &= ~mask;
93 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
94 (void) I915_READ(DEIMR);
95 }
96 }
97
98 static inline void
99 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
100 {
101 if ((dev_priv->irq_mask_reg & mask) != mask) {
102 dev_priv->irq_mask_reg |= mask;
103 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
104 (void) I915_READ(DEIMR);
105 }
106 }
107
108 void
109 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
110 {
111 if ((dev_priv->irq_mask_reg & mask) != 0) {
112 dev_priv->irq_mask_reg &= ~mask;
113 I915_WRITE(IMR, dev_priv->irq_mask_reg);
114 (void) I915_READ(IMR);
115 }
116 }
117
118 void
119 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
120 {
121 if ((dev_priv->irq_mask_reg & mask) != mask) {
122 dev_priv->irq_mask_reg |= mask;
123 I915_WRITE(IMR, dev_priv->irq_mask_reg);
124 (void) I915_READ(IMR);
125 }
126 }
127
128 static inline u32
129 i915_pipestat(int pipe)
130 {
131 if (pipe == 0)
132 return PIPEASTAT;
133 if (pipe == 1)
134 return PIPEBSTAT;
135 BUG();
136 }
137
138 void
139 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
140 {
141 if ((dev_priv->pipestat[pipe] & mask) != mask) {
142 u32 reg = i915_pipestat(pipe);
143
144 dev_priv->pipestat[pipe] |= mask;
145 /* Enable the interrupt, clear any pending status */
146 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
147 (void) I915_READ(reg);
148 }
149 }
150
151 void
152 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
153 {
154 if ((dev_priv->pipestat[pipe] & mask) != 0) {
155 u32 reg = i915_pipestat(pipe);
156
157 dev_priv->pipestat[pipe] &= ~mask;
158 I915_WRITE(reg, dev_priv->pipestat[pipe]);
159 (void) I915_READ(reg);
160 }
161 }
162
163 /**
164 * intel_enable_asle - enable ASLE interrupt for OpRegion
165 */
166 void intel_enable_asle (struct drm_device *dev)
167 {
168 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
169
170 if (HAS_PCH_SPLIT(dev))
171 ironlake_enable_display_irq(dev_priv, DE_GSE);
172 else {
173 i915_enable_pipestat(dev_priv, 1,
174 PIPE_LEGACY_BLC_EVENT_ENABLE);
175 if (INTEL_INFO(dev)->gen >= 4)
176 i915_enable_pipestat(dev_priv, 0,
177 PIPE_LEGACY_BLC_EVENT_ENABLE);
178 }
179 }
180
181 /**
182 * i915_pipe_enabled - check if a pipe is enabled
183 * @dev: DRM device
184 * @pipe: pipe to check
185 *
186 * Reading certain registers when the pipe is disabled can hang the chip.
187 * Use this routine to make sure the PLL is running and the pipe is active
188 * before reading such registers if unsure.
189 */
190 static int
191 i915_pipe_enabled(struct drm_device *dev, int pipe)
192 {
193 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
194 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
195 }
196
197 /* Called from drm generic code, passed a 'crtc', which
198 * we use as a pipe index
199 */
200 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
201 {
202 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
203 unsigned long high_frame;
204 unsigned long low_frame;
205 u32 high1, high2, low;
206
207 if (!i915_pipe_enabled(dev, pipe)) {
208 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
209 "pipe %d\n", pipe);
210 return 0;
211 }
212
213 high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
214 low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
215
216 /*
217 * High & low register fields aren't synchronized, so make sure
218 * we get a low value that's stable across two reads of the high
219 * register.
220 */
221 do {
222 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
223 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
224 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
225 } while (high1 != high2);
226
227 high1 >>= PIPE_FRAME_HIGH_SHIFT;
228 low >>= PIPE_FRAME_LOW_SHIFT;
229 return (high1 << 8) | low;
230 }
231
232 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
233 {
234 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
235 int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
236
237 if (!i915_pipe_enabled(dev, pipe)) {
238 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
239 "pipe %d\n", pipe);
240 return 0;
241 }
242
243 return I915_READ(reg);
244 }
245
246 /*
247 * Handle hotplug events outside the interrupt handler proper.
248 */
249 static void i915_hotplug_work_func(struct work_struct *work)
250 {
251 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
252 hotplug_work);
253 struct drm_device *dev = dev_priv->dev;
254 struct drm_mode_config *mode_config = &dev->mode_config;
255 struct intel_encoder *encoder;
256
257 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
258 if (encoder->hot_plug)
259 encoder->hot_plug(encoder);
260
261 /* Just fire off a uevent and let userspace tell us what to do */
262 drm_helper_hpd_irq_event(dev);
263 }
264
265 static void i915_handle_rps_change(struct drm_device *dev)
266 {
267 drm_i915_private_t *dev_priv = dev->dev_private;
268 u32 busy_up, busy_down, max_avg, min_avg;
269 u8 new_delay = dev_priv->cur_delay;
270
271 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
272 busy_up = I915_READ(RCPREVBSYTUPAVG);
273 busy_down = I915_READ(RCPREVBSYTDNAVG);
274 max_avg = I915_READ(RCBMAXAVG);
275 min_avg = I915_READ(RCBMINAVG);
276
277 /* Handle RCS change request from hw */
278 if (busy_up > max_avg) {
279 if (dev_priv->cur_delay != dev_priv->max_delay)
280 new_delay = dev_priv->cur_delay - 1;
281 if (new_delay < dev_priv->max_delay)
282 new_delay = dev_priv->max_delay;
283 } else if (busy_down < min_avg) {
284 if (dev_priv->cur_delay != dev_priv->min_delay)
285 new_delay = dev_priv->cur_delay + 1;
286 if (new_delay > dev_priv->min_delay)
287 new_delay = dev_priv->min_delay;
288 }
289
290 if (ironlake_set_drps(dev, new_delay))
291 dev_priv->cur_delay = new_delay;
292
293 return;
294 }
295
296 static irqreturn_t ironlake_irq_handler(struct drm_device *dev)
297 {
298 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
299 int ret = IRQ_NONE;
300 u32 de_iir, gt_iir, de_ier, pch_iir;
301 struct drm_i915_master_private *master_priv;
302 struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
303 u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
304
305 if (IS_GEN6(dev))
306 bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
307
308 /* disable master interrupt before clearing iir */
309 de_ier = I915_READ(DEIER);
310 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
311 (void)I915_READ(DEIER);
312
313 de_iir = I915_READ(DEIIR);
314 gt_iir = I915_READ(GTIIR);
315 pch_iir = I915_READ(SDEIIR);
316
317 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
318 goto done;
319
320 ret = IRQ_HANDLED;
321
322 if (dev->primary->master) {
323 master_priv = dev->primary->master->driver_priv;
324 if (master_priv->sarea_priv)
325 master_priv->sarea_priv->last_dispatch =
326 READ_BREADCRUMB(dev_priv);
327 }
328
329 if (gt_iir & GT_PIPE_NOTIFY) {
330 u32 seqno = render_ring->get_gem_seqno(dev, render_ring);
331 render_ring->irq_gem_seqno = seqno;
332 trace_i915_gem_request_complete(dev, seqno);
333 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
334 dev_priv->hangcheck_count = 0;
335 mod_timer(&dev_priv->hangcheck_timer,
336 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
337 }
338 if (gt_iir & bsd_usr_interrupt)
339 DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
340
341 if (de_iir & DE_GSE)
342 intel_opregion_gse_intr(dev);
343
344 if (de_iir & DE_PLANEA_FLIP_DONE) {
345 intel_prepare_page_flip(dev, 0);
346 intel_finish_page_flip_plane(dev, 0);
347 }
348
349 if (de_iir & DE_PLANEB_FLIP_DONE) {
350 intel_prepare_page_flip(dev, 1);
351 intel_finish_page_flip_plane(dev, 1);
352 }
353
354 if (de_iir & DE_PIPEA_VBLANK)
355 drm_handle_vblank(dev, 0);
356
357 if (de_iir & DE_PIPEB_VBLANK)
358 drm_handle_vblank(dev, 1);
359
360 /* check event from PCH */
361 if ((de_iir & DE_PCH_EVENT) &&
362 (pch_iir & SDE_HOTPLUG_MASK)) {
363 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
364 }
365
366 if (de_iir & DE_PCU_EVENT) {
367 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
368 i915_handle_rps_change(dev);
369 }
370
371 /* should clear PCH hotplug event before clear CPU irq */
372 I915_WRITE(SDEIIR, pch_iir);
373 I915_WRITE(GTIIR, gt_iir);
374 I915_WRITE(DEIIR, de_iir);
375
376 done:
377 I915_WRITE(DEIER, de_ier);
378 (void)I915_READ(DEIER);
379
380 return ret;
381 }
382
383 /**
384 * i915_error_work_func - do process context error handling work
385 * @work: work struct
386 *
387 * Fire an error uevent so userspace can see that a hang or error
388 * was detected.
389 */
390 static void i915_error_work_func(struct work_struct *work)
391 {
392 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
393 error_work);
394 struct drm_device *dev = dev_priv->dev;
395 char *error_event[] = { "ERROR=1", NULL };
396 char *reset_event[] = { "RESET=1", NULL };
397 char *reset_done_event[] = { "ERROR=0", NULL };
398
399 DRM_DEBUG_DRIVER("generating error event\n");
400 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
401
402 if (atomic_read(&dev_priv->mm.wedged)) {
403 DRM_DEBUG_DRIVER("resetting chip\n");
404 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
405 if (!i915_reset(dev, GRDOM_RENDER)) {
406 atomic_set(&dev_priv->mm.wedged, 0);
407 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
408 }
409 }
410 }
411
412 #ifdef CONFIG_DEBUG_FS
413 static struct drm_i915_error_object *
414 i915_error_object_create(struct drm_device *dev,
415 struct drm_gem_object *src)
416 {
417 drm_i915_private_t *dev_priv = dev->dev_private;
418 struct drm_i915_error_object *dst;
419 struct drm_i915_gem_object *src_priv;
420 int page, page_count;
421 u32 reloc_offset;
422
423 if (src == NULL)
424 return NULL;
425
426 src_priv = to_intel_bo(src);
427 if (src_priv->pages == NULL)
428 return NULL;
429
430 page_count = src->size / PAGE_SIZE;
431
432 dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
433 if (dst == NULL)
434 return NULL;
435
436 reloc_offset = src_priv->gtt_offset;
437 for (page = 0; page < page_count; page++) {
438 unsigned long flags;
439 void __iomem *s;
440 void *d;
441
442 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
443 if (d == NULL)
444 goto unwind;
445
446 local_irq_save(flags);
447 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
448 reloc_offset,
449 KM_IRQ0);
450 memcpy_fromio(d, s, PAGE_SIZE);
451 io_mapping_unmap_atomic(s, KM_IRQ0);
452 local_irq_restore(flags);
453
454 dst->pages[page] = d;
455
456 reloc_offset += PAGE_SIZE;
457 }
458 dst->page_count = page_count;
459 dst->gtt_offset = src_priv->gtt_offset;
460
461 return dst;
462
463 unwind:
464 while (page--)
465 kfree(dst->pages[page]);
466 kfree(dst);
467 return NULL;
468 }
469
470 static void
471 i915_error_object_free(struct drm_i915_error_object *obj)
472 {
473 int page;
474
475 if (obj == NULL)
476 return;
477
478 for (page = 0; page < obj->page_count; page++)
479 kfree(obj->pages[page]);
480
481 kfree(obj);
482 }
483
484 static void
485 i915_error_state_free(struct drm_device *dev,
486 struct drm_i915_error_state *error)
487 {
488 i915_error_object_free(error->batchbuffer[0]);
489 i915_error_object_free(error->batchbuffer[1]);
490 i915_error_object_free(error->ringbuffer);
491 kfree(error->active_bo);
492 kfree(error->overlay);
493 kfree(error);
494 }
495
496 static u32
497 i915_get_bbaddr(struct drm_device *dev, u32 *ring)
498 {
499 u32 cmd;
500
501 if (IS_I830(dev) || IS_845G(dev))
502 cmd = MI_BATCH_BUFFER;
503 else if (INTEL_INFO(dev)->gen >= 4)
504 cmd = (MI_BATCH_BUFFER_START | (2 << 6) |
505 MI_BATCH_NON_SECURE_I965);
506 else
507 cmd = (MI_BATCH_BUFFER_START | (2 << 6));
508
509 return ring[0] == cmd ? ring[1] : 0;
510 }
511
512 static u32
513 i915_ringbuffer_last_batch(struct drm_device *dev)
514 {
515 struct drm_i915_private *dev_priv = dev->dev_private;
516 u32 head, bbaddr;
517 u32 *ring;
518
519 /* Locate the current position in the ringbuffer and walk back
520 * to find the most recently dispatched batch buffer.
521 */
522 bbaddr = 0;
523 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
524 ring = (u32 *)(dev_priv->render_ring.virtual_start + head);
525
526 while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
527 bbaddr = i915_get_bbaddr(dev, ring);
528 if (bbaddr)
529 break;
530 }
531
532 if (bbaddr == 0) {
533 ring = (u32 *)(dev_priv->render_ring.virtual_start
534 + dev_priv->render_ring.size);
535 while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
536 bbaddr = i915_get_bbaddr(dev, ring);
537 if (bbaddr)
538 break;
539 }
540 }
541
542 return bbaddr;
543 }
544
545 /**
546 * i915_capture_error_state - capture an error record for later analysis
547 * @dev: drm device
548 *
549 * Should be called when an error is detected (either a hang or an error
550 * interrupt) to capture error state from the time of the error. Fills
551 * out a structure which becomes available in debugfs for user level tools
552 * to pick up.
553 */
554 static void i915_capture_error_state(struct drm_device *dev)
555 {
556 struct drm_i915_private *dev_priv = dev->dev_private;
557 struct drm_i915_gem_object *obj_priv;
558 struct drm_i915_error_state *error;
559 struct drm_gem_object *batchbuffer[2];
560 unsigned long flags;
561 u32 bbaddr;
562 int count;
563
564 spin_lock_irqsave(&dev_priv->error_lock, flags);
565 error = dev_priv->first_error;
566 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
567 if (error)
568 return;
569
570 error = kmalloc(sizeof(*error), GFP_ATOMIC);
571 if (!error) {
572 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
573 return;
574 }
575
576 error->seqno = i915_get_gem_seqno(dev, &dev_priv->render_ring);
577 error->eir = I915_READ(EIR);
578 error->pgtbl_er = I915_READ(PGTBL_ER);
579 error->pipeastat = I915_READ(PIPEASTAT);
580 error->pipebstat = I915_READ(PIPEBSTAT);
581 error->instpm = I915_READ(INSTPM);
582 if (INTEL_INFO(dev)->gen < 4) {
583 error->ipeir = I915_READ(IPEIR);
584 error->ipehr = I915_READ(IPEHR);
585 error->instdone = I915_READ(INSTDONE);
586 error->acthd = I915_READ(ACTHD);
587 error->bbaddr = 0;
588 } else {
589 error->ipeir = I915_READ(IPEIR_I965);
590 error->ipehr = I915_READ(IPEHR_I965);
591 error->instdone = I915_READ(INSTDONE_I965);
592 error->instps = I915_READ(INSTPS);
593 error->instdone1 = I915_READ(INSTDONE1);
594 error->acthd = I915_READ(ACTHD_I965);
595 error->bbaddr = I915_READ64(BB_ADDR);
596 }
597
598 bbaddr = i915_ringbuffer_last_batch(dev);
599
600 /* Grab the current batchbuffer, most likely to have crashed. */
601 batchbuffer[0] = NULL;
602 batchbuffer[1] = NULL;
603 count = 0;
604 list_for_each_entry(obj_priv,
605 &dev_priv->render_ring.active_list, list) {
606
607 struct drm_gem_object *obj = &obj_priv->base;
608
609 if (batchbuffer[0] == NULL &&
610 bbaddr >= obj_priv->gtt_offset &&
611 bbaddr < obj_priv->gtt_offset + obj->size)
612 batchbuffer[0] = obj;
613
614 if (batchbuffer[1] == NULL &&
615 error->acthd >= obj_priv->gtt_offset &&
616 error->acthd < obj_priv->gtt_offset + obj->size)
617 batchbuffer[1] = obj;
618
619 count++;
620 }
621 /* Scan the other lists for completeness for those bizarre errors. */
622 if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
623 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
624 struct drm_gem_object *obj = &obj_priv->base;
625
626 if (batchbuffer[0] == NULL &&
627 bbaddr >= obj_priv->gtt_offset &&
628 bbaddr < obj_priv->gtt_offset + obj->size)
629 batchbuffer[0] = obj;
630
631 if (batchbuffer[1] == NULL &&
632 error->acthd >= obj_priv->gtt_offset &&
633 error->acthd < obj_priv->gtt_offset + obj->size)
634 batchbuffer[1] = obj;
635
636 if (batchbuffer[0] && batchbuffer[1])
637 break;
638 }
639 }
640 if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
641 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
642 struct drm_gem_object *obj = &obj_priv->base;
643
644 if (batchbuffer[0] == NULL &&
645 bbaddr >= obj_priv->gtt_offset &&
646 bbaddr < obj_priv->gtt_offset + obj->size)
647 batchbuffer[0] = obj;
648
649 if (batchbuffer[1] == NULL &&
650 error->acthd >= obj_priv->gtt_offset &&
651 error->acthd < obj_priv->gtt_offset + obj->size)
652 batchbuffer[1] = obj;
653
654 if (batchbuffer[0] && batchbuffer[1])
655 break;
656 }
657 }
658
659 /* We need to copy these to an anonymous buffer as the simplest
660 * method to avoid being overwritten by userpace.
661 */
662 error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]);
663 if (batchbuffer[1] != batchbuffer[0])
664 error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]);
665 else
666 error->batchbuffer[1] = NULL;
667
668 /* Record the ringbuffer */
669 error->ringbuffer = i915_error_object_create(dev,
670 dev_priv->render_ring.gem_object);
671
672 /* Record buffers on the active list. */
673 error->active_bo = NULL;
674 error->active_bo_count = 0;
675
676 if (count)
677 error->active_bo = kmalloc(sizeof(*error->active_bo)*count,
678 GFP_ATOMIC);
679
680 if (error->active_bo) {
681 int i = 0;
682 list_for_each_entry(obj_priv,
683 &dev_priv->render_ring.active_list, list) {
684 struct drm_gem_object *obj = &obj_priv->base;
685
686 error->active_bo[i].size = obj->size;
687 error->active_bo[i].name = obj->name;
688 error->active_bo[i].seqno = obj_priv->last_rendering_seqno;
689 error->active_bo[i].gtt_offset = obj_priv->gtt_offset;
690 error->active_bo[i].read_domains = obj->read_domains;
691 error->active_bo[i].write_domain = obj->write_domain;
692 error->active_bo[i].fence_reg = obj_priv->fence_reg;
693 error->active_bo[i].pinned = 0;
694 if (obj_priv->pin_count > 0)
695 error->active_bo[i].pinned = 1;
696 if (obj_priv->user_pin_count > 0)
697 error->active_bo[i].pinned = -1;
698 error->active_bo[i].tiling = obj_priv->tiling_mode;
699 error->active_bo[i].dirty = obj_priv->dirty;
700 error->active_bo[i].purgeable = obj_priv->madv != I915_MADV_WILLNEED;
701
702 if (++i == count)
703 break;
704 }
705 error->active_bo_count = i;
706 }
707
708 do_gettimeofday(&error->time);
709
710 error->overlay = intel_overlay_capture_error_state(dev);
711
712 spin_lock_irqsave(&dev_priv->error_lock, flags);
713 if (dev_priv->first_error == NULL) {
714 dev_priv->first_error = error;
715 error = NULL;
716 }
717 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
718
719 if (error)
720 i915_error_state_free(dev, error);
721 }
722
723 void i915_destroy_error_state(struct drm_device *dev)
724 {
725 struct drm_i915_private *dev_priv = dev->dev_private;
726 struct drm_i915_error_state *error;
727
728 spin_lock(&dev_priv->error_lock);
729 error = dev_priv->first_error;
730 dev_priv->first_error = NULL;
731 spin_unlock(&dev_priv->error_lock);
732
733 if (error)
734 i915_error_state_free(dev, error);
735 }
736 #else
737 #define i915_capture_error_state(x)
738 #endif
739
740 static void i915_report_and_clear_eir(struct drm_device *dev)
741 {
742 struct drm_i915_private *dev_priv = dev->dev_private;
743 u32 eir = I915_READ(EIR);
744
745 if (!eir)
746 return;
747
748 printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
749 eir);
750
751 if (IS_G4X(dev)) {
752 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
753 u32 ipeir = I915_READ(IPEIR_I965);
754
755 printk(KERN_ERR " IPEIR: 0x%08x\n",
756 I915_READ(IPEIR_I965));
757 printk(KERN_ERR " IPEHR: 0x%08x\n",
758 I915_READ(IPEHR_I965));
759 printk(KERN_ERR " INSTDONE: 0x%08x\n",
760 I915_READ(INSTDONE_I965));
761 printk(KERN_ERR " INSTPS: 0x%08x\n",
762 I915_READ(INSTPS));
763 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
764 I915_READ(INSTDONE1));
765 printk(KERN_ERR " ACTHD: 0x%08x\n",
766 I915_READ(ACTHD_I965));
767 I915_WRITE(IPEIR_I965, ipeir);
768 (void)I915_READ(IPEIR_I965);
769 }
770 if (eir & GM45_ERROR_PAGE_TABLE) {
771 u32 pgtbl_err = I915_READ(PGTBL_ER);
772 printk(KERN_ERR "page table error\n");
773 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
774 pgtbl_err);
775 I915_WRITE(PGTBL_ER, pgtbl_err);
776 (void)I915_READ(PGTBL_ER);
777 }
778 }
779
780 if (!IS_GEN2(dev)) {
781 if (eir & I915_ERROR_PAGE_TABLE) {
782 u32 pgtbl_err = I915_READ(PGTBL_ER);
783 printk(KERN_ERR "page table error\n");
784 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
785 pgtbl_err);
786 I915_WRITE(PGTBL_ER, pgtbl_err);
787 (void)I915_READ(PGTBL_ER);
788 }
789 }
790
791 if (eir & I915_ERROR_MEMORY_REFRESH) {
792 u32 pipea_stats = I915_READ(PIPEASTAT);
793 u32 pipeb_stats = I915_READ(PIPEBSTAT);
794
795 printk(KERN_ERR "memory refresh error\n");
796 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
797 pipea_stats);
798 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
799 pipeb_stats);
800 /* pipestat has already been acked */
801 }
802 if (eir & I915_ERROR_INSTRUCTION) {
803 printk(KERN_ERR "instruction error\n");
804 printk(KERN_ERR " INSTPM: 0x%08x\n",
805 I915_READ(INSTPM));
806 if (INTEL_INFO(dev)->gen < 4) {
807 u32 ipeir = I915_READ(IPEIR);
808
809 printk(KERN_ERR " IPEIR: 0x%08x\n",
810 I915_READ(IPEIR));
811 printk(KERN_ERR " IPEHR: 0x%08x\n",
812 I915_READ(IPEHR));
813 printk(KERN_ERR " INSTDONE: 0x%08x\n",
814 I915_READ(INSTDONE));
815 printk(KERN_ERR " ACTHD: 0x%08x\n",
816 I915_READ(ACTHD));
817 I915_WRITE(IPEIR, ipeir);
818 (void)I915_READ(IPEIR);
819 } else {
820 u32 ipeir = I915_READ(IPEIR_I965);
821
822 printk(KERN_ERR " IPEIR: 0x%08x\n",
823 I915_READ(IPEIR_I965));
824 printk(KERN_ERR " IPEHR: 0x%08x\n",
825 I915_READ(IPEHR_I965));
826 printk(KERN_ERR " INSTDONE: 0x%08x\n",
827 I915_READ(INSTDONE_I965));
828 printk(KERN_ERR " INSTPS: 0x%08x\n",
829 I915_READ(INSTPS));
830 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
831 I915_READ(INSTDONE1));
832 printk(KERN_ERR " ACTHD: 0x%08x\n",
833 I915_READ(ACTHD_I965));
834 I915_WRITE(IPEIR_I965, ipeir);
835 (void)I915_READ(IPEIR_I965);
836 }
837 }
838
839 I915_WRITE(EIR, eir);
840 (void)I915_READ(EIR);
841 eir = I915_READ(EIR);
842 if (eir) {
843 /*
844 * some errors might have become stuck,
845 * mask them.
846 */
847 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
848 I915_WRITE(EMR, I915_READ(EMR) | eir);
849 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
850 }
851 }
852
853 /**
854 * i915_handle_error - handle an error interrupt
855 * @dev: drm device
856 *
857 * Do some basic checking of regsiter state at error interrupt time and
858 * dump it to the syslog. Also call i915_capture_error_state() to make
859 * sure we get a record and make it available in debugfs. Fire a uevent
860 * so userspace knows something bad happened (should trigger collection
861 * of a ring dump etc.).
862 */
863 static void i915_handle_error(struct drm_device *dev, bool wedged)
864 {
865 struct drm_i915_private *dev_priv = dev->dev_private;
866
867 i915_capture_error_state(dev);
868 i915_report_and_clear_eir(dev);
869
870 if (wedged) {
871 atomic_set(&dev_priv->mm.wedged, 1);
872
873 /*
874 * Wakeup waiting processes so they don't hang
875 */
876 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
877 }
878
879 queue_work(dev_priv->wq, &dev_priv->error_work);
880 }
881
882 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
883 {
884 drm_i915_private_t *dev_priv = dev->dev_private;
885 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
886 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
887 struct drm_i915_gem_object *obj_priv;
888 struct intel_unpin_work *work;
889 unsigned long flags;
890 bool stall_detected;
891
892 /* Ignore early vblank irqs */
893 if (intel_crtc == NULL)
894 return;
895
896 spin_lock_irqsave(&dev->event_lock, flags);
897 work = intel_crtc->unpin_work;
898
899 if (work == NULL || work->pending || !work->enable_stall_check) {
900 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
901 spin_unlock_irqrestore(&dev->event_lock, flags);
902 return;
903 }
904
905 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
906 obj_priv = to_intel_bo(work->pending_flip_obj);
907 if (INTEL_INFO(dev)->gen >= 4) {
908 int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF;
909 stall_detected = I915_READ(dspsurf) == obj_priv->gtt_offset;
910 } else {
911 int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR;
912 stall_detected = I915_READ(dspaddr) == (obj_priv->gtt_offset +
913 crtc->y * crtc->fb->pitch +
914 crtc->x * crtc->fb->bits_per_pixel/8);
915 }
916
917 spin_unlock_irqrestore(&dev->event_lock, flags);
918
919 if (stall_detected) {
920 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
921 intel_prepare_page_flip(dev, intel_crtc->plane);
922 }
923 }
924
925 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
926 {
927 struct drm_device *dev = (struct drm_device *) arg;
928 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
929 struct drm_i915_master_private *master_priv;
930 u32 iir, new_iir;
931 u32 pipea_stats, pipeb_stats;
932 u32 vblank_status;
933 int vblank = 0;
934 unsigned long irqflags;
935 int irq_received;
936 int ret = IRQ_NONE;
937 struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
938
939 atomic_inc(&dev_priv->irq_received);
940
941 if (HAS_PCH_SPLIT(dev))
942 return ironlake_irq_handler(dev);
943
944 iir = I915_READ(IIR);
945
946 if (INTEL_INFO(dev)->gen >= 4)
947 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
948 else
949 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
950
951 for (;;) {
952 irq_received = iir != 0;
953
954 /* Can't rely on pipestat interrupt bit in iir as it might
955 * have been cleared after the pipestat interrupt was received.
956 * It doesn't set the bit in iir again, but it still produces
957 * interrupts (for non-MSI).
958 */
959 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
960 pipea_stats = I915_READ(PIPEASTAT);
961 pipeb_stats = I915_READ(PIPEBSTAT);
962
963 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
964 i915_handle_error(dev, false);
965
966 /*
967 * Clear the PIPE(A|B)STAT regs before the IIR
968 */
969 if (pipea_stats & 0x8000ffff) {
970 if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS)
971 DRM_DEBUG_DRIVER("pipe a underrun\n");
972 I915_WRITE(PIPEASTAT, pipea_stats);
973 irq_received = 1;
974 }
975
976 if (pipeb_stats & 0x8000ffff) {
977 if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS)
978 DRM_DEBUG_DRIVER("pipe b underrun\n");
979 I915_WRITE(PIPEBSTAT, pipeb_stats);
980 irq_received = 1;
981 }
982 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
983
984 if (!irq_received)
985 break;
986
987 ret = IRQ_HANDLED;
988
989 /* Consume port. Then clear IIR or we'll miss events */
990 if ((I915_HAS_HOTPLUG(dev)) &&
991 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
992 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
993
994 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
995 hotplug_status);
996 if (hotplug_status & dev_priv->hotplug_supported_mask)
997 queue_work(dev_priv->wq,
998 &dev_priv->hotplug_work);
999
1000 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1001 I915_READ(PORT_HOTPLUG_STAT);
1002 }
1003
1004 I915_WRITE(IIR, iir);
1005 new_iir = I915_READ(IIR); /* Flush posted writes */
1006
1007 if (dev->primary->master) {
1008 master_priv = dev->primary->master->driver_priv;
1009 if (master_priv->sarea_priv)
1010 master_priv->sarea_priv->last_dispatch =
1011 READ_BREADCRUMB(dev_priv);
1012 }
1013
1014 if (iir & I915_USER_INTERRUPT) {
1015 u32 seqno =
1016 render_ring->get_gem_seqno(dev, render_ring);
1017 render_ring->irq_gem_seqno = seqno;
1018 trace_i915_gem_request_complete(dev, seqno);
1019 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
1020 dev_priv->hangcheck_count = 0;
1021 mod_timer(&dev_priv->hangcheck_timer,
1022 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1023 }
1024
1025 if (HAS_BSD(dev) && (iir & I915_BSD_USER_INTERRUPT))
1026 DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
1027
1028 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
1029 intel_prepare_page_flip(dev, 0);
1030 if (dev_priv->flip_pending_is_done)
1031 intel_finish_page_flip_plane(dev, 0);
1032 }
1033
1034 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
1035 intel_prepare_page_flip(dev, 1);
1036 if (dev_priv->flip_pending_is_done)
1037 intel_finish_page_flip_plane(dev, 1);
1038 }
1039
1040 if (pipea_stats & vblank_status) {
1041 vblank++;
1042 drm_handle_vblank(dev, 0);
1043 if (!dev_priv->flip_pending_is_done) {
1044 i915_pageflip_stall_check(dev, 0);
1045 intel_finish_page_flip(dev, 0);
1046 }
1047 }
1048
1049 if (pipeb_stats & vblank_status) {
1050 vblank++;
1051 drm_handle_vblank(dev, 1);
1052 if (!dev_priv->flip_pending_is_done) {
1053 i915_pageflip_stall_check(dev, 1);
1054 intel_finish_page_flip(dev, 1);
1055 }
1056 }
1057
1058 if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1059 (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1060 (iir & I915_ASLE_INTERRUPT))
1061 intel_opregion_asle_intr(dev);
1062
1063 /* With MSI, interrupts are only generated when iir
1064 * transitions from zero to nonzero. If another bit got
1065 * set while we were handling the existing iir bits, then
1066 * we would never get another interrupt.
1067 *
1068 * This is fine on non-MSI as well, as if we hit this path
1069 * we avoid exiting the interrupt handler only to generate
1070 * another one.
1071 *
1072 * Note that for MSI this could cause a stray interrupt report
1073 * if an interrupt landed in the time between writing IIR and
1074 * the posting read. This should be rare enough to never
1075 * trigger the 99% of 100,000 interrupts test for disabling
1076 * stray interrupts.
1077 */
1078 iir = new_iir;
1079 }
1080
1081 return ret;
1082 }
1083
1084 static int i915_emit_irq(struct drm_device * dev)
1085 {
1086 drm_i915_private_t *dev_priv = dev->dev_private;
1087 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1088
1089 i915_kernel_lost_context(dev);
1090
1091 DRM_DEBUG_DRIVER("\n");
1092
1093 dev_priv->counter++;
1094 if (dev_priv->counter > 0x7FFFFFFFUL)
1095 dev_priv->counter = 1;
1096 if (master_priv->sarea_priv)
1097 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1098
1099 BEGIN_LP_RING(4);
1100 OUT_RING(MI_STORE_DWORD_INDEX);
1101 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1102 OUT_RING(dev_priv->counter);
1103 OUT_RING(MI_USER_INTERRUPT);
1104 ADVANCE_LP_RING();
1105
1106 return dev_priv->counter;
1107 }
1108
1109 void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
1110 {
1111 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1112 struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1113
1114 if (dev_priv->trace_irq_seqno == 0)
1115 render_ring->user_irq_get(dev, render_ring);
1116
1117 dev_priv->trace_irq_seqno = seqno;
1118 }
1119
1120 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1121 {
1122 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1123 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1124 int ret = 0;
1125 struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1126
1127 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1128 READ_BREADCRUMB(dev_priv));
1129
1130 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1131 if (master_priv->sarea_priv)
1132 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1133 return 0;
1134 }
1135
1136 if (master_priv->sarea_priv)
1137 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1138
1139 render_ring->user_irq_get(dev, render_ring);
1140 DRM_WAIT_ON(ret, dev_priv->render_ring.irq_queue, 3 * DRM_HZ,
1141 READ_BREADCRUMB(dev_priv) >= irq_nr);
1142 render_ring->user_irq_put(dev, render_ring);
1143
1144 if (ret == -EBUSY) {
1145 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1146 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1147 }
1148
1149 return ret;
1150 }
1151
1152 /* Needs the lock as it touches the ring.
1153 */
1154 int i915_irq_emit(struct drm_device *dev, void *data,
1155 struct drm_file *file_priv)
1156 {
1157 drm_i915_private_t *dev_priv = dev->dev_private;
1158 drm_i915_irq_emit_t *emit = data;
1159 int result;
1160
1161 if (!dev_priv || !dev_priv->render_ring.virtual_start) {
1162 DRM_ERROR("called with no initialization\n");
1163 return -EINVAL;
1164 }
1165
1166 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1167
1168 mutex_lock(&dev->struct_mutex);
1169 result = i915_emit_irq(dev);
1170 mutex_unlock(&dev->struct_mutex);
1171
1172 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1173 DRM_ERROR("copy_to_user\n");
1174 return -EFAULT;
1175 }
1176
1177 return 0;
1178 }
1179
1180 /* Doesn't need the hardware lock.
1181 */
1182 int i915_irq_wait(struct drm_device *dev, void *data,
1183 struct drm_file *file_priv)
1184 {
1185 drm_i915_private_t *dev_priv = dev->dev_private;
1186 drm_i915_irq_wait_t *irqwait = data;
1187
1188 if (!dev_priv) {
1189 DRM_ERROR("called with no initialization\n");
1190 return -EINVAL;
1191 }
1192
1193 return i915_wait_irq(dev, irqwait->irq_seq);
1194 }
1195
1196 /* Called from drm generic code, passed 'crtc' which
1197 * we use as a pipe index
1198 */
1199 int i915_enable_vblank(struct drm_device *dev, int pipe)
1200 {
1201 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1202 unsigned long irqflags;
1203
1204 if (!i915_pipe_enabled(dev, pipe))
1205 return -EINVAL;
1206
1207 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1208 if (HAS_PCH_SPLIT(dev))
1209 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1210 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1211 else if (INTEL_INFO(dev)->gen >= 4)
1212 i915_enable_pipestat(dev_priv, pipe,
1213 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1214 else
1215 i915_enable_pipestat(dev_priv, pipe,
1216 PIPE_VBLANK_INTERRUPT_ENABLE);
1217 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1218 return 0;
1219 }
1220
1221 /* Called from drm generic code, passed 'crtc' which
1222 * we use as a pipe index
1223 */
1224 void i915_disable_vblank(struct drm_device *dev, int pipe)
1225 {
1226 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1227 unsigned long irqflags;
1228
1229 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1230 if (HAS_PCH_SPLIT(dev))
1231 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1232 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1233 else
1234 i915_disable_pipestat(dev_priv, pipe,
1235 PIPE_VBLANK_INTERRUPT_ENABLE |
1236 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1237 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1238 }
1239
1240 void i915_enable_interrupt (struct drm_device *dev)
1241 {
1242 struct drm_i915_private *dev_priv = dev->dev_private;
1243
1244 if (!HAS_PCH_SPLIT(dev))
1245 intel_opregion_enable_asle(dev);
1246 dev_priv->irq_enabled = 1;
1247 }
1248
1249
1250 /* Set the vblank monitor pipe
1251 */
1252 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1253 struct drm_file *file_priv)
1254 {
1255 drm_i915_private_t *dev_priv = dev->dev_private;
1256
1257 if (!dev_priv) {
1258 DRM_ERROR("called with no initialization\n");
1259 return -EINVAL;
1260 }
1261
1262 return 0;
1263 }
1264
1265 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1266 struct drm_file *file_priv)
1267 {
1268 drm_i915_private_t *dev_priv = dev->dev_private;
1269 drm_i915_vblank_pipe_t *pipe = data;
1270
1271 if (!dev_priv) {
1272 DRM_ERROR("called with no initialization\n");
1273 return -EINVAL;
1274 }
1275
1276 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1277
1278 return 0;
1279 }
1280
1281 /**
1282 * Schedule buffer swap at given vertical blank.
1283 */
1284 int i915_vblank_swap(struct drm_device *dev, void *data,
1285 struct drm_file *file_priv)
1286 {
1287 /* The delayed swap mechanism was fundamentally racy, and has been
1288 * removed. The model was that the client requested a delayed flip/swap
1289 * from the kernel, then waited for vblank before continuing to perform
1290 * rendering. The problem was that the kernel might wake the client
1291 * up before it dispatched the vblank swap (since the lock has to be
1292 * held while touching the ringbuffer), in which case the client would
1293 * clear and start the next frame before the swap occurred, and
1294 * flicker would occur in addition to likely missing the vblank.
1295 *
1296 * In the absence of this ioctl, userland falls back to a correct path
1297 * of waiting for a vblank, then dispatching the swap on its own.
1298 * Context switching to userland and back is plenty fast enough for
1299 * meeting the requirements of vblank swapping.
1300 */
1301 return -EINVAL;
1302 }
1303
1304 static struct drm_i915_gem_request *
1305 i915_get_tail_request(struct drm_device *dev)
1306 {
1307 drm_i915_private_t *dev_priv = dev->dev_private;
1308 return list_entry(dev_priv->render_ring.request_list.prev,
1309 struct drm_i915_gem_request, list);
1310 }
1311
1312 /**
1313 * This is called when the chip hasn't reported back with completed
1314 * batchbuffers in a long time. The first time this is called we simply record
1315 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1316 * again, we assume the chip is wedged and try to fix it.
1317 */
1318 void i915_hangcheck_elapsed(unsigned long data)
1319 {
1320 struct drm_device *dev = (struct drm_device *)data;
1321 drm_i915_private_t *dev_priv = dev->dev_private;
1322 uint32_t acthd, instdone, instdone1;
1323
1324 if (INTEL_INFO(dev)->gen < 4) {
1325 acthd = I915_READ(ACTHD);
1326 instdone = I915_READ(INSTDONE);
1327 instdone1 = 0;
1328 } else {
1329 acthd = I915_READ(ACTHD_I965);
1330 instdone = I915_READ(INSTDONE_I965);
1331 instdone1 = I915_READ(INSTDONE1);
1332 }
1333
1334 /* If all work is done then ACTHD clearly hasn't advanced. */
1335 if (list_empty(&dev_priv->render_ring.request_list) ||
1336 i915_seqno_passed(i915_get_gem_seqno(dev,
1337 &dev_priv->render_ring),
1338 i915_get_tail_request(dev)->seqno)) {
1339 bool missed_wakeup = false;
1340
1341 dev_priv->hangcheck_count = 0;
1342
1343 /* Issue a wake-up to catch stuck h/w. */
1344 if (dev_priv->render_ring.waiting_gem_seqno &&
1345 waitqueue_active(&dev_priv->render_ring.irq_queue)) {
1346 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
1347 missed_wakeup = true;
1348 }
1349
1350 if (dev_priv->bsd_ring.waiting_gem_seqno &&
1351 waitqueue_active(&dev_priv->bsd_ring.irq_queue)) {
1352 DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
1353 missed_wakeup = true;
1354 }
1355
1356 if (missed_wakeup)
1357 DRM_ERROR("Hangcheck timer elapsed... GPU idle, missed IRQ.\n");
1358 return;
1359 }
1360
1361 if (dev_priv->last_acthd == acthd &&
1362 dev_priv->last_instdone == instdone &&
1363 dev_priv->last_instdone1 == instdone1) {
1364 if (dev_priv->hangcheck_count++ > 1) {
1365 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1366
1367 if (!IS_GEN2(dev)) {
1368 /* Is the chip hanging on a WAIT_FOR_EVENT?
1369 * If so we can simply poke the RB_WAIT bit
1370 * and break the hang. This should work on
1371 * all but the second generation chipsets.
1372 */
1373 u32 tmp = I915_READ(PRB0_CTL);
1374 if (tmp & RING_WAIT) {
1375 I915_WRITE(PRB0_CTL, tmp);
1376 POSTING_READ(PRB0_CTL);
1377 goto out;
1378 }
1379 }
1380
1381 i915_handle_error(dev, true);
1382 return;
1383 }
1384 } else {
1385 dev_priv->hangcheck_count = 0;
1386
1387 dev_priv->last_acthd = acthd;
1388 dev_priv->last_instdone = instdone;
1389 dev_priv->last_instdone1 = instdone1;
1390 }
1391
1392 out:
1393 /* Reset timer case chip hangs without another request being added */
1394 mod_timer(&dev_priv->hangcheck_timer,
1395 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1396 }
1397
1398 /* drm_dma.h hooks
1399 */
1400 static void ironlake_irq_preinstall(struct drm_device *dev)
1401 {
1402 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1403
1404 I915_WRITE(HWSTAM, 0xeffe);
1405
1406 /* XXX hotplug from PCH */
1407
1408 I915_WRITE(DEIMR, 0xffffffff);
1409 I915_WRITE(DEIER, 0x0);
1410 (void) I915_READ(DEIER);
1411
1412 /* and GT */
1413 I915_WRITE(GTIMR, 0xffffffff);
1414 I915_WRITE(GTIER, 0x0);
1415 (void) I915_READ(GTIER);
1416
1417 /* south display irq */
1418 I915_WRITE(SDEIMR, 0xffffffff);
1419 I915_WRITE(SDEIER, 0x0);
1420 (void) I915_READ(SDEIER);
1421 }
1422
1423 static int ironlake_irq_postinstall(struct drm_device *dev)
1424 {
1425 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1426 /* enable kind of interrupts always enabled */
1427 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1428 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1429 u32 render_mask = GT_PIPE_NOTIFY | GT_BSD_USER_INTERRUPT;
1430 u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1431 SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1432
1433 dev_priv->irq_mask_reg = ~display_mask;
1434 dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
1435
1436 /* should always can generate irq */
1437 I915_WRITE(DEIIR, I915_READ(DEIIR));
1438 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
1439 I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1440 (void) I915_READ(DEIER);
1441
1442 if (IS_GEN6(dev))
1443 render_mask = GT_PIPE_NOTIFY | GT_GEN6_BSD_USER_INTERRUPT;
1444
1445 dev_priv->gt_irq_mask_reg = ~render_mask;
1446 dev_priv->gt_irq_enable_reg = render_mask;
1447
1448 I915_WRITE(GTIIR, I915_READ(GTIIR));
1449 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1450 if (IS_GEN6(dev)) {
1451 I915_WRITE(GEN6_RENDER_IMR, ~GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT);
1452 I915_WRITE(GEN6_BSD_IMR, ~GEN6_BSD_IMR_USER_INTERRUPT);
1453 }
1454
1455 I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1456 (void) I915_READ(GTIER);
1457
1458 dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1459 dev_priv->pch_irq_enable_reg = hotplug_mask;
1460
1461 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1462 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
1463 I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
1464 (void) I915_READ(SDEIER);
1465
1466 if (IS_IRONLAKE_M(dev)) {
1467 /* Clear & enable PCU event interrupts */
1468 I915_WRITE(DEIIR, DE_PCU_EVENT);
1469 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1470 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1471 }
1472
1473 return 0;
1474 }
1475
1476 void i915_driver_irq_preinstall(struct drm_device * dev)
1477 {
1478 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1479
1480 atomic_set(&dev_priv->irq_received, 0);
1481
1482 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1483 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1484
1485 if (HAS_PCH_SPLIT(dev)) {
1486 ironlake_irq_preinstall(dev);
1487 return;
1488 }
1489
1490 if (I915_HAS_HOTPLUG(dev)) {
1491 I915_WRITE(PORT_HOTPLUG_EN, 0);
1492 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1493 }
1494
1495 I915_WRITE(HWSTAM, 0xeffe);
1496 I915_WRITE(PIPEASTAT, 0);
1497 I915_WRITE(PIPEBSTAT, 0);
1498 I915_WRITE(IMR, 0xffffffff);
1499 I915_WRITE(IER, 0x0);
1500 (void) I915_READ(IER);
1501 }
1502
1503 /*
1504 * Must be called after intel_modeset_init or hotplug interrupts won't be
1505 * enabled correctly.
1506 */
1507 int i915_driver_irq_postinstall(struct drm_device *dev)
1508 {
1509 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1510 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1511 u32 error_mask;
1512
1513 DRM_INIT_WAITQUEUE(&dev_priv->render_ring.irq_queue);
1514
1515 if (HAS_BSD(dev))
1516 DRM_INIT_WAITQUEUE(&dev_priv->bsd_ring.irq_queue);
1517
1518 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1519
1520 if (HAS_PCH_SPLIT(dev))
1521 return ironlake_irq_postinstall(dev);
1522
1523 /* Unmask the interrupts that we always want on. */
1524 dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
1525
1526 dev_priv->pipestat[0] = 0;
1527 dev_priv->pipestat[1] = 0;
1528
1529 if (I915_HAS_HOTPLUG(dev)) {
1530 /* Enable in IER... */
1531 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1532 /* and unmask in IMR */
1533 dev_priv->irq_mask_reg &= ~I915_DISPLAY_PORT_INTERRUPT;
1534 }
1535
1536 /*
1537 * Enable some error detection, note the instruction error mask
1538 * bit is reserved, so we leave it masked.
1539 */
1540 if (IS_G4X(dev)) {
1541 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1542 GM45_ERROR_MEM_PRIV |
1543 GM45_ERROR_CP_PRIV |
1544 I915_ERROR_MEMORY_REFRESH);
1545 } else {
1546 error_mask = ~(I915_ERROR_PAGE_TABLE |
1547 I915_ERROR_MEMORY_REFRESH);
1548 }
1549 I915_WRITE(EMR, error_mask);
1550
1551 I915_WRITE(IMR, dev_priv->irq_mask_reg);
1552 I915_WRITE(IER, enable_mask);
1553 (void) I915_READ(IER);
1554
1555 if (I915_HAS_HOTPLUG(dev)) {
1556 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1557
1558 /* Note HDMI and DP share bits */
1559 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1560 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1561 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1562 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1563 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1564 hotplug_en |= HDMID_HOTPLUG_INT_EN;
1565 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1566 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1567 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1568 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1569 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1570 hotplug_en |= CRT_HOTPLUG_INT_EN;
1571
1572 /* Programming the CRT detection parameters tends
1573 to generate a spurious hotplug event about three
1574 seconds later. So just do it once.
1575 */
1576 if (IS_G4X(dev))
1577 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
1578 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1579 }
1580
1581 /* Ignore TV since it's buggy */
1582
1583 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1584 }
1585
1586 intel_opregion_enable_asle(dev);
1587
1588 return 0;
1589 }
1590
1591 static void ironlake_irq_uninstall(struct drm_device *dev)
1592 {
1593 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1594 I915_WRITE(HWSTAM, 0xffffffff);
1595
1596 I915_WRITE(DEIMR, 0xffffffff);
1597 I915_WRITE(DEIER, 0x0);
1598 I915_WRITE(DEIIR, I915_READ(DEIIR));
1599
1600 I915_WRITE(GTIMR, 0xffffffff);
1601 I915_WRITE(GTIER, 0x0);
1602 I915_WRITE(GTIIR, I915_READ(GTIIR));
1603 }
1604
1605 void i915_driver_irq_uninstall(struct drm_device * dev)
1606 {
1607 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1608
1609 if (!dev_priv)
1610 return;
1611
1612 dev_priv->vblank_pipe = 0;
1613
1614 if (HAS_PCH_SPLIT(dev)) {
1615 ironlake_irq_uninstall(dev);
1616 return;
1617 }
1618
1619 if (I915_HAS_HOTPLUG(dev)) {
1620 I915_WRITE(PORT_HOTPLUG_EN, 0);
1621 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1622 }
1623
1624 I915_WRITE(HWSTAM, 0xffffffff);
1625 I915_WRITE(PIPEASTAT, 0);
1626 I915_WRITE(PIPEBSTAT, 0);
1627 I915_WRITE(IMR, 0xffffffff);
1628 I915_WRITE(IER, 0x0);
1629
1630 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1631 I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1632 I915_WRITE(IIR, I915_READ(IIR));
1633 }
Linux kernel - Deliverables
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