1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
34 #include <drm/i915_drm.h>
36 #include "i915_trace.h"
37 #include "intel_drv.h"
39 static const u32 hpd_ibx
[] = {
40 [HPD_CRT
] = SDE_CRT_HOTPLUG
,
41 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG
,
42 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG
,
43 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG
,
44 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG
47 static const u32 hpd_cpt
[] = {
48 [HPD_CRT
] = SDE_CRT_HOTPLUG_CPT
,
49 [HPD_SDVO_B
] = SDE_SDVOB_HOTPLUG_CPT
,
50 [HPD_PORT_B
] = SDE_PORTB_HOTPLUG_CPT
,
51 [HPD_PORT_C
] = SDE_PORTC_HOTPLUG_CPT
,
52 [HPD_PORT_D
] = SDE_PORTD_HOTPLUG_CPT
55 static const u32 hpd_mask_i915
[] = {
56 [HPD_CRT
] = CRT_HOTPLUG_INT_EN
,
57 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_EN
,
58 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_EN
,
59 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_EN
,
60 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_EN
,
61 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_EN
64 static const u32 hpd_status_gen4
[] = {
65 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
66 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_G4X
,
67 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_G4X
,
68 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
69 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
70 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
73 static const u32 hpd_status_i915
[] = { /* i915 and valleyview are the same */
74 [HPD_CRT
] = CRT_HOTPLUG_INT_STATUS
,
75 [HPD_SDVO_B
] = SDVOB_HOTPLUG_INT_STATUS_I915
,
76 [HPD_SDVO_C
] = SDVOC_HOTPLUG_INT_STATUS_I915
,
77 [HPD_PORT_B
] = PORTB_HOTPLUG_INT_STATUS
,
78 [HPD_PORT_C
] = PORTC_HOTPLUG_INT_STATUS
,
79 [HPD_PORT_D
] = PORTD_HOTPLUG_INT_STATUS
82 /* For display hotplug interrupt */
84 ironlake_enable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
86 assert_spin_locked(&dev_priv
->irq_lock
);
88 if ((dev_priv
->irq_mask
& mask
) != 0) {
89 dev_priv
->irq_mask
&= ~mask
;
90 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
96 ironlake_disable_display_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
98 assert_spin_locked(&dev_priv
->irq_lock
);
100 if ((dev_priv
->irq_mask
& mask
) != mask
) {
101 dev_priv
->irq_mask
|= mask
;
102 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
107 static bool ivb_can_enable_err_int(struct drm_device
*dev
)
109 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
110 struct intel_crtc
*crtc
;
113 assert_spin_locked(&dev_priv
->irq_lock
);
115 for_each_pipe(pipe
) {
116 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
118 if (crtc
->cpu_fifo_underrun_disabled
)
125 static bool cpt_can_enable_serr_int(struct drm_device
*dev
)
127 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
129 struct intel_crtc
*crtc
;
131 assert_spin_locked(&dev_priv
->irq_lock
);
133 for_each_pipe(pipe
) {
134 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
136 if (crtc
->pch_fifo_underrun_disabled
)
143 static void ironlake_set_fifo_underrun_reporting(struct drm_device
*dev
,
144 enum pipe pipe
, bool enable
)
146 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
147 uint32_t bit
= (pipe
== PIPE_A
) ? DE_PIPEA_FIFO_UNDERRUN
:
148 DE_PIPEB_FIFO_UNDERRUN
;
151 ironlake_enable_display_irq(dev_priv
, bit
);
153 ironlake_disable_display_irq(dev_priv
, bit
);
156 static void ivybridge_set_fifo_underrun_reporting(struct drm_device
*dev
,
157 enum pipe pipe
, bool enable
)
159 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
161 I915_WRITE(GEN7_ERR_INT
, ERR_INT_FIFO_UNDERRUN(pipe
));
163 if (!ivb_can_enable_err_int(dev
))
166 ironlake_enable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
168 bool was_enabled
= !(I915_READ(DEIMR
) & DE_ERR_INT_IVB
);
170 /* Change the state _after_ we've read out the current one. */
171 ironlake_disable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
174 (I915_READ(GEN7_ERR_INT
) & ERR_INT_FIFO_UNDERRUN(pipe
))) {
175 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
182 * ibx_display_interrupt_update - update SDEIMR
183 * @dev_priv: driver private
184 * @interrupt_mask: mask of interrupt bits to update
185 * @enabled_irq_mask: mask of interrupt bits to enable
187 static void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
188 uint32_t interrupt_mask
,
189 uint32_t enabled_irq_mask
)
191 uint32_t sdeimr
= I915_READ(SDEIMR
);
192 sdeimr
&= ~interrupt_mask
;
193 sdeimr
|= (~enabled_irq_mask
& interrupt_mask
);
195 assert_spin_locked(&dev_priv
->irq_lock
);
197 I915_WRITE(SDEIMR
, sdeimr
);
198 POSTING_READ(SDEIMR
);
200 #define ibx_enable_display_interrupt(dev_priv, bits) \
201 ibx_display_interrupt_update((dev_priv), (bits), (bits))
202 #define ibx_disable_display_interrupt(dev_priv, bits) \
203 ibx_display_interrupt_update((dev_priv), (bits), 0)
205 static void ibx_set_fifo_underrun_reporting(struct drm_device
*dev
,
206 enum transcoder pch_transcoder
,
209 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
210 uint32_t bit
= (pch_transcoder
== TRANSCODER_A
) ?
211 SDE_TRANSA_FIFO_UNDER
: SDE_TRANSB_FIFO_UNDER
;
214 ibx_enable_display_interrupt(dev_priv
, bit
);
216 ibx_disable_display_interrupt(dev_priv
, bit
);
219 static void cpt_set_fifo_underrun_reporting(struct drm_device
*dev
,
220 enum transcoder pch_transcoder
,
223 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
227 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
));
229 if (!cpt_can_enable_serr_int(dev
))
232 ibx_enable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
234 uint32_t tmp
= I915_READ(SERR_INT
);
235 bool was_enabled
= !(I915_READ(SDEIMR
) & SDE_ERROR_CPT
);
237 /* Change the state _after_ we've read out the current one. */
238 ibx_disable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
241 (tmp
& SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
))) {
242 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
243 transcoder_name(pch_transcoder
));
249 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
252 * @enable: true if we want to report FIFO underrun errors, false otherwise
254 * This function makes us disable or enable CPU fifo underruns for a specific
255 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
256 * reporting for one pipe may also disable all the other CPU error interruts for
257 * the other pipes, due to the fact that there's just one interrupt mask/enable
258 * bit for all the pipes.
260 * Returns the previous state of underrun reporting.
262 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device
*dev
,
263 enum pipe pipe
, bool enable
)
265 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
266 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
267 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
271 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
273 ret
= !intel_crtc
->cpu_fifo_underrun_disabled
;
278 intel_crtc
->cpu_fifo_underrun_disabled
= !enable
;
280 if (IS_GEN5(dev
) || IS_GEN6(dev
))
281 ironlake_set_fifo_underrun_reporting(dev
, pipe
, enable
);
282 else if (IS_GEN7(dev
))
283 ivybridge_set_fifo_underrun_reporting(dev
, pipe
, enable
);
286 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
291 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
293 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
294 * @enable: true if we want to report FIFO underrun errors, false otherwise
296 * This function makes us disable or enable PCH fifo underruns for a specific
297 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
298 * underrun reporting for one transcoder may also disable all the other PCH
299 * error interruts for the other transcoders, due to the fact that there's just
300 * one interrupt mask/enable bit for all the transcoders.
302 * Returns the previous state of underrun reporting.
304 bool intel_set_pch_fifo_underrun_reporting(struct drm_device
*dev
,
305 enum transcoder pch_transcoder
,
308 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
309 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pch_transcoder
];
310 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
315 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
316 * has only one pch transcoder A that all pipes can use. To avoid racy
317 * pch transcoder -> pipe lookups from interrupt code simply store the
318 * underrun statistics in crtc A. Since we never expose this anywhere
319 * nor use it outside of the fifo underrun code here using the "wrong"
320 * crtc on LPT won't cause issues.
323 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
325 ret
= !intel_crtc
->pch_fifo_underrun_disabled
;
330 intel_crtc
->pch_fifo_underrun_disabled
= !enable
;
332 if (HAS_PCH_IBX(dev
))
333 ibx_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
335 cpt_set_fifo_underrun_reporting(dev
, pch_transcoder
, enable
);
338 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
344 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
346 u32 reg
= PIPESTAT(pipe
);
347 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
349 assert_spin_locked(&dev_priv
->irq_lock
);
351 if ((pipestat
& mask
) == mask
)
354 /* Enable the interrupt, clear any pending status */
355 pipestat
|= mask
| (mask
>> 16);
356 I915_WRITE(reg
, pipestat
);
361 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
)
363 u32 reg
= PIPESTAT(pipe
);
364 u32 pipestat
= I915_READ(reg
) & 0x7fff0000;
366 assert_spin_locked(&dev_priv
->irq_lock
);
368 if ((pipestat
& mask
) == 0)
372 I915_WRITE(reg
, pipestat
);
377 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
379 static void i915_enable_asle_pipestat(struct drm_device
*dev
)
381 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
382 unsigned long irqflags
;
384 if (!dev_priv
->opregion
.asle
|| !IS_MOBILE(dev
))
387 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
389 i915_enable_pipestat(dev_priv
, 1, PIPE_LEGACY_BLC_EVENT_ENABLE
);
390 if (INTEL_INFO(dev
)->gen
>= 4)
391 i915_enable_pipestat(dev_priv
, 0, PIPE_LEGACY_BLC_EVENT_ENABLE
);
393 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
397 * i915_pipe_enabled - check if a pipe is enabled
399 * @pipe: pipe to check
401 * Reading certain registers when the pipe is disabled can hang the chip.
402 * Use this routine to make sure the PLL is running and the pipe is active
403 * before reading such registers if unsure.
406 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
408 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
410 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
411 /* Locking is horribly broken here, but whatever. */
412 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
413 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
415 return intel_crtc
->active
;
417 return I915_READ(PIPECONF(pipe
)) & PIPECONF_ENABLE
;
421 /* Called from drm generic code, passed a 'crtc', which
422 * we use as a pipe index
424 static u32
i915_get_vblank_counter(struct drm_device
*dev
, int pipe
)
426 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
427 unsigned long high_frame
;
428 unsigned long low_frame
;
429 u32 high1
, high2
, low
;
431 if (!i915_pipe_enabled(dev
, pipe
)) {
432 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
433 "pipe %c\n", pipe_name(pipe
));
437 high_frame
= PIPEFRAME(pipe
);
438 low_frame
= PIPEFRAMEPIXEL(pipe
);
441 * High & low register fields aren't synchronized, so make sure
442 * we get a low value that's stable across two reads of the high
446 high1
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
447 low
= I915_READ(low_frame
) & PIPE_FRAME_LOW_MASK
;
448 high2
= I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
;
449 } while (high1
!= high2
);
451 high1
>>= PIPE_FRAME_HIGH_SHIFT
;
452 low
>>= PIPE_FRAME_LOW_SHIFT
;
453 return (high1
<< 8) | low
;
456 static u32
gm45_get_vblank_counter(struct drm_device
*dev
, int pipe
)
458 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
459 int reg
= PIPE_FRMCOUNT_GM45(pipe
);
461 if (!i915_pipe_enabled(dev
, pipe
)) {
462 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
463 "pipe %c\n", pipe_name(pipe
));
467 return I915_READ(reg
);
470 static int i915_get_crtc_scanoutpos(struct drm_device
*dev
, int pipe
,
471 int *vpos
, int *hpos
)
473 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
474 u32 vbl
= 0, position
= 0;
475 int vbl_start
, vbl_end
, htotal
, vtotal
;
478 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
481 if (!i915_pipe_enabled(dev
, pipe
)) {
482 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
483 "pipe %c\n", pipe_name(pipe
));
488 vtotal
= 1 + ((I915_READ(VTOTAL(cpu_transcoder
)) >> 16) & 0x1fff);
490 if (INTEL_INFO(dev
)->gen
>= 4) {
491 /* No obvious pixelcount register. Only query vertical
492 * scanout position from Display scan line register.
494 position
= I915_READ(PIPEDSL(pipe
));
496 /* Decode into vertical scanout position. Don't have
497 * horizontal scanout position.
499 *vpos
= position
& 0x1fff;
502 /* Have access to pixelcount since start of frame.
503 * We can split this into vertical and horizontal
506 position
= (I915_READ(PIPEFRAMEPIXEL(pipe
)) & PIPE_PIXEL_MASK
) >> PIPE_PIXEL_SHIFT
;
508 htotal
= 1 + ((I915_READ(HTOTAL(cpu_transcoder
)) >> 16) & 0x1fff);
509 *vpos
= position
/ htotal
;
510 *hpos
= position
- (*vpos
* htotal
);
513 /* Query vblank area. */
514 vbl
= I915_READ(VBLANK(cpu_transcoder
));
516 /* Test position against vblank region. */
517 vbl_start
= vbl
& 0x1fff;
518 vbl_end
= (vbl
>> 16) & 0x1fff;
520 if ((*vpos
< vbl_start
) || (*vpos
> vbl_end
))
523 /* Inside "upper part" of vblank area? Apply corrective offset: */
524 if (in_vbl
&& (*vpos
>= vbl_start
))
525 *vpos
= *vpos
- vtotal
;
527 /* Readouts valid? */
529 ret
|= DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
;
533 ret
|= DRM_SCANOUTPOS_INVBL
;
538 static int i915_get_vblank_timestamp(struct drm_device
*dev
, int pipe
,
540 struct timeval
*vblank_time
,
543 struct drm_crtc
*crtc
;
545 if (pipe
< 0 || pipe
>= INTEL_INFO(dev
)->num_pipes
) {
546 DRM_ERROR("Invalid crtc %d\n", pipe
);
550 /* Get drm_crtc to timestamp: */
551 crtc
= intel_get_crtc_for_pipe(dev
, pipe
);
553 DRM_ERROR("Invalid crtc %d\n", pipe
);
557 if (!crtc
->enabled
) {
558 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
562 /* Helper routine in DRM core does all the work: */
563 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
568 static int intel_hpd_irq_event(struct drm_device
*dev
, struct drm_connector
*connector
)
570 enum drm_connector_status old_status
;
572 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
573 old_status
= connector
->status
;
575 connector
->status
= connector
->funcs
->detect(connector
, false);
576 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
578 drm_get_connector_name(connector
),
579 old_status
, connector
->status
);
580 return (old_status
!= connector
->status
);
584 * Handle hotplug events outside the interrupt handler proper.
586 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
588 static void i915_hotplug_work_func(struct work_struct
*work
)
590 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
592 struct drm_device
*dev
= dev_priv
->dev
;
593 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
594 struct intel_connector
*intel_connector
;
595 struct intel_encoder
*intel_encoder
;
596 struct drm_connector
*connector
;
597 unsigned long irqflags
;
598 bool hpd_disabled
= false;
599 bool changed
= false;
602 /* HPD irq before everything is fully set up. */
603 if (!dev_priv
->enable_hotplug_processing
)
606 mutex_lock(&mode_config
->mutex
);
607 DRM_DEBUG_KMS("running encoder hotplug functions\n");
609 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
611 hpd_event_bits
= dev_priv
->hpd_event_bits
;
612 dev_priv
->hpd_event_bits
= 0;
613 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
614 intel_connector
= to_intel_connector(connector
);
615 intel_encoder
= intel_connector
->encoder
;
616 if (intel_encoder
->hpd_pin
> HPD_NONE
&&
617 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_MARK_DISABLED
&&
618 connector
->polled
== DRM_CONNECTOR_POLL_HPD
) {
619 DRM_INFO("HPD interrupt storm detected on connector %s: "
620 "switching from hotplug detection to polling\n",
621 drm_get_connector_name(connector
));
622 dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
= HPD_DISABLED
;
623 connector
->polled
= DRM_CONNECTOR_POLL_CONNECT
624 | DRM_CONNECTOR_POLL_DISCONNECT
;
627 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
628 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
629 drm_get_connector_name(connector
), intel_encoder
->hpd_pin
);
632 /* if there were no outputs to poll, poll was disabled,
633 * therefore make sure it's enabled when disabling HPD on
636 drm_kms_helper_poll_enable(dev
);
637 mod_timer(&dev_priv
->hotplug_reenable_timer
,
638 jiffies
+ msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY
));
641 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
643 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
644 intel_connector
= to_intel_connector(connector
);
645 intel_encoder
= intel_connector
->encoder
;
646 if (hpd_event_bits
& (1 << intel_encoder
->hpd_pin
)) {
647 if (intel_encoder
->hot_plug
)
648 intel_encoder
->hot_plug(intel_encoder
);
649 if (intel_hpd_irq_event(dev
, connector
))
653 mutex_unlock(&mode_config
->mutex
);
656 drm_kms_helper_hotplug_event(dev
);
659 static void ironlake_rps_change_irq_handler(struct drm_device
*dev
)
661 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
662 u32 busy_up
, busy_down
, max_avg
, min_avg
;
665 spin_lock(&mchdev_lock
);
667 I915_WRITE16(MEMINTRSTS
, I915_READ(MEMINTRSTS
));
669 new_delay
= dev_priv
->ips
.cur_delay
;
671 I915_WRITE16(MEMINTRSTS
, MEMINT_EVAL_CHG
);
672 busy_up
= I915_READ(RCPREVBSYTUPAVG
);
673 busy_down
= I915_READ(RCPREVBSYTDNAVG
);
674 max_avg
= I915_READ(RCBMAXAVG
);
675 min_avg
= I915_READ(RCBMINAVG
);
677 /* Handle RCS change request from hw */
678 if (busy_up
> max_avg
) {
679 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.max_delay
)
680 new_delay
= dev_priv
->ips
.cur_delay
- 1;
681 if (new_delay
< dev_priv
->ips
.max_delay
)
682 new_delay
= dev_priv
->ips
.max_delay
;
683 } else if (busy_down
< min_avg
) {
684 if (dev_priv
->ips
.cur_delay
!= dev_priv
->ips
.min_delay
)
685 new_delay
= dev_priv
->ips
.cur_delay
+ 1;
686 if (new_delay
> dev_priv
->ips
.min_delay
)
687 new_delay
= dev_priv
->ips
.min_delay
;
690 if (ironlake_set_drps(dev
, new_delay
))
691 dev_priv
->ips
.cur_delay
= new_delay
;
693 spin_unlock(&mchdev_lock
);
698 static void notify_ring(struct drm_device
*dev
,
699 struct intel_ring_buffer
*ring
)
701 if (ring
->obj
== NULL
)
704 trace_i915_gem_request_complete(ring
, ring
->get_seqno(ring
, false));
706 wake_up_all(&ring
->irq_queue
);
707 i915_queue_hangcheck(dev
);
710 static void gen6_pm_rps_work(struct work_struct
*work
)
712 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
717 spin_lock_irq(&dev_priv
->irq_lock
);
718 pm_iir
= dev_priv
->rps
.pm_iir
;
719 dev_priv
->rps
.pm_iir
= 0;
720 pm_imr
= I915_READ(GEN6_PMIMR
);
721 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
722 I915_WRITE(GEN6_PMIMR
, pm_imr
& ~GEN6_PM_RPS_EVENTS
);
723 spin_unlock_irq(&dev_priv
->irq_lock
);
725 if ((pm_iir
& GEN6_PM_RPS_EVENTS
) == 0)
728 mutex_lock(&dev_priv
->rps
.hw_lock
);
730 if (pm_iir
& GEN6_PM_RP_UP_THRESHOLD
) {
731 new_delay
= dev_priv
->rps
.cur_delay
+ 1;
734 * For better performance, jump directly
735 * to RPe if we're below it.
737 if (IS_VALLEYVIEW(dev_priv
->dev
) &&
738 dev_priv
->rps
.cur_delay
< dev_priv
->rps
.rpe_delay
)
739 new_delay
= dev_priv
->rps
.rpe_delay
;
741 new_delay
= dev_priv
->rps
.cur_delay
- 1;
743 /* sysfs frequency interfaces may have snuck in while servicing the
746 if (new_delay
>= dev_priv
->rps
.min_delay
&&
747 new_delay
<= dev_priv
->rps
.max_delay
) {
748 if (IS_VALLEYVIEW(dev_priv
->dev
))
749 valleyview_set_rps(dev_priv
->dev
, new_delay
);
751 gen6_set_rps(dev_priv
->dev
, new_delay
);
754 if (IS_VALLEYVIEW(dev_priv
->dev
)) {
756 * On VLV, when we enter RC6 we may not be at the minimum
757 * voltage level, so arm a timer to check. It should only
758 * fire when there's activity or once after we've entered
759 * RC6, and then won't be re-armed until the next RPS interrupt.
761 mod_delayed_work(dev_priv
->wq
, &dev_priv
->rps
.vlv_work
,
762 msecs_to_jiffies(100));
765 mutex_unlock(&dev_priv
->rps
.hw_lock
);
770 * ivybridge_parity_work - Workqueue called when a parity error interrupt
772 * @work: workqueue struct
774 * Doesn't actually do anything except notify userspace. As a consequence of
775 * this event, userspace should try to remap the bad rows since statistically
776 * it is likely the same row is more likely to go bad again.
778 static void ivybridge_parity_work(struct work_struct
*work
)
780 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
781 l3_parity
.error_work
);
782 u32 error_status
, row
, bank
, subbank
;
783 char *parity_event
[5];
787 /* We must turn off DOP level clock gating to access the L3 registers.
788 * In order to prevent a get/put style interface, acquire struct mutex
789 * any time we access those registers.
791 mutex_lock(&dev_priv
->dev
->struct_mutex
);
793 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
794 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
795 POSTING_READ(GEN7_MISCCPCTL
);
797 error_status
= I915_READ(GEN7_L3CDERRST1
);
798 row
= GEN7_PARITY_ERROR_ROW(error_status
);
799 bank
= GEN7_PARITY_ERROR_BANK(error_status
);
800 subbank
= GEN7_PARITY_ERROR_SUBBANK(error_status
);
802 I915_WRITE(GEN7_L3CDERRST1
, GEN7_PARITY_ERROR_VALID
|
803 GEN7_L3CDERRST1_ENABLE
);
804 POSTING_READ(GEN7_L3CDERRST1
);
806 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
808 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
809 dev_priv
->gt_irq_mask
&= ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
810 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
811 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
813 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
815 parity_event
[0] = "L3_PARITY_ERROR=1";
816 parity_event
[1] = kasprintf(GFP_KERNEL
, "ROW=%d", row
);
817 parity_event
[2] = kasprintf(GFP_KERNEL
, "BANK=%d", bank
);
818 parity_event
[3] = kasprintf(GFP_KERNEL
, "SUBBANK=%d", subbank
);
819 parity_event
[4] = NULL
;
821 kobject_uevent_env(&dev_priv
->dev
->primary
->kdev
.kobj
,
822 KOBJ_CHANGE
, parity_event
);
824 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
827 kfree(parity_event
[3]);
828 kfree(parity_event
[2]);
829 kfree(parity_event
[1]);
832 static void ivybridge_parity_error_irq_handler(struct drm_device
*dev
)
834 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
836 if (!HAS_L3_GPU_CACHE(dev
))
839 spin_lock(&dev_priv
->irq_lock
);
840 dev_priv
->gt_irq_mask
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
841 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
842 spin_unlock(&dev_priv
->irq_lock
);
844 queue_work(dev_priv
->wq
, &dev_priv
->l3_parity
.error_work
);
847 static void snb_gt_irq_handler(struct drm_device
*dev
,
848 struct drm_i915_private
*dev_priv
,
853 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
854 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
855 if (gt_iir
& GT_BSD_USER_INTERRUPT
)
856 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
857 if (gt_iir
& GT_BLT_USER_INTERRUPT
)
858 notify_ring(dev
, &dev_priv
->ring
[BCS
]);
860 if (gt_iir
& (GT_BLT_CS_ERROR_INTERRUPT
|
861 GT_BSD_CS_ERROR_INTERRUPT
|
862 GT_RENDER_CS_MASTER_ERROR_INTERRUPT
)) {
863 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir
);
864 i915_handle_error(dev
, false);
867 if (gt_iir
& GT_RENDER_L3_PARITY_ERROR_INTERRUPT
)
868 ivybridge_parity_error_irq_handler(dev
);
871 /* Legacy way of handling PM interrupts */
872 static void gen6_rps_irq_handler(struct drm_i915_private
*dev_priv
,
876 * IIR bits should never already be set because IMR should
877 * prevent an interrupt from being shown in IIR. The warning
878 * displays a case where we've unsafely cleared
879 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
880 * type is not a problem, it displays a problem in the logic.
882 * The mask bit in IMR is cleared by dev_priv->rps.work.
885 spin_lock(&dev_priv
->irq_lock
);
886 dev_priv
->rps
.pm_iir
|= pm_iir
;
887 I915_WRITE(GEN6_PMIMR
, dev_priv
->rps
.pm_iir
);
888 POSTING_READ(GEN6_PMIMR
);
889 spin_unlock(&dev_priv
->irq_lock
);
891 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
894 #define HPD_STORM_DETECT_PERIOD 1000
895 #define HPD_STORM_THRESHOLD 5
897 static inline void intel_hpd_irq_handler(struct drm_device
*dev
,
901 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
903 bool storm_detected
= false;
905 if (!hotplug_trigger
)
908 spin_lock(&dev_priv
->irq_lock
);
909 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
911 if (!(hpd
[i
] & hotplug_trigger
) ||
912 dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_ENABLED
)
915 dev_priv
->hpd_event_bits
|= (1 << i
);
916 if (!time_in_range(jiffies
, dev_priv
->hpd_stats
[i
].hpd_last_jiffies
,
917 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
918 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD
))) {
919 dev_priv
->hpd_stats
[i
].hpd_last_jiffies
= jiffies
;
920 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
921 } else if (dev_priv
->hpd_stats
[i
].hpd_cnt
> HPD_STORM_THRESHOLD
) {
922 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_MARK_DISABLED
;
923 dev_priv
->hpd_event_bits
&= ~(1 << i
);
924 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i
);
925 storm_detected
= true;
927 dev_priv
->hpd_stats
[i
].hpd_cnt
++;
932 dev_priv
->display
.hpd_irq_setup(dev
);
933 spin_unlock(&dev_priv
->irq_lock
);
935 queue_work(dev_priv
->wq
,
936 &dev_priv
->hotplug_work
);
939 static void gmbus_irq_handler(struct drm_device
*dev
)
941 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
943 wake_up_all(&dev_priv
->gmbus_wait_queue
);
946 static void dp_aux_irq_handler(struct drm_device
*dev
)
948 struct drm_i915_private
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
950 wake_up_all(&dev_priv
->gmbus_wait_queue
);
953 /* Unlike gen6_rps_irq_handler() from which this function is originally derived,
954 * we must be able to deal with other PM interrupts. This is complicated because
955 * of the way in which we use the masks to defer the RPS work (which for
956 * posterity is necessary because of forcewake).
958 static void hsw_pm_irq_handler(struct drm_i915_private
*dev_priv
,
961 if (pm_iir
& GEN6_PM_RPS_EVENTS
) {
962 spin_lock(&dev_priv
->irq_lock
);
963 dev_priv
->rps
.pm_iir
|= pm_iir
& GEN6_PM_RPS_EVENTS
;
964 I915_WRITE(GEN6_PMIMR
, dev_priv
->rps
.pm_iir
);
965 /* never want to mask useful interrupts. (also posting read) */
966 WARN_ON(I915_READ_NOTRACE(GEN6_PMIMR
) & ~GEN6_PM_RPS_EVENTS
);
967 spin_unlock(&dev_priv
->irq_lock
);
969 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
972 if (pm_iir
& PM_VEBOX_USER_INTERRUPT
)
973 notify_ring(dev_priv
->dev
, &dev_priv
->ring
[VECS
]);
975 if (pm_iir
& PM_VEBOX_CS_ERROR_INTERRUPT
) {
976 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir
);
977 i915_handle_error(dev_priv
->dev
, false);
981 static irqreturn_t
valleyview_irq_handler(int irq
, void *arg
)
983 struct drm_device
*dev
= (struct drm_device
*) arg
;
984 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
985 u32 iir
, gt_iir
, pm_iir
;
986 irqreturn_t ret
= IRQ_NONE
;
987 unsigned long irqflags
;
989 u32 pipe_stats
[I915_MAX_PIPES
];
991 atomic_inc(&dev_priv
->irq_received
);
994 iir
= I915_READ(VLV_IIR
);
995 gt_iir
= I915_READ(GTIIR
);
996 pm_iir
= I915_READ(GEN6_PMIIR
);
998 if (gt_iir
== 0 && pm_iir
== 0 && iir
== 0)
1003 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1005 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1006 for_each_pipe(pipe
) {
1007 int reg
= PIPESTAT(pipe
);
1008 pipe_stats
[pipe
] = I915_READ(reg
);
1011 * Clear the PIPE*STAT regs before the IIR
1013 if (pipe_stats
[pipe
] & 0x8000ffff) {
1014 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
1015 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1017 I915_WRITE(reg
, pipe_stats
[pipe
]);
1020 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1022 for_each_pipe(pipe
) {
1023 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
)
1024 drm_handle_vblank(dev
, pipe
);
1026 if (pipe_stats
[pipe
] & PLANE_FLIPDONE_INT_STATUS_VLV
) {
1027 intel_prepare_page_flip(dev
, pipe
);
1028 intel_finish_page_flip(dev
, pipe
);
1032 /* Consume port. Then clear IIR or we'll miss events */
1033 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
1034 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
1035 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
1037 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1040 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
1042 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
1043 I915_READ(PORT_HOTPLUG_STAT
);
1046 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
1047 gmbus_irq_handler(dev
);
1049 if (pm_iir
& GEN6_PM_RPS_EVENTS
)
1050 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1052 I915_WRITE(GTIIR
, gt_iir
);
1053 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1054 I915_WRITE(VLV_IIR
, iir
);
1061 static void ibx_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1063 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1065 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK
;
1067 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_ibx
);
1069 if (pch_iir
& SDE_AUDIO_POWER_MASK
) {
1070 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK
) >>
1071 SDE_AUDIO_POWER_SHIFT
);
1072 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1076 if (pch_iir
& SDE_AUX_MASK
)
1077 dp_aux_irq_handler(dev
);
1079 if (pch_iir
& SDE_GMBUS
)
1080 gmbus_irq_handler(dev
);
1082 if (pch_iir
& SDE_AUDIO_HDCP_MASK
)
1083 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1085 if (pch_iir
& SDE_AUDIO_TRANS_MASK
)
1086 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1088 if (pch_iir
& SDE_POISON
)
1089 DRM_ERROR("PCH poison interrupt\n");
1091 if (pch_iir
& SDE_FDI_MASK
)
1093 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1095 I915_READ(FDI_RX_IIR(pipe
)));
1097 if (pch_iir
& (SDE_TRANSB_CRC_DONE
| SDE_TRANSA_CRC_DONE
))
1098 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1100 if (pch_iir
& (SDE_TRANSB_CRC_ERR
| SDE_TRANSA_CRC_ERR
))
1101 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1103 if (pch_iir
& SDE_TRANSA_FIFO_UNDER
)
1104 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1106 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1108 if (pch_iir
& SDE_TRANSB_FIFO_UNDER
)
1109 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1111 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1114 static void ivb_err_int_handler(struct drm_device
*dev
)
1116 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1117 u32 err_int
= I915_READ(GEN7_ERR_INT
);
1119 if (err_int
& ERR_INT_POISON
)
1120 DRM_ERROR("Poison interrupt\n");
1122 if (err_int
& ERR_INT_FIFO_UNDERRUN_A
)
1123 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_A
, false))
1124 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1126 if (err_int
& ERR_INT_FIFO_UNDERRUN_B
)
1127 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_B
, false))
1128 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1130 if (err_int
& ERR_INT_FIFO_UNDERRUN_C
)
1131 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_C
, false))
1132 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1134 I915_WRITE(GEN7_ERR_INT
, err_int
);
1137 static void cpt_serr_int_handler(struct drm_device
*dev
)
1139 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1140 u32 serr_int
= I915_READ(SERR_INT
);
1142 if (serr_int
& SERR_INT_POISON
)
1143 DRM_ERROR("PCH poison interrupt\n");
1145 if (serr_int
& SERR_INT_TRANS_A_FIFO_UNDERRUN
)
1146 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
,
1148 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1150 if (serr_int
& SERR_INT_TRANS_B_FIFO_UNDERRUN
)
1151 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_B
,
1153 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1155 if (serr_int
& SERR_INT_TRANS_C_FIFO_UNDERRUN
)
1156 if (intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_C
,
1158 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1160 I915_WRITE(SERR_INT
, serr_int
);
1163 static void cpt_irq_handler(struct drm_device
*dev
, u32 pch_iir
)
1165 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1167 u32 hotplug_trigger
= pch_iir
& SDE_HOTPLUG_MASK_CPT
;
1169 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_cpt
);
1171 if (pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) {
1172 int port
= ffs((pch_iir
& SDE_AUDIO_POWER_MASK_CPT
) >>
1173 SDE_AUDIO_POWER_SHIFT_CPT
);
1174 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1178 if (pch_iir
& SDE_AUX_MASK_CPT
)
1179 dp_aux_irq_handler(dev
);
1181 if (pch_iir
& SDE_GMBUS_CPT
)
1182 gmbus_irq_handler(dev
);
1184 if (pch_iir
& SDE_AUDIO_CP_REQ_CPT
)
1185 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1187 if (pch_iir
& SDE_AUDIO_CP_CHG_CPT
)
1188 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1190 if (pch_iir
& SDE_FDI_MASK_CPT
)
1192 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1194 I915_READ(FDI_RX_IIR(pipe
)));
1196 if (pch_iir
& SDE_ERROR_CPT
)
1197 cpt_serr_int_handler(dev
);
1200 static void ilk_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
1202 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1204 if (de_iir
& DE_AUX_CHANNEL_A
)
1205 dp_aux_irq_handler(dev
);
1207 if (de_iir
& DE_GSE
)
1208 intel_opregion_asle_intr(dev
);
1210 if (de_iir
& DE_PIPEA_VBLANK
)
1211 drm_handle_vblank(dev
, 0);
1213 if (de_iir
& DE_PIPEB_VBLANK
)
1214 drm_handle_vblank(dev
, 1);
1216 if (de_iir
& DE_POISON
)
1217 DRM_ERROR("Poison interrupt\n");
1219 if (de_iir
& DE_PIPEA_FIFO_UNDERRUN
)
1220 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_A
, false))
1221 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1223 if (de_iir
& DE_PIPEB_FIFO_UNDERRUN
)
1224 if (intel_set_cpu_fifo_underrun_reporting(dev
, PIPE_B
, false))
1225 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1227 if (de_iir
& DE_PLANEA_FLIP_DONE
) {
1228 intel_prepare_page_flip(dev
, 0);
1229 intel_finish_page_flip_plane(dev
, 0);
1232 if (de_iir
& DE_PLANEB_FLIP_DONE
) {
1233 intel_prepare_page_flip(dev
, 1);
1234 intel_finish_page_flip_plane(dev
, 1);
1237 /* check event from PCH */
1238 if (de_iir
& DE_PCH_EVENT
) {
1239 u32 pch_iir
= I915_READ(SDEIIR
);
1241 if (HAS_PCH_CPT(dev
))
1242 cpt_irq_handler(dev
, pch_iir
);
1244 ibx_irq_handler(dev
, pch_iir
);
1246 /* should clear PCH hotplug event before clear CPU irq */
1247 I915_WRITE(SDEIIR
, pch_iir
);
1250 if (IS_GEN5(dev
) && de_iir
& DE_PCU_EVENT
)
1251 ironlake_rps_change_irq_handler(dev
);
1254 static void ivb_display_irq_handler(struct drm_device
*dev
, u32 de_iir
)
1256 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1259 if (de_iir
& DE_ERR_INT_IVB
)
1260 ivb_err_int_handler(dev
);
1262 if (de_iir
& DE_AUX_CHANNEL_A_IVB
)
1263 dp_aux_irq_handler(dev
);
1265 if (de_iir
& DE_GSE_IVB
)
1266 intel_opregion_asle_intr(dev
);
1268 for (i
= 0; i
< 3; i
++) {
1269 if (de_iir
& (DE_PIPEA_VBLANK_IVB
<< (5 * i
)))
1270 drm_handle_vblank(dev
, i
);
1271 if (de_iir
& (DE_PLANEA_FLIP_DONE_IVB
<< (5 * i
))) {
1272 intel_prepare_page_flip(dev
, i
);
1273 intel_finish_page_flip_plane(dev
, i
);
1277 /* check event from PCH */
1278 if (!HAS_PCH_NOP(dev
) && (de_iir
& DE_PCH_EVENT_IVB
)) {
1279 u32 pch_iir
= I915_READ(SDEIIR
);
1281 cpt_irq_handler(dev
, pch_iir
);
1283 /* clear PCH hotplug event before clear CPU irq */
1284 I915_WRITE(SDEIIR
, pch_iir
);
1288 static irqreturn_t
ivybridge_irq_handler(int irq
, void *arg
)
1290 struct drm_device
*dev
= (struct drm_device
*) arg
;
1291 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1292 u32 de_iir
, gt_iir
, de_ier
, pm_iir
, sde_ier
= 0;
1293 irqreturn_t ret
= IRQ_NONE
;
1295 atomic_inc(&dev_priv
->irq_received
);
1297 /* We get interrupts on unclaimed registers, so check for this before we
1298 * do any I915_{READ,WRITE}. */
1299 if (IS_HASWELL(dev
) &&
1300 (I915_READ_NOTRACE(FPGA_DBG
) & FPGA_DBG_RM_NOCLAIM
)) {
1301 DRM_ERROR("Unclaimed register before interrupt\n");
1302 I915_WRITE_NOTRACE(FPGA_DBG
, FPGA_DBG_RM_NOCLAIM
);
1305 /* disable master interrupt before clearing iir */
1306 de_ier
= I915_READ(DEIER
);
1307 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
1309 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1310 * interrupts will will be stored on its back queue, and then we'll be
1311 * able to process them after we restore SDEIER (as soon as we restore
1312 * it, we'll get an interrupt if SDEIIR still has something to process
1313 * due to its back queue). */
1314 if (!HAS_PCH_NOP(dev
)) {
1315 sde_ier
= I915_READ(SDEIER
);
1316 I915_WRITE(SDEIER
, 0);
1317 POSTING_READ(SDEIER
);
1320 /* On Haswell, also mask ERR_INT because we don't want to risk
1321 * generating "unclaimed register" interrupts from inside the interrupt
1323 if (IS_HASWELL(dev
)) {
1324 spin_lock(&dev_priv
->irq_lock
);
1325 ironlake_disable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
1326 spin_unlock(&dev_priv
->irq_lock
);
1329 gt_iir
= I915_READ(GTIIR
);
1331 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1332 I915_WRITE(GTIIR
, gt_iir
);
1336 de_iir
= I915_READ(DEIIR
);
1338 ivb_display_irq_handler(dev
, de_iir
);
1340 I915_WRITE(DEIIR
, de_iir
);
1344 pm_iir
= I915_READ(GEN6_PMIIR
);
1346 if (IS_HASWELL(dev
))
1347 hsw_pm_irq_handler(dev_priv
, pm_iir
);
1348 else if (pm_iir
& GEN6_PM_RPS_EVENTS
)
1349 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1350 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1354 if (IS_HASWELL(dev
)) {
1355 spin_lock(&dev_priv
->irq_lock
);
1356 if (ivb_can_enable_err_int(dev
))
1357 ironlake_enable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
1358 spin_unlock(&dev_priv
->irq_lock
);
1361 I915_WRITE(DEIER
, de_ier
);
1362 POSTING_READ(DEIER
);
1363 if (!HAS_PCH_NOP(dev
)) {
1364 I915_WRITE(SDEIER
, sde_ier
);
1365 POSTING_READ(SDEIER
);
1371 static void ilk_gt_irq_handler(struct drm_device
*dev
,
1372 struct drm_i915_private
*dev_priv
,
1376 (GT_RENDER_USER_INTERRUPT
| GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
))
1377 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
1378 if (gt_iir
& ILK_BSD_USER_INTERRUPT
)
1379 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
1382 static irqreturn_t
ironlake_irq_handler(int irq
, void *arg
)
1384 struct drm_device
*dev
= (struct drm_device
*) arg
;
1385 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1387 u32 de_iir
, gt_iir
, de_ier
, pm_iir
, sde_ier
;
1389 atomic_inc(&dev_priv
->irq_received
);
1391 /* disable master interrupt before clearing iir */
1392 de_ier
= I915_READ(DEIER
);
1393 I915_WRITE(DEIER
, de_ier
& ~DE_MASTER_IRQ_CONTROL
);
1394 POSTING_READ(DEIER
);
1396 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1397 * interrupts will will be stored on its back queue, and then we'll be
1398 * able to process them after we restore SDEIER (as soon as we restore
1399 * it, we'll get an interrupt if SDEIIR still has something to process
1400 * due to its back queue). */
1401 sde_ier
= I915_READ(SDEIER
);
1402 I915_WRITE(SDEIER
, 0);
1403 POSTING_READ(SDEIER
);
1405 de_iir
= I915_READ(DEIIR
);
1406 gt_iir
= I915_READ(GTIIR
);
1407 pm_iir
= I915_READ(GEN6_PMIIR
);
1409 if (de_iir
== 0 && gt_iir
== 0 && (!IS_GEN6(dev
) || pm_iir
== 0))
1415 ilk_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1417 snb_gt_irq_handler(dev
, dev_priv
, gt_iir
);
1420 ilk_display_irq_handler(dev
, de_iir
);
1422 if (IS_GEN6(dev
) && pm_iir
& GEN6_PM_RPS_EVENTS
)
1423 gen6_rps_irq_handler(dev_priv
, pm_iir
);
1425 I915_WRITE(GTIIR
, gt_iir
);
1426 I915_WRITE(DEIIR
, de_iir
);
1427 I915_WRITE(GEN6_PMIIR
, pm_iir
);
1430 I915_WRITE(DEIER
, de_ier
);
1431 POSTING_READ(DEIER
);
1432 I915_WRITE(SDEIER
, sde_ier
);
1433 POSTING_READ(SDEIER
);
1439 * i915_error_work_func - do process context error handling work
1440 * @work: work struct
1442 * Fire an error uevent so userspace can see that a hang or error
1445 static void i915_error_work_func(struct work_struct
*work
)
1447 struct i915_gpu_error
*error
= container_of(work
, struct i915_gpu_error
,
1449 drm_i915_private_t
*dev_priv
= container_of(error
, drm_i915_private_t
,
1451 struct drm_device
*dev
= dev_priv
->dev
;
1452 struct intel_ring_buffer
*ring
;
1453 char *error_event
[] = { "ERROR=1", NULL
};
1454 char *reset_event
[] = { "RESET=1", NULL
};
1455 char *reset_done_event
[] = { "ERROR=0", NULL
};
1458 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
, error_event
);
1461 * Note that there's only one work item which does gpu resets, so we
1462 * need not worry about concurrent gpu resets potentially incrementing
1463 * error->reset_counter twice. We only need to take care of another
1464 * racing irq/hangcheck declaring the gpu dead for a second time. A
1465 * quick check for that is good enough: schedule_work ensures the
1466 * correct ordering between hang detection and this work item, and since
1467 * the reset in-progress bit is only ever set by code outside of this
1468 * work we don't need to worry about any other races.
1470 if (i915_reset_in_progress(error
) && !i915_terminally_wedged(error
)) {
1471 DRM_DEBUG_DRIVER("resetting chip\n");
1472 kobject_uevent_env(&dev
->primary
->kdev
.kobj
, KOBJ_CHANGE
,
1475 ret
= i915_reset(dev
);
1479 * After all the gem state is reset, increment the reset
1480 * counter and wake up everyone waiting for the reset to
1483 * Since unlock operations are a one-sided barrier only,
1484 * we need to insert a barrier here to order any seqno
1486 * the counter increment.
1488 smp_mb__before_atomic_inc();
1489 atomic_inc(&dev_priv
->gpu_error
.reset_counter
);
1491 kobject_uevent_env(&dev
->primary
->kdev
.kobj
,
1492 KOBJ_CHANGE
, reset_done_event
);
1494 atomic_set(&error
->reset_counter
, I915_WEDGED
);
1497 for_each_ring(ring
, dev_priv
, i
)
1498 wake_up_all(&ring
->irq_queue
);
1500 intel_display_handle_reset(dev
);
1502 wake_up_all(&dev_priv
->gpu_error
.reset_queue
);
1506 static void i915_report_and_clear_eir(struct drm_device
*dev
)
1508 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1509 uint32_t instdone
[I915_NUM_INSTDONE_REG
];
1510 u32 eir
= I915_READ(EIR
);
1516 pr_err("render error detected, EIR: 0x%08x\n", eir
);
1518 i915_get_extra_instdone(dev
, instdone
);
1521 if (eir
& (GM45_ERROR_MEM_PRIV
| GM45_ERROR_CP_PRIV
)) {
1522 u32 ipeir
= I915_READ(IPEIR_I965
);
1524 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1525 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1526 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
1527 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
1528 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1529 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1530 I915_WRITE(IPEIR_I965
, ipeir
);
1531 POSTING_READ(IPEIR_I965
);
1533 if (eir
& GM45_ERROR_PAGE_TABLE
) {
1534 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1535 pr_err("page table error\n");
1536 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1537 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1538 POSTING_READ(PGTBL_ER
);
1542 if (!IS_GEN2(dev
)) {
1543 if (eir
& I915_ERROR_PAGE_TABLE
) {
1544 u32 pgtbl_err
= I915_READ(PGTBL_ER
);
1545 pr_err("page table error\n");
1546 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err
);
1547 I915_WRITE(PGTBL_ER
, pgtbl_err
);
1548 POSTING_READ(PGTBL_ER
);
1552 if (eir
& I915_ERROR_MEMORY_REFRESH
) {
1553 pr_err("memory refresh error:\n");
1555 pr_err("pipe %c stat: 0x%08x\n",
1556 pipe_name(pipe
), I915_READ(PIPESTAT(pipe
)));
1557 /* pipestat has already been acked */
1559 if (eir
& I915_ERROR_INSTRUCTION
) {
1560 pr_err("instruction error\n");
1561 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM
));
1562 for (i
= 0; i
< ARRAY_SIZE(instdone
); i
++)
1563 pr_err(" INSTDONE_%d: 0x%08x\n", i
, instdone
[i
]);
1564 if (INTEL_INFO(dev
)->gen
< 4) {
1565 u32 ipeir
= I915_READ(IPEIR
);
1567 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR
));
1568 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR
));
1569 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD
));
1570 I915_WRITE(IPEIR
, ipeir
);
1571 POSTING_READ(IPEIR
);
1573 u32 ipeir
= I915_READ(IPEIR_I965
);
1575 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965
));
1576 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965
));
1577 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS
));
1578 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965
));
1579 I915_WRITE(IPEIR_I965
, ipeir
);
1580 POSTING_READ(IPEIR_I965
);
1584 I915_WRITE(EIR
, eir
);
1586 eir
= I915_READ(EIR
);
1589 * some errors might have become stuck,
1592 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir
);
1593 I915_WRITE(EMR
, I915_READ(EMR
) | eir
);
1594 I915_WRITE(IIR
, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
1599 * i915_handle_error - handle an error interrupt
1602 * Do some basic checking of regsiter state at error interrupt time and
1603 * dump it to the syslog. Also call i915_capture_error_state() to make
1604 * sure we get a record and make it available in debugfs. Fire a uevent
1605 * so userspace knows something bad happened (should trigger collection
1606 * of a ring dump etc.).
1608 void i915_handle_error(struct drm_device
*dev
, bool wedged
)
1610 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1611 struct intel_ring_buffer
*ring
;
1614 i915_capture_error_state(dev
);
1615 i915_report_and_clear_eir(dev
);
1618 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG
,
1619 &dev_priv
->gpu_error
.reset_counter
);
1622 * Wakeup waiting processes so that the reset work item
1623 * doesn't deadlock trying to grab various locks.
1625 for_each_ring(ring
, dev_priv
, i
)
1626 wake_up_all(&ring
->irq_queue
);
1629 queue_work(dev_priv
->wq
, &dev_priv
->gpu_error
.work
);
1632 static void __always_unused
i915_pageflip_stall_check(struct drm_device
*dev
, int pipe
)
1634 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1635 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1636 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1637 struct drm_i915_gem_object
*obj
;
1638 struct intel_unpin_work
*work
;
1639 unsigned long flags
;
1640 bool stall_detected
;
1642 /* Ignore early vblank irqs */
1643 if (intel_crtc
== NULL
)
1646 spin_lock_irqsave(&dev
->event_lock
, flags
);
1647 work
= intel_crtc
->unpin_work
;
1650 atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
||
1651 !work
->enable_stall_check
) {
1652 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1653 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1657 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1658 obj
= work
->pending_flip_obj
;
1659 if (INTEL_INFO(dev
)->gen
>= 4) {
1660 int dspsurf
= DSPSURF(intel_crtc
->plane
);
1661 stall_detected
= I915_HI_DISPBASE(I915_READ(dspsurf
)) ==
1662 i915_gem_obj_ggtt_offset(obj
);
1664 int dspaddr
= DSPADDR(intel_crtc
->plane
);
1665 stall_detected
= I915_READ(dspaddr
) == (i915_gem_obj_ggtt_offset(obj
) +
1666 crtc
->y
* crtc
->fb
->pitches
[0] +
1667 crtc
->x
* crtc
->fb
->bits_per_pixel
/8);
1670 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1672 if (stall_detected
) {
1673 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1674 intel_prepare_page_flip(dev
, intel_crtc
->plane
);
1678 /* Called from drm generic code, passed 'crtc' which
1679 * we use as a pipe index
1681 static int i915_enable_vblank(struct drm_device
*dev
, int pipe
)
1683 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1684 unsigned long irqflags
;
1686 if (!i915_pipe_enabled(dev
, pipe
))
1689 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1690 if (INTEL_INFO(dev
)->gen
>= 4)
1691 i915_enable_pipestat(dev_priv
, pipe
,
1692 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1694 i915_enable_pipestat(dev_priv
, pipe
,
1695 PIPE_VBLANK_INTERRUPT_ENABLE
);
1697 /* maintain vblank delivery even in deep C-states */
1698 if (dev_priv
->info
->gen
== 3)
1699 I915_WRITE(INSTPM
, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS
));
1700 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1705 static int ironlake_enable_vblank(struct drm_device
*dev
, int pipe
)
1707 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1708 unsigned long irqflags
;
1710 if (!i915_pipe_enabled(dev
, pipe
))
1713 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1714 ironlake_enable_display_irq(dev_priv
, (pipe
== 0) ?
1715 DE_PIPEA_VBLANK
: DE_PIPEB_VBLANK
);
1716 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1721 static int ivybridge_enable_vblank(struct drm_device
*dev
, int pipe
)
1723 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1724 unsigned long irqflags
;
1726 if (!i915_pipe_enabled(dev
, pipe
))
1729 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1730 ironlake_enable_display_irq(dev_priv
,
1731 DE_PIPEA_VBLANK_IVB
<< (5 * pipe
));
1732 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1737 static int valleyview_enable_vblank(struct drm_device
*dev
, int pipe
)
1739 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1740 unsigned long irqflags
;
1743 if (!i915_pipe_enabled(dev
, pipe
))
1746 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1747 imr
= I915_READ(VLV_IMR
);
1749 imr
&= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
1751 imr
&= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1752 I915_WRITE(VLV_IMR
, imr
);
1753 i915_enable_pipestat(dev_priv
, pipe
,
1754 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1755 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1760 /* Called from drm generic code, passed 'crtc' which
1761 * we use as a pipe index
1763 static void i915_disable_vblank(struct drm_device
*dev
, int pipe
)
1765 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1766 unsigned long irqflags
;
1768 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1769 if (dev_priv
->info
->gen
== 3)
1770 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS
));
1772 i915_disable_pipestat(dev_priv
, pipe
,
1773 PIPE_VBLANK_INTERRUPT_ENABLE
|
1774 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1775 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1778 static void ironlake_disable_vblank(struct drm_device
*dev
, int pipe
)
1780 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1781 unsigned long irqflags
;
1783 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1784 ironlake_disable_display_irq(dev_priv
, (pipe
== 0) ?
1785 DE_PIPEA_VBLANK
: DE_PIPEB_VBLANK
);
1786 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1789 static void ivybridge_disable_vblank(struct drm_device
*dev
, int pipe
)
1791 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1792 unsigned long irqflags
;
1794 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1795 ironlake_disable_display_irq(dev_priv
,
1796 DE_PIPEA_VBLANK_IVB
<< (pipe
* 5));
1797 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1800 static void valleyview_disable_vblank(struct drm_device
*dev
, int pipe
)
1802 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
1803 unsigned long irqflags
;
1806 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
1807 i915_disable_pipestat(dev_priv
, pipe
,
1808 PIPE_START_VBLANK_INTERRUPT_ENABLE
);
1809 imr
= I915_READ(VLV_IMR
);
1811 imr
|= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
1813 imr
|= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
1814 I915_WRITE(VLV_IMR
, imr
);
1815 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
1819 ring_last_seqno(struct intel_ring_buffer
*ring
)
1821 return list_entry(ring
->request_list
.prev
,
1822 struct drm_i915_gem_request
, list
)->seqno
;
1826 ring_idle(struct intel_ring_buffer
*ring
, u32 seqno
)
1828 return (list_empty(&ring
->request_list
) ||
1829 i915_seqno_passed(seqno
, ring_last_seqno(ring
)));
1832 static struct intel_ring_buffer
*
1833 semaphore_waits_for(struct intel_ring_buffer
*ring
, u32
*seqno
)
1835 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1836 u32 cmd
, ipehr
, acthd
, acthd_min
;
1838 ipehr
= I915_READ(RING_IPEHR(ring
->mmio_base
));
1839 if ((ipehr
& ~(0x3 << 16)) !=
1840 (MI_SEMAPHORE_MBOX
| MI_SEMAPHORE_COMPARE
| MI_SEMAPHORE_REGISTER
))
1843 /* ACTHD is likely pointing to the dword after the actual command,
1844 * so scan backwards until we find the MBOX.
1846 acthd
= intel_ring_get_active_head(ring
) & HEAD_ADDR
;
1847 acthd_min
= max((int)acthd
- 3 * 4, 0);
1849 cmd
= ioread32(ring
->virtual_start
+ acthd
);
1854 if (acthd
< acthd_min
)
1858 *seqno
= ioread32(ring
->virtual_start
+acthd
+4)+1;
1859 return &dev_priv
->ring
[(ring
->id
+ (((ipehr
>> 17) & 1) + 1)) % 3];
1862 static int semaphore_passed(struct intel_ring_buffer
*ring
)
1864 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1865 struct intel_ring_buffer
*signaller
;
1868 ring
->hangcheck
.deadlock
= true;
1870 signaller
= semaphore_waits_for(ring
, &seqno
);
1871 if (signaller
== NULL
|| signaller
->hangcheck
.deadlock
)
1874 /* cursory check for an unkickable deadlock */
1875 ctl
= I915_READ_CTL(signaller
);
1876 if (ctl
& RING_WAIT_SEMAPHORE
&& semaphore_passed(signaller
) < 0)
1879 return i915_seqno_passed(signaller
->get_seqno(signaller
, false), seqno
);
1882 static void semaphore_clear_deadlocks(struct drm_i915_private
*dev_priv
)
1884 struct intel_ring_buffer
*ring
;
1887 for_each_ring(ring
, dev_priv
, i
)
1888 ring
->hangcheck
.deadlock
= false;
1891 static enum intel_ring_hangcheck_action
1892 ring_stuck(struct intel_ring_buffer
*ring
, u32 acthd
)
1894 struct drm_device
*dev
= ring
->dev
;
1895 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1898 if (ring
->hangcheck
.acthd
!= acthd
)
1904 /* Is the chip hanging on a WAIT_FOR_EVENT?
1905 * If so we can simply poke the RB_WAIT bit
1906 * and break the hang. This should work on
1907 * all but the second generation chipsets.
1909 tmp
= I915_READ_CTL(ring
);
1910 if (tmp
& RING_WAIT
) {
1911 DRM_ERROR("Kicking stuck wait on %s\n",
1913 I915_WRITE_CTL(ring
, tmp
);
1917 if (INTEL_INFO(dev
)->gen
>= 6 && tmp
& RING_WAIT_SEMAPHORE
) {
1918 switch (semaphore_passed(ring
)) {
1922 DRM_ERROR("Kicking stuck semaphore on %s\n",
1924 I915_WRITE_CTL(ring
, tmp
);
1935 * This is called when the chip hasn't reported back with completed
1936 * batchbuffers in a long time. We keep track per ring seqno progress and
1937 * if there are no progress, hangcheck score for that ring is increased.
1938 * Further, acthd is inspected to see if the ring is stuck. On stuck case
1939 * we kick the ring. If we see no progress on three subsequent calls
1940 * we assume chip is wedged and try to fix it by resetting the chip.
1942 void i915_hangcheck_elapsed(unsigned long data
)
1944 struct drm_device
*dev
= (struct drm_device
*)data
;
1945 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1946 struct intel_ring_buffer
*ring
;
1948 int busy_count
= 0, rings_hung
= 0;
1949 bool stuck
[I915_NUM_RINGS
] = { 0 };
1955 if (!i915_enable_hangcheck
)
1958 for_each_ring(ring
, dev_priv
, i
) {
1962 semaphore_clear_deadlocks(dev_priv
);
1964 seqno
= ring
->get_seqno(ring
, false);
1965 acthd
= intel_ring_get_active_head(ring
);
1967 if (ring
->hangcheck
.seqno
== seqno
) {
1968 if (ring_idle(ring
, seqno
)) {
1969 if (waitqueue_active(&ring
->irq_queue
)) {
1970 /* Issue a wake-up to catch stuck h/w. */
1971 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1973 wake_up_all(&ring
->irq_queue
);
1974 ring
->hangcheck
.score
+= HUNG
;
1980 /* We always increment the hangcheck score
1981 * if the ring is busy and still processing
1982 * the same request, so that no single request
1983 * can run indefinitely (such as a chain of
1984 * batches). The only time we do not increment
1985 * the hangcheck score on this ring, if this
1986 * ring is in a legitimate wait for another
1987 * ring. In that case the waiting ring is a
1988 * victim and we want to be sure we catch the
1989 * right culprit. Then every time we do kick
1990 * the ring, add a small increment to the
1991 * score so that we can catch a batch that is
1992 * being repeatedly kicked and so responsible
1993 * for stalling the machine.
1995 ring
->hangcheck
.action
= ring_stuck(ring
,
1998 switch (ring
->hangcheck
.action
) {
2013 ring
->hangcheck
.score
+= score
;
2016 /* Gradually reduce the count so that we catch DoS
2017 * attempts across multiple batches.
2019 if (ring
->hangcheck
.score
> 0)
2020 ring
->hangcheck
.score
--;
2023 ring
->hangcheck
.seqno
= seqno
;
2024 ring
->hangcheck
.acthd
= acthd
;
2028 for_each_ring(ring
, dev_priv
, i
) {
2029 if (ring
->hangcheck
.score
> FIRE
) {
2030 DRM_ERROR("%s on %s\n",
2031 stuck
[i
] ? "stuck" : "no progress",
2038 return i915_handle_error(dev
, true);
2041 /* Reset timer case chip hangs without another request
2043 i915_queue_hangcheck(dev
);
2046 void i915_queue_hangcheck(struct drm_device
*dev
)
2048 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2049 if (!i915_enable_hangcheck
)
2052 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
2053 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
2056 static void ibx_irq_preinstall(struct drm_device
*dev
)
2058 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2060 if (HAS_PCH_NOP(dev
))
2063 /* south display irq */
2064 I915_WRITE(SDEIMR
, 0xffffffff);
2066 * SDEIER is also touched by the interrupt handler to work around missed
2067 * PCH interrupts. Hence we can't update it after the interrupt handler
2068 * is enabled - instead we unconditionally enable all PCH interrupt
2069 * sources here, but then only unmask them as needed with SDEIMR.
2071 I915_WRITE(SDEIER
, 0xffffffff);
2072 POSTING_READ(SDEIER
);
2075 static void gen5_gt_irq_preinstall(struct drm_device
*dev
)
2077 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2080 I915_WRITE(GTIMR
, 0xffffffff);
2081 I915_WRITE(GTIER
, 0x0);
2082 POSTING_READ(GTIER
);
2084 if (INTEL_INFO(dev
)->gen
>= 6) {
2086 I915_WRITE(GEN6_PMIMR
, 0xffffffff);
2087 I915_WRITE(GEN6_PMIER
, 0x0);
2088 POSTING_READ(GEN6_PMIER
);
2094 static void ironlake_irq_preinstall(struct drm_device
*dev
)
2096 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2098 atomic_set(&dev_priv
->irq_received
, 0);
2100 I915_WRITE(HWSTAM
, 0xeffe);
2102 I915_WRITE(DEIMR
, 0xffffffff);
2103 I915_WRITE(DEIER
, 0x0);
2104 POSTING_READ(DEIER
);
2106 gen5_gt_irq_preinstall(dev
);
2108 ibx_irq_preinstall(dev
);
2111 static void valleyview_irq_preinstall(struct drm_device
*dev
)
2113 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2116 atomic_set(&dev_priv
->irq_received
, 0);
2119 I915_WRITE(VLV_IMR
, 0);
2120 I915_WRITE(RING_IMR(RENDER_RING_BASE
), 0);
2121 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE
), 0);
2122 I915_WRITE(RING_IMR(BLT_RING_BASE
), 0);
2125 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2126 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2128 gen5_gt_irq_preinstall(dev
);
2130 I915_WRITE(DPINVGTT
, 0xff);
2132 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2133 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2135 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2136 I915_WRITE(VLV_IIR
, 0xffffffff);
2137 I915_WRITE(VLV_IMR
, 0xffffffff);
2138 I915_WRITE(VLV_IER
, 0x0);
2139 POSTING_READ(VLV_IER
);
2142 static void ibx_hpd_irq_setup(struct drm_device
*dev
)
2144 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2145 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2146 struct intel_encoder
*intel_encoder
;
2147 u32 hotplug_irqs
, hotplug
, enabled_irqs
= 0;
2149 if (HAS_PCH_IBX(dev
)) {
2150 hotplug_irqs
= SDE_HOTPLUG_MASK
;
2151 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2152 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2153 enabled_irqs
|= hpd_ibx
[intel_encoder
->hpd_pin
];
2155 hotplug_irqs
= SDE_HOTPLUG_MASK_CPT
;
2156 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2157 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2158 enabled_irqs
|= hpd_cpt
[intel_encoder
->hpd_pin
];
2161 ibx_display_interrupt_update(dev_priv
, hotplug_irqs
, enabled_irqs
);
2164 * Enable digital hotplug on the PCH, and configure the DP short pulse
2165 * duration to 2ms (which is the minimum in the Display Port spec)
2167 * This register is the same on all known PCH chips.
2169 hotplug
= I915_READ(PCH_PORT_HOTPLUG
);
2170 hotplug
&= ~(PORTD_PULSE_DURATION_MASK
|PORTC_PULSE_DURATION_MASK
|PORTB_PULSE_DURATION_MASK
);
2171 hotplug
|= PORTD_HOTPLUG_ENABLE
| PORTD_PULSE_DURATION_2ms
;
2172 hotplug
|= PORTC_HOTPLUG_ENABLE
| PORTC_PULSE_DURATION_2ms
;
2173 hotplug
|= PORTB_HOTPLUG_ENABLE
| PORTB_PULSE_DURATION_2ms
;
2174 I915_WRITE(PCH_PORT_HOTPLUG
, hotplug
);
2177 static void ibx_irq_postinstall(struct drm_device
*dev
)
2179 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2182 if (HAS_PCH_NOP(dev
))
2185 if (HAS_PCH_IBX(dev
)) {
2186 mask
= SDE_GMBUS
| SDE_AUX_MASK
| SDE_TRANSB_FIFO_UNDER
|
2187 SDE_TRANSA_FIFO_UNDER
| SDE_POISON
;
2189 mask
= SDE_GMBUS_CPT
| SDE_AUX_MASK_CPT
| SDE_ERROR_CPT
;
2191 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2194 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2195 I915_WRITE(SDEIMR
, ~mask
);
2198 static void gen5_gt_irq_postinstall(struct drm_device
*dev
)
2200 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2201 u32 pm_irqs
, gt_irqs
;
2203 pm_irqs
= gt_irqs
= 0;
2205 dev_priv
->gt_irq_mask
= ~0;
2206 if (HAS_L3_GPU_CACHE(dev
)) {
2207 /* L3 parity interrupt is always unmasked. */
2208 dev_priv
->gt_irq_mask
= ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
2209 gt_irqs
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
2212 gt_irqs
|= GT_RENDER_USER_INTERRUPT
;
2214 gt_irqs
|= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
|
2215 ILK_BSD_USER_INTERRUPT
;
2217 gt_irqs
|= GT_BLT_USER_INTERRUPT
| GT_BSD_USER_INTERRUPT
;
2220 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2221 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
2222 I915_WRITE(GTIER
, gt_irqs
);
2223 POSTING_READ(GTIER
);
2225 if (INTEL_INFO(dev
)->gen
>= 6) {
2226 pm_irqs
|= GEN6_PM_RPS_EVENTS
;
2229 pm_irqs
|= PM_VEBOX_USER_INTERRUPT
;
2231 I915_WRITE(GEN6_PMIIR
, I915_READ(GEN6_PMIIR
));
2232 I915_WRITE(GEN6_PMIMR
, 0xffffffff);
2233 I915_WRITE(GEN6_PMIER
, pm_irqs
);
2234 POSTING_READ(GEN6_PMIER
);
2238 static int ironlake_irq_postinstall(struct drm_device
*dev
)
2240 unsigned long irqflags
;
2242 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2243 /* enable kind of interrupts always enabled */
2244 u32 display_mask
= DE_MASTER_IRQ_CONTROL
| DE_GSE
| DE_PCH_EVENT
|
2245 DE_PLANEA_FLIP_DONE
| DE_PLANEB_FLIP_DONE
|
2246 DE_AUX_CHANNEL_A
| DE_PIPEB_FIFO_UNDERRUN
|
2247 DE_PIPEA_FIFO_UNDERRUN
| DE_POISON
;
2249 dev_priv
->irq_mask
= ~display_mask
;
2251 /* should always can generate irq */
2252 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2253 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
2254 I915_WRITE(DEIER
, display_mask
|
2255 DE_PIPEA_VBLANK
| DE_PIPEB_VBLANK
| DE_PCU_EVENT
);
2256 POSTING_READ(DEIER
);
2258 gen5_gt_irq_postinstall(dev
);
2260 ibx_irq_postinstall(dev
);
2262 if (IS_IRONLAKE_M(dev
)) {
2263 /* Enable PCU event interrupts
2265 * spinlocking not required here for correctness since interrupt
2266 * setup is guaranteed to run in single-threaded context. But we
2267 * need it to make the assert_spin_locked happy. */
2268 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2269 ironlake_enable_display_irq(dev_priv
, DE_PCU_EVENT
);
2270 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2276 static int ivybridge_irq_postinstall(struct drm_device
*dev
)
2278 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2279 /* enable kind of interrupts always enabled */
2281 DE_MASTER_IRQ_CONTROL
| DE_GSE_IVB
| DE_PCH_EVENT_IVB
|
2282 DE_PLANEC_FLIP_DONE_IVB
|
2283 DE_PLANEB_FLIP_DONE_IVB
|
2284 DE_PLANEA_FLIP_DONE_IVB
|
2285 DE_AUX_CHANNEL_A_IVB
|
2288 dev_priv
->irq_mask
= ~display_mask
;
2290 /* should always can generate irq */
2291 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2292 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2293 I915_WRITE(DEIMR
, dev_priv
->irq_mask
);
2296 DE_PIPEC_VBLANK_IVB
|
2297 DE_PIPEB_VBLANK_IVB
|
2298 DE_PIPEA_VBLANK_IVB
);
2299 POSTING_READ(DEIER
);
2301 gen5_gt_irq_postinstall(dev
);
2303 ibx_irq_postinstall(dev
);
2308 static int valleyview_irq_postinstall(struct drm_device
*dev
)
2310 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2312 u32 pipestat_enable
= PLANE_FLIP_DONE_INT_EN_VLV
;
2313 unsigned long irqflags
;
2315 enable_mask
= I915_DISPLAY_PORT_INTERRUPT
;
2316 enable_mask
|= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2317 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2318 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2319 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2322 *Leave vblank interrupts masked initially. enable/disable will
2323 * toggle them based on usage.
2325 dev_priv
->irq_mask
= (~enable_mask
) |
2326 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
|
2327 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
2329 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2330 POSTING_READ(PORT_HOTPLUG_EN
);
2332 I915_WRITE(VLV_IMR
, dev_priv
->irq_mask
);
2333 I915_WRITE(VLV_IER
, enable_mask
);
2334 I915_WRITE(VLV_IIR
, 0xffffffff);
2335 I915_WRITE(PIPESTAT(0), 0xffff);
2336 I915_WRITE(PIPESTAT(1), 0xffff);
2337 POSTING_READ(VLV_IER
);
2339 /* Interrupt setup is already guaranteed to be single-threaded, this is
2340 * just to make the assert_spin_locked check happy. */
2341 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2342 i915_enable_pipestat(dev_priv
, 0, pipestat_enable
);
2343 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
2344 i915_enable_pipestat(dev_priv
, 1, pipestat_enable
);
2345 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2347 I915_WRITE(VLV_IIR
, 0xffffffff);
2348 I915_WRITE(VLV_IIR
, 0xffffffff);
2350 gen5_gt_irq_postinstall(dev
);
2352 /* ack & enable invalid PTE error interrupts */
2353 #if 0 /* FIXME: add support to irq handler for checking these bits */
2354 I915_WRITE(DPINVGTT
, DPINVGTT_STATUS_MASK
);
2355 I915_WRITE(DPINVGTT
, DPINVGTT_EN_MASK
);
2358 I915_WRITE(VLV_MASTER_IER
, MASTER_INTERRUPT_ENABLE
);
2363 static void valleyview_irq_uninstall(struct drm_device
*dev
)
2365 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2371 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2374 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2376 I915_WRITE(HWSTAM
, 0xffffffff);
2377 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2378 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2380 I915_WRITE(PIPESTAT(pipe
), 0xffff);
2381 I915_WRITE(VLV_IIR
, 0xffffffff);
2382 I915_WRITE(VLV_IMR
, 0xffffffff);
2383 I915_WRITE(VLV_IER
, 0x0);
2384 POSTING_READ(VLV_IER
);
2387 static void ironlake_irq_uninstall(struct drm_device
*dev
)
2389 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2394 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2396 I915_WRITE(HWSTAM
, 0xffffffff);
2398 I915_WRITE(DEIMR
, 0xffffffff);
2399 I915_WRITE(DEIER
, 0x0);
2400 I915_WRITE(DEIIR
, I915_READ(DEIIR
));
2402 I915_WRITE(GEN7_ERR_INT
, I915_READ(GEN7_ERR_INT
));
2404 I915_WRITE(GTIMR
, 0xffffffff);
2405 I915_WRITE(GTIER
, 0x0);
2406 I915_WRITE(GTIIR
, I915_READ(GTIIR
));
2408 if (HAS_PCH_NOP(dev
))
2411 I915_WRITE(SDEIMR
, 0xffffffff);
2412 I915_WRITE(SDEIER
, 0x0);
2413 I915_WRITE(SDEIIR
, I915_READ(SDEIIR
));
2414 if (HAS_PCH_CPT(dev
) || HAS_PCH_LPT(dev
))
2415 I915_WRITE(SERR_INT
, I915_READ(SERR_INT
));
2418 static void i8xx_irq_preinstall(struct drm_device
* dev
)
2420 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2423 atomic_set(&dev_priv
->irq_received
, 0);
2426 I915_WRITE(PIPESTAT(pipe
), 0);
2427 I915_WRITE16(IMR
, 0xffff);
2428 I915_WRITE16(IER
, 0x0);
2429 POSTING_READ16(IER
);
2432 static int i8xx_irq_postinstall(struct drm_device
*dev
)
2434 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2437 ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2439 /* Unmask the interrupts that we always want on. */
2440 dev_priv
->irq_mask
=
2441 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2442 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2443 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2444 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2445 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2446 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
2449 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2450 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2451 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2452 I915_USER_INTERRUPT
);
2453 POSTING_READ16(IER
);
2459 * Returns true when a page flip has completed.
2461 static bool i8xx_handle_vblank(struct drm_device
*dev
,
2464 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2465 u16 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(pipe
);
2467 if (!drm_handle_vblank(dev
, pipe
))
2470 if ((iir
& flip_pending
) == 0)
2473 intel_prepare_page_flip(dev
, pipe
);
2475 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2476 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2477 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2478 * the flip is completed (no longer pending). Since this doesn't raise
2479 * an interrupt per se, we watch for the change at vblank.
2481 if (I915_READ16(ISR
) & flip_pending
)
2484 intel_finish_page_flip(dev
, pipe
);
2489 static irqreturn_t
i8xx_irq_handler(int irq
, void *arg
)
2491 struct drm_device
*dev
= (struct drm_device
*) arg
;
2492 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2495 unsigned long irqflags
;
2499 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2500 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2502 atomic_inc(&dev_priv
->irq_received
);
2504 iir
= I915_READ16(IIR
);
2508 while (iir
& ~flip_mask
) {
2509 /* Can't rely on pipestat interrupt bit in iir as it might
2510 * have been cleared after the pipestat interrupt was received.
2511 * It doesn't set the bit in iir again, but it still produces
2512 * interrupts (for non-MSI).
2514 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2515 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2516 i915_handle_error(dev
, false);
2518 for_each_pipe(pipe
) {
2519 int reg
= PIPESTAT(pipe
);
2520 pipe_stats
[pipe
] = I915_READ(reg
);
2523 * Clear the PIPE*STAT regs before the IIR
2525 if (pipe_stats
[pipe
] & 0x8000ffff) {
2526 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2527 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2529 I915_WRITE(reg
, pipe_stats
[pipe
]);
2533 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2535 I915_WRITE16(IIR
, iir
& ~flip_mask
);
2536 new_iir
= I915_READ16(IIR
); /* Flush posted writes */
2538 i915_update_dri1_breadcrumb(dev
);
2540 if (iir
& I915_USER_INTERRUPT
)
2541 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2543 if (pipe_stats
[0] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2544 i8xx_handle_vblank(dev
, 0, iir
))
2545 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(0);
2547 if (pipe_stats
[1] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2548 i8xx_handle_vblank(dev
, 1, iir
))
2549 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(1);
2557 static void i8xx_irq_uninstall(struct drm_device
* dev
)
2559 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2562 for_each_pipe(pipe
) {
2563 /* Clear enable bits; then clear status bits */
2564 I915_WRITE(PIPESTAT(pipe
), 0);
2565 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
2567 I915_WRITE16(IMR
, 0xffff);
2568 I915_WRITE16(IER
, 0x0);
2569 I915_WRITE16(IIR
, I915_READ16(IIR
));
2572 static void i915_irq_preinstall(struct drm_device
* dev
)
2574 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2577 atomic_set(&dev_priv
->irq_received
, 0);
2579 if (I915_HAS_HOTPLUG(dev
)) {
2580 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2581 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2584 I915_WRITE16(HWSTAM
, 0xeffe);
2586 I915_WRITE(PIPESTAT(pipe
), 0);
2587 I915_WRITE(IMR
, 0xffffffff);
2588 I915_WRITE(IER
, 0x0);
2592 static int i915_irq_postinstall(struct drm_device
*dev
)
2594 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2597 I915_WRITE(EMR
, ~(I915_ERROR_PAGE_TABLE
| I915_ERROR_MEMORY_REFRESH
));
2599 /* Unmask the interrupts that we always want on. */
2600 dev_priv
->irq_mask
=
2601 ~(I915_ASLE_INTERRUPT
|
2602 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2603 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2604 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2605 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2606 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2609 I915_ASLE_INTERRUPT
|
2610 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2611 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2612 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
|
2613 I915_USER_INTERRUPT
;
2615 if (I915_HAS_HOTPLUG(dev
)) {
2616 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2617 POSTING_READ(PORT_HOTPLUG_EN
);
2619 /* Enable in IER... */
2620 enable_mask
|= I915_DISPLAY_PORT_INTERRUPT
;
2621 /* and unmask in IMR */
2622 dev_priv
->irq_mask
&= ~I915_DISPLAY_PORT_INTERRUPT
;
2625 I915_WRITE(IMR
, dev_priv
->irq_mask
);
2626 I915_WRITE(IER
, enable_mask
);
2629 i915_enable_asle_pipestat(dev
);
2635 * Returns true when a page flip has completed.
2637 static bool i915_handle_vblank(struct drm_device
*dev
,
2638 int plane
, int pipe
, u32 iir
)
2640 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2641 u32 flip_pending
= DISPLAY_PLANE_FLIP_PENDING(plane
);
2643 if (!drm_handle_vblank(dev
, pipe
))
2646 if ((iir
& flip_pending
) == 0)
2649 intel_prepare_page_flip(dev
, plane
);
2651 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2652 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2653 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2654 * the flip is completed (no longer pending). Since this doesn't raise
2655 * an interrupt per se, we watch for the change at vblank.
2657 if (I915_READ(ISR
) & flip_pending
)
2660 intel_finish_page_flip(dev
, pipe
);
2665 static irqreturn_t
i915_irq_handler(int irq
, void *arg
)
2667 struct drm_device
*dev
= (struct drm_device
*) arg
;
2668 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2669 u32 iir
, new_iir
, pipe_stats
[I915_MAX_PIPES
];
2670 unsigned long irqflags
;
2672 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2673 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2674 int pipe
, ret
= IRQ_NONE
;
2676 atomic_inc(&dev_priv
->irq_received
);
2678 iir
= I915_READ(IIR
);
2680 bool irq_received
= (iir
& ~flip_mask
) != 0;
2681 bool blc_event
= false;
2683 /* Can't rely on pipestat interrupt bit in iir as it might
2684 * have been cleared after the pipestat interrupt was received.
2685 * It doesn't set the bit in iir again, but it still produces
2686 * interrupts (for non-MSI).
2688 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2689 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2690 i915_handle_error(dev
, false);
2692 for_each_pipe(pipe
) {
2693 int reg
= PIPESTAT(pipe
);
2694 pipe_stats
[pipe
] = I915_READ(reg
);
2696 /* Clear the PIPE*STAT regs before the IIR */
2697 if (pipe_stats
[pipe
] & 0x8000ffff) {
2698 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2699 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2701 I915_WRITE(reg
, pipe_stats
[pipe
]);
2702 irq_received
= true;
2705 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2710 /* Consume port. Then clear IIR or we'll miss events */
2711 if ((I915_HAS_HOTPLUG(dev
)) &&
2712 (iir
& I915_DISPLAY_PORT_INTERRUPT
)) {
2713 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
2714 u32 hotplug_trigger
= hotplug_status
& HOTPLUG_INT_STATUS_I915
;
2716 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2719 intel_hpd_irq_handler(dev
, hotplug_trigger
, hpd_status_i915
);
2721 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
2722 POSTING_READ(PORT_HOTPLUG_STAT
);
2725 I915_WRITE(IIR
, iir
& ~flip_mask
);
2726 new_iir
= I915_READ(IIR
); /* Flush posted writes */
2728 if (iir
& I915_USER_INTERRUPT
)
2729 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2731 for_each_pipe(pipe
) {
2736 if (pipe_stats
[pipe
] & PIPE_VBLANK_INTERRUPT_STATUS
&&
2737 i915_handle_vblank(dev
, plane
, pipe
, iir
))
2738 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(plane
);
2740 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
2744 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
2745 intel_opregion_asle_intr(dev
);
2747 /* With MSI, interrupts are only generated when iir
2748 * transitions from zero to nonzero. If another bit got
2749 * set while we were handling the existing iir bits, then
2750 * we would never get another interrupt.
2752 * This is fine on non-MSI as well, as if we hit this path
2753 * we avoid exiting the interrupt handler only to generate
2756 * Note that for MSI this could cause a stray interrupt report
2757 * if an interrupt landed in the time between writing IIR and
2758 * the posting read. This should be rare enough to never
2759 * trigger the 99% of 100,000 interrupts test for disabling
2764 } while (iir
& ~flip_mask
);
2766 i915_update_dri1_breadcrumb(dev
);
2771 static void i915_irq_uninstall(struct drm_device
* dev
)
2773 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2776 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
2778 if (I915_HAS_HOTPLUG(dev
)) {
2779 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2780 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2783 I915_WRITE16(HWSTAM
, 0xffff);
2784 for_each_pipe(pipe
) {
2785 /* Clear enable bits; then clear status bits */
2786 I915_WRITE(PIPESTAT(pipe
), 0);
2787 I915_WRITE(PIPESTAT(pipe
), I915_READ(PIPESTAT(pipe
)));
2789 I915_WRITE(IMR
, 0xffffffff);
2790 I915_WRITE(IER
, 0x0);
2792 I915_WRITE(IIR
, I915_READ(IIR
));
2795 static void i965_irq_preinstall(struct drm_device
* dev
)
2797 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2800 atomic_set(&dev_priv
->irq_received
, 0);
2802 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2803 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
2805 I915_WRITE(HWSTAM
, 0xeffe);
2807 I915_WRITE(PIPESTAT(pipe
), 0);
2808 I915_WRITE(IMR
, 0xffffffff);
2809 I915_WRITE(IER
, 0x0);
2813 static int i965_irq_postinstall(struct drm_device
*dev
)
2815 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2818 unsigned long irqflags
;
2820 /* Unmask the interrupts that we always want on. */
2821 dev_priv
->irq_mask
= ~(I915_ASLE_INTERRUPT
|
2822 I915_DISPLAY_PORT_INTERRUPT
|
2823 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
|
2824 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
|
2825 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2826 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
|
2827 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
);
2829 enable_mask
= ~dev_priv
->irq_mask
;
2830 enable_mask
&= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2831 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
);
2832 enable_mask
|= I915_USER_INTERRUPT
;
2835 enable_mask
|= I915_BSD_USER_INTERRUPT
;
2837 /* Interrupt setup is already guaranteed to be single-threaded, this is
2838 * just to make the assert_spin_locked check happy. */
2839 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2840 i915_enable_pipestat(dev_priv
, 0, PIPE_GMBUS_EVENT_ENABLE
);
2841 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2844 * Enable some error detection, note the instruction error mask
2845 * bit is reserved, so we leave it masked.
2848 error_mask
= ~(GM45_ERROR_PAGE_TABLE
|
2849 GM45_ERROR_MEM_PRIV
|
2850 GM45_ERROR_CP_PRIV
|
2851 I915_ERROR_MEMORY_REFRESH
);
2853 error_mask
= ~(I915_ERROR_PAGE_TABLE
|
2854 I915_ERROR_MEMORY_REFRESH
);
2856 I915_WRITE(EMR
, error_mask
);
2858 I915_WRITE(IMR
, dev_priv
->irq_mask
);
2859 I915_WRITE(IER
, enable_mask
);
2862 I915_WRITE(PORT_HOTPLUG_EN
, 0);
2863 POSTING_READ(PORT_HOTPLUG_EN
);
2865 i915_enable_asle_pipestat(dev
);
2870 static void i915_hpd_irq_setup(struct drm_device
*dev
)
2872 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2873 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2874 struct intel_encoder
*intel_encoder
;
2877 assert_spin_locked(&dev_priv
->irq_lock
);
2879 if (I915_HAS_HOTPLUG(dev
)) {
2880 hotplug_en
= I915_READ(PORT_HOTPLUG_EN
);
2881 hotplug_en
&= ~HOTPLUG_INT_EN_MASK
;
2882 /* Note HDMI and DP share hotplug bits */
2883 /* enable bits are the same for all generations */
2884 list_for_each_entry(intel_encoder
, &mode_config
->encoder_list
, base
.head
)
2885 if (dev_priv
->hpd_stats
[intel_encoder
->hpd_pin
].hpd_mark
== HPD_ENABLED
)
2886 hotplug_en
|= hpd_mask_i915
[intel_encoder
->hpd_pin
];
2887 /* Programming the CRT detection parameters tends
2888 to generate a spurious hotplug event about three
2889 seconds later. So just do it once.
2892 hotplug_en
|= CRT_HOTPLUG_ACTIVATION_PERIOD_64
;
2893 hotplug_en
&= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK
;
2894 hotplug_en
|= CRT_HOTPLUG_VOLTAGE_COMPARE_50
;
2896 /* Ignore TV since it's buggy */
2897 I915_WRITE(PORT_HOTPLUG_EN
, hotplug_en
);
2901 static irqreturn_t
i965_irq_handler(int irq
, void *arg
)
2903 struct drm_device
*dev
= (struct drm_device
*) arg
;
2904 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
2906 u32 pipe_stats
[I915_MAX_PIPES
];
2907 unsigned long irqflags
;
2909 int ret
= IRQ_NONE
, pipe
;
2911 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
|
2912 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
2914 atomic_inc(&dev_priv
->irq_received
);
2916 iir
= I915_READ(IIR
);
2919 bool blc_event
= false;
2921 irq_received
= (iir
& ~flip_mask
) != 0;
2923 /* Can't rely on pipestat interrupt bit in iir as it might
2924 * have been cleared after the pipestat interrupt was received.
2925 * It doesn't set the bit in iir again, but it still produces
2926 * interrupts (for non-MSI).
2928 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
2929 if (iir
& I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT
)
2930 i915_handle_error(dev
, false);
2932 for_each_pipe(pipe
) {
2933 int reg
= PIPESTAT(pipe
);
2934 pipe_stats
[pipe
] = I915_READ(reg
);
2937 * Clear the PIPE*STAT regs before the IIR
2939 if (pipe_stats
[pipe
] & 0x8000ffff) {
2940 if (pipe_stats
[pipe
] & PIPE_FIFO_UNDERRUN_STATUS
)
2941 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2943 I915_WRITE(reg
, pipe_stats
[pipe
]);
2947 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
2954 /* Consume port. Then clear IIR or we'll miss events */
2955 if (iir
& I915_DISPLAY_PORT_INTERRUPT
) {
2956 u32 hotplug_status
= I915_READ(PORT_HOTPLUG_STAT
);
2957 u32 hotplug_trigger
= hotplug_status
& (IS_G4X(dev
) ?
2958 HOTPLUG_INT_STATUS_G4X
:
2959 HOTPLUG_INT_STATUS_I915
);
2961 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2964 intel_hpd_irq_handler(dev
, hotplug_trigger
,
2965 IS_G4X(dev
) ? hpd_status_gen4
: hpd_status_i915
);
2967 I915_WRITE(PORT_HOTPLUG_STAT
, hotplug_status
);
2968 I915_READ(PORT_HOTPLUG_STAT
);
2971 I915_WRITE(IIR
, iir
& ~flip_mask
);
2972 new_iir
= I915_READ(IIR
); /* Flush posted writes */
2974 if (iir
& I915_USER_INTERRUPT
)
2975 notify_ring(dev
, &dev_priv
->ring
[RCS
]);
2976 if (iir
& I915_BSD_USER_INTERRUPT
)
2977 notify_ring(dev
, &dev_priv
->ring
[VCS
]);
2979 for_each_pipe(pipe
) {
2980 if (pipe_stats
[pipe
] & PIPE_START_VBLANK_INTERRUPT_STATUS
&&
2981 i915_handle_vblank(dev
, pipe
, pipe
, iir
))
2982 flip_mask
&= ~DISPLAY_PLANE_FLIP_PENDING(pipe
);
2984 if (pipe_stats
[pipe
] & PIPE_LEGACY_BLC_EVENT_STATUS
)
2989 if (blc_event
|| (iir
& I915_ASLE_INTERRUPT
))
2990 intel_opregion_asle_intr(dev
);
2992 if (pipe_stats
[0] & PIPE_GMBUS_INTERRUPT_STATUS
)
2993 gmbus_irq_handler(dev
);
2995 /* With MSI, interrupts are only generated when iir
2996 * transitions from zero to nonzero. If another bit got
2997 * set while we were handling the existing iir bits, then
2998 * we would never get another interrupt.
3000 * This is fine on non-MSI as well, as if we hit this path
3001 * we avoid exiting the interrupt handler only to generate
3004 * Note that for MSI this could cause a stray interrupt report
3005 * if an interrupt landed in the time between writing IIR and
3006 * the posting read. This should be rare enough to never
3007 * trigger the 99% of 100,000 interrupts test for disabling
3013 i915_update_dri1_breadcrumb(dev
);
3018 static void i965_irq_uninstall(struct drm_device
* dev
)
3020 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
3026 del_timer_sync(&dev_priv
->hotplug_reenable_timer
);
3028 I915_WRITE(PORT_HOTPLUG_EN
, 0);
3029 I915_WRITE(PORT_HOTPLUG_STAT
, I915_READ(PORT_HOTPLUG_STAT
));
3031 I915_WRITE(HWSTAM
, 0xffffffff);
3033 I915_WRITE(PIPESTAT(pipe
), 0);
3034 I915_WRITE(IMR
, 0xffffffff);
3035 I915_WRITE(IER
, 0x0);
3038 I915_WRITE(PIPESTAT(pipe
),
3039 I915_READ(PIPESTAT(pipe
)) & 0x8000ffff);
3040 I915_WRITE(IIR
, I915_READ(IIR
));
3043 static void i915_reenable_hotplug_timer_func(unsigned long data
)
3045 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*)data
;
3046 struct drm_device
*dev
= dev_priv
->dev
;
3047 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3048 unsigned long irqflags
;
3051 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3052 for (i
= (HPD_NONE
+ 1); i
< HPD_NUM_PINS
; i
++) {
3053 struct drm_connector
*connector
;
3055 if (dev_priv
->hpd_stats
[i
].hpd_mark
!= HPD_DISABLED
)
3058 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3060 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3061 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3063 if (intel_connector
->encoder
->hpd_pin
== i
) {
3064 if (connector
->polled
!= intel_connector
->polled
)
3065 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3066 drm_get_connector_name(connector
));
3067 connector
->polled
= intel_connector
->polled
;
3068 if (!connector
->polled
)
3069 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3073 if (dev_priv
->display
.hpd_irq_setup
)
3074 dev_priv
->display
.hpd_irq_setup(dev
);
3075 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
3078 void intel_irq_init(struct drm_device
*dev
)
3080 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3082 INIT_WORK(&dev_priv
->hotplug_work
, i915_hotplug_work_func
);
3083 INIT_WORK(&dev_priv
->gpu_error
.work
, i915_error_work_func
);
3084 INIT_WORK(&dev_priv
->rps
.work
, gen6_pm_rps_work
);
3085 INIT_WORK(&dev_priv
->l3_parity
.error_work
, ivybridge_parity_work
);
3087 setup_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
3088 i915_hangcheck_elapsed
,
3089 (unsigned long) dev
);
3090 setup_timer(&dev_priv
->hotplug_reenable_timer
, i915_reenable_hotplug_timer_func
,
3091 (unsigned long) dev_priv
);
3093 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
, PM_QOS_DEFAULT_VALUE
);
3095 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
3096 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
3097 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
3098 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
3099 dev
->driver
->get_vblank_counter
= gm45_get_vblank_counter
;
3102 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3103 dev
->driver
->get_vblank_timestamp
= i915_get_vblank_timestamp
;
3105 dev
->driver
->get_vblank_timestamp
= NULL
;
3106 dev
->driver
->get_scanout_position
= i915_get_crtc_scanoutpos
;
3108 if (IS_VALLEYVIEW(dev
)) {
3109 dev
->driver
->irq_handler
= valleyview_irq_handler
;
3110 dev
->driver
->irq_preinstall
= valleyview_irq_preinstall
;
3111 dev
->driver
->irq_postinstall
= valleyview_irq_postinstall
;
3112 dev
->driver
->irq_uninstall
= valleyview_irq_uninstall
;
3113 dev
->driver
->enable_vblank
= valleyview_enable_vblank
;
3114 dev
->driver
->disable_vblank
= valleyview_disable_vblank
;
3115 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3116 } else if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
3117 /* Share uninstall handlers with ILK/SNB */
3118 dev
->driver
->irq_handler
= ivybridge_irq_handler
;
3119 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
3120 dev
->driver
->irq_postinstall
= ivybridge_irq_postinstall
;
3121 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
3122 dev
->driver
->enable_vblank
= ivybridge_enable_vblank
;
3123 dev
->driver
->disable_vblank
= ivybridge_disable_vblank
;
3124 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
3125 } else if (HAS_PCH_SPLIT(dev
)) {
3126 dev
->driver
->irq_handler
= ironlake_irq_handler
;
3127 dev
->driver
->irq_preinstall
= ironlake_irq_preinstall
;
3128 dev
->driver
->irq_postinstall
= ironlake_irq_postinstall
;
3129 dev
->driver
->irq_uninstall
= ironlake_irq_uninstall
;
3130 dev
->driver
->enable_vblank
= ironlake_enable_vblank
;
3131 dev
->driver
->disable_vblank
= ironlake_disable_vblank
;
3132 dev_priv
->display
.hpd_irq_setup
= ibx_hpd_irq_setup
;
3134 if (INTEL_INFO(dev
)->gen
== 2) {
3135 dev
->driver
->irq_preinstall
= i8xx_irq_preinstall
;
3136 dev
->driver
->irq_postinstall
= i8xx_irq_postinstall
;
3137 dev
->driver
->irq_handler
= i8xx_irq_handler
;
3138 dev
->driver
->irq_uninstall
= i8xx_irq_uninstall
;
3139 } else if (INTEL_INFO(dev
)->gen
== 3) {
3140 dev
->driver
->irq_preinstall
= i915_irq_preinstall
;
3141 dev
->driver
->irq_postinstall
= i915_irq_postinstall
;
3142 dev
->driver
->irq_uninstall
= i915_irq_uninstall
;
3143 dev
->driver
->irq_handler
= i915_irq_handler
;
3144 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3146 dev
->driver
->irq_preinstall
= i965_irq_preinstall
;
3147 dev
->driver
->irq_postinstall
= i965_irq_postinstall
;
3148 dev
->driver
->irq_uninstall
= i965_irq_uninstall
;
3149 dev
->driver
->irq_handler
= i965_irq_handler
;
3150 dev_priv
->display
.hpd_irq_setup
= i915_hpd_irq_setup
;
3152 dev
->driver
->enable_vblank
= i915_enable_vblank
;
3153 dev
->driver
->disable_vblank
= i915_disable_vblank
;
3157 void intel_hpd_init(struct drm_device
*dev
)
3159 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3160 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3161 struct drm_connector
*connector
;
3162 unsigned long irqflags
;
3165 for (i
= 1; i
< HPD_NUM_PINS
; i
++) {
3166 dev_priv
->hpd_stats
[i
].hpd_cnt
= 0;
3167 dev_priv
->hpd_stats
[i
].hpd_mark
= HPD_ENABLED
;
3169 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
3170 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3171 connector
->polled
= intel_connector
->polled
;
3172 if (!connector
->polled
&& I915_HAS_HOTPLUG(dev
) && intel_connector
->encoder
->hpd_pin
> HPD_NONE
)
3173 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3176 /* Interrupt setup is already guaranteed to be single-threaded, this is
3177 * just to make the assert_spin_locked checks happy. */
3178 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
3179 if (dev_priv
->display
.hpd_irq_setup
)
3180 dev_priv
->display
.hpd_irq_setup(dev
);
3181 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);