1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #define MAX_NOPID ((u32)~0)
36 /** These are the interrupts used by the driver */
37 #define I915_INTERRUPT_ENABLE_MASK (I915_USER_INTERRUPT | \
38 I915_ASLE_INTERRUPT | \
39 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
40 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
43 i915_enable_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
45 if ((dev_priv
->irq_mask_reg
& mask
) != 0) {
46 dev_priv
->irq_mask_reg
&= ~mask
;
47 I915_WRITE(IMR
, dev_priv
->irq_mask_reg
);
48 (void) I915_READ(IMR
);
53 i915_disable_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
55 if ((dev_priv
->irq_mask_reg
& mask
) != mask
) {
56 dev_priv
->irq_mask_reg
|= mask
;
57 I915_WRITE(IMR
, dev_priv
->irq_mask_reg
);
58 (void) I915_READ(IMR
);
63 * i915_get_pipe - return the the pipe associated with a given plane
65 * @plane: plane to look for
67 * The Intel Mesa & 2D drivers call the vblank routines with a plane number
68 * rather than a pipe number, since they may not always be equal. This routine
69 * maps the given @plane back to a pipe number.
72 i915_get_pipe(struct drm_device
*dev
, int plane
)
74 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
77 dspcntr
= plane
? I915_READ(DSPBCNTR
) : I915_READ(DSPACNTR
);
79 return dspcntr
& DISPPLANE_SEL_PIPE_MASK
? 1 : 0;
83 * i915_get_plane - return the the plane associated with a given pipe
85 * @pipe: pipe to look for
87 * The Intel Mesa & 2D drivers call the vblank routines with a plane number
88 * rather than a plane number, since they may not always be equal. This routine
89 * maps the given @pipe back to a plane number.
92 i915_get_plane(struct drm_device
*dev
, int pipe
)
94 if (i915_get_pipe(dev
, 0) == pipe
)
100 * i915_pipe_enabled - check if a pipe is enabled
102 * @pipe: pipe to check
104 * Reading certain registers when the pipe is disabled can hang the chip.
105 * Use this routine to make sure the PLL is running and the pipe is active
106 * before reading such registers if unsure.
109 i915_pipe_enabled(struct drm_device
*dev
, int pipe
)
111 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
112 unsigned long pipeconf
= pipe
? PIPEBCONF
: PIPEACONF
;
114 if (I915_READ(pipeconf
) & PIPEACONF_ENABLE
)
121 * Emit blits for scheduled buffer swaps.
123 * This function will be called with the HW lock held.
125 static void i915_vblank_tasklet(struct drm_device
*dev
)
127 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
128 unsigned long irqflags
;
129 struct list_head
*list
, *tmp
, hits
, *hit
;
130 int nhits
, nrects
, slice
[2], upper
[2], lower
[2], i
;
132 struct drm_drawable_info
*drw
;
133 drm_i915_sarea_t
*sarea_priv
= dev_priv
->sarea_priv
;
134 u32 cpp
= dev_priv
->cpp
;
135 u32 cmd
= (cpp
== 4) ? (XY_SRC_COPY_BLT_CMD
|
136 XY_SRC_COPY_BLT_WRITE_ALPHA
|
137 XY_SRC_COPY_BLT_WRITE_RGB
)
138 : XY_SRC_COPY_BLT_CMD
;
139 u32 src_pitch
= sarea_priv
->pitch
* cpp
;
140 u32 dst_pitch
= sarea_priv
->pitch
* cpp
;
141 u32 ropcpp
= (0xcc << 16) | ((cpp
- 1) << 24);
144 if (IS_I965G(dev
) && sarea_priv
->front_tiled
) {
145 cmd
|= XY_SRC_COPY_BLT_DST_TILED
;
148 if (IS_I965G(dev
) && sarea_priv
->back_tiled
) {
149 cmd
|= XY_SRC_COPY_BLT_SRC_TILED
;
153 counter
[0] = drm_vblank_count(dev
, 0);
154 counter
[1] = drm_vblank_count(dev
, 1);
158 INIT_LIST_HEAD(&hits
);
162 spin_lock_irqsave(&dev_priv
->swaps_lock
, irqflags
);
164 /* Find buffer swaps scheduled for this vertical blank */
165 list_for_each_safe(list
, tmp
, &dev_priv
->vbl_swaps
.head
) {
166 drm_i915_vbl_swap_t
*vbl_swap
=
167 list_entry(list
, drm_i915_vbl_swap_t
, head
);
168 int pipe
= i915_get_pipe(dev
, vbl_swap
->plane
);
170 if ((counter
[pipe
] - vbl_swap
->sequence
) > (1<<23))
174 dev_priv
->swaps_pending
--;
175 drm_vblank_put(dev
, pipe
);
177 spin_unlock(&dev_priv
->swaps_lock
);
178 spin_lock(&dev
->drw_lock
);
180 drw
= drm_get_drawable_info(dev
, vbl_swap
->drw_id
);
183 spin_unlock(&dev
->drw_lock
);
184 drm_free(vbl_swap
, sizeof(*vbl_swap
), DRM_MEM_DRIVER
);
185 spin_lock(&dev_priv
->swaps_lock
);
189 list_for_each(hit
, &hits
) {
190 drm_i915_vbl_swap_t
*swap_cmp
=
191 list_entry(hit
, drm_i915_vbl_swap_t
, head
);
192 struct drm_drawable_info
*drw_cmp
=
193 drm_get_drawable_info(dev
, swap_cmp
->drw_id
);
196 drw_cmp
->rects
[0].y1
> drw
->rects
[0].y1
) {
197 list_add_tail(list
, hit
);
202 spin_unlock(&dev
->drw_lock
);
204 /* List of hits was empty, or we reached the end of it */
206 list_add_tail(list
, hits
.prev
);
210 spin_lock(&dev_priv
->swaps_lock
);
214 spin_unlock_irqrestore(&dev_priv
->swaps_lock
, irqflags
);
218 spin_unlock(&dev_priv
->swaps_lock
);
220 i915_kernel_lost_context(dev
);
225 OUT_RING(GFX_OP_DRAWRECT_INFO_I965
);
227 OUT_RING(((sarea_priv
->width
- 1) & 0xffff) | ((sarea_priv
->height
- 1) << 16));
233 OUT_RING(GFX_OP_DRAWRECT_INFO
);
236 OUT_RING(sarea_priv
->width
| sarea_priv
->height
<< 16);
237 OUT_RING(sarea_priv
->width
| sarea_priv
->height
<< 16);
243 sarea_priv
->ctxOwner
= DRM_KERNEL_CONTEXT
;
245 upper
[0] = upper
[1] = 0;
246 slice
[0] = max(sarea_priv
->pipeA_h
/ nhits
, 1);
247 slice
[1] = max(sarea_priv
->pipeB_h
/ nhits
, 1);
248 lower
[0] = sarea_priv
->pipeA_y
+ slice
[0];
249 lower
[1] = sarea_priv
->pipeB_y
+ slice
[0];
251 spin_lock(&dev
->drw_lock
);
253 /* Emit blits for buffer swaps, partitioning both outputs into as many
254 * slices as there are buffer swaps scheduled in order to avoid tearing
255 * (based on the assumption that a single buffer swap would always
256 * complete before scanout starts).
258 for (i
= 0; i
++ < nhits
;
259 upper
[0] = lower
[0], lower
[0] += slice
[0],
260 upper
[1] = lower
[1], lower
[1] += slice
[1]) {
262 lower
[0] = lower
[1] = sarea_priv
->height
;
264 list_for_each(hit
, &hits
) {
265 drm_i915_vbl_swap_t
*swap_hit
=
266 list_entry(hit
, drm_i915_vbl_swap_t
, head
);
267 struct drm_clip_rect
*rect
;
268 int num_rects
, plane
;
269 unsigned short top
, bottom
;
271 drw
= drm_get_drawable_info(dev
, swap_hit
->drw_id
);
277 plane
= swap_hit
->plane
;
279 bottom
= lower
[plane
];
281 for (num_rects
= drw
->num_rects
; num_rects
--; rect
++) {
282 int y1
= max(rect
->y1
, top
);
283 int y2
= min(rect
->y2
, bottom
);
291 OUT_RING(ropcpp
| dst_pitch
);
292 OUT_RING((y1
<< 16) | rect
->x1
);
293 OUT_RING((y2
<< 16) | rect
->x2
);
294 OUT_RING(sarea_priv
->front_offset
);
295 OUT_RING((y1
<< 16) | rect
->x1
);
297 OUT_RING(sarea_priv
->back_offset
);
304 spin_unlock_irqrestore(&dev
->drw_lock
, irqflags
);
306 list_for_each_safe(hit
, tmp
, &hits
) {
307 drm_i915_vbl_swap_t
*swap_hit
=
308 list_entry(hit
, drm_i915_vbl_swap_t
, head
);
312 drm_free(swap_hit
, sizeof(*swap_hit
), DRM_MEM_DRIVER
);
316 u32
i915_get_vblank_counter(struct drm_device
*dev
, int plane
)
318 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
319 unsigned long high_frame
;
320 unsigned long low_frame
;
321 u32 high1
, high2
, low
, count
;
324 pipe
= i915_get_pipe(dev
, plane
);
325 high_frame
= pipe
? PIPEBFRAMEHIGH
: PIPEAFRAMEHIGH
;
326 low_frame
= pipe
? PIPEBFRAMEPIXEL
: PIPEAFRAMEPIXEL
;
328 if (!i915_pipe_enabled(dev
, pipe
)) {
329 DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe
);
334 * High & low register fields aren't synchronized, so make sure
335 * we get a low value that's stable across two reads of the high
339 high1
= ((I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
) >>
340 PIPE_FRAME_HIGH_SHIFT
);
341 low
= ((I915_READ(low_frame
) & PIPE_FRAME_LOW_MASK
) >>
342 PIPE_FRAME_LOW_SHIFT
);
343 high2
= ((I915_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
) >>
344 PIPE_FRAME_HIGH_SHIFT
);
345 } while (high1
!= high2
);
347 count
= (high1
<< 8) | low
;
353 i915_gem_vblank_work_handler(struct work_struct
*work
)
355 drm_i915_private_t
*dev_priv
;
356 struct drm_device
*dev
;
358 dev_priv
= container_of(work
, drm_i915_private_t
,
362 mutex_lock(&dev
->struct_mutex
);
363 i915_vblank_tasklet(dev
);
364 mutex_unlock(&dev
->struct_mutex
);
367 irqreturn_t
i915_driver_irq_handler(DRM_IRQ_ARGS
)
369 struct drm_device
*dev
= (struct drm_device
*) arg
;
370 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
372 u32 pipea_stats
, pipeb_stats
;
375 atomic_inc(&dev_priv
->irq_received
);
377 if (dev
->pdev
->msi_enabled
)
379 iir
= I915_READ(IIR
);
382 if (dev
->pdev
->msi_enabled
) {
383 I915_WRITE(IMR
, dev_priv
->irq_mask_reg
);
384 (void) I915_READ(IMR
);
390 * Clear the PIPE(A|B)STAT regs before the IIR otherwise
391 * we may get extra interrupts.
393 if (iir
& I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
) {
394 pipea_stats
= I915_READ(PIPEASTAT
);
395 if (!(dev_priv
->vblank_pipe
& DRM_I915_VBLANK_PIPE_A
))
396 pipea_stats
&= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE
|
397 PIPE_VBLANK_INTERRUPT_ENABLE
);
398 else if (pipea_stats
& (PIPE_START_VBLANK_INTERRUPT_STATUS
|
399 PIPE_VBLANK_INTERRUPT_STATUS
)) {
401 drm_handle_vblank(dev
, i915_get_plane(dev
, 0));
404 I915_WRITE(PIPEASTAT
, pipea_stats
);
406 if (iir
& I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
) {
407 pipeb_stats
= I915_READ(PIPEBSTAT
);
409 I915_WRITE(PIPEBSTAT
, pipeb_stats
);
411 /* The vblank interrupt gets enabled even if we didn't ask for
412 it, so make sure it's shut down again */
413 if (!(dev_priv
->vblank_pipe
& DRM_I915_VBLANK_PIPE_B
))
414 pipeb_stats
&= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE
|
415 PIPE_VBLANK_INTERRUPT_ENABLE
);
416 else if (pipeb_stats
& (PIPE_START_VBLANK_INTERRUPT_STATUS
|
417 PIPE_VBLANK_INTERRUPT_STATUS
)) {
419 drm_handle_vblank(dev
, i915_get_plane(dev
, 1));
422 if (pipeb_stats
& I915_LEGACY_BLC_EVENT_STATUS
)
423 opregion_asle_intr(dev
);
424 I915_WRITE(PIPEBSTAT
, pipeb_stats
);
427 I915_WRITE(IIR
, iir
);
428 if (dev
->pdev
->msi_enabled
)
429 I915_WRITE(IMR
, dev_priv
->irq_mask_reg
);
430 (void) I915_READ(IIR
); /* Flush posted writes */
432 if (dev_priv
->sarea_priv
)
433 dev_priv
->sarea_priv
->last_dispatch
=
434 READ_BREADCRUMB(dev_priv
);
436 if (iir
& I915_USER_INTERRUPT
) {
437 dev_priv
->mm
.irq_gem_seqno
= i915_get_gem_seqno(dev
);
438 DRM_WAKEUP(&dev_priv
->irq_queue
);
441 if (iir
& I915_ASLE_INTERRUPT
)
442 opregion_asle_intr(dev
);
444 if (vblank
&& dev_priv
->swaps_pending
> 0) {
445 if (dev_priv
->ring
.ring_obj
== NULL
)
446 drm_locked_tasklet(dev
, i915_vblank_tasklet
);
448 schedule_work(&dev_priv
->mm
.vblank_work
);
454 static int i915_emit_irq(struct drm_device
* dev
)
456 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
459 i915_kernel_lost_context(dev
);
464 if (dev_priv
->counter
> 0x7FFFFFFFUL
)
465 dev_priv
->counter
= 1;
466 if (dev_priv
->sarea_priv
)
467 dev_priv
->sarea_priv
->last_enqueue
= dev_priv
->counter
;
470 OUT_RING(MI_STORE_DWORD_INDEX
);
471 OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT
);
472 OUT_RING(dev_priv
->counter
);
475 OUT_RING(MI_USER_INTERRUPT
);
478 return dev_priv
->counter
;
481 void i915_user_irq_get(struct drm_device
*dev
)
483 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
485 spin_lock(&dev_priv
->user_irq_lock
);
486 if (dev
->irq_enabled
&& (++dev_priv
->user_irq_refcount
== 1))
487 i915_enable_irq(dev_priv
, I915_USER_INTERRUPT
);
488 spin_unlock(&dev_priv
->user_irq_lock
);
491 void i915_user_irq_put(struct drm_device
*dev
)
493 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
495 spin_lock(&dev_priv
->user_irq_lock
);
496 BUG_ON(dev
->irq_enabled
&& dev_priv
->user_irq_refcount
<= 0);
497 if (dev
->irq_enabled
&& (--dev_priv
->user_irq_refcount
== 0))
498 i915_disable_irq(dev_priv
, I915_USER_INTERRUPT
);
499 spin_unlock(&dev_priv
->user_irq_lock
);
502 static int i915_wait_irq(struct drm_device
* dev
, int irq_nr
)
504 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
507 DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr
,
508 READ_BREADCRUMB(dev_priv
));
510 if (READ_BREADCRUMB(dev_priv
) >= irq_nr
) {
511 if (dev_priv
->sarea_priv
) {
512 dev_priv
->sarea_priv
->last_dispatch
=
513 READ_BREADCRUMB(dev_priv
);
518 if (dev_priv
->sarea_priv
)
519 dev_priv
->sarea_priv
->perf_boxes
|= I915_BOX_WAIT
;
521 i915_user_irq_get(dev
);
522 DRM_WAIT_ON(ret
, dev_priv
->irq_queue
, 3 * DRM_HZ
,
523 READ_BREADCRUMB(dev_priv
) >= irq_nr
);
524 i915_user_irq_put(dev
);
527 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
528 READ_BREADCRUMB(dev_priv
), (int)dev_priv
->counter
);
531 if (dev_priv
->sarea_priv
)
532 dev_priv
->sarea_priv
->last_dispatch
=
533 READ_BREADCRUMB(dev_priv
);
538 /* Needs the lock as it touches the ring.
540 int i915_irq_emit(struct drm_device
*dev
, void *data
,
541 struct drm_file
*file_priv
)
543 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
544 drm_i915_irq_emit_t
*emit
= data
;
547 RING_LOCK_TEST_WITH_RETURN(dev
, file_priv
);
550 DRM_ERROR("called with no initialization\n");
553 mutex_lock(&dev
->struct_mutex
);
554 result
= i915_emit_irq(dev
);
555 mutex_unlock(&dev
->struct_mutex
);
557 if (DRM_COPY_TO_USER(emit
->irq_seq
, &result
, sizeof(int))) {
558 DRM_ERROR("copy_to_user\n");
565 /* Doesn't need the hardware lock.
567 int i915_irq_wait(struct drm_device
*dev
, void *data
,
568 struct drm_file
*file_priv
)
570 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
571 drm_i915_irq_wait_t
*irqwait
= data
;
574 DRM_ERROR("called with no initialization\n");
578 return i915_wait_irq(dev
, irqwait
->irq_seq
);
581 int i915_enable_vblank(struct drm_device
*dev
, int plane
)
583 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
584 int pipe
= i915_get_pipe(dev
, plane
);
585 u32 pipestat_reg
= 0;
590 pipestat_reg
= PIPEASTAT
;
591 i915_enable_irq(dev_priv
, I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
);
594 pipestat_reg
= PIPEBSTAT
;
595 i915_enable_irq(dev_priv
, I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
);
598 DRM_ERROR("tried to enable vblank on non-existent pipe %d\n",
604 pipestat
= I915_READ(pipestat_reg
);
606 pipestat
|= PIPE_START_VBLANK_INTERRUPT_ENABLE
;
608 pipestat
|= PIPE_VBLANK_INTERRUPT_ENABLE
;
609 /* Clear any stale interrupt status */
610 pipestat
|= (PIPE_START_VBLANK_INTERRUPT_STATUS
|
611 PIPE_VBLANK_INTERRUPT_STATUS
);
612 I915_WRITE(pipestat_reg
, pipestat
);
618 void i915_disable_vblank(struct drm_device
*dev
, int plane
)
620 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
621 int pipe
= i915_get_pipe(dev
, plane
);
622 u32 pipestat_reg
= 0;
627 pipestat_reg
= PIPEASTAT
;
628 i915_disable_irq(dev_priv
, I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
);
631 pipestat_reg
= PIPEBSTAT
;
632 i915_disable_irq(dev_priv
, I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
);
635 DRM_ERROR("tried to disable vblank on non-existent pipe %d\n",
641 pipestat
= I915_READ(pipestat_reg
);
642 pipestat
&= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE
|
643 PIPE_VBLANK_INTERRUPT_ENABLE
);
644 /* Clear any stale interrupt status */
645 pipestat
|= (PIPE_START_VBLANK_INTERRUPT_STATUS
|
646 PIPE_VBLANK_INTERRUPT_STATUS
);
647 I915_WRITE(pipestat_reg
, pipestat
);
651 /* Set the vblank monitor pipe
653 int i915_vblank_pipe_set(struct drm_device
*dev
, void *data
,
654 struct drm_file
*file_priv
)
656 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
659 DRM_ERROR("called with no initialization\n");
666 int i915_vblank_pipe_get(struct drm_device
*dev
, void *data
,
667 struct drm_file
*file_priv
)
669 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
670 drm_i915_vblank_pipe_t
*pipe
= data
;
673 DRM_ERROR("called with no initialization\n");
677 pipe
->pipe
= DRM_I915_VBLANK_PIPE_A
| DRM_I915_VBLANK_PIPE_B
;
683 * Schedule buffer swap at given vertical blank.
685 int i915_vblank_swap(struct drm_device
*dev
, void *data
,
686 struct drm_file
*file_priv
)
688 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
689 drm_i915_vblank_swap_t
*swap
= data
;
690 drm_i915_vbl_swap_t
*vbl_swap
;
691 unsigned int pipe
, seqtype
, curseq
, plane
;
692 unsigned long irqflags
;
693 struct list_head
*list
;
696 if (!dev_priv
|| !dev_priv
->sarea_priv
) {
697 DRM_ERROR("%s called with no initialization\n", __func__
);
701 if (dev_priv
->sarea_priv
->rotation
) {
702 DRM_DEBUG("Rotation not supported\n");
706 if (swap
->seqtype
& ~(_DRM_VBLANK_RELATIVE
| _DRM_VBLANK_ABSOLUTE
|
707 _DRM_VBLANK_SECONDARY
| _DRM_VBLANK_NEXTONMISS
)) {
708 DRM_ERROR("Invalid sequence type 0x%x\n", swap
->seqtype
);
712 plane
= (swap
->seqtype
& _DRM_VBLANK_SECONDARY
) ? 1 : 0;
713 pipe
= i915_get_pipe(dev
, plane
);
715 seqtype
= swap
->seqtype
& (_DRM_VBLANK_RELATIVE
| _DRM_VBLANK_ABSOLUTE
);
717 if (!(dev_priv
->vblank_pipe
& (1 << pipe
))) {
718 DRM_ERROR("Invalid pipe %d\n", pipe
);
722 spin_lock_irqsave(&dev
->drw_lock
, irqflags
);
724 if (!drm_get_drawable_info(dev
, swap
->drawable
)) {
725 spin_unlock_irqrestore(&dev
->drw_lock
, irqflags
);
726 DRM_DEBUG("Invalid drawable ID %d\n", swap
->drawable
);
730 spin_unlock_irqrestore(&dev
->drw_lock
, irqflags
);
733 * We take the ref here and put it when the swap actually completes
736 ret
= drm_vblank_get(dev
, pipe
);
739 curseq
= drm_vblank_count(dev
, pipe
);
741 if (seqtype
== _DRM_VBLANK_RELATIVE
)
742 swap
->sequence
+= curseq
;
744 if ((curseq
- swap
->sequence
) <= (1<<23)) {
745 if (swap
->seqtype
& _DRM_VBLANK_NEXTONMISS
) {
746 swap
->sequence
= curseq
+ 1;
748 DRM_DEBUG("Missed target sequence\n");
749 drm_vblank_put(dev
, pipe
);
754 spin_lock_irqsave(&dev_priv
->swaps_lock
, irqflags
);
756 list_for_each(list
, &dev_priv
->vbl_swaps
.head
) {
757 vbl_swap
= list_entry(list
, drm_i915_vbl_swap_t
, head
);
759 if (vbl_swap
->drw_id
== swap
->drawable
&&
760 vbl_swap
->plane
== plane
&&
761 vbl_swap
->sequence
== swap
->sequence
) {
762 spin_unlock_irqrestore(&dev_priv
->swaps_lock
, irqflags
);
763 DRM_DEBUG("Already scheduled\n");
768 spin_unlock_irqrestore(&dev_priv
->swaps_lock
, irqflags
);
770 if (dev_priv
->swaps_pending
>= 100) {
771 DRM_DEBUG("Too many swaps queued\n");
772 drm_vblank_put(dev
, pipe
);
776 vbl_swap
= drm_calloc(1, sizeof(*vbl_swap
), DRM_MEM_DRIVER
);
779 DRM_ERROR("Failed to allocate memory to queue swap\n");
780 drm_vblank_put(dev
, pipe
);
786 vbl_swap
->drw_id
= swap
->drawable
;
787 vbl_swap
->plane
= plane
;
788 vbl_swap
->sequence
= swap
->sequence
;
790 spin_lock_irqsave(&dev_priv
->swaps_lock
, irqflags
);
792 list_add_tail(&vbl_swap
->head
, &dev_priv
->vbl_swaps
.head
);
793 dev_priv
->swaps_pending
++;
795 spin_unlock_irqrestore(&dev_priv
->swaps_lock
, irqflags
);
802 void i915_driver_irq_preinstall(struct drm_device
* dev
)
804 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
806 I915_WRITE(HWSTAM
, 0xeffe);
807 I915_WRITE(IMR
, 0xffffffff);
808 I915_WRITE(IER
, 0x0);
811 int i915_driver_irq_postinstall(struct drm_device
*dev
)
813 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
814 int ret
, num_pipes
= 2;
816 spin_lock_init(&dev_priv
->swaps_lock
);
817 INIT_LIST_HEAD(&dev_priv
->vbl_swaps
.head
);
818 dev_priv
->swaps_pending
= 0;
820 /* Set initial unmasked IRQs to just the selected vblank pipes. */
821 dev_priv
->irq_mask_reg
= ~0;
823 ret
= drm_vblank_init(dev
, num_pipes
);
827 dev_priv
->vblank_pipe
= DRM_I915_VBLANK_PIPE_A
| DRM_I915_VBLANK_PIPE_B
;
828 dev_priv
->irq_mask_reg
&= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
;
829 dev_priv
->irq_mask_reg
&= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
;
831 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
833 dev_priv
->irq_mask_reg
&= I915_INTERRUPT_ENABLE_MASK
;
835 I915_WRITE(IMR
, dev_priv
->irq_mask_reg
);
836 I915_WRITE(IER
, I915_INTERRUPT_ENABLE_MASK
);
837 (void) I915_READ(IER
);
839 opregion_enable_asle(dev
);
840 DRM_INIT_WAITQUEUE(&dev_priv
->irq_queue
);
845 void i915_driver_irq_uninstall(struct drm_device
* dev
)
847 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
853 dev_priv
->vblank_pipe
= 0;
855 I915_WRITE(HWSTAM
, 0xffffffff);
856 I915_WRITE(IMR
, 0xffffffff);
857 I915_WRITE(IER
, 0x0);
859 temp
= I915_READ(PIPEASTAT
);
860 I915_WRITE(PIPEASTAT
, temp
);
861 temp
= I915_READ(PIPEBSTAT
);
862 I915_WRITE(PIPEBSTAT
, temp
);
863 temp
= I915_READ(IIR
);
864 I915_WRITE(IIR
, temp
);