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drm/i915: Use dev_priv in public intel_fifo_underrun.c functions
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
34 #include <drm/drmP.h>
35 #include <drm/i915_drm.h>
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "intel_drv.h"
39
40 /**
41 * DOC: interrupt handling
42 *
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
46 */
47
48 static const u32 hpd_ibx[] = {
49 [HPD_CRT] = SDE_CRT_HOTPLUG,
50 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
51 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
52 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
53 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
54 };
55
56 static const u32 hpd_cpt[] = {
57 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
58 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
59 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
60 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
61 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
62 };
63
64 static const u32 hpd_mask_i915[] = {
65 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
66 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
67 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
68 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
69 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
70 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
71 };
72
73 static const u32 hpd_status_g4x[] = {
74 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
75 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
76 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
77 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
78 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
79 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
80 };
81
82 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
83 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
84 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
85 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
86 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
87 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
88 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
89 };
90
91 /* IIR can theoretically queue up two events. Be paranoid. */
92 #define GEN8_IRQ_RESET_NDX(type, which) do { \
93 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
94 POSTING_READ(GEN8_##type##_IMR(which)); \
95 I915_WRITE(GEN8_##type##_IER(which), 0); \
96 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
97 POSTING_READ(GEN8_##type##_IIR(which)); \
98 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
99 POSTING_READ(GEN8_##type##_IIR(which)); \
100 } while (0)
101
102 #define GEN5_IRQ_RESET(type) do { \
103 I915_WRITE(type##IMR, 0xffffffff); \
104 POSTING_READ(type##IMR); \
105 I915_WRITE(type##IER, 0); \
106 I915_WRITE(type##IIR, 0xffffffff); \
107 POSTING_READ(type##IIR); \
108 I915_WRITE(type##IIR, 0xffffffff); \
109 POSTING_READ(type##IIR); \
110 } while (0)
111
112 /*
113 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
114 */
115 #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
116 u32 val = I915_READ(reg); \
117 if (val) { \
118 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
119 (reg), val); \
120 I915_WRITE((reg), 0xffffffff); \
121 POSTING_READ(reg); \
122 I915_WRITE((reg), 0xffffffff); \
123 POSTING_READ(reg); \
124 } \
125 } while (0)
126
127 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
128 GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
129 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
130 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
131 POSTING_READ(GEN8_##type##_IER(which)); \
132 } while (0)
133
134 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
135 GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
136 I915_WRITE(type##IMR, (imr_val)); \
137 I915_WRITE(type##IER, (ier_val)); \
138 POSTING_READ(type##IER); \
139 } while (0)
140
141 /* For display hotplug interrupt */
142 void
143 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
144 {
145 assert_spin_locked(&dev_priv->irq_lock);
146
147 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
148 return;
149
150 if ((dev_priv->irq_mask & mask) != 0) {
151 dev_priv->irq_mask &= ~mask;
152 I915_WRITE(DEIMR, dev_priv->irq_mask);
153 POSTING_READ(DEIMR);
154 }
155 }
156
157 void
158 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
159 {
160 assert_spin_locked(&dev_priv->irq_lock);
161
162 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
163 return;
164
165 if ((dev_priv->irq_mask & mask) != mask) {
166 dev_priv->irq_mask |= mask;
167 I915_WRITE(DEIMR, dev_priv->irq_mask);
168 POSTING_READ(DEIMR);
169 }
170 }
171
172 /**
173 * ilk_update_gt_irq - update GTIMR
174 * @dev_priv: driver private
175 * @interrupt_mask: mask of interrupt bits to update
176 * @enabled_irq_mask: mask of interrupt bits to enable
177 */
178 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
179 uint32_t interrupt_mask,
180 uint32_t enabled_irq_mask)
181 {
182 assert_spin_locked(&dev_priv->irq_lock);
183
184 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
185 return;
186
187 dev_priv->gt_irq_mask &= ~interrupt_mask;
188 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
189 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
190 POSTING_READ(GTIMR);
191 }
192
193 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
194 {
195 ilk_update_gt_irq(dev_priv, mask, mask);
196 }
197
198 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
199 {
200 ilk_update_gt_irq(dev_priv, mask, 0);
201 }
202
203 /**
204 * snb_update_pm_irq - update GEN6_PMIMR
205 * @dev_priv: driver private
206 * @interrupt_mask: mask of interrupt bits to update
207 * @enabled_irq_mask: mask of interrupt bits to enable
208 */
209 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
210 uint32_t interrupt_mask,
211 uint32_t enabled_irq_mask)
212 {
213 uint32_t new_val;
214
215 assert_spin_locked(&dev_priv->irq_lock);
216
217 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
218 return;
219
220 new_val = dev_priv->pm_irq_mask;
221 new_val &= ~interrupt_mask;
222 new_val |= (~enabled_irq_mask & interrupt_mask);
223
224 if (new_val != dev_priv->pm_irq_mask) {
225 dev_priv->pm_irq_mask = new_val;
226 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
227 POSTING_READ(GEN6_PMIMR);
228 }
229 }
230
231 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
232 {
233 snb_update_pm_irq(dev_priv, mask, mask);
234 }
235
236 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
237 {
238 snb_update_pm_irq(dev_priv, mask, 0);
239 }
240
241 /**
242 * bdw_update_pm_irq - update GT interrupt 2
243 * @dev_priv: driver private
244 * @interrupt_mask: mask of interrupt bits to update
245 * @enabled_irq_mask: mask of interrupt bits to enable
246 *
247 * Copied from the snb function, updated with relevant register offsets
248 */
249 static void bdw_update_pm_irq(struct drm_i915_private *dev_priv,
250 uint32_t interrupt_mask,
251 uint32_t enabled_irq_mask)
252 {
253 uint32_t new_val;
254
255 assert_spin_locked(&dev_priv->irq_lock);
256
257 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
258 return;
259
260 new_val = dev_priv->pm_irq_mask;
261 new_val &= ~interrupt_mask;
262 new_val |= (~enabled_irq_mask & interrupt_mask);
263
264 if (new_val != dev_priv->pm_irq_mask) {
265 dev_priv->pm_irq_mask = new_val;
266 I915_WRITE(GEN8_GT_IMR(2), dev_priv->pm_irq_mask);
267 POSTING_READ(GEN8_GT_IMR(2));
268 }
269 }
270
271 void gen8_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
272 {
273 bdw_update_pm_irq(dev_priv, mask, mask);
274 }
275
276 void gen8_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
277 {
278 bdw_update_pm_irq(dev_priv, mask, 0);
279 }
280
281 /**
282 * ibx_display_interrupt_update - update SDEIMR
283 * @dev_priv: driver private
284 * @interrupt_mask: mask of interrupt bits to update
285 * @enabled_irq_mask: mask of interrupt bits to enable
286 */
287 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
288 uint32_t interrupt_mask,
289 uint32_t enabled_irq_mask)
290 {
291 uint32_t sdeimr = I915_READ(SDEIMR);
292 sdeimr &= ~interrupt_mask;
293 sdeimr |= (~enabled_irq_mask & interrupt_mask);
294
295 assert_spin_locked(&dev_priv->irq_lock);
296
297 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
298 return;
299
300 I915_WRITE(SDEIMR, sdeimr);
301 POSTING_READ(SDEIMR);
302 }
303
304 static void
305 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
306 u32 enable_mask, u32 status_mask)
307 {
308 u32 reg = PIPESTAT(pipe);
309 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
310
311 assert_spin_locked(&dev_priv->irq_lock);
312 WARN_ON(!intel_irqs_enabled(dev_priv));
313
314 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
315 status_mask & ~PIPESTAT_INT_STATUS_MASK,
316 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
317 pipe_name(pipe), enable_mask, status_mask))
318 return;
319
320 if ((pipestat & enable_mask) == enable_mask)
321 return;
322
323 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
324
325 /* Enable the interrupt, clear any pending status */
326 pipestat |= enable_mask | status_mask;
327 I915_WRITE(reg, pipestat);
328 POSTING_READ(reg);
329 }
330
331 static void
332 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
333 u32 enable_mask, u32 status_mask)
334 {
335 u32 reg = PIPESTAT(pipe);
336 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
337
338 assert_spin_locked(&dev_priv->irq_lock);
339 WARN_ON(!intel_irqs_enabled(dev_priv));
340
341 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
342 status_mask & ~PIPESTAT_INT_STATUS_MASK,
343 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
344 pipe_name(pipe), enable_mask, status_mask))
345 return;
346
347 if ((pipestat & enable_mask) == 0)
348 return;
349
350 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
351
352 pipestat &= ~enable_mask;
353 I915_WRITE(reg, pipestat);
354 POSTING_READ(reg);
355 }
356
357 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
358 {
359 u32 enable_mask = status_mask << 16;
360
361 /*
362 * On pipe A we don't support the PSR interrupt yet,
363 * on pipe B and C the same bit MBZ.
364 */
365 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
366 return 0;
367 /*
368 * On pipe B and C we don't support the PSR interrupt yet, on pipe
369 * A the same bit is for perf counters which we don't use either.
370 */
371 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
372 return 0;
373
374 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
375 SPRITE0_FLIP_DONE_INT_EN_VLV |
376 SPRITE1_FLIP_DONE_INT_EN_VLV);
377 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
378 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
379 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
380 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
381
382 return enable_mask;
383 }
384
385 void
386 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
387 u32 status_mask)
388 {
389 u32 enable_mask;
390
391 if (IS_VALLEYVIEW(dev_priv->dev))
392 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
393 status_mask);
394 else
395 enable_mask = status_mask << 16;
396 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
397 }
398
399 void
400 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
401 u32 status_mask)
402 {
403 u32 enable_mask;
404
405 if (IS_VALLEYVIEW(dev_priv->dev))
406 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
407 status_mask);
408 else
409 enable_mask = status_mask << 16;
410 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
411 }
412
413 /**
414 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
415 */
416 static void i915_enable_asle_pipestat(struct drm_device *dev)
417 {
418 struct drm_i915_private *dev_priv = dev->dev_private;
419
420 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
421 return;
422
423 spin_lock_irq(&dev_priv->irq_lock);
424
425 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
426 if (INTEL_INFO(dev)->gen >= 4)
427 i915_enable_pipestat(dev_priv, PIPE_A,
428 PIPE_LEGACY_BLC_EVENT_STATUS);
429
430 spin_unlock_irq(&dev_priv->irq_lock);
431 }
432
433 /**
434 * i915_pipe_enabled - check if a pipe is enabled
435 * @dev: DRM device
436 * @pipe: pipe to check
437 *
438 * Reading certain registers when the pipe is disabled can hang the chip.
439 * Use this routine to make sure the PLL is running and the pipe is active
440 * before reading such registers if unsure.
441 */
442 static int
443 i915_pipe_enabled(struct drm_device *dev, int pipe)
444 {
445 struct drm_i915_private *dev_priv = dev->dev_private;
446
447 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
448 /* Locking is horribly broken here, but whatever. */
449 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
450 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
451
452 return intel_crtc->active;
453 } else {
454 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
455 }
456 }
457
458 /*
459 * This timing diagram depicts the video signal in and
460 * around the vertical blanking period.
461 *
462 * Assumptions about the fictitious mode used in this example:
463 * vblank_start >= 3
464 * vsync_start = vblank_start + 1
465 * vsync_end = vblank_start + 2
466 * vtotal = vblank_start + 3
467 *
468 * start of vblank:
469 * latch double buffered registers
470 * increment frame counter (ctg+)
471 * generate start of vblank interrupt (gen4+)
472 * |
473 * | frame start:
474 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
475 * | may be shifted forward 1-3 extra lines via PIPECONF
476 * | |
477 * | | start of vsync:
478 * | | generate vsync interrupt
479 * | | |
480 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
481 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
482 * ----va---> <-----------------vb--------------------> <--------va-------------
483 * | | <----vs-----> |
484 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
485 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
486 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
487 * | | |
488 * last visible pixel first visible pixel
489 * | increment frame counter (gen3/4)
490 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
491 *
492 * x = horizontal active
493 * _ = horizontal blanking
494 * hs = horizontal sync
495 * va = vertical active
496 * vb = vertical blanking
497 * vs = vertical sync
498 * vbs = vblank_start (number)
499 *
500 * Summary:
501 * - most events happen at the start of horizontal sync
502 * - frame start happens at the start of horizontal blank, 1-4 lines
503 * (depending on PIPECONF settings) after the start of vblank
504 * - gen3/4 pixel and frame counter are synchronized with the start
505 * of horizontal active on the first line of vertical active
506 */
507
508 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
509 {
510 /* Gen2 doesn't have a hardware frame counter */
511 return 0;
512 }
513
514 /* Called from drm generic code, passed a 'crtc', which
515 * we use as a pipe index
516 */
517 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
518 {
519 struct drm_i915_private *dev_priv = dev->dev_private;
520 unsigned long high_frame;
521 unsigned long low_frame;
522 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
523
524 if (!i915_pipe_enabled(dev, pipe)) {
525 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
526 "pipe %c\n", pipe_name(pipe));
527 return 0;
528 }
529
530 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
531 struct intel_crtc *intel_crtc =
532 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
533 const struct drm_display_mode *mode =
534 &intel_crtc->config.adjusted_mode;
535
536 htotal = mode->crtc_htotal;
537 hsync_start = mode->crtc_hsync_start;
538 vbl_start = mode->crtc_vblank_start;
539 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
540 vbl_start = DIV_ROUND_UP(vbl_start, 2);
541 } else {
542 enum transcoder cpu_transcoder = (enum transcoder) pipe;
543
544 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
545 hsync_start = (I915_READ(HSYNC(cpu_transcoder)) & 0x1fff) + 1;
546 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
547 if ((I915_READ(PIPECONF(cpu_transcoder)) &
548 PIPECONF_INTERLACE_MASK) != PIPECONF_PROGRESSIVE)
549 vbl_start = DIV_ROUND_UP(vbl_start, 2);
550 }
551
552 /* Convert to pixel count */
553 vbl_start *= htotal;
554
555 /* Start of vblank event occurs at start of hsync */
556 vbl_start -= htotal - hsync_start;
557
558 high_frame = PIPEFRAME(pipe);
559 low_frame = PIPEFRAMEPIXEL(pipe);
560
561 /*
562 * High & low register fields aren't synchronized, so make sure
563 * we get a low value that's stable across two reads of the high
564 * register.
565 */
566 do {
567 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
568 low = I915_READ(low_frame);
569 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
570 } while (high1 != high2);
571
572 high1 >>= PIPE_FRAME_HIGH_SHIFT;
573 pixel = low & PIPE_PIXEL_MASK;
574 low >>= PIPE_FRAME_LOW_SHIFT;
575
576 /*
577 * The frame counter increments at beginning of active.
578 * Cook up a vblank counter by also checking the pixel
579 * counter against vblank start.
580 */
581 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
582 }
583
584 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
585 {
586 struct drm_i915_private *dev_priv = dev->dev_private;
587 int reg = PIPE_FRMCOUNT_GM45(pipe);
588
589 if (!i915_pipe_enabled(dev, pipe)) {
590 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
591 "pipe %c\n", pipe_name(pipe));
592 return 0;
593 }
594
595 return I915_READ(reg);
596 }
597
598 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
599 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
600
601 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
602 {
603 struct drm_device *dev = crtc->base.dev;
604 struct drm_i915_private *dev_priv = dev->dev_private;
605 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
606 enum pipe pipe = crtc->pipe;
607 int position, vtotal;
608
609 vtotal = mode->crtc_vtotal;
610 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
611 vtotal /= 2;
612
613 if (IS_GEN2(dev))
614 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
615 else
616 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
617
618 /*
619 * See update_scanline_offset() for the details on the
620 * scanline_offset adjustment.
621 */
622 return (position + crtc->scanline_offset) % vtotal;
623 }
624
625 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
626 unsigned int flags, int *vpos, int *hpos,
627 ktime_t *stime, ktime_t *etime)
628 {
629 struct drm_i915_private *dev_priv = dev->dev_private;
630 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
631 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
632 const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
633 int position;
634 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
635 bool in_vbl = true;
636 int ret = 0;
637 unsigned long irqflags;
638
639 if (!intel_crtc->active) {
640 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
641 "pipe %c\n", pipe_name(pipe));
642 return 0;
643 }
644
645 htotal = mode->crtc_htotal;
646 hsync_start = mode->crtc_hsync_start;
647 vtotal = mode->crtc_vtotal;
648 vbl_start = mode->crtc_vblank_start;
649 vbl_end = mode->crtc_vblank_end;
650
651 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
652 vbl_start = DIV_ROUND_UP(vbl_start, 2);
653 vbl_end /= 2;
654 vtotal /= 2;
655 }
656
657 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
658
659 /*
660 * Lock uncore.lock, as we will do multiple timing critical raw
661 * register reads, potentially with preemption disabled, so the
662 * following code must not block on uncore.lock.
663 */
664 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
665
666 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
667
668 /* Get optional system timestamp before query. */
669 if (stime)
670 *stime = ktime_get();
671
672 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
673 /* No obvious pixelcount register. Only query vertical
674 * scanout position from Display scan line register.
675 */
676 position = __intel_get_crtc_scanline(intel_crtc);
677 } else {
678 /* Have access to pixelcount since start of frame.
679 * We can split this into vertical and horizontal
680 * scanout position.
681 */
682 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
683
684 /* convert to pixel counts */
685 vbl_start *= htotal;
686 vbl_end *= htotal;
687 vtotal *= htotal;
688
689 /*
690 * In interlaced modes, the pixel counter counts all pixels,
691 * so one field will have htotal more pixels. In order to avoid
692 * the reported position from jumping backwards when the pixel
693 * counter is beyond the length of the shorter field, just
694 * clamp the position the length of the shorter field. This
695 * matches how the scanline counter based position works since
696 * the scanline counter doesn't count the two half lines.
697 */
698 if (position >= vtotal)
699 position = vtotal - 1;
700
701 /*
702 * Start of vblank interrupt is triggered at start of hsync,
703 * just prior to the first active line of vblank. However we
704 * consider lines to start at the leading edge of horizontal
705 * active. So, should we get here before we've crossed into
706 * the horizontal active of the first line in vblank, we would
707 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
708 * always add htotal-hsync_start to the current pixel position.
709 */
710 position = (position + htotal - hsync_start) % vtotal;
711 }
712
713 /* Get optional system timestamp after query. */
714 if (etime)
715 *etime = ktime_get();
716
717 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
718
719 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
720
721 in_vbl = position >= vbl_start && position < vbl_end;
722
723 /*
724 * While in vblank, position will be negative
725 * counting up towards 0 at vbl_end. And outside
726 * vblank, position will be positive counting
727 * up since vbl_end.
728 */
729 if (position >= vbl_start)
730 position -= vbl_end;
731 else
732 position += vtotal - vbl_end;
733
734 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
735 *vpos = position;
736 *hpos = 0;
737 } else {
738 *vpos = position / htotal;
739 *hpos = position - (*vpos * htotal);
740 }
741
742 /* In vblank? */
743 if (in_vbl)
744 ret |= DRM_SCANOUTPOS_IN_VBLANK;
745
746 return ret;
747 }
748
749 int intel_get_crtc_scanline(struct intel_crtc *crtc)
750 {
751 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
752 unsigned long irqflags;
753 int position;
754
755 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
756 position = __intel_get_crtc_scanline(crtc);
757 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
758
759 return position;
760 }
761
762 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
763 int *max_error,
764 struct timeval *vblank_time,
765 unsigned flags)
766 {
767 struct drm_crtc *crtc;
768
769 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
770 DRM_ERROR("Invalid crtc %d\n", pipe);
771 return -EINVAL;
772 }
773
774 /* Get drm_crtc to timestamp: */
775 crtc = intel_get_crtc_for_pipe(dev, pipe);
776 if (crtc == NULL) {
777 DRM_ERROR("Invalid crtc %d\n", pipe);
778 return -EINVAL;
779 }
780
781 if (!crtc->enabled) {
782 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
783 return -EBUSY;
784 }
785
786 /* Helper routine in DRM core does all the work: */
787 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
788 vblank_time, flags,
789 crtc,
790 &to_intel_crtc(crtc)->config.adjusted_mode);
791 }
792
793 static bool intel_hpd_irq_event(struct drm_device *dev,
794 struct drm_connector *connector)
795 {
796 enum drm_connector_status old_status;
797
798 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
799 old_status = connector->status;
800
801 connector->status = connector->funcs->detect(connector, false);
802 if (old_status == connector->status)
803 return false;
804
805 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
806 connector->base.id,
807 connector->name,
808 drm_get_connector_status_name(old_status),
809 drm_get_connector_status_name(connector->status));
810
811 return true;
812 }
813
814 static void i915_digport_work_func(struct work_struct *work)
815 {
816 struct drm_i915_private *dev_priv =
817 container_of(work, struct drm_i915_private, dig_port_work);
818 u32 long_port_mask, short_port_mask;
819 struct intel_digital_port *intel_dig_port;
820 int i, ret;
821 u32 old_bits = 0;
822
823 spin_lock_irq(&dev_priv->irq_lock);
824 long_port_mask = dev_priv->long_hpd_port_mask;
825 dev_priv->long_hpd_port_mask = 0;
826 short_port_mask = dev_priv->short_hpd_port_mask;
827 dev_priv->short_hpd_port_mask = 0;
828 spin_unlock_irq(&dev_priv->irq_lock);
829
830 for (i = 0; i < I915_MAX_PORTS; i++) {
831 bool valid = false;
832 bool long_hpd = false;
833 intel_dig_port = dev_priv->hpd_irq_port[i];
834 if (!intel_dig_port || !intel_dig_port->hpd_pulse)
835 continue;
836
837 if (long_port_mask & (1 << i)) {
838 valid = true;
839 long_hpd = true;
840 } else if (short_port_mask & (1 << i))
841 valid = true;
842
843 if (valid) {
844 ret = intel_dig_port->hpd_pulse(intel_dig_port, long_hpd);
845 if (ret == true) {
846 /* if we get true fallback to old school hpd */
847 old_bits |= (1 << intel_dig_port->base.hpd_pin);
848 }
849 }
850 }
851
852 if (old_bits) {
853 spin_lock_irq(&dev_priv->irq_lock);
854 dev_priv->hpd_event_bits |= old_bits;
855 spin_unlock_irq(&dev_priv->irq_lock);
856 schedule_work(&dev_priv->hotplug_work);
857 }
858 }
859
860 /*
861 * Handle hotplug events outside the interrupt handler proper.
862 */
863 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
864
865 static void i915_hotplug_work_func(struct work_struct *work)
866 {
867 struct drm_i915_private *dev_priv =
868 container_of(work, struct drm_i915_private, hotplug_work);
869 struct drm_device *dev = dev_priv->dev;
870 struct drm_mode_config *mode_config = &dev->mode_config;
871 struct intel_connector *intel_connector;
872 struct intel_encoder *intel_encoder;
873 struct drm_connector *connector;
874 bool hpd_disabled = false;
875 bool changed = false;
876 u32 hpd_event_bits;
877
878 mutex_lock(&mode_config->mutex);
879 DRM_DEBUG_KMS("running encoder hotplug functions\n");
880
881 spin_lock_irq(&dev_priv->irq_lock);
882
883 hpd_event_bits = dev_priv->hpd_event_bits;
884 dev_priv->hpd_event_bits = 0;
885 list_for_each_entry(connector, &mode_config->connector_list, head) {
886 intel_connector = to_intel_connector(connector);
887 if (!intel_connector->encoder)
888 continue;
889 intel_encoder = intel_connector->encoder;
890 if (intel_encoder->hpd_pin > HPD_NONE &&
891 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
892 connector->polled == DRM_CONNECTOR_POLL_HPD) {
893 DRM_INFO("HPD interrupt storm detected on connector %s: "
894 "switching from hotplug detection to polling\n",
895 connector->name);
896 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
897 connector->polled = DRM_CONNECTOR_POLL_CONNECT
898 | DRM_CONNECTOR_POLL_DISCONNECT;
899 hpd_disabled = true;
900 }
901 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
902 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
903 connector->name, intel_encoder->hpd_pin);
904 }
905 }
906 /* if there were no outputs to poll, poll was disabled,
907 * therefore make sure it's enabled when disabling HPD on
908 * some connectors */
909 if (hpd_disabled) {
910 drm_kms_helper_poll_enable(dev);
911 mod_delayed_work(system_wq, &dev_priv->hotplug_reenable_work,
912 msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
913 }
914
915 spin_unlock_irq(&dev_priv->irq_lock);
916
917 list_for_each_entry(connector, &mode_config->connector_list, head) {
918 intel_connector = to_intel_connector(connector);
919 if (!intel_connector->encoder)
920 continue;
921 intel_encoder = intel_connector->encoder;
922 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
923 if (intel_encoder->hot_plug)
924 intel_encoder->hot_plug(intel_encoder);
925 if (intel_hpd_irq_event(dev, connector))
926 changed = true;
927 }
928 }
929 mutex_unlock(&mode_config->mutex);
930
931 if (changed)
932 drm_kms_helper_hotplug_event(dev);
933 }
934
935 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
936 {
937 struct drm_i915_private *dev_priv = dev->dev_private;
938 u32 busy_up, busy_down, max_avg, min_avg;
939 u8 new_delay;
940
941 spin_lock(&mchdev_lock);
942
943 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
944
945 new_delay = dev_priv->ips.cur_delay;
946
947 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
948 busy_up = I915_READ(RCPREVBSYTUPAVG);
949 busy_down = I915_READ(RCPREVBSYTDNAVG);
950 max_avg = I915_READ(RCBMAXAVG);
951 min_avg = I915_READ(RCBMINAVG);
952
953 /* Handle RCS change request from hw */
954 if (busy_up > max_avg) {
955 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
956 new_delay = dev_priv->ips.cur_delay - 1;
957 if (new_delay < dev_priv->ips.max_delay)
958 new_delay = dev_priv->ips.max_delay;
959 } else if (busy_down < min_avg) {
960 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
961 new_delay = dev_priv->ips.cur_delay + 1;
962 if (new_delay > dev_priv->ips.min_delay)
963 new_delay = dev_priv->ips.min_delay;
964 }
965
966 if (ironlake_set_drps(dev, new_delay))
967 dev_priv->ips.cur_delay = new_delay;
968
969 spin_unlock(&mchdev_lock);
970
971 return;
972 }
973
974 static void notify_ring(struct drm_device *dev,
975 struct intel_engine_cs *ring)
976 {
977 if (!intel_ring_initialized(ring))
978 return;
979
980 trace_i915_gem_request_complete(ring);
981
982 if (drm_core_check_feature(dev, DRIVER_MODESET))
983 intel_notify_mmio_flip(ring);
984
985 wake_up_all(&ring->irq_queue);
986 i915_queue_hangcheck(dev);
987 }
988
989 static u32 vlv_c0_residency(struct drm_i915_private *dev_priv,
990 struct intel_rps_ei *rps_ei)
991 {
992 u32 cz_ts, cz_freq_khz;
993 u32 render_count, media_count;
994 u32 elapsed_render, elapsed_media, elapsed_time;
995 u32 residency = 0;
996
997 cz_ts = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
998 cz_freq_khz = DIV_ROUND_CLOSEST(dev_priv->mem_freq * 1000, 4);
999
1000 render_count = I915_READ(VLV_RENDER_C0_COUNT_REG);
1001 media_count = I915_READ(VLV_MEDIA_C0_COUNT_REG);
1002
1003 if (rps_ei->cz_clock == 0) {
1004 rps_ei->cz_clock = cz_ts;
1005 rps_ei->render_c0 = render_count;
1006 rps_ei->media_c0 = media_count;
1007
1008 return dev_priv->rps.cur_freq;
1009 }
1010
1011 elapsed_time = cz_ts - rps_ei->cz_clock;
1012 rps_ei->cz_clock = cz_ts;
1013
1014 elapsed_render = render_count - rps_ei->render_c0;
1015 rps_ei->render_c0 = render_count;
1016
1017 elapsed_media = media_count - rps_ei->media_c0;
1018 rps_ei->media_c0 = media_count;
1019
1020 /* Convert all the counters into common unit of milli sec */
1021 elapsed_time /= VLV_CZ_CLOCK_TO_MILLI_SEC;
1022 elapsed_render /= cz_freq_khz;
1023 elapsed_media /= cz_freq_khz;
1024
1025 /*
1026 * Calculate overall C0 residency percentage
1027 * only if elapsed time is non zero
1028 */
1029 if (elapsed_time) {
1030 residency =
1031 ((max(elapsed_render, elapsed_media) * 100)
1032 / elapsed_time);
1033 }
1034
1035 return residency;
1036 }
1037
1038 /**
1039 * vlv_calc_delay_from_C0_counters - Increase/Decrease freq based on GPU
1040 * busy-ness calculated from C0 counters of render & media power wells
1041 * @dev_priv: DRM device private
1042 *
1043 */
1044 static int vlv_calc_delay_from_C0_counters(struct drm_i915_private *dev_priv)
1045 {
1046 u32 residency_C0_up = 0, residency_C0_down = 0;
1047 int new_delay, adj;
1048
1049 dev_priv->rps.ei_interrupt_count++;
1050
1051 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
1052
1053
1054 if (dev_priv->rps.up_ei.cz_clock == 0) {
1055 vlv_c0_residency(dev_priv, &dev_priv->rps.up_ei);
1056 vlv_c0_residency(dev_priv, &dev_priv->rps.down_ei);
1057 return dev_priv->rps.cur_freq;
1058 }
1059
1060
1061 /*
1062 * To down throttle, C0 residency should be less than down threshold
1063 * for continous EI intervals. So calculate down EI counters
1064 * once in VLV_INT_COUNT_FOR_DOWN_EI
1065 */
1066 if (dev_priv->rps.ei_interrupt_count == VLV_INT_COUNT_FOR_DOWN_EI) {
1067
1068 dev_priv->rps.ei_interrupt_count = 0;
1069
1070 residency_C0_down = vlv_c0_residency(dev_priv,
1071 &dev_priv->rps.down_ei);
1072 } else {
1073 residency_C0_up = vlv_c0_residency(dev_priv,
1074 &dev_priv->rps.up_ei);
1075 }
1076
1077 new_delay = dev_priv->rps.cur_freq;
1078
1079 adj = dev_priv->rps.last_adj;
1080 /* C0 residency is greater than UP threshold. Increase Frequency */
1081 if (residency_C0_up >= VLV_RP_UP_EI_THRESHOLD) {
1082 if (adj > 0)
1083 adj *= 2;
1084 else
1085 adj = 1;
1086
1087 if (dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit)
1088 new_delay = dev_priv->rps.cur_freq + adj;
1089
1090 /*
1091 * For better performance, jump directly
1092 * to RPe if we're below it.
1093 */
1094 if (new_delay < dev_priv->rps.efficient_freq)
1095 new_delay = dev_priv->rps.efficient_freq;
1096
1097 } else if (!dev_priv->rps.ei_interrupt_count &&
1098 (residency_C0_down < VLV_RP_DOWN_EI_THRESHOLD)) {
1099 if (adj < 0)
1100 adj *= 2;
1101 else
1102 adj = -1;
1103 /*
1104 * This means, C0 residency is less than down threshold over
1105 * a period of VLV_INT_COUNT_FOR_DOWN_EI. So, reduce the freq
1106 */
1107 if (dev_priv->rps.cur_freq > dev_priv->rps.min_freq_softlimit)
1108 new_delay = dev_priv->rps.cur_freq + adj;
1109 }
1110
1111 return new_delay;
1112 }
1113
1114 static void gen6_pm_rps_work(struct work_struct *work)
1115 {
1116 struct drm_i915_private *dev_priv =
1117 container_of(work, struct drm_i915_private, rps.work);
1118 u32 pm_iir;
1119 int new_delay, adj;
1120
1121 spin_lock_irq(&dev_priv->irq_lock);
1122 pm_iir = dev_priv->rps.pm_iir;
1123 dev_priv->rps.pm_iir = 0;
1124 if (INTEL_INFO(dev_priv->dev)->gen >= 8)
1125 gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1126 else {
1127 /* Make sure not to corrupt PMIMR state used by ringbuffer */
1128 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1129 }
1130 spin_unlock_irq(&dev_priv->irq_lock);
1131
1132 /* Make sure we didn't queue anything we're not going to process. */
1133 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1134
1135 if ((pm_iir & dev_priv->pm_rps_events) == 0)
1136 return;
1137
1138 mutex_lock(&dev_priv->rps.hw_lock);
1139
1140 adj = dev_priv->rps.last_adj;
1141 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1142 if (adj > 0)
1143 adj *= 2;
1144 else {
1145 /* CHV needs even encode values */
1146 adj = IS_CHERRYVIEW(dev_priv->dev) ? 2 : 1;
1147 }
1148 new_delay = dev_priv->rps.cur_freq + adj;
1149
1150 /*
1151 * For better performance, jump directly
1152 * to RPe if we're below it.
1153 */
1154 if (new_delay < dev_priv->rps.efficient_freq)
1155 new_delay = dev_priv->rps.efficient_freq;
1156 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1157 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1158 new_delay = dev_priv->rps.efficient_freq;
1159 else
1160 new_delay = dev_priv->rps.min_freq_softlimit;
1161 adj = 0;
1162 } else if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1163 new_delay = vlv_calc_delay_from_C0_counters(dev_priv);
1164 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1165 if (adj < 0)
1166 adj *= 2;
1167 else {
1168 /* CHV needs even encode values */
1169 adj = IS_CHERRYVIEW(dev_priv->dev) ? -2 : -1;
1170 }
1171 new_delay = dev_priv->rps.cur_freq + adj;
1172 } else { /* unknown event */
1173 new_delay = dev_priv->rps.cur_freq;
1174 }
1175
1176 /* sysfs frequency interfaces may have snuck in while servicing the
1177 * interrupt
1178 */
1179 new_delay = clamp_t(int, new_delay,
1180 dev_priv->rps.min_freq_softlimit,
1181 dev_priv->rps.max_freq_softlimit);
1182
1183 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq;
1184
1185 if (IS_VALLEYVIEW(dev_priv->dev))
1186 valleyview_set_rps(dev_priv->dev, new_delay);
1187 else
1188 gen6_set_rps(dev_priv->dev, new_delay);
1189
1190 mutex_unlock(&dev_priv->rps.hw_lock);
1191 }
1192
1193
1194 /**
1195 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1196 * occurred.
1197 * @work: workqueue struct
1198 *
1199 * Doesn't actually do anything except notify userspace. As a consequence of
1200 * this event, userspace should try to remap the bad rows since statistically
1201 * it is likely the same row is more likely to go bad again.
1202 */
1203 static void ivybridge_parity_work(struct work_struct *work)
1204 {
1205 struct drm_i915_private *dev_priv =
1206 container_of(work, struct drm_i915_private, l3_parity.error_work);
1207 u32 error_status, row, bank, subbank;
1208 char *parity_event[6];
1209 uint32_t misccpctl;
1210 uint8_t slice = 0;
1211
1212 /* We must turn off DOP level clock gating to access the L3 registers.
1213 * In order to prevent a get/put style interface, acquire struct mutex
1214 * any time we access those registers.
1215 */
1216 mutex_lock(&dev_priv->dev->struct_mutex);
1217
1218 /* If we've screwed up tracking, just let the interrupt fire again */
1219 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1220 goto out;
1221
1222 misccpctl = I915_READ(GEN7_MISCCPCTL);
1223 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1224 POSTING_READ(GEN7_MISCCPCTL);
1225
1226 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1227 u32 reg;
1228
1229 slice--;
1230 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1231 break;
1232
1233 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1234
1235 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1236
1237 error_status = I915_READ(reg);
1238 row = GEN7_PARITY_ERROR_ROW(error_status);
1239 bank = GEN7_PARITY_ERROR_BANK(error_status);
1240 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1241
1242 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1243 POSTING_READ(reg);
1244
1245 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1246 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1247 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1248 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1249 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1250 parity_event[5] = NULL;
1251
1252 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1253 KOBJ_CHANGE, parity_event);
1254
1255 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1256 slice, row, bank, subbank);
1257
1258 kfree(parity_event[4]);
1259 kfree(parity_event[3]);
1260 kfree(parity_event[2]);
1261 kfree(parity_event[1]);
1262 }
1263
1264 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1265
1266 out:
1267 WARN_ON(dev_priv->l3_parity.which_slice);
1268 spin_lock_irq(&dev_priv->irq_lock);
1269 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1270 spin_unlock_irq(&dev_priv->irq_lock);
1271
1272 mutex_unlock(&dev_priv->dev->struct_mutex);
1273 }
1274
1275 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1276 {
1277 struct drm_i915_private *dev_priv = dev->dev_private;
1278
1279 if (!HAS_L3_DPF(dev))
1280 return;
1281
1282 spin_lock(&dev_priv->irq_lock);
1283 gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1284 spin_unlock(&dev_priv->irq_lock);
1285
1286 iir &= GT_PARITY_ERROR(dev);
1287 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1288 dev_priv->l3_parity.which_slice |= 1 << 1;
1289
1290 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1291 dev_priv->l3_parity.which_slice |= 1 << 0;
1292
1293 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1294 }
1295
1296 static void ilk_gt_irq_handler(struct drm_device *dev,
1297 struct drm_i915_private *dev_priv,
1298 u32 gt_iir)
1299 {
1300 if (gt_iir &
1301 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1302 notify_ring(dev, &dev_priv->ring[RCS]);
1303 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1304 notify_ring(dev, &dev_priv->ring[VCS]);
1305 }
1306
1307 static void snb_gt_irq_handler(struct drm_device *dev,
1308 struct drm_i915_private *dev_priv,
1309 u32 gt_iir)
1310 {
1311
1312 if (gt_iir &
1313 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1314 notify_ring(dev, &dev_priv->ring[RCS]);
1315 if (gt_iir & GT_BSD_USER_INTERRUPT)
1316 notify_ring(dev, &dev_priv->ring[VCS]);
1317 if (gt_iir & GT_BLT_USER_INTERRUPT)
1318 notify_ring(dev, &dev_priv->ring[BCS]);
1319
1320 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1321 GT_BSD_CS_ERROR_INTERRUPT |
1322 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
1323 i915_handle_error(dev, false, "GT error interrupt 0x%08x",
1324 gt_iir);
1325 }
1326
1327 if (gt_iir & GT_PARITY_ERROR(dev))
1328 ivybridge_parity_error_irq_handler(dev, gt_iir);
1329 }
1330
1331 static void gen8_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1332 {
1333 if ((pm_iir & dev_priv->pm_rps_events) == 0)
1334 return;
1335
1336 spin_lock(&dev_priv->irq_lock);
1337 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1338 gen8_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1339 spin_unlock(&dev_priv->irq_lock);
1340
1341 queue_work(dev_priv->wq, &dev_priv->rps.work);
1342 }
1343
1344 static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1345 struct drm_i915_private *dev_priv,
1346 u32 master_ctl)
1347 {
1348 struct intel_engine_cs *ring;
1349 u32 rcs, bcs, vcs;
1350 uint32_t tmp = 0;
1351 irqreturn_t ret = IRQ_NONE;
1352
1353 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1354 tmp = I915_READ(GEN8_GT_IIR(0));
1355 if (tmp) {
1356 I915_WRITE(GEN8_GT_IIR(0), tmp);
1357 ret = IRQ_HANDLED;
1358
1359 rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1360 ring = &dev_priv->ring[RCS];
1361 if (rcs & GT_RENDER_USER_INTERRUPT)
1362 notify_ring(dev, ring);
1363 if (rcs & GT_CONTEXT_SWITCH_INTERRUPT)
1364 intel_execlists_handle_ctx_events(ring);
1365
1366 bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1367 ring = &dev_priv->ring[BCS];
1368 if (bcs & GT_RENDER_USER_INTERRUPT)
1369 notify_ring(dev, ring);
1370 if (bcs & GT_CONTEXT_SWITCH_INTERRUPT)
1371 intel_execlists_handle_ctx_events(ring);
1372 } else
1373 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1374 }
1375
1376 if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1377 tmp = I915_READ(GEN8_GT_IIR(1));
1378 if (tmp) {
1379 I915_WRITE(GEN8_GT_IIR(1), tmp);
1380 ret = IRQ_HANDLED;
1381
1382 vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1383 ring = &dev_priv->ring[VCS];
1384 if (vcs & GT_RENDER_USER_INTERRUPT)
1385 notify_ring(dev, ring);
1386 if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1387 intel_execlists_handle_ctx_events(ring);
1388
1389 vcs = tmp >> GEN8_VCS2_IRQ_SHIFT;
1390 ring = &dev_priv->ring[VCS2];
1391 if (vcs & GT_RENDER_USER_INTERRUPT)
1392 notify_ring(dev, ring);
1393 if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1394 intel_execlists_handle_ctx_events(ring);
1395 } else
1396 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1397 }
1398
1399 if (master_ctl & GEN8_GT_PM_IRQ) {
1400 tmp = I915_READ(GEN8_GT_IIR(2));
1401 if (tmp & dev_priv->pm_rps_events) {
1402 I915_WRITE(GEN8_GT_IIR(2),
1403 tmp & dev_priv->pm_rps_events);
1404 ret = IRQ_HANDLED;
1405 gen8_rps_irq_handler(dev_priv, tmp);
1406 } else
1407 DRM_ERROR("The master control interrupt lied (PM)!\n");
1408 }
1409
1410 if (master_ctl & GEN8_GT_VECS_IRQ) {
1411 tmp = I915_READ(GEN8_GT_IIR(3));
1412 if (tmp) {
1413 I915_WRITE(GEN8_GT_IIR(3), tmp);
1414 ret = IRQ_HANDLED;
1415
1416 vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1417 ring = &dev_priv->ring[VECS];
1418 if (vcs & GT_RENDER_USER_INTERRUPT)
1419 notify_ring(dev, ring);
1420 if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1421 intel_execlists_handle_ctx_events(ring);
1422 } else
1423 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1424 }
1425
1426 return ret;
1427 }
1428
1429 #define HPD_STORM_DETECT_PERIOD 1000
1430 #define HPD_STORM_THRESHOLD 5
1431
1432 static int pch_port_to_hotplug_shift(enum port port)
1433 {
1434 switch (port) {
1435 case PORT_A:
1436 case PORT_E:
1437 default:
1438 return -1;
1439 case PORT_B:
1440 return 0;
1441 case PORT_C:
1442 return 8;
1443 case PORT_D:
1444 return 16;
1445 }
1446 }
1447
1448 static int i915_port_to_hotplug_shift(enum port port)
1449 {
1450 switch (port) {
1451 case PORT_A:
1452 case PORT_E:
1453 default:
1454 return -1;
1455 case PORT_B:
1456 return 17;
1457 case PORT_C:
1458 return 19;
1459 case PORT_D:
1460 return 21;
1461 }
1462 }
1463
1464 static inline enum port get_port_from_pin(enum hpd_pin pin)
1465 {
1466 switch (pin) {
1467 case HPD_PORT_B:
1468 return PORT_B;
1469 case HPD_PORT_C:
1470 return PORT_C;
1471 case HPD_PORT_D:
1472 return PORT_D;
1473 default:
1474 return PORT_A; /* no hpd */
1475 }
1476 }
1477
1478 static inline void intel_hpd_irq_handler(struct drm_device *dev,
1479 u32 hotplug_trigger,
1480 u32 dig_hotplug_reg,
1481 const u32 *hpd)
1482 {
1483 struct drm_i915_private *dev_priv = dev->dev_private;
1484 int i;
1485 enum port port;
1486 bool storm_detected = false;
1487 bool queue_dig = false, queue_hp = false;
1488 u32 dig_shift;
1489 u32 dig_port_mask = 0;
1490
1491 if (!hotplug_trigger)
1492 return;
1493
1494 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x\n",
1495 hotplug_trigger, dig_hotplug_reg);
1496
1497 spin_lock(&dev_priv->irq_lock);
1498 for (i = 1; i < HPD_NUM_PINS; i++) {
1499 if (!(hpd[i] & hotplug_trigger))
1500 continue;
1501
1502 port = get_port_from_pin(i);
1503 if (port && dev_priv->hpd_irq_port[port]) {
1504 bool long_hpd;
1505
1506 if (HAS_PCH_SPLIT(dev)) {
1507 dig_shift = pch_port_to_hotplug_shift(port);
1508 long_hpd = (dig_hotplug_reg >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
1509 } else {
1510 dig_shift = i915_port_to_hotplug_shift(port);
1511 long_hpd = (hotplug_trigger >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
1512 }
1513
1514 DRM_DEBUG_DRIVER("digital hpd port %c - %s\n",
1515 port_name(port),
1516 long_hpd ? "long" : "short");
1517 /* for long HPD pulses we want to have the digital queue happen,
1518 but we still want HPD storm detection to function. */
1519 if (long_hpd) {
1520 dev_priv->long_hpd_port_mask |= (1 << port);
1521 dig_port_mask |= hpd[i];
1522 } else {
1523 /* for short HPD just trigger the digital queue */
1524 dev_priv->short_hpd_port_mask |= (1 << port);
1525 hotplug_trigger &= ~hpd[i];
1526 }
1527 queue_dig = true;
1528 }
1529 }
1530
1531 for (i = 1; i < HPD_NUM_PINS; i++) {
1532 if (hpd[i] & hotplug_trigger &&
1533 dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) {
1534 /*
1535 * On GMCH platforms the interrupt mask bits only
1536 * prevent irq generation, not the setting of the
1537 * hotplug bits itself. So only WARN about unexpected
1538 * interrupts on saner platforms.
1539 */
1540 WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
1541 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1542 hotplug_trigger, i, hpd[i]);
1543
1544 continue;
1545 }
1546
1547 if (!(hpd[i] & hotplug_trigger) ||
1548 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1549 continue;
1550
1551 if (!(dig_port_mask & hpd[i])) {
1552 dev_priv->hpd_event_bits |= (1 << i);
1553 queue_hp = true;
1554 }
1555
1556 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1557 dev_priv->hpd_stats[i].hpd_last_jiffies
1558 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1559 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1560 dev_priv->hpd_stats[i].hpd_cnt = 0;
1561 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1562 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1563 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1564 dev_priv->hpd_event_bits &= ~(1 << i);
1565 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1566 storm_detected = true;
1567 } else {
1568 dev_priv->hpd_stats[i].hpd_cnt++;
1569 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1570 dev_priv->hpd_stats[i].hpd_cnt);
1571 }
1572 }
1573
1574 if (storm_detected)
1575 dev_priv->display.hpd_irq_setup(dev);
1576 spin_unlock(&dev_priv->irq_lock);
1577
1578 /*
1579 * Our hotplug handler can grab modeset locks (by calling down into the
1580 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1581 * queue for otherwise the flush_work in the pageflip code will
1582 * deadlock.
1583 */
1584 if (queue_dig)
1585 queue_work(dev_priv->dp_wq, &dev_priv->dig_port_work);
1586 if (queue_hp)
1587 schedule_work(&dev_priv->hotplug_work);
1588 }
1589
1590 static void gmbus_irq_handler(struct drm_device *dev)
1591 {
1592 struct drm_i915_private *dev_priv = dev->dev_private;
1593
1594 wake_up_all(&dev_priv->gmbus_wait_queue);
1595 }
1596
1597 static void dp_aux_irq_handler(struct drm_device *dev)
1598 {
1599 struct drm_i915_private *dev_priv = dev->dev_private;
1600
1601 wake_up_all(&dev_priv->gmbus_wait_queue);
1602 }
1603
1604 #if defined(CONFIG_DEBUG_FS)
1605 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1606 uint32_t crc0, uint32_t crc1,
1607 uint32_t crc2, uint32_t crc3,
1608 uint32_t crc4)
1609 {
1610 struct drm_i915_private *dev_priv = dev->dev_private;
1611 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1612 struct intel_pipe_crc_entry *entry;
1613 int head, tail;
1614
1615 spin_lock(&pipe_crc->lock);
1616
1617 if (!pipe_crc->entries) {
1618 spin_unlock(&pipe_crc->lock);
1619 DRM_ERROR("spurious interrupt\n");
1620 return;
1621 }
1622
1623 head = pipe_crc->head;
1624 tail = pipe_crc->tail;
1625
1626 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1627 spin_unlock(&pipe_crc->lock);
1628 DRM_ERROR("CRC buffer overflowing\n");
1629 return;
1630 }
1631
1632 entry = &pipe_crc->entries[head];
1633
1634 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1635 entry->crc[0] = crc0;
1636 entry->crc[1] = crc1;
1637 entry->crc[2] = crc2;
1638 entry->crc[3] = crc3;
1639 entry->crc[4] = crc4;
1640
1641 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1642 pipe_crc->head = head;
1643
1644 spin_unlock(&pipe_crc->lock);
1645
1646 wake_up_interruptible(&pipe_crc->wq);
1647 }
1648 #else
1649 static inline void
1650 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1651 uint32_t crc0, uint32_t crc1,
1652 uint32_t crc2, uint32_t crc3,
1653 uint32_t crc4) {}
1654 #endif
1655
1656
1657 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1658 {
1659 struct drm_i915_private *dev_priv = dev->dev_private;
1660
1661 display_pipe_crc_irq_handler(dev, pipe,
1662 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1663 0, 0, 0, 0);
1664 }
1665
1666 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1667 {
1668 struct drm_i915_private *dev_priv = dev->dev_private;
1669
1670 display_pipe_crc_irq_handler(dev, pipe,
1671 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1672 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1673 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1674 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1675 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1676 }
1677
1678 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1679 {
1680 struct drm_i915_private *dev_priv = dev->dev_private;
1681 uint32_t res1, res2;
1682
1683 if (INTEL_INFO(dev)->gen >= 3)
1684 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1685 else
1686 res1 = 0;
1687
1688 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1689 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1690 else
1691 res2 = 0;
1692
1693 display_pipe_crc_irq_handler(dev, pipe,
1694 I915_READ(PIPE_CRC_RES_RED(pipe)),
1695 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1696 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1697 res1, res2);
1698 }
1699
1700 /* The RPS events need forcewake, so we add them to a work queue and mask their
1701 * IMR bits until the work is done. Other interrupts can be processed without
1702 * the work queue. */
1703 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1704 {
1705 if (pm_iir & dev_priv->pm_rps_events) {
1706 spin_lock(&dev_priv->irq_lock);
1707 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1708 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1709 spin_unlock(&dev_priv->irq_lock);
1710
1711 queue_work(dev_priv->wq, &dev_priv->rps.work);
1712 }
1713
1714 if (HAS_VEBOX(dev_priv->dev)) {
1715 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1716 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1717
1718 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1719 i915_handle_error(dev_priv->dev, false,
1720 "VEBOX CS error interrupt 0x%08x",
1721 pm_iir);
1722 }
1723 }
1724 }
1725
1726 static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
1727 {
1728 if (!drm_handle_vblank(dev, pipe))
1729 return false;
1730
1731 return true;
1732 }
1733
1734 static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1735 {
1736 struct drm_i915_private *dev_priv = dev->dev_private;
1737 u32 pipe_stats[I915_MAX_PIPES] = { };
1738 int pipe;
1739
1740 spin_lock(&dev_priv->irq_lock);
1741 for_each_pipe(dev_priv, pipe) {
1742 int reg;
1743 u32 mask, iir_bit = 0;
1744
1745 /*
1746 * PIPESTAT bits get signalled even when the interrupt is
1747 * disabled with the mask bits, and some of the status bits do
1748 * not generate interrupts at all (like the underrun bit). Hence
1749 * we need to be careful that we only handle what we want to
1750 * handle.
1751 */
1752 mask = 0;
1753 if (__cpu_fifo_underrun_reporting_enabled(dev_priv, pipe))
1754 mask |= PIPE_FIFO_UNDERRUN_STATUS;
1755
1756 switch (pipe) {
1757 case PIPE_A:
1758 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1759 break;
1760 case PIPE_B:
1761 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1762 break;
1763 case PIPE_C:
1764 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1765 break;
1766 }
1767 if (iir & iir_bit)
1768 mask |= dev_priv->pipestat_irq_mask[pipe];
1769
1770 if (!mask)
1771 continue;
1772
1773 reg = PIPESTAT(pipe);
1774 mask |= PIPESTAT_INT_ENABLE_MASK;
1775 pipe_stats[pipe] = I915_READ(reg) & mask;
1776
1777 /*
1778 * Clear the PIPE*STAT regs before the IIR
1779 */
1780 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1781 PIPESTAT_INT_STATUS_MASK))
1782 I915_WRITE(reg, pipe_stats[pipe]);
1783 }
1784 spin_unlock(&dev_priv->irq_lock);
1785
1786 for_each_pipe(dev_priv, pipe) {
1787 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1788 intel_pipe_handle_vblank(dev, pipe))
1789 intel_check_page_flip(dev, pipe);
1790
1791 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
1792 intel_prepare_page_flip(dev, pipe);
1793 intel_finish_page_flip(dev, pipe);
1794 }
1795
1796 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1797 i9xx_pipe_crc_irq_handler(dev, pipe);
1798
1799 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
1800 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe,
1801 false))
1802 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
1803 }
1804
1805 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1806 gmbus_irq_handler(dev);
1807 }
1808
1809 static void i9xx_hpd_irq_handler(struct drm_device *dev)
1810 {
1811 struct drm_i915_private *dev_priv = dev->dev_private;
1812 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1813
1814 if (hotplug_status) {
1815 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1816 /*
1817 * Make sure hotplug status is cleared before we clear IIR, or else we
1818 * may miss hotplug events.
1819 */
1820 POSTING_READ(PORT_HOTPLUG_STAT);
1821
1822 if (IS_G4X(dev)) {
1823 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1824
1825 intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_g4x);
1826 } else {
1827 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1828
1829 intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_i915);
1830 }
1831
1832 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) &&
1833 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1834 dp_aux_irq_handler(dev);
1835 }
1836 }
1837
1838 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1839 {
1840 struct drm_device *dev = arg;
1841 struct drm_i915_private *dev_priv = dev->dev_private;
1842 u32 iir, gt_iir, pm_iir;
1843 irqreturn_t ret = IRQ_NONE;
1844
1845 while (true) {
1846 /* Find, clear, then process each source of interrupt */
1847
1848 gt_iir = I915_READ(GTIIR);
1849 if (gt_iir)
1850 I915_WRITE(GTIIR, gt_iir);
1851
1852 pm_iir = I915_READ(GEN6_PMIIR);
1853 if (pm_iir)
1854 I915_WRITE(GEN6_PMIIR, pm_iir);
1855
1856 iir = I915_READ(VLV_IIR);
1857 if (iir) {
1858 /* Consume port before clearing IIR or we'll miss events */
1859 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1860 i9xx_hpd_irq_handler(dev);
1861 I915_WRITE(VLV_IIR, iir);
1862 }
1863
1864 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1865 goto out;
1866
1867 ret = IRQ_HANDLED;
1868
1869 if (gt_iir)
1870 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1871 if (pm_iir)
1872 gen6_rps_irq_handler(dev_priv, pm_iir);
1873 /* Call regardless, as some status bits might not be
1874 * signalled in iir */
1875 valleyview_pipestat_irq_handler(dev, iir);
1876 }
1877
1878 out:
1879 return ret;
1880 }
1881
1882 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1883 {
1884 struct drm_device *dev = arg;
1885 struct drm_i915_private *dev_priv = dev->dev_private;
1886 u32 master_ctl, iir;
1887 irqreturn_t ret = IRQ_NONE;
1888
1889 for (;;) {
1890 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1891 iir = I915_READ(VLV_IIR);
1892
1893 if (master_ctl == 0 && iir == 0)
1894 break;
1895
1896 ret = IRQ_HANDLED;
1897
1898 I915_WRITE(GEN8_MASTER_IRQ, 0);
1899
1900 /* Find, clear, then process each source of interrupt */
1901
1902 if (iir) {
1903 /* Consume port before clearing IIR or we'll miss events */
1904 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1905 i9xx_hpd_irq_handler(dev);
1906 I915_WRITE(VLV_IIR, iir);
1907 }
1908
1909 gen8_gt_irq_handler(dev, dev_priv, master_ctl);
1910
1911 /* Call regardless, as some status bits might not be
1912 * signalled in iir */
1913 valleyview_pipestat_irq_handler(dev, iir);
1914
1915 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
1916 POSTING_READ(GEN8_MASTER_IRQ);
1917 }
1918
1919 return ret;
1920 }
1921
1922 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1923 {
1924 struct drm_i915_private *dev_priv = dev->dev_private;
1925 int pipe;
1926 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1927 u32 dig_hotplug_reg;
1928
1929 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1930 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1931
1932 intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_ibx);
1933
1934 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1935 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1936 SDE_AUDIO_POWER_SHIFT);
1937 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1938 port_name(port));
1939 }
1940
1941 if (pch_iir & SDE_AUX_MASK)
1942 dp_aux_irq_handler(dev);
1943
1944 if (pch_iir & SDE_GMBUS)
1945 gmbus_irq_handler(dev);
1946
1947 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1948 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1949
1950 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1951 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1952
1953 if (pch_iir & SDE_POISON)
1954 DRM_ERROR("PCH poison interrupt\n");
1955
1956 if (pch_iir & SDE_FDI_MASK)
1957 for_each_pipe(dev_priv, pipe)
1958 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1959 pipe_name(pipe),
1960 I915_READ(FDI_RX_IIR(pipe)));
1961
1962 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1963 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1964
1965 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1966 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1967
1968 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1969 if (intel_set_pch_fifo_underrun_reporting(dev_priv,
1970 TRANSCODER_A,
1971 false))
1972 DRM_ERROR("PCH transcoder A FIFO underrun\n");
1973
1974 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1975 if (intel_set_pch_fifo_underrun_reporting(dev_priv,
1976 TRANSCODER_B,
1977 false))
1978 DRM_ERROR("PCH transcoder B FIFO underrun\n");
1979 }
1980
1981 static void ivb_err_int_handler(struct drm_device *dev)
1982 {
1983 struct drm_i915_private *dev_priv = dev->dev_private;
1984 u32 err_int = I915_READ(GEN7_ERR_INT);
1985 enum pipe pipe;
1986
1987 if (err_int & ERR_INT_POISON)
1988 DRM_ERROR("Poison interrupt\n");
1989
1990 for_each_pipe(dev_priv, pipe) {
1991 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
1992 if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe,
1993 false))
1994 DRM_ERROR("Pipe %c FIFO underrun\n",
1995 pipe_name(pipe));
1996 }
1997
1998 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1999 if (IS_IVYBRIDGE(dev))
2000 ivb_pipe_crc_irq_handler(dev, pipe);
2001 else
2002 hsw_pipe_crc_irq_handler(dev, pipe);
2003 }
2004 }
2005
2006 I915_WRITE(GEN7_ERR_INT, err_int);
2007 }
2008
2009 static void cpt_serr_int_handler(struct drm_device *dev)
2010 {
2011 struct drm_i915_private *dev_priv = dev->dev_private;
2012 u32 serr_int = I915_READ(SERR_INT);
2013
2014 if (serr_int & SERR_INT_POISON)
2015 DRM_ERROR("PCH poison interrupt\n");
2016
2017 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2018 if (intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
2019 false))
2020 DRM_ERROR("PCH transcoder A FIFO underrun\n");
2021
2022 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2023 if (intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_B,
2024 false))
2025 DRM_ERROR("PCH transcoder B FIFO underrun\n");
2026
2027 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2028 if (intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_C,
2029 false))
2030 DRM_ERROR("PCH transcoder C FIFO underrun\n");
2031
2032 I915_WRITE(SERR_INT, serr_int);
2033 }
2034
2035 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
2036 {
2037 struct drm_i915_private *dev_priv = dev->dev_private;
2038 int pipe;
2039 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2040 u32 dig_hotplug_reg;
2041
2042 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2043 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2044
2045 intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_cpt);
2046
2047 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2048 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2049 SDE_AUDIO_POWER_SHIFT_CPT);
2050 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2051 port_name(port));
2052 }
2053
2054 if (pch_iir & SDE_AUX_MASK_CPT)
2055 dp_aux_irq_handler(dev);
2056
2057 if (pch_iir & SDE_GMBUS_CPT)
2058 gmbus_irq_handler(dev);
2059
2060 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2061 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2062
2063 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2064 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2065
2066 if (pch_iir & SDE_FDI_MASK_CPT)
2067 for_each_pipe(dev_priv, pipe)
2068 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2069 pipe_name(pipe),
2070 I915_READ(FDI_RX_IIR(pipe)));
2071
2072 if (pch_iir & SDE_ERROR_CPT)
2073 cpt_serr_int_handler(dev);
2074 }
2075
2076 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
2077 {
2078 struct drm_i915_private *dev_priv = dev->dev_private;
2079 enum pipe pipe;
2080
2081 if (de_iir & DE_AUX_CHANNEL_A)
2082 dp_aux_irq_handler(dev);
2083
2084 if (de_iir & DE_GSE)
2085 intel_opregion_asle_intr(dev);
2086
2087 if (de_iir & DE_POISON)
2088 DRM_ERROR("Poison interrupt\n");
2089
2090 for_each_pipe(dev_priv, pipe) {
2091 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2092 intel_pipe_handle_vblank(dev, pipe))
2093 intel_check_page_flip(dev, pipe);
2094
2095 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2096 if (intel_set_cpu_fifo_underrun_reporting(dev_priv,
2097 pipe,
2098 false))
2099 DRM_ERROR("Pipe %c FIFO underrun\n",
2100 pipe_name(pipe));
2101
2102 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2103 i9xx_pipe_crc_irq_handler(dev, pipe);
2104
2105 /* plane/pipes map 1:1 on ilk+ */
2106 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
2107 intel_prepare_page_flip(dev, pipe);
2108 intel_finish_page_flip_plane(dev, pipe);
2109 }
2110 }
2111
2112 /* check event from PCH */
2113 if (de_iir & DE_PCH_EVENT) {
2114 u32 pch_iir = I915_READ(SDEIIR);
2115
2116 if (HAS_PCH_CPT(dev))
2117 cpt_irq_handler(dev, pch_iir);
2118 else
2119 ibx_irq_handler(dev, pch_iir);
2120
2121 /* should clear PCH hotplug event before clear CPU irq */
2122 I915_WRITE(SDEIIR, pch_iir);
2123 }
2124
2125 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
2126 ironlake_rps_change_irq_handler(dev);
2127 }
2128
2129 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
2130 {
2131 struct drm_i915_private *dev_priv = dev->dev_private;
2132 enum pipe pipe;
2133
2134 if (de_iir & DE_ERR_INT_IVB)
2135 ivb_err_int_handler(dev);
2136
2137 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2138 dp_aux_irq_handler(dev);
2139
2140 if (de_iir & DE_GSE_IVB)
2141 intel_opregion_asle_intr(dev);
2142
2143 for_each_pipe(dev_priv, pipe) {
2144 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2145 intel_pipe_handle_vblank(dev, pipe))
2146 intel_check_page_flip(dev, pipe);
2147
2148 /* plane/pipes map 1:1 on ilk+ */
2149 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
2150 intel_prepare_page_flip(dev, pipe);
2151 intel_finish_page_flip_plane(dev, pipe);
2152 }
2153 }
2154
2155 /* check event from PCH */
2156 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
2157 u32 pch_iir = I915_READ(SDEIIR);
2158
2159 cpt_irq_handler(dev, pch_iir);
2160
2161 /* clear PCH hotplug event before clear CPU irq */
2162 I915_WRITE(SDEIIR, pch_iir);
2163 }
2164 }
2165
2166 /*
2167 * To handle irqs with the minimum potential races with fresh interrupts, we:
2168 * 1 - Disable Master Interrupt Control.
2169 * 2 - Find the source(s) of the interrupt.
2170 * 3 - Clear the Interrupt Identity bits (IIR).
2171 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2172 * 5 - Re-enable Master Interrupt Control.
2173 */
2174 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2175 {
2176 struct drm_device *dev = arg;
2177 struct drm_i915_private *dev_priv = dev->dev_private;
2178 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2179 irqreturn_t ret = IRQ_NONE;
2180
2181 /* We get interrupts on unclaimed registers, so check for this before we
2182 * do any I915_{READ,WRITE}. */
2183 intel_uncore_check_errors(dev);
2184
2185 /* disable master interrupt before clearing iir */
2186 de_ier = I915_READ(DEIER);
2187 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2188 POSTING_READ(DEIER);
2189
2190 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2191 * interrupts will will be stored on its back queue, and then we'll be
2192 * able to process them after we restore SDEIER (as soon as we restore
2193 * it, we'll get an interrupt if SDEIIR still has something to process
2194 * due to its back queue). */
2195 if (!HAS_PCH_NOP(dev)) {
2196 sde_ier = I915_READ(SDEIER);
2197 I915_WRITE(SDEIER, 0);
2198 POSTING_READ(SDEIER);
2199 }
2200
2201 /* Find, clear, then process each source of interrupt */
2202
2203 gt_iir = I915_READ(GTIIR);
2204 if (gt_iir) {
2205 I915_WRITE(GTIIR, gt_iir);
2206 ret = IRQ_HANDLED;
2207 if (INTEL_INFO(dev)->gen >= 6)
2208 snb_gt_irq_handler(dev, dev_priv, gt_iir);
2209 else
2210 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
2211 }
2212
2213 de_iir = I915_READ(DEIIR);
2214 if (de_iir) {
2215 I915_WRITE(DEIIR, de_iir);
2216 ret = IRQ_HANDLED;
2217 if (INTEL_INFO(dev)->gen >= 7)
2218 ivb_display_irq_handler(dev, de_iir);
2219 else
2220 ilk_display_irq_handler(dev, de_iir);
2221 }
2222
2223 if (INTEL_INFO(dev)->gen >= 6) {
2224 u32 pm_iir = I915_READ(GEN6_PMIIR);
2225 if (pm_iir) {
2226 I915_WRITE(GEN6_PMIIR, pm_iir);
2227 ret = IRQ_HANDLED;
2228 gen6_rps_irq_handler(dev_priv, pm_iir);
2229 }
2230 }
2231
2232 I915_WRITE(DEIER, de_ier);
2233 POSTING_READ(DEIER);
2234 if (!HAS_PCH_NOP(dev)) {
2235 I915_WRITE(SDEIER, sde_ier);
2236 POSTING_READ(SDEIER);
2237 }
2238
2239 return ret;
2240 }
2241
2242 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2243 {
2244 struct drm_device *dev = arg;
2245 struct drm_i915_private *dev_priv = dev->dev_private;
2246 u32 master_ctl;
2247 irqreturn_t ret = IRQ_NONE;
2248 uint32_t tmp = 0;
2249 enum pipe pipe;
2250
2251 master_ctl = I915_READ(GEN8_MASTER_IRQ);
2252 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2253 if (!master_ctl)
2254 return IRQ_NONE;
2255
2256 I915_WRITE(GEN8_MASTER_IRQ, 0);
2257 POSTING_READ(GEN8_MASTER_IRQ);
2258
2259 /* Find, clear, then process each source of interrupt */
2260
2261 ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
2262
2263 if (master_ctl & GEN8_DE_MISC_IRQ) {
2264 tmp = I915_READ(GEN8_DE_MISC_IIR);
2265 if (tmp) {
2266 I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2267 ret = IRQ_HANDLED;
2268 if (tmp & GEN8_DE_MISC_GSE)
2269 intel_opregion_asle_intr(dev);
2270 else
2271 DRM_ERROR("Unexpected DE Misc interrupt\n");
2272 }
2273 else
2274 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2275 }
2276
2277 if (master_ctl & GEN8_DE_PORT_IRQ) {
2278 tmp = I915_READ(GEN8_DE_PORT_IIR);
2279 if (tmp) {
2280 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2281 ret = IRQ_HANDLED;
2282 if (tmp & GEN8_AUX_CHANNEL_A)
2283 dp_aux_irq_handler(dev);
2284 else
2285 DRM_ERROR("Unexpected DE Port interrupt\n");
2286 }
2287 else
2288 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2289 }
2290
2291 for_each_pipe(dev_priv, pipe) {
2292 uint32_t pipe_iir, flip_done = 0, fault_errors = 0;
2293
2294 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2295 continue;
2296
2297 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2298 if (pipe_iir) {
2299 ret = IRQ_HANDLED;
2300 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2301
2302 if (pipe_iir & GEN8_PIPE_VBLANK &&
2303 intel_pipe_handle_vblank(dev, pipe))
2304 intel_check_page_flip(dev, pipe);
2305
2306 if (IS_GEN9(dev))
2307 flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE;
2308 else
2309 flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE;
2310
2311 if (flip_done) {
2312 intel_prepare_page_flip(dev, pipe);
2313 intel_finish_page_flip_plane(dev, pipe);
2314 }
2315
2316 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2317 hsw_pipe_crc_irq_handler(dev, pipe);
2318
2319 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
2320 if (intel_set_cpu_fifo_underrun_reporting(dev_priv,
2321 pipe,
2322 false))
2323 DRM_ERROR("Pipe %c FIFO underrun\n",
2324 pipe_name(pipe));
2325 }
2326
2327
2328 if (IS_GEN9(dev))
2329 fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2330 else
2331 fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2332
2333 if (fault_errors)
2334 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2335 pipe_name(pipe),
2336 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2337 } else
2338 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2339 }
2340
2341 if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
2342 /*
2343 * FIXME(BDW): Assume for now that the new interrupt handling
2344 * scheme also closed the SDE interrupt handling race we've seen
2345 * on older pch-split platforms. But this needs testing.
2346 */
2347 u32 pch_iir = I915_READ(SDEIIR);
2348 if (pch_iir) {
2349 I915_WRITE(SDEIIR, pch_iir);
2350 ret = IRQ_HANDLED;
2351 cpt_irq_handler(dev, pch_iir);
2352 } else
2353 DRM_ERROR("The master control interrupt lied (SDE)!\n");
2354
2355 }
2356
2357 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2358 POSTING_READ(GEN8_MASTER_IRQ);
2359
2360 return ret;
2361 }
2362
2363 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2364 bool reset_completed)
2365 {
2366 struct intel_engine_cs *ring;
2367 int i;
2368
2369 /*
2370 * Notify all waiters for GPU completion events that reset state has
2371 * been changed, and that they need to restart their wait after
2372 * checking for potential errors (and bail out to drop locks if there is
2373 * a gpu reset pending so that i915_error_work_func can acquire them).
2374 */
2375
2376 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2377 for_each_ring(ring, dev_priv, i)
2378 wake_up_all(&ring->irq_queue);
2379
2380 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2381 wake_up_all(&dev_priv->pending_flip_queue);
2382
2383 /*
2384 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2385 * reset state is cleared.
2386 */
2387 if (reset_completed)
2388 wake_up_all(&dev_priv->gpu_error.reset_queue);
2389 }
2390
2391 /**
2392 * i915_error_work_func - do process context error handling work
2393 * @work: work struct
2394 *
2395 * Fire an error uevent so userspace can see that a hang or error
2396 * was detected.
2397 */
2398 static void i915_error_work_func(struct work_struct *work)
2399 {
2400 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
2401 work);
2402 struct drm_i915_private *dev_priv =
2403 container_of(error, struct drm_i915_private, gpu_error);
2404 struct drm_device *dev = dev_priv->dev;
2405 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2406 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2407 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2408 int ret;
2409
2410 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2411
2412 /*
2413 * Note that there's only one work item which does gpu resets, so we
2414 * need not worry about concurrent gpu resets potentially incrementing
2415 * error->reset_counter twice. We only need to take care of another
2416 * racing irq/hangcheck declaring the gpu dead for a second time. A
2417 * quick check for that is good enough: schedule_work ensures the
2418 * correct ordering between hang detection and this work item, and since
2419 * the reset in-progress bit is only ever set by code outside of this
2420 * work we don't need to worry about any other races.
2421 */
2422 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2423 DRM_DEBUG_DRIVER("resetting chip\n");
2424 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2425 reset_event);
2426
2427 /*
2428 * In most cases it's guaranteed that we get here with an RPM
2429 * reference held, for example because there is a pending GPU
2430 * request that won't finish until the reset is done. This
2431 * isn't the case at least when we get here by doing a
2432 * simulated reset via debugs, so get an RPM reference.
2433 */
2434 intel_runtime_pm_get(dev_priv);
2435 /*
2436 * All state reset _must_ be completed before we update the
2437 * reset counter, for otherwise waiters might miss the reset
2438 * pending state and not properly drop locks, resulting in
2439 * deadlocks with the reset work.
2440 */
2441 ret = i915_reset(dev);
2442
2443 intel_display_handle_reset(dev);
2444
2445 intel_runtime_pm_put(dev_priv);
2446
2447 if (ret == 0) {
2448 /*
2449 * After all the gem state is reset, increment the reset
2450 * counter and wake up everyone waiting for the reset to
2451 * complete.
2452 *
2453 * Since unlock operations are a one-sided barrier only,
2454 * we need to insert a barrier here to order any seqno
2455 * updates before
2456 * the counter increment.
2457 */
2458 smp_mb__before_atomic();
2459 atomic_inc(&dev_priv->gpu_error.reset_counter);
2460
2461 kobject_uevent_env(&dev->primary->kdev->kobj,
2462 KOBJ_CHANGE, reset_done_event);
2463 } else {
2464 atomic_set_mask(I915_WEDGED, &error->reset_counter);
2465 }
2466
2467 /*
2468 * Note: The wake_up also serves as a memory barrier so that
2469 * waiters see the update value of the reset counter atomic_t.
2470 */
2471 i915_error_wake_up(dev_priv, true);
2472 }
2473 }
2474
2475 static void i915_report_and_clear_eir(struct drm_device *dev)
2476 {
2477 struct drm_i915_private *dev_priv = dev->dev_private;
2478 uint32_t instdone[I915_NUM_INSTDONE_REG];
2479 u32 eir = I915_READ(EIR);
2480 int pipe, i;
2481
2482 if (!eir)
2483 return;
2484
2485 pr_err("render error detected, EIR: 0x%08x\n", eir);
2486
2487 i915_get_extra_instdone(dev, instdone);
2488
2489 if (IS_G4X(dev)) {
2490 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2491 u32 ipeir = I915_READ(IPEIR_I965);
2492
2493 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2494 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2495 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2496 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2497 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2498 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2499 I915_WRITE(IPEIR_I965, ipeir);
2500 POSTING_READ(IPEIR_I965);
2501 }
2502 if (eir & GM45_ERROR_PAGE_TABLE) {
2503 u32 pgtbl_err = I915_READ(PGTBL_ER);
2504 pr_err("page table error\n");
2505 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2506 I915_WRITE(PGTBL_ER, pgtbl_err);
2507 POSTING_READ(PGTBL_ER);
2508 }
2509 }
2510
2511 if (!IS_GEN2(dev)) {
2512 if (eir & I915_ERROR_PAGE_TABLE) {
2513 u32 pgtbl_err = I915_READ(PGTBL_ER);
2514 pr_err("page table error\n");
2515 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2516 I915_WRITE(PGTBL_ER, pgtbl_err);
2517 POSTING_READ(PGTBL_ER);
2518 }
2519 }
2520
2521 if (eir & I915_ERROR_MEMORY_REFRESH) {
2522 pr_err("memory refresh error:\n");
2523 for_each_pipe(dev_priv, pipe)
2524 pr_err("pipe %c stat: 0x%08x\n",
2525 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2526 /* pipestat has already been acked */
2527 }
2528 if (eir & I915_ERROR_INSTRUCTION) {
2529 pr_err("instruction error\n");
2530 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
2531 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2532 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2533 if (INTEL_INFO(dev)->gen < 4) {
2534 u32 ipeir = I915_READ(IPEIR);
2535
2536 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2537 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
2538 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
2539 I915_WRITE(IPEIR, ipeir);
2540 POSTING_READ(IPEIR);
2541 } else {
2542 u32 ipeir = I915_READ(IPEIR_I965);
2543
2544 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2545 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2546 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2547 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2548 I915_WRITE(IPEIR_I965, ipeir);
2549 POSTING_READ(IPEIR_I965);
2550 }
2551 }
2552
2553 I915_WRITE(EIR, eir);
2554 POSTING_READ(EIR);
2555 eir = I915_READ(EIR);
2556 if (eir) {
2557 /*
2558 * some errors might have become stuck,
2559 * mask them.
2560 */
2561 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2562 I915_WRITE(EMR, I915_READ(EMR) | eir);
2563 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2564 }
2565 }
2566
2567 /**
2568 * i915_handle_error - handle an error interrupt
2569 * @dev: drm device
2570 *
2571 * Do some basic checking of regsiter state at error interrupt time and
2572 * dump it to the syslog. Also call i915_capture_error_state() to make
2573 * sure we get a record and make it available in debugfs. Fire a uevent
2574 * so userspace knows something bad happened (should trigger collection
2575 * of a ring dump etc.).
2576 */
2577 void i915_handle_error(struct drm_device *dev, bool wedged,
2578 const char *fmt, ...)
2579 {
2580 struct drm_i915_private *dev_priv = dev->dev_private;
2581 va_list args;
2582 char error_msg[80];
2583
2584 va_start(args, fmt);
2585 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2586 va_end(args);
2587
2588 i915_capture_error_state(dev, wedged, error_msg);
2589 i915_report_and_clear_eir(dev);
2590
2591 if (wedged) {
2592 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2593 &dev_priv->gpu_error.reset_counter);
2594
2595 /*
2596 * Wakeup waiting processes so that the reset work function
2597 * i915_error_work_func doesn't deadlock trying to grab various
2598 * locks. By bumping the reset counter first, the woken
2599 * processes will see a reset in progress and back off,
2600 * releasing their locks and then wait for the reset completion.
2601 * We must do this for _all_ gpu waiters that might hold locks
2602 * that the reset work needs to acquire.
2603 *
2604 * Note: The wake_up serves as the required memory barrier to
2605 * ensure that the waiters see the updated value of the reset
2606 * counter atomic_t.
2607 */
2608 i915_error_wake_up(dev_priv, false);
2609 }
2610
2611 /*
2612 * Our reset work can grab modeset locks (since it needs to reset the
2613 * state of outstanding pagelips). Hence it must not be run on our own
2614 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2615 * code will deadlock.
2616 */
2617 schedule_work(&dev_priv->gpu_error.work);
2618 }
2619
2620 /* Called from drm generic code, passed 'crtc' which
2621 * we use as a pipe index
2622 */
2623 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2624 {
2625 struct drm_i915_private *dev_priv = dev->dev_private;
2626 unsigned long irqflags;
2627
2628 if (!i915_pipe_enabled(dev, pipe))
2629 return -EINVAL;
2630
2631 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2632 if (INTEL_INFO(dev)->gen >= 4)
2633 i915_enable_pipestat(dev_priv, pipe,
2634 PIPE_START_VBLANK_INTERRUPT_STATUS);
2635 else
2636 i915_enable_pipestat(dev_priv, pipe,
2637 PIPE_VBLANK_INTERRUPT_STATUS);
2638 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2639
2640 return 0;
2641 }
2642
2643 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2644 {
2645 struct drm_i915_private *dev_priv = dev->dev_private;
2646 unsigned long irqflags;
2647 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2648 DE_PIPE_VBLANK(pipe);
2649
2650 if (!i915_pipe_enabled(dev, pipe))
2651 return -EINVAL;
2652
2653 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2654 ironlake_enable_display_irq(dev_priv, bit);
2655 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2656
2657 return 0;
2658 }
2659
2660 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2661 {
2662 struct drm_i915_private *dev_priv = dev->dev_private;
2663 unsigned long irqflags;
2664
2665 if (!i915_pipe_enabled(dev, pipe))
2666 return -EINVAL;
2667
2668 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2669 i915_enable_pipestat(dev_priv, pipe,
2670 PIPE_START_VBLANK_INTERRUPT_STATUS);
2671 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2672
2673 return 0;
2674 }
2675
2676 static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2677 {
2678 struct drm_i915_private *dev_priv = dev->dev_private;
2679 unsigned long irqflags;
2680
2681 if (!i915_pipe_enabled(dev, pipe))
2682 return -EINVAL;
2683
2684 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2685 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2686 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2687 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2688 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2689 return 0;
2690 }
2691
2692 /* Called from drm generic code, passed 'crtc' which
2693 * we use as a pipe index
2694 */
2695 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2696 {
2697 struct drm_i915_private *dev_priv = dev->dev_private;
2698 unsigned long irqflags;
2699
2700 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2701 i915_disable_pipestat(dev_priv, pipe,
2702 PIPE_VBLANK_INTERRUPT_STATUS |
2703 PIPE_START_VBLANK_INTERRUPT_STATUS);
2704 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2705 }
2706
2707 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2708 {
2709 struct drm_i915_private *dev_priv = dev->dev_private;
2710 unsigned long irqflags;
2711 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2712 DE_PIPE_VBLANK(pipe);
2713
2714 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2715 ironlake_disable_display_irq(dev_priv, bit);
2716 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2717 }
2718
2719 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2720 {
2721 struct drm_i915_private *dev_priv = dev->dev_private;
2722 unsigned long irqflags;
2723
2724 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2725 i915_disable_pipestat(dev_priv, pipe,
2726 PIPE_START_VBLANK_INTERRUPT_STATUS);
2727 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2728 }
2729
2730 static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2731 {
2732 struct drm_i915_private *dev_priv = dev->dev_private;
2733 unsigned long irqflags;
2734
2735 if (!i915_pipe_enabled(dev, pipe))
2736 return;
2737
2738 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2739 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2740 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2741 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2742 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2743 }
2744
2745 static u32
2746 ring_last_seqno(struct intel_engine_cs *ring)
2747 {
2748 return list_entry(ring->request_list.prev,
2749 struct drm_i915_gem_request, list)->seqno;
2750 }
2751
2752 static bool
2753 ring_idle(struct intel_engine_cs *ring, u32 seqno)
2754 {
2755 return (list_empty(&ring->request_list) ||
2756 i915_seqno_passed(seqno, ring_last_seqno(ring)));
2757 }
2758
2759 static bool
2760 ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
2761 {
2762 if (INTEL_INFO(dev)->gen >= 8) {
2763 return (ipehr >> 23) == 0x1c;
2764 } else {
2765 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2766 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2767 MI_SEMAPHORE_REGISTER);
2768 }
2769 }
2770
2771 static struct intel_engine_cs *
2772 semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset)
2773 {
2774 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2775 struct intel_engine_cs *signaller;
2776 int i;
2777
2778 if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
2779 for_each_ring(signaller, dev_priv, i) {
2780 if (ring == signaller)
2781 continue;
2782
2783 if (offset == signaller->semaphore.signal_ggtt[ring->id])
2784 return signaller;
2785 }
2786 } else {
2787 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2788
2789 for_each_ring(signaller, dev_priv, i) {
2790 if(ring == signaller)
2791 continue;
2792
2793 if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
2794 return signaller;
2795 }
2796 }
2797
2798 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2799 ring->id, ipehr, offset);
2800
2801 return NULL;
2802 }
2803
2804 static struct intel_engine_cs *
2805 semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
2806 {
2807 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2808 u32 cmd, ipehr, head;
2809 u64 offset = 0;
2810 int i, backwards;
2811
2812 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2813 if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
2814 return NULL;
2815
2816 /*
2817 * HEAD is likely pointing to the dword after the actual command,
2818 * so scan backwards until we find the MBOX. But limit it to just 3
2819 * or 4 dwords depending on the semaphore wait command size.
2820 * Note that we don't care about ACTHD here since that might
2821 * point at at batch, and semaphores are always emitted into the
2822 * ringbuffer itself.
2823 */
2824 head = I915_READ_HEAD(ring) & HEAD_ADDR;
2825 backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4;
2826
2827 for (i = backwards; i; --i) {
2828 /*
2829 * Be paranoid and presume the hw has gone off into the wild -
2830 * our ring is smaller than what the hardware (and hence
2831 * HEAD_ADDR) allows. Also handles wrap-around.
2832 */
2833 head &= ring->buffer->size - 1;
2834
2835 /* This here seems to blow up */
2836 cmd = ioread32(ring->buffer->virtual_start + head);
2837 if (cmd == ipehr)
2838 break;
2839
2840 head -= 4;
2841 }
2842
2843 if (!i)
2844 return NULL;
2845
2846 *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
2847 if (INTEL_INFO(ring->dev)->gen >= 8) {
2848 offset = ioread32(ring->buffer->virtual_start + head + 12);
2849 offset <<= 32;
2850 offset = ioread32(ring->buffer->virtual_start + head + 8);
2851 }
2852 return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
2853 }
2854
2855 static int semaphore_passed(struct intel_engine_cs *ring)
2856 {
2857 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2858 struct intel_engine_cs *signaller;
2859 u32 seqno;
2860
2861 ring->hangcheck.deadlock++;
2862
2863 signaller = semaphore_waits_for(ring, &seqno);
2864 if (signaller == NULL)
2865 return -1;
2866
2867 /* Prevent pathological recursion due to driver bugs */
2868 if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
2869 return -1;
2870
2871 if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
2872 return 1;
2873
2874 /* cursory check for an unkickable deadlock */
2875 if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
2876 semaphore_passed(signaller) < 0)
2877 return -1;
2878
2879 return 0;
2880 }
2881
2882 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2883 {
2884 struct intel_engine_cs *ring;
2885 int i;
2886
2887 for_each_ring(ring, dev_priv, i)
2888 ring->hangcheck.deadlock = 0;
2889 }
2890
2891 static enum intel_ring_hangcheck_action
2892 ring_stuck(struct intel_engine_cs *ring, u64 acthd)
2893 {
2894 struct drm_device *dev = ring->dev;
2895 struct drm_i915_private *dev_priv = dev->dev_private;
2896 u32 tmp;
2897
2898 if (acthd != ring->hangcheck.acthd) {
2899 if (acthd > ring->hangcheck.max_acthd) {
2900 ring->hangcheck.max_acthd = acthd;
2901 return HANGCHECK_ACTIVE;
2902 }
2903
2904 return HANGCHECK_ACTIVE_LOOP;
2905 }
2906
2907 if (IS_GEN2(dev))
2908 return HANGCHECK_HUNG;
2909
2910 /* Is the chip hanging on a WAIT_FOR_EVENT?
2911 * If so we can simply poke the RB_WAIT bit
2912 * and break the hang. This should work on
2913 * all but the second generation chipsets.
2914 */
2915 tmp = I915_READ_CTL(ring);
2916 if (tmp & RING_WAIT) {
2917 i915_handle_error(dev, false,
2918 "Kicking stuck wait on %s",
2919 ring->name);
2920 I915_WRITE_CTL(ring, tmp);
2921 return HANGCHECK_KICK;
2922 }
2923
2924 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2925 switch (semaphore_passed(ring)) {
2926 default:
2927 return HANGCHECK_HUNG;
2928 case 1:
2929 i915_handle_error(dev, false,
2930 "Kicking stuck semaphore on %s",
2931 ring->name);
2932 I915_WRITE_CTL(ring, tmp);
2933 return HANGCHECK_KICK;
2934 case 0:
2935 return HANGCHECK_WAIT;
2936 }
2937 }
2938
2939 return HANGCHECK_HUNG;
2940 }
2941
2942 /**
2943 * This is called when the chip hasn't reported back with completed
2944 * batchbuffers in a long time. We keep track per ring seqno progress and
2945 * if there are no progress, hangcheck score for that ring is increased.
2946 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2947 * we kick the ring. If we see no progress on three subsequent calls
2948 * we assume chip is wedged and try to fix it by resetting the chip.
2949 */
2950 static void i915_hangcheck_elapsed(unsigned long data)
2951 {
2952 struct drm_device *dev = (struct drm_device *)data;
2953 struct drm_i915_private *dev_priv = dev->dev_private;
2954 struct intel_engine_cs *ring;
2955 int i;
2956 int busy_count = 0, rings_hung = 0;
2957 bool stuck[I915_NUM_RINGS] = { 0 };
2958 #define BUSY 1
2959 #define KICK 5
2960 #define HUNG 20
2961
2962 if (!i915.enable_hangcheck)
2963 return;
2964
2965 for_each_ring(ring, dev_priv, i) {
2966 u64 acthd;
2967 u32 seqno;
2968 bool busy = true;
2969
2970 semaphore_clear_deadlocks(dev_priv);
2971
2972 seqno = ring->get_seqno(ring, false);
2973 acthd = intel_ring_get_active_head(ring);
2974
2975 if (ring->hangcheck.seqno == seqno) {
2976 if (ring_idle(ring, seqno)) {
2977 ring->hangcheck.action = HANGCHECK_IDLE;
2978
2979 if (waitqueue_active(&ring->irq_queue)) {
2980 /* Issue a wake-up to catch stuck h/w. */
2981 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2982 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2983 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2984 ring->name);
2985 else
2986 DRM_INFO("Fake missed irq on %s\n",
2987 ring->name);
2988 wake_up_all(&ring->irq_queue);
2989 }
2990 /* Safeguard against driver failure */
2991 ring->hangcheck.score += BUSY;
2992 } else
2993 busy = false;
2994 } else {
2995 /* We always increment the hangcheck score
2996 * if the ring is busy and still processing
2997 * the same request, so that no single request
2998 * can run indefinitely (such as a chain of
2999 * batches). The only time we do not increment
3000 * the hangcheck score on this ring, if this
3001 * ring is in a legitimate wait for another
3002 * ring. In that case the waiting ring is a
3003 * victim and we want to be sure we catch the
3004 * right culprit. Then every time we do kick
3005 * the ring, add a small increment to the
3006 * score so that we can catch a batch that is
3007 * being repeatedly kicked and so responsible
3008 * for stalling the machine.
3009 */
3010 ring->hangcheck.action = ring_stuck(ring,
3011 acthd);
3012
3013 switch (ring->hangcheck.action) {
3014 case HANGCHECK_IDLE:
3015 case HANGCHECK_WAIT:
3016 case HANGCHECK_ACTIVE:
3017 break;
3018 case HANGCHECK_ACTIVE_LOOP:
3019 ring->hangcheck.score += BUSY;
3020 break;
3021 case HANGCHECK_KICK:
3022 ring->hangcheck.score += KICK;
3023 break;
3024 case HANGCHECK_HUNG:
3025 ring->hangcheck.score += HUNG;
3026 stuck[i] = true;
3027 break;
3028 }
3029 }
3030 } else {
3031 ring->hangcheck.action = HANGCHECK_ACTIVE;
3032
3033 /* Gradually reduce the count so that we catch DoS
3034 * attempts across multiple batches.
3035 */
3036 if (ring->hangcheck.score > 0)
3037 ring->hangcheck.score--;
3038
3039 ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0;
3040 }
3041
3042 ring->hangcheck.seqno = seqno;
3043 ring->hangcheck.acthd = acthd;
3044 busy_count += busy;
3045 }
3046
3047 for_each_ring(ring, dev_priv, i) {
3048 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3049 DRM_INFO("%s on %s\n",
3050 stuck[i] ? "stuck" : "no progress",
3051 ring->name);
3052 rings_hung++;
3053 }
3054 }
3055
3056 if (rings_hung)
3057 return i915_handle_error(dev, true, "Ring hung");
3058
3059 if (busy_count)
3060 /* Reset timer case chip hangs without another request
3061 * being added */
3062 i915_queue_hangcheck(dev);
3063 }
3064
3065 void i915_queue_hangcheck(struct drm_device *dev)
3066 {
3067 struct drm_i915_private *dev_priv = dev->dev_private;
3068 if (!i915.enable_hangcheck)
3069 return;
3070
3071 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
3072 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
3073 }
3074
3075 static void ibx_irq_reset(struct drm_device *dev)
3076 {
3077 struct drm_i915_private *dev_priv = dev->dev_private;
3078
3079 if (HAS_PCH_NOP(dev))
3080 return;
3081
3082 GEN5_IRQ_RESET(SDE);
3083
3084 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3085 I915_WRITE(SERR_INT, 0xffffffff);
3086 }
3087
3088 /*
3089 * SDEIER is also touched by the interrupt handler to work around missed PCH
3090 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3091 * instead we unconditionally enable all PCH interrupt sources here, but then
3092 * only unmask them as needed with SDEIMR.
3093 *
3094 * This function needs to be called before interrupts are enabled.
3095 */
3096 static void ibx_irq_pre_postinstall(struct drm_device *dev)
3097 {
3098 struct drm_i915_private *dev_priv = dev->dev_private;
3099
3100 if (HAS_PCH_NOP(dev))
3101 return;
3102
3103 WARN_ON(I915_READ(SDEIER) != 0);
3104 I915_WRITE(SDEIER, 0xffffffff);
3105 POSTING_READ(SDEIER);
3106 }
3107
3108 static void gen5_gt_irq_reset(struct drm_device *dev)
3109 {
3110 struct drm_i915_private *dev_priv = dev->dev_private;
3111
3112 GEN5_IRQ_RESET(GT);
3113 if (INTEL_INFO(dev)->gen >= 6)
3114 GEN5_IRQ_RESET(GEN6_PM);
3115 }
3116
3117 /* drm_dma.h hooks
3118 */
3119 static void ironlake_irq_reset(struct drm_device *dev)
3120 {
3121 struct drm_i915_private *dev_priv = dev->dev_private;
3122
3123 I915_WRITE(HWSTAM, 0xffffffff);
3124
3125 GEN5_IRQ_RESET(DE);
3126 if (IS_GEN7(dev))
3127 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3128
3129 gen5_gt_irq_reset(dev);
3130
3131 ibx_irq_reset(dev);
3132 }
3133
3134 static void valleyview_irq_preinstall(struct drm_device *dev)
3135 {
3136 struct drm_i915_private *dev_priv = dev->dev_private;
3137 int pipe;
3138
3139 /* VLV magic */
3140 I915_WRITE(VLV_IMR, 0);
3141 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
3142 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
3143 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
3144
3145 /* and GT */
3146 I915_WRITE(GTIIR, I915_READ(GTIIR));
3147 I915_WRITE(GTIIR, I915_READ(GTIIR));
3148
3149 gen5_gt_irq_reset(dev);
3150
3151 I915_WRITE(DPINVGTT, 0xff);
3152
3153 I915_WRITE(PORT_HOTPLUG_EN, 0);
3154 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3155 for_each_pipe(dev_priv, pipe)
3156 I915_WRITE(PIPESTAT(pipe), 0xffff);
3157 I915_WRITE(VLV_IIR, 0xffffffff);
3158 I915_WRITE(VLV_IMR, 0xffffffff);
3159 I915_WRITE(VLV_IER, 0x0);
3160 POSTING_READ(VLV_IER);
3161 }
3162
3163 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3164 {
3165 GEN8_IRQ_RESET_NDX(GT, 0);
3166 GEN8_IRQ_RESET_NDX(GT, 1);
3167 GEN8_IRQ_RESET_NDX(GT, 2);
3168 GEN8_IRQ_RESET_NDX(GT, 3);
3169 }
3170
3171 static void gen8_irq_reset(struct drm_device *dev)
3172 {
3173 struct drm_i915_private *dev_priv = dev->dev_private;
3174 int pipe;
3175
3176 I915_WRITE(GEN8_MASTER_IRQ, 0);
3177 POSTING_READ(GEN8_MASTER_IRQ);
3178
3179 gen8_gt_irq_reset(dev_priv);
3180
3181 for_each_pipe(dev_priv, pipe)
3182 if (intel_display_power_is_enabled(dev_priv,
3183 POWER_DOMAIN_PIPE(pipe)))
3184 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3185
3186 GEN5_IRQ_RESET(GEN8_DE_PORT_);
3187 GEN5_IRQ_RESET(GEN8_DE_MISC_);
3188 GEN5_IRQ_RESET(GEN8_PCU_);
3189
3190 ibx_irq_reset(dev);
3191 }
3192
3193 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv)
3194 {
3195 uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3196
3197 spin_lock_irq(&dev_priv->irq_lock);
3198 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B],
3199 ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
3200 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C],
3201 ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
3202 spin_unlock_irq(&dev_priv->irq_lock);
3203 }
3204
3205 static void cherryview_irq_preinstall(struct drm_device *dev)
3206 {
3207 struct drm_i915_private *dev_priv = dev->dev_private;
3208 int pipe;
3209
3210 I915_WRITE(GEN8_MASTER_IRQ, 0);
3211 POSTING_READ(GEN8_MASTER_IRQ);
3212
3213 gen8_gt_irq_reset(dev_priv);
3214
3215 GEN5_IRQ_RESET(GEN8_PCU_);
3216
3217 POSTING_READ(GEN8_PCU_IIR);
3218
3219 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3220
3221 I915_WRITE(PORT_HOTPLUG_EN, 0);
3222 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3223
3224 for_each_pipe(dev_priv, pipe)
3225 I915_WRITE(PIPESTAT(pipe), 0xffff);
3226
3227 I915_WRITE(VLV_IMR, 0xffffffff);
3228 I915_WRITE(VLV_IER, 0x0);
3229 I915_WRITE(VLV_IIR, 0xffffffff);
3230 POSTING_READ(VLV_IIR);
3231 }
3232
3233 static void ibx_hpd_irq_setup(struct drm_device *dev)
3234 {
3235 struct drm_i915_private *dev_priv = dev->dev_private;
3236 struct intel_encoder *intel_encoder;
3237 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
3238
3239 if (HAS_PCH_IBX(dev)) {
3240 hotplug_irqs = SDE_HOTPLUG_MASK;
3241 for_each_intel_encoder(dev, intel_encoder)
3242 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3243 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
3244 } else {
3245 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3246 for_each_intel_encoder(dev, intel_encoder)
3247 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3248 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
3249 }
3250
3251 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3252
3253 /*
3254 * Enable digital hotplug on the PCH, and configure the DP short pulse
3255 * duration to 2ms (which is the minimum in the Display Port spec)
3256 *
3257 * This register is the same on all known PCH chips.
3258 */
3259 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3260 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3261 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3262 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3263 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3264 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3265 }
3266
3267 static void ibx_irq_postinstall(struct drm_device *dev)
3268 {
3269 struct drm_i915_private *dev_priv = dev->dev_private;
3270 u32 mask;
3271
3272 if (HAS_PCH_NOP(dev))
3273 return;
3274
3275 if (HAS_PCH_IBX(dev))
3276 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3277 else
3278 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3279
3280 GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
3281 I915_WRITE(SDEIMR, ~mask);
3282 }
3283
3284 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3285 {
3286 struct drm_i915_private *dev_priv = dev->dev_private;
3287 u32 pm_irqs, gt_irqs;
3288
3289 pm_irqs = gt_irqs = 0;
3290
3291 dev_priv->gt_irq_mask = ~0;
3292 if (HAS_L3_DPF(dev)) {
3293 /* L3 parity interrupt is always unmasked. */
3294 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3295 gt_irqs |= GT_PARITY_ERROR(dev);
3296 }
3297
3298 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3299 if (IS_GEN5(dev)) {
3300 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3301 ILK_BSD_USER_INTERRUPT;
3302 } else {
3303 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3304 }
3305
3306 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3307
3308 if (INTEL_INFO(dev)->gen >= 6) {
3309 pm_irqs |= dev_priv->pm_rps_events;
3310
3311 if (HAS_VEBOX(dev))
3312 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3313
3314 dev_priv->pm_irq_mask = 0xffffffff;
3315 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3316 }
3317 }
3318
3319 static int ironlake_irq_postinstall(struct drm_device *dev)
3320 {
3321 struct drm_i915_private *dev_priv = dev->dev_private;
3322 u32 display_mask, extra_mask;
3323
3324 if (INTEL_INFO(dev)->gen >= 7) {
3325 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3326 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3327 DE_PLANEB_FLIP_DONE_IVB |
3328 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3329 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3330 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
3331 } else {
3332 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3333 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3334 DE_AUX_CHANNEL_A |
3335 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3336 DE_POISON);
3337 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3338 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
3339 }
3340
3341 dev_priv->irq_mask = ~display_mask;
3342
3343 I915_WRITE(HWSTAM, 0xeffe);
3344
3345 ibx_irq_pre_postinstall(dev);
3346
3347 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3348
3349 gen5_gt_irq_postinstall(dev);
3350
3351 ibx_irq_postinstall(dev);
3352
3353 if (IS_IRONLAKE_M(dev)) {
3354 /* Enable PCU event interrupts
3355 *
3356 * spinlocking not required here for correctness since interrupt
3357 * setup is guaranteed to run in single-threaded context. But we
3358 * need it to make the assert_spin_locked happy. */
3359 spin_lock_irq(&dev_priv->irq_lock);
3360 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
3361 spin_unlock_irq(&dev_priv->irq_lock);
3362 }
3363
3364 return 0;
3365 }
3366
3367 static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3368 {
3369 u32 pipestat_mask;
3370 u32 iir_mask;
3371
3372 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3373 PIPE_FIFO_UNDERRUN_STATUS;
3374
3375 I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3376 I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3377 POSTING_READ(PIPESTAT(PIPE_A));
3378
3379 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3380 PIPE_CRC_DONE_INTERRUPT_STATUS;
3381
3382 i915_enable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3383 PIPE_GMBUS_INTERRUPT_STATUS);
3384 i915_enable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3385
3386 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3387 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3388 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3389 dev_priv->irq_mask &= ~iir_mask;
3390
3391 I915_WRITE(VLV_IIR, iir_mask);
3392 I915_WRITE(VLV_IIR, iir_mask);
3393 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3394 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3395 POSTING_READ(VLV_IER);
3396 }
3397
3398 static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3399 {
3400 u32 pipestat_mask;
3401 u32 iir_mask;
3402
3403 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3404 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3405 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3406
3407 dev_priv->irq_mask |= iir_mask;
3408 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3409 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3410 I915_WRITE(VLV_IIR, iir_mask);
3411 I915_WRITE(VLV_IIR, iir_mask);
3412 POSTING_READ(VLV_IIR);
3413
3414 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3415 PIPE_CRC_DONE_INTERRUPT_STATUS;
3416
3417 i915_disable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3418 PIPE_GMBUS_INTERRUPT_STATUS);
3419 i915_disable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3420
3421 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3422 PIPE_FIFO_UNDERRUN_STATUS;
3423 I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3424 I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3425 POSTING_READ(PIPESTAT(PIPE_A));
3426 }
3427
3428 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3429 {
3430 assert_spin_locked(&dev_priv->irq_lock);
3431
3432 if (dev_priv->display_irqs_enabled)
3433 return;
3434
3435 dev_priv->display_irqs_enabled = true;
3436
3437 if (intel_irqs_enabled(dev_priv))
3438 valleyview_display_irqs_install(dev_priv);
3439 }
3440
3441 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3442 {
3443 assert_spin_locked(&dev_priv->irq_lock);
3444
3445 if (!dev_priv->display_irqs_enabled)
3446 return;
3447
3448 dev_priv->display_irqs_enabled = false;
3449
3450 if (intel_irqs_enabled(dev_priv))
3451 valleyview_display_irqs_uninstall(dev_priv);
3452 }
3453
3454 static int valleyview_irq_postinstall(struct drm_device *dev)
3455 {
3456 struct drm_i915_private *dev_priv = dev->dev_private;
3457
3458 dev_priv->irq_mask = ~0;
3459
3460 I915_WRITE(PORT_HOTPLUG_EN, 0);
3461 POSTING_READ(PORT_HOTPLUG_EN);
3462
3463 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3464 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3465 I915_WRITE(VLV_IIR, 0xffffffff);
3466 POSTING_READ(VLV_IER);
3467
3468 /* Interrupt setup is already guaranteed to be single-threaded, this is
3469 * just to make the assert_spin_locked check happy. */
3470 spin_lock_irq(&dev_priv->irq_lock);
3471 if (dev_priv->display_irqs_enabled)
3472 valleyview_display_irqs_install(dev_priv);
3473 spin_unlock_irq(&dev_priv->irq_lock);
3474
3475 I915_WRITE(VLV_IIR, 0xffffffff);
3476 I915_WRITE(VLV_IIR, 0xffffffff);
3477
3478 gen5_gt_irq_postinstall(dev);
3479
3480 /* ack & enable invalid PTE error interrupts */
3481 #if 0 /* FIXME: add support to irq handler for checking these bits */
3482 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3483 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3484 #endif
3485
3486 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3487
3488 return 0;
3489 }
3490
3491 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3492 {
3493 /* These are interrupts we'll toggle with the ring mask register */
3494 uint32_t gt_interrupts[] = {
3495 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3496 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3497 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3498 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3499 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3500 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3501 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3502 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3503 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3504 0,
3505 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3506 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3507 };
3508
3509 dev_priv->pm_irq_mask = 0xffffffff;
3510 GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3511 GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3512 GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, dev_priv->pm_rps_events);
3513 GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3514 }
3515
3516 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3517 {
3518 uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3519 uint32_t de_pipe_enables;
3520 int pipe;
3521
3522 if (IS_GEN9(dev_priv))
3523 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3524 GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3525 else
3526 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3527 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3528
3529 de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3530 GEN8_PIPE_FIFO_UNDERRUN;
3531
3532 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3533 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3534 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3535
3536 for_each_pipe(dev_priv, pipe)
3537 if (intel_display_power_is_enabled(dev_priv,
3538 POWER_DOMAIN_PIPE(pipe)))
3539 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3540 dev_priv->de_irq_mask[pipe],
3541 de_pipe_enables);
3542
3543 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~GEN8_AUX_CHANNEL_A, GEN8_AUX_CHANNEL_A);
3544 }
3545
3546 static int gen8_irq_postinstall(struct drm_device *dev)
3547 {
3548 struct drm_i915_private *dev_priv = dev->dev_private;
3549
3550 ibx_irq_pre_postinstall(dev);
3551
3552 gen8_gt_irq_postinstall(dev_priv);
3553 gen8_de_irq_postinstall(dev_priv);
3554
3555 ibx_irq_postinstall(dev);
3556
3557 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3558 POSTING_READ(GEN8_MASTER_IRQ);
3559
3560 return 0;
3561 }
3562
3563 static int cherryview_irq_postinstall(struct drm_device *dev)
3564 {
3565 struct drm_i915_private *dev_priv = dev->dev_private;
3566 u32 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
3567 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3568 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3569 I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3570 u32 pipestat_enable = PLANE_FLIP_DONE_INT_STATUS_VLV |
3571 PIPE_CRC_DONE_INTERRUPT_STATUS;
3572 int pipe;
3573
3574 /*
3575 * Leave vblank interrupts masked initially. enable/disable will
3576 * toggle them based on usage.
3577 */
3578 dev_priv->irq_mask = ~enable_mask;
3579
3580 for_each_pipe(dev_priv, pipe)
3581 I915_WRITE(PIPESTAT(pipe), 0xffff);
3582
3583 spin_lock_irq(&dev_priv->irq_lock);
3584 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3585 for_each_pipe(dev_priv, pipe)
3586 i915_enable_pipestat(dev_priv, pipe, pipestat_enable);
3587 spin_unlock_irq(&dev_priv->irq_lock);
3588
3589 I915_WRITE(VLV_IIR, 0xffffffff);
3590 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3591 I915_WRITE(VLV_IER, enable_mask);
3592
3593 gen8_gt_irq_postinstall(dev_priv);
3594
3595 I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
3596 POSTING_READ(GEN8_MASTER_IRQ);
3597
3598 return 0;
3599 }
3600
3601 static void gen8_irq_uninstall(struct drm_device *dev)
3602 {
3603 struct drm_i915_private *dev_priv = dev->dev_private;
3604
3605 if (!dev_priv)
3606 return;
3607
3608 gen8_irq_reset(dev);
3609 }
3610
3611 static void valleyview_irq_uninstall(struct drm_device *dev)
3612 {
3613 struct drm_i915_private *dev_priv = dev->dev_private;
3614 int pipe;
3615
3616 if (!dev_priv)
3617 return;
3618
3619 I915_WRITE(VLV_MASTER_IER, 0);
3620
3621 for_each_pipe(dev_priv, pipe)
3622 I915_WRITE(PIPESTAT(pipe), 0xffff);
3623
3624 I915_WRITE(HWSTAM, 0xffffffff);
3625 I915_WRITE(PORT_HOTPLUG_EN, 0);
3626 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3627
3628 /* Interrupt setup is already guaranteed to be single-threaded, this is
3629 * just to make the assert_spin_locked check happy. */
3630 spin_lock_irq(&dev_priv->irq_lock);
3631 if (dev_priv->display_irqs_enabled)
3632 valleyview_display_irqs_uninstall(dev_priv);
3633 spin_unlock_irq(&dev_priv->irq_lock);
3634
3635 dev_priv->irq_mask = 0;
3636
3637 I915_WRITE(VLV_IIR, 0xffffffff);
3638 I915_WRITE(VLV_IMR, 0xffffffff);
3639 I915_WRITE(VLV_IER, 0x0);
3640 POSTING_READ(VLV_IER);
3641 }
3642
3643 static void cherryview_irq_uninstall(struct drm_device *dev)
3644 {
3645 struct drm_i915_private *dev_priv = dev->dev_private;
3646 int pipe;
3647
3648 if (!dev_priv)
3649 return;
3650
3651 I915_WRITE(GEN8_MASTER_IRQ, 0);
3652 POSTING_READ(GEN8_MASTER_IRQ);
3653
3654 #define GEN8_IRQ_FINI_NDX(type, which) \
3655 do { \
3656 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
3657 I915_WRITE(GEN8_##type##_IER(which), 0); \
3658 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
3659 POSTING_READ(GEN8_##type##_IIR(which)); \
3660 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
3661 } while (0)
3662
3663 #define GEN8_IRQ_FINI(type) \
3664 do { \
3665 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
3666 I915_WRITE(GEN8_##type##_IER, 0); \
3667 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
3668 POSTING_READ(GEN8_##type##_IIR); \
3669 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
3670 } while (0)
3671
3672 GEN8_IRQ_FINI_NDX(GT, 0);
3673 GEN8_IRQ_FINI_NDX(GT, 1);
3674 GEN8_IRQ_FINI_NDX(GT, 2);
3675 GEN8_IRQ_FINI_NDX(GT, 3);
3676
3677 GEN8_IRQ_FINI(PCU);
3678
3679 #undef GEN8_IRQ_FINI
3680 #undef GEN8_IRQ_FINI_NDX
3681
3682 I915_WRITE(PORT_HOTPLUG_EN, 0);
3683 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3684
3685 for_each_pipe(dev_priv, pipe)
3686 I915_WRITE(PIPESTAT(pipe), 0xffff);
3687
3688 I915_WRITE(VLV_IMR, 0xffffffff);
3689 I915_WRITE(VLV_IER, 0x0);
3690 I915_WRITE(VLV_IIR, 0xffffffff);
3691 POSTING_READ(VLV_IIR);
3692 }
3693
3694 static void ironlake_irq_uninstall(struct drm_device *dev)
3695 {
3696 struct drm_i915_private *dev_priv = dev->dev_private;
3697
3698 if (!dev_priv)
3699 return;
3700
3701 ironlake_irq_reset(dev);
3702 }
3703
3704 static void i8xx_irq_preinstall(struct drm_device * dev)
3705 {
3706 struct drm_i915_private *dev_priv = dev->dev_private;
3707 int pipe;
3708
3709 for_each_pipe(dev_priv, pipe)
3710 I915_WRITE(PIPESTAT(pipe), 0);
3711 I915_WRITE16(IMR, 0xffff);
3712 I915_WRITE16(IER, 0x0);
3713 POSTING_READ16(IER);
3714 }
3715
3716 static int i8xx_irq_postinstall(struct drm_device *dev)
3717 {
3718 struct drm_i915_private *dev_priv = dev->dev_private;
3719
3720 I915_WRITE16(EMR,
3721 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3722
3723 /* Unmask the interrupts that we always want on. */
3724 dev_priv->irq_mask =
3725 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3726 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3727 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3728 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3729 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3730 I915_WRITE16(IMR, dev_priv->irq_mask);
3731
3732 I915_WRITE16(IER,
3733 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3734 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3735 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3736 I915_USER_INTERRUPT);
3737 POSTING_READ16(IER);
3738
3739 /* Interrupt setup is already guaranteed to be single-threaded, this is
3740 * just to make the assert_spin_locked check happy. */
3741 spin_lock_irq(&dev_priv->irq_lock);
3742 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3743 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3744 spin_unlock_irq(&dev_priv->irq_lock);
3745
3746 return 0;
3747 }
3748
3749 /*
3750 * Returns true when a page flip has completed.
3751 */
3752 static bool i8xx_handle_vblank(struct drm_device *dev,
3753 int plane, int pipe, u32 iir)
3754 {
3755 struct drm_i915_private *dev_priv = dev->dev_private;
3756 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3757
3758 if (!intel_pipe_handle_vblank(dev, pipe))
3759 return false;
3760
3761 if ((iir & flip_pending) == 0)
3762 goto check_page_flip;
3763
3764 intel_prepare_page_flip(dev, plane);
3765
3766 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3767 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3768 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3769 * the flip is completed (no longer pending). Since this doesn't raise
3770 * an interrupt per se, we watch for the change at vblank.
3771 */
3772 if (I915_READ16(ISR) & flip_pending)
3773 goto check_page_flip;
3774
3775 intel_finish_page_flip(dev, pipe);
3776 return true;
3777
3778 check_page_flip:
3779 intel_check_page_flip(dev, pipe);
3780 return false;
3781 }
3782
3783 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3784 {
3785 struct drm_device *dev = arg;
3786 struct drm_i915_private *dev_priv = dev->dev_private;
3787 u16 iir, new_iir;
3788 u32 pipe_stats[2];
3789 int pipe;
3790 u16 flip_mask =
3791 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3792 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3793
3794 iir = I915_READ16(IIR);
3795 if (iir == 0)
3796 return IRQ_NONE;
3797
3798 while (iir & ~flip_mask) {
3799 /* Can't rely on pipestat interrupt bit in iir as it might
3800 * have been cleared after the pipestat interrupt was received.
3801 * It doesn't set the bit in iir again, but it still produces
3802 * interrupts (for non-MSI).
3803 */
3804 spin_lock(&dev_priv->irq_lock);
3805 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3806 i915_handle_error(dev, false,
3807 "Command parser error, iir 0x%08x",
3808 iir);
3809
3810 for_each_pipe(dev_priv, pipe) {
3811 int reg = PIPESTAT(pipe);
3812 pipe_stats[pipe] = I915_READ(reg);
3813
3814 /*
3815 * Clear the PIPE*STAT regs before the IIR
3816 */
3817 if (pipe_stats[pipe] & 0x8000ffff)
3818 I915_WRITE(reg, pipe_stats[pipe]);
3819 }
3820 spin_unlock(&dev_priv->irq_lock);
3821
3822 I915_WRITE16(IIR, iir & ~flip_mask);
3823 new_iir = I915_READ16(IIR); /* Flush posted writes */
3824
3825 i915_update_dri1_breadcrumb(dev);
3826
3827 if (iir & I915_USER_INTERRUPT)
3828 notify_ring(dev, &dev_priv->ring[RCS]);
3829
3830 for_each_pipe(dev_priv, pipe) {
3831 int plane = pipe;
3832 if (HAS_FBC(dev))
3833 plane = !plane;
3834
3835 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3836 i8xx_handle_vblank(dev, plane, pipe, iir))
3837 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3838
3839 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3840 i9xx_pipe_crc_irq_handler(dev, pipe);
3841
3842 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3843 intel_set_cpu_fifo_underrun_reporting(dev_priv,
3844 pipe, false))
3845 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3846 }
3847
3848 iir = new_iir;
3849 }
3850
3851 return IRQ_HANDLED;
3852 }
3853
3854 static void i8xx_irq_uninstall(struct drm_device * dev)
3855 {
3856 struct drm_i915_private *dev_priv = dev->dev_private;
3857 int pipe;
3858
3859 for_each_pipe(dev_priv, pipe) {
3860 /* Clear enable bits; then clear status bits */
3861 I915_WRITE(PIPESTAT(pipe), 0);
3862 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3863 }
3864 I915_WRITE16(IMR, 0xffff);
3865 I915_WRITE16(IER, 0x0);
3866 I915_WRITE16(IIR, I915_READ16(IIR));
3867 }
3868
3869 static void i915_irq_preinstall(struct drm_device * dev)
3870 {
3871 struct drm_i915_private *dev_priv = dev->dev_private;
3872 int pipe;
3873
3874 if (I915_HAS_HOTPLUG(dev)) {
3875 I915_WRITE(PORT_HOTPLUG_EN, 0);
3876 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3877 }
3878
3879 I915_WRITE16(HWSTAM, 0xeffe);
3880 for_each_pipe(dev_priv, pipe)
3881 I915_WRITE(PIPESTAT(pipe), 0);
3882 I915_WRITE(IMR, 0xffffffff);
3883 I915_WRITE(IER, 0x0);
3884 POSTING_READ(IER);
3885 }
3886
3887 static int i915_irq_postinstall(struct drm_device *dev)
3888 {
3889 struct drm_i915_private *dev_priv = dev->dev_private;
3890 u32 enable_mask;
3891
3892 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3893
3894 /* Unmask the interrupts that we always want on. */
3895 dev_priv->irq_mask =
3896 ~(I915_ASLE_INTERRUPT |
3897 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3898 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3899 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3900 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3901 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3902
3903 enable_mask =
3904 I915_ASLE_INTERRUPT |
3905 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3906 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3907 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3908 I915_USER_INTERRUPT;
3909
3910 if (I915_HAS_HOTPLUG(dev)) {
3911 I915_WRITE(PORT_HOTPLUG_EN, 0);
3912 POSTING_READ(PORT_HOTPLUG_EN);
3913
3914 /* Enable in IER... */
3915 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3916 /* and unmask in IMR */
3917 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3918 }
3919
3920 I915_WRITE(IMR, dev_priv->irq_mask);
3921 I915_WRITE(IER, enable_mask);
3922 POSTING_READ(IER);
3923
3924 i915_enable_asle_pipestat(dev);
3925
3926 /* Interrupt setup is already guaranteed to be single-threaded, this is
3927 * just to make the assert_spin_locked check happy. */
3928 spin_lock_irq(&dev_priv->irq_lock);
3929 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3930 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3931 spin_unlock_irq(&dev_priv->irq_lock);
3932
3933 return 0;
3934 }
3935
3936 /*
3937 * Returns true when a page flip has completed.
3938 */
3939 static bool i915_handle_vblank(struct drm_device *dev,
3940 int plane, int pipe, u32 iir)
3941 {
3942 struct drm_i915_private *dev_priv = dev->dev_private;
3943 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3944
3945 if (!intel_pipe_handle_vblank(dev, pipe))
3946 return false;
3947
3948 if ((iir & flip_pending) == 0)
3949 goto check_page_flip;
3950
3951 intel_prepare_page_flip(dev, plane);
3952
3953 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3954 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3955 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3956 * the flip is completed (no longer pending). Since this doesn't raise
3957 * an interrupt per se, we watch for the change at vblank.
3958 */
3959 if (I915_READ(ISR) & flip_pending)
3960 goto check_page_flip;
3961
3962 intel_finish_page_flip(dev, pipe);
3963 return true;
3964
3965 check_page_flip:
3966 intel_check_page_flip(dev, pipe);
3967 return false;
3968 }
3969
3970 static irqreturn_t i915_irq_handler(int irq, void *arg)
3971 {
3972 struct drm_device *dev = arg;
3973 struct drm_i915_private *dev_priv = dev->dev_private;
3974 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3975 u32 flip_mask =
3976 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3977 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3978 int pipe, ret = IRQ_NONE;
3979
3980 iir = I915_READ(IIR);
3981 do {
3982 bool irq_received = (iir & ~flip_mask) != 0;
3983 bool blc_event = false;
3984
3985 /* Can't rely on pipestat interrupt bit in iir as it might
3986 * have been cleared after the pipestat interrupt was received.
3987 * It doesn't set the bit in iir again, but it still produces
3988 * interrupts (for non-MSI).
3989 */
3990 spin_lock(&dev_priv->irq_lock);
3991 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3992 i915_handle_error(dev, false,
3993 "Command parser error, iir 0x%08x",
3994 iir);
3995
3996 for_each_pipe(dev_priv, pipe) {
3997 int reg = PIPESTAT(pipe);
3998 pipe_stats[pipe] = I915_READ(reg);
3999
4000 /* Clear the PIPE*STAT regs before the IIR */
4001 if (pipe_stats[pipe] & 0x8000ffff) {
4002 I915_WRITE(reg, pipe_stats[pipe]);
4003 irq_received = true;
4004 }
4005 }
4006 spin_unlock(&dev_priv->irq_lock);
4007
4008 if (!irq_received)
4009 break;
4010
4011 /* Consume port. Then clear IIR or we'll miss events */
4012 if (I915_HAS_HOTPLUG(dev) &&
4013 iir & I915_DISPLAY_PORT_INTERRUPT)
4014 i9xx_hpd_irq_handler(dev);
4015
4016 I915_WRITE(IIR, iir & ~flip_mask);
4017 new_iir = I915_READ(IIR); /* Flush posted writes */
4018
4019 if (iir & I915_USER_INTERRUPT)
4020 notify_ring(dev, &dev_priv->ring[RCS]);
4021
4022 for_each_pipe(dev_priv, pipe) {
4023 int plane = pipe;
4024 if (HAS_FBC(dev))
4025 plane = !plane;
4026
4027 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4028 i915_handle_vblank(dev, plane, pipe, iir))
4029 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4030
4031 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4032 blc_event = true;
4033
4034 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4035 i9xx_pipe_crc_irq_handler(dev, pipe);
4036
4037 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
4038 intel_set_cpu_fifo_underrun_reporting(dev_priv,
4039 pipe, false))
4040 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
4041 }
4042
4043 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4044 intel_opregion_asle_intr(dev);
4045
4046 /* With MSI, interrupts are only generated when iir
4047 * transitions from zero to nonzero. If another bit got
4048 * set while we were handling the existing iir bits, then
4049 * we would never get another interrupt.
4050 *
4051 * This is fine on non-MSI as well, as if we hit this path
4052 * we avoid exiting the interrupt handler only to generate
4053 * another one.
4054 *
4055 * Note that for MSI this could cause a stray interrupt report
4056 * if an interrupt landed in the time between writing IIR and
4057 * the posting read. This should be rare enough to never
4058 * trigger the 99% of 100,000 interrupts test for disabling
4059 * stray interrupts.
4060 */
4061 ret = IRQ_HANDLED;
4062 iir = new_iir;
4063 } while (iir & ~flip_mask);
4064
4065 i915_update_dri1_breadcrumb(dev);
4066
4067 return ret;
4068 }
4069
4070 static void i915_irq_uninstall(struct drm_device * dev)
4071 {
4072 struct drm_i915_private *dev_priv = dev->dev_private;
4073 int pipe;
4074
4075 if (I915_HAS_HOTPLUG(dev)) {
4076 I915_WRITE(PORT_HOTPLUG_EN, 0);
4077 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4078 }
4079
4080 I915_WRITE16(HWSTAM, 0xffff);
4081 for_each_pipe(dev_priv, pipe) {
4082 /* Clear enable bits; then clear status bits */
4083 I915_WRITE(PIPESTAT(pipe), 0);
4084 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4085 }
4086 I915_WRITE(IMR, 0xffffffff);
4087 I915_WRITE(IER, 0x0);
4088
4089 I915_WRITE(IIR, I915_READ(IIR));
4090 }
4091
4092 static void i965_irq_preinstall(struct drm_device * dev)
4093 {
4094 struct drm_i915_private *dev_priv = dev->dev_private;
4095 int pipe;
4096
4097 I915_WRITE(PORT_HOTPLUG_EN, 0);
4098 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4099
4100 I915_WRITE(HWSTAM, 0xeffe);
4101 for_each_pipe(dev_priv, pipe)
4102 I915_WRITE(PIPESTAT(pipe), 0);
4103 I915_WRITE(IMR, 0xffffffff);
4104 I915_WRITE(IER, 0x0);
4105 POSTING_READ(IER);
4106 }
4107
4108 static int i965_irq_postinstall(struct drm_device *dev)
4109 {
4110 struct drm_i915_private *dev_priv = dev->dev_private;
4111 u32 enable_mask;
4112 u32 error_mask;
4113
4114 /* Unmask the interrupts that we always want on. */
4115 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4116 I915_DISPLAY_PORT_INTERRUPT |
4117 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4118 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4119 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4120 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4121 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4122
4123 enable_mask = ~dev_priv->irq_mask;
4124 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4125 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4126 enable_mask |= I915_USER_INTERRUPT;
4127
4128 if (IS_G4X(dev))
4129 enable_mask |= I915_BSD_USER_INTERRUPT;
4130
4131 /* Interrupt setup is already guaranteed to be single-threaded, this is
4132 * just to make the assert_spin_locked check happy. */
4133 spin_lock_irq(&dev_priv->irq_lock);
4134 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4135 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4136 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4137 spin_unlock_irq(&dev_priv->irq_lock);
4138
4139 /*
4140 * Enable some error detection, note the instruction error mask
4141 * bit is reserved, so we leave it masked.
4142 */
4143 if (IS_G4X(dev)) {
4144 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4145 GM45_ERROR_MEM_PRIV |
4146 GM45_ERROR_CP_PRIV |
4147 I915_ERROR_MEMORY_REFRESH);
4148 } else {
4149 error_mask = ~(I915_ERROR_PAGE_TABLE |
4150 I915_ERROR_MEMORY_REFRESH);
4151 }
4152 I915_WRITE(EMR, error_mask);
4153
4154 I915_WRITE(IMR, dev_priv->irq_mask);
4155 I915_WRITE(IER, enable_mask);
4156 POSTING_READ(IER);
4157
4158 I915_WRITE(PORT_HOTPLUG_EN, 0);
4159 POSTING_READ(PORT_HOTPLUG_EN);
4160
4161 i915_enable_asle_pipestat(dev);
4162
4163 return 0;
4164 }
4165
4166 static void i915_hpd_irq_setup(struct drm_device *dev)
4167 {
4168 struct drm_i915_private *dev_priv = dev->dev_private;
4169 struct intel_encoder *intel_encoder;
4170 u32 hotplug_en;
4171
4172 assert_spin_locked(&dev_priv->irq_lock);
4173
4174 if (I915_HAS_HOTPLUG(dev)) {
4175 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
4176 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
4177 /* Note HDMI and DP share hotplug bits */
4178 /* enable bits are the same for all generations */
4179 for_each_intel_encoder(dev, intel_encoder)
4180 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
4181 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
4182 /* Programming the CRT detection parameters tends
4183 to generate a spurious hotplug event about three
4184 seconds later. So just do it once.
4185 */
4186 if (IS_G4X(dev))
4187 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4188 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
4189 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4190
4191 /* Ignore TV since it's buggy */
4192 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
4193 }
4194 }
4195
4196 static irqreturn_t i965_irq_handler(int irq, void *arg)
4197 {
4198 struct drm_device *dev = arg;
4199 struct drm_i915_private *dev_priv = dev->dev_private;
4200 u32 iir, new_iir;
4201 u32 pipe_stats[I915_MAX_PIPES];
4202 int ret = IRQ_NONE, pipe;
4203 u32 flip_mask =
4204 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4205 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4206
4207 iir = I915_READ(IIR);
4208
4209 for (;;) {
4210 bool irq_received = (iir & ~flip_mask) != 0;
4211 bool blc_event = false;
4212
4213 /* Can't rely on pipestat interrupt bit in iir as it might
4214 * have been cleared after the pipestat interrupt was received.
4215 * It doesn't set the bit in iir again, but it still produces
4216 * interrupts (for non-MSI).
4217 */
4218 spin_lock(&dev_priv->irq_lock);
4219 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4220 i915_handle_error(dev, false,
4221 "Command parser error, iir 0x%08x",
4222 iir);
4223
4224 for_each_pipe(dev_priv, pipe) {
4225 int reg = PIPESTAT(pipe);
4226 pipe_stats[pipe] = I915_READ(reg);
4227
4228 /*
4229 * Clear the PIPE*STAT regs before the IIR
4230 */
4231 if (pipe_stats[pipe] & 0x8000ffff) {
4232 I915_WRITE(reg, pipe_stats[pipe]);
4233 irq_received = true;
4234 }
4235 }
4236 spin_unlock(&dev_priv->irq_lock);
4237
4238 if (!irq_received)
4239 break;
4240
4241 ret = IRQ_HANDLED;
4242
4243 /* Consume port. Then clear IIR or we'll miss events */
4244 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4245 i9xx_hpd_irq_handler(dev);
4246
4247 I915_WRITE(IIR, iir & ~flip_mask);
4248 new_iir = I915_READ(IIR); /* Flush posted writes */
4249
4250 if (iir & I915_USER_INTERRUPT)
4251 notify_ring(dev, &dev_priv->ring[RCS]);
4252 if (iir & I915_BSD_USER_INTERRUPT)
4253 notify_ring(dev, &dev_priv->ring[VCS]);
4254
4255 for_each_pipe(dev_priv, pipe) {
4256 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4257 i915_handle_vblank(dev, pipe, pipe, iir))
4258 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4259
4260 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4261 blc_event = true;
4262
4263 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4264 i9xx_pipe_crc_irq_handler(dev, pipe);
4265
4266 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
4267 intel_set_cpu_fifo_underrun_reporting(dev_priv,
4268 pipe, false))
4269 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
4270 }
4271
4272 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4273 intel_opregion_asle_intr(dev);
4274
4275 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4276 gmbus_irq_handler(dev);
4277
4278 /* With MSI, interrupts are only generated when iir
4279 * transitions from zero to nonzero. If another bit got
4280 * set while we were handling the existing iir bits, then
4281 * we would never get another interrupt.
4282 *
4283 * This is fine on non-MSI as well, as if we hit this path
4284 * we avoid exiting the interrupt handler only to generate
4285 * another one.
4286 *
4287 * Note that for MSI this could cause a stray interrupt report
4288 * if an interrupt landed in the time between writing IIR and
4289 * the posting read. This should be rare enough to never
4290 * trigger the 99% of 100,000 interrupts test for disabling
4291 * stray interrupts.
4292 */
4293 iir = new_iir;
4294 }
4295
4296 i915_update_dri1_breadcrumb(dev);
4297
4298 return ret;
4299 }
4300
4301 static void i965_irq_uninstall(struct drm_device * dev)
4302 {
4303 struct drm_i915_private *dev_priv = dev->dev_private;
4304 int pipe;
4305
4306 if (!dev_priv)
4307 return;
4308
4309 I915_WRITE(PORT_HOTPLUG_EN, 0);
4310 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4311
4312 I915_WRITE(HWSTAM, 0xffffffff);
4313 for_each_pipe(dev_priv, pipe)
4314 I915_WRITE(PIPESTAT(pipe), 0);
4315 I915_WRITE(IMR, 0xffffffff);
4316 I915_WRITE(IER, 0x0);
4317
4318 for_each_pipe(dev_priv, pipe)
4319 I915_WRITE(PIPESTAT(pipe),
4320 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4321 I915_WRITE(IIR, I915_READ(IIR));
4322 }
4323
4324 static void intel_hpd_irq_reenable_work(struct work_struct *work)
4325 {
4326 struct drm_i915_private *dev_priv =
4327 container_of(work, typeof(*dev_priv),
4328 hotplug_reenable_work.work);
4329 struct drm_device *dev = dev_priv->dev;
4330 struct drm_mode_config *mode_config = &dev->mode_config;
4331 int i;
4332
4333 intel_runtime_pm_get(dev_priv);
4334
4335 spin_lock_irq(&dev_priv->irq_lock);
4336 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
4337 struct drm_connector *connector;
4338
4339 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
4340 continue;
4341
4342 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4343
4344 list_for_each_entry(connector, &mode_config->connector_list, head) {
4345 struct intel_connector *intel_connector = to_intel_connector(connector);
4346
4347 if (intel_connector->encoder->hpd_pin == i) {
4348 if (connector->polled != intel_connector->polled)
4349 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
4350 connector->name);
4351 connector->polled = intel_connector->polled;
4352 if (!connector->polled)
4353 connector->polled = DRM_CONNECTOR_POLL_HPD;
4354 }
4355 }
4356 }
4357 if (dev_priv->display.hpd_irq_setup)
4358 dev_priv->display.hpd_irq_setup(dev);
4359 spin_unlock_irq(&dev_priv->irq_lock);
4360
4361 intel_runtime_pm_put(dev_priv);
4362 }
4363
4364 /**
4365 * intel_irq_init - initializes irq support
4366 * @dev_priv: i915 device instance
4367 *
4368 * This function initializes all the irq support including work items, timers
4369 * and all the vtables. It does not setup the interrupt itself though.
4370 */
4371 void intel_irq_init(struct drm_i915_private *dev_priv)
4372 {
4373 struct drm_device *dev = dev_priv->dev;
4374
4375 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
4376 INIT_WORK(&dev_priv->dig_port_work, i915_digport_work_func);
4377 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
4378 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4379 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4380
4381 /* Let's track the enabled rps events */
4382 if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
4383 /* WaGsvRC0ResidencyMethod:vlv */
4384 dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
4385 else
4386 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4387
4388 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
4389 i915_hangcheck_elapsed,
4390 (unsigned long) dev);
4391 INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work,
4392 intel_hpd_irq_reenable_work);
4393
4394 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4395
4396 if (IS_GEN2(dev_priv)) {
4397 dev->max_vblank_count = 0;
4398 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4399 } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4400 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4401 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
4402 } else {
4403 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4404 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4405 }
4406
4407 /*
4408 * Opt out of the vblank disable timer on everything except gen2.
4409 * Gen2 doesn't have a hardware frame counter and so depends on
4410 * vblank interrupts to produce sane vblank seuquence numbers.
4411 */
4412 if (!IS_GEN2(dev_priv))
4413 dev->vblank_disable_immediate = true;
4414
4415 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
4416 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4417 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4418 }
4419
4420 if (IS_CHERRYVIEW(dev_priv)) {
4421 dev->driver->irq_handler = cherryview_irq_handler;
4422 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4423 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4424 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4425 dev->driver->enable_vblank = valleyview_enable_vblank;
4426 dev->driver->disable_vblank = valleyview_disable_vblank;
4427 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4428 } else if (IS_VALLEYVIEW(dev_priv)) {
4429 dev->driver->irq_handler = valleyview_irq_handler;
4430 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4431 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4432 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4433 dev->driver->enable_vblank = valleyview_enable_vblank;
4434 dev->driver->disable_vblank = valleyview_disable_vblank;
4435 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4436 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
4437 dev->driver->irq_handler = gen8_irq_handler;
4438 dev->driver->irq_preinstall = gen8_irq_reset;
4439 dev->driver->irq_postinstall = gen8_irq_postinstall;
4440 dev->driver->irq_uninstall = gen8_irq_uninstall;
4441 dev->driver->enable_vblank = gen8_enable_vblank;
4442 dev->driver->disable_vblank = gen8_disable_vblank;
4443 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4444 } else if (HAS_PCH_SPLIT(dev)) {
4445 dev->driver->irq_handler = ironlake_irq_handler;
4446 dev->driver->irq_preinstall = ironlake_irq_reset;
4447 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4448 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4449 dev->driver->enable_vblank = ironlake_enable_vblank;
4450 dev->driver->disable_vblank = ironlake_disable_vblank;
4451 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4452 } else {
4453 if (INTEL_INFO(dev_priv)->gen == 2) {
4454 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4455 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4456 dev->driver->irq_handler = i8xx_irq_handler;
4457 dev->driver->irq_uninstall = i8xx_irq_uninstall;
4458 } else if (INTEL_INFO(dev_priv)->gen == 3) {
4459 dev->driver->irq_preinstall = i915_irq_preinstall;
4460 dev->driver->irq_postinstall = i915_irq_postinstall;
4461 dev->driver->irq_uninstall = i915_irq_uninstall;
4462 dev->driver->irq_handler = i915_irq_handler;
4463 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4464 } else {
4465 dev->driver->irq_preinstall = i965_irq_preinstall;
4466 dev->driver->irq_postinstall = i965_irq_postinstall;
4467 dev->driver->irq_uninstall = i965_irq_uninstall;
4468 dev->driver->irq_handler = i965_irq_handler;
4469 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4470 }
4471 dev->driver->enable_vblank = i915_enable_vblank;
4472 dev->driver->disable_vblank = i915_disable_vblank;
4473 }
4474 }
4475
4476 /**
4477 * intel_hpd_init - initializes and enables hpd support
4478 * @dev_priv: i915 device instance
4479 *
4480 * This function enables the hotplug support. It requires that interrupts have
4481 * already been enabled with intel_irq_init_hw(). From this point on hotplug and
4482 * poll request can run concurrently to other code, so locking rules must be
4483 * obeyed.
4484 *
4485 * This is a separate step from interrupt enabling to simplify the locking rules
4486 * in the driver load and resume code.
4487 */
4488 void intel_hpd_init(struct drm_i915_private *dev_priv)
4489 {
4490 struct drm_device *dev = dev_priv->dev;
4491 struct drm_mode_config *mode_config = &dev->mode_config;
4492 struct drm_connector *connector;
4493 int i;
4494
4495 for (i = 1; i < HPD_NUM_PINS; i++) {
4496 dev_priv->hpd_stats[i].hpd_cnt = 0;
4497 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4498 }
4499 list_for_each_entry(connector, &mode_config->connector_list, head) {
4500 struct intel_connector *intel_connector = to_intel_connector(connector);
4501 connector->polled = intel_connector->polled;
4502 if (connector->encoder && !connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
4503 connector->polled = DRM_CONNECTOR_POLL_HPD;
4504 if (intel_connector->mst_port)
4505 connector->polled = DRM_CONNECTOR_POLL_HPD;
4506 }
4507
4508 /* Interrupt setup is already guaranteed to be single-threaded, this is
4509 * just to make the assert_spin_locked checks happy. */
4510 spin_lock_irq(&dev_priv->irq_lock);
4511 if (dev_priv->display.hpd_irq_setup)
4512 dev_priv->display.hpd_irq_setup(dev);
4513 spin_unlock_irq(&dev_priv->irq_lock);
4514 }
4515
4516 /**
4517 * intel_irq_install - enables the hardware interrupt
4518 * @dev_priv: i915 device instance
4519 *
4520 * This function enables the hardware interrupt handling, but leaves the hotplug
4521 * handling still disabled. It is called after intel_irq_init().
4522 *
4523 * In the driver load and resume code we need working interrupts in a few places
4524 * but don't want to deal with the hassle of concurrent probe and hotplug
4525 * workers. Hence the split into this two-stage approach.
4526 */
4527 int intel_irq_install(struct drm_i915_private *dev_priv)
4528 {
4529 /*
4530 * We enable some interrupt sources in our postinstall hooks, so mark
4531 * interrupts as enabled _before_ actually enabling them to avoid
4532 * special cases in our ordering checks.
4533 */
4534 dev_priv->pm.irqs_enabled = true;
4535
4536 return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
4537 }
4538
4539 /**
4540 * intel_irq_uninstall - finilizes all irq handling
4541 * @dev_priv: i915 device instance
4542 *
4543 * This stops interrupt and hotplug handling and unregisters and frees all
4544 * resources acquired in the init functions.
4545 */
4546 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4547 {
4548 drm_irq_uninstall(dev_priv->dev);
4549 intel_hpd_cancel_work(dev_priv);
4550 dev_priv->pm.irqs_enabled = false;
4551 }
4552
4553 /**
4554 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4555 * @dev_priv: i915 device instance
4556 *
4557 * This function is used to disable interrupts at runtime, both in the runtime
4558 * pm and the system suspend/resume code.
4559 */
4560 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4561 {
4562 dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
4563 dev_priv->pm.irqs_enabled = false;
4564 }
4565
4566 /**
4567 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4568 * @dev_priv: i915 device instance
4569 *
4570 * This function is used to enable interrupts at runtime, both in the runtime
4571 * pm and the system suspend/resume code.
4572 */
4573 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4574 {
4575 dev_priv->pm.irqs_enabled = true;
4576 dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
4577 dev_priv->dev->driver->irq_postinstall(dev_priv->dev);
4578 }
Linux kernel - Deliverables
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